1 #ifndef _DALI_INTERNAL_PLATFORM_ATOMICS_H_
2 #define _DALI_INTERNAL_PLATFORM_ATOMICS_H_
5 * Copyright (c) 2014 Samsung Electronics Co., Ltd.
7 * Licensed under the Apache License, Version 2.0 (the "License");
8 * you may not use this file except in compliance with the License.
9 * You may obtain a copy of the License at
11 * http://www.apache.org/licenses/LICENSE-2.0
13 * Unless required by applicable law or agreed to in writing, software
14 * distributed under the License is distributed on an "AS IS" BASIS,
15 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
16 * See the License for the specific language governing permissions and
17 * limitations under the License.
24 * Interface for atomic memory operations.
25 * There may be platform-specific versions of this file in other directories.
34 * @brief Atomic write to an aligned memory location in cacheable memory.
36 * For common platforms with coherent caches such as ARM mpcore and Intel CPUs,
37 * a cacheline can be in a writeable state in the L1 cache of exactly one core
38 * at a time. Therefore, a write to a location that does not require a read /
39 * modify / write cycle or cross a cacheline boundary is automatically
42 * @param address A pointer to a location in a cacheable memory region that is
43 * aligned to a 4 byte boundary.
44 * @param value A value to assign to the memory location in address.
46 inline void AtomicWriteToCacheableAlignedAddress( volatile uint32_t * const address, const uint32_t value )
48 DALI_ASSERT_DEBUG( ptrdiff_t(address) % 4 == 0 && "Address must be 32 bit aligned" );
53 * @brief Atomic read from an aligned memory location in cacheable memory.
55 * For common platforms with coherent caches such as ARM mpcore and Intel CPUs,
56 * a cacheline can be in a writeable state in the L1 cache of exactly one core
57 * at a time. Therefore, a read a location that does not cross a cacheline
58 * boundary is automatically atomic.
60 * @param address A pointer to a location in a cacheable memory region that is
61 * aligned to a 4 byte boundary.
62 * @return The value stored at the memory location in address.
64 inline uint32_t AtomicReadFromCacheableAlignedAddress( const volatile uint32_t * const address )
66 DALI_ASSERT_DEBUG( ptrdiff_t(address) % 4 == 0 && "Address must be 32 bit aligned" );
70 } /* namespace Internal */
71 } /* namespace Dali */
73 #endif /* _DALI_INTERNAL_PLATFORM_ATOMICS_H_ */