3 * MIPS Technologies, Inc., California.
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 * 3. Neither the name of the MIPS Technologies, Inc., nor the names of its
14 * contributors may be used to endorse or promote products derived from
15 * this software without specific prior written permission.
17 * THIS SOFTWARE IS PROVIDED BY THE MIPS TECHNOLOGIES, INC. ``AS IS'' AND
18 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
20 * ARE DISCLAIMED. IN NO EVENT SHALL THE MIPS TECHNOLOGIES, INC. BE LIABLE
21 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
22 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
23 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
24 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
25 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
29 * Author: Nemanja Lukic (nlukic@mips.com)
32 #include "pixman-mips-dspr2-asm.h"
34 LEAF_MIPS_DSPR2(pixman_fill_buff16_mips)
38 * a2 - value to fill buffer with
43 beqz t1, 0f /* check if address is 4-byte aligned */
49 srl t1, a1, 5 /* t1 how many multiples of 32 bytes */
50 replv.ph a2, a2 /* replicate fill value (16bit) in a2 */
88 END(pixman_fill_buff16_mips)
90 LEAF_MIPS32R2(pixman_fill_buff32_mips)
94 * a2 - value to fill buffer with
99 srl t1, a1, 5 /* t1 how many multiples of 32 bytes */
137 END(pixman_fill_buff32_mips)
139 LEAF_MIPS_DSPR2(pixman_composite_src_8888_0565_asm_mips)
142 * a1 - src (a8r8g8b8)
160 CONVERT_2x8888_TO_2x0565 t0, t1, t2, t3, t4, t5, t6, t7, t8
173 CONVERT_1x8888_TO_1x0565 t0, t1, t2, t3
180 END(pixman_composite_src_8888_0565_asm_mips)
182 LEAF_MIPS_DSPR2(pixman_composite_src_0565_8888_asm_mips)
184 * a0 - dst (a8r8g8b8)
202 CONVERT_2x0565_TO_2x8888 t0, t1, t2, t3, t4, t5, t6, t7, t8, t9
215 CONVERT_1x0565_TO_1x8888 t0, t1, t2, t3
222 END(pixman_composite_src_0565_8888_asm_mips)
224 LEAF_MIPS_DSPR2(pixman_composite_src_x888_8888_asm_mips)
226 * a0 - dst (a8r8g8b8)
227 * a1 - src (x8r8g8b8)
234 srl t8, a2, 3 /* t1 = how many multiples of 8 src pixels */
235 beqz t8, 3f /* branch if less than 8 src pixels */
310 END(pixman_composite_src_x888_8888_asm_mips)
312 LEAF_MIPS_DSPR2(pixman_composite_over_n_8888_8888_ca_asm_mips)
314 * a0 - dst (a8r8g8b8)
315 * a1 - src (32bit constant)
316 * a2 - mask (a8r8g8b8)
320 SAVE_REGS_ON_STACK 16, s0, s1, s2, s3, s4, s5, s6, s7
324 addiu t7, zero, -1 /* t7 = 0xffffffff */
325 srl t8, a1, 24 /* t8 = srca */
328 beqz t1, 3f /* last pixel */
330 beq t8, t6, 2f /* if (srca == 0xff) */
334 lw t0, 0(a2) /* t0 = mask */
335 lw t1, 4(a2) /* t1 = mask */
337 beqz t2, 12f /* if (t0 == 0) && (t1 == 0) */
340 move s0, t8 /* s0 = srca */
341 move s1, t8 /* s1 = srca */
342 move t4, a1 /* t4 = src */
343 move t5, a1 /* t5 = src */
344 lw t2, 0(a0) /* t2 = dst */
345 beq t3, t7, 11f /* if (t0 == 0xffffffff) && (t1 == 0xffffffff) */
346 lw t3, 4(a0) /* t0 = dst */
347 MIPS_2xUN8x4_MUL_2xUN8x4 a1, a1, t0, t1, t4, t5, t9, s0, s1, s2, s3, s4, s5
348 MIPS_2xUN8x4_MUL_2xUN8 t0, t1, t8, t8, s0, s1, t9, s2, s3, s4, s5, s6, s7
352 MIPS_2xUN8x4_MUL_2xUN8x4 t2, t3, s0, s1, s2, s3, t9, t0, t1, s4, s5, s6, s7
366 lw t0, 0(a2) /* t0 = mask */
367 lw t1, 4(a2) /* t1 = mask */
369 beqz t2, 22f /* if (t0 == 0) & (t1 == 0) */
373 beq t2, t7, 21f /* if (t0 == 0xffffffff) && (t1 == 0xffffffff) */
375 lw t2, 0(a0) /* t2 = dst */
376 lw t3, 4(a0) /* t3 = dst */
377 MIPS_2xUN8x4_MUL_2xUN8x4 a1, a1, t0, t1, t4, t5, t9, s0, s1, s2, s3, s4, s5
380 MIPS_2xUN8x4_MUL_2xUN8x4 t2, t3, t0, t1, s0, s1, t9, s2, s3, s4, s5, s6, s7
395 lw t1, 0(a2) /* t1 = mask */
398 move s0, t8 /* s0 = srca */
399 move t2, a1 /* t2 = src */
401 lw t0, 0(a0) /* t0 = dst */
403 MIPS_UN8x4_MUL_UN8x4 a1, t1, t2, t9, t3, t4, t5, t6
404 MIPS_UN8x4_MUL_UN8 t1, t8, s0, t9, t3, t4, t5
407 MIPS_UN8x4_MUL_UN8x4 t0, s0, t3, t9, t4, t5, t6, t1
411 RESTORE_REGS_FROM_STACK 16, s0, s1, s2, s3, s4, s5, s6, s7
415 END(pixman_composite_over_n_8888_8888_ca_asm_mips)
417 LEAF_MIPS_DSPR2(pixman_composite_over_n_8888_0565_ca_asm_mips)
420 * a1 - src (32bit constant)
421 * a2 - mask (a8r8g8b8)
425 SAVE_REGS_ON_STACK 20, s0, s1, s2, s3, s4, s5, s6, s7, s8
433 srl t8, a1, 24 /* t8 = srca */
435 beqz t1, 3f /* last pixel */
437 li s0, 0xff /* s0 = 0xff */
438 addiu s1, zero, -1 /* s1 = 0xffffffff */
440 beq t8, s0, 2f /* if (srca == 0xff) */
444 lw t0, 0(a2) /* t0 = mask */
445 lw t1, 4(a2) /* t1 = mask */
447 beqz t2, 12f /* if (t0 == 0) && (t1 == 0) */
452 lhu t2, 0(a0) /* t2 = dst */
453 beq t3, s1, 11f /* if (t0 == 0xffffffff) && (t1 == 0xffffffff) */
454 lhu t3, 2(a0) /* t3 = dst */
455 MIPS_2xUN8x4_MUL_2xUN8x4 a1, a1, t0, t1, s2, s3, t9, t4, s4, s5, s6, s7, s8
456 MIPS_2xUN8x4_MUL_2xUN8 t0, t1, t8, t8, t0, t1, t9, t4, s4, s5, s6, s7, s8
460 CONVERT_2x0565_TO_2x8888 t2, t3, s4, s5, t6, t7, t4, s6, s7, s8
461 MIPS_2xUN8x4_MUL_2xUN8x4 s4, s5, t0, t1, s4, s5, t9, t4, s6, s7, s8, t0, t1
464 CONVERT_2x8888_TO_2x0565 s2, s3, t2, t3, t5, t6, t7, s1, s2
476 lw t0, 0(a2) /* t0 = mask */
477 lw t1, 4(a2) /* t1 = mask */
479 beqz t2, 22f /* if (t0 == 0) & (t1 == 0) */
483 beq t3, s1, 21f /* if (t0 == 0xffffffff) && (t1 == 0xffffffff) */
485 lhu t2, 0(a0) /* t2 = dst */
486 lhu t3, 2(a0) /* t3 = dst */
487 MIPS_2xUN8x4_MUL_2xUN8x4 a1, a1, t0, t1, s2, s3, t9, t4, s4, s5, s6, s7, s8
490 CONVERT_2x0565_TO_2x8888 t2, t3, s4, s5, t6, t7, t4, s6, s7, s8
491 MIPS_2xUN8x4_MUL_2xUN8x4 s4, s5, t0, t1, s4, s5, t9, t4, s6, s7, s8, t2, t3
495 CONVERT_2x8888_TO_2x0565 t2, t3, t0, t1, t5, t6, t7, s2, s3
507 lw t1, 0(a2) /* t1 = mask */
510 move s0, t8 /* s0 = srca */
511 move t2, a1 /* t2 = src */
513 lhu t0, 0(a0) /* t0 = dst */
515 MIPS_UN8x4_MUL_UN8x4 a1, t1, t2, t9, t3, t4, t5, t6
516 MIPS_UN8x4_MUL_UN8 t1, t8, s0, t9, t3, t4, t5
519 CONVERT_1x0565_TO_1x8888 t0, s1, s2, s3
520 MIPS_UN8x4_MUL_UN8x4 s1, s0, t3, t9, t4, t5, t6, t1
522 CONVERT_1x8888_TO_1x0565 t0, s1, s2, s3
525 RESTORE_REGS_FROM_STACK 20, s0, s1, s2, s3, s4, s5, s6, s7, s8
529 END(pixman_composite_over_n_8888_0565_ca_asm_mips)