1 /* ------------------------------------------------------------------
2 * Copyright (C) 1998-2010 PacketVideo
4 * Licensed under the Apache License, Version 2.0 (the "License");
5 * you may not use this file except in compliance with the License.
6 * You may obtain a copy of the License at
8 * http://www.apache.org/licenses/LICENSE-2.0
10 * Unless required by applicable law or agreed to in writing, software
11 * distributed under the License is distributed on an "AS IS" BASIS,
12 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either
14 * See the License for the specific language governing permissions
15 * and limitations under the License.
16 * -------------------------------------------------------------------
18 /****************************************************************************************
19 Portions of this file are derived from the following 3GPP standard:
22 ANSI-C code for the Adaptive Multi-Rate - Wideband (AMR-WB) speech codec
23 Available from http://www.3gpp.org
25 (C) 2007, 3GPP Organizational Partners (ARIB, ATIS, CCSA, ETSI, TTA, TTC)
26 Permission to distribute, modify and use this file under the standard license
27 terms listed above has been obtained from the copyright holder.
28 ****************************************************************************************/
30 ------------------------------------------------------------------------------
34 Pathname: ./src/pvamrwbdecoder_basic_op_gcc_armv5.h
36 ------------------------------------------------------------------------------
39 ------------------------------------------------------------------------------
42 #ifndef PVAMRWBDECODER_BASIC_OP_GCC_ARMV5_H
43 #define PVAMRWBDECODER_BASIC_OP_GCC_ARMV5_H
52 static inline int16 sub_int16(int16 var1, int16 var2)
54 register int32 L_var_out;
55 register int32 L_var_aux;
56 register int32 ra = (int32)var1;
57 register int32 rb = (int32)var2;
60 "mov %0, %2, lsl #16\n"
61 "mov %1, %3, lsl #16\n"
69 return (int16)L_var_out;
73 static inline int16 add_int16(int16 var1, int16 var2)
75 register int32 L_var_out;
76 register int32 L_var_aux;
77 register int32 ra = (int32)var1;
78 register int32 rb = (int32)var2;
81 "mov %0, %2, lsl #16\n"
82 "mov %1, %3, lsl #16\n"
90 return (int16)L_var_out;
94 static inline int32 mul_32by16(int16 hi, int16 lo, int16 n)
98 register int32 ra = (int32)hi;
99 register int32 rb = (int32)lo;
100 register int32 rc = (int32)n;
104 "smulbb %0, %2, %4\n"
105 "smulbb %1, %3, %4\n"
106 "add %0, %0, %1, asr #15\n"
118 static inline int32 sub_int32(int32 L_var1, int32 L_var2)
120 register int32 L_var_out;
121 register int32 ra = L_var1;
122 register int32 rb = L_var2;
133 static inline int32 add_int32(int32 L_var1, int32 L_var2)
135 register int32 L_var_out;
136 register int32 ra = L_var1;
137 register int32 rb = L_var2;
148 static inline int32 msu_16by16_from_int32(int32 L_var3, int16 var1, int16 var2)
150 register int32 L_var_out;
151 register int32 ra = (int32)var1;
152 register int32 rb = (int32)var2;
153 register int32 rc = L_var3;
156 "smulbb %0, %1, %2\n"
167 static inline int32 mac_16by16_to_int32(int32 L_var3, int16 var1, int16 var2)
169 register int32 L_var_out;
170 register int32 ra = (int32)var1;
171 register int32 rb = (int32)var2;
172 register int32 rc = L_var3;
175 "smulbb %0, %1, %2\n"
186 static inline int32 mul_16by16_to_int32(int16 var1, int16 var2)
188 register int32 L_var_out;
189 register int32 ra = (int32)var1;
190 register int32 rb = (int32)var2;
193 "smulbb %0, %1, %2\n"
203 static inline int16 mult_int16(int16 var1, int16 var2)
205 register int32 L_var_out;
206 register int32 ra = (int32)var1;
207 register int32 rb = (int32)var2;
210 "smulbb %0, %1, %2\n"
211 "mov %0, %0, asr #15"
216 return (int16)L_var_out;
219 static inline int16 amr_wb_round(int32 L_var1)
221 register int32 L_var_out;
222 register int32 ra = (int32)L_var1;
223 register int32 rb = (int32)0x00008000L;
227 "mov %0, %0, asr #16"
231 return (int16)L_var_out;
234 static inline int16 amr_wb_shl1_round(int32 L_var1)
236 register int32 L_var_out;
237 register int32 ra = (int32)L_var1;
238 register int32 rb = (int32)0x00008000L;
243 "mov %0, %0, asr #16"
247 return (int16)L_var_out;
251 static inline int32 fxp_mac_16by16(const int16 L_var1, const int16 L_var2, int32 L_add)
254 register int32 ra = (int32)L_var1;
255 register int32 rb = (int32)L_var2;
256 register int32 rc = (int32)L_add;
259 "smlabb %0, %1, %2, %3"
267 static inline int32 fxp_mul_16by16bb(int16 L_var1, const int16 L_var2)
270 register int32 ra = (int32)L_var1;
271 register int32 rb = (int32)L_var2;
282 #define fxp_mul_16by16(a, b) fxp_mul_16by16bb( a, b)
285 static inline int32 fxp_mul32_by_16(int32 L_var1, const int32 L_var2)
288 register int32 ra = (int32)L_var1;
289 register int32 rb = (int32)L_var2;
299 #define fxp_mul32_by_16b( a, b) fxp_mul32_by_16( a, b)
310 #endif /* PVAMRWBDECODER_BASIC_OP_GCC_ARMV5_H */