1 /* Assemble V850 instructions.
2 Copyright (C) 1996 Free Software Foundation, Inc.
4 This program is free software; you can redistribute it and/or modify
5 it under the terms of the GNU General Public License as published by
6 the Free Software Foundation; either version 2 of the License, or
7 (at your option) any later version.
9 This program is distributed in the hope that it will be useful,
10 but WITHOUT ANY WARRANTY; without even the implied warranty of
11 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 GNU General Public License for more details.
14 You should have received a copy of the GNU General Public License
15 along with this program; if not, write to the Free Software
16 Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */
19 #include "opcode/v850.h"
23 #define OP(x) ((x & 0x3f) << 5)
24 #define OP_MASK OP (0x3f)
26 /* conditional branch opcode */
27 #define BOP(x) ((0x0b << 7) | (x & 0x0f))
28 #define BOP_MASK ((0x0f << 7) | 0x0f)
30 /* one-word opcodes */
31 #define one(x) ((unsigned int) (x))
33 /* two-word opcodes */
34 #define two(x,y) ((unsigned int) (x) | ((unsigned int) (y) << 16))
38 /* The functions used to insert and extract complicated operands. */
41 insert_d9 (insn, value, errmsg)
46 if (value > 0xff || value < -0x100)
47 *errmsg = "branch value out of range";
50 *errmsg = "branch to odd offset";
52 return (insn | ((value & 0x1f0) << 7) | ((value & 0x0e) << 3));
56 extract_d9 (insn, invalid)
60 unsigned long ret = ((insn & 0xf800) >> 7) | ((insn & 0x0070) >> 3);
62 if ((insn & 0x8000) != 0)
69 insert_d22 (insn, value, errmsg)
74 if (value > 0x1fffff || value < -0x200000)
75 *errmsg = "branch value out of range";
78 *errmsg = "branch to odd offset";
80 return (insn | ((value & 0xfffe) << 16) | ((value & 0x3f0000) >> 16));
84 extract_d22 (insn, invalid)
88 unsigned long ret = ((insn & 0xfffe0000) >> 16) | ((insn & 0x3f) << 16);
90 return ((ret << 10) >> 10);
94 insert_d16_15 (insn, value, errmsg)
99 if (value > 0x7fff || value < -0x8000)
100 *errmsg = "value out of range";
102 if ((value % 2) != 0)
103 *errmsg = "load/store half/word at odd offset";
105 return insn | ((value & 0xfffe) << 16);
109 extract_d16_15 (insn, invalid)
113 signed long ret = (insn & 0xfffe0000);
119 insert_d8_7 (insn, value, errmsg)
124 if (value > 0xff || value < 0)
125 *errmsg = "short load/store half value out of range";
127 if ((value % 2) != 0)
128 *errmsg = "short load/store half at odd offset";
132 return (insn | (value & 0x7f));
136 extract_d8_7 (insn, invalid)
140 unsigned long ret = (insn & 0x7f);
146 insert_d8_6 (insn, value, errmsg)
151 if (value > 0xff || value < 0)
152 *errmsg = "short load/store word value out of range";
154 if ((value % 4) != 0)
155 *errmsg = "short load/store word at odd offset";
159 return (insn | (value & 0x7e));
163 extract_d8_6 (insn, invalid)
167 unsigned long ret = (insn & 0x7e);
172 /* start-sanitize-v850e */
175 insert_d5_4 (insn, value, errmsg)
178 const char ** errmsg;
180 if (value > 0x1f || value < 0)
181 *errmsg = "unsigned short load half value out of range";
184 *errmsg = "unsigned short load half at odd offset";
188 return (insn | (value & 0x0f));
192 extract_d5_4 (insn, invalid)
196 unsigned long ret = (insn & 0x0f);
202 insert_d16_16 (insn, value, errmsg)
205 const char ** errmsg;
207 if (value > 0x7fff || value < -0x8000)
208 *errmsg = "value out of range";
210 return (insn | ((value & 0xfffe) << 16) | ((value & 1) << 5));
214 extract_d16_16 (insn, invalid)
218 signed long ret = insn & 0xfffe0000;
222 ret |= ((insn & 0x20) >> 5);
228 insert_i9 (insn, value, errmsg)
231 const char ** errmsg;
233 if (value > 0xff || value < -0x100)
234 *errmsg = "value out of range";
236 return insn | ((value & 0x1e0) << 13) | (value & 0x1f);
240 extract_i9 (insn, invalid)
244 signed long ret = insn & 0x003c0000;
249 ret |= (insn & 0x1f);
255 insert_u9 (insn, value, errmsg)
258 const char ** errmsg;
261 *errmsg = "value out of range";
263 return insn | ((value & 0x1e0) << 13) | (value & 0x1f);
267 extract_u9 (insn, invalid)
271 unsigned long ret = insn & 0x003c0000;
275 ret |= (insn & 0x1f);
280 /* start-sanitize-v850e */
282 insert_spe (insn, value, errmsg)
285 const char ** errmsg;
288 *errmsg = "invalid register for stack adjustment";
290 return insn & (~ 0x180000);
294 extract_spe (insn, invalid)
301 /* end-sanitize-v850e */
302 /* start-sanitize-v850eq */
305 insert_i5div (insn, value, errmsg)
308 const char ** errmsg;
311 *errmsg = "value out of range";
314 *errmsg = "value must be even";
318 return insn | ((value & 0x1e) << 17);
322 extract_i5div (insn, invalid)
326 unsigned long ret = insn & 0x3c0000;
335 /* end-sanitize-v850eq */
338 /* Warning: code in gas/config/tc-v850.c examines the contents of this array.
339 If you change any of the values here, be sure to look for side effects in
341 const struct v850_operand v850_operands[] =
346 /* The R1 field in a format 1, 6, 7, or 9 insn. */
347 #define R1 (UNUSED+1)
348 { 5, 0, 0, 0, V850_OPERAND_REG },
350 /* As above, but register 0 is not allowed. */
351 #define R1_NOTR0 (R1 + 1)
352 { 5, 0, 0, 0, V850_OPERAND_REG | V850_NOT_R0 },
354 /* The R2 field in a format 1, 2, 4, 5, 6, 7, 9 insn. */
355 #define R2 (R1_NOTR0 + 1)
356 { 5, 11, 0, 0, V850_OPERAND_REG },
358 /* As above, but register 0 is not allowed. */
359 #define R2_NOTR0 (R2 + 1)
360 { 5, 11, 0, 0, V850_OPERAND_REG | V850_NOT_R0 },
362 /* The imm5 field in a format 2 insn. */
363 #define I5 (R2_NOTR0 + 1)
364 { 5, 0, 0, 0, V850_OPERAND_SIGNED },
366 /* The unsigned imm5 field in a format 2 insn. */
370 /* The imm16 field in a format 6 insn. */
371 #define I16 (I5U + 1)
372 { 16, 16, 0, 0, V850_OPERAND_SIGNED },
374 /* The signed disp7 field in a format 4 insn. */
378 /* The disp16 field in a format 6 insn. */
379 #define D16_15 (D7 + 1)
380 { 15, 17, insert_d16_15, extract_d16_15, V850_OPERAND_SIGNED },
382 /* The 3 bit immediate field in format 8 insn. */
383 #define B3 (D16_15 + 1)
386 /* The 4 bit condition code in a setf instruction */
387 #define CCCC (B3 + 1)
388 { 4, 0, 0, 0, V850_OPERAND_CC },
390 /* The unsigned DISP8 field in a format 4 insn. */
391 #define D8_7 (CCCC + 1)
392 { 7, 0, insert_d8_7, extract_d8_7, 0 },
394 /* The unsigned DISP8 field in a format 4 insn. */
395 #define D8_6 (D8_7 + 1)
396 { 6, 1, insert_d8_6, extract_d8_6, 0 },
398 /* System register operands. */
399 #define SR1 (D8_6 + 1)
400 { 5, 0, 0, 0, V850_OPERAND_SRG },
404 { 0, 0, 0, 0, V850_OPERAND_EP },
406 /* The imm16 field (unsigned) in a format 6 insn. */
407 #define I16U (EP + 1)
410 /* The R2 field as a system register. */
411 #define SR2 (I16U + 1)
412 { 5, 11, 0, 0, V850_OPERAND_SRG },
414 /* The disp16 field in a format 8 insn. */
415 #define D16 (SR2 + 1)
416 { 16, 16, 0, 0, V850_OPERAND_SIGNED },
418 /* The DISP22 field in a format 4 insn, relaxable. */
419 #define D9_RELAX (D16 + 1)
420 { 9, 0, insert_d9, extract_d9, V850_OPERAND_RELAX | V850_OPERAND_SIGNED | V850_OPERAND_DISP },
422 /* The DISP22 field in a format 4 insn.
424 This _must_ follow D9_RELAX; the assembler assumes that the longer
425 version immediately follows the shorter version for relaxing. */
426 #define D22 (D9_RELAX + 1)
427 { 22, 0, insert_d22, extract_d22, V850_OPERAND_SIGNED | V850_OPERAND_DISP },
429 /* start-sanitize-v850e */
431 /* The signed disp4 field in a format 4 insn. */
435 /* The unsigned disp5 field in a format 4 insn. */
436 #define D5_4 (D4 + 1)
437 { 4, 0, insert_d5_4, extract_d5_4, 0 },
439 /* The disp16 field in an format 7 unsigned byte load insn. */
440 #define D16_16 (D5_4 + 1)
441 { -1, 0xfffe0020, insert_d16_16, extract_d16_16, 0 },
443 /* Third register in conditional moves. */
444 #define R3 (D16_16 + 1)
445 { 5, 27, 0, 0, V850_OPERAND_REG },
447 /* Condition code in conditional moves. */
448 #define MOVCC (R3 + 1)
449 { 4, 17, 0, 0, V850_OPERAND_CC },
451 /* The imm9 field in a multiply word. */
452 #define I9 (MOVCC + 1)
453 { 9, 0, insert_i9, extract_i9, V850_OPERAND_SIGNED },
455 /* The unsigned imm9 field in a multiply word. */
457 { 9, 0, insert_u9, extract_u9, 0 },
459 /* A list of registers in a prepare/dispose instruction. */
460 #define LIST12 (U9 + 1)
461 { -1, 0xffe00001, 0, 0, V850E_PUSH_POP },
463 /* The IMM6 field in a call instruction. */
464 #define I6 (LIST12 + 1)
467 /* The 16 bit immediate following a 32 bit instruction. */
468 #define IMM16 (I6 + 1)
469 { 16, 16, 0, 0, V850_OPERAND_SIGNED | V850E_IMMEDIATE16 },
471 /* The 32 bit immediate following a 32 bit instruction. */
472 #define IMM32 (IMM16 + 1)
473 { 0, 0, 0, 0, V850E_IMMEDIATE32 },
475 /* The imm5 field in a push/pop instruction. */
476 #define IMM5 (IMM32 + 1)
479 /* Reg2 in dispose instruction. */
480 #define R2DISPOSE (IMM5 + 1)
481 { 5, 16, 0, 0, V850_OPERAND_REG | V850_NOT_R0 },
483 /* Stack pointer in prepare instruction. */
484 #define SP (R2DISPOSE + 1)
485 { 2, 19, insert_spe, extract_spe, V850_OPERAND_REG },
487 /* end-sanitize-v850e */
488 /* start-sanitize-v850eq */
490 /* The IMM5 field in a divide N step instruction. */
491 #define I5DIV (SP + 1)
492 { 9, 0, insert_i5div, extract_i5div, V850_OPERAND_SIGNED },
494 /* The list of registers in a PUSHMH/POPMH instruction. */
495 #define LIST18_H (I5DIV + 1)
496 { -1, 0xfff8000f, 0, 0, V850E_PUSH_POP },
498 /* The list of registers in a PUSHML/POPML instruction. */
499 #define LIST18_L (LIST18_H + 1)
500 { -1, 0xfff8001f, 0, 0, V850E_PUSH_POP }, /* The setting of the 4th bit is a flag to disassmble() in v850-dis.c */
502 /* end-sanitize-v850eq */
506 /* reg-reg instruction format (Format I) */
509 /* imm-reg instruction format (Format II) */
512 /* conditional branch instruction format (Format III) */
513 #define IF3 {D9_RELAX}
515 /* 3 operand instruction (Format VI) */
516 #define IF6 {I16, R1, R2}
518 /* 3 operand instruction (Format VI) */
519 #define IF6U {I16U, R1, R2}
525 The format of the opcode table is:
527 NAME OPCODE MASK { OPERANDS } MEMOP
529 NAME is the name of the instruction.
530 OPCODE is the instruction opcode.
531 MASK is the opcode mask; this is used to tell the disassembler
532 which bits in the actual opcode must match OPCODE.
533 OPERANDS is the list of operands.
534 MEMOP specifies which operand (if any) is a memory operand.
536 The disassembler reads the table in order and prints the first
537 instruction which matches, so this table is sorted to put more
538 specific instructions before more general instructions. It is also
539 sorted by major opcode. */
541 const struct v850_opcode v850_opcodes[] =
543 { "breakpoint", 0xffff, 0xffff, {UNUSED}, 0 },
545 { "jmp", one (0x0060), one (0xffe0), {R1}, 1 },
547 /* load/store instructions */
548 /* start-sanitize-v850eq */
550 { "sld.bu", one (0x0300), one (0x0780), {D7, EP, R2_NOTR0}, 1 },
551 { "sld.hu", one (0x0400), one (0x0780), {D8_7, EP, R2_NOTR0}, 1 },
552 { "sld.b", one (0x0060), one (0x07f0), {D4, EP, R2}, 1 },
553 { "sld.h", one (0x0070), one (0x07f0), {D5_4, EP, R2}, 1 },
555 /* end-sanitize-v850eq */
556 { "sld.b", one (0x0300), one (0x0780), {D7, EP, R2}, 1 },
557 { "sld.h", one (0x0400), one (0x0780), {D8_7, EP, R2}, 1 },
558 /* start-sanitize-v850e */
559 { "sld.bu", one (0x0060), one (0x07f0), {D4, EP, R2_NOTR0}, 1 },
560 { "sld.hu", one (0x0070), one (0x07f0), {D5_4, EP, R2_NOTR0}, 1 },
561 /* end-sanitize-v850e */
562 /* start-sanitize-v850eq */
564 /* end-sanitize-v850eq */
565 { "sld.w", one (0x0500), one (0x0781), {D8_6, EP, R2}, 1 },
566 { "sst.b", one (0x0380), one (0x0780), {R2, D7, EP}, 2 },
567 { "sst.h", one (0x0480), one (0x0780), {R2, D8_7, EP}, 2 },
568 { "sst.w", one (0x0501), one (0x0781), {R2, D8_6, EP}, 2 },
570 /* start-sanitize-v850eq */
571 { "pushml", two (0x07e0, 0x0001), two (0xfff0, 0x0007), {LIST18_L}, 0 },
572 { "pushmh", two (0x07e0, 0x0003), two (0xfff0, 0x0007), {LIST18_H}, 0 },
573 { "popml", two (0x07f0, 0x0001), two (0xfff0, 0x0007), {LIST18_L}, 0 },
574 { "popmh", two (0x07f0, 0x0003), two (0xfff0, 0x0007), {LIST18_H}, 0 },
575 /* end-sanitize-v850eq */
577 /* start-sanitize-v850e */
578 { "prepare", two (0x0780, 0x0003), two (0xffc0, 0x001f), {LIST12, IMM5, SP}, 0 },
579 { "prepare", two (0x0780, 0x000b), two (0xffc0, 0x001f), {LIST12, IMM5, IMM16}, 0 },
580 { "prepare", two (0x0780, 0x0013), two (0xffc0, 0x001f), {LIST12, IMM5, IMM16}, 0 },
581 { "prepare", two (0x0780, 0x001b), two (0xffc0, 0x001f), {LIST12, IMM5, IMM32}, 0 },
582 { "prepare", two (0x0780, 0x0001), two (0xffc0, 0x001f), {LIST12, IMM5}, 0 },
583 { "dispose", one (0x0640), one (0xffc0), {IMM5, LIST12, R2DISPOSE},0 },
584 { "dispose", two (0x0640, 0x0000), two (0xffc0, 0x001f), {IMM5, LIST12}, 0 },
585 /* end-sanitize-v850e */
587 { "ld.b", two (0x0700, 0x0000), two (0x07e0, 0x0000), {D16, R1, R2}, 1 },
588 { "ld.h", two (0x0720, 0x0000), two (0x07e0, 0x0001), {D16_15, R1, R2}, 1 },
589 { "ld.w", two (0x0720, 0x0001), two (0x07e0, 0x0001), {D16_15, R1, R2}, 1 },
590 /* start-sanitize-v850e */
591 { "ld.bu", two (0x0780, 0x0001), two (0x07c0, 0x0001), {D16_16, R1, R2_NOTR0}, 1 },
592 { "ld.hu", two (0x07e0, 0x0001), two (0x07e0, 0x0001), {D16_15, R1, R2_NOTR0}, 1 },
593 /* end-sanitize-v850e */
594 { "st.b", two (0x0740, 0x0000), two (0x07e0, 0x0000), {R2, D16, R1}, 2 },
595 { "st.h", two (0x0760, 0x0000), two (0x07e0, 0x0001), {R2, D16_15, R1}, 2 },
596 { "st.w", two (0x0760, 0x0001), two (0x07e0, 0x0001), {R2, D16_15, R1}, 2 },
598 /* start-sanitize-v850e */
599 /* byte swap/extend instructions */
600 { "zxb", one (0x0080), one (0xffe0), {R1_NOTR0}, 0 },
601 { "zxh", one (0x00c0), one (0xffe0), {R1_NOTR0}, 0 },
602 { "sxb", one (0x00a0), one (0xffe0), {R1_NOTR0}, 0 },
603 { "sxh", one (0x00e0), one (0xffe0), {R1_NOTR0}, 0 },
604 { "bsh", two (0x07e0, 0x0342), two (0x07ff, 0x07ff), {R2, R3}, 0 },
605 { "bsw", two (0x07e0, 0x0340), two (0x07ff, 0x07ff), {R2, R3}, 0 },
606 { "hsw", two (0x07e0, 0x0344), two (0x07ff, 0x07ff), {R2, R3}, 0 },
608 /* jump table instructions */
609 { "switch", one (0x0040), one (0xffe0), {R1}, 1 },
610 { "callt", one (0x0200), one (0xffc0), {I6}, 0 },
611 { "ctret", two (0x07e0, 0x0144), two (0xffff, 0xffff), {0}, 0 },
612 /* end-sanitize-v850e */
614 /* arithmetic operation instructions */
615 { "setf", two (0x07e0, 0x0000), two (0x07f0, 0xffff), {CCCC, R2}, 0 },
616 /* start-sanitize-v850e */
617 { "cmov", two (0x07e0, 0x0320), two (0x07e0, 0x07e1), {MOVCC, R2, R1, R3}, 0 },
618 { "cmov", two (0x07e0, 0x0300), two (0x07e0, 0x07e1), {MOVCC, I5, R2, R3}, 0 },
619 /* end-sanitize-v850e */
620 /* start-sanitize-v850e */
621 { "mul", two (0x07e0, 0x0220), two (0x07e0, 0x07ff), {R1, R2, R3}, 0 },
622 { "mul", two (0x07e0, 0x0240), two (0x07e0, 0x07c3), {I9, R2, R3}, 0 },
623 { "mulu", two (0x07e0, 0x0222), two (0x07e0, 0x07ff), {R1, R2, R3}, 0 },
624 { "mulu", two (0x07e0, 0x0242), two (0x07e0, 0x07c3), {U9, R2, R3}, 0 },
625 /* end-sanitize-v850e */
626 /* start-sanitize-v850e */
628 { "div", two (0x07e0, 0x02c0), two (0x07e0, 0x07ff), {R1, R2, R3}, 0 },
629 { "divu", two (0x07e0, 0x02c2), two (0x07e0, 0x07ff), {R1, R2, R3}, 0 },
630 { "divhu", two (0x07e0, 0x0282), two (0x07e0, 0x07ff), {R1, R2, R3}, 0 },
631 { "divh", two (0x07e0, 0x0280), two (0x07e0, 0x07ff), {R1, R2, R3}, 0 },
632 /* end-sanitize-v850e */
633 { "divh", OP (0x02), OP_MASK, {R1, R2_NOTR0}, 0 },
635 /* start-sanitize-v850eq */
636 { "divhn", two (0x07e0, 0x0280), two (0x07e0, 0x07c3), {I5DIV, R1, R2, R3}, 0 },
637 { "divhun", two (0x07e0, 0x0282), two (0x07e0, 0x07c3), {I5DIV, R1, R2, R3}, 0 },
638 { "divn", two (0x07e0, 0x02c0), two (0x07e0, 0x07c3), {I5DIV, R1, R2, R3}, 0 },
639 { "divun", two (0x07e0, 0x02c2), two (0x07e0, 0x07c3), {I5DIV, R1, R2, R3}, 0 },
640 { "sdivhn", two (0x07e0, 0x0180), two (0x07e0, 0x07c3), {I5DIV, R1, R2, R3}, 0 },
641 { "sdivhun", two (0x07e0, 0x0182), two (0x07e0, 0x07c3), {I5DIV, R1, R2, R3}, 0 },
642 { "sdivn", two (0x07e0, 0x01c0), two (0x07e0, 0x07c3), {I5DIV, R1, R2, R3}, 0 },
643 { "sdivun", two (0x07e0, 0x01c2), two (0x07e0, 0x07c3), {I5DIV, R1, R2, R3}, 0 },
644 /* end-sanitize-v850eq */
646 { "nop", one (0x00), one (0xffff), {0}, 0 },
647 { "mov", OP (0x10), OP_MASK, {I5, R2_NOTR0}, 0 },
648 /* start-sanitize-v850e */
649 { "mov", one (0x0620), one (0xffe0), {IMM32, R1_NOTR0}, 0 },
650 /* end-sanitize-v850e */
651 { "mov", OP (0x00), OP_MASK, {R1, R2_NOTR0}, 0 },
652 { "movea", OP (0x31), OP_MASK, {I16, R1, R2_NOTR0}, 0 },
653 { "movhi", OP (0x32), OP_MASK, {I16U, R1, R2_NOTR0}, 0 },
654 { "add", OP (0x0e), OP_MASK, IF1, 0 },
655 { "add", OP (0x12), OP_MASK, IF2, 0 },
656 { "addi", OP (0x30), OP_MASK, IF6, 0 },
657 { "sub", OP (0x0d), OP_MASK, IF1, 0 },
658 { "subr", OP (0x0c), OP_MASK, IF1, 0 },
659 { "mulh", OP (0x17), OP_MASK, {I5, R2_NOTR0}, 0 },
660 { "mulh", OP (0x07), OP_MASK, {R1, R2_NOTR0}, 0 },
661 { "mulhi", OP (0x37), OP_MASK, {I16, R1, R2_NOTR0}, 0 },
662 { "cmp", OP (0x0f), OP_MASK, IF1, 0 },
663 { "cmp", OP (0x13), OP_MASK, IF2, 0 },
665 /* saturated operation instructions */
666 { "satadd", OP (0x11), OP_MASK, {I5, R2_NOTR0}, 0 },
667 { "satadd", OP (0x06), OP_MASK, {R1, R2_NOTR0}, 0 },
668 { "satsub", OP (0x05), OP_MASK, {R1, R2_NOTR0}, 0 },
669 { "satsubi", OP (0x33), OP_MASK, {I16, R1, R2_NOTR0}, 0 },
670 { "satsubr", OP (0x04), OP_MASK, {R1, R2_NOTR0}, 0 },
672 /* logical operation instructions */
673 { "tst", OP (0x0b), OP_MASK, IF1, 0 },
674 { "or", OP (0x08), OP_MASK, IF1, 0 },
675 { "ori", OP (0x34), OP_MASK, IF6U, 0 },
676 { "and", OP (0x0a), OP_MASK, IF1, 0 },
677 { "andi", OP (0x36), OP_MASK, IF6U, 0 },
678 { "xor", OP (0x09), OP_MASK, IF1, 0 },
679 { "xori", OP (0x35), OP_MASK, IF6U, 0 },
680 { "not", OP (0x01), OP_MASK, IF1, 0 },
681 { "sar", OP (0x15), OP_MASK, {I5U, R2}, 0 },
682 { "sar", two (0x07e0, 0x00a0), two (0x07e0, 0xffff), {R1, R2}, 0 },
683 { "shl", OP (0x16), OP_MASK, {I5U, R2}, 0 },
684 { "shl", two (0x07e0, 0x00c0), two (0x07e0, 0xffff), {R1, R2}, 0 },
685 { "shr", OP (0x14), OP_MASK, {I5U, R2}, 0 },
686 { "shr", two (0x07e0, 0x0080), two (0x07e0, 0xffff), {R1, R2}, 0 },
687 /* start-sanitize-v850e */
688 { "sasf", two (0x07e0, 0x0200), two (0x07f0, 0xffff), {CCCC, R2}, 0 },
689 /* end-sanitize-v850e */
691 /* branch instructions */
693 { "bgt", BOP (0xf), BOP_MASK, IF3, 0 },
694 { "bge", BOP (0xe), BOP_MASK, IF3, 0 },
695 { "blt", BOP (0x6), BOP_MASK, IF3, 0 },
696 { "ble", BOP (0x7), BOP_MASK, IF3, 0 },
697 /* unsigned integer */
698 { "bh", BOP (0xb), BOP_MASK, IF3, 0 },
699 { "bnh", BOP (0x3), BOP_MASK, IF3, 0 },
700 { "bl", BOP (0x1), BOP_MASK, IF3, 0 },
701 { "bnl", BOP (0x9), BOP_MASK, IF3, 0 },
703 { "be", BOP (0x2), BOP_MASK, IF3, 0 },
704 { "bne", BOP (0xa), BOP_MASK, IF3, 0 },
706 { "bv", BOP (0x0), BOP_MASK, IF3, 0 },
707 { "bnv", BOP (0x8), BOP_MASK, IF3, 0 },
708 { "bn", BOP (0x4), BOP_MASK, IF3, 0 },
709 { "bp", BOP (0xc), BOP_MASK, IF3, 0 },
710 { "bc", BOP (0x1), BOP_MASK, IF3, 0 },
711 { "bnc", BOP (0x9), BOP_MASK, IF3, 0 },
712 { "bz", BOP (0x2), BOP_MASK, IF3, 0 },
713 { "bnz", BOP (0xa), BOP_MASK, IF3, 0 },
714 { "br", BOP (0x5), BOP_MASK, IF3, 0 },
715 { "bsa", BOP (0xd), BOP_MASK, IF3, 0 },
719 We use the short form in the opcode/mask fields. The assembler
720 will twiddle bits as necessary if the long form is needed. */
723 { "jgt", BOP (0xf), BOP_MASK, IF3, 0 },
724 { "jge", BOP (0xe), BOP_MASK, IF3, 0 },
725 { "jlt", BOP (0x6), BOP_MASK, IF3, 0 },
726 { "jle", BOP (0x7), BOP_MASK, IF3, 0 },
727 /* unsigned integer */
728 { "jh", BOP (0xb), BOP_MASK, IF3, 0 },
729 { "jnh", BOP (0x3), BOP_MASK, IF3, 0 },
730 { "jl", BOP (0x1), BOP_MASK, IF3, 0 },
731 { "jnl", BOP (0x9), BOP_MASK, IF3, 0 },
733 { "je", BOP (0x2), BOP_MASK, IF3, 0 },
734 { "jne", BOP (0xa), BOP_MASK, IF3, 0 },
736 { "jv", BOP (0x0), BOP_MASK, IF3, 0 },
737 { "jnv", BOP (0x8), BOP_MASK, IF3, 0 },
738 { "jn", BOP (0x4), BOP_MASK, IF3, 0 },
739 { "jp", BOP (0xc), BOP_MASK, IF3, 0 },
740 { "jc", BOP (0x1), BOP_MASK, IF3, 0 },
741 { "jnc", BOP (0x9), BOP_MASK, IF3, 0 },
742 { "jz", BOP (0x2), BOP_MASK, IF3, 0 },
743 { "jnz", BOP (0xa), BOP_MASK, IF3, 0 },
744 { "jsa", BOP (0xd), BOP_MASK, IF3, 0 },
745 { "jbr", BOP (0x5), BOP_MASK, IF3, 0 },
747 { "jr", one (0x0780), two (0xffc0, 0x0001), {D22}, 0 },
748 { "jarl", one (0x0780), two (0x07c0, 0x0001), {D22, R2}, 0 },
750 /* bit manipulation instructions */
751 { "set1", two (0x07c0, 0x0000), two (0xc7e0, 0x0000), {B3, D16, R1}, 2 },
752 /* start-sanitize-v850e */
753 { "set1", two (0x07e0, 0x00e0), two (0x07e0, 0xffff), {R2, R1}, 2 },
754 /* end-sanitize-v850e */
755 { "not1", two (0x47c0, 0x0000), two (0xc7e0, 0x0000), {B3, D16, R1}, 2 },
756 /* start-sanitize-v850e */
757 { "not1", two (0x07e0, 0x00e2), two (0x07e0, 0xffff), {R2, R1}, 2 },
758 /* end-sanitize-v850e */
759 { "clr1", two (0x87c0, 0x0000), two (0xc7e0, 0x0000), {B3, D16, R1}, 2 },
760 /* start-sanitize-v850e */
761 { "clr1", two (0x07e0, 0x00e4), two (0x07e0, 0xffff), {R2, R1}, 2 },
762 /* end-sanitize-v850e */
763 { "tst1", two (0xc7c0, 0x0000), two (0xc7e0, 0x0000), {B3, D16, R1}, 2 },
764 /* start-sanitize-v850e */
765 { "tst1", two (0x07e0, 0x00e6), two (0x07e0, 0xffff), {R2, R1}, 2 },
766 /* end-sanitize-v850e */
768 /* special instructions */
769 { "di", two (0x07e0, 0x0160), two (0xffff, 0xffff), {0}, 0 },
770 { "ei", two (0x87e0, 0x0160), two (0xffff, 0xffff), {0}, 0 },
771 { "halt", two (0x07e0, 0x0120), two (0xffff, 0xffff), {0}, 0 },
772 { "reti", two (0x07e0, 0x0140), two (0xffff, 0xffff), {0}, 0 },
773 { "trap", two (0x07e0, 0x0100), two (0xffe0, 0xffff), {I5U}, 0 },
774 { "ldsr", two (0x07e0, 0x0020), two (0x07e0, 0xffff), {R1, SR2}, 0 },
775 { "stsr", two (0x07e0, 0x0040), two (0x07e0, 0xffff), {SR1, R2}, 0 },
780 const int v850_num_opcodes =
781 sizeof (v850_opcodes) / sizeof (v850_opcodes[0]);