2 #include "opcode/v850.h"
5 #define OP(x) ((x & 0x3f) << 5)
6 #define OP_MASK OP(0x3f)
8 /* conditional branch opcode */
9 #define BOP(x) ((0x0b << 7) | (x & 0x0f))
10 #define BOP_MASK ((0x0b << 7) | 0x0f)
12 /* one-word opcodes */
13 #define one(x) ((unsigned int) (x))
15 /* two-word opcodes */
16 #define two(x,y) ((unsigned int) (y) | ((unsigned int) (x) << 16))
20 const struct v850_operand v850_operands[] = {
24 /* The R1 field in a format 1, 6, 7, or 9 insn. */
26 { 5, 0, OPERAND_REG },
28 /* The R2 field in a format 1, 2, 4, 5, 6, 7, 9 insn. */
30 { 5, 11, OPERAND_REG },
32 /* The IMM5 field in a format 2 insn. */
34 { 5, 0, OPERAND_NUM },
36 #define IMM16 field in a format 6 insn. */
38 { 16, 0, OPERAND_NUM },
40 /* The DISP6 field in a format 4 insn. */
42 { 6, 1, OPERAND_NUM },
44 /* The DISP8 field in a format 3 insn. */
46 { 9, 0, OPERAND_NUM },
48 /* The DISP16 field in a format 6 insn. */
50 { 16, 0, OPERAND_NUM },
52 /* The DISP22 field in a format 4 insn. */
54 { 16, 0, OPERAND_NUM },
57 /* The 3 bit immediate field in format 8 insn. */
58 { 3, 11, OPERAND_NUM }
62 /* reg-reg instruction format (Format I) */
65 /* imm-reg instruction format (Format II) */
68 /* conditional branch instruction format (Format III) */
71 /* 16-bit load/store instruction (Format IV) */
75 /* Jump instruction (Format V) */
78 /* 3 operand instruction (Format VI) */
79 #define IF6 {I16, R1, R2}
81 /* 32-bit load/store instruction (Format VII) */
82 #define IF7A {D16, R1, R2}
83 #define IF7B {R2, D16, R1}
85 /* Bit manipulation function. */
91 The format of the opcode table is:
93 NAME OPCODE MASK { OPERANDS }
95 NAME is the name of the instruction.
96 OPCODE is the instruction opcode.
97 MASK is the opcode mask; this is used to tell the disassembler
98 which bits in the actual opcode must match OPCODE.
99 OPERANDS is the list of operands.
101 The disassembler reads the table in order and prints the first
102 instruction which matches, so this table is sorted to put more
103 specific instructions before more general instructions. It is also
104 sorted by major opcode. */
106 const struct v850_opcode v850_opcodes[] = {
107 /* load/store instructions */
108 { "sld.b", OP(0x00), OP_MASK, IF4A },
109 { "sld.h", OP(0x00), OP_MASK, IF4A },
110 { "sld.w", OP(0x00), OP_MASK, IF4A },
111 { "sst.b", OP(0x00), OP_MASK, IF4B },
112 { "sst.w", OP(0x00), OP_MASK, IF4B },
113 { "sst.l", OP(0x00), OP_MASK, IF4B },
115 { "ld.b", OP(0x00), OP_MASK, IF7A },
116 { "ld.h", OP(0x00), OP_MASK, IF7A },
117 { "ld.w", OP(0x00), OP_MASK, IF7A },
118 { "st.b", OP(0x00), OP_MASK, IF7B },
119 { "st.h", OP(0x00), OP_MASK, IF7B },
120 { "st.w", OP(0x00), OP_MASK, IF7B },
122 /* arithmetic operation instructions */
123 { "mov", OP(0x00), OP_MASK, IF1 },
124 { "mov", OP(0x08), OP_MASK, IF2 },
125 { "movea", OP(0x31), OP_MASK, IF6 },
126 { "movhi", OP(0x31), OP_MASK, IF6 },
127 { "add", OP(0x0e), OP_MASK, IF1 },
128 { "add", OP(0x12), OP_MASK, IF2 },
129 { "addi", OP(0x30), OP_MASK, IF6 },
130 { "sub", OP(0x0d), OP_MASK, IF1 },
131 { "subr", OP(0x0c), OP_MASK, IF1 },
132 { "mulh", OP(0x07), OP_MASK, IF1 },
133 { "mulh", OP(0x17), OP_MASK, IF2 },
134 { "mulhi", OP(0x37), OP_MASK, IF6 },
135 { "divh", OP(0x02), OP_MASK, IF1 },
136 { "cmp", OP(0x0f), OP_MASK, IF1 },
137 { "cmp", OP(0x13), OP_MASK, IF2 },
139 { "setf", two(0x0000,0x0000), two(0x0000,0xffff), {I5,R2} },
140 /* XXX - really I4 */
142 /* saturated operation instructions */
143 { "satadd", OP(0x06), OP_MASK, IF1 },
144 { "satadd", OP(0x11), OP_MASK, IF2 },
145 { "satsub", OP(0x05), OP_MASK, IF1 },
146 { "satsubi", OP(0x33), OP_MASK, IF6 },
147 { "satsubr", OP(0x04), OP_MASK, IF1 },
149 /* logical operation instructions */
150 { "tst", OP(0x0b), OP_MASK, IF1 },
151 { "or", OP(0x08), OP_MASK, IF1 },
152 { "ori", OP(0x34), OP_MASK, IF6 },
153 { "and", OP(0x0a), OP_MASK, IF1 },
154 { "andi", OP(0x36), OP_MASK, IF6 },
155 { "xor", OP(0x09), OP_MASK, IF1 },
156 { "xori", OP(0x35), OP_MASK, IF6 },
157 { "not", OP(0x01), OP_MASK, IF1 },
158 { "sar", OP(0x15), OP_MASK, IF2 },
159 { "sar", two(0x07e0,0x00a0), two(0x07e0,0xffff), {R1,R2} },
160 { "shl", OP(0x16), OP_MASK, IF2 },
161 { "shl", two(0x07e0,0x00c0), two(0x07e0,0xffff), {R1,R2} },
162 { "shr", OP(0x14), OP_MASK, IF2 },
163 { "shr", two(0x07e0,0x0080), two(0x07e0,0xffff), {R1,R2} },
165 /* branch instructions */
167 { "bgt", BOP(0xf), BOP_MASK, IF3 },
168 { "bge", BOP(0xe), BOP_MASK, IF3 },
169 { "blt", BOP(0x6), BOP_MASK, IF3 },
170 { "ble", BOP(0x7), BOP_MASK, IF3 },
171 /* unsigned integer */
172 { "bh", BOP(0xb), BOP_MASK, IF3 },
173 { "bnh", BOP(0x3), BOP_MASK, IF3 },
174 { "bl", BOP(0x1), BOP_MASK, IF3 },
175 { "bnl", BOP(0x9), BOP_MASK, IF3 },
177 { "be", BOP(0x2), BOP_MASK, IF3 },
178 { "bne", BOP(0xa), BOP_MASK, IF3 },
180 { "bv", BOP(0x0), BOP_MASK, IF3 },
181 { "bnv", BOP(0x8), BOP_MASK, IF3 },
182 { "bn", BOP(0x4), BOP_MASK, IF3 },
183 { "bp", BOP(0xc), BOP_MASK, IF3 },
184 { "bc", BOP(0x1), BOP_MASK, IF3 },
185 { "bnc", BOP(0x9), BOP_MASK, IF3 },
186 { "bz", BOP(0x2), BOP_MASK, IF3 },
187 { "bnz", BOP(0xa), BOP_MASK, IF3 },
188 { "br", BOP(0x5), BOP_MASK, IF3 },
189 { "bsa", BOP(0xd), BOP_MASK, IF3 },
191 { "jmp", one(0x0060), one(0xffe0), R1 },
192 { "jarl", one(0x0780), one(0xf83f), { D22, R2 } },
193 { "jr", one(0x0780), one(0xffe0), { D22 } },
195 /* bit manipulation instructions */
196 { "set1", two(0x07c0,0x0000), two(0xc7e0,0x0000), {B3, D16, R1} },
197 { "not1", two(0x47c0,0x0000), two(0xc7e0,0x0000), {B3, D16, R1} },
198 { "clr1", two(0x87c0,0x0000), two(0xc7e0,0x0000), {B3, D16, R1} },
199 { "tst1", two(0xc7c0,0x0000), two(0xc7e0,0x0000), {B3, D16, R1} },
201 /* special instructions */
202 { "di", two(0x07e0,0x0160), two(0xffff,0xffff), {0} },
203 { "ei", two(0x87e0,0x0160), two(0xffff,0xffff), {0} },
204 { "halt", two(0x07e0,0x0120), two(0xffff,0xffff), {0} },
205 { "reti", two(0x07e0,0x0140), two(0xffff,0xffff), {0} },
206 { "trap", two(0x07e0,0x0100), two(0xffe0,0xffff), {I5} },
207 { "ldsr", two(0x07e0,0x0020), two(0x07e0,0xffff), {0} },
208 { "stsr", two(0x07e0,0x0040), two(0x07e0,0xffff), {0} },
209 { "nop", one(0x00), one(0xff), {0} },
213 const int v850_num_opcodes =
214 sizeof (v850_opcodes) / sizeof (v850_opcodes[0]);