2 #include "opcode/v850.h"
4 /* Local insertion and extraction functions. */
5 static unsigned long insert_d9 PARAMS ((unsigned long, long, const char **));
6 static long extract_d9 PARAMS ((unsigned long, int *));
9 #define OP(x) ((x & 0x3f) << 5)
10 #define OP_MASK OP(0x3f)
12 /* conditional branch opcode */
13 #define BOP(x) ((0x0b << 7) | (x & 0x0f))
14 #define BOP_MASK ((0x0b << 7) | 0x0f)
16 /* one-word opcodes */
17 #define one(x) ((unsigned int) (x))
19 /* two-word opcodes */
20 #define two(x,y) ((unsigned int) (x) | ((unsigned int) (y) << 16))
24 const struct v850_operand v850_operands[] = {
28 /* The R1 field in a format 1, 6, 7, or 9 insn. */
30 { 5, 0, 0, 0, V850_OPERAND_REG },
32 /* The R2 field in a format 1, 2, 4, 5, 6, 7, 9 insn. */
34 { 5, 11, 0, 0, V850_OPERAND_REG },
36 /* The IMM5 field in a format 2 insn. */
38 { 5, 0, 0, 0, V850_OPERAND_SIGNED },
43 /* The IMM16 field in a format 6 insn. */
47 /* The signed DISP7 field in a format 4 insn. */
49 { 7, 0, 0, 0, V850_OPERAND_SIGNED },
51 /* The DISP9 field in a format 3 insn. */
53 { 0, 0, insert_d9, extract_d9, V850_OPERAND_SIGNED },
55 /* The DISP16 field in a format 6 insn. */
57 { 16, 16, 0, 0, V850_OPERAND_SIGNED },
59 /* The DISP22 field in a format 4 insn. */
64 /* The 3 bit immediate field in format 8 insn. */
68 /* The 4 bit condition code in a setf instruction */
69 { 4, 0, 0, 0, V850_OPERAND_CC },
71 /* The unsigned DISP8 field in a format 4 insn. */
75 /* System register operands. */
77 { 5, 0, 0, 0, V850_OPERAND_SRG },
80 { 5, 11, 0, 0, V850_OPERAND_SRG },
84 /* reg-reg instruction format (Format I) */
87 /* imm-reg instruction format (Format II) */
90 /* conditional branch instruction format (Format III) */
93 /* 16-bit load/store instruction (Format IV) */
94 #define IF4A {D7S, R1, R2}
95 #define IF4B {R2, D7S, R1}
96 #define IF4C {D8, R1, R2}
97 #define IF4D {R2, D8, R1}
99 /* Jump instruction (Format V) */
102 /* 3 operand instruction (Format VI) */
103 #define IF6 {I16, R1, R2}
105 /* 32-bit load/store instruction (Format VII) */
106 #define IF7A {D16, R1, R2}
107 #define IF7B {R2, D16, R1}
109 /* Bit manipulation function. */
115 The format of the opcode table is:
117 NAME OPCODE MASK { OPERANDS }
119 NAME is the name of the instruction.
120 OPCODE is the instruction opcode.
121 MASK is the opcode mask; this is used to tell the disassembler
122 which bits in the actual opcode must match OPCODE.
123 OPERANDS is the list of operands.
125 The disassembler reads the table in order and prints the first
126 instruction which matches, so this table is sorted to put more
127 specific instructions before more general instructions. It is also
128 sorted by major opcode. */
130 const struct v850_opcode v850_opcodes[] = {
131 /* load/store instructions */
132 { "sld.b", OP(0x00), OP_MASK, IF4A, 2 },
133 { "sld.h", OP(0x00), OP_MASK, IF4C, 2 },
134 { "sld.w", OP(0x00), OP_MASK, IF4C, 2 },
135 { "sst.b", OP(0x00), OP_MASK, IF4B, 2 },
136 { "sst.h", OP(0x00), OP_MASK, IF4D, 2 },
137 { "sst.w", OP(0x00), OP_MASK, IF4D, 2 },
139 { "ld.b", OP(0x00), OP_MASK, IF7A, 4 },
140 { "ld.h", OP(0x00), OP_MASK, IF7A, 4 },
141 { "ld.w", OP(0x00), OP_MASK, IF7A, 4 },
142 { "st.b", OP(0x00), OP_MASK, IF7B, 4 },
143 { "st.h", OP(0x00), OP_MASK, IF7B, 4 },
144 { "st.w", OP(0x00), OP_MASK, IF7B, 4 },
146 /* arithmetic operation instructions */
147 { "mov", OP(0x00), OP_MASK, IF1, 2 },
148 { "mov", OP(0x08), OP_MASK, IF2, 2 },
149 { "movea", OP(0x31), OP_MASK, IF6, 4 },
150 { "movhi", OP(0x31), OP_MASK, IF6, 4 },
151 { "add", OP(0x0e), OP_MASK, IF1, 2 },
152 { "add", OP(0x12), OP_MASK, IF2, 2 },
153 { "addi", OP(0x30), OP_MASK, IF6, 4 },
154 { "sub", OP(0x0d), OP_MASK, IF1, 2 },
155 { "subr", OP(0x0c), OP_MASK, IF1, 2 },
156 { "mulh", OP(0x07), OP_MASK, IF1, 2 },
157 { "mulh", OP(0x17), OP_MASK, IF2, 2 },
158 { "mulhi", OP(0x37), OP_MASK, IF6, 4 },
159 { "divh", OP(0x02), OP_MASK, IF1, 2 },
160 { "cmp", OP(0x0f), OP_MASK, IF1, 2 },
161 { "cmp", OP(0x13), OP_MASK, IF2, 2 },
162 { "setf", two(0x07e0,0x0000), two(0x07f0,0xffff), {CCCC,R2}, 4 },
164 /* saturated operation instructions */
165 { "satadd", OP(0x06), OP_MASK, IF1, 2 },
166 { "satadd", OP(0x11), OP_MASK, IF2, 2 },
167 { "satsub", OP(0x05), OP_MASK, IF1, 2 },
168 { "satsubi", OP(0x33), OP_MASK, IF6, 4 },
169 { "satsubr", OP(0x04), OP_MASK, IF1, 2 },
171 /* logical operation instructions */
172 { "tst", OP(0x0b), OP_MASK, IF1, 2 },
173 { "or", OP(0x08), OP_MASK, IF1, 2 },
174 { "ori", OP(0x34), OP_MASK, IF6, 4 },
175 { "and", OP(0x0a), OP_MASK, IF1, 2 },
176 { "andi", OP(0x36), OP_MASK, IF6, 4 },
177 { "xor", OP(0x09), OP_MASK, IF1, 2 },
178 { "xori", OP(0x35), OP_MASK, IF6, 4 },
179 { "not", OP(0x01), OP_MASK, IF1, 4 },
180 { "sar", OP(0x15), OP_MASK, {I5U, R2}, 2 },
181 { "sar", two(0x07e0,0x00a0), two(0x07e0,0xffff), {R1,R2}, 4 },
182 { "shl", OP(0x16), OP_MASK, {I5U, R2}, 2 },
183 { "shl", two(0x07e0,0x00c0), two(0x07e0,0xffff), {R1,R2}, 4 },
184 { "shr", OP(0x14), OP_MASK, {I5U, R2}, 2 },
185 { "shr", two(0x07e0,0x0080), two(0x07e0,0xffff), {R1,R2}, 4 },
187 /* branch instructions */
189 { "bgt", BOP(0xf), BOP_MASK, IF3, 2 },
190 { "bge", BOP(0xe), BOP_MASK, IF3, 2 },
191 { "blt", BOP(0x6), BOP_MASK, IF3, 2 },
192 { "ble", BOP(0x7), BOP_MASK, IF3, 2 },
193 /* unsigned integer */
194 { "bh", BOP(0xb), BOP_MASK, IF3, 2 },
195 { "bnh", BOP(0x3), BOP_MASK, IF3, 2 },
196 { "bl", BOP(0x1), BOP_MASK, IF3, 2 },
197 { "bnl", BOP(0x9), BOP_MASK, IF3, 2 },
199 { "be", BOP(0x2), BOP_MASK, IF3, 2 },
200 { "bne", BOP(0xa), BOP_MASK, IF3, 2 },
202 { "bv", BOP(0x0), BOP_MASK, IF3, 2 },
203 { "bnv", BOP(0x8), BOP_MASK, IF3, 2 },
204 { "bn", BOP(0x4), BOP_MASK, IF3, 2 },
205 { "bp", BOP(0xc), BOP_MASK, IF3, 2 },
206 { "bc", BOP(0x1), BOP_MASK, IF3, 2 },
207 { "bnc", BOP(0x9), BOP_MASK, IF3, 2 },
208 { "bz", BOP(0x2), BOP_MASK, IF3, 2 },
209 { "bnz", BOP(0xa), BOP_MASK, IF3, 2 },
210 { "br", BOP(0x5), BOP_MASK, IF3, 2 },
211 { "bsa", BOP(0xd), BOP_MASK, IF3, 2 },
213 { "jmp", one(0x0060), one(0xffe0), { R1}, 2 },
214 { "jarl", one(0x0780), one(0xf83f), { D22, R2 }, 4 },
215 { "jr", one(0x0780), one(0xffe0), { D22 }, 4 },
217 /* bit manipulation instructions */
218 { "set1", two(0x07c0,0x0000), two(0xc7e0,0x0000), {B3, D16, R1}, 4 },
219 { "not1", two(0x47c0,0x0000), two(0xc7e0,0x0000), {B3, D16, R1}, 4 },
220 { "clr1", two(0x87c0,0x0000), two(0xc7e0,0x0000), {B3, D16, R1}, 4 },
221 { "tst1", two(0xc7c0,0x0000), two(0xc7e0,0x0000), {B3, D16, R1}, 4 },
223 /* special instructions */
224 { "di", two(0x07e0,0x0160), two(0xffff,0xffff), {0}, 4 },
225 { "ei", two(0x87e0,0x0160), two(0xffff,0xffff), {0}, 4 },
226 { "halt", two(0x07e0,0x0120), two(0xffff,0xffff), {0}, 4 },
227 { "reti", two(0x07e0,0x0140), two(0xffff,0xffff), {0}, 4 },
228 { "trap", two(0x07e0,0x0100), two(0xffe0,0xffff), {I5U}, 4 },
229 { "ldsr", two(0x07e0,0x0020), two(0x07e0,0xffff), {R1,SR2}, 4 },
230 { "stsr", two(0x07e0,0x0040), two(0x07e0,0xffff), {SR1,R2}, 4 },
231 { "nop", one(0x00), one(0xff), {0}, 2 },
235 const int v850_num_opcodes =
236 sizeof (v850_opcodes) / sizeof (v850_opcodes[0]);
239 /* The functions used to insert and extract complicated operands. */
242 insert_d9 (insn, value, errmsg)
247 if (value > 511 || value <= -512)
248 *errmsg = "value out of range";
250 return (insn | ((value & 0x1f0) << 7) | ((value & 0x0e) << 3));
254 extract_d9 (insn, invalid)
258 long ret = ((insn & 0xf800) >> 7) | ((insn & 0x0070) >> 3);
260 if ((insn & 0x8000) != 0)