1 /* Disassemble V850 instructions.
2 Copyright 1996-2013 Free Software Foundation, Inc.
4 This file is part of the GNU opcodes library.
6 This library is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 3, or (at your option)
11 It is distributed in the hope that it will be useful, but WITHOUT
12 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
13 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
14 License for more details.
16 You should have received a copy of the GNU General Public License
17 along with this program; if not, write to the Free Software
18 Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
19 MA 02110-1301, USA. */
25 #include "opcode/v850.h"
29 static const char *const v850_reg_names[] =
31 "r0", "r1", "r2", "sp", "gp", "r5", "r6", "r7",
32 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
33 "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23",
34 "r24", "r25", "r26", "r27", "r28", "r29", "ep", "lp"
37 static const char *const v850_sreg_names[] =
39 "eipc/vip/mpm", "eipsw/mpc", "fepc/tid", "fepsw/ppa", "ecr/vmecr", "psw/vmtid",
40 "sr6/fpsr/vmadr/dcc", "sr7/fpepc/dc0",
41 "sr8/fpst/vpecr/dcv1", "sr9/fpcc/vptid", "sr10/fpcfg/vpadr/spal", "sr11/spau",
42 "sr12/vdecr/ipa0l", "eiic/vdtid/ipa0u", "feic/ipa1l", "dbic/ipa1u",
43 "ctpc/ipa2l", "ctpsw/ipa2u", "dbpc/ipa3l", "dbpsw/ipa3u", "ctbp/dpa0l",
44 "dir/dpa0u", "bpc/dpa0u", "asid/dpa1l",
45 "bpav/dpa1u", "bpam/dpa2l", "bpdv/dpa2u", "bpdm/dpa3l", "eiwr/dpa3u",
46 "fewr", "dbwr", "bsel"
49 static const char *const v850_cc_names[] =
51 "v", "c/l", "z", "nh", "s/n", "t", "lt", "le",
52 "nv", "nc/nl", "nz", "h", "ns/p", "sa", "ge", "gt"
55 static const char *const v850_float_cc_names[] =
57 "f/t", "un/or", "eq/neq", "ueq/ogl", "olt/uge", "ult/oge", "ole/ugt", "ule/ogt",
58 "sf/st", "ngle/gle", "seq/sne", "ngl/gl", "lt/nlt", "nge/ge", "le/nle", "ngt/gt"
62 static const char *const v850_vreg_names[] =
64 "vr0", "vr1", "vr2", "vr3", "vr4", "vr5", "vr6", "vr7", "vr8", "vr9",
65 "vr10", "vr11", "vr12", "vr13", "vr14", "vr15", "vr16", "vr17", "vr18",
66 "vr19", "vr20", "vr21", "vr22", "vr23", "vr24", "vr25", "vr26", "vr27",
67 "vr28", "vr29", "vr30", "vr31"
70 static const char *const v850_cacheop_names[] =
72 "chbii", "cibii", "cfali", "cisti", "cildi", "chbid", "chbiwbd",
73 "chbwbd", "cibid", "cibiwbd", "cibwbd", "cfald", "cistd", "cildd"
76 static const int const v850_cacheop_codes[] =
78 0x00, 0x20, 0x40, 0x60, 0x61, 0x04, 0x06,
79 0x07, 0x24, 0x26, 0x27, 0x44, 0x64, 0x65, -1
82 static const char *const v850_prefop_names[] =
85 static const int const v850_prefop_codes[] =
89 print_value (int flags,
91 struct disassemble_info *info,
94 if (flags & V850_PCREL)
96 bfd_vma addr = value + memaddr;
97 info->print_address_func (addr, info);
99 else if (flags & V850_OPERAND_DISP)
101 if (flags & V850_OPERAND_SIGNED)
103 info->fprintf_func (info->stream, "%ld", value);
107 info->fprintf_func (info->stream, "%lu", value);
110 else if ((flags & V850E_IMMEDIATE32)
111 || (flags & V850E_IMMEDIATE16HI))
113 info->fprintf_func (info->stream, "0x%lx", value);
117 if (flags & V850_OPERAND_SIGNED)
119 info->fprintf_func (info->stream, "%ld", value);
123 info->fprintf_func (info->stream, "%lu", value);
129 get_operand_value (const struct v850_operand *operand,
133 struct disassemble_info * info,
140 if ((operand->flags & V850E_IMMEDIATE16)
141 || (operand->flags & V850E_IMMEDIATE16HI))
143 int status = info->read_memory_func (memaddr + bytes_read, buffer, 2, info);
147 value = bfd_getl16 (buffer);
149 if (operand->flags & V850E_IMMEDIATE16HI)
151 else if (value & 0x8000)
152 value |= (-1L << 16);
158 info->memory_error_func (status, memaddr + bytes_read, info);
163 if (operand->flags & V850E_IMMEDIATE23)
165 int status = info->read_memory_func (memaddr + 2, buffer, 4, info);
169 value = bfd_getl32 (buffer);
171 value = (operand->extract) (value, invalid);
177 info->memory_error_func (status, memaddr + bytes_read, info);
182 if (operand->flags & V850E_IMMEDIATE32)
184 int status = info->read_memory_func (memaddr + bytes_read, buffer, 4, info);
189 value = bfd_getl32 (buffer);
195 info->memory_error_func (status, memaddr + bytes_read, info);
200 if (operand->extract)
201 value = (operand->extract) (insn, invalid);
204 if (operand->bits == -1)
205 value = (insn & operand->shift);
207 value = (insn >> operand->shift) & ((1 << operand->bits) - 1);
209 if (operand->flags & V850_OPERAND_SIGNED)
210 value = ((long)(value << (sizeof (long)*8 - operand->bits))
211 >> (sizeof (long)*8 - operand->bits));
219 disassemble (bfd_vma memaddr,
220 struct disassemble_info *info,
224 struct v850_opcode *op = (struct v850_opcode *) v850_opcodes;
225 const struct v850_operand *operand;
227 int target_processor;
233 target_processor = PROCESSOR_V850;
237 target_processor = PROCESSOR_V850E;
240 case bfd_mach_v850e1:
241 target_processor = PROCESSOR_V850E;
244 case bfd_mach_v850e2:
245 target_processor = PROCESSOR_V850E2;
248 case bfd_mach_v850e2v3:
249 target_processor = PROCESSOR_V850E2V3;
252 case bfd_mach_v850e3v5:
253 target_processor = PROCESSOR_V850E3V5;
257 /* If this is a two byte insn, then mask off the high bits. */
261 /* Find the opcode. */
264 if ((op->mask & insn) == op->opcode
265 && (op->processors & target_processor)
266 && !(op->processors & PROCESSOR_OPTION_ALIAS))
268 /* Code check start. */
269 const unsigned char *opindex_ptr;
273 for (opindex_ptr = op->operands, opnum = 1;
275 opindex_ptr++, opnum++)
280 operand = &v850_operands[*opindex_ptr];
282 value = get_operand_value (operand, insn, bytes_read, memaddr,
288 if ((operand->flags & V850_NOT_R0) && value == 0 && (op->memop) <=2)
291 if ((operand->flags & V850_NOT_SA) && value == 0xd)
294 if ((operand->flags & V850_NOT_IMM0) && value == 0)
298 /* Code check end. */
301 (*info->fprintf_func) (info->stream, "%s\t", op->name);
303 fprintf (stderr, "match: insn: %lx, mask: %lx, opcode: %lx, name: %s\n",
304 insn, op->mask, op->opcode, op->name );
308 /* Now print the operands.
310 MEMOP is the operand number at which a memory
311 address specification starts, or zero if this
312 instruction has no memory addresses.
314 A memory address is always two arguments.
316 This information allows us to determine when to
317 insert commas into the output stream as well as
318 when to insert disp[reg] expressions onto the
321 for (opindex_ptr = op->operands, opnum = 1;
323 opindex_ptr++, opnum++)
325 bfd_boolean square = FALSE;
330 operand = &v850_operands[*opindex_ptr];
332 value = get_operand_value (operand, insn, bytes_read, memaddr,
335 /* The first operand is always output without any
338 For the following arguments:
340 If memop && opnum == memop + 1, then we need '[' since
341 we're about to output the register used in a memory
344 If memop && opnum == memop + 2, then we need ']' since
345 we just finished the register in a memory reference. We
346 also need a ',' before this operand.
348 Else we just need a comma.
350 We may need to output a trailing ']' if the last operand
351 in an instruction is the register for a memory address.
353 The exception (and there's always an exception) are the
354 "jmp" insn which needs square brackets around it's only
355 register argument, and the clr1/not1/set1/tst1 insns
356 which [...] around their second register argument. */
359 if (operand->flags & V850_OPERAND_BANG)
363 else if (operand->flags & V850_OPERAND_PERCENT)
368 if (opnum == 1 && opnum == memop)
370 info->fprintf_func (info->stream, "%s[", prefix);
373 else if ( (strcmp ("stc.w", op->name) == 0
374 || strcmp ("cache", op->name) == 0
375 || strcmp ("pref", op->name) == 0)
376 && opnum == 2 && opnum == memop)
378 info->fprintf_func (info->stream, ", [");
381 else if ( (strcmp (op->name, "pushsp") == 0
382 || strcmp (op->name, "popsp") == 0
383 || strcmp (op->name, "dbpush" ) == 0)
386 info->fprintf_func (info->stream, "-");
389 && (v850_operands[*(opindex_ptr - 1)].flags
390 & V850_OPERAND_DISP) != 0
393 info->fprintf_func (info->stream, "%s[", prefix);
397 && ( op->opcode == 0x00e407e0 /* clr1 */
398 || op->opcode == 0x00e207e0 /* not1 */
399 || op->opcode == 0x00e007e0 /* set1 */
400 || op->opcode == 0x00e607e0 /* tst1 */
403 info->fprintf_func (info->stream, ", %s[", prefix);
407 info->fprintf_func (info->stream, ", %s", prefix);
409 /* Extract the flags, ignoring ones which do not
410 effect disassembly output. */
411 flag = operand->flags & (V850_OPERAND_REG
415 | V850E_OPERAND_REG_LIST
418 | V850_OPERAND_CACHEOP
419 | V850_OPERAND_PREFOP
420 | V850_OPERAND_FLOAT_CC);
424 case V850_OPERAND_REG:
425 info->fprintf_func (info->stream, "%s", v850_reg_names[value]);
427 case (V850_OPERAND_REG|V850_REG_EVEN):
428 info->fprintf_func (info->stream, "%s", v850_reg_names[value * 2]);
430 case V850_OPERAND_EP:
431 info->fprintf_func (info->stream, "ep");
433 case V850_OPERAND_SRG:
434 info->fprintf_func (info->stream, "%s", v850_sreg_names[value]);
436 case V850E_OPERAND_REG_LIST:
438 static int list12_regs[32] = { 30, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
439 0, 0, 0, 0, 0, 31, 29, 28, 23, 22, 21, 20, 27, 26, 25, 24 };
442 unsigned long int mask = 0;
445 switch (operand->shift)
447 case 0xffe00001: regs = list12_regs; break;
449 /* xgettext:c-format */
450 fprintf (stderr, _("unknown operand shift: %x\n"), operand->shift);
454 for (i = 0; i < 32; i++)
456 if (value & (1 << i))
460 default: mask |= (1 << regs[ i ]); break;
461 /* xgettext:c-format */
462 case 0: fprintf (stderr, _("unknown reg: %d\n"), i ); abort ();
463 case -1: pc = 1; break;
468 info->fprintf_func (info->stream, "{");
477 for (bit = 0; bit < 32; bit++)
478 if (mask & (1 << bit))
480 unsigned long int first = bit;
481 unsigned long int last;
484 info->fprintf_func (info->stream, ", ");
488 info->fprintf_func (info->stream, "%s", v850_reg_names[first]);
490 for (bit++; bit < 32; bit++)
491 if ((mask & (1 << bit)) == 0)
496 if (last > first + 1)
498 info->fprintf_func (info->stream, " - %s", v850_reg_names[ last - 1 ]);
504 info->fprintf_func (info->stream, "%sPC", mask ? ", " : "");
507 info->fprintf_func (info->stream, "}");
511 case V850_OPERAND_CC:
512 info->fprintf_func (info->stream, "%s", v850_cc_names[value]);
515 case V850_OPERAND_FLOAT_CC:
516 info->fprintf_func (info->stream, "%s", v850_float_cc_names[value]);
519 case V850_OPERAND_CACHEOP:
523 for (idx = 0; v850_cacheop_codes[idx] != -1; idx++)
525 if (value == v850_cacheop_codes[idx])
527 info->fprintf_func (info->stream, "%s",
528 v850_cacheop_names[idx]);
529 goto MATCH_CACHEOP_CODE;
532 info->fprintf_func (info->stream, "%d", (int) value);
537 case V850_OPERAND_PREFOP:
541 for (idx = 0; v850_prefop_codes[idx] != -1; idx++)
543 if (value == v850_prefop_codes[idx])
545 info->fprintf_func (info->stream, "%s",
546 v850_prefop_names[idx]);
547 goto MATCH_PREFOP_CODE;
550 info->fprintf_func (info->stream, "%d", (int) value);
555 case V850_OPERAND_VREG:
556 info->fprintf_func (info->stream, "%s", v850_vreg_names[value]);
560 print_value (operand->flags, memaddr, info, value);
565 (*info->fprintf_func) (info->stream, "]");
579 print_insn_v850 (bfd_vma memaddr, struct disassemble_info * info)
581 int status, status2, match;
583 int length = 0, code_length = 0;
584 unsigned long insn = 0, insn2 = 0;
585 int target_processor;
591 target_processor = PROCESSOR_V850;
595 target_processor = PROCESSOR_V850E;
598 case bfd_mach_v850e1:
599 target_processor = PROCESSOR_V850E;
602 case bfd_mach_v850e2:
603 target_processor = PROCESSOR_V850E2;
606 case bfd_mach_v850e2v3:
607 target_processor = PROCESSOR_V850E2V3;
610 case bfd_mach_v850e3v5:
611 target_processor = PROCESSOR_V850E3V5;
615 status = info->read_memory_func (memaddr, buffer, 2, info);
619 info->memory_error_func (status, memaddr, info);
623 insn = bfd_getl16 (buffer);
625 status2 = info->read_memory_func (memaddr+2, buffer, 2 , info);
629 insn2 = bfd_getl16 (buffer);
630 /* fprintf (stderr, "insn2 0x%08lx\n", insn2); */
635 && ((target_processor & PROCESSOR_V850E2_UP) != 0))
637 if ((insn & 0xffff) == 0x02e0 /* jr 32bit */
638 && !status2 && (insn2 & 0x1) == 0)
643 else if ((insn & 0xffe0) == 0x02e0 /* jarl 32bit */
644 && !status2 && (insn2 & 0x1) == 0)
649 else if ((insn & 0xffe0) == 0x06e0 /* jmp 32bit */
650 && !status2 && (insn2 & 0x1) == 0)
658 && ((target_processor & PROCESSOR_V850E3V5_UP) != 0))
660 if ( ((insn & 0xffe0) == 0x07a0 /* ld.dw 23bit (v850e3v5) */
661 && !status2 && (insn2 & 0x000f) == 0x0009)
662 || ((insn & 0xffe0) == 0x07a0 /* st.dw 23bit (v850e3v5) */
663 && !status2 && (insn2 & 0x000f) == 0x000f))
671 && ((target_processor & PROCESSOR_V850E2V3_UP) != 0))
673 if (((insn & 0xffe0) == 0x0780 /* ld.b 23bit */
674 && !status2 && (insn2 & 0x000f) == 0x0005)
675 || ((insn & 0xffe0) == 0x07a0 /* ld.bu 23bit */
676 && !status2 && (insn2 & 0x000f) == 0x0005)
677 || ((insn & 0xffe0) == 0x0780 /* ld.h 23bit */
678 && !status2 && (insn2 & 0x000f) == 0x0007)
679 || ((insn & 0xffe0) == 0x07a0 /* ld.hu 23bit */
680 && !status2 && (insn2 & 0x000f) == 0x0007)
681 || ((insn & 0xffe0) == 0x0780 /* ld.w 23bit */
682 && !status2 && (insn2 & 0x000f) == 0x0009))
687 else if (((insn & 0xffe0) == 0x0780 /* st.b 23bit */
688 && !status2 && (insn2 & 0x000f) == 0x000d)
689 || ((insn & 0xffe0) == 0x07a0 /* st.h 23bit */
690 && !status2 && (insn2 & 0x000f) == 0x000d)
691 || ((insn & 0xffe0) == 0x0780 /* st.w 23bit */
692 && !status2 && (insn2 & 0x000f) == 0x000f))
700 && target_processor != PROCESSOR_V850)
702 if ((insn & 0xffe0) == 0x0620) /* 32 bit MOV */
707 else if ((insn & 0xffc0) == 0x0780 /* prepare {list}, imm5, imm16<<16 */
708 && !status2 && (insn2 & 0x001f) == 0x0013)
713 else if ((insn & 0xffc0) == 0x0780 /* prepare {list}, imm5, imm16 */
714 && !status2 && (insn2 & 0x001f) == 0x000b)
719 else if ((insn & 0xffc0) == 0x0780 /* prepare {list}, imm5, imm32 */
720 && !status2 && (insn2 & 0x001f) == 0x001b)
729 && (insn & 0x0600) == 0x0600))
731 /* This is a 4 byte insn. */
732 status = info->read_memory_func (memaddr, buffer, 4, info);
735 insn = bfd_getl32 (buffer);
738 length = code_length = 4;
742 if (code_length > length)
744 status = info->read_memory_func (memaddr + length, buffer, code_length - length, info);
749 if (length == 0 && !status)
750 length = code_length = 2;
755 /* when the last 2 bytes of section is 0xffff, length will be 0 and cause infinitive loop */
759 match = disassemble (memaddr, info, length, insn);
765 status = info->read_memory_func (memaddr, buffer, code_length, info);
767 while (l < code_length)
769 if (code_length - l == 2)
771 insn = bfd_getl16 (buffer + l) & 0xffff;
772 info->fprintf_func (info->stream, ".short\t0x%04lx", insn);
777 insn = bfd_getl32 (buffer + l);
778 info->fprintf_func (info->stream, ".long\t0x%08lx", insn);