1 /* Opcode table for TI TMS320C80 (MVP).
2 Copyright 1996 Free Software Foundation, Inc.
4 This file is part of GDB, GAS, and the GNU binutils.
6 GDB, GAS, and the GNU binutils are free software; you can redistribute
7 them and/or modify them under the terms of the GNU General Public
8 License as published by the Free Software Foundation; either version
9 1, or (at your option) any later version.
11 GDB, GAS, and the GNU binutils are distributed in the hope that they
12 will be useful, but WITHOUT ANY WARRANTY; without even the implied
13 warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See
14 the GNU General Public License for more details.
16 You should have received a copy of the GNU General Public License
17 along with this file; see the file COPYING. If not, write to the Free
18 Software Foundation, 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */
22 #include "opcode/tic80.h"
24 /* This file holds the TMS320C80 (MVP) opcode table. The table is
25 strictly constant data, so the compiler should be able to put it in
28 This file also holds the operand table. All knowledge about
29 inserting operands into instructions and vice-versa is kept in this
33 /* The operands table. The fields are:
35 bits, shift, insertion function, extraction function, flags
38 const struct tic80_operand tic80_operands[] =
41 /* The zero index is used to indicate the end of the list of operands. */
46 /* Short signed immediate value in bits 14-0. */
48 #define SSI (UNUSED + 1)
49 { 15, 0, NULL, NULL, TIC80_OPERAND_SIGNED },
51 /* Short unsigned immediate value in bits 14-0 */
54 { 15, 0, NULL, NULL, 0 },
56 /* Short unsigned bitfield in bits 14-0. We distinguish this
57 from a regular unsigned immediate value only for the convenience
58 of the disassembler and the user. */
60 #define SUBF (SUI + 1)
61 { 15, 0, NULL, NULL, TIC80_OPERAND_BITFIELD },
63 /* Long signed immediate in following 32 bit word */
65 #define LSI (SUBF + 1)
66 { 32, 0, NULL, NULL, TIC80_OPERAND_SIGNED },
68 /* Long unsigned immediate in following 32 bit word */
71 { 32, 0, NULL, NULL, 0 },
73 /* Long unsigned bitfield in following 32 bit word. We distinguish
74 this from a regular unsigned immediate value only for the
75 convenience of the disassembler and the user. */
77 #define LUBF (LUI + 1)
78 { 32, 0, NULL, NULL, TIC80_OPERAND_BITFIELD },
80 /* Single precision floating point immediate in following 32 bit
83 #define SPFI (LUBF + 1)
84 { 32, 0, NULL, NULL, TIC80_OPERAND_FLOAT },
86 /* Register in bits 4-0 */
88 #define REG_0 (SPFI + 1)
89 { 5, 0, NULL, NULL, TIC80_OPERAND_GPR },
91 /* Register in bits 26-22 */
93 #define REG_22 (REG_0 + 1)
94 { 5, 22, NULL, NULL, TIC80_OPERAND_GPR },
96 /* Register in bits 31-27 */
98 #define REG_DEST (REG_22 + 1)
99 { 5, 27, NULL, NULL, TIC80_OPERAND_GPR },
101 /* Short signed offset in bits 14-0 */
103 #define OFF_SS (REG_DEST + 1)
104 { 15, 0, NULL, NULL, TIC80_OPERAND_RELATIVE | TIC80_OPERAND_SIGNED },
106 /* Long signed offset in following 32 bit word */
108 #define OFF_SL (OFF_SS + 1)
109 {32, 0, NULL, NULL, TIC80_OPERAND_RELATIVE | TIC80_OPERAND_SIGNED },
111 /* BITNUM in bits 31-27 */
113 #define BITNUM (OFF_SL + 1)
114 { 5, 27, NULL, NULL, TIC80_OPERAND_BITNUM },
116 /* Condition code in bits 31-27 */
118 #define CC (BITNUM + 1)
119 { 5, 27, NULL, NULL, TIC80_OPERAND_CC },
121 /* Control register number in bits 14-0 */
123 #define CR_SI (CC + 1)
124 { 15, 0, NULL, NULL, TIC80_OPERAND_CR },
126 /* Control register number in next 32 bit word */
128 #define CR_LI (CR_SI + 1)
129 { 32, 0, NULL, NULL, TIC80_OPERAND_CR },
131 /* A base register in bits 26-22, enclosed in parens, with optional ":m"
132 flag in bit 17 (short immediate instructions only) */
134 #define REG_BASE_M_SI (CR_LI + 1)
135 { 5, 22, NULL, NULL, TIC80_OPERAND_GPR | TIC80_OPERAND_PARENS | TIC80_OPERAND_M_SI },
137 /* A base register in bits 26-22, enclosed in parens, with optional ":m"
138 flag in bit 15 (long immediate and register instructions only) */
140 #define REG_BASE_M_LI (REG_BASE_M_SI + 1)
141 { 5, 22, NULL, NULL, TIC80_OPERAND_GPR | TIC80_OPERAND_PARENS | TIC80_OPERAND_M_LI },
143 /* Scaled register in bits 4-0, with optional ":s" modifier flag in bit 11 */
145 #define REG_SCALED (REG_BASE_M_LI + 1)
146 { 5, 0, NULL, NULL, TIC80_OPERAND_GPR | TIC80_OPERAND_SCALED },
148 /* Long signed immediate in following 32 bit word, with optional ":s" modifier
151 #define LSI_SCALED (REG_SCALED + 1)
152 { 32, 0, NULL, NULL, TIC80_OPERAND_SIGNED | TIC80_OPERAND_SCALED },
154 /* Unsigned immediate in bits 4-0, used only for shift instructions */
156 #define ROTATE (LSI_SCALED + 1)
157 { 5, 0, NULL, NULL, 0 },
159 /* Unsigned immediate in bits 9-5, used only for shift instructions */
160 #define ENDMASK (ROTATE + 1)
161 { 5, 5, NULL, NULL, 0 },
165 const int tic80_num_operands = sizeof (tic80_operands)/sizeof(*tic80_operands);
168 /* Macros used to generate entries for the opcodes table. */
172 /* Short-Immediate Format Instructions - basic opcode */
173 #define OP_SI(x) (((x) & 0x7F) << 15)
174 #define MASK_SI OP_SI(0x7F)
176 /* Long-Immediate Format Instructions - basic opcode */
177 #define OP_LI(x) (((x) & 0x3FF) << 12)
178 #define MASK_LI OP_LI(0x3FF)
180 /* Register Format Instructions - basic opcode */
181 #define OP_REG(x) OP_LI(x) /* For readability */
182 #define MASK_REG MASK_LI /* For readability */
184 /* The 'n' bit at bit 10 */
185 #define n(x) ((x) << 10)
187 /* The 'i' bit at bit 11 */
188 #define i(x) ((x) << 11)
190 /* The 'F' bit at bit 27 */
191 #define F(x) ((x) << 27)
193 /* The 'E' bit at bit 27 */
194 #define E(x) ((x) << 27)
196 /* The 'M' bit at bit 15 in register and long immediate opcodes */
197 #define M_REG(x) ((x) << 15)
198 #define M_LI(x) ((x) << 15)
200 /* The 'M' bit at bit 17 in short immediate opcodes */
201 #define M_SI(x) ((x) << 17)
203 /* The 'SZ' field at bits 14-13 in register and long immediate opcodes */
204 #define SZ_REG(x) ((x) << 13)
205 #define SZ_LI(x) ((x) << 13)
207 /* The 'SZ' field at bits 16-15 in short immediate opcodes */
208 #define SZ_SI(x) ((x) << 15)
210 /* The 'D' (direct external memory access) bit at bit 10 in long immediate
211 and register opcodes. */
212 #define D(x) ((x) << 10)
214 /* The 'S' (scale offset by data size) bit at bit 11 in long immediate
215 and register opcodes. */
216 #define S(x) ((x) << 11)
218 /* The 'PD' field at bits 10-9 in floating point instructions */
219 #define PD(x) ((x) << 9)
221 /* The 'P2' field at bits 8-7 in floating point instructions */
222 #define P2(x) ((x) << 7)
224 /* The 'P1' field at bits 6-5 in floating point instructions */
225 #define P1(x) ((x) << 5)
228 const struct tic80_opcode tic80_opcodes[] = {
230 /* The "nop" instruction is really "rdcr 0,r0". We put it first so that this
231 specific bit pattern will get disassembled as a nop rather than an rdcr. The
232 mask of all ones ensures that this will happen. */
234 {"nop", OP_SI(0x4), ~0, 0, {0} },
236 /* The "br" instruction is really "bbz target,r0,31". We put it first so that
237 this specific bit pattern will get disassembled as a br rather than bbz. */
239 {"br", OP_SI(0x48), 0xFFFF8000, 0, {OFF_SS} },
240 {"br", OP_LI(0x391), 0xFFFFF000, 0, {OFF_SL} },
241 {"br", OP_REG(0x390), 0xFFFFF000, 0, {REG_0} },
243 {"br.a", OP_SI(0x49), 0xFFFF8000, 0, {OFF_SS} },
244 {"br.a", OP_LI(0x393), 0xFFFFF000, 0, {OFF_SL} },
245 {"br.a", OP_REG(0x392), 0xFFFFF000, 0, {REG_0} },
247 /* Signed integer ADD */
249 {"add", OP_SI(0x58), MASK_SI, FMT_SI, {SSI, REG_22, REG_DEST} },
250 {"add", OP_LI(0x3B1), MASK_LI, FMT_LI, {LSI, REG_22, REG_DEST} },
251 {"add", OP_REG(0x3B0), MASK_REG, FMT_REG, {REG_0, REG_22, REG_DEST} },
253 /* Unsigned integer ADD */
255 {"addu", OP_SI(0x59), MASK_SI, FMT_SI, {SSI, REG_22, REG_DEST} },
256 {"addu", OP_LI(0x3B3), MASK_LI, FMT_LI, {LSI, REG_22, REG_DEST} },
257 {"addu", OP_REG(0x3B2), MASK_REG, FMT_REG, {REG_0, REG_22, REG_DEST} },
261 {"and", OP_SI(0x11), MASK_SI, FMT_SI, {SUBF, REG_22, REG_DEST} },
262 {"and", OP_LI(0x323), MASK_LI, FMT_LI, {LUBF, REG_22, REG_DEST} },
263 {"and", OP_REG(0x322), MASK_REG, FMT_REG, {REG_0, REG_22, REG_DEST} },
265 {"and.tt", OP_SI(0x11), MASK_SI, FMT_SI, {SUBF, REG_22, REG_DEST} },
266 {"and.tt", OP_LI(0x323), MASK_LI, FMT_LI, {LUBF, REG_22, REG_DEST} },
267 {"and.tt", OP_REG(0x322), MASK_REG, FMT_REG, {REG_0, REG_22, REG_DEST} },
269 /* Bitwise AND with ones complement of both sources */
271 {"and.ff", OP_SI(0x18), MASK_SI, FMT_SI, {SUBF, REG_22, REG_DEST} },
272 {"and.ff", OP_LI(0x331), MASK_LI, FMT_LI, {LUBF, REG_22, REG_DEST} },
273 {"and.ff", OP_REG(0x330), MASK_REG, FMT_REG, {REG_0, REG_22, REG_DEST} },
275 /* Bitwise AND with ones complement of source 1 */
277 {"and.ft", OP_SI(0x14), MASK_SI, FMT_SI, {SUBF, REG_22, REG_DEST} },
278 {"and.ft", OP_LI(0x329), MASK_LI, FMT_LI, {LUBF, REG_22, REG_DEST} },
279 {"and.ft", OP_REG(0x328), MASK_REG, FMT_REG, {REG_0, REG_22, REG_DEST} },
281 /* Bitwise AND with ones complement of source 2 */
283 {"and.tf", OP_SI(0x12), MASK_SI, FMT_SI, {SUBF, REG_22, REG_DEST} },
284 {"and.tf", OP_LI(0x325), MASK_LI, FMT_LI, {LUBF, REG_22, REG_DEST} },
285 {"and.tf", OP_REG(0x324), MASK_REG, FMT_REG, {REG_0, REG_22, REG_DEST} },
287 /* Branch Bit One - nonannulled */
289 {"bbo", OP_SI(0x4A), MASK_SI, FMT_SI, {OFF_SS, REG_22, BITNUM} },
290 {"bbo", OP_LI(0x395), MASK_LI, FMT_LI, {OFF_SL, REG_22, BITNUM} },
291 {"bbo", OP_REG(0x394), MASK_REG, FMT_REG, {REG_0, REG_22, BITNUM} },
293 /* Branch Bit One - annulled */
295 {"bbo.a", OP_SI(0x4B), MASK_SI, FMT_SI, {OFF_SS, REG_22, BITNUM} },
296 {"bbo.a", OP_LI(0x397), MASK_LI, FMT_LI, {OFF_SL, REG_22, BITNUM} },
297 {"bbo.a", OP_REG(0x396), MASK_REG, FMT_REG, {REG_0, REG_22, BITNUM} },
299 /* Branch Bit Zero - nonannulled */
301 {"bbz", OP_SI(0x48), MASK_SI, FMT_SI, {OFF_SS, REG_22, BITNUM} },
302 {"bbz", OP_LI(0x391), MASK_LI, FMT_LI, {OFF_SL, REG_22, BITNUM} },
303 {"bbz", OP_REG(0x390), MASK_REG, FMT_REG, {REG_0, REG_22, BITNUM} },
305 /* Branch Bit Zero - annulled */
307 {"bbz.a", OP_SI(0x49), MASK_SI, FMT_SI, {OFF_SS, REG_22, BITNUM} },
308 {"bbz.a", OP_LI(0x393), MASK_LI, FMT_LI, {OFF_SL, REG_22, BITNUM} },
309 {"bbz.a", OP_REG(0x392), MASK_REG, FMT_REG, {REG_0, REG_22, BITNUM} },
311 /* Branch Conditional - nonannulled */
313 {"bcnd", OP_SI(0x4C), MASK_SI, FMT_SI, {OFF_SS, REG_22, CC} },
314 {"bcnd", OP_LI(0x399), MASK_LI, FMT_LI, {OFF_SL, REG_22, CC} },
315 {"bcnd", OP_REG(0x398), MASK_REG, FMT_REG, {REG_0, REG_22, CC} },
317 /* Branch Conditional - annulled */
319 {"bcnd.a", OP_SI(0x4D), MASK_SI, FMT_SI, {OFF_SS, REG_22, CC} },
320 {"bcnd.a", OP_LI(0x39B), MASK_LI, FMT_LI, {OFF_SL, REG_22, CC} },
321 {"bcnd.a", OP_REG(0x39A), MASK_REG, FMT_REG, {REG_0, REG_22, CC} },
323 /* Branch Control Register */
325 {"brcr", OP_SI(0x6), MASK_SI, FMT_SI, {CR_SI} },
326 {"brcr", OP_LI(0x30D), MASK_LI, FMT_LI, {CR_LI} },
327 {"brcr", OP_REG(0x30C), MASK_REG, FMT_REG, {REG_0} },
329 /* Branch and save return - nonannulled */
331 {"bsr", OP_SI(0x40), MASK_SI, FMT_SI, {OFF_SS, REG_DEST} },
332 {"bsr", OP_LI(0x381), MASK_LI, FMT_LI, {OFF_SL, REG_DEST} },
333 {"bsr", OP_REG(0x380), MASK_REG, FMT_REG, {REG_0, REG_DEST} },
335 /* Branch and save return - annulled */
337 {"bsr.a", OP_SI(0x41), MASK_SI, FMT_SI, {OFF_SS, REG_DEST} },
338 {"bsr.a", OP_LI(0x383), MASK_LI, FMT_LI, {OFF_SL, REG_DEST} },
339 {"bsr.a", OP_REG(0x382), MASK_REG, FMT_REG, {REG_0, REG_DEST} },
343 {"cmnd", OP_SI(0x2), MASK_SI, FMT_SI, {SUI} },
344 {"cmnd", OP_LI(0x305), MASK_LI, FMT_LI, {LUI} },
345 {"cmnd", OP_REG(0x304), MASK_REG, FMT_REG, {REG_0} },
347 /* Integer compare */
349 {"cmp", OP_SI(0x50), MASK_SI, FMT_SI, {SSI, REG_22, REG_DEST} },
350 {"cmp", OP_LI(0x3A1), MASK_LI, FMT_LI, {LSI, REG_22, REG_DEST} },
351 {"cmp", OP_REG(0x3A0), MASK_REG, FMT_REG, {REG_0, REG_22, REG_DEST} },
353 /* Flush data cache subblock - don't clear subblock preset flag */
355 {"dcachec", OP_SI(0x38), F(1) | (MASK_SI & ~M_SI(1)), FMT_SI, {SSI, REG_BASE_M_SI} },
356 {"dcachec", OP_LI(0x371), F(1) | (MASK_LI & ~M_LI(1)) | S(1) | D(1), FMT_LI, {LSI, REG_BASE_M_LI} },
357 {"dcachec", OP_REG(0x370), F(1) | (MASK_REG & ~M_REG(1)) | S(1) | D(1), FMT_REG, {REG_0, REG_BASE_M_LI} },
359 /* Flush data cache subblock - clear subblock preset flag */
361 {"dcachef", OP_SI(0x38) | F(1), F(1) | (MASK_SI & ~M_SI(1)), FMT_SI, {SSI, REG_BASE_M_SI} },
362 {"dcachef", OP_LI(0x371) | F(1), F(1) | (MASK_LI & ~M_LI(1)) | S(1) | D(1), FMT_LI, {LSI, REG_BASE_M_LI} },
363 {"dcachef", OP_REG(0x370) | F(1), F(1) | (MASK_REG & ~M_REG(1)) | S(1) | D(1), FMT_REG, {REG_0, REG_BASE_M_LI} },
365 /* Direct load signed data into register */
367 {"dld.b", OP_LI(0x341) | D(1), (MASK_LI & ~M_REG(1)) | D(1), FMT_LI, {LSI_SCALED, REG_BASE_M_LI, REG_DEST} },
368 {"dld.b", OP_REG(0x340) | D(1), (MASK_REG & ~M_REG(1)) | D(1), FMT_REG, {REG_SCALED, REG_BASE_M_LI, REG_DEST} },
370 {"dld.h", OP_LI(0x343) | D(1), (MASK_LI & ~M_REG(1)) | D(1), FMT_LI, {LSI_SCALED, REG_BASE_M_LI, REG_DEST} },
371 {"dld.h", OP_REG(0x342) | D(1), (MASK_REG & ~M_REG(1)) | D(1), FMT_REG, {REG_SCALED, REG_BASE_M_LI, REG_DEST} },
373 {"dld", OP_LI(0x345) | D(1), (MASK_LI & ~M_REG(1)) | D(1), FMT_LI, {LSI_SCALED, REG_BASE_M_LI, REG_DEST} },
374 {"dld", OP_REG(0x344) | D(1), (MASK_REG & ~M_REG(1)) | D(1), FMT_REG, {REG_SCALED, REG_BASE_M_LI, REG_DEST} },
376 {"dld.d", OP_LI(0x347) | D(1), (MASK_LI & ~M_REG(1)) | D(1), FMT_LI, {LSI_SCALED, REG_BASE_M_LI, REG_DEST} },
377 {"dld.d", OP_REG(0x346) | D(1), (MASK_REG & ~M_REG(1)) | D(1), FMT_REG, {REG_SCALED, REG_BASE_M_LI, REG_DEST} },
379 /* Direct load unsigned data into register */
381 {"dld.ub", OP_LI(0x351) | D(1), (MASK_LI & ~M_REG(1)) | D(1), FMT_LI, {LSI_SCALED, REG_BASE_M_LI, REG_DEST} },
382 {"dld.ub", OP_REG(0x350) | D(1), (MASK_REG & ~M_REG(1)) | D(1), FMT_REG, {REG_SCALED, REG_BASE_M_LI, REG_DEST} },
384 {"dld.uh", OP_LI(0x353) | D(1), (MASK_LI & ~M_REG(1)) | D(1), FMT_LI, {LSI_SCALED, REG_BASE_M_LI, REG_DEST} },
385 {"dld.uh", OP_REG(0x352) | D(1), (MASK_REG & ~M_REG(1)) | D(1), FMT_REG, {REG_SCALED, REG_BASE_M_LI, REG_DEST} },
387 /* Direct store data into memory */
389 {"dst.b", OP_LI(0x361) | D(1), (MASK_LI & ~M_REG(1)) | D(1), FMT_LI, {LSI_SCALED, REG_BASE_M_LI, REG_DEST} },
390 {"dst.b", OP_REG(0x360) | D(1), (MASK_REG & ~M_REG(1)) | D(1), FMT_REG, {REG_SCALED, REG_BASE_M_LI, REG_DEST} },
392 {"dst.h", OP_LI(0x363) | D(1), (MASK_LI & ~M_REG(1)) | D(1), FMT_LI, {LSI_SCALED, REG_BASE_M_LI, REG_DEST} },
393 {"dst.h", OP_REG(0x362) | D(1), (MASK_REG & ~M_REG(1)) | D(1), FMT_REG, {REG_SCALED, REG_BASE_M_LI, REG_DEST} },
395 {"dst", OP_LI(0x365) | D(1), (MASK_LI & ~M_REG(1)) | D(1), FMT_LI, {LSI_SCALED, REG_BASE_M_LI, REG_DEST} },
396 {"dst", OP_REG(0x364) | D(1), (MASK_REG & ~M_REG(1)) | D(1), FMT_REG, {REG_SCALED, REG_BASE_M_LI, REG_DEST} },
398 {"dst.d", OP_LI(0x367) | D(1), (MASK_LI & ~M_REG(1)) | D(1), FMT_LI, {LSI_SCALED, REG_BASE_M_LI, REG_DEST} },
399 {"dst.d", OP_REG(0x366) | D(1), (MASK_REG & ~M_REG(1)) | D(1), FMT_REG, {REG_SCALED, REG_BASE_M_LI, REG_DEST} },
403 {"estop", OP_LI(0x3FC), MASK_LI, FMT_LI, {0} },
407 {"etrap", OP_SI(0x1) | E(1), MASK_SI | E(1), FMT_SI, {SUI} },
408 {"etrap", OP_LI(0x303) | E(1), MASK_LI | E(1), FMT_LI, {LUI} },
409 {"etrap", OP_REG(0x302) | E(1), MASK_REG | E(1), FMT_REG, {REG_0} },
411 /* Extract signed field (actually an sr.ds instruction) */
413 {"exts", OP_SI(0xA) | i(0) | n(1), MASK_SI | i(1) | n(1), FMT_SI, {ROTATE, ENDMASK, REG_22, REG_DEST} },
414 {"exts", OP_REG(0x314) | i(0) | n(1), MASK_REG | i(1) | n(1), FMT_REG, {REG_0, ENDMASK, REG_22, REG_DEST} },
416 /* Extract unsigned field (actually an sr.dz instruction */
418 {"extu", OP_SI(0x8) | i(0) | n(1), MASK_SI | i(1) | n(1), FMT_SI, {ROTATE, ENDMASK, REG_22, REG_DEST} },
419 {"extu", OP_REG(0x310) | i(0) | n(1), MASK_REG | i(1) | n(1), FMT_REG, {REG_0, ENDMASK, REG_22, REG_DEST} },
421 /* Floating-point addition */
423 {"fadd.sss", OP_LI(0x3E1) | PD(0) | P2(0) | P1(0), MASK_LI | PD(3) | P2(3) | P1(3), FMT_LI, {SPFI, REG_22, REG_DEST} },
424 {"fadd.ssd", OP_LI(0x3E1) | PD(1) | P2(0) | P1(0), MASK_LI | PD(3) | P2(3) | P1(3), FMT_LI, {SPFI, REG_22, REG_DEST} },
425 {"fadd.sdd", OP_LI(0x3E1) | PD(1) | P2(1) | P1(0), MASK_LI | PD(3) | P2(3) | P1(3), FMT_LI, {SPFI, REG_22, REG_DEST} },
426 {"fadd.dsd", OP_LI(0x3E1) | PD(1) | P2(0) | P1(1), MASK_LI | PD(3) | P2(3) | P1(3), FMT_LI, {SPFI, REG_22, REG_DEST} },
427 {"fadd.ddd", OP_LI(0x3E1) | PD(1) | P2(1) | P1(1), MASK_LI | PD(3) | P2(3) | P1(3), FMT_LI, {SPFI, REG_22, REG_DEST} },
429 {"fadd.sss", OP_REG(0x3E0) | PD(0) | P2(0) | P1(0), MASK_REG | PD(3) | P2(3) | P1(3), FMT_REG, {REG_0, REG_22, REG_DEST} },
430 {"fadd.ssd", OP_REG(0x3E0) | PD(1) | P2(0) | P1(0), MASK_REG | PD(3) | P2(3) | P1(3), FMT_REG, {REG_0, REG_22, REG_DEST} },
431 {"fadd.sdd", OP_REG(0x3E0) | PD(1) | P2(1) | P1(0), MASK_REG | PD(3) | P2(3) | P1(3), FMT_REG, {REG_0, REG_22, REG_DEST} },
432 {"fadd.dsd", OP_REG(0x3E0) | PD(1) | P2(0) | P1(1), MASK_REG | PD(3) | P2(3) | P1(3), FMT_REG, {REG_0, REG_22, REG_DEST} },
433 {"fadd.ddd", OP_REG(0x3E0) | PD(1) | P2(1) | P1(1), MASK_REG | PD(3) | P2(3) | P1(3), FMT_REG, {REG_0, REG_22, REG_DEST} },
435 /* Floating point compare */
437 {"fcmp.ss", OP_LI(0x3EB) | PD(0) | P2(0) | P1(0), MASK_LI | PD(3) | P2(3) | P1(3), FMT_REG, {SPFI, REG_22, REG_DEST} },
438 {"fcmp.sd", OP_LI(0x3EB) | PD(0) | P2(1) | P1(0), MASK_LI | PD(3) | P2(3) | P1(3), FMT_REG, {SPFI, REG_22, REG_DEST} },
439 {"fcmp.ds", OP_LI(0x3EB) | PD(0) | P2(0) | P1(1), MASK_LI | PD(3) | P2(3) | P1(3), FMT_REG, {SPFI, REG_22, REG_DEST} },
440 {"fcmp.dd", OP_LI(0x3EB) | PD(0) | P2(1) | P1(1), MASK_LI | PD(3) | P2(3) | P1(3), FMT_REG, {SPFI, REG_22, REG_DEST} },
442 {"fcmp.ss", OP_REG(0x3EA) | PD(0) | P2(0) | P1(0), MASK_REG | PD(3) | P2(3) | P1(3), FMT_REG, {REG_0, REG_22, REG_DEST} },
443 {"fcmp.sd", OP_REG(0x3EA) | PD(0) | P2(1) | P1(0), MASK_REG | PD(3) | P2(3) | P1(3), FMT_REG, {REG_0, REG_22, REG_DEST} },
444 {"fcmp.ds", OP_REG(0x3EA) | PD(0) | P2(0) | P1(1), MASK_REG | PD(3) | P2(3) | P1(3), FMT_REG, {REG_0, REG_22, REG_DEST} },
445 {"fcmp.dd", OP_REG(0x3EA) | PD(0) | P2(1) | P1(1), MASK_REG | PD(3) | P2(3) | P1(3), FMT_REG, {REG_0, REG_22, REG_DEST} },
447 /* Floating point divide */
449 {"fdiv.sss", OP_LI(0x3E7) | PD(0) | P2(0) | P1(0), MASK_LI | PD(3) | P2(3) | P1(3), FMT_LI, {SPFI, REG_22, REG_DEST} },
450 {"fdiv.ssd", OP_LI(0x3E7) | PD(1) | P2(0) | P1(0), MASK_LI | PD(3) | P2(3) | P1(3), FMT_LI, {SPFI, REG_22, REG_DEST} },
451 {"fdiv.sdd", OP_LI(0x3E7) | PD(1) | P2(1) | P1(0), MASK_LI | PD(3) | P2(3) | P1(3), FMT_LI, {SPFI, REG_22, REG_DEST} },
452 {"fdiv.dsd", OP_LI(0x3E7) | PD(1) | P2(0) | P1(1), MASK_LI | PD(3) | P2(3) | P1(3), FMT_LI, {SPFI, REG_22, REG_DEST} },
453 {"fdiv.ddd", OP_LI(0x3E7) | PD(1) | P2(1) | P1(1), MASK_LI | PD(3) | P2(3) | P1(3), FMT_LI, {SPFI, REG_22, REG_DEST} },
455 {"fdiv.sss", OP_REG(0x3E6) | PD(0) | P2(0) | P1(0), MASK_REG | PD(3) | P2(3) | P1(3), FMT_REG, {REG_0, REG_22, REG_DEST} },
456 {"fdiv.ssd", OP_REG(0x3E6) | PD(1) | P2(0) | P1(0), MASK_REG | PD(3) | P2(3) | P1(3), FMT_REG, {REG_0, REG_22, REG_DEST} },
457 {"fdiv.sdd", OP_REG(0x3E6) | PD(1) | P2(1) | P1(0), MASK_REG | PD(3) | P2(3) | P1(3), FMT_REG, {REG_0, REG_22, REG_DEST} },
458 {"fdiv.dsd", OP_REG(0x3E6) | PD(1) | P2(0) | P1(1), MASK_REG | PD(3) | P2(3) | P1(3), FMT_REG, {REG_0, REG_22, REG_DEST} },
459 {"fdiv.ddd", OP_REG(0x3E6) | PD(1) | P2(1) | P1(1), MASK_REG | PD(3) | P2(3) | P1(3), FMT_REG, {REG_0, REG_22, REG_DEST} },
461 /* WORK IN PROGRESS BELOW THIS POINT */
463 {"illop0", OP_SI(0), MASK_SI, FMT_SI, FIXME},
465 {"ld", OP_LI(0x345), MASK_LI & ~M_LI(1), FMT_LI, FIXME},
466 {"ld", OP_REG(0x344), MASK_REG & ~M_REG(1), FMT_REG, FIXME},
467 {"ld", OP_SI(0x22), MASK_SI & ~M_SI(1), FMT_SI, FIXME},
468 {"ld.b", OP_LI(0x341), MASK_LI & ~M_LI(1), FMT_LI, FIXME},
469 {"ld.b", OP_REG(0x340), MASK_REG & ~M_REG(1), FMT_REG, FIXME},
470 {"ld.b", OP_SI(0x20), MASK_SI & ~M_SI(1), FMT_SI, FIXME},
471 {"ld.d", OP_LI(0x347), MASK_LI & ~M_LI(1), FMT_LI, FIXME},
472 {"ld.d", OP_REG(0x346), MASK_REG & ~M_REG(1), FMT_REG, FIXME},
473 {"ld.d", OP_SI(0x23), MASK_SI & ~M_SI(1), FMT_SI, FIXME},
474 {"ld.h", OP_LI(0x343), MASK_LI & ~M_LI(1), FMT_LI, FIXME},
475 {"ld.h", OP_REG(0x342), MASK_REG & ~M_REG(1), FMT_REG, FIXME},
476 {"ld.h", OP_SI(0x21), MASK_SI & ~M_SI(1), FMT_SI, FIXME},
477 {"ld.u", OP_LI(0x355), MASK_LI & ~M_LI(1), FMT_LI, FIXME},
478 {"ld.u", OP_REG(0x354), MASK_REG & ~M_REG(1), FMT_REG, FIXME},
479 {"ld.u", OP_SI(0x2A), MASK_SI & ~M_SI(1), FMT_SI, FIXME},
480 {"ld.ub", OP_LI(0x351), MASK_LI & ~M_LI(1), FMT_LI, FIXME},
481 {"ld.ub", OP_REG(0x350), MASK_REG & ~M_REG(1), FMT_REG, FIXME},
482 {"ld.ub", OP_SI(0x28), MASK_SI & ~M_SI(1), FMT_SI, FIXME},
483 {"ld.ud", OP_LI(0x357), MASK_LI & ~M_LI(1), FMT_LI, FIXME},
484 {"ld.ud", OP_REG(0x356), MASK_REG & ~M_REG(1), FMT_REG, FIXME},
485 {"ld.ud", OP_SI(0x2B), MASK_SI & ~M_SI(1), FMT_SI, FIXME},
486 {"ld.uh", OP_LI(0x353), MASK_LI & ~M_LI(1), FMT_LI, FIXME},
487 {"ld.uh", OP_REG(0x352), MASK_REG & ~M_REG(1), FMT_REG, FIXME},
488 {"ld.uh", OP_SI(0x29), MASK_SI & ~M_SI(1), FMT_SI, FIXME},
489 {"or.ff", OP_LI(0x33D), MASK_LI, FMT_LI, FIXME},
490 {"or.ff", OP_REG(0x33C), MASK_REG, FMT_REG, FIXME},
491 {"or.ff", OP_SI(0x1E), MASK_SI, FMT_SI, FIXME},
492 {"or.ft", OP_LI(0x33B), MASK_LI, FMT_LI, FIXME},
493 {"or.ft", OP_REG(0x33A), MASK_REG, FMT_REG, FIXME},
494 {"or.ft", OP_SI(0x1D), MASK_SI, FMT_SI, FIXME},
495 {"or.tf", OP_LI(0x337), MASK_LI, FMT_LI, FIXME},
496 {"or.tf", OP_REG(0x336), MASK_REG, FMT_REG, FIXME},
497 {"or.tf", OP_SI(0x1B), MASK_SI, FMT_SI, FIXME},
498 {"or.tt", OP_LI(0x32F), MASK_LI, FMT_LI, FIXME},
499 {"or.tt", OP_REG(0x32E), MASK_REG, FMT_REG, FIXME},
500 {"or.tt", OP_SI(0x17), MASK_SI, FMT_SI, FIXME},
501 {"rdcr", OP_LI(0x309), MASK_LI, FMT_LI, FIXME},
502 {"rdcr", OP_REG(0x308), MASK_REG, FMT_REG, FIXME},
503 {"rdcr", OP_SI(0x4), MASK_SI, FMT_SI, FIXME},
504 {"shift.dm", OP_REG(0x312), MASK_REG, FMT_REG, FIXME},
505 {"shift.dm", OP_SI(0x9), MASK_SI, FMT_SI, FIXME},
506 {"shift.ds", OP_REG(0x314), MASK_REG, FMT_REG, FIXME},
507 {"shift.ds", OP_SI(0xA), MASK_SI, FMT_SI, FIXME},
508 {"shift.dz", OP_REG(0x310), MASK_REG, FMT_REG, FIXME},
509 {"shift.dz", OP_SI(0x8), MASK_SI, FMT_SI, FIXME},
510 {"shift.em", OP_REG(0x318), MASK_REG, FMT_REG, FIXME},
511 {"shift.em", OP_SI(0xC), MASK_SI, FMT_SI, FIXME},
512 {"shift.es", OP_REG(0x31A), MASK_REG, FMT_REG, FIXME},
513 {"shift.es", OP_SI(0xD), MASK_SI, FMT_SI, FIXME},
514 {"shift.ez", OP_REG(0x316), MASK_REG, FMT_REG, FIXME},
515 {"shift.ez", OP_SI(0xB), MASK_SI, FMT_SI, FIXME},
516 {"shift.im", OP_REG(0x31E), MASK_REG, FMT_REG, FIXME},
517 {"shift.im", OP_SI(0xF), MASK_SI, FMT_SI, FIXME},
518 {"shift.iz", OP_REG(0x31C), MASK_REG, FMT_REG, FIXME},
519 {"shift.iz", OP_SI(0xE), MASK_SI, FMT_SI, FIXME},
520 {"st", OP_LI(0x365), MASK_LI & ~M_LI(1), FMT_LI, FIXME},
521 {"st", OP_REG(0x364), MASK_REG & ~M_REG(1), FMT_REG, FIXME},
522 {"st", OP_SI(0x32), MASK_SI & ~M_SI(1), FMT_SI, FIXME},
523 {"st.b", OP_LI(0x361), MASK_LI & ~M_LI(1), FMT_LI, FIXME},
524 {"st.b", OP_REG(0x360), MASK_REG & ~M_REG(1), FMT_REG, FIXME},
525 {"st.b", OP_SI(0x30), MASK_SI & ~M_SI(1), FMT_SI, FIXME},
526 {"st.d", OP_LI(0x367), MASK_LI & ~M_LI(1), FMT_LI, FIXME},
527 {"st.d", OP_REG(0x366), MASK_REG & ~M_REG(1), FMT_REG, FIXME},
528 {"st.d", OP_SI(0x33), MASK_SI & ~M_SI(1), FMT_SI, FIXME},
529 {"st.h", OP_LI(0x363), MASK_LI & ~M_LI(1), FMT_LI, FIXME},
530 {"st.h", OP_REG(0x362), MASK_REG & ~M_REG(1), FMT_REG, FIXME},
531 {"st.h", OP_SI(0x31), MASK_SI & ~M_SI(1), FMT_SI, FIXME},
532 {"swcr", OP_LI(0x30B), MASK_LI, FMT_LI, FIXME},
533 {"swcr", OP_REG(0x30A), MASK_REG, FMT_REG, FIXME},
534 {"swcr", OP_SI(0x5), MASK_SI, FMT_SI, FIXME},
535 {"trap", OP_LI(0x303), MASK_LI, FMT_LI, FIXME},
536 {"trap", OP_REG(0x302), MASK_REG, FMT_REG, FIXME},
537 {"trap", OP_SI(0x1), MASK_SI, FMT_SI, FIXME},
538 {"xnor", OP_LI(0x333), MASK_LI, FMT_LI, FIXME},
539 {"xnor", OP_REG(0x332), MASK_REG, FMT_REG, FIXME},
540 {"xnor", OP_SI(0x19), MASK_SI, FMT_SI, FIXME},
541 {"xor", OP_LI(0x32D), MASK_LI, FMT_LI, FIXME},
542 {"xor", OP_REG(0x32C), MASK_REG, FMT_REG, FIXME},
543 {"xor", OP_SI(0x16), MASK_SI, FMT_SI, FIXME},
547 const int tic80_num_opcodes = sizeof (tic80_opcodes) / sizeof (tic80_opcodes[0]);