1 /* Disassembly routines for TMS320C30 architecture
2 Copyright 1998, 1999, 2000, 2002, 2005, 2007 Free Software Foundation, Inc.
3 Contributed by Steven Haworth (steve@pm.cse.rmit.edu.au)
5 This file is part of the GNU opcodes library.
7 This library is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 3, or (at your option)
12 It is distributed in the hope that it will be useful, but WITHOUT
13 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
14 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
15 License for more details.
17 You should have received a copy of the GNU General Public License
18 along with this file; see the file COPYING. If not, write to the
19 Free Software Foundation, 51 Franklin Street - Fifth Floor, Boston,
20 MA 02110-1301, USA. */
26 #include "opcode/tic30.h"
29 #define PARALLEL_INSN 2
31 /* Gets the type of instruction based on the top 2 or 3 bits of the
33 #define GET_TYPE(insn) (insn & 0x80000000 ? insn & 0xC0000000 : insn & 0xE0000000)
35 /* Instruction types. */
36 #define TWO_OPERAND_1 0x00000000
37 #define TWO_OPERAND_2 0x40000000
38 #define THREE_OPERAND 0x20000000
39 #define PAR_STORE 0xC0000000
40 #define MUL_ADDS 0x80000000
41 #define BRANCHES 0x60000000
43 /* Specific instruction id bits. */
44 #define NORMAL_IDEN 0x1F800000
45 #define PAR_STORE_IDEN 0x3E000000
46 #define MUL_ADD_IDEN 0x2C000000
47 #define BR_IMM_IDEN 0x1F000000
48 #define BR_COND_IDEN 0x1C3F0000
50 /* Addressing modes. */
51 #define AM_REGISTER 0x00000000
52 #define AM_DIRECT 0x00200000
53 #define AM_INDIRECT 0x00400000
54 #define AM_IMM 0x00600000
56 #define P_FIELD 0x03000000
59 #define LDP_INSN 0x08700000
61 /* TMS320C30 program counter for current instruction. */
62 static unsigned int _pc;
72 get_tic30_instruction (unsigned long insn_word, struct instruction *insn)
74 switch (GET_TYPE (insn_word))
79 insn->type = NORMAL_INSN;
81 insn_template *current_optab = (insn_template *) tic30_optab;
83 for (; current_optab < tic30_optab_end; current_optab++)
85 if (GET_TYPE (current_optab->base_opcode) == GET_TYPE (insn_word))
87 if (current_optab->operands == 0)
89 if (current_optab->base_opcode == insn_word)
91 insn->tm = current_optab;
95 else if ((current_optab->base_opcode & NORMAL_IDEN) == (insn_word & NORMAL_IDEN))
97 insn->tm = current_optab;
106 insn->type = PARALLEL_INSN;
108 partemplate *current_optab = (partemplate *) tic30_paroptab;
110 for (; current_optab < tic30_paroptab_end; current_optab++)
112 if (GET_TYPE (current_optab->base_opcode) == GET_TYPE (insn_word))
114 if ((current_optab->base_opcode & PAR_STORE_IDEN)
115 == (insn_word & PAR_STORE_IDEN))
117 insn->ptm = current_optab;
126 insn->type = PARALLEL_INSN;
128 partemplate *current_optab = (partemplate *) tic30_paroptab;
130 for (; current_optab < tic30_paroptab_end; current_optab++)
132 if (GET_TYPE (current_optab->base_opcode) == GET_TYPE (insn_word))
134 if ((current_optab->base_opcode & MUL_ADD_IDEN)
135 == (insn_word & MUL_ADD_IDEN))
137 insn->ptm = current_optab;
146 insn->type = NORMAL_INSN;
148 insn_template *current_optab = (insn_template *) tic30_optab;
150 for (; current_optab < tic30_optab_end; current_optab++)
152 if (GET_TYPE (current_optab->base_opcode) == GET_TYPE (insn_word))
154 if (current_optab->operand_types[0] & Imm24)
156 if ((current_optab->base_opcode & BR_IMM_IDEN)
157 == (insn_word & BR_IMM_IDEN))
159 insn->tm = current_optab;
163 else if (current_optab->operands > 0)
165 if ((current_optab->base_opcode & BR_COND_IDEN)
166 == (insn_word & BR_COND_IDEN))
168 insn->tm = current_optab;
174 if ((current_optab->base_opcode & (BR_COND_IDEN | 0x00800000))
175 == (insn_word & (BR_COND_IDEN | 0x00800000)))
177 insn->tm = current_optab;
192 get_register_operand (unsigned char fragment, char *buffer)
194 const reg *current_reg = tic30_regtab;
198 for (; current_reg < tic30_regtab_end; current_reg++)
200 if ((fragment & 0x1F) == current_reg->opcode)
202 strcpy (buffer, current_reg->name);
210 get_indirect_operand (unsigned short fragment,
220 /* Determine which bits identify the sections of the indirect
221 operand based on the size in bytes. */
225 mod = (fragment & 0x00F8) >> 3;
226 arnum = (fragment & 0x0007);
230 mod = (fragment & 0xF800) >> 11;
231 arnum = (fragment & 0x0700) >> 8;
232 disp = (fragment & 0x00FF);
238 const ind_addr_type *current_ind = tic30_indaddr_tab;
240 for (; current_ind < tic30_indaddrtab_end; current_ind++)
242 if (current_ind->modfield == mod)
244 if (current_ind->displacement == IMPLIED_DISP && size == 2)
252 len = strlen (current_ind->syntax);
253 for (i = 0, bufcnt = 0; i < len; i++, bufcnt++)
255 buffer[bufcnt] = current_ind->syntax[i];
256 if (buffer[bufcnt - 1] == 'a' && buffer[bufcnt] == 'r')
257 buffer[++bufcnt] = arnum + '0';
258 if (buffer[bufcnt] == '('
259 && current_ind->displacement == DISP_REQUIRED)
261 sprintf (&buffer[bufcnt + 1], "%u", disp);
262 bufcnt += strlen (&buffer[bufcnt + 1]);
265 buffer[bufcnt + 1] = '\0';
275 cnvt_tmsfloat_ieee (unsigned long tmsfloat, int size, float *ieeefloat)
277 unsigned long exp, sign, mant;
286 if ((tmsfloat & 0x0000F000) == 0x00008000)
287 tmsfloat = 0x80000000;
291 tmsfloat = (long) tmsfloat >> 4;
294 exp = tmsfloat & 0xFF000000;
295 if (exp == 0x80000000)
301 sign = (tmsfloat & 0x00800000) << 8;
302 mant = tmsfloat & 0x007FFFFF;
303 if (exp == 0xFF000000)
309 *ieeefloat = HUGE_VALF;
311 *ieeefloat = -HUGE_VALF;
314 *ieeefloat = 1.0 / 0.0;
316 *ieeefloat = -1.0 / 0.0;
323 mant = (~mant) & 0x007FFFFF;
325 exp += mant & 0x00800000;
329 if (tmsfloat == 0x80000000)
330 sign = mant = exp = 0;
331 tmsfloat = sign | exp | mant;
338 print_two_operand (disassemble_info *info,
339 unsigned long insn_word,
340 struct instruction *insn)
343 char operand[2][13] =
350 if (insn->tm == NULL)
352 strcpy (name, insn->tm->name);
353 if (insn->tm->opcode_modifier == AddressMode)
356 /* Determine whether instruction is a store or a normal instruction. */
357 if ((insn->tm->operand_types[1] & (Direct | Indirect))
358 == (Direct | Indirect))
368 /* Get the destination register. */
369 if (insn->tm->operands == 2)
370 get_register_operand ((insn_word & 0x001F0000) >> 16, operand[dest_op]);
371 /* Get the source operand based on addressing mode. */
372 switch (insn_word & AddressMode)
375 /* Check for the NOP instruction before getting the operand. */
376 if ((insn->tm->operand_types[0] & NotReq) == 0)
377 get_register_operand ((insn_word & 0x0000001F), operand[src_op]);
380 sprintf (operand[src_op], "@0x%lX", (insn_word & 0x0000FFFF));
383 get_indirect_operand ((insn_word & 0x0000FFFF), 2, operand[src_op]);
386 /* Get the value of the immediate operand based on variable type. */
387 switch (insn->tm->imm_arg_type)
390 cnvt_tmsfloat_ieee ((insn_word & 0x0000FFFF), 2, &f_number);
391 sprintf (operand[src_op], "%2.2f", f_number);
394 sprintf (operand[src_op], "%d", (short) (insn_word & 0x0000FFFF));
397 sprintf (operand[src_op], "%lu", (insn_word & 0x0000FFFF));
402 /* Handle special case for LDP instruction. */
403 if ((insn_word & 0xFFFFFF00) == LDP_INSN)
405 strcpy (name, "ldp");
406 sprintf (operand[0], "0x%06lX", (insn_word & 0x000000FF) << 16);
407 operand[1][0] = '\0';
411 /* Handle case for stack and rotate instructions. */
412 else if (insn->tm->operands == 1)
414 if (insn->tm->opcode_modifier == StackOp)
415 get_register_operand ((insn_word & 0x001F0000) >> 16, operand[0]);
417 /* Output instruction to stream. */
418 info->fprintf_func (info->stream, " %s %s%c%s", name,
419 operand[0][0] ? operand[0] : "",
420 operand[1][0] ? ',' : ' ',
421 operand[1][0] ? operand[1] : "");
426 print_three_operand (disassemble_info *info,
427 unsigned long insn_word,
428 struct instruction *insn)
430 char operand[3][13] =
437 if (insn->tm == NULL)
439 switch (insn_word & AddressMode)
442 get_register_operand ((insn_word & 0x000000FF), operand[0]);
443 get_register_operand ((insn_word & 0x0000FF00) >> 8, operand[1]);
446 get_register_operand ((insn_word & 0x000000FF), operand[0]);
447 get_indirect_operand ((insn_word & 0x0000FF00) >> 8, 1, operand[1]);
450 get_indirect_operand ((insn_word & 0x000000FF), 1, operand[0]);
451 get_register_operand ((insn_word & 0x0000FF00) >> 8, operand[1]);
454 get_indirect_operand ((insn_word & 0x000000FF), 1, operand[0]);
455 get_indirect_operand ((insn_word & 0x0000FF00) >> 8, 1, operand[1]);
460 if (insn->tm->operands == 3)
461 get_register_operand ((insn_word & 0x001F0000) >> 16, operand[2]);
462 info->fprintf_func (info->stream, " %s %s,%s%c%s", insn->tm->name,
463 operand[0], operand[1],
464 operand[2][0] ? ',' : ' ',
465 operand[2][0] ? operand[2] : "");
470 print_par_insn (disassemble_info *info,
471 unsigned long insn_word,
472 struct instruction *insn)
476 char operand[2][3][13] =
490 if (insn->ptm == NULL)
492 /* Parse out the names of each of the parallel instructions from the
493 q_insn1_insn2 format. */
494 name1 = (char *) strdup (insn->ptm->name + 2);
496 len = strlen (name1);
497 for (i = 0; i < len; i++)
501 name2 = &name1[i + 1];
506 /* Get the operands of the instruction based on the operand order. */
507 switch (insn->ptm->oporder)
510 get_indirect_operand ((insn_word & 0x000000FF), 1, operand[0][0]);
511 get_indirect_operand ((insn_word & 0x0000FF00) >> 8, 1, operand[1][1]);
512 get_register_operand ((insn_word >> 16) & 0x07, operand[1][0]);
513 get_register_operand ((insn_word >> 22) & 0x07, operand[0][1]);
516 get_indirect_operand ((insn_word & 0x000000FF), 1, operand[0][0]);
517 get_indirect_operand ((insn_word & 0x0000FF00) >> 8, 1, operand[1][0]);
518 get_register_operand ((insn_word >> 19) & 0x07, operand[1][1]);
519 get_register_operand ((insn_word >> 22) & 0x07, operand[0][1]);
522 get_indirect_operand ((insn_word & 0x000000FF), 1, operand[0][1]);
523 get_indirect_operand ((insn_word & 0x0000FF00) >> 8, 1, operand[1][1]);
524 get_register_operand ((insn_word >> 16) & 0x07, operand[1][0]);
525 get_register_operand ((insn_word >> 22) & 0x07, operand[0][0]);
528 get_indirect_operand ((insn_word & 0x000000FF), 1, operand[0][0]);
529 get_indirect_operand ((insn_word & 0x0000FF00) >> 8, 1, operand[1][1]);
530 get_register_operand ((insn_word >> 16) & 0x07, operand[1][0]);
531 get_register_operand ((insn_word >> 19) & 0x07, operand[0][1]);
532 get_register_operand ((insn_word >> 22) & 0x07, operand[0][2]);
535 get_indirect_operand ((insn_word & 0x000000FF), 1, operand[0][1]);
536 get_indirect_operand ((insn_word & 0x0000FF00) >> 8, 1, operand[1][1]);
537 get_register_operand ((insn_word >> 16) & 0x07, operand[1][0]);
538 get_register_operand ((insn_word >> 19) & 0x07, operand[0][0]);
539 get_register_operand ((insn_word >> 22) & 0x07, operand[0][2]);
542 if (insn_word & 0x00800000)
543 get_register_operand (0x01, operand[0][2]);
545 get_register_operand (0x00, operand[0][2]);
546 if (insn_word & 0x00400000)
547 get_register_operand (0x03, operand[1][2]);
549 get_register_operand (0x02, operand[1][2]);
550 switch (insn_word & P_FIELD)
553 get_indirect_operand ((insn_word & 0x000000FF), 1, operand[0][1]);
554 get_indirect_operand ((insn_word & 0x0000FF00) >> 8, 1, operand[0][0]);
555 get_register_operand ((insn_word >> 16) & 0x07, operand[1][1]);
556 get_register_operand ((insn_word >> 19) & 0x07, operand[1][0]);
559 get_indirect_operand ((insn_word & 0x000000FF), 1, operand[1][0]);
560 get_indirect_operand ((insn_word & 0x0000FF00) >> 8, 1, operand[0][0]);
561 get_register_operand ((insn_word >> 16) & 0x07, operand[1][1]);
562 get_register_operand ((insn_word >> 19) & 0x07, operand[0][1]);
565 get_indirect_operand ((insn_word & 0x000000FF), 1, operand[1][1]);
566 get_indirect_operand ((insn_word & 0x0000FF00) >> 8, 1, operand[1][0]);
567 get_register_operand ((insn_word >> 16) & 0x07, operand[0][1]);
568 get_register_operand ((insn_word >> 19) & 0x07, operand[0][0]);
571 get_indirect_operand ((insn_word & 0x000000FF), 1, operand[1][1]);
572 get_indirect_operand ((insn_word & 0x0000FF00) >> 8, 1, operand[0][0]);
573 get_register_operand ((insn_word >> 16) & 0x07, operand[1][0]);
574 get_register_operand ((insn_word >> 19) & 0x07, operand[0][1]);
581 info->fprintf_func (info->stream, " %s %s,%s%c%s", name1,
582 operand[0][0], operand[0][1],
583 operand[0][2][0] ? ',' : ' ',
584 operand[0][2][0] ? operand[0][2] : "");
585 info->fprintf_func (info->stream, "\n\t\t\t|| %s %s,%s%c%s", name2,
586 operand[1][0], operand[1][1],
587 operand[1][2][0] ? ',' : ' ',
588 operand[1][2][0] ? operand[1][2] : "");
594 print_branch (disassemble_info *info,
595 unsigned long insn_word,
596 struct instruction *insn)
598 char operand[2][13] =
603 unsigned long address;
606 if (insn->tm == NULL)
608 /* Get the operands for 24-bit immediate jumps. */
609 if (insn->tm->operand_types[0] & Imm24)
611 address = insn_word & 0x00FFFFFF;
612 sprintf (operand[0], "0x%lX", address);
615 /* Get the operand for the trap instruction. */
616 else if (insn->tm->operand_types[0] & IVector)
618 address = insn_word & 0x0000001F;
619 sprintf (operand[0], "0x%lX", address);
623 address = insn_word & 0x0000FFFF;
624 /* Get the operands for the DB instructions. */
625 if (insn->tm->operands == 2)
627 get_register_operand (((insn_word & 0x01C00000) >> 22) + REG_AR0, operand[0]);
628 if (insn_word & PCRel)
630 sprintf (operand[1], "%d", (short) address);
634 get_register_operand (insn_word & 0x0000001F, operand[1]);
636 /* Get the operands for the standard branches. */
637 else if (insn->tm->operands == 1)
639 if (insn_word & PCRel)
641 address = (short) address;
642 sprintf (operand[0], "%ld", address);
646 get_register_operand (insn_word & 0x0000001F, operand[0]);
649 info->fprintf_func (info->stream, " %s %s%c%s", insn->tm->name,
650 operand[0][0] ? operand[0] : "",
651 operand[1][0] ? ',' : ' ',
652 operand[1][0] ? operand[1] : "");
653 /* Print destination of branch in relation to current symbol. */
654 if (print_label && info->symbols)
656 asymbol *sym = *info->symbols;
658 if ((insn->tm->opcode_modifier == PCRel) && (insn_word & PCRel))
660 address = (_pc + 1 + (short) address) - ((sym->section->vma + sym->value) / 4);
661 /* Check for delayed instruction, if so adjust destination. */
662 if (insn_word & 0x00200000)
667 address -= ((sym->section->vma + sym->value) / 4);
670 info->fprintf_func (info->stream, " <%s>", sym->name);
672 info->fprintf_func (info->stream, " <%s %c %d>", sym->name,
673 ((short) address < 0) ? '-' : '+',
680 print_insn_tic30 (bfd_vma pc, disassemble_info *info)
682 unsigned long insn_word;
683 struct instruction insn = { 0, NULL, NULL };
684 bfd_vma bufaddr = pc - info->buffer_vma;
686 /* Obtain the current instruction word from the buffer. */
687 insn_word = (*(info->buffer + bufaddr) << 24) | (*(info->buffer + bufaddr + 1) << 16) |
688 (*(info->buffer + bufaddr + 2) << 8) | *(info->buffer + bufaddr + 3);
690 /* Get the instruction refered to by the current instruction word
691 and print it out based on its type. */
692 if (!get_tic30_instruction (insn_word, &insn))
694 switch (GET_TYPE (insn_word))
698 if (!print_two_operand (info, insn_word, &insn))
702 if (!print_three_operand (info, insn_word, &insn))
707 if (!print_par_insn (info, insn_word, &insn))
711 if (!print_branch (info, insn_word, &insn))