1 /* Print SPARC instructions.
2 Copyright 1989, 1991, 1992, 1993 Free Software Foundation, Inc.
4 This program is free software; you can redistribute it and/or modify
5 it under the terms of the GNU General Public License as published by
6 the Free Software Foundation; either version 2 of the License, or
7 (at your option) any later version.
9 This program is distributed in the hope that it will be useful,
10 but WITHOUT ANY WARRANTY; without even the implied warranty of
11 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 GNU General Public License for more details.
14 You should have received a copy of the GNU General Public License
15 along with this program; if not, write to the Free Software
16 Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. */
18 #include "opcode/sparc.h"
22 static char *reg_names[] =
23 { "g0", "g1", "g2", "g3", "g4", "g5", "g6", "g7",
24 "o0", "o1", "o2", "o3", "o4", "o5", "sp", "o7",
25 "l0", "l1", "l2", "l3", "l4", "l5", "l6", "l7",
26 "i0", "i1", "i2", "i3", "i4", "i5", "fp", "i7",
27 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
28 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
29 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
30 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31",
31 "y", "psr", "wim", "tbr", "pc", "npc", "fpsr", "cpsr" };
33 #define freg_names (®_names[4 * 8])
35 /* FIXME--need to deal with byte order (probably using masking and
36 shifting rather than bitfields is easiest). */
40 unsigned long int code;
49 #define rs1 ldst.anrs1
52 #define asi ldst.anasi
54 #define rs2 ldst.anrs2
59 unsigned int anop:2, anrd:5, op3:6, anrs1:5, i:1;
60 unsigned int IMM13:13;
61 #define imm13 IMM13.IMM13
69 unsigned int DISP22:22;
70 #define disp22 branch.DISP22
75 unsigned int _OP:2, _RD:5, op3:6, _RS1:5;
76 unsigned int DISP14:14;
77 #define disp14 DISP14.DISP14
86 unsigned int DISP21:21;
87 #define disp21 branch2.DISP21
95 unsigned int adisp30:30;
96 #define disp30 call.adisp30
100 /* Nonzero if INSN is the opcode for a delayed branch. */
102 is_delayed_branch (insn)
103 union sparc_insn insn;
107 for (i = 0; i < NUMOPCODES; ++i)
109 const struct sparc_opcode *opcode = &sparc_opcodes[i];
110 if ((opcode->match & insn.code) == opcode->match
111 && (opcode->lose & insn.code) == 0)
112 return (opcode->flags & F_DELAYED);
117 static int opcodes_sorted = 0;
118 extern void qsort ();
120 /* Print one instruction from MEMADDR on STREAM.
122 We suffix the instruction with a comment that gives the absolute
123 address involved, as well as its symbolic form, if the instruction
124 is preceded by a findable `sethi' and it either adds an immediate
125 displacement to that register, or it is an `add' or `or' instruction
128 print_insn_sparc (memaddr, info)
130 disassemble_info *info;
132 FILE *stream = info->stream;
133 union sparc_insn insn;
135 register unsigned int i;
139 static int compare_opcodes ();
140 qsort ((char *) sparc_opcodes, NUMOPCODES,
141 sizeof (sparc_opcodes[0]), compare_opcodes);
147 (*info->read_memory_func) (memaddr, (char *) &insn, sizeof (insn), info);
150 (*info->memory_error_func) (status, memaddr, info);
155 for (i = 0; i < NUMOPCODES; ++i)
157 const struct sparc_opcode *opcode = &sparc_opcodes[i];
158 if ((opcode->match & insn.code) == opcode->match
159 && (opcode->lose & insn.code) == 0)
161 /* Nonzero means that we have found an instruction which has
162 the effect of adding or or'ing the imm13 field to rs1. */
163 int imm_added_to_rs1 = 0;
165 /* Nonzero means that we have found a plus sign in the args
166 field of the opcode table. */
169 /* Do we have an `add' or `or' instruction where rs1 is the same
170 as rsd, and which has the i bit set? */
171 if ((opcode->match == 0x80102000 || opcode->match == 0x80002000)
173 && insn.rs1 == insn.rd)
174 imm_added_to_rs1 = 1;
176 if (insn.rs1 != insn.rd
177 && strchr (opcode->args, 'r') != 0)
178 /* Can't do simple format if source and dest are different. */
181 (*info->fprintf_func) (stream, opcode->name);
184 register const char *s;
186 if (opcode->args[0] != ',')
187 (*info->fprintf_func) (stream, " ");
188 for (s = opcode->args; *s != '\0'; ++s)
192 (*info->fprintf_func) (stream, ",");
196 (*info->fprintf_func) (stream, "a");
201 (*info->fprintf_func) (stream, "pn");
206 (*info->fprintf_func) (stream, "pt");
213 } /* switch on arg */
214 } /* while there are comma started args */
216 (*info->fprintf_func) (stream, " ");
223 /* note fall-through */
225 (*info->fprintf_func) (stream, "%c", *s);
229 (*info->fprintf_func) (stream, "0");
232 #define reg(n) (*info->fprintf_func) (stream, "%%%s", reg_names[n])
247 #define freg(n) (*info->fprintf_func) (stream, "%%%s", freg_names[n])
249 case 'v': /* double/even */
250 case 'V': /* quad/multiple of 4 */
255 case 'B': /* double/even */
256 case 'R': /* quad/multiple of 4 */
261 case 'H': /* double/even */
262 case 'J': /* quad/multiple of 4 */
267 #define creg(n) (*info->fprintf_func) (stream, "%%c%u", (unsigned int) (n))
282 (*info->fprintf_func) (stream, "%%hi(%#x)",
283 (int) insn.imm22 << 10);
288 /* We cannot trust the compiler to sign-extend
289 when extracting the bitfield, hence the shifts. */
290 int imm = ((int) insn.imm13 << 19) >> 19;
292 /* Check to see whether we have a 1+i, and take
295 Note: because of the way we sort the table,
296 we will be matching 1+i rather than i+1,
297 so it is OK to assume that i is after +,
300 imm_added_to_rs1 = 1;
303 (*info->fprintf_func) (stream, "%d", imm);
305 (*info->fprintf_func) (stream, "%#x", imm);
310 case 'I': /* 11 bit immediate. */
311 case 'j': /* 10 bit immediate. */
313 /* We cannot trust the compiler to sign-extend
314 when extracting the bitfield, hence the shifts. */
318 imm = ((int) insn.imm13 << 21) >> 21;
320 imm = ((int) insn.imm13 << 22) >> 22;
322 /* Check to see whether we have a 1+i, and take
325 Note: because of the way we sort the table,
326 we will be matching 1+i rather than i+1,
327 so it is OK to assume that i is after +,
330 imm_added_to_rs1 = 1;
333 (info->fprintf_func) (stream, "%d", imm);
335 (info->fprintf_func) (stream, "%#x", (unsigned) imm);
343 print_address ((bfd_vma)
345 + (((int) insn.disp14 << 18) >> 18) * 4),
350 print_address ((bfd_vma)
352 /* We use only 19 of the 21 bits. */
353 + (((int) insn.disp21 << 13) >> 13) * 4),
361 fprintf (stream, "fcc%c", *s - '6' + '0');
365 fputs ("icc", stream);
369 fputs ("xcc", stream);
373 fputs ("%ccr", stream);
377 fputs ("%fprs", stream);
382 fprintf(stream, "%%asr%d", insn.rs1);
386 fprintf(stream, "%%asr%d", insn.rd);
390 print_address ((bfd_vma) memaddr + insn.disp30 * 4,
395 if ((insn.code >> 22) == 0)
396 /* Special case for `unimp'. Don't try to turn
397 it's operand into a function offset. */
398 (*info->fprintf_func)
400 (int) (((int) insn.disp22 << 10) >> 10));
402 /* We cannot trust the compiler to sign-extend
403 when extracting the bitfield, hence the shifts. */
404 print_address ((bfd_vma)
406 + (((int) insn.disp22 << 10) >> 10) * 4),
411 (*info->fprintf_func) (stream, "(%d)", (int) insn.asi);
415 (*info->fprintf_func) (stream, "%csr");
419 (*info->fprintf_func) (stream, "%fsr");
423 (*info->fprintf_func) (stream, "%psr");
427 (*info->fprintf_func) (stream, "%fq");
431 (*info->fprintf_func) (stream, "%cq");
435 (*info->fprintf_func) (stream, "%tbr");
439 (*info->fprintf_func) (stream, "%wim");
443 (*info->fprintf_func) (stream, "%y");
449 /* If we are adding or or'ing something to rs1, then
450 check to see whether the previous instruction was
451 a sethi to the same register as in the sethi.
452 If so, attempt to print the result of the add or
453 or (in this context add and or do the same thing)
454 and its symbolic value. */
455 if (imm_added_to_rs1)
457 union sparc_insn prev_insn;
461 (*info->read_memory_func)
463 (char *)&prev_insn, sizeof (prev_insn), info);
467 /* If it is a delayed branch, we need to look at the
468 instruction before the delayed branch. This handles
471 sethi %o1, %hi(_foo), %o1
473 or %o1, %lo(_foo), %o1
476 if (is_delayed_branch (prev_insn))
477 errcode = (*info->read_memory_func)
478 (memaddr - 8, (char *)&prev_insn, sizeof (prev_insn),
482 /* If there was a problem reading memory, then assume
483 the previous instruction was not sethi. */
486 /* Is it sethi to the same register? */
487 if ((prev_insn.code & 0xc1c00000) == 0x01000000
488 && prev_insn.rd == insn.rs1)
490 (*info->fprintf_func) (stream, "\t! ");
491 /* We cannot trust the compiler to sign-extend
492 when extracting the bitfield, hence the shifts. */
493 print_address (((int) prev_insn.imm22 << 10)
494 | (insn.imm13 << 19) >> 19, stream);
499 return sizeof (insn);
503 (*info->fprintf_func) (stream, "%#8x", insn.code);
504 return sizeof (insn);
507 /* Compare opcodes A and B. */
510 compare_opcodes (a, b)
513 struct sparc_opcode *op0 = (struct sparc_opcode *) a;
514 struct sparc_opcode *op1 = (struct sparc_opcode *) b;
515 unsigned long int match0 = op0->match, match1 = op1->match;
516 unsigned long int lose0 = op0->lose, lose1 = op1->lose;
517 register unsigned int i;
519 /* If a bit is set in both match and lose, there is something
520 wrong with the opcode table. */
523 fprintf (stderr, "Internal error: bad sparc-opcode.h: \"%s\", %#.8lx, %#.8lx\n",
524 op0->name, match0, lose0);
525 op0->lose &= ~op0->match;
531 fprintf (stderr, "Internal error: bad sparc-opcode.h: \"%s\", %#.8lx, %#.8lx\n",
532 op1->name, match1, lose1);
533 op1->lose &= ~op1->match;
537 /* Because the bits that are variable in one opcode are constant in
538 another, it is important to order the opcodes in the right order. */
539 for (i = 0; i < 32; ++i)
541 unsigned long int x = 1 << i;
542 int x0 = (match0 & x) != 0;
543 int x1 = (match1 & x) != 0;
549 for (i = 0; i < 32; ++i)
551 unsigned long int x = 1 << i;
552 int x0 = (lose0 & x) != 0;
553 int x1 = (lose1 & x) != 0;
559 /* They are functionally equal. So as long as the opcode table is
560 valid, we can put whichever one first we want, on aesthetic grounds. */
562 /* Our first aesthetic ground is that aliases defer to real insns. */
564 int alias_diff = (op0->flags & F_ALIAS) - (op1->flags & F_ALIAS);
566 /* Put the one that isn't an alias first. */
570 /* Except for aliases, two "identical" instructions had
571 better have the same opcode. This is a sanity check on the table. */
572 i = strcmp (op0->name, op1->name);
574 if (op0->flags & F_ALIAS) /* If they're both aliases, be arbitrary. */
578 "Internal error: bad sparc-opcode.h: \"%s\" == \"%s\"\n",
579 op0->name, op1->name);
581 /* Fewer arguments are preferred. */
583 int length_diff = strlen (op0->args) - strlen (op1->args);
584 if (length_diff != 0)
585 /* Put the one with fewer arguments first. */
589 /* Put 1+i before i+1. */
591 char *p0 = (char *) strchr(op0->args, '+');
592 char *p1 = (char *) strchr(op1->args, '+');
596 /* There is a plus in both operands. Note that a plus
597 sign cannot be the first character in args,
598 so the following [-1]'s are valid. */
599 if (p0[-1] == 'i' && p1[1] == 'i')
600 /* op0 is i+1 and op1 is 1+i, so op1 goes first. */
602 if (p0[1] == 'i' && p1[-1] == 'i')
603 /* op0 is 1+i and op1 is i+1, so op0 goes first. */
608 /* They are, as far as we can tell, identical.
609 Since qsort may have rearranged the table partially, there is
610 no way to tell which one was first in the opcode table as
611 written, so just say there are equal. */