1 /* Print SPARC instructions.
2 Copyright 1989, 1991, 1992, 1993, 1995 Free Software Foundation, Inc.
4 This program is free software; you can redistribute it and/or modify
5 it under the terms of the GNU General Public License as published by
6 the Free Software Foundation; either version 2 of the License, or
7 (at your option) any later version.
9 This program is distributed in the hope that it will be useful,
10 but WITHOUT ANY WARRANTY; without even the implied warranty of
11 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 GNU General Public License for more details.
14 You should have received a copy of the GNU General Public License
15 along with this program; if not, write to the Free Software
16 Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */
19 #include "opcode/sparc.h"
21 #include "libiberty.h"
24 /* For faster lookup, after insns are sorted they are hashed. */
25 /* ??? I think there is room for even more improvement. */
28 /* It is important that we only look at insn code bits as that is how the
29 opcode table is hashed. OPCODE_BITS is a table of valid bits for each
30 of the main types (0,1,2,3). */
31 static int opcode_bits[4] = { 0x01c00000, 0x0, 0x01f80000, 0x01f80000 };
32 #define HASH_INSN(INSN) \
33 ((((INSN) >> 24) & 0xc0) | (((INSN) & opcode_bits[((INSN) >> 30) & 3]) >> 19))
35 struct opcode_hash *next;
36 struct sparc_opcode *opcode;
38 static struct opcode_hash *opcode_hash_table[HASH_SIZE];
39 static void build_hash_table ();
41 /* Sign-extend a value which is N bits long. */
42 #define SEX(value, bits) \
43 ((((int)(value)) << ((8 * sizeof (int)) - bits)) \
44 >> ((8 * sizeof (int)) - bits) )
46 static char *reg_names[] =
47 { "g0", "g1", "g2", "g3", "g4", "g5", "g6", "g7",
48 "o0", "o1", "o2", "o3", "o4", "o5", "sp", "o7",
49 "l0", "l1", "l2", "l3", "l4", "l5", "l6", "l7",
50 "i0", "i1", "i2", "i3", "i4", "i5", "fp", "i7",
51 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
52 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
53 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
54 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31",
56 "f32", "f33", "f34", "f35", "f36", "f37", "f38", "f39",
57 "f40", "f41", "f42", "f43", "f44", "f45", "f46", "f47",
58 "f48", "f49", "f50", "f51", "f52", "f53", "f54", "f55",
59 "f56", "f57", "f58", "f59", "f60", "f61", "f62", "f63",
60 /* psr, wim, tbr, fpsr, cpsr are v8 only. */
62 "y", "psr", "wim", "tbr", "pc", "npc", "fpsr", "cpsr"
65 #define freg_names (®_names[4 * 8])
68 /* These are ordered according to there register number in
69 rdpr and wrpr insns. */
70 static char *v9_priv_reg_names[] =
72 "tpc", "tnpc", "tstate", "tt", "tick", "tba", "pstate", "tl",
73 "pil", "cwp", "cansave", "canrestore", "cleanwin", "otherwin",
75 /* "ver" - special cased */
79 /* Macros used to extract instruction fields. Not all fields have
80 macros defined here, only those which are actually used. */
82 #define X_RD(i) (((i) >> 25) & 0x1f)
83 #define X_RS1(i) (((i) >> 14) & 0x1f)
84 #define X_LDST_I(i) (((i) >> 13) & 1)
85 #define X_ASI(i) (((i) >> 5) & 0xff)
86 #define X_RS2(i) (((i) >> 0) & 0x1f)
87 #define X_IMM13(i) (((i) >> 0) & 0x1fff)
88 #define X_DISP22(i) (((i) >> 0) & 0x3fffff)
89 #define X_IMM22(i) X_DISP22 (i)
90 #define X_DISP30(i) (((i) >> 0) & 0x3fffffff)
93 #define X_DISP16(i) (((((i) >> 20) & 3) << 14) | (((i) >> 0) & 0x3fff))
94 #define X_MEMBAR(i) ((i) & 0x7f)
97 /* Here is the union which was used to extract instruction fields
98 before the shift and mask macros were written.
102 unsigned long int code;
110 unsigned int anrs1:5;
111 #define rs1 ldst.anrs1
113 unsigned int anasi:8;
114 #define asi ldst.anasi
115 unsigned int anrs2:5;
116 #define rs2 ldst.anrs2
121 unsigned int anop:2, anrd:5, op3:6, anrs1:5, i:1;
122 unsigned int IMM13:13;
123 #define imm13 IMM13.IMM13
131 unsigned int DISP22:22;
132 #define disp22 branch.DISP22
141 unsigned int rcond:3;
143 unsigned int DISP16HI:2;
146 unsigned int DISP16LO:14;
152 unsigned int adisp30:30;
153 #define disp30 call.adisp30
159 /* Nonzero if INSN is the opcode for a delayed branch. */
161 is_delayed_branch (insn)
164 struct opcode_hash *op;
166 for (op = opcode_hash_table[HASH_INSN (insn)]; op; op = op->next)
168 CONST struct sparc_opcode *opcode = op->opcode;
169 if ((opcode->match & insn) == opcode->match
170 && (opcode->lose & insn) == 0)
171 return (opcode->flags & F_DELAYED);
176 /* Nonzero of opcode table has been initialized. */
177 static int opcodes_initialized = 0;
179 /* extern void qsort (); */
180 static int compare_opcodes ();
182 /* Print one instruction from MEMADDR on INFO->STREAM.
184 We suffix the instruction with a comment that gives the absolute
185 address involved, as well as its symbolic form, if the instruction
186 is preceded by a findable `sethi' and it either adds an immediate
187 displacement to that register, or it is an `add' or `or' instruction
191 print_insn (memaddr, info, sparc64_p)
193 disassemble_info *info;
196 FILE *stream = info->stream;
199 register unsigned int i;
200 register struct opcode_hash *op;
202 if (!opcodes_initialized)
204 qsort ((char *) sparc_opcodes, NUMOPCODES,
205 sizeof (sparc_opcodes[0]), compare_opcodes);
206 build_hash_table (sparc_opcodes, opcode_hash_table, NUMOPCODES);
207 opcodes_initialized = 1;
212 (*info->read_memory_func) (memaddr, buffer, sizeof (buffer), info);
215 (*info->memory_error_func) (status, memaddr, info);
220 insn = bfd_getb32 (buffer);
222 info->insn_info_valid = 1; /* We do return this info */
223 info->insn_type = dis_nonbranch; /* Assume non branch insn */
224 info->branch_delay_insns = 0; /* Assume no delay */
225 info->target = 0; /* Assume no target known */
227 for (op = opcode_hash_table[HASH_INSN (insn)]; op; op = op->next)
229 CONST struct sparc_opcode *opcode = op->opcode;
231 /* If the current architecture isn't sparc64, skip sparc64 insns. */
233 && opcode->architecture == v9)
236 /* If the current architecture is sparc64, skip sparc32 only insns. */
238 && (opcode->flags & F_NOTV9))
241 if ((opcode->match & insn) == opcode->match
242 && (opcode->lose & insn) == 0)
244 /* Nonzero means that we have found an instruction which has
245 the effect of adding or or'ing the imm13 field to rs1. */
246 int imm_added_to_rs1 = 0;
248 /* Nonzero means that we have found a plus sign in the args
249 field of the opcode table. */
252 /* Nonzero means we have an annulled branch. */
255 /* Do we have an `add' or `or' instruction where rs1 is the same
256 as rsd, and which has the i bit set? */
257 if ((opcode->match == 0x80102000 || opcode->match == 0x80002000)
259 && X_RS1 (insn) == X_RD (insn))
260 imm_added_to_rs1 = 1;
262 if (X_RS1 (insn) != X_RD (insn)
263 && strchr (opcode->args, 'r') != 0)
264 /* Can't do simple format if source and dest are different. */
267 (*info->fprintf_func) (stream, opcode->name);
270 register CONST char *s;
272 if (opcode->args[0] != ',')
273 (*info->fprintf_func) (stream, " ");
274 for (s = opcode->args; *s != '\0'; ++s)
278 (*info->fprintf_func) (stream, ",");
282 (*info->fprintf_func) (stream, "a");
288 (*info->fprintf_func) (stream, "pn");
293 (*info->fprintf_func) (stream, "pt");
300 } /* switch on arg */
301 } /* while there are comma started args */
303 (*info->fprintf_func) (stream, " ");
310 /* note fall-through */
312 (*info->fprintf_func) (stream, "%c", *s);
316 (*info->fprintf_func) (stream, "0");
319 #define reg(n) (*info->fprintf_func) (stream, "%%%s", reg_names[n])
334 #define freg(n) (*info->fprintf_func) (stream, "%%%s", freg_names[n])
335 #define fregx(n) (*info->fprintf_func) (stream, "%%%s", freg_names[((n) & ~1) | (((n) & 1) << 5)])
339 case 'v': /* double/even */
340 case 'V': /* quad/multiple of 4 */
341 fregx (X_RS1 (insn));
347 case 'B': /* double/even */
348 case 'R': /* quad/multiple of 4 */
349 fregx (X_RS2 (insn));
355 case 'H': /* double/even */
356 case 'J': /* quad/multiple of 4 */
362 #define creg(n) (*info->fprintf_func) (stream, "%%c%u", (unsigned int) (n))
377 (*info->fprintf_func) (stream, "%%hi(%#x)",
379 & ((int) X_IMM22 (insn) << 10)));
384 int imm = SEX (X_IMM13 (insn), 13);
386 /* Check to see whether we have a 1+i, and take
389 Note: because of the way we sort the table,
390 we will be matching 1+i rather than i+1,
391 so it is OK to assume that i is after +,
394 imm_added_to_rs1 = 1;
397 (*info->fprintf_func) (stream, "%d", imm);
399 (*info->fprintf_func) (stream, "%#x", imm);
404 case 'I': /* 11 bit immediate. */
405 case 'j': /* 10 bit immediate. */
410 imm = SEX (X_IMM13 (insn), 11);
412 imm = SEX (X_IMM13 (insn), 10);
414 /* Check to see whether we have a 1+i, and take
417 Note: because of the way we sort the table,
418 we will be matching 1+i rather than i+1,
419 so it is OK to assume that i is after +,
422 imm_added_to_rs1 = 1;
425 (info->fprintf_func) (stream, "%d", imm);
427 (info->fprintf_func) (stream, "%#x", (unsigned) imm);
433 int mask = X_MEMBAR (insn);
434 int bit = 0x40, printed_one = 0;
438 (info->fprintf_func) (stream, "0");
445 (info->fprintf_func) (stream, "|");
446 name = sparc_decode_membar (bit);
447 (info->fprintf_func) (stream, "%s", name);
456 info->target = memaddr + (SEX (X_DISP16 (insn), 16)) * 4;
457 (*info->print_address_func) (info->target, info);
461 info->target = memaddr + (SEX (X_DISP22 (insn), 19)) * 4;
462 (*info->print_address_func) (info->target, info);
469 (*info->fprintf_func) (stream, "%%fcc%c", *s - '6' + '0');
473 (*info->fprintf_func) (stream, "%%icc");
477 (*info->fprintf_func) (stream, "%%xcc");
481 (*info->fprintf_func) (stream, "%%ccr");
485 (*info->fprintf_func) (stream, "%%fprs");
489 (*info->fprintf_func) (stream, "%%asi");
493 (*info->fprintf_func) (stream, "%%tick");
497 (*info->fprintf_func) (stream, "%%pc");
501 if (X_RS1 (insn) == 31)
502 (*info->fprintf_func) (stream, "%%ver");
503 else if ((unsigned) X_RS1 (insn) < 16)
504 (*info->fprintf_func) (stream, "%%%s",
505 v9_priv_reg_names[X_RS1 (insn)]);
507 (*info->fprintf_func) (stream, "%%reserved");
511 if ((unsigned) X_RD (insn) < 15)
512 (*info->fprintf_func) (stream, "%%%s",
513 v9_priv_reg_names[X_RD (insn)]);
515 (*info->fprintf_func) (stream, "%%reserved");
520 char *name = sparc_decode_prefetch (X_RD (insn));
523 (*info->fprintf_func) (stream, "%s", name);
525 (*info->fprintf_func) (stream, "%d", X_RD (insn));
531 (*info->fprintf_func) (stream, "%%asr%d", X_RS1 (insn));
535 (*info->fprintf_func) (stream, "%%asr%d", X_RD (insn));
539 info->target = memaddr + X_DISP30 (insn) * 4;
540 (*info->print_address_func) (info->target, info);
544 (*info->fprintf_func)
545 (stream, "%#x", (SEX (X_DISP22 (insn), 22)));
549 info->target = memaddr + (SEX (X_DISP22 (insn), 22)) * 4;
550 (*info->print_address_func) (info->target, info);
555 char *name = sparc_decode_asi (X_ASI (insn));
558 (*info->fprintf_func) (stream, "%s", name);
560 (*info->fprintf_func) (stream, "(%d)", X_ASI (insn));
565 (*info->fprintf_func) (stream, "%%csr");
569 (*info->fprintf_func) (stream, "%%fsr");
573 (*info->fprintf_func) (stream, "%%psr");
577 (*info->fprintf_func) (stream, "%%fq");
581 (*info->fprintf_func) (stream, "%%cq");
585 (*info->fprintf_func) (stream, "%%tbr");
589 (*info->fprintf_func) (stream, "%%wim");
593 (*info->fprintf_func) (stream, "%d",
594 ((X_LDST_I (insn) << 8)
599 (*info->fprintf_func) (stream, "%%y");
605 /* If we are adding or or'ing something to rs1, then
606 check to see whether the previous instruction was
607 a sethi to the same register as in the sethi.
608 If so, attempt to print the result of the add or
609 or (in this context add and or do the same thing)
610 and its symbolic value. */
611 if (imm_added_to_rs1)
613 unsigned long prev_insn;
617 (*info->read_memory_func)
618 (memaddr - 4, buffer, sizeof (buffer), info);
619 prev_insn = bfd_getb32 (buffer);
623 /* If it is a delayed branch, we need to look at the
624 instruction before the delayed branch. This handles
627 sethi %o1, %hi(_foo), %o1
629 or %o1, %lo(_foo), %o1
632 if (is_delayed_branch (prev_insn))
634 errcode = (*info->read_memory_func)
635 (memaddr - 8, buffer, sizeof (buffer), info);
636 prev_insn = bfd_getb32 (buffer);
640 /* If there was a problem reading memory, then assume
641 the previous instruction was not sethi. */
644 /* Is it sethi to the same register? */
645 if ((prev_insn & 0xc1c00000) == 0x01000000
646 && X_RD (prev_insn) == X_RS1 (insn))
648 (*info->fprintf_func) (stream, "\t! ");
650 (0xFFFFFFFF & (int) X_IMM22 (prev_insn) << 10)
651 | SEX (X_IMM13 (insn), 13);
652 (*info->print_address_func) (info->target, info);
653 info->insn_type = dis_dref;
654 info->data_size = 4; /* FIXME!!! */
659 if (opcode->flags & (F_UNBR|F_CONDBR|F_JSR))
661 /* FIXME -- check is_annulled flag */
662 if (opcode->flags & F_UNBR)
663 info->insn_type = dis_branch;
664 if (opcode->flags & F_CONDBR)
665 info->insn_type = dis_condbranch;
666 if (opcode->flags & F_JSR)
667 info->insn_type = dis_jsr;
668 if (opcode->flags & F_DELAYED)
669 info->branch_delay_insns = 1;
672 return sizeof (buffer);
676 info->insn_type = dis_noninsn; /* Mark as non-valid instruction */
677 (*info->fprintf_func) (stream, "%#8x", insn);
678 return sizeof (buffer);
681 /* Compare opcodes A and B. */
684 compare_opcodes (a, b)
687 struct sparc_opcode *op0 = (struct sparc_opcode *) a;
688 struct sparc_opcode *op1 = (struct sparc_opcode *) b;
689 unsigned long int match0 = op0->match, match1 = op1->match;
690 unsigned long int lose0 = op0->lose, lose1 = op1->lose;
691 register unsigned int i;
693 /* If a bit is set in both match and lose, there is something
694 wrong with the opcode table. */
697 fprintf (stderr, "Internal error: bad sparc-opcode.h: \"%s\", %#.8lx, %#.8lx\n",
698 op0->name, match0, lose0);
699 op0->lose &= ~op0->match;
705 fprintf (stderr, "Internal error: bad sparc-opcode.h: \"%s\", %#.8lx, %#.8lx\n",
706 op1->name, match1, lose1);
707 op1->lose &= ~op1->match;
711 /* Because the bits that are variable in one opcode are constant in
712 another, it is important to order the opcodes in the right order. */
713 for (i = 0; i < 32; ++i)
715 unsigned long int x = 1 << i;
716 int x0 = (match0 & x) != 0;
717 int x1 = (match1 & x) != 0;
723 for (i = 0; i < 32; ++i)
725 unsigned long int x = 1 << i;
726 int x0 = (lose0 & x) != 0;
727 int x1 = (lose1 & x) != 0;
733 /* Put non-sparc64 insns ahead of sparc64 ones. */
734 if ((op0->architecture == v9) != (op1->architecture == v9))
735 return (op0->architecture == v9) - (op1->architecture == v9);
737 /* They are functionally equal. So as long as the opcode table is
738 valid, we can put whichever one first we want, on aesthetic grounds. */
740 /* Our first aesthetic ground is that aliases defer to real insns. */
742 int alias_diff = (op0->flags & F_ALIAS) - (op1->flags & F_ALIAS);
744 /* Put the one that isn't an alias first. */
748 /* Except for aliases, two "identical" instructions had
749 better have the same opcode. This is a sanity check on the table. */
750 i = strcmp (op0->name, op1->name);
752 if (op0->flags & F_ALIAS) /* If they're both aliases, be arbitrary. */
756 "Internal error: bad sparc-opcode.h: \"%s\" == \"%s\"\n",
757 op0->name, op1->name);
759 /* Fewer arguments are preferred. */
761 int length_diff = strlen (op0->args) - strlen (op1->args);
762 if (length_diff != 0)
763 /* Put the one with fewer arguments first. */
767 /* Put 1+i before i+1. */
769 char *p0 = (char *) strchr(op0->args, '+');
770 char *p1 = (char *) strchr(op1->args, '+');
774 /* There is a plus in both operands. Note that a plus
775 sign cannot be the first character in args,
776 so the following [-1]'s are valid. */
777 if (p0[-1] == 'i' && p1[1] == 'i')
778 /* op0 is i+1 and op1 is 1+i, so op1 goes first. */
780 if (p0[1] == 'i' && p1[-1] == 'i')
781 /* op0 is 1+i and op1 is i+1, so op0 goes first. */
786 /* Put 1,i before i,1. */
788 int i0 = strncmp (op0->args, "i,1", 3) == 0;
789 int i1 = strncmp (op1->args, "i,1", 3) == 0;
795 /* They are, as far as we can tell, identical.
796 Since qsort may have rearranged the table partially, there is
797 no way to tell which one was first in the opcode table as
798 written, so just say there are equal. */
802 /* Build a hash table from the opcode table. */
805 build_hash_table (table, hash_table, num_opcodes)
806 struct sparc_opcode *table;
807 struct opcode_hash **hash_table;
811 int hash_count[HASH_SIZE];
812 static struct opcode_hash *hash_buf = NULL;
814 /* Start at the end of the table and work backwards so that each
817 memset (hash_table, 0, HASH_SIZE * sizeof (hash_table[0]));
818 memset (hash_count, 0, HASH_SIZE * sizeof (hash_count[0]));
819 if (hash_buf != NULL)
821 hash_buf = (struct opcode_hash *) xmalloc (sizeof (struct opcode_hash) * num_opcodes);
822 for (i = num_opcodes - 1; i >= 0; --i)
824 register int hash = HASH_INSN (sparc_opcodes[i].match);
825 register struct opcode_hash *h = &hash_buf[i];
826 h->next = hash_table[hash];
827 h->opcode = &sparc_opcodes[i];
828 hash_table[hash] = h;
832 #if 0 /* for debugging */
834 int min_count = num_opcodes, max_count = 0;
837 for (i = 0; i < HASH_SIZE; ++i)
839 if (hash_count[i] < min_count)
840 min_count = hash_count[i];
841 if (hash_count[i] > max_count)
842 max_count = hash_count[i];
843 total += hash_count[i];
846 printf ("Opcode hash table stats: min %d, max %d, ave %f\n",
847 min_count, max_count, (double) total / HASH_SIZE);
853 print_insn_sparc (memaddr, info)
855 disassemble_info *info;
857 return print_insn (memaddr, info, 0);
861 print_insn_sparc64 (memaddr, info)
863 disassemble_info *info;
865 return print_insn (memaddr, info, 1);