1 /* Print SPARC instructions.
2 Copyright 1989, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999,
3 2000, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2010
4 Free Software Foundation, Inc.
6 This file is part of the GNU opcodes library.
8 This library is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 3, or (at your option)
13 It is distributed in the hope that it will be useful, but WITHOUT
14 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
15 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
16 License for more details.
18 You should have received a copy of the GNU General Public License
19 along with this program; if not, write to the Free Software
20 Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
21 MA 02110-1301, USA. */
26 #include "opcode/sparc.h"
28 #include "libiberty.h"
31 /* Bitmask of v9 architectures. */
32 #define MASK_V9 ((1 << SPARC_OPCODE_ARCH_V9) \
33 | (1 << SPARC_OPCODE_ARCH_V9A) \
34 | (1 << SPARC_OPCODE_ARCH_V9B))
35 /* 1 if INSN is for v9 only. */
36 #define V9_ONLY_P(insn) (! ((insn)->architecture & ~MASK_V9))
37 /* 1 if INSN is for v9. */
38 #define V9_P(insn) (((insn)->architecture & MASK_V9) != 0)
40 /* The sorted opcode table. */
41 static const sparc_opcode **sorted_opcodes;
43 /* For faster lookup, after insns are sorted they are hashed. */
44 /* ??? I think there is room for even more improvement. */
47 /* It is important that we only look at insn code bits as that is how the
48 opcode table is hashed. OPCODE_BITS is a table of valid bits for each
49 of the main types (0,1,2,3). */
50 static int opcode_bits[4] = { 0x01c00000, 0x0, 0x01f80000, 0x01f80000 };
51 #define HASH_INSN(INSN) \
52 ((((INSN) >> 24) & 0xc0) | (((INSN) & opcode_bits[((INSN) >> 30) & 3]) >> 19))
53 typedef struct sparc_opcode_hash
55 struct sparc_opcode_hash *next;
56 const sparc_opcode *opcode;
59 static sparc_opcode_hash *opcode_hash_table[HASH_SIZE];
61 /* Sign-extend a value which is N bits long. */
62 #define SEX(value, bits) \
63 ((((int)(value)) << ((8 * sizeof (int)) - bits)) \
64 >> ((8 * sizeof (int)) - bits) )
66 static char *reg_names[] =
67 { "g0", "g1", "g2", "g3", "g4", "g5", "g6", "g7",
68 "o0", "o1", "o2", "o3", "o4", "o5", "sp", "o7",
69 "l0", "l1", "l2", "l3", "l4", "l5", "l6", "l7",
70 "i0", "i1", "i2", "i3", "i4", "i5", "fp", "i7",
71 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
72 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
73 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
74 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31",
75 "f32", "f33", "f34", "f35", "f36", "f37", "f38", "f39",
76 "f40", "f41", "f42", "f43", "f44", "f45", "f46", "f47",
77 "f48", "f49", "f50", "f51", "f52", "f53", "f54", "f55",
78 "f56", "f57", "f58", "f59", "f60", "f61", "f62", "f63",
79 /* psr, wim, tbr, fpsr, cpsr are v8 only. */
80 "y", "psr", "wim", "tbr", "pc", "npc", "fpsr", "cpsr"
83 #define freg_names (®_names[4 * 8])
85 /* These are ordered according to there register number in
86 rdpr and wrpr insns. */
87 static char *v9_priv_reg_names[] =
89 "tpc", "tnpc", "tstate", "tt", "tick", "tba", "pstate", "tl",
90 "pil", "cwp", "cansave", "canrestore", "cleanwin", "otherwin",
92 /* "ver" - special cased */
95 /* These are ordered according to there register number in
96 rdhpr and wrhpr insns. */
97 static char *v9_hpriv_reg_names[] =
99 "hpstate", "htstate", "resv2", "hintp", "resv4", "htba", "hver",
100 "resv7", "resv8", "resv9", "resv10", "resv11", "resv12", "resv13",
101 "resv14", "resv15", "resv16", "resv17", "resv18", "resv19", "resv20",
102 "resv21", "resv22", "resv23", "resv24", "resv25", "resv26", "resv27",
103 "resv28", "resv29", "resv30", "hstick_cmpr"
106 /* These are ordered according to there register number in
107 rd and wr insns (-16). */
108 static char *v9a_asr_reg_names[] =
110 "pcr", "pic", "dcr", "gsr", "set_softint", "clear_softint",
111 "softint", "tick_cmpr", "stick", "stick_cmpr", "resv26",
115 /* Macros used to extract instruction fields. Not all fields have
116 macros defined here, only those which are actually used. */
118 #define X_RD(i) (((i) >> 25) & 0x1f)
119 #define X_RS1(i) (((i) >> 14) & 0x1f)
120 #define X_LDST_I(i) (((i) >> 13) & 1)
121 #define X_ASI(i) (((i) >> 5) & 0xff)
122 #define X_RS2(i) (((i) >> 0) & 0x1f)
123 #define X_RS3(i) (((i) >> 9) & 0x1f)
124 #define X_IMM(i,n) (((i) >> 0) & ((1 << (n)) - 1))
125 #define X_SIMM(i,n) SEX (X_IMM ((i), (n)), (n))
126 #define X_DISP22(i) (((i) >> 0) & 0x3fffff)
127 #define X_IMM22(i) X_DISP22 (i)
128 #define X_DISP30(i) (((i) >> 0) & 0x3fffffff)
130 /* These are for v9. */
131 #define X_DISP16(i) (((((i) >> 20) & 3) << 14) | (((i) >> 0) & 0x3fff))
132 #define X_DISP10(i) (((((i) >> 19) & 3) << 8) | (((i) >> 5) & 0xff))
133 #define X_DISP19(i) (((i) >> 0) & 0x7ffff)
134 #define X_MEMBAR(i) ((i) & 0x7f)
136 /* Here is the union which was used to extract instruction fields
137 before the shift and mask macros were written.
141 unsigned long int code;
149 unsigned int anrs1:5;
150 #define rs1 ldst.anrs1
152 unsigned int anasi:8;
153 #define asi ldst.anasi
154 unsigned int anrs2:5;
155 #define rs2 ldst.anrs2
160 unsigned int anop:2, anrd:5, op3:6, anrs1:5, i:1;
161 unsigned int IMM13:13;
162 #define imm13 IMM13.IMM13
170 unsigned int DISP22:22;
171 #define disp22 branch.DISP22
179 unsigned int rcond:3;
181 unsigned int DISP16HI:2;
184 unsigned int DISP16LO:14;
189 unsigned int adisp30:30;
190 #define disp30 call.adisp30
194 /* Nonzero if INSN is the opcode for a delayed branch. */
197 is_delayed_branch (unsigned long insn)
199 sparc_opcode_hash *op;
201 for (op = opcode_hash_table[HASH_INSN (insn)]; op; op = op->next)
203 const sparc_opcode *opcode = op->opcode;
205 if ((opcode->match & insn) == opcode->match
206 && (opcode->lose & insn) == 0)
207 return opcode->flags & F_DELAYED;
212 /* extern void qsort (); */
214 /* Records current mask of SPARC_OPCODE_ARCH_FOO values, used to pass value
215 to compare_opcodes. */
216 static unsigned int current_arch_mask;
218 /* Given BFD mach number, return a mask of SPARC_OPCODE_ARCH_FOO values. */
221 compute_arch_mask (unsigned long mach)
226 case bfd_mach_sparc :
227 return SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_V8);
228 case bfd_mach_sparc_sparclet :
229 return SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_SPARCLET);
230 case bfd_mach_sparc_sparclite :
231 case bfd_mach_sparc_sparclite_le :
232 /* sparclites insns are recognized by default (because that's how
233 they've always been treated, for better or worse). Kludge this by
234 indicating generic v8 is also selected. */
235 return (SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_SPARCLITE)
236 | SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_V8));
237 case bfd_mach_sparc_v8plus :
238 case bfd_mach_sparc_v9 :
239 return SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_V9);
240 case bfd_mach_sparc_v8plusa :
241 case bfd_mach_sparc_v9a :
242 return SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_V9A);
243 case bfd_mach_sparc_v8plusb :
244 case bfd_mach_sparc_v9b :
245 return SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_V9B);
250 /* Compare opcodes A and B. */
253 compare_opcodes (const void * a, const void * b)
255 sparc_opcode *op0 = * (sparc_opcode **) a;
256 sparc_opcode *op1 = * (sparc_opcode **) b;
257 unsigned long int match0 = op0->match, match1 = op1->match;
258 unsigned long int lose0 = op0->lose, lose1 = op1->lose;
259 register unsigned int i;
261 /* If one (and only one) insn isn't supported by the current architecture,
262 prefer the one that is. If neither are supported, but they're both for
263 the same architecture, continue processing. Otherwise (both unsupported
264 and for different architectures), prefer lower numbered arch's (fudged
265 by comparing the bitmasks). */
266 if (op0->architecture & current_arch_mask)
268 if (! (op1->architecture & current_arch_mask))
273 if (op1->architecture & current_arch_mask)
275 else if (op0->architecture != op1->architecture)
276 return op0->architecture - op1->architecture;
279 /* If a bit is set in both match and lose, there is something
280 wrong with the opcode table. */
285 /* xgettext:c-format */
286 _("Internal error: bad sparc-opcode.h: \"%s\", %#.8lx, %#.8lx\n"),
287 op0->name, match0, lose0);
288 op0->lose &= ~op0->match;
296 /* xgettext:c-format */
297 _("Internal error: bad sparc-opcode.h: \"%s\", %#.8lx, %#.8lx\n"),
298 op1->name, match1, lose1);
299 op1->lose &= ~op1->match;
303 /* Because the bits that are variable in one opcode are constant in
304 another, it is important to order the opcodes in the right order. */
305 for (i = 0; i < 32; ++i)
307 unsigned long int x = 1 << i;
308 int x0 = (match0 & x) != 0;
309 int x1 = (match1 & x) != 0;
315 for (i = 0; i < 32; ++i)
317 unsigned long int x = 1 << i;
318 int x0 = (lose0 & x) != 0;
319 int x1 = (lose1 & x) != 0;
325 /* They are functionally equal. So as long as the opcode table is
326 valid, we can put whichever one first we want, on aesthetic grounds. */
328 /* Our first aesthetic ground is that aliases defer to real insns. */
330 int alias_diff = (op0->flags & F_ALIAS) - (op1->flags & F_ALIAS);
333 /* Put the one that isn't an alias first. */
337 /* Except for aliases, two "identical" instructions had
338 better have the same opcode. This is a sanity check on the table. */
339 i = strcmp (op0->name, op1->name);
342 if (op0->flags & F_ALIAS) /* If they're both aliases, be arbitrary. */
346 /* xgettext:c-format */
347 _("Internal error: bad sparc-opcode.h: \"%s\" == \"%s\"\n"),
348 op0->name, op1->name);
351 /* Fewer arguments are preferred. */
353 int length_diff = strlen (op0->args) - strlen (op1->args);
355 if (length_diff != 0)
356 /* Put the one with fewer arguments first. */
360 /* Put 1+i before i+1. */
362 char *p0 = (char *) strchr (op0->args, '+');
363 char *p1 = (char *) strchr (op1->args, '+');
367 /* There is a plus in both operands. Note that a plus
368 sign cannot be the first character in args,
369 so the following [-1]'s are valid. */
370 if (p0[-1] == 'i' && p1[1] == 'i')
371 /* op0 is i+1 and op1 is 1+i, so op1 goes first. */
373 if (p0[1] == 'i' && p1[-1] == 'i')
374 /* op0 is 1+i and op1 is i+1, so op0 goes first. */
379 /* Put 1,i before i,1. */
381 int i0 = strncmp (op0->args, "i,1", 3) == 0;
382 int i1 = strncmp (op1->args, "i,1", 3) == 0;
388 /* They are, as far as we can tell, identical.
389 Since qsort may have rearranged the table partially, there is
390 no way to tell which one was first in the opcode table as
391 written, so just say there are equal. */
392 /* ??? This is no longer true now that we sort a vector of pointers,
393 not the table itself. */
397 /* Build a hash table from the opcode table.
398 OPCODE_TABLE is a sorted list of pointers into the opcode table. */
401 build_hash_table (const sparc_opcode **opcode_table,
402 sparc_opcode_hash **hash_table,
406 int hash_count[HASH_SIZE];
407 static sparc_opcode_hash *hash_buf = NULL;
409 /* Start at the end of the table and work backwards so that each
412 memset (hash_table, 0, HASH_SIZE * sizeof (hash_table[0]));
413 memset (hash_count, 0, HASH_SIZE * sizeof (hash_count[0]));
414 if (hash_buf != NULL)
416 hash_buf = xmalloc (sizeof (* hash_buf) * num_opcodes);
417 for (i = num_opcodes - 1; i >= 0; --i)
419 int hash = HASH_INSN (opcode_table[i]->match);
420 sparc_opcode_hash *h = &hash_buf[i];
422 h->next = hash_table[hash];
423 h->opcode = opcode_table[i];
424 hash_table[hash] = h;
428 #if 0 /* for debugging */
430 int min_count = num_opcodes, max_count = 0;
433 for (i = 0; i < HASH_SIZE; ++i)
435 if (hash_count[i] < min_count)
436 min_count = hash_count[i];
437 if (hash_count[i] > max_count)
438 max_count = hash_count[i];
439 total += hash_count[i];
442 printf ("Opcode hash table stats: min %d, max %d, ave %f\n",
443 min_count, max_count, (double) total / HASH_SIZE);
448 /* Print one instruction from MEMADDR on INFO->STREAM.
450 We suffix the instruction with a comment that gives the absolute
451 address involved, as well as its symbolic form, if the instruction
452 is preceded by a findable `sethi' and it either adds an immediate
453 displacement to that register, or it is an `add' or `or' instruction
457 print_insn_sparc (bfd_vma memaddr, disassemble_info *info)
459 FILE *stream = info->stream;
462 sparc_opcode_hash *op;
463 /* Nonzero of opcode table has been initialized. */
464 static int opcodes_initialized = 0;
465 /* bfd mach number of last call. */
466 static unsigned long current_mach = 0;
467 bfd_vma (*getword) (const void *);
469 if (!opcodes_initialized
470 || info->mach != current_mach)
474 current_arch_mask = compute_arch_mask (info->mach);
476 if (!opcodes_initialized)
478 xmalloc (sparc_num_opcodes * sizeof (sparc_opcode *));
479 /* Reset the sorted table so we can resort it. */
480 for (i = 0; i < sparc_num_opcodes; ++i)
481 sorted_opcodes[i] = &sparc_opcodes[i];
482 qsort ((char *) sorted_opcodes, sparc_num_opcodes,
483 sizeof (sorted_opcodes[0]), compare_opcodes);
485 build_hash_table (sorted_opcodes, opcode_hash_table, sparc_num_opcodes);
486 current_mach = info->mach;
487 opcodes_initialized = 1;
492 (*info->read_memory_func) (memaddr, buffer, sizeof (buffer), info);
496 (*info->memory_error_func) (status, memaddr, info);
501 /* On SPARClite variants such as DANlite (sparc86x), instructions
502 are always big-endian even when the machine is in little-endian mode. */
503 if (info->endian == BFD_ENDIAN_BIG || info->mach == bfd_mach_sparc_sparclite)
504 getword = bfd_getb32;
506 getword = bfd_getl32;
508 insn = getword (buffer);
510 info->insn_info_valid = 1; /* We do return this info. */
511 info->insn_type = dis_nonbranch; /* Assume non branch insn. */
512 info->branch_delay_insns = 0; /* Assume no delay. */
513 info->target = 0; /* Assume no target known. */
515 for (op = opcode_hash_table[HASH_INSN (insn)]; op; op = op->next)
517 const sparc_opcode *opcode = op->opcode;
519 /* If the insn isn't supported by the current architecture, skip it. */
520 if (! (opcode->architecture & current_arch_mask))
523 if ((opcode->match & insn) == opcode->match
524 && (opcode->lose & insn) == 0)
526 /* Nonzero means that we have found an instruction which has
527 the effect of adding or or'ing the imm13 field to rs1. */
528 int imm_added_to_rs1 = 0;
529 int imm_ored_to_rs1 = 0;
531 /* Nonzero means that we have found a plus sign in the args
532 field of the opcode table. */
535 /* Nonzero means we have an annulled branch. */
538 /* Do we have an `add' or `or' instruction combining an
539 immediate with rs1? */
540 if (opcode->match == 0x80102000) /* or */
542 if (opcode->match == 0x80002000) /* add */
543 imm_added_to_rs1 = 1;
545 if (X_RS1 (insn) != X_RD (insn)
546 && strchr (opcode->args, 'r') != 0)
547 /* Can't do simple format if source and dest are different. */
549 if (X_RS2 (insn) != X_RD (insn)
550 && strchr (opcode->args, 'O') != 0)
551 /* Can't do simple format if source and dest are different. */
554 (*info->fprintf_func) (stream, opcode->name);
559 if (opcode->args[0] != ',')
560 (*info->fprintf_func) (stream, " ");
562 for (s = opcode->args; *s != '\0'; ++s)
566 (*info->fprintf_func) (stream, ",");
571 (*info->fprintf_func) (stream, "a");
576 (*info->fprintf_func) (stream, "pn");
581 (*info->fprintf_func) (stream, "pt");
590 (*info->fprintf_func) (stream, " ");
599 (*info->fprintf_func) (stream, "%c", *s);
603 (*info->fprintf_func) (stream, "0");
606 #define reg(n) (*info->fprintf_func) (stream, "%%%s", reg_names[n])
622 #define freg(n) (*info->fprintf_func) (stream, "%%%s", freg_names[n])
623 #define fregx(n) (*info->fprintf_func) (stream, "%%%s", freg_names[((n) & ~1) | (((n) & 1) << 5)])
627 case 'v': /* Double/even. */
628 case 'V': /* Quad/multiple of 4. */
629 fregx (X_RS1 (insn));
635 case 'B': /* Double/even. */
636 case 'R': /* Quad/multiple of 4. */
637 fregx (X_RS2 (insn));
643 case '5': /* Double/even. */
644 fregx (X_RS3 (insn));
650 case 'H': /* Double/even. */
651 case 'J': /* Quad/multiple of 4. */
657 #define creg(n) (*info->fprintf_func) (stream, "%%c%u", (unsigned int) (n))
672 (*info->fprintf_func) (stream, "%%hi(%#x)",
673 ((unsigned) 0xFFFFFFFF
674 & ((int) X_IMM22 (insn) << 10)));
677 case 'i': /* 13 bit immediate. */
678 case 'I': /* 11 bit immediate. */
679 case 'j': /* 10 bit immediate. */
684 imm = X_SIMM (insn, 13);
686 imm = X_SIMM (insn, 11);
688 imm = X_SIMM (insn, 10);
690 /* Check to see whether we have a 1+i, and take
693 Note: because of the way we sort the table,
694 we will be matching 1+i rather than i+1,
695 so it is OK to assume that i is after +,
698 imm_added_to_rs1 = 1;
701 (*info->fprintf_func) (stream, "%d", imm);
703 (*info->fprintf_func) (stream, "%#x", imm);
707 case ')': /* 5 bit unsigned immediate from RS3. */
708 (info->fprintf_func) (stream, "%#x", X_RS3 (insn));
711 case 'X': /* 5 bit unsigned immediate. */
712 case 'Y': /* 6 bit unsigned immediate. */
714 int imm = X_IMM (insn, *s == 'X' ? 5 : 6);
717 (info->fprintf_func) (stream, "%d", imm);
719 (info->fprintf_func) (stream, "%#x", (unsigned) imm);
724 (info->fprintf_func) (stream, "%ld", X_IMM (insn, 3));
729 int mask = X_MEMBAR (insn);
730 int bit = 0x40, printed_one = 0;
734 (info->fprintf_func) (stream, "0");
741 (info->fprintf_func) (stream, "|");
742 name = sparc_decode_membar (bit);
743 (info->fprintf_func) (stream, "%s", name);
752 info->target = memaddr + SEX (X_DISP10 (insn), 10) * 4;
753 (*info->print_address_func) (info->target, info);
757 info->target = memaddr + SEX (X_DISP16 (insn), 16) * 4;
758 (*info->print_address_func) (info->target, info);
762 info->target = memaddr + SEX (X_DISP19 (insn), 19) * 4;
763 (*info->print_address_func) (info->target, info);
770 (*info->fprintf_func) (stream, "%%fcc%c", *s - '6' + '0');
774 (*info->fprintf_func) (stream, "%%icc");
778 (*info->fprintf_func) (stream, "%%xcc");
782 (*info->fprintf_func) (stream, "%%ccr");
786 (*info->fprintf_func) (stream, "%%fprs");
790 (*info->fprintf_func) (stream, "%%asi");
794 (*info->fprintf_func) (stream, "%%tick");
798 (*info->fprintf_func) (stream, "%%pc");
802 if (X_RS1 (insn) == 31)
803 (*info->fprintf_func) (stream, "%%ver");
804 else if ((unsigned) X_RS1 (insn) < 17)
805 (*info->fprintf_func) (stream, "%%%s",
806 v9_priv_reg_names[X_RS1 (insn)]);
808 (*info->fprintf_func) (stream, "%%reserved");
812 if ((unsigned) X_RD (insn) < 17)
813 (*info->fprintf_func) (stream, "%%%s",
814 v9_priv_reg_names[X_RD (insn)]);
816 (*info->fprintf_func) (stream, "%%reserved");
820 if ((unsigned) X_RS1 (insn) < 32)
821 (*info->fprintf_func) (stream, "%%%s",
822 v9_hpriv_reg_names[X_RS1 (insn)]);
824 (*info->fprintf_func) (stream, "%%reserved");
828 if ((unsigned) X_RD (insn) < 32)
829 (*info->fprintf_func) (stream, "%%%s",
830 v9_hpriv_reg_names[X_RD (insn)]);
832 (*info->fprintf_func) (stream, "%%reserved");
836 if (X_RS1 (insn) < 16 || X_RS1 (insn) > 28)
837 (*info->fprintf_func) (stream, "%%reserved");
839 (*info->fprintf_func) (stream, "%%%s",
840 v9a_asr_reg_names[X_RS1 (insn)-16]);
844 if (X_RD (insn) < 16 || X_RD (insn) > 28)
845 (*info->fprintf_func) (stream, "%%reserved");
847 (*info->fprintf_func) (stream, "%%%s",
848 v9a_asr_reg_names[X_RD (insn)-16]);
853 const char *name = sparc_decode_prefetch (X_RD (insn));
856 (*info->fprintf_func) (stream, "%s", name);
858 (*info->fprintf_func) (stream, "%ld", X_RD (insn));
863 (*info->fprintf_func) (stream, "%%asr%ld", X_RS1 (insn));
867 (*info->fprintf_func) (stream, "%%asr%ld", X_RD (insn));
871 info->target = memaddr + SEX (X_DISP30 (insn), 30) * 4;
872 (*info->print_address_func) (info->target, info);
876 (*info->fprintf_func)
877 (stream, "%#x", SEX (X_DISP22 (insn), 22));
881 info->target = memaddr + SEX (X_DISP22 (insn), 22) * 4;
882 (*info->print_address_func) (info->target, info);
887 const char *name = sparc_decode_asi (X_ASI (insn));
890 (*info->fprintf_func) (stream, "%s", name);
892 (*info->fprintf_func) (stream, "(%ld)", X_ASI (insn));
897 (*info->fprintf_func) (stream, "%%csr");
901 (*info->fprintf_func) (stream, "%%fsr");
905 (*info->fprintf_func) (stream, "%%efsr");
909 (*info->fprintf_func) (stream, "%%psr");
913 (*info->fprintf_func) (stream, "%%fq");
917 (*info->fprintf_func) (stream, "%%cq");
921 (*info->fprintf_func) (stream, "%%tbr");
925 (*info->fprintf_func) (stream, "%%wim");
929 (*info->fprintf_func) (stream, "%ld",
930 ((X_LDST_I (insn) << 8)
935 (*info->fprintf_func) (stream, "%%y");
941 int val = *s == 'U' ? X_RS1 (insn) : X_RD (insn);
942 const char *name = sparc_decode_sparclet_cpreg (val);
945 (*info->fprintf_func) (stream, "%s", name);
947 (*info->fprintf_func) (stream, "%%cpreg(%d)", val);
954 /* If we are adding or or'ing something to rs1, then
955 check to see whether the previous instruction was
956 a sethi to the same register as in the sethi.
957 If so, attempt to print the result of the add or
958 or (in this context add and or do the same thing)
959 and its symbolic value. */
960 if (imm_ored_to_rs1 || imm_added_to_rs1)
962 unsigned long prev_insn;
967 (*info->read_memory_func)
968 (memaddr - 4, buffer, sizeof (buffer), info);
972 prev_insn = getword (buffer);
976 /* If it is a delayed branch, we need to look at the
977 instruction before the delayed branch. This handles
980 sethi %o1, %hi(_foo), %o1
982 or %o1, %lo(_foo), %o1 */
984 if (is_delayed_branch (prev_insn))
987 errcode = (*info->read_memory_func)
988 (memaddr - 8, buffer, sizeof (buffer), info);
992 prev_insn = getword (buffer);
996 /* If there was a problem reading memory, then assume
997 the previous instruction was not sethi. */
1000 /* Is it sethi to the same register? */
1001 if ((prev_insn & 0xc1c00000) == 0x01000000
1002 && X_RD (prev_insn) == X_RS1 (insn))
1004 (*info->fprintf_func) (stream, "\t! ");
1006 ((unsigned) 0xFFFFFFFF
1007 & ((int) X_IMM22 (prev_insn) << 10));
1008 if (imm_added_to_rs1)
1009 info->target += X_SIMM (insn, 13);
1011 info->target |= X_SIMM (insn, 13);
1012 (*info->print_address_func) (info->target, info);
1013 info->insn_type = dis_dref;
1014 info->data_size = 4; /* FIXME!!! */
1019 if (opcode->flags & (F_UNBR|F_CONDBR|F_JSR))
1021 /* FIXME -- check is_annulled flag. */
1023 if (opcode->flags & F_UNBR)
1024 info->insn_type = dis_branch;
1025 if (opcode->flags & F_CONDBR)
1026 info->insn_type = dis_condbranch;
1027 if (opcode->flags & F_JSR)
1028 info->insn_type = dis_jsr;
1029 if (opcode->flags & F_DELAYED)
1030 info->branch_delay_insns = 1;
1033 return sizeof (buffer);
1037 info->insn_type = dis_noninsn; /* Mark as non-valid instruction. */
1038 (*info->fprintf_func) (stream, _("unknown"));
1039 return sizeof (buffer);