1 /* Print SPARC instructions.
2 Copyright (C) 1989-2016 Free Software Foundation, Inc.
4 This file is part of the GNU opcodes library.
6 This library is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 3, or (at your option)
11 It is distributed in the hope that it will be useful, but WITHOUT
12 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
13 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
14 License for more details.
16 You should have received a copy of the GNU General Public License
17 along with this program; if not, write to the Free Software
18 Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
19 MA 02110-1301, USA. */
23 #include "opcode/sparc.h"
25 #include "libiberty.h"
28 /* Bitmask of v9 architectures. */
29 #define MASK_V9 ((1 << SPARC_OPCODE_ARCH_V9) \
30 | (1 << SPARC_OPCODE_ARCH_V9A) \
31 | (1 << SPARC_OPCODE_ARCH_V9B) \
32 | (1 << SPARC_OPCODE_ARCH_V9C) \
33 | (1 << SPARC_OPCODE_ARCH_V9D) \
34 | (1 << SPARC_OPCODE_ARCH_V9E) \
35 | (1 << SPARC_OPCODE_ARCH_V9V) \
36 | (1 << SPARC_OPCODE_ARCH_V9M))
37 /* 1 if INSN is for v9 only. */
38 #define V9_ONLY_P(insn) (! ((insn)->architecture & ~MASK_V9))
39 /* 1 if INSN is for v9. */
40 #define V9_P(insn) (((insn)->architecture & MASK_V9) != 0)
42 /* The sorted opcode table. */
43 static const sparc_opcode **sorted_opcodes;
45 /* For faster lookup, after insns are sorted they are hashed. */
46 /* ??? I think there is room for even more improvement. */
49 /* It is important that we only look at insn code bits as that is how the
50 opcode table is hashed. OPCODE_BITS is a table of valid bits for each
51 of the main types (0,1,2,3). */
52 static int opcode_bits[4] = { 0x01c00000, 0x0, 0x01f80000, 0x01f80000 };
53 #define HASH_INSN(INSN) \
54 ((((INSN) >> 24) & 0xc0) | (((INSN) & opcode_bits[((INSN) >> 30) & 3]) >> 19))
55 typedef struct sparc_opcode_hash
57 struct sparc_opcode_hash *next;
58 const sparc_opcode *opcode;
61 static sparc_opcode_hash *opcode_hash_table[HASH_SIZE];
63 /* Sign-extend a value which is N bits long. */
64 #define SEX(value, bits) \
65 ((((int)(value)) << ((8 * sizeof (int)) - bits)) \
66 >> ((8 * sizeof (int)) - bits) )
68 static char *reg_names[] =
69 { "g0", "g1", "g2", "g3", "g4", "g5", "g6", "g7",
70 "o0", "o1", "o2", "o3", "o4", "o5", "sp", "o7",
71 "l0", "l1", "l2", "l3", "l4", "l5", "l6", "l7",
72 "i0", "i1", "i2", "i3", "i4", "i5", "fp", "i7",
73 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
74 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
75 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
76 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31",
77 "f32", "f33", "f34", "f35", "f36", "f37", "f38", "f39",
78 "f40", "f41", "f42", "f43", "f44", "f45", "f46", "f47",
79 "f48", "f49", "f50", "f51", "f52", "f53", "f54", "f55",
80 "f56", "f57", "f58", "f59", "f60", "f61", "f62", "f63",
81 /* psr, wim, tbr, fpsr, cpsr are v8 only. */
82 "y", "psr", "wim", "tbr", "pc", "npc", "fpsr", "cpsr"
85 #define freg_names (®_names[4 * 8])
87 /* These are ordered according to there register number in
88 rdpr and wrpr insns. */
89 static char *v9_priv_reg_names[] =
91 "tpc", "tnpc", "tstate", "tt", "tick", "tba", "pstate", "tl",
92 "pil", "cwp", "cansave", "canrestore", "cleanwin", "otherwin",
94 /* "ver" and "pmcdper" - special cased */
97 /* These are ordered according to there register number in
98 rdhpr and wrhpr insns. */
99 static char *v9_hpriv_reg_names[] =
101 "hpstate", "htstate", "resv2", "hintp", "resv4", "htba", "hver",
102 "resv7", "resv8", "resv9", "resv10", "resv11", "resv12", "resv13",
103 "resv14", "resv15", "resv16", "resv17", "resv18", "resv19", "resv20",
104 "resv21", "resv22", "hmcdper", "hmcddfr", "resv25", "resv26", "hva_mask_nz",
105 "hstick_offset", "hstick_enable", "resv30", "hstick_cmpr"
108 /* These are ordered according to there register number in
109 rd and wr insns (-16). */
110 static char *v9a_asr_reg_names[] =
112 "pcr", "pic", "dcr", "gsr", "softint_set", "softint_clear",
113 "softint", "tick_cmpr", "stick", "stick_cmpr", "cfr",
117 /* Macros used to extract instruction fields. Not all fields have
118 macros defined here, only those which are actually used. */
120 #define X_RD(i) (((i) >> 25) & 0x1f)
121 #define X_RS1(i) (((i) >> 14) & 0x1f)
122 #define X_LDST_I(i) (((i) >> 13) & 1)
123 #define X_ASI(i) (((i) >> 5) & 0xff)
124 #define X_RS2(i) (((i) >> 0) & 0x1f)
125 #define X_RS3(i) (((i) >> 9) & 0x1f)
126 #define X_IMM(i,n) (((i) >> 0) & ((1 << (n)) - 1))
127 #define X_SIMM(i,n) SEX (X_IMM ((i), (n)), (n))
128 #define X_DISP22(i) (((i) >> 0) & 0x3fffff)
129 #define X_IMM22(i) X_DISP22 (i)
130 #define X_DISP30(i) (((i) >> 0) & 0x3fffffff)
132 /* These are for v9. */
133 #define X_DISP16(i) (((((i) >> 20) & 3) << 14) | (((i) >> 0) & 0x3fff))
134 #define X_DISP10(i) (((((i) >> 19) & 3) << 8) | (((i) >> 5) & 0xff))
135 #define X_DISP19(i) (((i) >> 0) & 0x7ffff)
136 #define X_MEMBAR(i) ((i) & 0x7f)
138 /* Here is the union which was used to extract instruction fields
139 before the shift and mask macros were written.
143 unsigned long int code;
151 unsigned int anrs1:5;
152 #define rs1 ldst.anrs1
154 unsigned int anasi:8;
155 #define asi ldst.anasi
156 unsigned int anrs2:5;
157 #define rs2 ldst.anrs2
162 unsigned int anop:2, anrd:5, op3:6, anrs1:5, i:1;
163 unsigned int IMM13:13;
164 #define imm13 IMM13.IMM13
172 unsigned int DISP22:22;
173 #define disp22 branch.DISP22
181 unsigned int rcond:3;
183 unsigned int DISP16HI:2;
186 unsigned int DISP16LO:14;
191 unsigned int adisp30:30;
192 #define disp30 call.adisp30
196 /* Nonzero if INSN is the opcode for a delayed branch. */
199 is_delayed_branch (unsigned long insn)
201 sparc_opcode_hash *op;
203 for (op = opcode_hash_table[HASH_INSN (insn)]; op; op = op->next)
205 const sparc_opcode *opcode = op->opcode;
207 if ((opcode->match & insn) == opcode->match
208 && (opcode->lose & insn) == 0)
209 return opcode->flags & F_DELAYED;
214 /* extern void qsort (); */
216 /* Records current mask of SPARC_OPCODE_ARCH_FOO values, used to pass value
217 to compare_opcodes. */
218 static unsigned int current_arch_mask;
220 /* Given BFD mach number, return a mask of SPARC_OPCODE_ARCH_FOO values. */
223 compute_arch_mask (unsigned long mach)
228 case bfd_mach_sparc :
229 return (SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_V8)
230 | SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_LEON));
231 case bfd_mach_sparc_sparclet :
232 return SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_SPARCLET);
233 case bfd_mach_sparc_sparclite :
234 case bfd_mach_sparc_sparclite_le :
235 /* sparclites insns are recognized by default (because that's how
236 they've always been treated, for better or worse). Kludge this by
237 indicating generic v8 is also selected. */
238 return (SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_SPARCLITE)
239 | SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_V8));
240 case bfd_mach_sparc_v8plus :
241 case bfd_mach_sparc_v9 :
242 return SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_V9);
243 case bfd_mach_sparc_v8plusa :
244 case bfd_mach_sparc_v9a :
245 return SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_V9A);
246 case bfd_mach_sparc_v8plusb :
247 case bfd_mach_sparc_v9b :
248 return SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_V9B);
249 case bfd_mach_sparc_v8plusc :
250 case bfd_mach_sparc_v9c :
251 return SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_V9C);
252 case bfd_mach_sparc_v8plusd :
253 case bfd_mach_sparc_v9d :
254 return SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_V9D);
255 case bfd_mach_sparc_v8pluse :
256 case bfd_mach_sparc_v9e :
257 return SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_V9E);
258 case bfd_mach_sparc_v8plusv :
259 case bfd_mach_sparc_v9v :
260 return SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_V9V);
261 case bfd_mach_sparc_v8plusm :
262 case bfd_mach_sparc_v9m :
263 return SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_V9M);
268 /* Compare opcodes A and B. */
271 compare_opcodes (const void * a, const void * b)
273 sparc_opcode *op0 = * (sparc_opcode **) a;
274 sparc_opcode *op1 = * (sparc_opcode **) b;
275 unsigned long int match0 = op0->match, match1 = op1->match;
276 unsigned long int lose0 = op0->lose, lose1 = op1->lose;
277 register unsigned int i;
279 /* If one (and only one) insn isn't supported by the current architecture,
280 prefer the one that is. If neither are supported, but they're both for
281 the same architecture, continue processing. Otherwise (both unsupported
282 and for different architectures), prefer lower numbered arch's (fudged
283 by comparing the bitmasks). */
284 if (op0->architecture & current_arch_mask)
286 if (! (op1->architecture & current_arch_mask))
291 if (op1->architecture & current_arch_mask)
293 else if (op0->architecture != op1->architecture)
294 return op0->architecture - op1->architecture;
297 /* If a bit is set in both match and lose, there is something
298 wrong with the opcode table. */
303 /* xgettext:c-format */
304 _("Internal error: bad sparc-opcode.h: \"%s\", %#.8lx, %#.8lx\n"),
305 op0->name, match0, lose0);
306 op0->lose &= ~op0->match;
314 /* xgettext:c-format */
315 _("Internal error: bad sparc-opcode.h: \"%s\", %#.8lx, %#.8lx\n"),
316 op1->name, match1, lose1);
317 op1->lose &= ~op1->match;
321 /* Because the bits that are variable in one opcode are constant in
322 another, it is important to order the opcodes in the right order. */
323 for (i = 0; i < 32; ++i)
325 unsigned long int x = 1 << i;
326 int x0 = (match0 & x) != 0;
327 int x1 = (match1 & x) != 0;
333 for (i = 0; i < 32; ++i)
335 unsigned long int x = 1 << i;
336 int x0 = (lose0 & x) != 0;
337 int x1 = (lose1 & x) != 0;
343 /* They are functionally equal. So as long as the opcode table is
344 valid, we can put whichever one first we want, on aesthetic grounds. */
346 /* Our first aesthetic ground is that aliases defer to real insns. */
348 int alias_diff = (op0->flags & F_ALIAS) - (op1->flags & F_ALIAS);
351 /* Put the one that isn't an alias first. */
355 /* Except for aliases, two "identical" instructions had
356 better have the same opcode. This is a sanity check on the table. */
357 i = strcmp (op0->name, op1->name);
360 if (op0->flags & F_ALIAS)
362 if (op0->flags & F_PREFERRED)
364 if (op1->flags & F_PREFERRED)
367 /* If they're both aliases, and neither is marked as preferred,
373 /* xgettext:c-format */
374 _("Internal error: bad sparc-opcode.h: \"%s\" == \"%s\"\n"),
375 op0->name, op1->name);
378 /* Fewer arguments are preferred. */
380 int length_diff = strlen (op0->args) - strlen (op1->args);
382 if (length_diff != 0)
383 /* Put the one with fewer arguments first. */
387 /* Put 1+i before i+1. */
389 char *p0 = (char *) strchr (op0->args, '+');
390 char *p1 = (char *) strchr (op1->args, '+');
394 /* There is a plus in both operands. Note that a plus
395 sign cannot be the first character in args,
396 so the following [-1]'s are valid. */
397 if (p0[-1] == 'i' && p1[1] == 'i')
398 /* op0 is i+1 and op1 is 1+i, so op1 goes first. */
400 if (p0[1] == 'i' && p1[-1] == 'i')
401 /* op0 is 1+i and op1 is i+1, so op0 goes first. */
406 /* Put 1,i before i,1. */
408 int i0 = strncmp (op0->args, "i,1", 3) == 0;
409 int i1 = strncmp (op1->args, "i,1", 3) == 0;
415 /* They are, as far as we can tell, identical.
416 Since qsort may have rearranged the table partially, there is
417 no way to tell which one was first in the opcode table as
418 written, so just say there are equal. */
419 /* ??? This is no longer true now that we sort a vector of pointers,
420 not the table itself. */
424 /* Build a hash table from the opcode table.
425 OPCODE_TABLE is a sorted list of pointers into the opcode table. */
428 build_hash_table (const sparc_opcode **opcode_table,
429 sparc_opcode_hash **hash_table,
433 int hash_count[HASH_SIZE];
434 static sparc_opcode_hash *hash_buf = NULL;
436 /* Start at the end of the table and work backwards so that each
439 memset (hash_table, 0, HASH_SIZE * sizeof (hash_table[0]));
440 memset (hash_count, 0, HASH_SIZE * sizeof (hash_count[0]));
441 if (hash_buf != NULL)
443 hash_buf = xmalloc (sizeof (* hash_buf) * num_opcodes);
444 for (i = num_opcodes - 1; i >= 0; --i)
446 int hash = HASH_INSN (opcode_table[i]->match);
447 sparc_opcode_hash *h = &hash_buf[i];
449 h->next = hash_table[hash];
450 h->opcode = opcode_table[i];
451 hash_table[hash] = h;
455 #if 0 /* for debugging */
457 int min_count = num_opcodes, max_count = 0;
460 for (i = 0; i < HASH_SIZE; ++i)
462 if (hash_count[i] < min_count)
463 min_count = hash_count[i];
464 if (hash_count[i] > max_count)
465 max_count = hash_count[i];
466 total += hash_count[i];
469 printf ("Opcode hash table stats: min %d, max %d, ave %f\n",
470 min_count, max_count, (double) total / HASH_SIZE);
475 /* Print one instruction from MEMADDR on INFO->STREAM.
477 We suffix the instruction with a comment that gives the absolute
478 address involved, as well as its symbolic form, if the instruction
479 is preceded by a findable `sethi' and it either adds an immediate
480 displacement to that register, or it is an `add' or `or' instruction
484 print_insn_sparc (bfd_vma memaddr, disassemble_info *info)
486 FILE *stream = info->stream;
489 sparc_opcode_hash *op;
490 /* Nonzero of opcode table has been initialized. */
491 static int opcodes_initialized = 0;
492 /* bfd mach number of last call. */
493 static unsigned long current_mach = 0;
494 bfd_vma (*getword) (const void *);
496 if (!opcodes_initialized
497 || info->mach != current_mach)
501 current_arch_mask = compute_arch_mask (info->mach);
503 if (!opcodes_initialized)
505 xmalloc (sparc_num_opcodes * sizeof (sparc_opcode *));
506 /* Reset the sorted table so we can resort it. */
507 for (i = 0; i < sparc_num_opcodes; ++i)
508 sorted_opcodes[i] = &sparc_opcodes[i];
509 qsort ((char *) sorted_opcodes, sparc_num_opcodes,
510 sizeof (sorted_opcodes[0]), compare_opcodes);
512 build_hash_table (sorted_opcodes, opcode_hash_table, sparc_num_opcodes);
513 current_mach = info->mach;
514 opcodes_initialized = 1;
519 (*info->read_memory_func) (memaddr, buffer, sizeof (buffer), info);
523 (*info->memory_error_func) (status, memaddr, info);
528 /* On SPARClite variants such as DANlite (sparc86x), instructions
529 are always big-endian even when the machine is in little-endian mode. */
530 if (info->endian == BFD_ENDIAN_BIG || info->mach == bfd_mach_sparc_sparclite)
531 getword = bfd_getb32;
533 getword = bfd_getl32;
535 insn = getword (buffer);
537 info->insn_info_valid = 1; /* We do return this info. */
538 info->insn_type = dis_nonbranch; /* Assume non branch insn. */
539 info->branch_delay_insns = 0; /* Assume no delay. */
540 info->target = 0; /* Assume no target known. */
542 for (op = opcode_hash_table[HASH_INSN (insn)]; op; op = op->next)
544 const sparc_opcode *opcode = op->opcode;
546 /* If the insn isn't supported by the current architecture, skip it. */
547 if (! (opcode->architecture & current_arch_mask))
550 if ((opcode->match & insn) == opcode->match
551 && (opcode->lose & insn) == 0)
553 /* Nonzero means that we have found an instruction which has
554 the effect of adding or or'ing the imm13 field to rs1. */
555 int imm_added_to_rs1 = 0;
556 int imm_ored_to_rs1 = 0;
558 /* Nonzero means that we have found a plus sign in the args
559 field of the opcode table. */
562 /* Nonzero means we have an annulled branch. */
565 /* Do we have an `add' or `or' instruction combining an
566 immediate with rs1? */
567 if (opcode->match == 0x80102000) /* or */
569 if (opcode->match == 0x80002000) /* add */
570 imm_added_to_rs1 = 1;
572 if (X_RS1 (insn) != X_RD (insn)
573 && strchr (opcode->args, 'r') != 0)
574 /* Can't do simple format if source and dest are different. */
576 if (X_RS2 (insn) != X_RD (insn)
577 && strchr (opcode->args, 'O') != 0)
578 /* Can't do simple format if source and dest are different. */
581 (*info->fprintf_func) (stream, "%s", opcode->name);
586 if (opcode->args[0] != ',')
587 (*info->fprintf_func) (stream, " ");
589 for (s = opcode->args; *s != '\0'; ++s)
593 (*info->fprintf_func) (stream, ",");
598 (*info->fprintf_func) (stream, "a");
603 (*info->fprintf_func) (stream, "pn");
608 (*info->fprintf_func) (stream, "pt");
617 (*info->fprintf_func) (stream, " ");
626 (*info->fprintf_func) (stream, "%c", *s);
630 (*info->fprintf_func) (stream, "0");
633 #define reg(n) (*info->fprintf_func) (stream, "%%%s", reg_names[n])
649 #define freg(n) (*info->fprintf_func) (stream, "%%%s", freg_names[n])
650 #define fregx(n) (*info->fprintf_func) (stream, "%%%s", freg_names[((n) & ~1) | (((n) & 1) << 5)])
654 case 'v': /* Double/even. */
655 case 'V': /* Quad/multiple of 4. */
656 fregx (X_RS1 (insn));
662 case 'B': /* Double/even. */
663 case 'R': /* Quad/multiple of 4. */
664 fregx (X_RS2 (insn));
670 case '5': /* Double/even. */
671 fregx (X_RS3 (insn));
677 case 'H': /* Double/even. */
678 case 'J': /* Quad/multiple of 4. */
679 case '}': /* Double/even. */
685 #define creg(n) (*info->fprintf_func) (stream, "%%c%u", (unsigned int) (n))
700 (*info->fprintf_func) (stream, "%%hi(%#x)",
701 ((unsigned) 0xFFFFFFFF
702 & ((int) X_IMM22 (insn) << 10)));
705 case 'i': /* 13 bit immediate. */
706 case 'I': /* 11 bit immediate. */
707 case 'j': /* 10 bit immediate. */
712 imm = X_SIMM (insn, 13);
714 imm = X_SIMM (insn, 11);
716 imm = X_SIMM (insn, 10);
718 /* Check to see whether we have a 1+i, and take
721 Note: because of the way we sort the table,
722 we will be matching 1+i rather than i+1,
723 so it is OK to assume that i is after +,
726 imm_added_to_rs1 = 1;
729 (*info->fprintf_func) (stream, "%d", imm);
731 (*info->fprintf_func) (stream, "%#x", imm);
735 case ')': /* 5 bit unsigned immediate from RS3. */
736 (info->fprintf_func) (stream, "%#x", (unsigned int) X_RS3 (insn));
739 case 'X': /* 5 bit unsigned immediate. */
740 case 'Y': /* 6 bit unsigned immediate. */
742 int imm = X_IMM (insn, *s == 'X' ? 5 : 6);
745 (info->fprintf_func) (stream, "%d", imm);
747 (info->fprintf_func) (stream, "%#x", (unsigned) imm);
752 (info->fprintf_func) (stream, "%ld", X_IMM (insn, 3));
757 int mask = X_MEMBAR (insn);
758 int bit = 0x40, printed_one = 0;
762 (info->fprintf_func) (stream, "0");
769 (info->fprintf_func) (stream, "|");
770 name = sparc_decode_membar (bit);
771 (info->fprintf_func) (stream, "%s", name);
780 info->target = memaddr + SEX (X_DISP10 (insn), 10) * 4;
781 (*info->print_address_func) (info->target, info);
785 info->target = memaddr + SEX (X_DISP16 (insn), 16) * 4;
786 (*info->print_address_func) (info->target, info);
790 info->target = memaddr + SEX (X_DISP19 (insn), 19) * 4;
791 (*info->print_address_func) (info->target, info);
798 (*info->fprintf_func) (stream, "%%fcc%c", *s - '6' + '0');
802 (*info->fprintf_func) (stream, "%%icc");
806 (*info->fprintf_func) (stream, "%%xcc");
810 (*info->fprintf_func) (stream, "%%ccr");
814 (*info->fprintf_func) (stream, "%%fprs");
818 (*info->fprintf_func) (stream, "%%mcdper");
822 (*info->fprintf_func) (stream, "%%asi");
826 (*info->fprintf_func) (stream, "%%tick");
830 (*info->fprintf_func) (stream, "%%pc");
834 if (X_RS1 (insn) == 31)
835 (*info->fprintf_func) (stream, "%%ver");
836 else if (X_RS1 (insn) == 23)
837 (*info->fprintf_func) (stream, "%%pmcdper");
838 else if ((unsigned) X_RS1 (insn) < 17)
839 (*info->fprintf_func) (stream, "%%%s",
840 v9_priv_reg_names[X_RS1 (insn)]);
842 (*info->fprintf_func) (stream, "%%reserved");
846 if (X_RD (insn) == 31)
847 (*info->fprintf_func) (stream, "%%ver");
848 else if (X_RD (insn) == 23)
849 (*info->fprintf_func) (stream, "%%pmcdper");
850 else if ((unsigned) X_RD (insn) < 17)
851 (*info->fprintf_func) (stream, "%%%s",
852 v9_priv_reg_names[X_RD (insn)]);
854 (*info->fprintf_func) (stream, "%%reserved");
858 if ((unsigned) X_RS1 (insn) < 32)
859 (*info->fprintf_func) (stream, "%%%s",
860 v9_hpriv_reg_names[X_RS1 (insn)]);
862 (*info->fprintf_func) (stream, "%%reserved");
866 if ((unsigned) X_RD (insn) < 32)
867 (*info->fprintf_func) (stream, "%%%s",
868 v9_hpriv_reg_names[X_RD (insn)]);
870 (*info->fprintf_func) (stream, "%%reserved");
874 if (X_RS1 (insn) < 16 || X_RS1 (insn) > 28)
875 (*info->fprintf_func) (stream, "%%reserved");
877 (*info->fprintf_func) (stream, "%%%s",
878 v9a_asr_reg_names[X_RS1 (insn)-16]);
882 if (X_RD (insn) < 16 || X_RD (insn) > 28)
883 (*info->fprintf_func) (stream, "%%reserved");
885 (*info->fprintf_func) (stream, "%%%s",
886 v9a_asr_reg_names[X_RD (insn)-16]);
891 const char *name = sparc_decode_prefetch (X_RD (insn));
894 (*info->fprintf_func) (stream, "%s", name);
896 (*info->fprintf_func) (stream, "%ld", X_RD (insn));
901 (*info->fprintf_func) (stream, "%%asr%ld", X_RS1 (insn));
905 (*info->fprintf_func) (stream, "%%asr%ld", X_RD (insn));
909 info->target = memaddr + SEX (X_DISP30 (insn), 30) * 4;
910 (*info->print_address_func) (info->target, info);
914 (*info->fprintf_func)
915 (stream, "%#x", SEX (X_DISP22 (insn), 22));
919 info->target = memaddr + SEX (X_DISP22 (insn), 22) * 4;
920 (*info->print_address_func) (info->target, info);
925 const char *name = sparc_decode_asi (X_ASI (insn));
928 (*info->fprintf_func) (stream, "%s", name);
930 (*info->fprintf_func) (stream, "(%ld)", X_ASI (insn));
935 (*info->fprintf_func) (stream, "%%csr");
939 (*info->fprintf_func) (stream, "%%fsr");
943 (*info->fprintf_func) (stream, "%%efsr");
947 (*info->fprintf_func) (stream, "%%psr");
951 (*info->fprintf_func) (stream, "%%fq");
955 (*info->fprintf_func) (stream, "%%cq");
959 (*info->fprintf_func) (stream, "%%tbr");
963 (*info->fprintf_func) (stream, "%%wim");
967 (*info->fprintf_func) (stream, "%ld",
968 ((X_LDST_I (insn) << 8)
973 (*info->fprintf_func) (stream, "%%y");
979 int val = *s == 'U' ? X_RS1 (insn) : X_RD (insn);
980 const char *name = sparc_decode_sparclet_cpreg (val);
983 (*info->fprintf_func) (stream, "%s", name);
985 (*info->fprintf_func) (stream, "%%cpreg(%d)", val);
992 /* If we are adding or or'ing something to rs1, then
993 check to see whether the previous instruction was
994 a sethi to the same register as in the sethi.
995 If so, attempt to print the result of the add or
996 or (in this context add and or do the same thing)
997 and its symbolic value. */
998 if (imm_ored_to_rs1 || imm_added_to_rs1)
1000 unsigned long prev_insn;
1005 (*info->read_memory_func)
1006 (memaddr - 4, buffer, sizeof (buffer), info);
1010 prev_insn = getword (buffer);
1014 /* If it is a delayed branch, we need to look at the
1015 instruction before the delayed branch. This handles
1018 sethi %o1, %hi(_foo), %o1
1020 or %o1, %lo(_foo), %o1 */
1022 if (is_delayed_branch (prev_insn))
1025 errcode = (*info->read_memory_func)
1026 (memaddr - 8, buffer, sizeof (buffer), info);
1030 prev_insn = getword (buffer);
1034 /* If there was a problem reading memory, then assume
1035 the previous instruction was not sethi. */
1038 /* Is it sethi to the same register? */
1039 if ((prev_insn & 0xc1c00000) == 0x01000000
1040 && X_RD (prev_insn) == X_RS1 (insn))
1042 (*info->fprintf_func) (stream, "\t! ");
1044 ((unsigned) 0xFFFFFFFF
1045 & ((int) X_IMM22 (prev_insn) << 10));
1046 if (imm_added_to_rs1)
1047 info->target += X_SIMM (insn, 13);
1049 info->target |= X_SIMM (insn, 13);
1050 (*info->print_address_func) (info->target, info);
1051 info->insn_type = dis_dref;
1052 info->data_size = 4; /* FIXME!!! */
1057 if (opcode->flags & (F_UNBR|F_CONDBR|F_JSR))
1059 /* FIXME -- check is_annulled flag. */
1061 if (opcode->flags & F_UNBR)
1062 info->insn_type = dis_branch;
1063 if (opcode->flags & F_CONDBR)
1064 info->insn_type = dis_condbranch;
1065 if (opcode->flags & F_JSR)
1066 info->insn_type = dis_jsr;
1067 if (opcode->flags & F_DELAYED)
1068 info->branch_delay_insns = 1;
1071 return sizeof (buffer);
1075 info->insn_type = dis_noninsn; /* Mark as non-valid instruction. */
1076 (*info->fprintf_func) (stream, _("unknown"));
1077 return sizeof (buffer);