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[external/binutils.git] / opcodes / sh64-opc.c
1 /* Definitions for SH64 opcodes.
2    Copyright (C) 2000, 2001, 2002, 2005, 2007 Free Software Foundation, Inc.
3
4    This file is part of the GNU opcodes library.
5
6    This library is free software; you can redistribute it and/or modify
7    it under the terms of the GNU General Public License as published by
8    the Free Software Foundation; either version 3, or (at your option)
9    any later version.
10
11    It is distributed in the hope that it will be useful, but WITHOUT
12    ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
13    or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
14    License for more details.
15
16    You should have received a copy of the GNU General Public License
17    along with this file; see the file COPYING.  If not, write to the
18    Free Software Foundation, 51 Franklin Street - Fifth Floor, Boston,
19    MA 02110-1301, USA.  */
20
21 #include "sh64-opc.h"
22 #include <stdio.h>
23
24 /* Users currently assume that no mnemonic appears twice.  For
25    disassembly, the first complete match is displayed.  */
26 const shmedia_opcode_info shmedia_table[] = {
27
28 /* 000000mmmmmm1001nnnnnndddddd0000  add <A_GREG_M>,<A_GREG_N>,<A_GREG_D>  */
29     { "add",        {A_GREG_M,A_GREG_N,A_GREG_D},
30       {OFFSET_20,OFFSET_10,OFFSET_4}, SHMEDIA_ADD_OPC
31     },
32 /* 000000mmmmmm1000nnnnnndddddd0000  add.l <A_GREG_M>,<A_GREG_N>,<A_GREG_D>  */
33     { "add.l",      {A_GREG_M,A_GREG_N,A_GREG_D},     {OFFSET_20,OFFSET_10,OFFSET_4}, 0x00080000
34     },
35 /* 110100mmmmmmssssssssssdddddd0000  addi <A_GREG_M>,<A_IMMS10>,<A_GREG_D>  */
36     { "addi",       {A_GREG_M,A_IMMS10BY1,A_GREG_D},  {OFFSET_20,OFFSET_10,OFFSET_4}, 
37       SHMEDIA_ADDI_OPC
38     },
39 /* 110101mmmmmmssssssssssdddddd0000  addi.l <A_GREG_M>,<A_IMMS10>,<A_GREG_D>  */
40     { "addi.l",     {A_GREG_M,A_IMMS10BY1,A_GREG_D},  {OFFSET_20,OFFSET_10,OFFSET_4}, 0xd4000000
41     },
42 /* 000000mmmmmm1100nnnnnndddddd0000  addz.l <A_GREG_M>,<A_GREG_N>,<A_GREG_D>  */
43     { "addz.l",     {A_GREG_M,A_GREG_N,A_GREG_D},     {OFFSET_20,OFFSET_10,OFFSET_4}, 0x000c0000
44     },
45 /* 111000mmmmmm0100ssssss1111110000  alloco <A_GREG_M>,<A_IMMS6BY32>  */
46     { "alloco",     {A_GREG_M,A_IMMS6BY32},           {OFFSET_20,OFFSET_10},          0xe00403f0
47     },
48 /* 000001mmmmmm1011nnnnnndddddd0000  and <A_GREG_M>,<A_GREG_N>,<A_GREG_D>  */
49     { "and",        {A_GREG_M,A_GREG_N,A_GREG_D},     {OFFSET_20,OFFSET_10,OFFSET_4}, 0x040b0000
50     },
51 /* 000001mmmmmm1111nnnnnndddddd0000  andc <A_GREG_M>,<A_GREG_N>,<A_GREG_D>  */
52     { "andc",       {A_GREG_M,A_GREG_N,A_GREG_D},     {OFFSET_20,OFFSET_10,OFFSET_4}, 0x040f0000
53     },
54 /* 110110mmmmmmssssssssssdddddd0000  andi <A_GREG_M>,<A_IMMS10>,<A_GREG_D>  */
55     { "andi",       {A_GREG_M,A_IMMS10,A_GREG_D},     {OFFSET_20,OFFSET_10,OFFSET_4}, 0xd8000000
56     },
57 /* 011001mmmmmm0001nnnnnnl00ccc0000  beq <A_GREG_M>,<A_GREG_N>,<A_TREG_A>  */
58     { "beq/l",      {A_GREG_M,A_GREG_N,A_TREG_A},     {OFFSET_20,OFFSET_10,OFFSET_4}, 0x64010200
59     },
60 /* 011001mmmmmm0001nnnnnnl00ccc0000  beq <A_GREG_M>,<A_GREG_N>,<A_TREG_A>  */
61     { "beq",        {A_GREG_M,A_GREG_N,A_TREG_A},     {OFFSET_20,OFFSET_10,OFFSET_4}, 0x64010200
62     },
63 /* 011001mmmmmm0001nnnnnn000ccc0000  beq/u <A_GREG_M>,<A_GREG_N>,<A_TREG_A>  */
64     { "beq/u",      {A_GREG_M,A_GREG_N,A_TREG_A},     {OFFSET_20,OFFSET_10,OFFSET_4}, 0x64010000
65     },
66 /* 111001mmmmmm0001ssssssl00ccc0000  beqi <A_GREG_M>,<A_IMMS6>,<A_TREG_A>  */
67     { "beqi/l",     {A_GREG_M,A_IMMS6,A_TREG_A},      {OFFSET_20,OFFSET_10,OFFSET_4}, 0xe4010200
68     },
69 /* 111001mmmmmm0001ssssssl00ccc0000  beqi <A_GREG_M>,<A_IMMS6>,<A_TREG_A>  */
70     { "beqi",       {A_GREG_M,A_IMMS6,A_TREG_A},      {OFFSET_20,OFFSET_10,OFFSET_4}, 0xe4010200
71     },
72 /* 111001mmmmmm0001ssssss000ccc0000  beqi/u <A_GREG_M>,<A_IMMS6>,<A_TREG_A>  */
73     { "beqi/u",     {A_GREG_M,A_IMMS6,A_TREG_A},      {OFFSET_20,OFFSET_10,OFFSET_4}, 0xe4010000
74     },
75 /* 011001mmmmmm0011nnnnnnl00ccc0000  bge <A_GREG_M>,<A_GREG_N>,<A_TREG_A>  */
76     { "bge/l",      {A_GREG_M,A_GREG_N,A_TREG_A},     {OFFSET_20,OFFSET_10,OFFSET_4}, 0x64030200
77     },
78 /* 011001mmmmmm0011nnnnnnl00ccc0000  bge <A_GREG_M>,<A_GREG_N>,<A_TREG_A>  */
79     { "bge",        {A_GREG_M,A_GREG_N,A_TREG_A},     {OFFSET_20,OFFSET_10,OFFSET_4}, 0x64030200
80     },
81 /* 011001mmmmmm0011nnnnnn000ccc0000  bge/u <A_GREG_M>,<A_GREG_N>,<A_TREG_A>  */
82     { "bge/u",      {A_GREG_M,A_GREG_N,A_TREG_A},     {OFFSET_20,OFFSET_10,OFFSET_4}, 0x64030000
83     },
84 /* 011001mmmmmm1011nnnnnnl00ccc0000  bgeu <A_GREG_M>,<A_GREG_N>,<A_TREG_A>  */
85     { "bgeu/l",     {A_GREG_M,A_GREG_N,A_TREG_A},     {OFFSET_20,OFFSET_10,OFFSET_4}, 0x640b0200
86     },
87 /* 011001mmmmmm1011nnnnnnl00ccc0000  bgeu <A_GREG_M>,<A_GREG_N>,<A_TREG_A>  */
88     { "bgeu",       {A_GREG_M,A_GREG_N,A_TREG_A},     {OFFSET_20,OFFSET_10,OFFSET_4}, 0x640b0200
89     },
90 /* 011001mmmmmm1011nnnnnn000ccc0000  bgeu/u <A_GREG_M>,<A_GREG_N>,<A_TREG_A>  */
91     { "bgeu/u",     {A_GREG_M,A_GREG_N,A_TREG_A},     {OFFSET_20,OFFSET_10,OFFSET_4}, 0x640b0000
92     },
93 /* 011001mmmmmm0111nnnnnnl00ccc0000  bgt <A_GREG_M>,<A_GREG_N>,<A_TREG_A>  */
94     { "bgt/l",      {A_GREG_M,A_GREG_N,A_TREG_A},     {OFFSET_20,OFFSET_10,OFFSET_4}, 0x64070200
95     },
96 /* 011001mmmmmm0111nnnnnnl00ccc0000  bgt <A_GREG_M>,<A_GREG_N>,<A_TREG_A>  */
97     { "bgt",        {A_GREG_M,A_GREG_N,A_TREG_A},     {OFFSET_20,OFFSET_10,OFFSET_4}, 0x64070200
98     },
99 /* 011001mmmmmm0111nnnnnn000ccc0000  bgt/u <A_GREG_M>,<A_GREG_N>,<A_TREG_A>  */
100     { "bgt/u",      {A_GREG_M,A_GREG_N,A_TREG_A},     {OFFSET_20,OFFSET_10,OFFSET_4}, 0x64070000
101     },
102 /* 011001mmmmmm1111nnnnnnl00ccc0000  bgtu <A_GREG_M>,<A_GREG_N>,<A_TREG_A>  */
103     { "bgtu/l",     {A_GREG_M,A_GREG_N,A_TREG_A},     {OFFSET_20,OFFSET_10,OFFSET_4}, 0x640f0200
104     },
105 /* 011001mmmmmm1111nnnnnnl00ccc0000  bgtu <A_GREG_M>,<A_GREG_N>,<A_TREG_A>  */
106     { "bgtu",       {A_GREG_M,A_GREG_N,A_TREG_A},     {OFFSET_20,OFFSET_10,OFFSET_4}, 0x640f0200
107     },
108 /* 011001mmmmmm1111nnnnnn000ccc0000  bgtu/u <A_GREG_M>,<A_GREG_N>,<A_TREG_A>  */
109     { "bgtu/u",     {A_GREG_M,A_GREG_N,A_TREG_A},     {OFFSET_20,OFFSET_10,OFFSET_4}, 0x640f0000
110     },
111 /* 010001000bbb0001111111dddddd0000  blink <A_TREG_B>,<A_GREG_D>  */
112     { "blink",      {A_TREG_B,A_GREG_D},              {OFFSET_20,OFFSET_4},           0x4401fc00
113     },
114 /* 011001mmmmmm0101nnnnnnl00ccc0000  bne <A_GREG_M>,<A_GREG_N>,<A_TREG_A>  */
115     { "bne/l",      {A_GREG_M,A_GREG_N,A_TREG_A},     {OFFSET_20,OFFSET_10,OFFSET_4}, 0x64050200
116     },
117 /* 011001mmmmmm0101nnnnnnl00ccc0000  bne <A_GREG_M>,<A_GREG_N>,<A_TREG_A>  */
118     { "bne",        {A_GREG_M,A_GREG_N,A_TREG_A},     {OFFSET_20,OFFSET_10,OFFSET_4}, 0x64050200
119     },
120 /* 011001mmmmmm0101nnnnnn000ccc0000  bne/u <A_GREG_M>,<A_GREG_N>,<A_TREG_A>  */
121     { "bne/u",      {A_GREG_M,A_GREG_N,A_TREG_A},     {OFFSET_20,OFFSET_10,OFFSET_4}, 0x64050000
122     },
123 /* 111001mmmmmm0101ssssssl00ccc0000  bnei <A_GREG_M>,<A_IMMS6>,<A_TREG_A>  */
124     { "bnei/l",     {A_GREG_M,A_IMMS6,A_TREG_A},      {OFFSET_20,OFFSET_10,OFFSET_4}, 0xe4050200
125     },
126 /* 111001mmmmmm0101ssssssl00ccc0000  bnei <A_GREG_M>,<A_IMMS6>,<A_TREG_A>  */
127     { "bnei",       {A_GREG_M,A_IMMS6,A_TREG_A},      {OFFSET_20,OFFSET_10,OFFSET_4}, 0xe4050200
128     },
129 /* 111001mmmmmm0101ssssss000ccc0000  bnei/u <A_GREG_M>,<A_IMMS6>,<A_TREG_A>  */
130     { "bnei/u",     {A_GREG_M,A_IMMS6,A_TREG_A},      {OFFSET_20,OFFSET_10,OFFSET_4}, 0xe4050000
131     },
132 /* 01101111111101011111111111110000  brk  */
133     { "brk",        {A_NONE},                         {OFFSET_NONE},                  0x6ff5fff0
134     },
135 /* 000000mmmmmm1111111111dddddd0000  byterev <A_GREG_M>,<A_GREG_D>  */
136     { "byterev",    {A_GREG_M,A_GREG_D},              {OFFSET_20,OFFSET_4},           0x000ffc00
137     },
138 /* 000000mmmmmm0001nnnnnndddddd0000  cmpeq <A_GREG_M>,<A_GREG_N>,<A_GREG_D>  */
139     { "cmpeq",      {A_GREG_M,A_GREG_N,A_GREG_D},     {OFFSET_20,OFFSET_10,OFFSET_4}, 0x00010000
140     },
141 /* 000000mmmmmm0011nnnnnndddddd0000  cmpgt <A_GREG_M>,<A_GREG_N>,<A_GREG_D>  */
142     { "cmpgt",      {A_GREG_M,A_GREG_N,A_GREG_D},     {OFFSET_20,OFFSET_10,OFFSET_4}, 0x00030000
143     },
144 /* 000000mmmmmm0111nnnnnndddddd0000  cmpgtu <A_GREG_M>,<A_GREG_N>,<A_GREG_D>  */
145     { "cmpgtu",     {A_GREG_M,A_GREG_N,A_GREG_D},     {OFFSET_20,OFFSET_10,OFFSET_4}, 0x00070000
146     },
147 /* 001000mmmmmm0001nnnnnnwwwwww0000  cmveq <A_GREG_M>,<A_GREG_N>,<A_GREG_D>  */
148     { "cmveq",      {A_GREG_M,A_GREG_N,A_GREG_D},     {OFFSET_20,OFFSET_10,OFFSET_4}, 0x20010000
149     },
150 /* 001000mmmmmm0101nnnnnnwwwwww0000  cmvne <A_GREG_M>,<A_GREG_N>,<A_GREG_D>  */
151     { "cmvne",      {A_GREG_M,A_GREG_N,A_GREG_D},     {OFFSET_20,OFFSET_10,OFFSET_4}, 0x20050000
152     },
153 /* 000110gggggg0001ggggggffffff0000  fabs.d <A_DREG_G>,<A_DREG_F>  */
154     { "fabs.d",     {A_DREG_G,A_REUSE_PREV,A_DREG_F},    {OFFSET_20,OFFSET_10,OFFSET_4}, 0x18010000
155     },
156 /* 000110gggggg0000ggggggffffff0000  fabs.s <A_FREG_G>,<A_FREG_F>  */
157     { "fabs.s",     {A_FREG_G,A_REUSE_PREV,A_FREG_F},    {OFFSET_20,OFFSET_10,OFFSET_4}, 0x18000000
158     },
159 /* 001101gggggg0001hhhhhhffffff0000  fadd.s <A_DREG_G>,<A_DREG_H>,<A_DREG_F>  */
160     { "fadd.d",     {A_DREG_G,A_DREG_H,A_DREG_F},     {OFFSET_20,OFFSET_10,OFFSET_4}, 0x34010000
161     },
162 /* 001101gggggg0000hhhhhhffffff0000  fadd.s <A_FREG_G>,<A_FREG_H>,<A_FREG_F>  */
163     { "fadd.s",     {A_FREG_G,A_FREG_H,A_FREG_F},     {OFFSET_20,OFFSET_10,OFFSET_4}, 0x34000000
164     },
165 /* 001100gggggg1001hhhhhhdddddd0000  fcmpeq.s <A_DREG_G>,<A_DREG_H>,<A_GREG_D>  */
166     { "fcmpeq.d",   {A_DREG_G,A_DREG_H,A_GREG_D},     {OFFSET_20,OFFSET_10,OFFSET_4}, 0x30090000
167     },
168 /* 001100gggggg1000hhhhhhdddddd0000  fcmpeq.s <A_FREG_G>,<A_FREG_H>,<A_GREG_D>  */
169     { "fcmpeq.s",   {A_FREG_G,A_FREG_H,A_GREG_D},     {OFFSET_20,OFFSET_10,OFFSET_4}, 0x30080000
170     },
171 /* 001100gggggg1111hhhhhhdddddd0000  fcmpge.d <A_DREG_G>,<A_DREG_H>,<A_GREG_D>  */
172     { "fcmpge.d",   {A_DREG_G,A_DREG_H,A_GREG_D},     {OFFSET_20,OFFSET_10,OFFSET_4}, 0x300f0000
173     },
174 /* 001100gggggg1110hhhhhhdddddd0000  fcmpge.s <A_FREG_G>,<A_FREG_H>,<A_GREG_D>  */
175     { "fcmpge.s",   {A_FREG_G,A_FREG_H,A_GREG_D},     {OFFSET_20,OFFSET_10,OFFSET_4}, 0x300e0000
176     },
177 /* 001100gggggg1101hhhhhhdddddd0000  fcmpgt.d <A_DREG_G>,<A_DREG_H>,<A_GREG_D>  */
178     { "fcmpgt.d",   {A_DREG_G,A_DREG_H,A_GREG_D},     {OFFSET_20,OFFSET_10,OFFSET_4}, 0x300d0000
179     },
180 /* 001100gggggg1100hhhhhhdddddd0000  fcmpgt.s <A_FREG_G>,<A_FREG_H>,<A_GREG_D>  */
181     { "fcmpgt.s",   {A_FREG_G,A_FREG_H,A_GREG_D},     {OFFSET_20,OFFSET_10,OFFSET_4}, 0x300c0000
182     },
183 /* 001100gggggg1011hhhhhhdddddd0000  fcmpun.d <A_DREG_G>,<A_DREG_H>,<A_GREG_D>  */
184     { "fcmpun.d",   {A_DREG_G,A_DREG_H,A_GREG_D},     {OFFSET_20,OFFSET_10,OFFSET_4}, 0x300b0000
185     },
186 /* 001100gggggg1010hhhhhhdddddd0000  fcmpun.s <A_FREG_G>,<A_FREG_H>,<A_GREG_D>  */
187     { "fcmpun.s",   {A_FREG_G,A_FREG_H,A_GREG_D},     {OFFSET_20,OFFSET_10,OFFSET_4}, 0x300a0000
188     },
189 /* 001110gggggg0111ggggggffffff0000  fcnv.ds <A_DREG_G>,<A_FREG_F>  */
190     { "fcnv.ds",    {A_DREG_G,A_REUSE_PREV,A_FREG_F},    {OFFSET_20,OFFSET_10,OFFSET_4}, 0x38070000
191     },
192 /* 001110gggggg0110ggggggffffff0000  fcnv.sd <A_FREG_G>,<A_DREG_F>  */
193     { "fcnv.sd",    {A_FREG_G,A_REUSE_PREV,A_DREG_F},    {OFFSET_20,OFFSET_10,OFFSET_4}, 0x38060000
194     },
195 /* 001101gggggg0101hhhhhhffffff0000  fdiv.d <A_DREG_G>,<A_DREG_H>,<A_DREG_F>  */
196     { "fdiv.d",     {A_DREG_G,A_DREG_H,A_DREG_F},     {OFFSET_20,OFFSET_10,OFFSET_4}, 0x34050000
197     },
198 /* 001101gggggg0100hhhhhhffffff0000  fdiv.s <A_FREG_G>,<A_FREG_H>,<A_FREG_F>  */
199     { "fdiv.s",     {A_FREG_G,A_FREG_H,A_FREG_F},     {OFFSET_20,OFFSET_10,OFFSET_4}, 0x34040000
200     },
201 /* 0001111111110010111111ffffff0000  fgetscr <A_FREG_F>  */
202     { "fgetscr",    {A_FREG_F},                       {OFFSET_4}, 0x1ff2fc00
203     },
204 /* 000101gggggg0110hhhhhhffffff0000  fipr.s <A_FVREG_G>,<A_FVREG_H>,<A_FREG_F>  */
205     { "fipr.s",     {A_FVREG_G,A_FVREG_H,A_FREG_F},   {OFFSET_20,OFFSET_10,OFFSET_4}, 0x14060000
206     },
207 /* 100111mmmmmmssssssssssffffff0000  fld.d <A_GREG_M>,<A_IMMS10BY8>,<A_DREG_F>  */
208     { "fld.d",      {A_GREG_M,A_IMMS10BY8,A_DREG_F},  {OFFSET_20,OFFSET_10,OFFSET_4}, 0x9c000000
209     },
210 /* 100110mmmmmmssssssssssffffff0000  fld.p <A_GREG_M>,<A_IMMS10BY8>,<A_FPREG_F>  */
211     { "fld.p",      {A_GREG_M,A_IMMS10BY8,A_FPREG_F},  {OFFSET_20,OFFSET_10,OFFSET_4}, 0x98000000
212     },
213 /* 100101mmmmmmssssssssssffffff0000  fld.s <A_GREG_M>,<A_IMMS10BY4>,<A_FREG_F>  */
214     { "fld.s",      {A_GREG_M,A_IMMS10BY4,A_FREG_F},  {OFFSET_20,OFFSET_10,OFFSET_4}, 0x94000000
215     },
216 /* 000111mmmmmm1001nnnnnnffffff0000  fldx.d <A_GREG_M>,<A_GREG_N>,<A_DREG_F>  */
217     { "fldx.d",     {A_GREG_M,A_GREG_N,A_DREG_F},     {OFFSET_20,OFFSET_10,OFFSET_4}, 0x1c090000
218     },
219 /* 000111mmmmmm1101nnnnnnffffff0000  fldx.p <A_GREG_M>,<A_GREG_N>,<A_FPREG_F>  */
220     { "fldx.p",     {A_GREG_M,A_GREG_N,A_FPREG_F},     {OFFSET_20,OFFSET_10,OFFSET_4}, 0x1c0d0000
221     },
222 /* 000111mmmmmm1000nnnnnnffffff0000  fldx.s <A_GREG_M>,<A_GREG_N>,<A_FREG_F>  */
223     { "fldx.s",     {A_GREG_M,A_GREG_N,A_FREG_F},     {OFFSET_20,OFFSET_10,OFFSET_4}, 0x1c080000
224     },
225 /* 001110gggggg1110ggggggffffff0000  float.ld <A_FREG_G>,<A_DREG_F>  */
226     { "float.ld",   {A_FREG_G,A_REUSE_PREV,A_DREG_F},    {OFFSET_20,OFFSET_10,OFFSET_4}, 0x380e0000
227     },
228 /* 001110gggggg1100ggggggffffff0000  float.ls <A_FREG_G>,<A_FREG_F>  */
229     { "float.ls",   {A_FREG_G,A_REUSE_PREV,A_FREG_F},    {OFFSET_20,OFFSET_10,OFFSET_4}, 0x380c0000
230     },
231 /* 001110gggggg1101ggggggffffff0000  float.qd <A_DREG_G>,<A_DREG_F>  */
232     { "float.qd",   {A_DREG_G,A_REUSE_PREV,A_DREG_F},    {OFFSET_20,OFFSET_10,OFFSET_4}, 0x380d0000
233     },
234 /* 001110gggggg1111ggggggffffff0000  float.qs <A_DREG_G>,<A_FREG_F>  */
235     { "float.qs",   {A_DREG_G,A_REUSE_PREV,A_FREG_F},    {OFFSET_20,OFFSET_10,OFFSET_4}, 0x380f0000
236     },
237 /* 001101gggggg1110hhhhhhqqqqqq0000  fmac.s <A_FREG_G>,<A_FREG_H>,<A_FREG_F>  */
238     { "fmac.s",     {A_FREG_G,A_FREG_H,A_FREG_F},     {OFFSET_20,OFFSET_10,OFFSET_4}, 0x340e0000
239     },
240 /* 001110gggggg0001ggggggffffff0000  fmov.d <A_DREG_G>,<A_DREG_F>  */
241     { "fmov.d",     {A_DREG_G,A_REUSE_PREV,A_DREG_F},    {OFFSET_20,OFFSET_10,OFFSET_4}, 0x38010000
242     },
243 /* 001100gggggg0001ggggggdddddd0000  fmov.dq <A_DREG_G>,<A_GREG_D>  */
244     { "fmov.dq",    {A_DREG_G,A_REUSE_PREV,A_GREG_D},    {OFFSET_20,OFFSET_10,OFFSET_4}, 0x30010000
245     },
246 /* 000111mmmmmm0000111111ffffff0000  fmov.ls <A_GREG_M>,<A_FREG_F>  */
247     { "fmov.ls",    {A_GREG_M,A_FREG_F},              {OFFSET_20,OFFSET_4},           0x1c00fc00
248     },
249 /* 000111mmmmmm0001111111ffffff0000  fmov.qd <A_GREG_M>,<A_DREG_F>  */
250     { "fmov.qd",    {A_GREG_M,A_DREG_F},              {OFFSET_20,OFFSET_4},           0x1c01fc00
251     },
252 /* 001110gggggg0000ggggggffffff0000  fmov.s <A_FREG_G>,<A_FREG_F>  */
253     { "fmov.s",     {A_FREG_G,A_REUSE_PREV,A_FREG_F},    {OFFSET_20,OFFSET_10,OFFSET_4}, 0x38000000
254     },
255 /* 001100gggggg0000ggggggdddddd0000  fmov.sl <A_FREG_G>,<A_GREG_D>  */
256     { "fmov.sl",    {A_FREG_G,A_REUSE_PREV,A_GREG_D},    {OFFSET_20,OFFSET_10,OFFSET_4}, 0x30000000
257     },
258 /* 001101gggggg0111hhhhhhffffff0000  fmul.d <A_DREG_G>,<A_DREG_H>,<A_DREG_F>  */
259     { "fmul.d",     {A_DREG_G,A_DREG_H,A_DREG_F},     {OFFSET_20,OFFSET_10,OFFSET_4}, 0x34070000
260     },
261 /* 001101gggggg0110hhhhhhffffff0000  fmul.s <A_FREG_G>,<A_FREG_H>,<A_FREG_F>  */
262     { "fmul.s",     {A_FREG_G,A_FREG_H,A_FREG_F},     {OFFSET_20,OFFSET_10,OFFSET_4}, 0x34060000
263     },
264 /* 000110gggggg0011ggggggffffff0000  fneg.d <A_DREG_G>,<A_DREG_F>  */
265     { "fneg.d",     {A_DREG_G,A_REUSE_PREV,A_DREG_F},    {OFFSET_20,OFFSET_10,OFFSET_4}, 0x18030000
266     },
267 /* 000110gggggg0010ggggggffffff0000  fneg.s <A_FREG_G>,<A_FREG_F>  */
268     { "fneg.s",     {A_FREG_G,A_REUSE_PREV,A_FREG_F},    {OFFSET_20,OFFSET_10,OFFSET_4}, 0x18020000
269     },
270 /* 001100gggggg0010gggggg1111110000  fputscr <A_FREG_G>  */
271     { "fputscr",    {A_FREG_G,A_REUSE_PREV},          {OFFSET_20,OFFSET_10},          0x300203f0
272     },
273 /* 001110gggggg0101ggggggffffff0000  fsqrt.d <A_DREG_G>,<A_DREG_F>  */
274     { "fsqrt.d",    {A_DREG_G,A_REUSE_PREV,A_DREG_F},    {OFFSET_20,OFFSET_10,OFFSET_4}, 0x38050000
275     },
276 /* 001110gggggg0100ggggggffffff0000  fsqrt.s <A_FREG_G>,<A_FREG_F>  */
277     { "fsqrt.s",    {A_FREG_G,A_REUSE_PREV,A_FREG_F},    {OFFSET_20,OFFSET_10,OFFSET_4}, 0x38040000
278     },
279 /* 101111mmmmmmsssssssssszzzzzz0000  fst.d <A_GREG_M>,<A_IMMS10BY8>,<A_DREG_F>  */
280     { "fst.d",      {A_GREG_M,A_IMMS10BY8,A_DREG_F},  {OFFSET_20,OFFSET_10,OFFSET_4}, 0xbc000000
281     },
282 /* 101110mmmmmmsssssssssszzzzzz0000  fst.p <A_GREG_M>,<A_IMMS10BY8>,<A_FPREG_F>  */
283     { "fst.p",      {A_GREG_M,A_IMMS10BY8,A_FPREG_F},  {OFFSET_20,OFFSET_10,OFFSET_4}, 0xb8000000
284     },
285 /* 101101mmmmmmsssssssssszzzzzz0000  fst.s <A_GREG_M>,<A_IMMS10BY4>,<A_FREG_F>  */
286     { "fst.s",      {A_GREG_M,A_IMMS10BY4,A_FREG_F},  {OFFSET_20,OFFSET_10,OFFSET_4}, 0xb4000000
287     },
288 /* 001111mmmmmm1001nnnnnnzzzzzz0000  fstx.d <A_GREG_M>,<A_GREG_N>,<A_DREG_F>  */
289     { "fstx.d",     {A_GREG_M,A_GREG_N,A_DREG_F},     {OFFSET_20,OFFSET_10,OFFSET_4}, 0x3c090000
290     },
291 /* 001111mmmmmm1101nnnnnnzzzzzz0000  fstx.p <A_GREG_M>,<A_GREG_N>,<A_FPREG_F>  */
292     { "fstx.p",     {A_GREG_M,A_GREG_N,A_FPREG_F},     {OFFSET_20,OFFSET_10,OFFSET_4}, 0x3c0d0000
293     },
294 /* 001111mmmmmm1000nnnnnnzzzzzz0000  fstx.s <A_GREG_M>,<A_GREG_N>,<A_FREG_F>  */
295     { "fstx.s",     {A_GREG_M,A_GREG_N,A_FREG_F},     {OFFSET_20,OFFSET_10,OFFSET_4}, 0x3c080000
296     },
297 /* 001101gggggg0011hhhhhhffffff0000  fsub.d <A_DREG_G>,<A_DREG_H>,<A_DREG_F>  */
298     { "fsub.d",     {A_DREG_G,A_DREG_H,A_DREG_F},     {OFFSET_20,OFFSET_10,OFFSET_4}, 0x34030000
299     },
300 /* 001101gggggg0010hhhhhhffffff0000  fsub.s <A_FREG_G>,<A_FREG_H>,<A_FREG_F>  */
301     { "fsub.s",     {A_FREG_G,A_FREG_H,A_FREG_F},     {OFFSET_20,OFFSET_10,OFFSET_4}, 0x34020000
302     },
303 /* 001110gggggg1011ggggggffffff0000  ftrc.dl <A_DREG_G>,<A_FREG_F>  */
304     { "ftrc.dl",    {A_DREG_G,A_REUSE_PREV,A_FREG_F},    {OFFSET_20,OFFSET_10,OFFSET_4}, 0x380b0000
305     },
306 /* 001110gggggg1001ggggggffffff0000  ftrc.dq <A_DREG_G>,<A_DREG_F>  */
307     { "ftrc.dq",    {A_DREG_G,A_REUSE_PREV,A_DREG_F},    {OFFSET_20,OFFSET_10,OFFSET_4}, 0x38090000
308     },
309 /* 001110gggggg1000ggggggffffff0000  ftrc.sl <A_FREG_G>,<A_FREG_F>  */
310     { "ftrc.sl",    {A_FREG_G,A_REUSE_PREV,A_FREG_F},    {OFFSET_20,OFFSET_10,OFFSET_4}, 0x38080000
311     },
312 /* 001110gggggg1010ggggggffffff0000  ftrc.sq <A_FREG_G>,<A_DREG_F>  */
313     { "ftrc.sq",    {A_FREG_G,A_REUSE_PREV,A_DREG_F},    {OFFSET_20,OFFSET_10,OFFSET_4}, 0x380a0000
314     },
315 /* 000101gggggg1110hhhhhhffffff0000  ftrv.s <A_FMREG_G>,<A_FVREG_H>,<A_FVREG_F>  */
316     { "ftrv.s",     {A_FMREG_G,A_FVREG_H,A_FVREG_F},     {OFFSET_20,OFFSET_10,OFFSET_4}, 0x140e0000
317     },
318 /* 110000mmmmmm1111ssssssdddddd0000  getcfg <A_GREG_M>,<A_IMMS6>,<A_GREG_D>  */
319     { "getcfg",     {A_GREG_M,A_IMMS6,A_GREG_D},      {OFFSET_20,OFFSET_10,OFFSET_4}, 0xc00f0000
320     },
321 /* 001001kkkkkk1111111111dddddd0000  getcon <A_CREG_K>,<A_GREG_M>  */
322     { "getcon",     {A_CREG_K,A_GREG_D},              {OFFSET_20,OFFSET_4},           0x240ffc00
323     },
324 /* 010001rrrbbb0101111111dddddd0000  gettr <A_TREG_A>,<A_GREG_D>  */
325     { "gettr",      {A_TREG_B,A_GREG_D},              {OFFSET_20,OFFSET_4},           0x4405fc00
326     },
327 /* 111000mmmmmm0101ssssss1111110000  icbi <A_GREG_M>,<A_IMMS6BY32>  */
328     { "icbi",       {A_GREG_M,A_IMMS6BY32},           {OFFSET_20,OFFSET_10},          0xe00503f0
329     },
330 /* 100000mmmmmmssssssssssdddddd0000  ld.b <A_GREG_M>,<A_IMMS10BY1>,<A_GREG_D>  */
331     { "ld.b",       {A_GREG_M,A_IMMS10BY1,A_GREG_D},  {OFFSET_20,OFFSET_10,OFFSET_4}, 0x80000000
332     },
333 /* 100010mmmmmmssssssssssdddddd0000  ld.l <A_GREG_M>,<A_IMMS10BY4>,<A_GREG_D>  */
334     { "ld.l",       {A_GREG_M,A_IMMS10BY4,A_GREG_D},  {OFFSET_20,OFFSET_10,OFFSET_4}, 0x88000000
335     },
336 /* 100011mmmmmmssssssssssdddddd0000  ld.q <A_GREG_M>,<A_IMMS10BY8>,<A_GREG_D>  */
337     { "ld.q",       {A_GREG_M,A_IMMS10BY8,A_GREG_D},  {OFFSET_20,OFFSET_10,OFFSET_4}, 0x8c000000
338     },
339 /* 100100mmmmmmssssssssssdddddd0000  ld.ub <A_GREG_M>,<A_IMMS10BY1>,<A_GREG_D>  */
340     { "ld.ub",      {A_GREG_M,A_IMMS10BY1,A_GREG_D},  {OFFSET_20,OFFSET_10,OFFSET_4}, 0x90000000
341     },
342 /* 101100mmmmmmssssssssssdddddd0000  ld.uw <A_GREG_M>,<A_IMMS10BY2>,<A_GREG_D>  */
343     { "ld.uw",      {A_GREG_M,A_IMMS10BY2,A_GREG_D},  {OFFSET_20,OFFSET_10,OFFSET_4}, 0xb0000000
344     },
345 /* 100001mmmmmmssssssssssdddddd0000  ld.w <A_GREG_M>,<A_IMMS10BY2>,<A_GREG_D>  */
346     { "ld.w",       {A_GREG_M,A_IMMS10BY2,A_GREG_D},  {OFFSET_20,OFFSET_10,OFFSET_4}, 0x84000000
347     },
348 /* 110000mmmmmm0110ssssssdddddd0000  ldhi.l <A_GREG_M>,<A_IMMS6>,<A_GREG_D>  */
349     { "ldhi.l",     {A_GREG_M,A_IMMS6,A_GREG_D},      {OFFSET_20,OFFSET_10,OFFSET_4}, 0xc0060000
350     },
351 /* 110000mmmmmm0111ssssssdddddd0000  ldhi.q <A_GREG_M>,<A_IMMS6>,<A_GREG_D>  */
352     { "ldhi.q",     {A_GREG_M,A_IMMS6,A_GREG_D},      {OFFSET_20,OFFSET_10,OFFSET_4}, 0xc0070000
353     },
354 /* 110000mmmmmm0010ssssssdddddd0000  ldlo.l <A_GREG_M>,<A_IMMS6>,<A_GREG_D>  */
355     { "ldlo.l",     {A_GREG_M,A_IMMS6,A_GREG_D},      {OFFSET_20,OFFSET_10,OFFSET_4}, 0xc0020000
356     },
357 /* 110000mmmmmm0011ssssssdddddd0000  ldlo.q <A_GREG_M>,<A_IMMS6>,<A_GREG_D>  */
358     { "ldlo.q",     {A_GREG_M,A_IMMS6,A_GREG_D},      {OFFSET_20,OFFSET_10,OFFSET_4}, 0xc0030000
359     },
360 /* 010000mmmmmm0000nnnnnndddddd0000  ldx.b <A_GREG_M>,<A_GREG_N>,<A_GREG_D>  */
361     { "ldx.b",      {A_GREG_M,A_GREG_N,A_GREG_D},     {OFFSET_20,OFFSET_10,OFFSET_4}, 0x40000000
362     },
363 /* 010000mmmmmm0010nnnnnndddddd0000  ldx.l <A_GREG_M>,<A_GREG_N>,<A_GREG_D>  */
364     { "ldx.l",      {A_GREG_M,A_GREG_N,A_GREG_D},     {OFFSET_20,OFFSET_10,OFFSET_4}, 0x40020000
365     },
366 /* 010000mmmmmm0011nnnnnndddddd0000  ldx.q <A_GREG_M>,<A_GREG_N>,<A_GREG_D>  */
367     { "ldx.q",      {A_GREG_M,A_GREG_N,A_GREG_D},     {OFFSET_20,OFFSET_10,OFFSET_4}, 0x40030000
368     },
369 /* 010000mmmmmm0100nnnnnndddddd0000  ldx.ub <A_GREG_M>,<A_GREG_N>,<A_GREG_D>  */
370     { "ldx.ub",     {A_GREG_M,A_GREG_N,A_GREG_D},     {OFFSET_20,OFFSET_10,OFFSET_4}, 0x40040000
371     },
372 /* 010000mmmmmm0101nnnnnndddddd0000  ldx.uw <A_GREG_M>,<A_GREG_N>,<A_GREG_D>  */
373     { "ldx.uw",     {A_GREG_M,A_GREG_N,A_GREG_D},     {OFFSET_20,OFFSET_10,OFFSET_4}, 0x40050000
374     },
375 /* 010000mmmmmm0001nnnnnndddddd0000  ldx.w <A_GREG_M>,<A_GREG_N>,<A_GREG_D>  */
376     { "ldx.w",      {A_GREG_M,A_GREG_N,A_GREG_D},     {OFFSET_20,OFFSET_10,OFFSET_4}, 0x40010000
377     },
378 /* 001010mmmmmm1010111111dddddd0000  mabs.l <A_GREG_M>,<A_GREG_D>  */
379     { "mabs.l",     {A_GREG_M,A_GREG_D},              {OFFSET_20,OFFSET_4},           0x280afc00
380     },
381 /* 001010mmmmmm1001111111dddddd0000  mabs.w <A_GREG_M>,<A_GREG_D>  */
382     { "mabs.w",     {A_GREG_M,A_GREG_D},              {OFFSET_20,OFFSET_4},           0x2809fc00
383     },
384 /* 000010mmmmmm0010nnnnnndddddd0000  madd.l <A_GREG_M>,<A_GREG_N>,<A_GREG_D> */
385     { "madd.l",     {A_GREG_M,A_GREG_N,A_GREG_D},     {OFFSET_20,OFFSET_10,OFFSET_4}, 0x08020000
386     },
387 /* 000010mmmmmm0001nnnnnndddddd0000  madd.w <A_GREG_M>,<A_GREG_N>,<A_GREG_D>  */
388     { "madd.w",     {A_GREG_M,A_GREG_N,A_GREG_D},     {OFFSET_20,OFFSET_10,OFFSET_4}, 0x08010000
389     },
390 /* 000010mmmmmm0110nnnnnndddddd0000  madds.l <A_GREG_M>,<A_GREG_N>,<A_GREG_D>  */
391     { "madds.l",    {A_GREG_M,A_GREG_N,A_GREG_D},     {OFFSET_20,OFFSET_10,OFFSET_4}, 0x08060000
392     },
393 /* 000010mmmmmm0100nnnnnndddddd0000  madds.ub <A_GREG_M>,<A_GREG_N>,<A_GREG_D>  */
394     { "madds.ub",   {A_GREG_M,A_GREG_N,A_GREG_D},     {OFFSET_20,OFFSET_10,OFFSET_4}, 0x08040000
395     },
396 /* 000010mmmmmm0101nnnnnndddddd0000  madds.w <A_GREG_M>,<A_GREG_N>,<A_GREG_D>  */
397     { "madds.w",    {A_GREG_M,A_GREG_N,A_GREG_D},     {OFFSET_20,OFFSET_10,OFFSET_4}, 0x08050000
398     },
399 /* 001010mmmmmm0000nnnnnndddddd0000  mcmpeq.b <A_GREG_M>,<A_GREG_N>,<A_GREG_D>  */
400     { "mcmpeq.b",   {A_GREG_M,A_GREG_N,A_GREG_D},     {OFFSET_20,OFFSET_10,OFFSET_4}, 0x28000000
401     },
402 /* 001010mmmmmm0010nnnnnndddddd0000  mcmpeq.l <A_GREG_M>,<A_GREG_N>,<A_GREG_D>  */
403     { "mcmpeq.l",   {A_GREG_M,A_GREG_N,A_GREG_D},     {OFFSET_20,OFFSET_10,OFFSET_4}, 0x28020000
404     },
405 /* 001010mmmmmm0001nnnnnndddddd0000  mcmpeq.w <A_GREG_M>,<A_GREG_N>,<A_GREG_D>  */
406     { "mcmpeq.w",   {A_GREG_M,A_GREG_N,A_GREG_D},     {OFFSET_20,OFFSET_10,OFFSET_4}, 0x28010000
407     },
408 /* 001010mmmmmm0110nnnnnndddddd0000  mcmpgt.l <A_GREG_M>,<A_GREG_N>,<A_GREG_D>  */
409     { "mcmpgt.l",   {A_GREG_M,A_GREG_N,A_GREG_D},     {OFFSET_20,OFFSET_10,OFFSET_4}, 0x28060000
410     },
411 /* 001010mmmmmm0100nnnnnndddddd0000  mcmpgt.ub <A_GREG_M>,<A_GREG_N>,<A_GREG_D>  */
412     { "mcmpgt.ub",  {A_GREG_M,A_GREG_N,A_GREG_D},     {OFFSET_20,OFFSET_10,OFFSET_4}, 0x28040000
413     },
414 /* 001010mmmmmm0101nnnnnndddddd0000  mcmpgt.w <A_GREG_M>,<A_GREG_N>,<A_GREG_D>  */
415     { "mcmpgt.w",   {A_GREG_M,A_GREG_N,A_GREG_D},     {OFFSET_20,OFFSET_10,OFFSET_4}, 0x28050000
416     },
417 /* 010010mmmmmm0011nnnnnnwwwwww0000  mcmv <A_GREG_M>,<A_GREG_N>,<A_GREG_D>  */
418     { "mcmv",       {A_GREG_M,A_GREG_N,A_GREG_D},     {OFFSET_20,OFFSET_10,OFFSET_4}, 0x48030000
419     },
420 /* 010011mmmmmm1101nnnnnndddddd0000  mcnvs.lw <A_GREG_M>,<A_GREG_N>,<A_GREG_D>  */
421     { "mcnvs.lw",   {A_GREG_M,A_GREG_N,A_GREG_D},     {OFFSET_20,OFFSET_10,OFFSET_4}, 0x4c0d0000
422     },
423 /* 010011mmmmmm1000nnnnnndddddd0000  mcnvs.wb <A_GREG_M>,<A_GREG_N>,<A_GREG_D>  */
424     { "mcnvs.wb",   {A_GREG_M,A_GREG_N,A_GREG_D},     {OFFSET_20,OFFSET_10,OFFSET_4}, 0x4c080000
425     },
426 /* 010011mmmmmm1100nnnnnndddddd0000  mcnvs.wub <A_GREG_M>,<A_GREG_N>,<A_GREG_D>  */
427     { "mcnvs.wub",  {A_GREG_M,A_GREG_N,A_GREG_D},     {OFFSET_20,OFFSET_10,OFFSET_4}, 0x4c0c0000
428     },
429 /* 001010mmmmmm0111nnnnnndddddd0000  mextr1 <A_GREG_M>,<A_GREG_N>,<A_GREG_D>  */
430     { "mextr1",     {A_GREG_M,A_GREG_N,A_GREG_D},     {OFFSET_20,OFFSET_10,OFFSET_4}, 0x28070000
431     },
432 /* 001010mmmmmm1011nnnnnndddddd0000  mextr2 <A_GREG_M>,<A_GREG_N>,<A_GREG_D>  */
433     { "mextr2",     {A_GREG_M,A_GREG_N,A_GREG_D},     {OFFSET_20,OFFSET_10,OFFSET_4}, 0x280b0000
434     },
435 /* 001010mmmmmm1111nnnnnndddddd0000  mextr3 <A_GREG_M>,<A_GREG_N>,<A_GREG_D>  */
436     { "mextr3",     {A_GREG_M,A_GREG_N,A_GREG_D},     {OFFSET_20,OFFSET_10,OFFSET_4}, 0x280f0000
437     },
438 /* 001011mmmmmm0011nnnnnndddddd0000  mextr4 <A_GREG_M>,<A_GREG_N>,<A_GREG_D>  */
439     { "mextr4",     {A_GREG_M,A_GREG_N,A_GREG_D},     {OFFSET_20,OFFSET_10,OFFSET_4}, 0x2c030000
440     },
441 /* 001011mmmmmm0111nnnnnndddddd0000  mextr5 <A_GREG_M>,<A_GREG_N>,<A_GREG_D>  */
442     { "mextr5",     {A_GREG_M,A_GREG_N,A_GREG_D},     {OFFSET_20,OFFSET_10,OFFSET_4}, 0x2c070000
443     },
444 /* 001011mmmmmm1011nnnnnndddddd0000  mextr6 <A_GREG_M>,<A_GREG_N>,<A_GREG_D>  */
445     { "mextr6",     {A_GREG_M,A_GREG_N,A_GREG_D},     {OFFSET_20,OFFSET_10,OFFSET_4}, 0x2c0b0000
446     },
447 /* 001011mmmmmm1111nnnnnndddddd0000  mextr7 <A_GREG_M>,<A_GREG_N>,<A_GREG_D>  */
448     { "mextr7",     {A_GREG_M,A_GREG_N,A_GREG_D},     {OFFSET_20,OFFSET_10,OFFSET_4}, 0x2c0f0000
449     },
450 /* 010010mmmmmm0001nnnnnnwwwwww0000  mmacfx.wl <A_GREG_M>,<A_GREG_N>,<A_GREG_D>  */
451     { "mmacfx.wl",  {A_GREG_M,A_GREG_N,A_GREG_D},     {OFFSET_20,OFFSET_10,OFFSET_4}, 0x48010000
452     },
453 /* 010010mmmmmm0101nnnnnnwwwwww0000  mmacnfx.wl <A_GREG_M>,<A_GREG_N>,<A_GREG_D>  */
454     { "mmacnfx.wl", {A_GREG_M,A_GREG_N,A_GREG_D},     {OFFSET_20,OFFSET_10,OFFSET_4}, 0x48050000
455     },
456 /* 010011mmmmmm0010nnnnnndddddd0000  mmul.l <A_GREG_M>,<A_GREG_N>,<A_GREG_D>  */
457     { "mmul.l",     {A_GREG_M,A_GREG_N,A_GREG_D},     {OFFSET_20,OFFSET_10,OFFSET_4}, 0x4c020000
458     },
459 /* 010011mmmmmm0001nnnnnndddddd0000  mmul.m <A_GREG_M>,<A_GREG_N>,<A_GREG_D>  */
460     { "mmul.w",     {A_GREG_M,A_GREG_N,A_GREG_D},     {OFFSET_20,OFFSET_10,OFFSET_4}, 0x4c010000
461     },
462 /* 010011mmmmmm0110nnnnnndddddd0000  mmulfx.l <A_GREG_M>,<A_GREG_N>,<A_GREG_D>  */
463     { "mmulfx.l",   {A_GREG_M,A_GREG_N,A_GREG_D},     {OFFSET_20,OFFSET_10,OFFSET_4}, 0x4c060000
464     },
465 /* 010011mmmmmm0101nnnnnndddddd0000  mmulfx.w <A_GREG_M>,<A_GREG_N>,<A_GREG_D>  */
466     { "mmulfx.w",   {A_GREG_M,A_GREG_N,A_GREG_D},     {OFFSET_20,OFFSET_10,OFFSET_4}, 0x4c050000
467     },
468 /* 010011mmmmmm1001nnnnnndddddd0000  mmulfxrp.w <A_GREG_M>,<A_GREG_N>,<A_GREG_D>  */
469     { "mmulfxrp.w", {A_GREG_M,A_GREG_N,A_GREG_D},     {OFFSET_20,OFFSET_10,OFFSET_4}, 0x4c090000
470     },
471 /* 010011mmmmmm1110nnnnnndddddd0000  mmulhi.wl <A_GREG_M>,<A_GREG_N>,<A_GREG_D>  */
472     { "mmulhi.wl",  {A_GREG_M,A_GREG_N,A_GREG_D},     {OFFSET_20,OFFSET_10,OFFSET_4}, 0x4c0e0000
473     },
474 /* 010011mmmmmm1010nnnnnndddddd0000  mmullo.wl <A_GREG_M>,<A_GREG_N>,<A_GREG_D>  */
475     { "mmullo.wl",  {A_GREG_M,A_GREG_N,A_GREG_D},     {OFFSET_20,OFFSET_10,OFFSET_4}, 0x4c0a0000
476     },
477 /* 010010mmmmmm1001nnnnnnwwwwww0000  mmulsum.wq <A_GREG_M>,<A_GREG_N>,<A_GREG_D>  */
478     { "mmulsum.wq", {A_GREG_M,A_GREG_N,A_GREG_D},     {OFFSET_20,OFFSET_10,OFFSET_4}, 0x48090000
479     },
480 /* 110011ssssssssssssssssdddddd0000  movi <A_IMMS16>,<A_GREG_D>  */
481     { "movi",       {A_IMMS16,A_GREG_D}, {OFFSET_10,OFFSET_4}, SHMEDIA_MOVI_OPC
482     },
483 /* 001010mmmmmm1101nnnnnndddddd0000  mperm.w <A_GREG_M>,<A_GREG_N>,<A_GREG_D>  */
484     { "mperm.w",    {A_GREG_M,A_GREG_N,A_GREG_D},     {OFFSET_20,OFFSET_10,OFFSET_4}, 0x280d0000
485     },
486 /* 010010mmmmmm0000nnnnnnwwwwww0000  msad.ubq <A_GREG_M>,<A_GREG_N>,<A_GREG_D>  */
487     { "msad.ubq",   {A_GREG_M,A_GREG_N,A_GREG_D},     {OFFSET_20,OFFSET_10,OFFSET_4}, 0x48000000
488     },
489 /* 000011mmmmmm1010nnnnnndddddd0000  mshard.l <A_GREG_M>,<A_GREG_N>,<A_GREG_D>  */
490     { "mshard.l",   {A_GREG_M,A_GREG_N,A_GREG_D},     {OFFSET_20,OFFSET_10,OFFSET_4}, 0x0c0a0000
491     },
492 /* 000011mmmmmm1001nnnnnndddddd0000  mshard.w <A_GREG_M>,<A_GREG_N>,<A_GREG_D>  */
493     { "mshard.w",   {A_GREG_M,A_GREG_N,A_GREG_D},     {OFFSET_20,OFFSET_10,OFFSET_4}, 0x0c090000
494     },
495 /* 000011mmmmmm1011nnnnnndddddd0000  mshards.q <A_GREG_M>,<A_GREG_N>,<A_GREG_D>  */
496     { "mshards.q",  {A_GREG_M,A_GREG_N,A_GREG_D},     {OFFSET_20,OFFSET_10,OFFSET_4}, 0x0c0b0000
497     },
498 /* 001011mmmmmm0100nnnnnndddddd0000  mshfhi.b <A_GREG_M>,<A_GREG_N>,<A_GREG_D>  */
499     { "mshfhi.b",   {A_GREG_M,A_GREG_N,A_GREG_D},     {OFFSET_20,OFFSET_10,OFFSET_4}, 0x2c040000
500     },
501 /* 001011mmmmmm0110nnnnnndddddd0000  mshfhi.l <A_GREG_M>,<A_GREG_N>,<A_GREG_D>  */
502     { "mshfhi.l",   {A_GREG_M,A_GREG_N,A_GREG_D},     {OFFSET_20,OFFSET_10,OFFSET_4}, 0x2c060000
503     },
504 /* 001011mmmmmm0101nnnnnndddddd0000  mshfhi.w <A_GREG_M>,<A_GREG_N>,<A_GREG_D>  */
505     { "mshfhi.w",   {A_GREG_M,A_GREG_N,A_GREG_D},     {OFFSET_20,OFFSET_10,OFFSET_4}, 0x2c050000
506     },
507 /* 001011mmmmmm0000nnnnnndddddd0000  mshflo.b <A_GREG_M>,<A_GREG_N>,<A_GREG_D>  */
508     { "mshflo.b",   {A_GREG_M,A_GREG_N,A_GREG_D},     {OFFSET_20,OFFSET_10,OFFSET_4}, 0x2c000000
509     },
510 /* 001011mmmmmm0010nnnnnndddddd0000  mshflo.l <A_GREG_M>,<A_GREG_N>,<A_GREG_D>  */
511     { "mshflo.l",   {A_GREG_M,A_GREG_N,A_GREG_D},     {OFFSET_20,OFFSET_10,OFFSET_4}, 0x2c020000
512     },
513 /* 001011mmmmmm0001nnnnnndddddd0000  mshflo.w <A_GREG_M>,<A_GREG_N>,<A_GREG_D>  */
514     { "mshflo.w",   {A_GREG_M,A_GREG_N,A_GREG_D},     {OFFSET_20,OFFSET_10,OFFSET_4}, 0x2c010000
515     },
516 /* 000011mmmmmm0010nnnnnndddddd0000  mshlld.l <A_GREG_M>,<A_GREG_N>,<A_GREG_D>  */
517     { "mshlld.l",   {A_GREG_M,A_GREG_N,A_GREG_D},     {OFFSET_20,OFFSET_10,OFFSET_4}, 0x0c020000
518     },
519 /* 000011mmmmmm0001nnnnnndddddd0000  mshlld.w <A_GREG_M>,<A_GREG_N>,<A_GREG_D>  */
520     { "mshlld.w",   {A_GREG_M,A_GREG_N,A_GREG_D},     {OFFSET_20,OFFSET_10,OFFSET_4}, 0x0c010000
521     },
522 /* 000011mmmmmm0110nnnnnndddddd0000  mshalds.l <A_GREG_M>,<A_GREG_N>,<A_GREG_D>  */
523     { "mshalds.l",  {A_GREG_M,A_GREG_N,A_GREG_D},     {OFFSET_20,OFFSET_10,OFFSET_4}, 0x0c060000
524     },
525 /* 000011mmmmmm0101nnnnnndddddd0000  mshalds.w <A_GREG_M>,<A_GREG_N>,<A_GREG_D>  */
526     { "mshalds.w",  {A_GREG_M,A_GREG_N,A_GREG_D},     {OFFSET_20,OFFSET_10,OFFSET_4}, 0x0c050000
527     },
528 /* 000011mmmmmm1110nnnnnndddddd0000  mshlrd.l <A_GREG_M>,<A_GREG_N>,<A_GREG_D>  */
529     { "mshlrd.l",   {A_GREG_M,A_GREG_N,A_GREG_D},     {OFFSET_20,OFFSET_10,OFFSET_4}, 0x0c0e0000
530     },
531 /* 000011mmmmmm1101nnnnnndddddd0000  mshlrd.w <A_GREG_M>,<A_GREG_N>,<A_GREG_D>  */
532     { "mshlrd.w",   {A_GREG_M,A_GREG_N,A_GREG_D},     {OFFSET_20,OFFSET_10,OFFSET_4}, 0x0c0d0000
533     },
534 /* 000010mmmmmm1010nnnnnndddddd0000  msub.l <A_GREG_M>,<A_GREG_N>,<A_GREG_D>  */
535     { "msub.l",     {A_GREG_M,A_GREG_N,A_GREG_D},     {OFFSET_20,OFFSET_10,OFFSET_4}, 0x080a0000
536     },
537 /* 000010mmmmmm1001nnnnnndddddd0000  msub.w <A_GREG_M>,<A_GREG_N>,<A_GREG_D>  */
538     { "msub.w",     {A_GREG_M,A_GREG_N,A_GREG_D},     {OFFSET_20,OFFSET_10,OFFSET_4}, 0x08090000
539     },
540 /* 000010mmmmmm1110nnnnnndddddd0000  msubs.l <A_GREG_M>,<A_GREG_N>,<A_GREG_D>  */
541     { "msubs.l",    {A_GREG_M,A_GREG_N,A_GREG_D},     {OFFSET_20,OFFSET_10,OFFSET_4}, 0x080e0000
542     },
543 /* 000010mmmmmm1100nnnnnndddddd0000  msubs.ub <A_GREG_M>,<A_GREG_N>,<A_GREG_D>  */
544     { "msubs.ub",   {A_GREG_M,A_GREG_N,A_GREG_D},     {OFFSET_20,OFFSET_10,OFFSET_4}, 0x080c0000
545     },
546 /* 000010mmmmmm1101nnnnnndddddd0000  msubs.w <A_GREG_M>,<A_GREG_N>,<A_GREG_D>  */
547     { "msubs.w",    {A_GREG_M,A_GREG_N,A_GREG_D},     {OFFSET_20,OFFSET_10,OFFSET_4}, 0x080d0000
548     },
549 /* 000001mmmmmm1110nnnnnndddddd0000  muls.l <A_GREG_M>,<A_GREG_N>,<A_GREG_D>  */
550     { "muls.l",     {A_GREG_M,A_GREG_N,A_GREG_D},     {OFFSET_20,OFFSET_10,OFFSET_4}, 0x040e0000
551     },
552 /* 000000mmmmmm1110nnnnnndddddd0000  mulu.l <A_GREG_M>,<A_GREG_N>,<A_GREG_D>  */
553     { "mulu.l",     {A_GREG_M,A_GREG_N,A_GREG_D},     {OFFSET_20,OFFSET_10,OFFSET_4}, 0x000e0000
554     },
555 /* 01101111111100001111111111110000  nop   */
556     { "nop",        {A_NONE},                         {OFFSET_NONE},
557       SHMEDIA_NOP_OPC
558     },
559 /* 000000mmmmmm1101111111dddddd0000  nsb <A_GREG_M>,<A_GREG_D>   */
560     { "nsb",        {A_GREG_M,A_GREG_D},              {OFFSET_20,OFFSET_4},           0x000dfc00
561     },
562 /* 111000mmmmmm1001ssssss1111110000  ocbi <A_GREG_M>,<A_IMMS6BY32>  */
563     { "ocbi",       {A_GREG_M,A_IMMS6BY32},           {OFFSET_20,OFFSET_10},          0xe00903f0
564     },
565 /* 111000mmmmmm1000ssssss1111110000  ocbp <A_GREG_M>,<A_IMMS6BY32>  */
566     { "ocbp",       {A_GREG_M,A_IMMS6BY32},           {OFFSET_20,OFFSET_10},          0xe00803f0
567     },
568 /* 111000mmmmmm1100ssssss1111110000  ocbwb <A_GREG_M>,<A_IMMS6BY32>  */
569     { "ocbwb",      {A_GREG_M,A_IMMS6BY32},           {OFFSET_20,OFFSET_10},          0xe00c03f0
570     },
571 /* 000001mmmmmm1001nnnnnndddddd0000  or <A_GREG_M>,<A_GREG_N>,<A_GREG_D>  */
572     { "or",         {A_GREG_M,A_GREG_N,A_GREG_D},     {OFFSET_20,OFFSET_10,OFFSET_4}, 0x04090000
573     },
574 /* 110111mmmmmmssssssssssdddddd0000  ori <A_GREG_M>,<A_IMMS10>,<A_GREG_D>  */
575     { "ori",        {A_GREG_M,A_IMMS10,A_GREG_D},     {OFFSET_20,OFFSET_10,OFFSET_4}, 0xdc000000
576     },
577 /* 111000mmmmmm0001ssssss1111110000  prefi <A_GREG_M>,<A_IMMS6BY32>  */
578     { "prefi",      {A_GREG_M,A_IMMS6BY32},           {OFFSET_20,OFFSET_10},          0xe00103f0
579     },
580 /* 111010sssssssssssssssslrraaa0000  pta <A_PCIMMS16BY4>,<A_TREG_A>  */
581     { "pta/l",      {A_PCIMMS16BY4,A_TREG_A}, {OFFSET_10,OFFSET_4},
582       SHMEDIA_PTA_OPC | SHMEDIA_LIKELY_BIT
583     },
584 /* 111010sssssssssssssssslrraaa0000  pta <A_PCIMMS16BY4>,<A_TREG_A>  */
585     { "pta",        {A_PCIMMS16BY4,A_TREG_A}, {OFFSET_10,OFFSET_4},
586       SHMEDIA_PTA_OPC | SHMEDIA_LIKELY_BIT
587     },
588 /* 111010ssssssssssssssss0rraaa0000  pta/u <A_PCIMMS16BY4>,<A_TREG_A>  */
589     { "pta/u",      {A_PCIMMS16BY4,A_TREG_A}, {OFFSET_10,OFFSET_4},
590       SHMEDIA_PTA_OPC
591     },
592 /* 0110101111110001nnnnnnl00aaa0000  ptabs <A_GREG_M>,<A_TREG_A>  */
593     { "ptabs/l",    {A_GREG_N,A_TREG_A},      {OFFSET_10,OFFSET_4}, 0x6bf10200
594     },
595 /* 0110101111110001nnnnnnl00aaa0000  ptabs <A_GREG_M>,<A_TREG_A>  */
596     { "ptabs",      {A_GREG_N,A_TREG_A},      {OFFSET_10,OFFSET_4}, 0x6bf10200
597     },
598 /* 0110101111110001nnnnnn000aaa0000  ptabs/u <A_GREG_M>,<A_TREG_A>  */
599     { "ptabs/u",    {A_GREG_N,A_TREG_A},      {OFFSET_10,OFFSET_4}, 0x6bf10000
600     },
601 /* 111011sssssssssssssssslrraaa0000  ptb <A_PCIMMS16BY4>,<A_TREG_A>  */
602     { "ptb/l",      {A_PCIMMS16BY4,A_TREG_A}, {OFFSET_10,OFFSET_4},
603       SHMEDIA_PTB_OPC | SHMEDIA_LIKELY_BIT
604     },
605 /* 111011sssssssssssssssslrraaa0000  ptb <A_PCIMMS16BY4>,<A_TREG_A>  */
606     { "ptb",        {A_PCIMMS16BY4,A_TREG_A}, {OFFSET_10,OFFSET_4},
607       SHMEDIA_PTB_OPC | SHMEDIA_LIKELY_BIT
608     },
609 /* 111011ssssssssssssssss0rraaa0000  ptb/u <A_PCIMMS16BY4>,<A_TREG_A>  */
610     { "ptb/u",      {A_PCIMMS16BY4,A_TREG_A}, {OFFSET_10,OFFSET_4},
611       SHMEDIA_PTB_OPC
612     },
613 /* 111010sssssssssssssssslrraaa0000  pt/l <A_PCIMMS16BY4>,<A_TREG_A>  */
614     { "pt/l",       {A_PCIMMS16BY4_PT,A_TREG_A},
615       {OFFSET_10,OFFSET_4}, SHMEDIA_PT_OPC | SHMEDIA_LIKELY_BIT
616     },
617 /* 111010sssssssssssssssslrraaa0000  pt <A_PCIMMS16BY4>,<A_TREG_A>  */
618     { "pt",         {A_PCIMMS16BY4_PT,A_TREG_A},
619       {OFFSET_10,OFFSET_4}, SHMEDIA_PT_OPC | SHMEDIA_LIKELY_BIT
620     },
621 /* 111010ssssssssssssssss0rraaa0000  pt/u <A_PCIMMS16BY4>,<A_TREG_A>  */
622     { "pt/u",       {A_PCIMMS16BY4_PT,A_TREG_A},
623       {OFFSET_10,OFFSET_4}, SHMEDIA_PT_OPC
624     },
625 /* 0110101111110101nnnnnnl00aaa0000  ptrel <A_GREG_M>,<A_TREG_A>  */
626     { "ptrel/l",    {A_GREG_N,A_TREG_A},      {OFFSET_10,OFFSET_4},
627       SHMEDIA_PTREL_OPC | SHMEDIA_LIKELY_BIT
628     },
629 /* 0110101111110101nnnnnnl00aaa0000  ptrel <A_GREG_M>,<A_TREG_A>  */
630     { "ptrel",      {A_GREG_N,A_TREG_A},      {OFFSET_10,OFFSET_4},
631       SHMEDIA_PTREL_OPC | SHMEDIA_LIKELY_BIT
632     },
633 /* 0110101111110101nnnnnn000aaa0000  ptrel/u <A_GREG_M>,<A_TREG_A>  */
634     { "ptrel/u",    {A_GREG_N,A_TREG_A},      {OFFSET_10,OFFSET_4},
635       SHMEDIA_PTREL_OPC
636     },
637 /* 111000mmmmmm1111ssssssyyyyyy0000  putcfg <A_GREG_M>,<A_IMMS6>,<A_GREG_D>  */
638     { "putcfg",     {A_GREG_M,A_IMMS6,A_GREG_D},      {OFFSET_20,OFFSET_10,OFFSET_4}, 0xe00f0000
639     },
640 /* 011011mmmmmm1111111111jjjjjj0000  putcon <A_GREG_M>,<A_CREG_J>  */
641     { "putcon",     {A_GREG_M,A_CREG_J},      {OFFSET_20,OFFSET_4}, 0x6c0ffc00
642     },
643 /* 01101111111100111111111111110000  rte   */
644     { "rte",        {A_NONE},                 {OFFSET_NONE},        0x6ff3fff0
645     },
646 /* 000001mmmmmm0111nnnnnndddddd0000  shard <A_GREG_M>,<A_GREG_N>,<A_GREG_D>  */
647     { "shard",      {A_GREG_M,A_GREG_N,A_GREG_D},     {OFFSET_20,OFFSET_10,OFFSET_4}, 0x04070000
648     },
649 /* 000001mmmmmm0110nnnnnndddddd0000  shard.l <A_GREG_M>,<A_GREG_N>,<A_GREG_D>  */
650     { "shard.l",    {A_GREG_M,A_GREG_N,A_GREG_D},     {OFFSET_20,OFFSET_10,OFFSET_4}, 0x04060000
651     },
652 /* 110001mmmmmm0111ssssssdddddd0000  shari <A_GREG_M>,<A_IMMU6>,<A_GREG_D>  */
653     { "shari",      {A_GREG_M,A_IMMU6,A_GREG_D},      {OFFSET_20,OFFSET_10,OFFSET_4}, 0xc4070000
654     },
655 /* 110001mmmmmm0110ssssssdddddd0000  shari <A_GREG_M>,<A_IMMU6>,<A_GREG_D>  */
656     { "shari.l",    {A_GREG_M,A_IMMU6,A_GREG_D},      {OFFSET_20,OFFSET_10,OFFSET_4}, 0xc4060000
657     },
658 /* 000001mmmmmm0001nnnnnndddddd0000  shlld <A_GREG_M>,<A_GREG_N>,<A_GREG_D>  */
659     { "shlld",      {A_GREG_M,A_GREG_N,A_GREG_D},     {OFFSET_20,OFFSET_10,OFFSET_4}, 0x04010000
660     },
661 /* 000001mmmmmm0000nnnnnndddddd0000  shlld.l <A_GREG_M>,<A_GREG_N>,<A_GREG_D>  */
662     { "shlld.l",    {A_GREG_M,A_GREG_N,A_GREG_D},     {OFFSET_20,OFFSET_10,OFFSET_4}, 0x04000000
663     },
664 /* 110001mmmmmm0001ssssssdddddd0000  shlli <A_GREG_M>,<A_IMMU6>,<A_GREG_D>  */
665     { "shlli",      {A_GREG_M,A_IMMU6,A_GREG_D},      {OFFSET_20,OFFSET_10,OFFSET_4}, 0xc4010000
666     },
667 /* 110001mmmmmm0000ssssssdddddd0000  shlli.l <A_GREG_M>,<A_IMMU5>,<A_GREG_D>  */
668     { "shlli.l",    {A_GREG_M,A_IMMU5,A_GREG_D},      {OFFSET_20,OFFSET_10,OFFSET_4}, 0xc4000000
669     },
670 /* 000001mmmmmm0011nnnnnndddddd0000  shlrd <A_GREG_M>,<A_GREG_N>,<A_GREG_D>  */
671     { "shlrd",      {A_GREG_M,A_GREG_N,A_GREG_D},     {OFFSET_20,OFFSET_10,OFFSET_4}, 0x04030000
672     },
673 /* 000001mmmmmm0010nnnnnndddddd0000  shlrd.l <A_GREG_M>,<A_GREG_N>,<A_GREG_D>  */
674     { "shlrd.l",    {A_GREG_M,A_GREG_N,A_GREG_D},     {OFFSET_20,OFFSET_10,OFFSET_4}, 0x04020000
675     },
676 /* 110001mmmmmm0011ssssssdddddd0000  shlri <A_GREG_M>,<A_IMMU6>,<A_GREG_D>  */
677     { "shlri",      {A_GREG_M,A_IMMU6,A_GREG_D},      {OFFSET_20,OFFSET_10,OFFSET_4}, 0xc4030000
678     },
679 /* 110001mmmmmm0010ssssssdddddd0000  shlri.l <A_GREG_M>,<A_IMMU5>,<A_GREG_D>  */
680     { "shlri.l",    {A_GREG_M,A_IMMU5,A_GREG_D},      {OFFSET_20,OFFSET_10,OFFSET_4}, 0xc4020000
681     },
682 /* 110010sssssssssssssssswwwwww0000  shori <A_IMMU16>,<A_GREG_D>  */
683     { "shori",      {A_IMMU16,A_GREG_D}, {OFFSET_10,OFFSET_4}, SHMEDIA_SHORI_OPC
684     },
685 /* 01101111111101111111111111110000  sleep   */
686     { "sleep",      {A_NONE},            {OFFSET_NONE}, 0x6ff7fff0
687     },
688 /* 101000mmmmmmssssssssssdddddd0000  st.b <A_GREG_M>,<A_IMMS10BY1>,<A_GREG_D>  */
689     { "st.b",       {A_GREG_M,A_IMMS10BY1,A_GREG_D},  {OFFSET_20,OFFSET_10,OFFSET_4}, 0xa0000000
690     },
691 /* 101010mmmmmmssssssssssdddddd0000  st.l <A_GREG_M>,<A_IMMS10BY4>,<A_GREG_D>  */
692     { "st.l",       {A_GREG_M,A_IMMS10BY4,A_GREG_D},  {OFFSET_20,OFFSET_10,OFFSET_4}, 0xa8000000
693     },
694 /* 101011mmmmmmssssssssssdddddd0000  st.q <A_GREG_M>,<A_IMMS10BY8>,<A_GREG_D>  */
695     { "st.q",       {A_GREG_M,A_IMMS10BY8,A_GREG_D},  {OFFSET_20,OFFSET_10,OFFSET_4}, 0xac000000
696     },
697 /* 101001mmmmmmssssssssssdddddd0000  st.w <A_GREG_M>,<A_IMMS10BY2>,<A_GREG_D>  */
698     { "st.w",       {A_GREG_M,A_IMMS10BY2,A_GREG_D},  {OFFSET_20,OFFSET_10,OFFSET_4}, 0xa4000000
699     },
700 /* 111000mmmmmm0110ssssssdddddd0000  sthi.l <A_GREG_M>,<A_IMMS6>,<A_GREG_D>  */
701     { "sthi.l",     {A_GREG_M,A_IMMS6,A_GREG_D},      {OFFSET_20,OFFSET_10,OFFSET_4}, 0xe0060000
702     },
703 /* 111000mmmmmm0111ssssssdddddd0000  sthi.q <A_GREG_M>,<A_IMMS6>,<A_GREG_D>  */
704     { "sthi.q",     {A_GREG_M,A_IMMS6,A_GREG_D},      {OFFSET_20,OFFSET_10,OFFSET_4}, 0xe0070000
705     },
706 /* 111000mmmmmm0010ssssssdddddd0000  stlo.l <A_GREG_M>,<A_IMMS6>,<A_GREG_D>  */
707     { "stlo.l",     {A_GREG_M,A_IMMS6,A_GREG_D},      {OFFSET_20,OFFSET_10,OFFSET_4}, 0xe0020000
708     },
709 /* 111000mmmmmm0011ssssssdddddd0000  stlo.q <A_GREG_M>,<A_IMMS6>,<A_GREG_D>  */
710     { "stlo.q",     {A_GREG_M,A_IMMS6,A_GREG_D},      {OFFSET_20,OFFSET_10,OFFSET_4}, 0xe0030000
711     },
712 /* 011000mmmmmm0000nnnnnndddddd0000  stx.b <A_GREG_M>,<A_GREG_N>,<A_GREG_D>  */
713     { "stx.b",      {A_GREG_M,A_GREG_N,A_GREG_D},     {OFFSET_20,OFFSET_10,OFFSET_4}, 0x60000000
714     },
715 /* 011000mmmmmm0010nnnnnndddddd0000  stx.l <A_GREG_M>,<A_GREG_N>,<A_GREG_D>  */
716     { "stx.l",      {A_GREG_M,A_GREG_N,A_GREG_D},     {OFFSET_20,OFFSET_10,OFFSET_4}, 0x60020000
717     },
718 /* 011000mmmmmm0011nnnnnndddddd0000  stx.q <A_GREG_M>,<A_GREG_N>,<A_GREG_D>  */
719     { "stx.q",      {A_GREG_M,A_GREG_N,A_GREG_D},     {OFFSET_20,OFFSET_10,OFFSET_4}, 0x60030000
720     },
721 /* 011000mmmmmm0001nnnnnndddddd0000  stx.w <A_GREG_M>,<A_GREG_N>,<A_GREG_D>  */
722     { "stx.w",      {A_GREG_M,A_GREG_N,A_GREG_D},     {OFFSET_20,OFFSET_10,OFFSET_4}, 0x60010000
723     },
724 /* 000000mmmmmm1011nnnnnndddddd0000  sub <A_GREG_M>,<A_GREG_N>,<A_GREG_D>  */
725     { "sub",        {A_GREG_M,A_GREG_N,A_GREG_D},     {OFFSET_20,OFFSET_10,OFFSET_4}, 0x000b0000
726     },
727 /* 000000mmmmmm1010nnnnnndddddd0000  sub.l <A_GREG_M>,<A_GREG_N>,<A_GREG_D>  */
728     { "sub.l",      {A_GREG_M,A_GREG_N,A_GREG_D},     {OFFSET_20,OFFSET_10,OFFSET_4}, 0x000a0000
729     },
730 /* 001000mmmmmm0011nnnnnnwwwwww0000  swap.q <A_GREG_M>,<A_GREG_N>,<A_GREG_D>  */
731     { "swap.q",     {A_GREG_M,A_GREG_N,A_GREG_D},     {OFFSET_20,OFFSET_10,OFFSET_4}, 0x20030000
732     },
733 /* 01101111111100101111111111110000  synci   */
734     { "synci",      {A_NONE},                         {OFFSET_NONE},                  0x6ff2fff0
735     },
736 /* 01101111111101101111111111110000  synco   */
737     { "synco",      {A_NONE},                         {OFFSET_NONE},                  0x6ff6fff0
738     },
739 /* 011011mmmmmm00011111111111110000  trapa <A_GREG_M>   */
740     { "trapa",      {A_GREG_M},                       {OFFSET_20}, 0x6c01fff0
741     },
742 /* 000001mmmmmm1101nnnnnndddddd0000  xor <A_GREG_M>,<A_GREG_N>,<A_GREG_D>  */
743     { "xor",        {A_GREG_M,A_GREG_N,A_GREG_D},     {OFFSET_20,OFFSET_10,OFFSET_4}, 0x040d0000
744     },
745 /* 110001mmmmmm1101ssssssdddddd0000  xori <A_GREG_M>,<A_IMMS6>,<A_GREG_D>  */
746     { "xori",       {A_GREG_M,A_IMMS6,A_GREG_D},      {OFFSET_20,OFFSET_10,OFFSET_4}, 0xc40d0000
747     },
748
749     { NULL, {}, {}, 0 }
750 };
751
752 /* Predefined control register names as per SH-5/ST50-005-08.  */
753 const shmedia_creg_info shmedia_creg_table[] = {
754   { 0, "sr" },
755   { 1, "ssr" },
756   { 2, "pssr" },
757
758   { 4, "intevt" },
759   { 5, "expevt" },
760   { 6, "pexpevt" },
761   { 7, "tra" },
762   { 8, "spc" },
763   { 9, "pspc" },
764   { 10, "resvec" },
765   { 11, "vbr" },
766
767   { 13, "tea" },
768
769   { 16, "dcr" },
770   { 17, "kcr0" },
771   { 18, "kcr1" },
772
773   { 62, "ctc" },
774   { 63, "usr" },
775   { -1, (char *) 0 }
776 };
777