1 /* s12z-dis.c -- Freescale S12Z disassembly
2 Copyright (C) 2018 Free Software Foundation, Inc.
4 This file is part of the GNU opcodes library.
6 This library is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 3, or (at your option)
11 It is distributed in the hope that it will be useful, but WITHOUT
12 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
13 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
14 License for more details.
16 You should have received a copy of the GNU General Public License
17 along with this program; if not, write to the Free Software
18 Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
19 MA 02110-1301, USA. */
27 #include "opcode/s12z.h"
33 #include "disassemble.h"
36 read_memory (bfd_vma memaddr, bfd_byte* buffer, int size,
37 struct disassemble_info* info)
39 int status = (*info->read_memory_func) (memaddr, buffer, size, info);
42 (*info->memory_error_func) (status, memaddr, info);
48 typedef int (* insn_bytes_f) (bfd_vma memaddr,
49 struct disassemble_info* info);
51 typedef void (*operands_f) (bfd_vma memaddr, struct disassemble_info* info);
87 static const struct opr_pb opr_pb[] = {
88 {0xF0, 0x70, 1, OPR_IMMe4},
89 {0xF8, 0xB8, 1, OPR_REG},
90 {0xC0, 0x40, 1, OPR_OFXYS},
91 {0xEF, 0xE3, 1, OPR_XY_PRE_INC},
92 {0xEF, 0xE7, 1, OPR_XY_POST_INC},
93 {0xEF, 0xC3, 1, OPR_XY_PRE_DEC},
94 {0xEF, 0xC7, 1, OPR_XY_POST_DEC},
95 {0xFF, 0xFB, 1, OPR_S_PRE_DEC},
96 {0xFF, 0xFF, 1, OPR_S_POST_INC},
97 {0xC8, 0x88, 1, OPR_REG_DIRECT},
98 {0xE8, 0xC8, 1, OPR_REG_INDIRECT},
100 {0xCE, 0xC0, 2, OPR_IDX_DIRECT},
101 {0xCE, 0xC4, 2, OPR_IDX_INDIRECT},
102 {0xC0, 0x00, 2, OPR_EXT1},
104 {0xC8, 0x80, 3, OPR_IDX2_REG},
105 {0xFA, 0xF8, 3, OPR_EXT18},
107 {0xCF, 0xC2, 4, OPR_IDX3_DIRECT},
108 {0xCF, 0xC6, 4, OPR_IDX3_INDIRECT},
110 {0xF8, 0xE8, 4, OPR_IDX3_DIRECT_REG},
111 {0xFF, 0xFA, 4, OPR_EXT3_DIRECT},
112 {0xFF, 0xFE, 4, OPR_EXT3_INDIRECT},
116 /* Return the number of bytes in a OPR operand, including the XB postbyte.
117 It does not include any preceeding opcodes. */
119 opr_n_bytes (bfd_vma memaddr, struct disassemble_info* info)
122 int status = read_memory (memaddr, &xb, 1, info);
127 for (i = 0; i < sizeof (opr_pb) / sizeof (opr_pb[0]); ++i)
129 const struct opr_pb *pb = opr_pb + i;
130 if ((xb & pb->mask) == pb->value)
132 return pb->n_operands;
140 opr_n_bytes_p1 (bfd_vma memaddr, struct disassemble_info* info)
142 return 1 + opr_n_bytes (memaddr, info);
146 opr_n_bytes2 (bfd_vma memaddr, struct disassemble_info* info)
148 int s = opr_n_bytes (memaddr, info);
149 s += opr_n_bytes (memaddr + s, info);
172 static const struct opr_bb bb_modes[] =
174 {0x60, 0x00, 2, false, BB_REG_REG_REG},
175 {0x60, 0x20, 3, false, BB_REG_REG_IMM},
176 {0x70, 0x40, 2, true, BB_REG_OPR_REG},
177 {0x70, 0x50, 2, true, BB_OPR_REG_REG},
178 {0x70, 0x60, 3, true, BB_REG_OPR_IMM},
179 {0x70, 0x70, 3, true, BB_OPR_REG_IMM}
183 bfextins_n_bytes (bfd_vma memaddr, struct disassemble_info* info)
186 int status = read_memory (memaddr, &bb, 1, info);
191 const struct opr_bb *bbs = 0;
192 for (i = 0; i < sizeof (bb_modes) / sizeof (bb_modes[0]); ++i)
195 if ((bb & bbs->mask) == bbs->value)
201 int n = bbs->n_operands;
203 n += opr_n_bytes (memaddr + n - 1, info);
209 single (bfd_vma memaddr ATTRIBUTE_UNUSED,
210 struct disassemble_info* info ATTRIBUTE_UNUSED)
216 two (bfd_vma memaddr ATTRIBUTE_UNUSED,
217 struct disassemble_info* info ATTRIBUTE_UNUSED)
223 three (bfd_vma memaddr ATTRIBUTE_UNUSED,
224 struct disassemble_info* info ATTRIBUTE_UNUSED)
230 four (bfd_vma memaddr ATTRIBUTE_UNUSED,
231 struct disassemble_info* info ATTRIBUTE_UNUSED)
237 five (bfd_vma memaddr ATTRIBUTE_UNUSED,
238 struct disassemble_info* info ATTRIBUTE_UNUSED)
244 pcrel_15bit (bfd_vma memaddr, struct disassemble_info* info)
247 int status = read_memory (memaddr, &byte, 1, info);
250 return (byte & 0x80) ? 3 : 2;
257 operand_separator (struct disassemble_info *info)
259 if ((info->flags & 0x2))
261 (*info->fprintf_func) (info->stream, ", ");
265 (*info->fprintf_func) (info->stream, " ");
274 imm1 (bfd_vma memaddr, struct disassemble_info* info)
277 int status = read_memory (memaddr, &byte, 1, info);
281 operand_separator (info);
282 (*info->fprintf_func) (info->stream, "#%d", byte);
286 trap_decode (bfd_vma memaddr, struct disassemble_info* info)
288 imm1 (memaddr - 1, info);
292 const struct reg registers[S12Z_N_REGISTERS] =
315 xys_from_postbyte (uint8_t postbyte)
318 switch ((postbyte & 0x30) >> 4)
337 xysp_from_postbyte (uint8_t postbyte)
340 switch ((postbyte & 0x30) >> 4)
358 /* Render the symbol name whose value is ADDR or the adddress itself if there is
361 decode_possible_symbol (bfd_vma addr, struct disassemble_info *info)
363 if (!info->symbol_at_address_func (addr, info))
365 (*info->fprintf_func) (info->stream, "%" BFD_VMA_FMT "d", addr);
371 for (j = 0; j < info->symtab_size; ++j)
373 sym = info->symtab[j];
374 if (bfd_asymbol_value (sym) == addr)
379 if (j < info->symtab_size)
380 (*info->fprintf_func) (info->stream, "%s", bfd_asymbol_name (sym));
382 (*info->fprintf_func) (info->stream, "%" BFD_VMA_FMT "d", addr);
386 static void ld_18bit_decode (bfd_vma memaddr, struct disassemble_info* info);
389 ext24_decode (bfd_vma memaddr, struct disassemble_info* info)
392 int status = read_memory (memaddr, buffer, 3, info);
398 for (i = 0; i < 3; ++i)
404 operand_separator (info);
405 decode_possible_symbol (addr, info);
410 decode_signed_value (bfd_vma memaddr, struct disassemble_info* info, short size)
415 if (0 > read_memory (memaddr, buffer, size, info))
422 for (i = 0; i < size; ++i)
424 value |= buffer[i] << (8 * (size - i - 1));
427 if (buffer[0] & 0x80)
429 /* Deal with negative values */
430 value -= 0x1UL << (size * 8);
437 opr_decode (bfd_vma memaddr, struct disassemble_info* info)
440 int status = read_memory (memaddr, &postbyte, 1, info);
444 enum OPR_MODE mode = -1;
446 for (i = 0; i < sizeof (opr_pb) / sizeof (opr_pb[0]); ++i)
448 const struct opr_pb *pb = opr_pb + i;
449 if ((postbyte & pb->mask) == pb->value)
456 operand_separator (info);
462 uint8_t x = (postbyte & 0x0F);
468 (*info->fprintf_func) (info->stream, "#%d", n);
473 uint8_t x = (postbyte & 0x07);
474 (*info->fprintf_func) (info->stream, "%s", registers[x].name);
479 const char *reg = xys_from_postbyte (postbyte);
480 (*info->fprintf_func) (info->stream, "(%d,%s)", postbyte & 0x0F, reg);
485 (*info->fprintf_func) (info->stream, "(%s,%s)", registers[postbyte & 0x07].name,
486 xys_from_postbyte (postbyte));
489 case OPR_REG_INDIRECT:
491 (*info->fprintf_func) (info->stream, "[%s,%s]", registers[postbyte & 0x07].name,
492 (postbyte & 0x10) ? "y": "x");
496 case OPR_IDX_INDIRECT:
499 read_memory (memaddr + 1, &x1, 1, info);
504 /* Deal with negative values */
508 (*info->fprintf_func) (info->stream, "[%d,%s]", idx,
509 xysp_from_postbyte (postbyte));
513 case OPR_IDX3_DIRECT:
516 read_memory (memaddr + 1, x, 3, info);
517 int idx = x[0] << 16 | x[1] << 8 | x[2];
521 /* Deal with negative values */
525 (*info->fprintf_func) (info->stream, "(%d,%s)", idx,
526 xysp_from_postbyte (postbyte));
530 case OPR_IDX3_DIRECT_REG:
533 read_memory (memaddr + 1, x, 3, info);
534 int idx = x[0] << 16 | x[1] << 8 | x[2];
538 /* Deal with negative values */
542 (*info->fprintf_func) (info->stream, "(%d,%s)", idx,
543 registers[postbyte & 0x07].name);
547 case OPR_IDX3_INDIRECT:
550 read_memory (memaddr + 1, x, 3, info);
551 int idx = x[0] << 16 | x[1] << 8 | x[2];
555 /* Deal with negative values */
559 (*info->fprintf_func) (info->stream, "[%d,%s]", idx,
560 xysp_from_postbyte (postbyte));
567 read_memory (memaddr + 1, &x1, 1, info);
572 /* Deal with negative values */
576 (*info->fprintf_func) (info->stream, "(%d,%s)", idx,
577 xysp_from_postbyte (postbyte));
584 read_memory (memaddr + 1, x, 2, info);
585 uint32_t offset = x[1] | x[0] << 8 ;
586 offset |= (postbyte & 0x30) << 12;
588 (*info->fprintf_func) (info->stream, "(%d,%s)", offset,
589 registers[postbyte & 0x07].name);
595 (*info->fprintf_func) (info->stream, "(+%s)",
596 (postbyte & 0x10) ? "y": "x");
600 case OPR_XY_POST_INC:
602 (*info->fprintf_func) (info->stream, "(%s+)",
603 (postbyte & 0x10) ? "y": "x");
609 (*info->fprintf_func) (info->stream, "(-%s)",
610 (postbyte & 0x10) ? "y": "x");
614 case OPR_XY_POST_DEC:
616 (*info->fprintf_func) (info->stream, "(%s-)",
617 (postbyte & 0x10) ? "y": "x");
623 (*info->fprintf_func) (info->stream, "(-s)");
628 (*info->fprintf_func) (info->stream, "(s+)");
634 const size_t size = 2;
636 status = read_memory (memaddr + 1, buffer, size, info);
641 for (i = 0; i < size; ++i)
647 ext18 |= (postbyte & 0x01) << 16;
648 ext18 |= (postbyte & 0x04) << 15;
650 decode_possible_symbol (ext18, info);
657 read_memory (memaddr + 1, &x1, 1, info);
660 addr |= (postbyte & 0x3f) << 8;
662 decode_possible_symbol (addr, info);
666 case OPR_EXT3_DIRECT:
668 const size_t size = 3;
670 status = read_memory (memaddr + 1, buffer, size, info);
675 for (i = 0; i < size; ++i)
677 ext24 |= buffer[i] << (8 * (size - i - 1));
680 decode_possible_symbol (ext24, info);
684 case OPR_EXT3_INDIRECT:
686 const size_t size = 3;
688 status = read_memory (memaddr + 1, buffer, size, info);
693 for (i = 0; i < size; ++i)
695 ext24 |= buffer[i] << (8 * (size - i - 1));
698 (*info->fprintf_func) (info->stream, "[%d]", ext24);
704 (*info->fprintf_func) (info->stream, "Unknown OPR mode #0x%x (%d)", postbyte, mode);
710 opr_decode2 (bfd_vma memaddr, struct disassemble_info* info)
712 int n = opr_n_bytes (memaddr, info);
713 opr_decode (memaddr, info);
714 opr_decode (memaddr + n, info);
718 imm1234 (bfd_vma memaddr, struct disassemble_info* info, int base)
721 int status = read_memory (memaddr - 1, &opcode, 1, info);
727 int size = registers[opcode & 0xF].bytes;
729 uint32_t imm = decode_signed_value (memaddr, info, size);
730 operand_separator (info);
731 (*info->fprintf_func) (info->stream, "#%d", imm);
735 /* Special case of LD and CMP with register S and IMM operand */
737 reg_s_imm (bfd_vma memaddr, struct disassemble_info* info)
739 operand_separator (info);
740 (*info->fprintf_func) (info->stream, "s");
742 uint32_t imm = decode_signed_value (memaddr, info, 3);
743 operand_separator (info);
744 (*info->fprintf_func) (info->stream, "#%d", imm);
747 /* Special case of LD, CMP and ST with register S and OPR operand */
749 reg_s_opr (bfd_vma memaddr, struct disassemble_info* info)
751 operand_separator (info);
752 (*info->fprintf_func) (info->stream, "s");
754 opr_decode (memaddr, info);
758 imm1234_8base (bfd_vma memaddr, struct disassemble_info* info)
760 imm1234 (memaddr, info, 8);
764 imm1234_0base (bfd_vma memaddr, struct disassemble_info* info)
766 imm1234 (memaddr, info, 0);
770 tfr (bfd_vma memaddr, struct disassemble_info* info)
773 int status = read_memory (memaddr, &byte, 1, info);
777 operand_separator (info);
778 (*info->fprintf_func) (info->stream, "%s, %s",
779 registers[byte >> 4].name,
780 registers[byte & 0xF].name);
785 reg (bfd_vma memaddr, struct disassemble_info* info)
788 int status = read_memory (memaddr - 1, &byte, 1, info);
792 operand_separator (info);
793 (*info->fprintf_func) (info->stream, "%s", registers[byte & 0x07].name);
797 reg_xy (bfd_vma memaddr, struct disassemble_info* info)
800 int status = read_memory (memaddr - 1, &byte, 1, info);
804 operand_separator (info);
805 (*info->fprintf_func) (info->stream, "%s", (byte & 0x01) ? "y" : "x");
809 lea_reg_xys_opr (bfd_vma memaddr, struct disassemble_info* info)
812 int status = read_memory (memaddr - 1, &byte, 1, info);
816 char *reg_xys = NULL;
830 operand_separator (info);
831 (*info->fprintf_func) (info->stream, "%s", reg_xys);
832 opr_decode (memaddr, info);
838 lea_reg_xys (bfd_vma memaddr, struct disassemble_info* info)
841 int status = read_memory (memaddr - 1, &byte, 1, info);
845 char *reg_xys = NULL;
859 status = read_memory (memaddr, &byte, 1, info);
865 operand_separator (info);
866 (*info->fprintf_func) (info->stream, "%s, (%d,%s)", reg_xys, v, reg_xys);
870 /* PC Relative offsets of size 15 or 7 bits */
872 rel_15_7 (bfd_vma memaddr, struct disassemble_info* info, int offset)
875 int status = read_memory (memaddr, &upper, 1, info);
879 bool rel_size = (upper & 0x80);
881 int16_t addr = upper;
884 /* 15 bits. Get the next byte */
886 status = read_memory (memaddr + 1, &lower, 1, info);
894 bool negative = (addr & 0x4000);
897 addr = addr - 0x4000;
902 bool negative = (addr & 0x40);
908 operand_separator (info);
909 if (!info->symbol_at_address_func (addr + memaddr - offset, info))
911 (*info->fprintf_func) (info->stream, "*%+d", addr);
917 for (i = 0; i < info->symtab_size; ++i)
919 sym = info->symtab[i];
920 if (bfd_asymbol_value (sym) == addr + memaddr - offset)
925 if (i < info->symtab_size)
926 (*info->fprintf_func) (info->stream, "%s", bfd_asymbol_name (sym));
928 (*info->fprintf_func) (info->stream, "*%+d", addr);
933 /* PC Relative offsets of size 15 or 7 bits */
935 decode_rel_15_7 (bfd_vma memaddr, struct disassemble_info* info)
937 rel_15_7 (memaddr, info, 1);
942 const char *mnemonic;
943 insn_bytes_f insn_bytes;
945 operands_f operands2;
948 static int shift_n_bytes (bfd_vma memaddr, struct disassemble_info* info);
949 static int mov_imm_opr_n_bytes (bfd_vma memaddr, struct disassemble_info* info);
950 static int loop_prim_n_bytes (bfd_vma memaddr, struct disassemble_info* info);
951 static void mov_imm_opr (bfd_vma memaddr, struct disassemble_info* info);
952 static void bm_rel_decode (bfd_vma memaddr, struct disassemble_info* info);
953 static int bm_rel_n_bytes (bfd_vma memaddr, struct disassemble_info* info);
954 static int mul_n_bytes (bfd_vma memaddr, struct disassemble_info* info);
955 static void mul_decode (bfd_vma memaddr, struct disassemble_info* info);
956 static int bm_n_bytes (bfd_vma memaddr, struct disassemble_info* info);
957 static void bm_decode (bfd_vma memaddr, struct disassemble_info* info);
960 cmp_xy (bfd_vma memaddr ATTRIBUTE_UNUSED, struct disassemble_info* info)
962 operand_separator (info);
963 (*info->fprintf_func) (info->stream, "x, y");
967 sub_d6_x_y (bfd_vma memaddr ATTRIBUTE_UNUSED, struct disassemble_info* info)
969 operand_separator (info);
970 (*info->fprintf_func) (info->stream, "d6, x, y");
974 sub_d6_y_x (bfd_vma memaddr ATTRIBUTE_UNUSED, struct disassemble_info* info)
976 operand_separator (info);
977 (*info->fprintf_func) (info->stream, "d6, y, x");
980 static const char shift_size_table[] = {
984 static const struct opcode page2[] =
986 [0x00] = {"ld", opr_n_bytes_p1, 0, reg_s_opr},
987 [0x01] = {"st", opr_n_bytes_p1, 0, reg_s_opr},
988 [0x02] = {"cmp", opr_n_bytes_p1, 0, reg_s_opr},
989 [0x03] = {"ld", four, 0, reg_s_imm},
990 [0x04] = {"cmp", four, 0, reg_s_imm},
991 [0x05] = {"stop", single, 0, 0},
992 [0x06] = {"wai", single, 0, 0},
993 [0x07] = {"sys", single, 0, 0},
994 [0x08] = {NULL, bfextins_n_bytes, 0, 0}, /* BFEXT / BFINS */
995 [0x09] = {NULL, bfextins_n_bytes, 0, 0},
996 [0x0a] = {NULL, bfextins_n_bytes, 0, 0},
997 [0x0b] = {NULL, bfextins_n_bytes, 0, 0},
998 [0x0c] = {NULL, bfextins_n_bytes, 0, 0},
999 [0x0d] = {NULL, bfextins_n_bytes, 0, 0},
1000 [0x0e] = {NULL, bfextins_n_bytes, 0, 0},
1001 [0x0f] = {NULL, bfextins_n_bytes, 0, 0},
1002 [0x10] = {"minu", opr_n_bytes_p1, reg, opr_decode},
1003 [0x11] = {"minu", opr_n_bytes_p1, reg, opr_decode},
1004 [0x12] = {"minu", opr_n_bytes_p1, reg, opr_decode},
1005 [0x13] = {"minu", opr_n_bytes_p1, reg, opr_decode},
1006 [0x14] = {"minu", opr_n_bytes_p1, reg, opr_decode},
1007 [0x15] = {"minu", opr_n_bytes_p1, reg, opr_decode},
1008 [0x16] = {"minu", opr_n_bytes_p1, reg, opr_decode},
1009 [0x17] = {"minu", opr_n_bytes_p1, reg, opr_decode},
1010 [0x18] = {"maxu", opr_n_bytes_p1, reg, opr_decode},
1011 [0x19] = {"maxu", opr_n_bytes_p1, reg, opr_decode},
1012 [0x1a] = {"maxu", opr_n_bytes_p1, reg, opr_decode},
1013 [0x1b] = {"maxu", opr_n_bytes_p1, reg, opr_decode},
1014 [0x1c] = {"maxu", opr_n_bytes_p1, reg, opr_decode},
1015 [0x1d] = {"maxu", opr_n_bytes_p1, reg, opr_decode},
1016 [0x1e] = {"maxu", opr_n_bytes_p1, reg, opr_decode},
1017 [0x1f] = {"maxu", opr_n_bytes_p1, reg, opr_decode},
1018 [0x20] = {"mins", opr_n_bytes_p1, reg, opr_decode},
1019 [0x21] = {"mins", opr_n_bytes_p1, reg, opr_decode},
1020 [0x22] = {"mins", opr_n_bytes_p1, reg, opr_decode},
1021 [0x23] = {"mins", opr_n_bytes_p1, reg, opr_decode},
1022 [0x24] = {"mins", opr_n_bytes_p1, reg, opr_decode},
1023 [0x25] = {"mins", opr_n_bytes_p1, reg, opr_decode},
1024 [0x26] = {"mins", opr_n_bytes_p1, reg, opr_decode},
1025 [0x27] = {"mins", opr_n_bytes_p1, reg, opr_decode},
1026 [0x28] = {"maxs", opr_n_bytes_p1, reg, opr_decode},
1027 [0x29] = {"maxs", opr_n_bytes_p1, reg, opr_decode},
1028 [0x2a] = {"maxs", opr_n_bytes_p1, reg, opr_decode},
1029 [0x2b] = {"maxs", opr_n_bytes_p1, reg, opr_decode},
1030 [0x2c] = {"maxs", opr_n_bytes_p1, reg, opr_decode},
1031 [0x2d] = {"maxs", opr_n_bytes_p1, reg, opr_decode},
1032 [0x2e] = {"maxs", opr_n_bytes_p1, reg, opr_decode},
1033 [0x2f] = {"maxs", opr_n_bytes_p1, reg, opr_decode},
1034 [0x30] = {"div", mul_n_bytes, mul_decode, 0},
1035 [0x31] = {"div", mul_n_bytes, mul_decode, 0},
1036 [0x32] = {"div", mul_n_bytes, mul_decode, 0},
1037 [0x33] = {"div", mul_n_bytes, mul_decode, 0},
1038 [0x34] = {"div", mul_n_bytes, mul_decode, 0},
1039 [0x35] = {"div", mul_n_bytes, mul_decode, 0},
1040 [0x36] = {"div", mul_n_bytes, mul_decode, 0},
1041 [0x37] = {"div", mul_n_bytes, mul_decode, 0},
1042 [0x38] = {"mod", mul_n_bytes, mul_decode, 0},
1043 [0x39] = {"mod", mul_n_bytes, mul_decode, 0},
1044 [0x3a] = {"mod", mul_n_bytes, mul_decode, 0},
1045 [0x3b] = {"mod", mul_n_bytes, mul_decode, 0},
1046 [0x3c] = {"mod", mul_n_bytes, mul_decode, 0},
1047 [0x3d] = {"mod", mul_n_bytes, mul_decode, 0},
1048 [0x3e] = {"mod", mul_n_bytes, mul_decode, 0},
1049 [0x3f] = {"mod", mul_n_bytes, mul_decode, 0},
1050 [0x40] = {"abs", single, reg, 0},
1051 [0x41] = {"abs", single, reg, 0},
1052 [0x42] = {"abs", single, reg, 0},
1053 [0x43] = {"abs", single, reg, 0},
1054 [0x44] = {"abs", single, reg, 0},
1055 [0x45] = {"abs", single, reg, 0},
1056 [0x46] = {"abs", single, reg, 0},
1057 [0x47] = {"abs", single, reg, 0},
1058 [0x48] = {"mac", mul_n_bytes, mul_decode, 0},
1059 [0x49] = {"mac", mul_n_bytes, mul_decode, 0},
1060 [0x4a] = {"mac", mul_n_bytes, mul_decode, 0},
1061 [0x4b] = {"mac", mul_n_bytes, mul_decode, 0},
1062 [0x4c] = {"mac", mul_n_bytes, mul_decode, 0},
1063 [0x4d] = {"mac", mul_n_bytes, mul_decode, 0},
1064 [0x4e] = {"mac", mul_n_bytes, mul_decode, 0},
1065 [0x4f] = {"mac", mul_n_bytes, mul_decode, 0},
1066 [0x50] = {"adc", three, reg, imm1234_0base},
1067 [0x51] = {"adc", three, reg, imm1234_0base},
1068 [0x52] = {"adc", three, reg, imm1234_0base},
1069 [0x53] = {"adc", three, reg, imm1234_0base},
1070 [0x54] = {"adc", two, reg, imm1234_0base},
1071 [0x55] = {"adc", two, reg, imm1234_0base},
1072 [0x56] = {"adc", five, reg, imm1234_0base},
1073 [0x57] = {"adc", five, reg, imm1234_0base},
1074 [0x58] = {"bit", three, reg, imm1234_8base},
1075 [0x59] = {"bit", three, reg, imm1234_8base},
1076 [0x5a] = {"bit", three, reg, imm1234_8base},
1077 [0x5b] = {"bit", three, reg, imm1234_8base},
1078 [0x5c] = {"bit", two, reg, imm1234_8base},
1079 [0x5d] = {"bit", two, reg, imm1234_8base},
1080 [0x5e] = {"bit", five, reg, imm1234_8base},
1081 [0x5f] = {"bit", five, reg, imm1234_8base},
1082 [0x60] = {"adc", opr_n_bytes_p1, reg, opr_decode},
1083 [0x61] = {"adc", opr_n_bytes_p1, reg, opr_decode},
1084 [0x62] = {"adc", opr_n_bytes_p1, reg, opr_decode},
1085 [0x63] = {"adc", opr_n_bytes_p1, reg, opr_decode},
1086 [0x64] = {"adc", opr_n_bytes_p1, reg, opr_decode},
1087 [0x65] = {"adc", opr_n_bytes_p1, reg, opr_decode},
1088 [0x66] = {"adc", opr_n_bytes_p1, reg, opr_decode},
1089 [0x67] = {"adc", opr_n_bytes_p1, reg, opr_decode},
1090 [0x68] = {"bit", opr_n_bytes_p1, reg, opr_decode},
1091 [0x69] = {"bit", opr_n_bytes_p1, reg, opr_decode},
1092 [0x6a] = {"bit", opr_n_bytes_p1, reg, opr_decode},
1093 [0x6b] = {"bit", opr_n_bytes_p1, reg, opr_decode},
1094 [0x6c] = {"bit", opr_n_bytes_p1, reg, opr_decode},
1095 [0x6d] = {"bit", opr_n_bytes_p1, reg, opr_decode},
1096 [0x6e] = {"bit", opr_n_bytes_p1, reg, opr_decode},
1097 [0x6f] = {"bit", opr_n_bytes_p1, reg, opr_decode},
1098 [0x70] = {"sbc", three, reg, imm1234_0base},
1099 [0x71] = {"sbc", three, reg, imm1234_0base},
1100 [0x72] = {"sbc", three, reg, imm1234_0base},
1101 [0x73] = {"sbc", three, reg, imm1234_0base},
1102 [0x74] = {"sbc", two, reg, imm1234_0base},
1103 [0x75] = {"sbc", two, reg, imm1234_0base},
1104 [0x76] = {"sbc", five, reg, imm1234_0base},
1105 [0x77] = {"sbc", five, reg, imm1234_0base},
1106 [0x78] = {"eor", three, reg, imm1234_8base},
1107 [0x79] = {"eor", three, reg, imm1234_8base},
1108 [0x7a] = {"eor", three, reg, imm1234_8base},
1109 [0x7b] = {"eor", three, reg, imm1234_8base},
1110 [0x7c] = {"eor", two, reg, imm1234_8base},
1111 [0x7d] = {"eor", two, reg, imm1234_8base},
1112 [0x7e] = {"eor", five, reg, imm1234_8base},
1113 [0x7f] = {"eor", five, reg, imm1234_8base},
1114 [0x80] = {"sbc", opr_n_bytes_p1, reg, opr_decode},
1115 [0x81] = {"sbc", opr_n_bytes_p1, reg, opr_decode},
1116 [0x82] = {"sbc", opr_n_bytes_p1, reg, opr_decode},
1117 [0x83] = {"sbc", opr_n_bytes_p1, reg, opr_decode},
1118 [0x84] = {"sbc", opr_n_bytes_p1, reg, opr_decode},
1119 [0x85] = {"sbc", opr_n_bytes_p1, reg, opr_decode},
1120 [0x86] = {"sbc", opr_n_bytes_p1, reg, opr_decode},
1121 [0x87] = {"sbc", opr_n_bytes_p1, reg, opr_decode},
1122 [0x88] = {"eor", opr_n_bytes_p1, reg, opr_decode},
1123 [0x89] = {"eor", opr_n_bytes_p1, reg, opr_decode},
1124 [0x8a] = {"eor", opr_n_bytes_p1, reg, opr_decode},
1125 [0x8b] = {"eor", opr_n_bytes_p1, reg, opr_decode},
1126 [0x8c] = {"eor", opr_n_bytes_p1, reg, opr_decode},
1127 [0x8d] = {"eor", opr_n_bytes_p1, reg, opr_decode},
1128 [0x8e] = {"eor", opr_n_bytes_p1, reg, opr_decode},
1129 [0x8f] = {"eor", opr_n_bytes_p1, reg, opr_decode},
1130 [0x90] = {"rti", single, 0, 0},
1131 [0x91] = {"clb", two, tfr, 0},
1132 [0x92] = {"trap", single, trap_decode, 0},
1133 [0x93] = {"trap", single, trap_decode, 0},
1134 [0x94] = {"trap", single, trap_decode, 0},
1135 [0x95] = {"trap", single, trap_decode, 0},
1136 [0x96] = {"trap", single, trap_decode, 0},
1137 [0x97] = {"trap", single, trap_decode, 0},
1138 [0x98] = {"trap", single, trap_decode, 0},
1139 [0x99] = {"trap", single, trap_decode, 0},
1140 [0x9a] = {"trap", single, trap_decode, 0},
1141 [0x9b] = {"trap", single, trap_decode, 0},
1142 [0x9c] = {"trap", single, trap_decode, 0},
1143 [0x9d] = {"trap", single, trap_decode, 0},
1144 [0x9e] = {"trap", single, trap_decode, 0},
1145 [0x9f] = {"trap", single, trap_decode, 0},
1146 [0xa0] = {"sat", single, reg, 0},
1147 [0xa1] = {"sat", single, reg, 0},
1148 [0xa2] = {"sat", single, reg, 0},
1149 [0xa3] = {"sat", single, reg, 0},
1150 [0xa4] = {"sat", single, reg, 0},
1151 [0xa5] = {"sat", single, reg, 0},
1152 [0xa6] = {"sat", single, reg, 0},
1153 [0xa7] = {"sat", single, reg, 0},
1154 [0xa8] = {"trap", single, trap_decode, 0},
1155 [0xa9] = {"trap", single, trap_decode, 0},
1156 [0xaa] = {"trap", single, trap_decode, 0},
1157 [0xab] = {"trap", single, trap_decode, 0},
1158 [0xac] = {"trap", single, trap_decode, 0},
1159 [0xad] = {"trap", single, trap_decode, 0},
1160 [0xae] = {"trap", single, trap_decode, 0},
1161 [0xaf] = {"trap", single, trap_decode, 0},
1162 [0xb0] = {"qmul", mul_n_bytes, mul_decode, 0},
1163 [0xb1] = {"qmul", mul_n_bytes, mul_decode, 0},
1164 [0xb2] = {"qmul", mul_n_bytes, mul_decode, 0},
1165 [0xb3] = {"qmul", mul_n_bytes, mul_decode, 0},
1166 [0xb4] = {"qmul", mul_n_bytes, mul_decode, 0},
1167 [0xb5] = {"qmul", mul_n_bytes, mul_decode, 0},
1168 [0xb6] = {"qmul", mul_n_bytes, mul_decode, 0},
1169 [0xb7] = {"qmul", mul_n_bytes, mul_decode, 0},
1170 [0xb8] = {"trap", single, trap_decode, 0},
1171 [0xb9] = {"trap", single, trap_decode, 0},
1172 [0xba] = {"trap", single, trap_decode, 0},
1173 [0xbb] = {"trap", single, trap_decode, 0},
1174 [0xbc] = {"trap", single, trap_decode, 0},
1175 [0xbd] = {"trap", single, trap_decode, 0},
1176 [0xbe] = {"trap", single, trap_decode, 0},
1177 [0xbf] = {"trap", single, trap_decode, 0},
1178 [0xc0] = {"trap", single, trap_decode, 0},
1179 [0xc1] = {"trap", single, trap_decode, 0},
1180 [0xc2] = {"trap", single, trap_decode, 0},
1181 [0xc3] = {"trap", single, trap_decode, 0},
1182 [0xc4] = {"trap", single, trap_decode, 0},
1183 [0xc5] = {"trap", single, trap_decode, 0},
1184 [0xc6] = {"trap", single, trap_decode, 0},
1185 [0xc7] = {"trap", single, trap_decode, 0},
1186 [0xc8] = {"trap", single, trap_decode, 0},
1187 [0xc9] = {"trap", single, trap_decode, 0},
1188 [0xca] = {"trap", single, trap_decode, 0},
1189 [0xcb] = {"trap", single, trap_decode, 0},
1190 [0xcc] = {"trap", single, trap_decode, 0},
1191 [0xcd] = {"trap", single, trap_decode, 0},
1192 [0xce] = {"trap", single, trap_decode, 0},
1193 [0xcf] = {"trap", single, trap_decode, 0},
1194 [0xd0] = {"trap", single, trap_decode, 0},
1195 [0xd1] = {"trap", single, trap_decode, 0},
1196 [0xd2] = {"trap", single, trap_decode, 0},
1197 [0xd3] = {"trap", single, trap_decode, 0},
1198 [0xd4] = {"trap", single, trap_decode, 0},
1199 [0xd5] = {"trap", single, trap_decode, 0},
1200 [0xd6] = {"trap", single, trap_decode, 0},
1201 [0xd7] = {"trap", single, trap_decode, 0},
1202 [0xd8] = {"trap", single, trap_decode, 0},
1203 [0xd9] = {"trap", single, trap_decode, 0},
1204 [0xda] = {"trap", single, trap_decode, 0},
1205 [0xdb] = {"trap", single, trap_decode, 0},
1206 [0xdc] = {"trap", single, trap_decode, 0},
1207 [0xdd] = {"trap", single, trap_decode, 0},
1208 [0xde] = {"trap", single, trap_decode, 0},
1209 [0xdf] = {"trap", single, trap_decode, 0},
1210 [0xe0] = {"trap", single, trap_decode, 0},
1211 [0xe1] = {"trap", single, trap_decode, 0},
1212 [0xe2] = {"trap", single, trap_decode, 0},
1213 [0xe3] = {"trap", single, trap_decode, 0},
1214 [0xe4] = {"trap", single, trap_decode, 0},
1215 [0xe5] = {"trap", single, trap_decode, 0},
1216 [0xe6] = {"trap", single, trap_decode, 0},
1217 [0xe7] = {"trap", single, trap_decode, 0},
1218 [0xe8] = {"trap", single, trap_decode, 0},
1219 [0xe9] = {"trap", single, trap_decode, 0},
1220 [0xea] = {"trap", single, trap_decode, 0},
1221 [0xeb] = {"trap", single, trap_decode, 0},
1222 [0xec] = {"trap", single, trap_decode, 0},
1223 [0xed] = {"trap", single, trap_decode, 0},
1224 [0xee] = {"trap", single, trap_decode, 0},
1225 [0xef] = {"trap", single, trap_decode, 0},
1226 [0xf0] = {"trap", single, trap_decode, 0},
1227 [0xf1] = {"trap", single, trap_decode, 0},
1228 [0xf2] = {"trap", single, trap_decode, 0},
1229 [0xf3] = {"trap", single, trap_decode, 0},
1230 [0xf4] = {"trap", single, trap_decode, 0},
1231 [0xf5] = {"trap", single, trap_decode, 0},
1232 [0xf6] = {"trap", single, trap_decode, 0},
1233 [0xf7] = {"trap", single, trap_decode, 0},
1234 [0xf8] = {"trap", single, trap_decode, 0},
1235 [0xf9] = {"trap", single, trap_decode, 0},
1236 [0xfa] = {"trap", single, trap_decode, 0},
1237 [0xfb] = {"trap", single, trap_decode, 0},
1238 [0xfc] = {"trap", single, trap_decode, 0},
1239 [0xfd] = {"trap", single, trap_decode, 0},
1240 [0xfe] = {"trap", single, trap_decode, 0},
1241 [0xff] = {"trap", single, trap_decode, 0},
1244 static const struct opcode page1[] =
1246 [0x00] = {"bgnd", single, 0, 0},
1247 [0x01] = {"nop", single, 0, 0},
1248 [0x02] = {"brclr", bm_rel_n_bytes, bm_rel_decode, 0},
1249 [0x03] = {"brset", bm_rel_n_bytes, bm_rel_decode, 0},
1250 [0x04] = {NULL, two, 0, 0}, /* psh/pul */
1251 [0x05] = {"rts", single, 0, 0},
1252 [0x06] = {"lea", opr_n_bytes_p1, reg, opr_decode},
1253 [0x07] = {"lea", opr_n_bytes_p1, reg, opr_decode},
1254 [0x08] = {"lea", opr_n_bytes_p1, lea_reg_xys_opr, 0},
1255 [0x09] = {"lea", opr_n_bytes_p1, lea_reg_xys_opr, 0},
1256 [0x0a] = {"lea", opr_n_bytes_p1, lea_reg_xys_opr, 0},
1257 [0x0b] = {NULL, loop_prim_n_bytes, 0, 0}, /* Loop primitives TBcc / DBcc */
1258 [0x0c] = {"mov.b", mov_imm_opr_n_bytes, mov_imm_opr, 0},
1259 [0x0d] = {"mov.w", mov_imm_opr_n_bytes, mov_imm_opr, 0},
1260 [0x0e] = {"mov.p", mov_imm_opr_n_bytes, mov_imm_opr, 0},
1261 [0x0f] = {"mov.l", mov_imm_opr_n_bytes, mov_imm_opr, 0},
1262 [0x10] = {NULL, shift_n_bytes, 0, 0}, /* lsr/lsl/asl/asr/rol/ror */
1263 [0x11] = {NULL, shift_n_bytes, 0, 0},
1264 [0x12] = {NULL, shift_n_bytes, 0, 0},
1265 [0x13] = {NULL, shift_n_bytes, 0, 0},
1266 [0x14] = {NULL, shift_n_bytes, 0, 0},
1267 [0x15] = {NULL, shift_n_bytes, 0, 0},
1268 [0x16] = {NULL, shift_n_bytes, 0, 0},
1269 [0x17] = {NULL, shift_n_bytes, 0, 0},
1270 [0x18] = {"lea", two, lea_reg_xys, NULL},
1271 [0x19] = {"lea", two, lea_reg_xys, NULL},
1272 [0x1a] = {"lea", two, lea_reg_xys, NULL},
1274 [0x1c] = {"mov.b", opr_n_bytes2, 0, opr_decode2},
1275 [0x1d] = {"mov.w", opr_n_bytes2, 0, opr_decode2},
1276 [0x1e] = {"mov.p", opr_n_bytes2, 0, opr_decode2},
1277 [0x1f] = {"mov.l", opr_n_bytes2, 0, opr_decode2},
1278 [0x20] = {"bra", pcrel_15bit, decode_rel_15_7, 0},
1279 [0x21] = {"bsr", pcrel_15bit, decode_rel_15_7, 0},
1280 [0x22] = {"bhi", pcrel_15bit, decode_rel_15_7, 0},
1281 [0x23] = {"bls", pcrel_15bit, decode_rel_15_7, 0},
1282 [0x24] = {"bcc", pcrel_15bit, decode_rel_15_7, 0},
1283 [0x25] = {"bcs", pcrel_15bit, decode_rel_15_7, 0},
1284 [0x26] = {"bne", pcrel_15bit, decode_rel_15_7, 0},
1285 [0x27] = {"beq", pcrel_15bit, decode_rel_15_7, 0},
1286 [0x28] = {"bvc", pcrel_15bit, decode_rel_15_7, 0},
1287 [0x29] = {"bvs", pcrel_15bit, decode_rel_15_7, 0},
1288 [0x2a] = {"bpl", pcrel_15bit, decode_rel_15_7, 0},
1289 [0x2b] = {"bmi", pcrel_15bit, decode_rel_15_7, 0},
1290 [0x2c] = {"bge", pcrel_15bit, decode_rel_15_7, 0},
1291 [0x2d] = {"blt", pcrel_15bit, decode_rel_15_7, 0},
1292 [0x2e] = {"bgt", pcrel_15bit, decode_rel_15_7, 0},
1293 [0x2f] = {"ble", pcrel_15bit, decode_rel_15_7, 0},
1294 [0x30] = {"inc", single, reg, 0},
1295 [0x31] = {"inc", single, reg, 0},
1296 [0x32] = {"inc", single, reg, 0},
1297 [0x33] = {"inc", single, reg, 0},
1298 [0x34] = {"inc", single, reg, 0},
1299 [0x35] = {"inc", single, reg, 0},
1300 [0x36] = {"inc", single, reg, 0},
1301 [0x37] = {"inc", single, reg, 0},
1302 [0x38] = {"clr", single, reg, 0},
1303 [0x39] = {"clr", single, reg, 0},
1304 [0x3a] = {"clr", single, reg, 0},
1305 [0x3b] = {"clr", single, reg, 0},
1306 [0x3c] = {"clr", single, reg, 0},
1307 [0x3d] = {"clr", single, reg, 0},
1308 [0x3e] = {"clr", single, reg, 0},
1309 [0x3f] = {"clr", single, reg, 0},
1310 [0x40] = {"dec", single, reg, 0},
1311 [0x41] = {"dec", single, reg, 0},
1312 [0x42] = {"dec", single, reg, 0},
1313 [0x43] = {"dec", single, reg, 0},
1314 [0x44] = {"dec", single, reg, 0},
1315 [0x45] = {"dec", single, reg, 0},
1316 [0x46] = {"dec", single, reg, 0},
1317 [0x47] = {"dec", single, reg, 0},
1318 [0x48] = {"mul", mul_n_bytes, mul_decode, 0},
1319 [0x49] = {"mul", mul_n_bytes, mul_decode, 0},
1320 [0x4a] = {"mul", mul_n_bytes, mul_decode, 0},
1321 [0x4b] = {"mul", mul_n_bytes, mul_decode, 0},
1322 [0x4c] = {"mul", mul_n_bytes, mul_decode, 0},
1323 [0x4d] = {"mul", mul_n_bytes, mul_decode, 0},
1324 [0x4e] = {"mul", mul_n_bytes, mul_decode, 0},
1325 [0x4f] = {"mul", mul_n_bytes, mul_decode, 0},
1326 [0x50] = {"add", three, reg, imm1234_0base},
1327 [0x51] = {"add", three, reg, imm1234_0base},
1328 [0x52] = {"add", three, reg, imm1234_0base},
1329 [0x53] = {"add", three, reg, imm1234_0base},
1330 [0x54] = {"add", two, reg, imm1234_0base},
1331 [0x55] = {"add", two, reg, imm1234_0base},
1332 [0x56] = {"add", five, reg, imm1234_0base},
1333 [0x57] = {"add", five, reg, imm1234_0base},
1334 [0x58] = {"and", three, reg, imm1234_8base},
1335 [0x59] = {"and", three, reg, imm1234_8base},
1336 [0x5a] = {"and", three, reg, imm1234_8base},
1337 [0x5b] = {"and", three, reg, imm1234_8base},
1338 [0x5c] = {"and", two, reg, imm1234_8base},
1339 [0x5d] = {"and", two, reg, imm1234_8base},
1340 [0x5e] = {"and", five, reg, imm1234_8base},
1341 [0x5f] = {"and", five, reg, imm1234_8base},
1342 [0x60] = {"add", opr_n_bytes_p1, reg, opr_decode},
1343 [0x61] = {"add", opr_n_bytes_p1, reg, opr_decode},
1344 [0x62] = {"add", opr_n_bytes_p1, reg, opr_decode},
1345 [0x63] = {"add", opr_n_bytes_p1, reg, opr_decode},
1346 [0x64] = {"add", opr_n_bytes_p1, reg, opr_decode},
1347 [0x65] = {"add", opr_n_bytes_p1, reg, opr_decode},
1348 [0x66] = {"add", opr_n_bytes_p1, reg, opr_decode},
1349 [0x67] = {"add", opr_n_bytes_p1, reg, opr_decode},
1350 [0x68] = {"and", opr_n_bytes_p1, reg, opr_decode},
1351 [0x69] = {"and", opr_n_bytes_p1, reg, opr_decode},
1352 [0x6a] = {"and", opr_n_bytes_p1, reg, opr_decode},
1353 [0x6b] = {"and", opr_n_bytes_p1, reg, opr_decode},
1354 [0x6c] = {"and", opr_n_bytes_p1, reg, opr_decode},
1355 [0x6d] = {"and", opr_n_bytes_p1, reg, opr_decode},
1356 [0x6e] = {"and", opr_n_bytes_p1, reg, opr_decode},
1357 [0x6f] = {"and", opr_n_bytes_p1, reg, opr_decode},
1358 [0x70] = {"sub", three, reg, imm1234_0base},
1359 [0x71] = {"sub", three, reg, imm1234_0base},
1360 [0x72] = {"sub", three, reg, imm1234_0base},
1361 [0x73] = {"sub", three, reg, imm1234_0base},
1362 [0x74] = {"sub", two, reg, imm1234_0base},
1363 [0x75] = {"sub", two, reg, imm1234_0base},
1364 [0x76] = {"sub", five, reg, imm1234_0base},
1365 [0x77] = {"sub", five, reg, imm1234_0base},
1366 [0x78] = {"or", three, reg, imm1234_8base},
1367 [0x79] = {"or", three, reg, imm1234_8base},
1368 [0x7a] = {"or", three, reg, imm1234_8base},
1369 [0x7b] = {"or", three, reg, imm1234_8base},
1370 [0x7c] = {"or", two, reg, imm1234_8base},
1371 [0x7d] = {"or", two, reg, imm1234_8base},
1372 [0x7e] = {"or", five, reg, imm1234_8base},
1373 [0x7f] = {"or", five, reg, imm1234_8base},
1374 [0x80] = {"sub", opr_n_bytes_p1, reg, opr_decode},
1375 [0x81] = {"sub", opr_n_bytes_p1, reg, opr_decode},
1376 [0x82] = {"sub", opr_n_bytes_p1, reg, opr_decode},
1377 [0x83] = {"sub", opr_n_bytes_p1, reg, opr_decode},
1378 [0x84] = {"sub", opr_n_bytes_p1, reg, opr_decode},
1379 [0x85] = {"sub", opr_n_bytes_p1, reg, opr_decode},
1380 [0x86] = {"sub", opr_n_bytes_p1, reg, opr_decode},
1381 [0x87] = {"sub", opr_n_bytes_p1, reg, opr_decode},
1382 [0x88] = {"or", opr_n_bytes_p1, reg, opr_decode},
1383 [0x89] = {"or", opr_n_bytes_p1, reg, opr_decode},
1384 [0x8a] = {"or", opr_n_bytes_p1, reg, opr_decode},
1385 [0x8b] = {"or", opr_n_bytes_p1, reg, opr_decode},
1386 [0x8c] = {"or", opr_n_bytes_p1, reg, opr_decode},
1387 [0x8d] = {"or", opr_n_bytes_p1, reg, opr_decode},
1388 [0x8e] = {"or", opr_n_bytes_p1, reg, opr_decode},
1389 [0x8f] = {"or", opr_n_bytes_p1, reg, opr_decode},
1390 [0x90] = {"ld", three, reg, imm1234_0base},
1391 [0x91] = {"ld", three, reg, imm1234_0base},
1392 [0x92] = {"ld", three, reg, imm1234_0base},
1393 [0x93] = {"ld", three, reg, imm1234_0base},
1394 [0x94] = {"ld", two, reg, imm1234_0base},
1395 [0x95] = {"ld", two, reg, imm1234_0base},
1396 [0x96] = {"ld", five, reg, imm1234_0base},
1397 [0x97] = {"ld", five, reg, imm1234_0base},
1398 [0x98] = {"ld", four, reg_xy, imm1234_0base},
1399 [0x99] = {"ld", four, reg_xy, imm1234_0base},
1400 [0x9a] = {"clr", single, reg_xy, 0},
1401 [0x9b] = {"clr", single, reg_xy, 0},
1402 [0x9c] = {"inc.b", opr_n_bytes_p1, 0, opr_decode},
1403 [0x9d] = {"inc.w", opr_n_bytes_p1, 0, opr_decode},
1404 [0x9e] = {"tfr", two, tfr, NULL},
1405 [0x9f] = {"inc.l", opr_n_bytes_p1, 0, opr_decode},
1406 [0xa0] = {"ld", opr_n_bytes_p1, reg, opr_decode},
1407 [0xa1] = {"ld", opr_n_bytes_p1, reg, opr_decode},
1408 [0xa2] = {"ld", opr_n_bytes_p1, reg, opr_decode},
1409 [0xa3] = {"ld", opr_n_bytes_p1, reg, opr_decode},
1410 [0xa4] = {"ld", opr_n_bytes_p1, reg, opr_decode},
1411 [0xa5] = {"ld", opr_n_bytes_p1, reg, opr_decode},
1412 [0xa6] = {"ld", opr_n_bytes_p1, reg, opr_decode},
1413 [0xa7] = {"ld", opr_n_bytes_p1, reg, opr_decode},
1414 [0xa8] = {"ld", opr_n_bytes_p1, reg_xy, opr_decode},
1415 [0xa9] = {"ld", opr_n_bytes_p1, reg_xy, opr_decode},
1416 [0xaa] = {"jmp", opr_n_bytes_p1, opr_decode, 0},
1417 [0xab] = {"jsr", opr_n_bytes_p1, opr_decode, 0},
1418 [0xac] = {"dec.b", opr_n_bytes_p1, 0, opr_decode},
1419 [0xad] = {"dec.w", opr_n_bytes_p1, 0, opr_decode},
1420 [0xae] = {NULL, two, 0, 0}, /* EXG / SEX */
1421 [0xaf] = {"dec.l", opr_n_bytes_p1, 0, opr_decode},
1422 [0xb0] = {"ld", four, reg, ext24_decode},
1423 [0xb1] = {"ld", four, reg, ext24_decode},
1424 [0xb2] = {"ld", four, reg, ext24_decode},
1425 [0xb3] = {"ld", four, reg, ext24_decode},
1426 [0xb4] = {"ld", four, reg, ext24_decode},
1427 [0xb5] = {"ld", four, reg, ext24_decode},
1428 [0xb6] = {"ld", four, reg, ext24_decode},
1429 [0xb7] = {"ld", four, reg, ext24_decode},
1430 [0xb8] = {"ld", four, reg_xy, ext24_decode},
1431 [0xb9] = {"ld", four, reg_xy, ext24_decode},
1432 [0xba] = {"jmp", four, ext24_decode, 0},
1433 [0xbb] = {"jsr", four, ext24_decode, 0},
1434 [0xbc] = {"clr.b", opr_n_bytes_p1, 0, opr_decode},
1435 [0xbd] = {"clr.w", opr_n_bytes_p1, 0, opr_decode},
1436 [0xbe] = {"clr.p", opr_n_bytes_p1, 0, opr_decode},
1437 [0xbf] = {"clr.l", opr_n_bytes_p1, 0, opr_decode},
1438 [0xc0] = {"st", opr_n_bytes_p1, reg, opr_decode},
1439 [0xc1] = {"st", opr_n_bytes_p1, reg, opr_decode},
1440 [0xc2] = {"st", opr_n_bytes_p1, reg, opr_decode},
1441 [0xc3] = {"st", opr_n_bytes_p1, reg, opr_decode},
1442 [0xc4] = {"st", opr_n_bytes_p1, reg, opr_decode},
1443 [0xc5] = {"st", opr_n_bytes_p1, reg, opr_decode},
1444 [0xc6] = {"st", opr_n_bytes_p1, reg, opr_decode},
1445 [0xc7] = {"st", opr_n_bytes_p1, reg, opr_decode},
1446 [0xc8] = {"st", opr_n_bytes_p1, reg_xy, opr_decode},
1447 [0xc9] = {"st", opr_n_bytes_p1, reg_xy, opr_decode},
1448 [0xca] = {"ld", three, reg_xy, ld_18bit_decode},
1449 [0xcb] = {"ld", three, reg_xy, ld_18bit_decode},
1450 [0xcc] = {"com.b", opr_n_bytes_p1, NULL, opr_decode},
1451 [0xcd] = {"com.w", opr_n_bytes_p1, NULL, opr_decode},
1452 [0xce] = {"andcc", two, imm1, 0},
1453 [0xcf] = {"com.l", opr_n_bytes_p1, NULL, opr_decode},
1454 [0xd0] = {"st", four, reg, ext24_decode},
1455 [0xd1] = {"st", four, reg, ext24_decode},
1456 [0xd2] = {"st", four, reg, ext24_decode},
1457 [0xd3] = {"st", four, reg, ext24_decode},
1458 [0xd4] = {"st", four, reg, ext24_decode},
1459 [0xd5] = {"st", four, reg, ext24_decode},
1460 [0xd6] = {"st", four, reg, ext24_decode},
1461 [0xd7] = {"st", four, reg, ext24_decode},
1462 [0xd8] = {"st", four, reg_xy, ext24_decode},
1463 [0xd9] = {"st", four, reg_xy, ext24_decode},
1464 [0xda] = {"ld", three, reg_xy, ld_18bit_decode},
1465 [0xdb] = {"ld", three, reg_xy, ld_18bit_decode},
1466 [0xdc] = {"neg.b", opr_n_bytes_p1, NULL, opr_decode},
1467 [0xdd] = {"neg.w", opr_n_bytes_p1, NULL, opr_decode},
1468 [0xde] = {"orcc", two, imm1, 0},
1469 [0xdf] = {"neg.l", opr_n_bytes_p1, NULL, opr_decode},
1470 [0xe0] = {"cmp", three, reg, imm1234_0base},
1471 [0xe1] = {"cmp", three, reg, imm1234_0base},
1472 [0xe2] = {"cmp", three, reg, imm1234_0base},
1473 [0xe3] = {"cmp", three, reg, imm1234_0base},
1474 [0xe4] = {"cmp", two, reg, imm1234_0base},
1475 [0xe5] = {"cmp", two, reg, imm1234_0base},
1476 [0xe6] = {"cmp", five, reg, imm1234_0base},
1477 [0xe7] = {"cmp", five, reg, imm1234_0base},
1478 [0xe8] = {"cmp", four, reg_xy, imm1234_0base},
1479 [0xe9] = {"cmp", four, reg_xy, imm1234_0base},
1480 [0xea] = {"ld", three, reg_xy, ld_18bit_decode},
1481 [0xeb] = {"ld", three, reg_xy, ld_18bit_decode},
1482 [0xec] = {"bclr", bm_n_bytes, bm_decode, 0},
1483 [0xed] = {"bset", bm_n_bytes, bm_decode, 0},
1484 [0xee] = {"btgl", bm_n_bytes, bm_decode, 0},
1485 [0xef] = {"!!invalid!!", NULL, NULL, NULL}, /* SPARE */
1486 [0xf0] = {"cmp", opr_n_bytes_p1, reg, opr_decode},
1487 [0xf1] = {"cmp", opr_n_bytes_p1, reg, opr_decode},
1488 [0xf2] = {"cmp", opr_n_bytes_p1, reg, opr_decode},
1489 [0xf3] = {"cmp", opr_n_bytes_p1, reg, opr_decode},
1490 [0xf4] = {"cmp", opr_n_bytes_p1, reg, opr_decode},
1491 [0xf5] = {"cmp", opr_n_bytes_p1, reg, opr_decode},
1492 [0xf6] = {"cmp", opr_n_bytes_p1, reg, opr_decode},
1493 [0xf7] = {"cmp", opr_n_bytes_p1, reg, opr_decode},
1494 [0xf8] = {"cmp", opr_n_bytes_p1, reg_xy, opr_decode},
1495 [0xf9] = {"cmp", opr_n_bytes_p1, reg_xy, opr_decode},
1496 [0xfa] = {"ld", three, reg_xy, ld_18bit_decode},
1497 [0xfb] = {"ld", three, reg_xy, ld_18bit_decode},
1498 [0xfc] = {"cmp", single, cmp_xy, 0},
1499 [0xfd] = {"sub", single, sub_d6_x_y, 0},
1500 [0xfe] = {"sub", single, sub_d6_y_x, 0},
1501 [0xff] = {"swi", single, 0, 0}
1505 static const char *oprregs1[] =
1507 "d3", "d2", "d1", "d0", "ccl", "cch"
1510 static const char *oprregs2[] =
1512 "y", "x", "d7", "d6", "d5", "d4"
1533 static const struct mb mul_table[] = {
1534 {0x40, 0x00, MUL_REG_REG},
1536 {0x47, 0x40, MUL_REG_OPR},
1537 {0x47, 0x41, MUL_REG_OPR},
1538 {0x47, 0x43, MUL_REG_OPR},
1540 {0x47, 0x44, MUL_REG_IMM},
1541 {0x47, 0x45, MUL_REG_IMM},
1542 {0x47, 0x47, MUL_REG_IMM},
1544 {0x43, 0x42, MUL_OPR_OPR},
1548 mul_decode (bfd_vma memaddr, struct disassemble_info* info)
1551 int status = read_memory (memaddr, &mb, 1, info);
1557 status = read_memory (memaddr - 1, &byte, 1, info);
1561 (*info->fprintf_func) (info->stream, "%c", (mb & 0x80) ? 's' : 'u');
1563 enum MUL_MODE mode = -1;
1565 for (i = 0; i < sizeof (mul_table) / sizeof (mul_table[0]); ++i)
1567 const struct mb *mm = mul_table + i;
1568 if ((mb & mm->mask) == mm->value)
1581 int size1 = (mb & 0x30) >> 4;
1582 int size2 = (mb & 0x0c) >> 2;
1583 (*info->fprintf_func) (info->stream, ".%c%c",
1584 shift_size_table [size1],
1585 shift_size_table [size2]);
1590 int size = (mb & 0x3);
1591 (*info->fprintf_func) (info->stream, ".%c", shift_size_table [size]);
1596 operand_separator (info);
1597 (*info->fprintf_func) (info->stream, "%s", registers[byte & 0x7].name);
1604 operand_separator (info);
1605 (*info->fprintf_func) (info->stream, "%s", registers[(mb & 0x38) >> 3].name);
1614 operand_separator (info);
1615 int size = (mb & 0x3);
1616 uint32_t imm = decode_signed_value (memaddr + 1, info, size + 1);
1617 (*info->fprintf_func) (info->stream, "#%d", imm);
1620 operand_separator (info);
1621 (*info->fprintf_func) (info->stream, "%s", registers[mb & 0x07].name);
1624 opr_decode (memaddr + 1, info);
1628 int first = opr_n_bytes (memaddr + 1, info);
1629 opr_decode (memaddr + 1, info);
1630 opr_decode (memaddr + first + 1, info);
1638 mul_n_bytes (bfd_vma memaddr, struct disassemble_info* info)
1642 int status = read_memory (memaddr, &mb, 1, info);
1646 enum MUL_MODE mode = -1;
1648 for (i = 0; i < sizeof (mul_table) / sizeof (mul_table[0]); ++i)
1650 const struct mb *mm = mul_table + i;
1651 if ((mb & mm->mask) == mm->value)
1658 int size = (mb & 0x3) + 1;
1668 nx += opr_n_bytes (memaddr + 1, info);
1672 int first = opr_n_bytes (memaddr + nx - 1, info);
1674 int second = opr_n_bytes (memaddr + nx - 1, info);
1684 /* The NXP documentation is vague about BM_RESERVED0 and BM_RESERVED1,
1685 and contains obvious typos.
1686 However the Freescale tools and experiments with the chip itself
1687 seem to indicate that they behave like BM_REG_IMM and BM_OPR_REG
1707 static const struct bm bm_table[] = {
1708 { 0xC6, 0x04, BM_REG_IMM},
1709 { 0x84, 0x00, BM_REG_IMM},
1710 { 0x06, 0x06, BM_REG_IMM},
1711 { 0xC6, 0x44, BM_RESERVED0},
1713 { 0x8F, 0x80, BM_OPR_B},
1714 { 0x8E, 0x82, BM_OPR_W},
1715 { 0x8C, 0x88, BM_OPR_L},
1717 { 0x83, 0x81, BM_OPR_REG},
1718 { 0x87, 0x84, BM_RESERVED1},
1722 bm_decode (bfd_vma memaddr, struct disassemble_info* info)
1725 int status = read_memory (memaddr, &bm, 1, info);
1730 enum BM_MODE mode = -1;
1731 for (i = 0; i < sizeof (bm_table) / sizeof (bm_table[0]); ++i)
1733 const struct bm *bme = bm_table + i;
1734 if ((bm & bme->mask) == bme->value)
1745 operand_separator (info);
1746 (*info->fprintf_func) (info->stream, "%s", registers[bm & 0x07].name);
1749 (*info->fprintf_func) (info->stream, ".%c", 'b');
1750 opr_decode (memaddr + 1, info);
1753 (*info->fprintf_func) (info->stream, ".%c", 'w');
1754 opr_decode (memaddr + 1, info);
1757 (*info->fprintf_func) (info->stream, ".%c", 'l');
1758 opr_decode (memaddr + 1, info);
1764 read_memory (memaddr + 1, &xb, 1, info);
1765 /* Don't emit a size suffix for register operands */
1766 if ((xb & 0xF8) != 0xB8)
1767 (*info->fprintf_func) (info->stream, ".%c", shift_size_table[(bm & 0x0c) >> 2]);
1768 opr_decode (memaddr + 1, info);
1774 operand_separator (info);
1779 imm = (bm & 0x38) >> 3;
1780 (*info->fprintf_func) (info->stream, "#%d", imm);
1784 imm |= (bm & 0x03) << 3;
1787 imm |= (bm & 0x01) << 3;
1790 imm |= (bm & 0x70) >> 4;
1791 (*info->fprintf_func) (info->stream, "#%d", imm);
1795 (*info->fprintf_func) (info->stream, "%s", registers[(bm & 0x70) >> 4].name);
1805 bm_rel_decode (bfd_vma memaddr, struct disassemble_info* info)
1808 int status = read_memory (memaddr, &bm, 1, info);
1813 enum BM_MODE mode = -1;
1814 for (i = 0; i < sizeof (bm_table) / sizeof (bm_table[0]); ++i)
1816 const struct bm *bme = bm_table + i;
1817 if ((bm & bme->mask) == bme->value)
1830 (*info->fprintf_func) (info->stream, ".%c", 'b');
1833 (*info->fprintf_func) (info->stream, ".%c", 'w');
1836 (*info->fprintf_func) (info->stream, ".%c", 'l');
1842 read_memory (memaddr + 1, &xb, 1, info);
1843 /* Don't emit a size suffix for register operands */
1844 if ((xb & 0xF8) != 0xB8)
1845 (*info->fprintf_func) (info->stream, ".%c",
1846 shift_size_table[(bm & 0x0C) >> 2]);
1856 operand_separator (info);
1857 (*info->fprintf_func) (info->stream, "%s", registers[bm & 0x07].name);
1862 opr_decode (memaddr + 1, info);
1863 n = 1 + opr_n_bytes (memaddr + 1, info);
1867 opr_decode (memaddr + 1, info);
1873 operand_separator (info);
1877 imm |= (bm & 0x02) << 3;
1880 imm |= (bm & 0x01) << 3;
1883 imm |= (bm & 0x70) >> 4;
1884 (*info->fprintf_func) (info->stream, "#%d", imm);
1887 imm = (bm & 0x38) >> 3;
1888 (*info->fprintf_func) (info->stream, "#%d", imm);
1891 imm = (bm & 0xF8) >> 3;
1892 (*info->fprintf_func) (info->stream, "#%d", imm);
1896 (*info->fprintf_func) (info->stream, "%s", registers[(bm & 0x70) >> 4].name);
1897 n += opr_n_bytes (memaddr + 1, info);
1901 rel_15_7 (memaddr + n, info, n + 1);
1905 bm_n_bytes (bfd_vma memaddr, struct disassemble_info* info)
1908 int status = read_memory (memaddr, &bm, 1, info);
1913 enum BM_MODE mode = -1;
1914 for (i = 0; i < sizeof (bm_table) / sizeof (bm_table[0]); ++i)
1916 const struct bm *bme = bm_table + i;
1917 if ((bm & bme->mask) == bme->value)
1934 n += opr_n_bytes (memaddr + 1, info);
1938 n += opr_n_bytes (memaddr + 1, info);
1946 bm_rel_n_bytes (bfd_vma memaddr, struct disassemble_info* info)
1948 int n = 1 + bm_n_bytes (memaddr, info);
1951 int status = read_memory (memaddr + n - 2, &rb, 1, info);
1965 /* shift direction */
1996 static const struct sb sb_table[] = {
1997 {0x30, 0x00, SB_REG_REG_N_EFF},
1998 {0x30, 0x10, SB_REG_REG_N},
1999 {0x34, 0x20, SB_REG_OPR_EFF},
2000 {0x34, 0x24, SB_ROT},
2001 {0x34, 0x30, SB_REG_OPR_OPR},
2002 {0x34, 0x34, SB_OPR_N},
2006 shift_n_bytes (bfd_vma memaddr, struct disassemble_info* info)
2009 int status = read_memory (memaddr++, &sb, 1, info);
2014 enum SB_MODE mode = -1;
2015 for (i = 0; i < sizeof (sb_table) / sizeof (sb_table[0]); ++i)
2017 const struct sb *sbe = sb_table + i;
2018 if ((sb & sbe->mask) == sbe->value)
2024 case SB_REG_REG_N_EFF:
2027 case SB_REG_OPR_EFF:
2029 return 2 + opr_n_bytes (memaddr, info);
2031 case SB_REG_OPR_OPR:
2033 int opr1 = opr_n_bytes (memaddr, info);
2035 if ((sb & 0x30) != 0x20)
2036 opr2 = opr_n_bytes (memaddr + opr1, info);
2037 return 2 + opr1 + opr2;
2050 mov_imm_opr_n_bytes (bfd_vma memaddr, struct disassemble_info* info)
2053 int status = read_memory (memaddr - 1, &byte, 1, info);
2057 int size = byte - 0x0c + 1;
2059 return size + opr_n_bytes (memaddr + size, info) + 1;
2063 mov_imm_opr (bfd_vma memaddr, struct disassemble_info* info)
2066 int status = read_memory (memaddr - 1, &byte, 1, info);
2070 int size = byte - 0x0c + 1;
2071 uint32_t imm = decode_signed_value (memaddr, info, size);
2073 operand_separator (info);
2074 (*info->fprintf_func) (info->stream, "#%d", imm);
2075 opr_decode (memaddr + size, info);
2081 ld_18bit_decode (bfd_vma memaddr, struct disassemble_info* info)
2085 int status = read_memory (memaddr, buffer + 1, 2, info);
2090 status = read_memory (memaddr - 1, buffer, 1, info);
2094 buffer[0] = (buffer[0] & 0x30) >> 4;
2098 for (i = 0; i < size; ++i)
2100 imm |= buffer[i] << (8 * (size - i - 1));
2103 operand_separator (info);
2104 (*info->fprintf_func) (info->stream, "#%d", imm);
2109 /* Loop Primitives */
2124 static const struct lp lp_mode[] = {
2125 {0x08, 0x00, LP_REG},
2126 {0x0C, 0x08, LP_XY},
2127 {0x0C, 0x0C, LP_OPR},
2131 static const char *lb_condition[] =
2133 "ne", "eq", "pl", "mi", "gt", "le",
2138 loop_prim_n_bytes (bfd_vma memaddr, struct disassemble_info* info)
2142 read_memory (memaddr + mx++, &lb, 1, info);
2144 enum LP_MODE mode = -1;
2146 for (i = 0; i < sizeof (lp_mode) / sizeof (lp_mode[0]); ++i)
2148 const struct lp *pb = lp_mode + i;
2149 if ((lb & pb->mask) == pb->value)
2158 mx += opr_n_bytes (memaddr + mx, info) ;
2162 read_memory (memaddr + mx++, &rb, 1, info);
2173 print_insn_exg_sex (bfd_vma memaddr, struct disassemble_info* info)
2176 int status = read_memory (memaddr, &eb, 1, info);
2180 const struct reg *first = ®isters[(eb & 0xf0) >> 4];
2181 const struct reg *second = ®isters[(eb & 0xf)];
2183 if (first->bytes < second->bytes)
2184 (*info->fprintf_func) (info->stream, "sex");
2186 (*info->fprintf_func) (info->stream, "exg");
2188 operand_separator (info);
2189 (*info->fprintf_func) (info->stream, "%s", first->name);
2190 operand_separator (info);
2191 (*info->fprintf_func) (info->stream, "%s", second->name);
2198 print_insn_loop_primitive (bfd_vma memaddr, struct disassemble_info* info)
2202 int status = read_memory (memaddr, &lb, 1, info);
2206 mnemonic[x++] = (lb & 0x80) ? 'd' : 't';
2207 mnemonic[x++] = 'b';
2208 stpcpy (mnemonic + x, lb_condition [(lb & 0x70) >> 4]);
2211 const char *reg_dxy = NULL;
2212 enum LP_MODE mode = -1;
2214 for (i = 0; i < sizeof (lp_mode) / sizeof (lp_mode[0]); ++i)
2216 const struct lp *pb = lp_mode + i;
2217 if ((lb & pb->mask) == pb->value)
2227 reg_dxy = registers [lb & 0x07].name;
2230 reg_dxy = (lb & 0x1) ? "y" : "x";
2233 mnemonic[x++] = '.';
2234 mnemonic[x++] = shift_size_table [lb & 0x03];
2235 offs += opr_n_bytes (memaddr + 1, info);
2239 mnemonic[x++] = '\0';
2241 (*info->fprintf_func) (info->stream, "%s", mnemonic);
2244 opr_decode (memaddr + 1, info);
2247 operand_separator (info);
2248 (*info->fprintf_func) (info->stream, "%s", reg_dxy);
2251 rel_15_7 (memaddr + offs, info, offs + 1);
2258 print_insn_shift (bfd_vma memaddr, struct disassemble_info* info, uint8_t byte)
2262 int status = read_memory (memaddr, &sb, 1, info);
2266 enum SB_DIR dir = (sb & 0x40) ? SB_LEFT : SB_RIGHT;
2267 enum SB_TYPE type = (sb & 0x80) ? SB_ARITHMETIC : SB_LOGICAL;
2268 enum SB_MODE mode = -1;
2269 for (i = 0; i < sizeof (sb_table) / sizeof (sb_table[0]); ++i)
2271 const struct sb *sbe = sb_table + i;
2272 if ((sb & sbe->mask) == sbe->value)
2280 mnemonic[x++] = 'r';
2281 mnemonic[x++] = 'o';
2285 mnemonic[x++] = (type == SB_LOGICAL) ? 'l' : 'a';
2286 mnemonic[x++] = 's';
2289 mnemonic[x++] = (dir == SB_LEFT) ? 'l' : 'r';
2293 case SB_REG_OPR_EFF:
2295 case SB_REG_OPR_OPR:
2296 mnemonic[x++] = '.';
2297 mnemonic[x++] = shift_size_table[sb & 0x03];
2302 read_memory (memaddr + 1, &xb, 1, info);
2303 /* The size suffix is not printed if the OPR operand refers
2304 directly to a register, because the size is implied by the
2305 size of that register. */
2306 if ((xb & 0xF8) != 0xB8)
2308 mnemonic[x++] = '.';
2309 mnemonic[x++] = shift_size_table[sb & 0x03];
2317 mnemonic[x++] = '\0';
2319 (*info->fprintf_func) (info->stream, "%s", mnemonic);
2321 /* Destination register */
2324 case SB_REG_REG_N_EFF:
2326 case SB_REG_OPR_EFF:
2327 case SB_REG_OPR_OPR:
2328 operand_separator (info);
2329 (*info->fprintf_func) (info->stream, "%s", registers[byte & 0x7].name);
2333 opr_decode (memaddr + 1, info);
2340 /* Source register */
2343 case SB_REG_REG_N_EFF:
2345 operand_separator (info);
2346 (*info->fprintf_func) (info->stream, "%s", registers[sb & 0x7].name);
2349 case SB_REG_OPR_OPR:
2350 opr_decode (memaddr + 1, info);
2360 case SB_REG_OPR_EFF:
2362 opr_decode (memaddr + 1, info);
2368 operand_separator (info);
2372 read_memory (memaddr + 1, &xb, 1, info);
2373 int shift = ((sb & 0x08) >> 3) | ((xb & 0x0f) << 1);
2374 (*info->fprintf_func) (info->stream, "#%d", shift);
2378 (*info->fprintf_func) (info->stream, "%s:%d", __FILE__, __LINE__);
2383 opr_decode (memaddr + 1, info);
2386 case SB_REG_OPR_OPR:
2389 int n = opr_n_bytes (memaddr + 1, info);
2390 read_memory (memaddr + 1 + n, &xb, 1, info);
2392 if ((xb & 0xF0) == 0x70)
2394 int imm = xb & 0x0F;
2396 imm |= (sb & 0x08) >> 3;
2397 operand_separator (info);
2398 (*info->fprintf_func) (info->stream, "#%d", imm);
2402 opr_decode (memaddr + 1 + n, info);
2412 case SB_REG_REG_N_EFF:
2413 case SB_REG_OPR_EFF:
2415 operand_separator (info);
2416 (*info->fprintf_func) (info->stream, "#%d",
2417 (sb & 0x08) ? 2 : 1);
2428 print_insn_s12z (bfd_vma memaddr, struct disassemble_info* info)
2431 int status = read_memory (memaddr++, &byte, 1, info);
2435 const struct opcode *opc2 = NULL;
2436 const struct opcode *opc = page1 + byte;
2439 (*info->fprintf_func) (info->stream, "%s", opc->mnemonic);
2443 /* The special cases ... */
2449 read_memory (memaddr++, &byte2, 1, info);
2450 opc2 = page2 + byte2;
2453 (*info->fprintf_func) (info->stream, "%s", opc2->mnemonic);
2457 opc2->operands (memaddr, info);
2460 if (opc2->operands2)
2462 opc2->operands2 (memaddr, info);
2465 else if (byte2 >= 0x08 && byte2 <= 0x1F)
2468 read_memory (memaddr, &bb, 1, info);
2470 (*info->fprintf_func) (info->stream, "bfins");
2472 (*info->fprintf_func) (info->stream, "bfext");
2474 enum BB_MODE mode = -1;
2476 const struct opr_bb *bbs = 0;
2477 for (i = 0; i < sizeof (bb_modes) / sizeof (bb_modes[0]); ++i)
2480 if ((bb & bbs->mask) == bbs->value)
2489 case BB_REG_OPR_REG:
2490 case BB_REG_OPR_IMM:
2491 case BB_OPR_REG_REG:
2492 case BB_OPR_REG_IMM:
2494 int size = (bb >> 2) & 0x03;
2495 (*info->fprintf_func) (info->stream, ".%c",
2496 shift_size_table [size]);
2503 int reg1 = byte2 & 0x07;
2507 case BB_REG_REG_REG:
2508 case BB_REG_REG_IMM:
2509 case BB_REG_OPR_REG:
2510 case BB_REG_OPR_IMM:
2511 operand_separator (info);
2512 (*info->fprintf_func) (info->stream, "%s",
2513 registers[reg1].name);
2515 case BB_OPR_REG_REG:
2516 opr_decode (memaddr + 1, info);
2518 case BB_OPR_REG_IMM:
2519 opr_decode (memaddr + 2, info);
2523 /* Second operand */
2526 case BB_REG_REG_REG:
2527 case BB_REG_REG_IMM:
2529 int reg_src = (bb >> 2) & 0x07;
2530 operand_separator (info);
2531 (*info->fprintf_func) (info->stream, "%s",
2532 registers[reg_src].name);
2535 case BB_OPR_REG_REG:
2536 case BB_OPR_REG_IMM:
2538 int reg_src = (byte2 & 0x07);
2539 operand_separator (info);
2540 (*info->fprintf_func) (info->stream, "%s",
2541 registers[reg_src].name);
2544 case BB_REG_OPR_REG:
2545 opr_decode (memaddr + 1, info);
2547 case BB_REG_OPR_IMM:
2548 opr_decode (memaddr + 2, info);
2553 operand_separator (info);
2556 case BB_REG_REG_REG:
2557 case BB_OPR_REG_REG:
2558 case BB_REG_OPR_REG:
2560 int reg_parm = bb & 0x03;
2561 (*info->fprintf_func) (info->stream, "%s",
2562 registers[reg_parm].name);
2565 case BB_REG_REG_IMM:
2566 case BB_OPR_REG_IMM:
2567 case BB_REG_OPR_IMM:
2570 read_memory (memaddr + 1, &i1, 1, info);
2571 int offset = i1 & 0x1f;
2572 int width = bb & 0x03;
2575 (*info->fprintf_func) (info->stream, "#%d:%d", width, offset);
2582 case 0xae: /* EXG / SEX */
2583 status = print_insn_exg_sex (memaddr, info);
2585 case 0x0b: /* Loop Primitives TBcc and DBcc */
2586 status = print_insn_loop_primitive (memaddr, info);
2588 case 0x10: /* shift */
2589 case 0x11: /* shift */
2590 case 0x12: /* shift */
2591 case 0x13: /* shift */
2592 case 0x14: /* shift */
2593 case 0x15: /* shift */
2594 case 0x16: /* shift */
2595 case 0x17: /* shift */
2596 status = print_insn_shift (memaddr, info, byte);
2598 case 0x04: /* psh / pul */
2600 read_memory (memaddr, &byte, 1, info);
2601 (*info->fprintf_func) (info->stream, (byte & 0x80) ? "pul" : "psh");
2605 if ((byte & 0x3F) == 0)
2607 operand_separator (info);
2608 (*info->fprintf_func) (info->stream, "%s", "ALL16b");
2611 for (bit = 5; bit >= 0; --bit)
2613 if (byte & (0x1 << bit))
2615 operand_separator (info);
2616 (*info->fprintf_func) (info->stream, "%s", oprregs2[bit]);
2622 if ((byte & 0x3F) == 0)
2624 operand_separator (info);
2625 (*info->fprintf_func) (info->stream, "%s", "ALL");
2628 for (bit = 5; bit >= 0; --bit)
2630 if (byte & (0x1 << bit))
2632 operand_separator (info);
2633 (*info->fprintf_func) (info->stream, "%s", oprregs1[bit]);
2640 operand_separator (info);
2641 (*info->fprintf_func) (info->stream, "???");
2650 opc->operands (memaddr, info);
2655 opc->operands2 (memaddr, info);
2661 /* Opcodes in page2 have an additional byte */
2665 if (opc2 && opc2->insn_bytes == 0)
2668 if (!opc2 && opc->insn_bytes == 0)
2672 n += opc2->insn_bytes (memaddr, info);
2674 n += opc->insn_bytes (memaddr, info);