1 /* Disassembler code for Renesas RL78.
2 Copyright 2011, 2012 Free Software Foundation, Inc.
3 Contributed by Red Hat.
6 This file is part of the GNU opcodes library.
8 This library is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 3, or (at your option)
13 It is distributed in the hope that it will be useful, but WITHOUT
14 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
15 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
16 License for more details.
18 You should have received a copy of the GNU General Public License
19 along with this program; if not, write to the Free Software
20 Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
21 MA 02110-1301, USA. */
28 #include "opcode/rl78.h"
30 #define DEBUG_SEMANTICS 0
35 disassemble_info * dis;
39 rl78_get_byte (void * vdata)
42 RL78_Data *rl78_data = (RL78_Data *) vdata;
44 rl78_data->dis->read_memory_func (rl78_data->pc,
57 "x", "a", "c", "b", "e", "d", "l", "h",
58 "ax", "bc", "de", "hl",
59 "sp", "psw", "cs", "es", "pmc", "mem"
65 "t", "f", "c", "nc", "h", "nh", "z", "nz"
73 case RL78_Operand_Indirect:
74 case RL78_Operand_BitIndirect:
75 case RL78_Operand_PostInc:
76 case RL78_Operand_PreDec:
84 print_insn_rl78 (bfd_vma addr, disassemble_info * dis)
88 RL78_Opcode_Decoded opcode;
97 rv = rl78_decode_opcode (addr, &opcode, rl78_get_byte, &rl78_data);
99 dis->bytes_per_line = 10;
101 #define PR (dis->fprintf_func)
102 #define PS (dis->stream)
103 #define PC(c) PR (PS, "%c", c)
111 case RLO_unknown: s = "uknown"; break;
112 case RLO_add: s = "add: %e0%0 += %e1%1"; break;
113 case RLO_addc: s = "addc: %e0%0 += %e1%1 + CY"; break;
114 case RLO_and: s = "and: %e0%0 &= %e1%1"; break;
115 case RLO_branch: s = "branch: pc = %e0%0"; break;
116 case RLO_branch_cond: s = "branch_cond: pc = %e0%0 if %c1 / %e1%1"; break;
117 case RLO_branch_cond_clear: s = "branch_cond_clear: pc = %e0%0 if %c1 / %e1%1, %e1%1 = 0"; break;
118 case RLO_call: s = "call: pc = %e1%0"; break;
119 case RLO_cmp: s = "cmp: %e0%0 - %e1%1"; break;
120 case RLO_mov: s = "mov: %e0%0 = %e1%1"; break;
121 case RLO_or: s = "or: %e0%0 |= %e1%1"; break;
122 case RLO_rol: s = "rol: %e0%0 <<= %e1%1"; break;
123 case RLO_rolc: s = "rol: %e0%0 <<= %e1%1,CY"; break;
124 case RLO_ror: s = "ror: %e0%0 >>= %e1%1"; break;
125 case RLO_rorc: s = "ror: %e0%0 >>= %e1%1,CY"; break;
126 case RLO_sar: s = "sar: %e0%0 >>= %e1%1 signed"; break;
127 case RLO_sel: s = "sel: rb = %1"; break;
128 case RLO_shr: s = "shr: %e0%0 >>= %e1%1 unsigned"; break;
129 case RLO_shl: s = "shl: %e0%0 <<= %e1%1"; break;
130 case RLO_skip: s = "skip: if %c1"; break;
131 case RLO_sub: s = "sub: %e0%0 -= %e1%1"; break;
132 case RLO_subc: s = "subc: %e0%0 -= %e1%1 - CY"; break;
133 case RLO_xch: s = "xch: %e0%0 <-> %e1%1"; break;
134 case RLO_xor: s = "xor: %e0%0 ^= %e1%1"; break;
137 sprintf(buf, "%s%%W%%f\t\033[32m%s\033[0m", s, opcode.syntax);
150 RL78_Opcode_Operand * oper;
200 if (opcode.size == RL78_Word)
201 PR (PS, " \033[33mW\033[0m");
208 PR (PS, " \033[35m");
210 if (opcode.flags & RL78_PSW_Z)
211 { PR (PS, "Z"); comma = ","; }
212 if (opcode.flags & RL78_PSW_AC)
213 { PR (PS, "%sAC", comma); comma = ","; }
214 if (opcode.flags & RL78_PSW_CY)
215 { PR (PS, "%sCY", comma); comma = ","; }
224 oper = opcode.op + *s - '0';
230 if (oper->use_es && indirect_type (oper->type))
236 PR (PS, "%s", condition_names[oper->condition]);
242 case RL78_Operand_Immediate:
244 dis->print_address_func (oper->addend, dis);
246 || oper->addend > 999
247 || oper->addend < -999)
248 PR (PS, "%#x", oper->addend);
250 PR (PS, "%d", oper->addend);
253 case RL78_Operand_Register:
254 PR (PS, "%s", register_names[oper->reg]);
257 case RL78_Operand_Bit:
258 PR (PS, "%s.%d", register_names[oper->reg], oper->bit_number);
261 case RL78_Operand_Indirect:
262 case RL78_Operand_BitIndirect:
266 if (oper->addend == 0xffffa && do_sfr && opcode.size == RL78_Byte)
268 else if (oper->addend == 0xffff8 && do_sfr && opcode.size == RL78_Word)
270 else if (oper->addend >= 0xffe20)
271 PR (PS, "%#x", oper->addend);
273 dis->print_address_func (oper->addend, dis);
279 PR (PS, "%d[%s]", oper->addend, register_names[oper->reg]);
283 PR (PS, "[%s", register_names[oper->reg]);
284 if (oper->reg2 != RL78_Reg_None)
285 PR (PS, "+%s", register_names[oper->reg2]);
287 PR (PS, "+%d", oper->addend);
292 if (oper->type == RL78_Operand_BitIndirect)
293 PR (PS, ".%d", oper->bit_number);
297 /* Shouldn't happen - push and pop don't print
298 [SP] directly. But we *do* use them for
299 semantic debugging. */
300 case RL78_Operand_PostInc:
301 PR (PS, "[%s++]", register_names[oper->reg]);
303 case RL78_Operand_PreDec:
304 PR (PS, "[--%s]", register_names[oper->reg]);
309 /* If we ever print this, that means the
310 programmer tried to print an operand with a
311 type we don't expect. Print the line and
312 operand number from rl78-decode.opc for
314 PR (PS, "???%d.%d", opcode.lineno, *s - '0');
323 PR (PS, "\t\033[34m(line %d)\033[0m", opcode.lineno);