opcodes/rl78-decode.opc

   1 /* -*- c -*- */
   2 #include "sysdep.h"
   3 #include <stdio.h>
   4 #include <stdlib.h>
   5 #include <string.h>
   6 #include "ansidecl.h"
   7 #include "opcode/rl78.h"
   8
   9 static int trace = 0;
  10
  11 typedef struct
  12 {
  13   RL78_Opcode_Decoded * rl78;
  14   int (* getbyte)(void *);
  15   void * ptr;
  16   unsigned char * op;
  17 } LocalData;
  18
  19 #define ID(x) rl78->id = RLO_##x, rl78->lineno = __LINE__
  20 #define OP(n,t,r,a) (rl78->op[n].type = t, \
  21                      rl78->op[n].reg = r,            \
  22                      rl78->op[n].addend = a )
  23 #define OPX(n,t,r1,r2,a) \
  24         (rl78->op[n].type = t, \
  25         rl78->op[n].reg = r1, \
  26         rl78->op[n].reg2 = r2, \
  27         rl78->op[n].addend = a )
  28
  29 #define W() rl78->size = RL78_Word
  30
  31 #define AU ATTRIBUTE_UNUSED
  32 #define GETBYTE() (ld->op [ld->rl78->n_bytes++] = ld->getbyte (ld->ptr))
  33 #define B ((unsigned long) GETBYTE())
  34
  35 #define SYNTAX(x) rl78->syntax = x
  36
  37 #define UNSUPPORTED() \
  38   rl78->syntax = "*unknown*"
  39
  40 #define RB(x) ((x)+RL78_Reg_X)
  41 #define RW(x) ((x)+RL78_Reg_AX)
  42
  43 #define Fz      rl78->flags = RL78_PSW_Z
  44 #define Fza     rl78->flags = RL78_PSW_Z | RL78_PSW_AC
  45 #define Fzc     rl78->flags = RL78_PSW_Z | RL78_PSW_CY
  46 #define Fzac    rl78->flags = RL78_PSW_Z | RL78_PSW_AC | RL78_PSW_CY
  47 #define Fa      rl78->flags = RL78_PSW_AC
  48 #define Fc      rl78->flags = RL78_PSW_CY
  49 #define Fac     rl78->flags = RL78_PSW_AC | RL78_PSW_CY
  50
  51 #define IMMU(bytes)   immediate (bytes, 0, ld)
  52 #define IMMS(bytes)   immediate (bytes, 1, ld)
  53
  54 static int
  55 immediate (int bytes, int sign_extend, LocalData * ld)
  56 {
  57   unsigned long i = 0;
  58
  59   switch (bytes)
  60     {
  61     case 1:
  62       i |= B;
  63       if (sign_extend && (i & 0x80))
  64         i -= 0x100;
  65       break;
  66     case 2:
  67       i |= B;
  68       i |= B << 8;
  69       if (sign_extend && (i & 0x8000))
  70         i -= 0x10000;
  71       break;
  72     case 3:
  73       i |= B;
  74       i |= B << 8;
  75       i |= B << 16;
  76       if (sign_extend && (i & 0x800000))
  77         i -= 0x1000000;
  78       break;
  79     default:
  80       fprintf (stderr, "Programmer error: immediate() called with invalid byte count %d\n", bytes);
  81       abort();
  82     }
  83   return i;
  84 }
  85
  86 #define DC(c)           OP (0, RL78_Operand_Immediate, 0, c)
  87 #define DR(r)           OP (0, RL78_Operand_Register, RL78_Reg_##r, 0)
  88 #define DRB(r)          OP (0, RL78_Operand_Register, RB(r), 0)
  89 #define DRW(r)          OP (0, RL78_Operand_Register, RW(r), 0)
  90 #define DM(r,a)         OP (0, RL78_Operand_Indirect, RL78_Reg_##r, a)
  91 #define DM2(r1,r2,a)    OPX (0, RL78_Operand_Indirect, RL78_Reg_##r1, RL78_Reg_##r2, a)
  92 #define DE()            rl78->op[0].use_es = 1
  93 #define DB(b)           set_bit (rl78->op, b)
  94 #define DCY()           DR(PSW); DB(0)
  95 #define DPUSH()         OP (0, RL78_Operand_PreDec, RL78_Reg_SP, 0);
  96
  97 #define SC(c)           OP (1, RL78_Operand_Immediate, 0, c)
  98 #define SR(r)           OP (1, RL78_Operand_Register, RL78_Reg_##r, 0)
  99 #define SRB(r)          OP (1, RL78_Operand_Register, RB(r), 0)
 100 #define SRW(r)          OP (1, RL78_Operand_Register, RW(r), 0)
 101 #define SM(r,a)         OP (1, RL78_Operand_Indirect, RL78_Reg_##r, a)
 102 #define SM2(r1,r2,a)    OPX (1, RL78_Operand_Indirect, RL78_Reg_##r1, RL78_Reg_##r2, a)
 103 #define SE()            rl78->op[1].use_es = 1
 104 #define SB(b)           set_bit (rl78->op+1, b)
 105 #define SCY()           SR(PSW); SB(0)
 106 #define COND(c)         rl78->op[1].condition = RL78_Condition_##c
 107 #define SPOP()          OP (1, RL78_Operand_PostInc, RL78_Reg_SP, 0);
 108
 109 static void
 110 set_bit (RL78_Opcode_Operand *op, int bit)
 111 {
 112   op->bit_number = bit;
 113   switch (op->type) {
 114   case RL78_Operand_Register:
 115     op->type = RL78_Operand_Bit;
 116     break;
 117   case RL78_Operand_Indirect:
 118     op->type = RL78_Operand_BitIndirect;
 119     break;
 120   default:
 121     break;
 122   }
 123 }
 124
 125 static int
 126 saddr (int x)
 127 {
 128   if (x < 0x20)
 129     return 0xfff00 + x;
 130   return 0xffe00 + x;
 131 }
 132
 133 static int
 134 sfr (int x)
 135 {
 136   return 0xfff00 + x;
 137 }
 138
 139 #define SADDR saddr (IMMU (1))
 140 #define SFR sfr (IMMU (1))
 141
 142 int
 143 rl78_decode_opcode (unsigned long pc AU,
 144                   RL78_Opcode_Decoded * rl78,
 145                   int (* getbyte)(void *),
 146                   void * ptr)
 147 {
 148   LocalData lds, * ld = &lds;
 149   unsigned char op_buf[20] = {0};
 150   unsigned char *op = op_buf;
 151   int op0, op1;
 152
 153   lds.rl78 = rl78;
 154   lds.getbyte = getbyte;
 155   lds.ptr = ptr;
 156   lds.op = op;
 157
 158   memset (rl78, 0, sizeof (*rl78));
 159
 160  start_again:
 161
 162 /* Byte registers, not including A.  */
 163 /** VARY rba 000 010 011 100 101 110 111 */
 164 /* Word registers, not including AX.  */
 165 /** VARY ra 01 10 11 */
 166
 167 /*----------------------------------------------------------------------*/
 168 /* ES: prefix                                                           */
 169
 170 /** 0001 0001                   es:                                     */
 171   DE(); SE();
 172   op ++;
 173   pc ++;
 174   goto start_again;
 175
 176 /*----------------------------------------------------------------------*/
 177
 178 /** 0000 1111                   add     %0, %e1%!1                      */
 179   ID(add); DR(A); SM(None, IMMU(2)); Fzac;
 180
 181 /** 0000 1101                   add     %0, %e1%1                       */
 182   ID(add); DR(A); SM(HL, 0); Fzac;
 183
 184 /** 0110 0001 1000 000          add     %0, %e1%1                       */
 185   ID(add); DR(A); SM2(HL, B, 0); Fzac;
 186
 187 /** 0000 1110                   add     %0, %e1%1                       */
 188   ID(add); DR(A); SM(HL, IMMU(1)); Fzac;
 189
 190 /** 0110 0001 1000 0010         add     %0, %e1%1                       */
 191   ID(add); DR(A); SM2(HL, C, 0); Fzac;
 192
 193 /** 0000 1100                   add     %0, #%1                         */
 194   ID(add); DR(A); SC(IMMU(1)); Fzac;
 195
 196 /** 0110 0001 0000 1rba         add     %0, %1                          */
 197   ID(add); DR(A); SRB(rba); Fzac;
 198
 199 /** 0000 1011                   add     %0, %1                          */
 200   ID(add); DR(A); SM(None, SADDR); Fzac;
 201
 202 /** 0110 0001 0000 0reg         add     %0, %1                          */
 203   ID(add); DRB(reg); SR(A); Fzac;
 204
 205 /** 0000 1010                   add     %0, #%1                         */
 206   ID(add); DM(None, SADDR); SC(IMMU(1)); Fzac;
 207
 208 /*----------------------------------------------------------------------*/
 209
 210 /** 0001 1111                   addc    %0, %e1%!1                      */
 211   ID(addc); DR(A); SM(None, IMMU(2)); Fzac;
 212
 213 /** 0001 1101                   addc    %0, %e1%1                       */
 214   ID(addc); DR(A); SM(HL, 0); Fzac;
 215
 216 /** 0110 0001 1001 0000         addc    %0, %e1%1                       */
 217   ID(addc); DR(A); SM2(HL, B, 0); Fzac;
 218
 219 /** 0110 0001 1001 0010         addc    %0, %e1%1                       */
 220   ID(addc); DR(A); SM2(HL, C, 0); Fzac;
 221
 222 /** 0001 1110                   addc    %0, %e1%1                       */
 223   ID(addc); DR(A); SM(HL, IMMU(1)); Fzac;
 224
 225 /** 0001 1100                   addc    %0, #%1                         */
 226   ID(addc); DR(A); SC(IMMU(1)); Fzac;
 227
 228 /** 0110 0001 0001 1rba         addc    %0, %1                          */
 229   ID(addc); DR(A); SRB(rba); Fzac;
 230
 231 /** 0110 0001 0001 0reg         addc    %0, %1                          */
 232   ID(addc); DRB(reg); SR(A); Fzac;
 233
 234 /** 0001 1011                   addc    %0, %1                          */
 235   ID(addc); DR(A); SM(None, SADDR); Fzac;
 236
 237 /** 0001 1010                   addc    %0, #%1                         */
 238   ID(addc); DM(None, SADDR); SC(IMMU(1)); Fzac;
 239
 240 /*----------------------------------------------------------------------*/
 241
 242 /** 0000 0010                   addw    %0, %e1%!1                      */
 243   ID(add); W(); DR(AX); SM(None, IMMU(2)); Fzac;
 244
 245 /** 0110 0001 0000 1001         addw    %0, %e1%1                       */
 246   ID(add); W(); DR(AX); SM(HL, IMMU(1)); Fzac;
 247
 248 /** 0000 0100                   addw    %0, #%1                         */
 249   ID(add); W(); DR(AX); SC(IMMU(2)); Fzac;
 250
 251 /** 0000 0rw1                   addw    %0, %1                          */
 252   ID(add); W(); DR(AX); SRW(rw); Fzac;
 253
 254 /** 0000 0110                   addw    %0, %1                          */
 255   ID(add); W(); DR(AX); SM(None, SADDR); Fzac;
 256
 257 /** 0001 0000                   addw    %0, #%1                         */
 258   ID(add); W(); DR(SP); SC(IMMU(1)); Fzac;
 259
 260 /*----------------------------------------------------------------------*/
 261
 262 /** 0101 1111                   and     %0, %e1%!1                      */
 263   ID(and); DR(A); SM(None, IMMU(2)); Fz;
 264
 265 /** 0101 1101                   and     %0, %e1%1                       */
 266   ID(and); DR(A); SM(HL, 0); Fz;
 267
 268 /** 0110 0001 1101 0000         and     %0, %e1%1                       */
 269   ID(and); DR(A); SM2(HL, B, 0); Fz;
 270
 271 /** 0101 1110                   and     %0, %e1%1                       */
 272   ID(and); DR(A); SM(HL, IMMU(1)); Fz;
 273
 274 /** 0110 0001 1101 0010         and     %0, %e1%1                       */
 275   ID(and); DR(A); SM2(HL, C, 0); Fz;
 276
 277 /** 0101 1100                   and     %0, #%1                         */
 278   ID(and); DR(A); SC(IMMU(1)); Fz;
 279
 280 /** 0110 0001 0101 1rba         and     %0, %1                          */
 281   ID(and); DR(A); SRB(rba); Fz;
 282
 283 /** 0110 0001 0101 0reg         and     %0, %1                          */
 284   ID(and); DRB(reg); SR(A); Fz;
 285
 286 /** 0101 1011                   and     %0, %1                          */
 287   ID(and); DR(A); SM(None, SADDR); Fz;
 288
 289 /** 0101 1010                   and     %0, #%1                         */
 290   ID(and); DM(None, SADDR); SC(IMMU(1)); Fz;
 291
 292 /*----------------------------------------------------------------------*/
 293
 294 /** 0111 0001 1bit 0101         and1    cy, %e1%1                       */
 295   ID(and); DCY(); SM(HL, 0); SB(bit);
 296
 297 /** 0111 0001 1bit 1101         and1    cy, %1                          */
 298   ID(and); DCY(); SR(A); SB(bit);
 299
 300 /** 0111 0001 0bit 1101         and1    cy, %s1                         */
 301   ID(and); DCY(); SM(None, SFR); SB(bit);
 302
 303 /** 0111 0001 0bit 0101         and1    cy, %s1                         */
 304   ID(and); DCY(); SM(None, SADDR); SB(bit);
 305
 306 /*----------------------------------------------------------------------*/
 307
 308 /* Note that the branch insns need to be listed before the shift
 309    ones, as "shift count of zero" means "branch insn" */
 310
 311 /** 1101 1100                   bc      $%a0                            */
 312   ID(branch_cond); DC(pc+IMMS(1)+2); SR(None); COND(C);
 313
 314 /** 1101 1110                   bnc     $%a0                            */
 315   ID(branch_cond); DC(pc+IMMS(1)+2); SR(None); COND(NC);
 316
 317 /** 0110 0001 1100 0011         bh      $%a0                            */
 318   ID(branch_cond); DC(pc+IMMS(1)+3); SR(None); COND(H);
 319
 320 /** 0110 0001 1101 0011         bnh     $%a0                            */
 321   ID(branch_cond); DC(pc+IMMS(1)+3); SR(None); COND(NH);
 322
 323 /** 1101 1101                   bz      $%a0                            */
 324   ID(branch_cond); DC(pc+IMMS(1)+2); SR(None); COND(Z);
 325
 326 /** 1101 1111                   bnz     $%a0                            */
 327   ID(branch_cond); DC(pc+IMMS(1)+2); SR(None); COND(NZ);
 328
 329 /*----------------------------------------------------------------------*/
 330
 331 /** 0011 0001 1bit 0101         bf      %e1%1, $%a0                     */
 332   ID(branch_cond); DC(pc+IMMS(1)+3); SM(HL,0); SB(bit); COND(F);
 333
 334 /** 0011 0001 0bit 0101         bf      %1, $%a0                        */
 335   ID(branch_cond); DC(pc+IMMS(1)+3); SR(A); SB(bit); COND(F);
 336
 337 /** 0011 0001 1bit 0100         bf      %s1, $%a0                       */
 338   ID(branch_cond); SM(None, SFR); SB(bit); DC(pc+IMMS(1)+4); COND(F);
 339
 340 /** 0011 0001 0bit 0100         bf      %s1, $%a0                       */
 341   ID(branch_cond); SM(None, SADDR); SB(bit); DC(pc+IMMS(1)+4); COND(F);
 342
 343 /*----------------------------------------------------------------------*/
 344
 345 /** 1110 1100                   br      !%!a0                           */
 346   ID(branch); DC(IMMU(3));
 347
 348 /** 1110 1101                   br      %!a0                            */
 349   ID(branch); DC(IMMU(2));
 350
 351 /** 1110 1110                   br      $%!a0                           */
 352   ID(branch); DC(pc+IMMS(2)+3);
 353
 354 /** 1110 1111                   br      $%a0                            */
 355   ID(branch); DC(pc+IMMS(1)+2);
 356
 357 /** 0110 0001 1100 1011         br      ax                              */
 358   ID(branch); DR(AX);
 359
 360 /*----------------------------------------------------------------------*/
 361
 362 /** 1111 1111                   brk1                                    */
 363   ID(break);
 364
 365 /** 0110 0001 1100 1100         brk                                     */
 366   ID(break);
 367
 368 /*----------------------------------------------------------------------*/
 369
 370 /** 0011 0001 1bit 0011         bt      %e1%1, $%a0                     */
 371   ID(branch_cond); DC(pc+IMMS(1)+3); SM(HL,0); SB(bit); COND(T);
 372
 373 /** 0011 0001 0bit 0011         bt      %1, $%a0                        */
 374   ID(branch_cond); DC(pc+IMMS(1)+3); SR(A); SB(bit); COND(T);
 375
 376 /** 0011 0001 1bit 0010         bt      %s1, $%a0                       */
 377   ID(branch_cond); SM(None, SFR); SB(bit); DC(pc+IMMS(1)+4); COND(T);
 378
 379 /** 0011 0001 0bit 0010         bt      %s1, $%a0                       */
 380   ID(branch_cond); SM(None, SADDR); SB(bit); DC(pc+IMMS(1)+4); COND(T);
 381
 382 /*----------------------------------------------------------------------*/
 383
 384 /** 0011 0001 1bit 0001         btclr   %e1%1, $%a0                     */
 385   ID(branch_cond_clear); DC(pc+IMMS(1)+3); SM(HL,0); SB(bit); COND(T);
 386
 387 /** 0011 0001 0bit 0001         btclr   %1, $%a0                        */
 388   ID(branch_cond_clear); DC(pc+IMMS(1)+3); SR(A); SB(bit); COND(T);
 389
 390 /** 0011 0001 1bit 0000         btclr   %s1, $%a0                       */
 391   ID(branch_cond_clear); SM(None, SFR); SB(bit); DC(pc+IMMS(1)+4); COND(T);
 392
 393 /** 0011 0001 0bit 0000         btclr   %s1, $%a0                       */
 394   ID(branch_cond_clear); SM(None, SADDR); SB(bit); DC(pc+IMMS(1)+4); COND(T);
 395
 396 /*----------------------------------------------------------------------*/
 397
 398 /** 1111 1100                   call    !%!a0                           */
 399   ID(call); DC(IMMU(3));
 400
 401 /** 1111 1101                   call    %!a0                            */
 402   ID(call); DC(IMMU(2));
 403
 404 /** 1111 1110                   call    $%!a0                           */
 405   ID(call); DC(pc+IMMS(2)+3);
 406
 407 /** 0110 0001 11rg 1010         call    %0                              */
 408   ID(call); DRW(rg);
 409
 410 /** 0110 0001 1nnn 01mm         callt   [%x0]                           */
 411   ID(call); DM(None, 0x80 + mm*16 + nnn*2);
 412
 413 /*----------------------------------------------------------------------*/
 414
 415 /** 0111 0001 0bit 1000         clr1    %e0%!0                          */
 416   ID(mov); DM(None, IMMU(2)); DB(bit); SC(0);
 417
 418 /** 0111 0001 1bit 0011         clr1    %e0%0                           */
 419   ID(mov); DM(HL, 0); DB(bit); SC(0);
 420
 421 /** 0111 0001 1bit 1011         clr1    %0                              */
 422   ID(mov); DR(A); DB(bit); SC(0);
 423
 424 /** 0111 0001 1000 1000         clr1    cy                              */
 425   ID(mov); DCY(); SC(0);
 426
 427 /** 0111 0001 0bit 1011         clr1    %s0                             */
 428   op0 = SFR;
 429   ID(mov); DM(None, op0); DB(bit); SC(0);
 430   if (op0 == RL78_SFR_PSW && bit == 7)
 431     rl78->syntax = "di";
 432
 433 /** 0111 0001 0bit 0011         clr1    %0                              */
 434   ID(mov); DM(None, SADDR); DB(bit); SC(0);
 435
 436 /*----------------------------------------------------------------------*/
 437
 438 /** 1111 0101                   clrb    %e0%!0                          */
 439   ID(mov); DM(None, IMMU(2)); SC(0);
 440
 441 /** 1111 00rg                   clrb    %0                              */
 442   ID(mov); DRB(rg); SC(0);
 443
 444 /** 1111 0100                   clrb    %0                              */
 445   ID(mov); DM(None, SADDR); SC(0);
 446
 447 /*----------------------------------------------------------------------*/
 448
 449 /** 1111 0110                   clrw    %0                              */
 450   ID(mov); DR(AX); SC(0);
 451
 452 /** 1111 0111                   clrw    %0                              */
 453   ID(mov); DR(BC); SC(0);
 454
 455 /*----------------------------------------------------------------------*/
 456
 457 /** 0100 0000                   cmp     %e0%!0, #%1                     */
 458   ID(cmp); DM(None, IMMU(2)); SC(IMMU(1)); Fzac;
 459
 460 /** 0100 1010                   cmp     %0, #%1                         */
 461   ID(cmp); DM(None, SADDR); SC(IMMU(1)); Fzac;
 462
 463 /** 0100 1111                   cmp     %0, %e1%!1                      */
 464   ID(cmp); DR(A); SM(None, IMMU(2)); Fzac;
 465
 466 /** 0100 1101                   cmp     %0, %e1%1                       */
 467   ID(cmp); DR(A); SM(HL, 0); Fzac;
 468
 469 /** 0110 0001 1100 0000         cmp     %0, %e1%1                       */
 470   ID(cmp); DR(A); SM2(HL, B, 0); Fzac;
 471
 472 /** 0110 0001 1100 0010         cmp     %0, %e1%1                       */
 473   ID(cmp); DR(A); SM2(HL, C, 0); Fzac;
 474
 475 /** 0100 1110                   cmp     %0, %e1%1                       */
 476   ID(cmp); DR(A); SM(HL, IMMU(1)); Fzac;
 477
 478 /** 0100 1100                   cmp     %0, #%1                         */
 479   ID(cmp); DR(A); SC(IMMU(1)); Fzac;
 480
 481 /** 0110 0001 0100 1rba         cmp     %0, %1                          */
 482   ID(cmp); DR(A); SRB(rba); Fzac;
 483
 484 /** 0110 0001 0100 0reg         cmp     %0, %1                          */
 485   ID(cmp); DRB(reg); SR(A); Fzac;
 486
 487 /** 0100 1011                   cmp     %0, %1                          */
 488   ID(cmp); DR(A); SM(None, SADDR); Fzac;
 489
 490 /*----------------------------------------------------------------------*/
 491
 492 /** 1101 0101                   cmp0    %e0%!0                          */
 493   ID(cmp); DM(None, IMMU(2)); SC(0); Fzac;
 494
 495 /** 1101 00rg                   cmp0    %0                              */
 496   ID(cmp); DRB(rg); SC(0); Fzac;
 497
 498 /** 1101 0100                   cmp0    %0                              */
 499   ID(cmp); DM(None, SADDR); SC(0); Fzac;
 500
 501 /*----------------------------------------------------------------------*/
 502
 503 /** 0110 0001 1101 1110         cmps    %0, %e1%1                       */
 504   ID(cmp); DR(X); SM(HL, IMMU(1)); Fzac;
 505
 506 /*----------------------------------------------------------------------*/
 507
 508 /** 0100 0010                   cmpw    %0, %e1%!1                      */
 509   ID(cmp); W(); DR(AX); SM(None, IMMU(2)); Fzac;
 510
 511 /** 0110 0001 0100 1001         cmpw    %0, %e1%1                       */
 512   ID(cmp); W(); DR(AX); SM(HL, IMMU(1)); Fzac;
 513
 514 /** 0100 0100                   cmpw    %0, #%1                         */
 515   ID(cmp); W(); DR(AX); SC(IMMU(2)); Fzac;
 516
 517 /** 0100 0ra1                   cmpw    %0, %1                          */
 518   ID(cmp); W(); DR(AX); SRW(ra); Fzac;
 519
 520 /** 0100 0110                   cmpw    %0, %1                          */
 521   ID(cmp); W(); DR(AX); SM(None, SADDR); Fzac;
 522
 523 /*----------------------------------------------------------------------*/
 524
 525 /** 1011 0000                   dec     %e0%!0                          */
 526   ID(sub); DM(None, IMMU(2)); SC(1); Fza;
 527
 528 /** 0110 0001 0110 1001         dec     %e0%0                           */
 529   ID(sub); DM(HL, IMMU(1)); SC(1); Fza;
 530
 531 /** 1001 0reg                   dec     %0                              */
 532   ID(sub); DRB(reg); SC(1); Fza;
 533
 534 /** 1011 0100                   dec     %0                              */
 535   ID(sub); DM(None, SADDR); SC(1); Fza;
 536
 537 /*----------------------------------------------------------------------*/
 538
 539 /** 1011 0010                   decw    %e0%!0                          */
 540   ID(sub); W(); DM(None, IMMU(2)); SC(1);
 541
 542 /** 0110 0001 1000 1001         decw    %e0%0                           */
 543   ID(sub); W(); DM(HL, IMMU(1)); SC(1);
 544
 545 /** 1011 0rg1                   decw    %0                              */
 546   ID(sub); W(); DRW(rg); SC(1);
 547
 548 /** 1011 0110                   decw    %0                              */
 549   ID(sub); W(); DM(None, SADDR); SC(1);
 550
 551 /*----------------------------------------------------------------------*/
 552
 553 /** 0110 0001 1110 1101         halt                                    */
 554   ID(halt);
 555
 556 /*----------------------------------------------------------------------*/
 557
 558 /** 1010 0000                   inc     %e0%!0                          */
 559   ID(add); DM(None, IMMU(2)); SC(1); Fza;
 560
 561 /** 0110 0001 0101 1001         inc     %e0%0                           */
 562   ID(add); DM(HL, IMMU(1)); SC(1); Fza;
 563
 564 /** 1000 0reg                   inc     %0                              */
 565   ID(add); DRB(reg); SC(1); Fza;
 566
 567 /** 1010 0100                   inc     %0                              */
 568   ID(add); DM(None, SADDR); SC(1); Fza;
 569
 570 /*----------------------------------------------------------------------*/
 571
 572 /** 1010 0010                   incw    %e0%!0                          */
 573   ID(add); W(); DM(None, IMMU(2)); SC(1);
 574
 575 /** 0110 0001 0111 1001         incw    %e0%0                           */
 576   ID(add); W(); DM(HL, IMMU(1)); SC(1);
 577
 578 /** 1010 0rg1                   incw    %0                              */
 579   ID(add); W(); DRW(rg); SC(1);
 580
 581 /** 1010 0110                   incw    %0                              */
 582   ID(add); W(); DM(None, SADDR); SC(1);
 583
 584 /*----------------------------------------------------------------------*/
 585
 586 /** 1100 1111                   mov     %e0%!0, #%1                     */
 587   ID(mov); DM(None, IMMU(2)); SC(IMMU(1));
 588
 589 /** 1001 1111                   mov     %e0%!0, %1                      */
 590   ID(mov); DM(None, IMMU(2)); SR(A);
 591
 592 /** 1001 1001                   mov     %e0%0,%1                        */
 593   ID(mov); DM(DE, 0); SR(A);
 594
 595 /** 1100 1010                   mov     %e0%0, #%1                      */
 596   ID(mov); DM(DE, IMMU(1)); SC(IMMU(1));
 597
 598 /** 1001 1010                   mov     %e0%0, %1                       */
 599   ID(mov); DM(DE, IMMU(1)); SR(A);
 600
 601 /** 1001 1011                   mov     %e0%0,%1                        */
 602   ID(mov); DM(HL, 0); SR(A);
 603
 604 /** 0110 0001 1101 1001         mov     %e0%0, %1                       */
 605   ID(mov); DM2(HL, B, 0); SR(A);
 606
 607 /** 1100 1100                   mov     %e0%0, #%1                      */
 608   ID(mov); DM(HL, IMMU(1)); SC(IMMU(1));
 609
 610 /** 1001 1100                   mov     %e0%0, %1                       */
 611   ID(mov); DM(HL, IMMU(1)); SR(A);
 612
 613 /** 0110 0001 1111 1001         mov     %e0%0, %1                       */
 614   ID(mov); DM2(HL, C, 0); SR(A);
 615
 616 /** 1100 1000                   mov     %0, #%1                         */
 617   ID(mov); DM(SP, IMMU(1)); SC(IMMU(1));
 618
 619 /** 1001 1000                   mov     %0, %1                          */
 620   ID(mov); DM(SP, IMMU(1)); SR(A);
 621
 622 /** 1000 1111                   mov     %0, %e1%!1                      */
 623   ID(mov); DR(A); SM(None, IMMU(2));
 624
 625 /** 1000 1001                   mov     %0, %e1%1                       */
 626   ID(mov); DR(A); SM(DE, 0);
 627
 628 /** 1000 1010                   mov     %0, %e1%1                       */
 629   ID(mov); DR(A); SM(DE, IMMU(1));
 630
 631 /** 1000 1011                   mov     %0, %e1%1                       */
 632   ID(mov); DR(A); SM(HL, 0);
 633
 634 /** 1000 1100                   mov     %0, %e1%1                       */
 635   ID(mov); DR(A); SM(HL, IMMU(1));
 636
 637 /** 0110 0001 1100 1001         mov     %0, %e1%1                       */
 638   ID(mov); DR(A); SM2(HL, B, 0);
 639
 640 /** 0110 0001 1110 1001         mov     %0, %e1%1                       */
 641   ID(mov); DR(A); SM2(HL, C, 0);
 642
 643 /** 1000 1000                   mov     %0, %e1%1                       */
 644   ID(mov); DR(A); SM(SP, IMMU(1));
 645
 646 /** 0101 0reg                   mov     %0, #%1                         */
 647   ID(mov); DRB(reg); SC(IMMU(1));
 648
 649 /** 0110 0rba                   mov     %0, %1                          */
 650   ID(mov); DR(A); SRB(rba);
 651
 652 /** 1000 1110 1111 1101         mov     %0, %1                          */
 653   ID(mov); DR(A); SR(ES);
 654
 655 /** 0000 1001                   mov     %0, %e1%1                       */
 656   ID(mov); DR(A); SM(B, IMMU(2));
 657
 658 /** 0100 1001                   mov     %0, %e1%1                       */
 659   ID(mov); DR(A); SM(BC, IMMU(2));
 660
 661 /** 0010 1001                   mov     %0, %e1%1                       */
 662   ID(mov); DR(A); SM(C, IMMU(2));
 663
 664 /** 1000 1110                   mov     %0, %s1                         */
 665   ID(mov); DR(A); SM(None, SFR);
 666
 667 /** 1000 1101                   mov     %0, %1                          */
 668   ID(mov); DR(A); SM(None, SADDR);
 669
 670 /** 1110 1001                   mov     %0, %e1%!1                      */
 671   ID(mov); DR(B); SM(None, IMMU(2));
 672
 673 /** 0111 0rba                   mov     %0, %1                          */
 674   ID(mov); DRB(rba); SR(A);
 675
 676 /** 1110 1000                   mov     %0, %1                          */
 677   ID(mov); DR(B); SM(None, SADDR);
 678
 679 /** 1111 1001                   mov     %0, %e1%!1                      */
 680   ID(mov); DR(C); SM(None, IMMU(2));
 681
 682 /** 1111 1000                   mov     %0, %1                          */
 683   ID(mov); DR(C); SM(None, SADDR);
 684
 685 /** 1101 1001                   mov     %0, %e1%!1                      */
 686   ID(mov); DR(X); SM(None, IMMU(2));
 687
 688 /** 1101 1000                   mov     %0, %1                          */
 689   ID(mov); DR(X); SM(None, SADDR);
 690
 691 /** 1001 1110 1111 1100         mov     %0, %1                          */
 692   ID(mov); DR(CS); SR(A);
 693
 694 /** 0100 0001                   mov     %0, #%1                         */
 695   ID(mov); DR(ES); SC(IMMU(1));
 696
 697 /** 1001 1110 1111 1101         mov     %0, %1                          */
 698   ID(mov); DR(ES); SR(A);
 699
 700 /** 0110 0001 1011 1000         mov     %0, %1                          */
 701   ID(mov); DR(ES); SM(None, SADDR);
 702
 703 /** 0001 1001                   mov     %e0%0, #%1                      */
 704   ID(mov); DM(B, IMMU(2)); SC(IMMU(1));
 705
 706 /** 0001 1000                   mov     %e0%0, %1                       */
 707   ID(mov); DM(B, IMMU(2)); SR(A);
 708
 709 /** 0011 1001                   mov     %e0%0, #%1                      */
 710   ID(mov); DM(BC, IMMU(2)); SC(IMMU(1));
 711
 712 /** 0100 1000                   mov     %e0%0, %1                       */
 713   ID(mov); DM(BC, IMMU(2)); SR(A);
 714
 715 /** 0011 1000                   mov     %e0%0, #%1                      */
 716   ID(mov); DM(C, IMMU(2)); SC(IMMU(1));
 717
 718 /** 0010 1000                   mov     %e0%0, %1                       */
 719   ID(mov); DM(C, IMMU(2)); SR(A);
 720
 721 /** 1100 1101                   mov     %0, #%1                         */
 722   ID(mov); DM(None, SADDR); SC(IMMU(1));
 723
 724 /** 1001 1101                   mov     %0, %1                          */
 725   ID(mov); DM(None, SADDR); SR(A);
 726
 727 /** 1100 1110                   mov     %s0, #%1                        */
 728   op0 = SFR;
 729   op1 = IMMU(1);
 730   ID(mov); DM(None, op0); SC(op1);
 731   if (op0 == 0xffffb)
 732     switch (op1)
 733       {
 734       case 0x01:
 735         rl78->syntax = "mulhu"; ID(mulhu);
 736         break;
 737       case 0x02:
 738         rl78->syntax = "mulh"; ID(mulh);
 739         break;
 740       case 0x03:
 741         rl78->syntax = "divhu"; ID(divhu);
 742         break;
 743       case 0x04:
 744         rl78->syntax = "divwu"; ID(divwu);
 745         break;
 746       case 0x05:
 747         rl78->syntax = "machu"; ID(machu);
 748         break;
 749       case 0x06:
 750         rl78->syntax = "mach"; ID(mach);
 751         break;
 752       }
 753
 754 /** 1001 1110                   mov     %0, %1                          */
 755   ID(mov); DM(None, SFR); SR(A);
 756
 757 /*----------------------------------------------------------------------*/
 758
 759 /** 0111 0001 1bit 0001         mov1    %e0%0, cy                       */
 760   ID(mov); DM(HL, 0); DB(bit); SCY();
 761
 762 /** 0111 0001 1bit 1001         mov1    %e0%0, cy                       */
 763   ID(mov); DR(A); DB(bit); SCY();
 764
 765 /** 0111 0001 1bit 0100         mov1    cy, %e1%1                       */
 766   ID(mov); DCY(); SM(HL, 0); SB(bit);
 767
 768 /** 0111 0001 1bit 1100         mov1    cy, %e1%1                       */
 769   ID(mov); DCY(); SR(A); SB(bit);
 770
 771 /** 0111 0001 0bit 0100         mov1    cy, %1                          */
 772   ID(mov); DCY(); SM(None, SADDR); SB(bit);
 773
 774 /** 0111 0001 0bit 1100         mov1    cy, %s1                         */
 775   ID(mov); DCY(); SM(None, SFR); SB(bit);
 776
 777 /** 0111 0001 0bit 0001         mov1    %0, cy                          */
 778   ID(mov); DM(None, SADDR); DB(bit); SCY();
 779
 780 /** 0111 0001 0bit 1001         mov1    %s0, cy                         */
 781   ID(mov); DM(None, SFR); DB(bit); SCY();
 782
 783 /*----------------------------------------------------------------------*/
 784
 785 /** 0110 0001 1100 1110         movs    %e0%0, %1                       */
 786   ID(mov); DM(HL, IMMU(1)); SR(X); Fzc;
 787
 788 /*----------------------------------------------------------------------*/
 789
 790 /** 1011 1111                   movw    %e0%!0, %1                      */
 791   ID(mov); W(); DM(None, IMMU(2)); SR(AX);
 792
 793 /** 1011 1001                   movw    %e0%0, %1                       */
 794   ID(mov); W(); DM(DE, 0); SR(AX);
 795
 796 /** 1011 1010                   movw    %e0%0, %1                       */
 797   ID(mov); W(); DM(DE, IMMU(1)); SR(AX);
 798
 799 /** 1011 1011                   movw    %e0%0, %1                       */
 800   ID(mov); W(); DM(HL, 0); SR(AX);
 801
 802 /** 1011 1100                   movw    %e0%0, %1                       */
 803   ID(mov); W(); DM(HL, IMMU(1)); SR(AX);
 804
 805 /** 1011 1000                   movw    %0, %1                          */
 806   ID(mov); W(); DM(SP, IMMU(1)); SR(AX);
 807
 808 /** 1010 1111                   movw    %0, %e1%!1                      */
 809   ID(mov); W(); DR(AX); SM(None, IMMU(2));
 810
 811
 812 /** 1010 1001                   movw    %0, %e1%1                       */
 813   ID(mov); W(); DR(AX); SM(DE, 0);
 814
 815 /** 1010 1010                   movw    %0, %e1%1                       */
 816   ID(mov); W(); DR(AX); SM(DE, IMMU(1));
 817
 818 /** 1010 1011                   movw    %0, %e1%1                       */
 819   ID(mov); W(); DR(AX); SM(HL, 0);
 820
 821 /** 1010 1100                   movw    %0, %e1%1                       */
 822   ID(mov); W(); DR(AX); SM(HL, IMMU(1));
 823
 824 /** 1010 1000                   movw    %0, %1                          */
 825   ID(mov); W(); DR(AX); SM(SP, IMMU(1));
 826
 827 /** 0011 0rg0                   movw    %0, #%1                         */
 828   ID(mov); W(); DRW(rg); SC(IMMU(2));
 829
 830 /** 0001 0ra1                   movw    %0, %1                          */
 831   ID(mov); W(); DR(AX); SRW(ra);
 832
 833 /** 0001 0ra0                   movw    %0, %1                          */
 834   ID(mov); W(); DRW(ra); SR(AX);
 835
 836 /** 0101 1001                   movw    %0, %e1%1                       */
 837   ID(mov); W(); DR(AX); SM(B, IMMU(2));
 838
 839 /** 0110 1001                   movw    %0, %e1%1                       */
 840   ID(mov); W(); DR(AX); SM(C, IMMU(2));
 841
 842 /** 0111 1001                   movw    %0, %e1%1                       */
 843   ID(mov); W(); DR(AX); SM(BC, IMMU(2));
 844
 845 /** 0101 1000                   movw    %e0%0, %1                       */
 846   ID(mov); W(); DM(B, IMMU(2)); SR(AX);
 847
 848 /** 0110 1000                   movw    %e0%0, %1                       */
 849   ID(mov); W(); DM(C, IMMU(2)); SR(AX);
 850
 851 /** 0111 1000                   movw    %e0%0, %1                       */
 852   ID(mov); W(); DM(BC, IMMU(2)); SR(AX);
 853
 854 /** 1010 1101                   movw    %0, %1                          */
 855   ID(mov); W(); DR(AX); SM(None, SADDR);
 856
 857 /** 1010 1110                   movw    %0, %s1                         */
 858   ID(mov); W(); DR(AX); SM(None, SFR);
 859
 860 /** 11ra 1011                   movw    %0, %e1%!1                      */
 861   ID(mov); W(); DRW(ra); SM(None, IMMU(2));
 862
 863 /** 11ra 1010                   movw    %0, %1                          */
 864   ID(mov); W(); DRW(ra); SM(None, SADDR);
 865
 866 /** 1100 1001                   movw    %0, #%1                         */
 867   ID(mov); W(); DM(None, SADDR); SC(IMMU(2));
 868
 869 /** 1011 1101                   movw    %0, %1                          */
 870   ID(mov); W(); DM(None, SADDR); SR(AX);
 871
 872 /** 1100 1011                   movw    %0, #%1                         */
 873   ID(mov); W(); DM(None, SFR); SC(IMMU(2));
 874
 875 /** 1011 1110                   movw    %0, %1                          */
 876   ID(mov); W(); DM(None, SFR); SR(AX);
 877
 878 /*----------------------------------------------------------------------*/
 879
 880 /** 1101 0110                   mulu    x                               */
 881   ID(mulu);
 882
 883 /*----------------------------------------------------------------------*/
 884
 885 /** 0000 0000                   nop                                     */
 886   ID(nop);
 887
 888 /*----------------------------------------------------------------------*/
 889
 890 /** 0111 0001 1100 0000         not1    cy                              */
 891   ID(xor); DCY(); SC(1);
 892
 893 /*----------------------------------------------------------------------*/
 894
 895 /** 1110 0101                   oneb    %e0%!0                          */
 896   ID(mov); DM(None, IMMU(2)); SC(1);
 897
 898 /** 1110 00rg                   oneb    %0                              */
 899   ID(mov); DRB(rg); SC(1);
 900
 901 /** 1110 0100                   oneb    %0                              */
 902   ID(mov); DM(None, SADDR); SC(1);
 903
 904 /*----------------------------------------------------------------------*/
 905
 906 /** 1110 0110                   onew    %0                              */
 907   ID(mov); DR(AX); SC(1);
 908
 909 /** 1110 0111                   onew    %0                              */
 910   ID(mov); DR(BC); SC(1);
 911
 912 /*----------------------------------------------------------------------*/
 913
 914 /** 0110 1111                   or      %0, %e1%!1                      */
 915   ID(or); DR(A); SM(None, IMMU(2)); Fz;
 916
 917 /** 0110 1101                   or      %0, %e1%1                       */
 918   ID(or); DR(A); SM(HL, 0); Fz;
 919
 920 /** 0110 0001 1110 0000         or      %0, %e1%1                       */
 921   ID(or); DR(A); SM2(HL, B, 0); Fz;
 922
 923 /** 0110 1110                   or      %0, %e1%1                       */
 924   ID(or); DR(A); SM(HL, IMMU(1)); Fz;
 925
 926 /** 0110 0001 1110 0010         or      %0, %e1%1                       */
 927   ID(or); DR(A); SM2(HL, C, 0); Fz;
 928
 929 /** 0110 1100                   or      %0, #%1                         */
 930   ID(or); DR(A); SC(IMMU(1)); Fz;
 931
 932 /** 0110 0001 0110 1rba         or      %0, %1                          */
 933   ID(or); DR(A); SRB(rba); Fz;
 934
 935 /** 0110 0001 0110 0reg         or      %0, %1                          */
 936   ID(or); DRB(reg); SR(A); Fz;
 937
 938 /** 0110 1011                   or      %0, %1                          */
 939   ID(or); DR(A); SM(None, SADDR); Fz;
 940
 941 /** 0110 1010                   or      %0, #%1                         */
 942   ID(or); DM(None, SADDR); SC(IMMU(1)); Fz;
 943
 944 /*----------------------------------------------------------------------*/
 945
 946 /** 0111 0001 1bit 0110         or1     cy, %e1%1                       */
 947   ID(or); DCY(); SM(HL, 0); SB(bit);
 948
 949 /** 0111 0001 1bit 1110         or1     cy, %1                          */
 950   ID(or); DCY(); SR(A); SB(bit);
 951
 952 /** 0111 0001 0bit 1110         or1     cy, %s1                         */
 953   ID(or); DCY(); SM(None, SFR); SB(bit);
 954
 955 /** 0111 0001 0bit 0110         or1     cy, %s1                         */
 956   ID(or); DCY(); SM(None, SADDR); SB(bit);
 957
 958 /*----------------------------------------------------------------------*/
 959
 960 /** 1100 0rg0                   pop     %0                              */
 961   ID(mov); W(); DRW(rg); SPOP();
 962
 963 /** 0110 0001 1100 1101         pop     %s0                             */
 964   ID(mov); W(); DR(PSW); SPOP();
 965
 966 /*----------------------------------------------------------------------*/
 967
 968 /** 1100 0rg1                   push    %1                              */
 969   ID(mov); W(); DPUSH(); SRW(rg);
 970
 971 /** 0110 0001 1101 1101         push    %s1                             */
 972   ID(mov); W(); DPUSH(); SR(PSW);
 973
 974 /*----------------------------------------------------------------------*/
 975
 976 /** 1101 0111                   ret                                     */
 977   ID(ret);
 978
 979 /** 0110 0001 1111 1100         reti                                    */
 980   ID(reti);
 981
 982 /** 0110 0001 1110 1100         retb                                    */
 983   ID(reti);
 984
 985 /*----------------------------------------------------------------------*/
 986
 987 /** 0110 0001 1110 1011         rol     %0, %1                          */
 988   ID(rol); DR(A); SC(1);
 989
 990 /** 0110 0001 1101 1100         rolc    %0, %1                          */
 991   ID(rolc); DR(A); SC(1);
 992
 993 /** 0110 0001 111r 1110         rolwc   %0, %1                          */
 994   ID(rolc); W(); DRW(r); SC(1);
 995
 996 /** 0110 0001 1101 1011         ror     %0, %1                          */
 997   ID(ror); DR(A); SC(1);
 998
 999 /** 0110 0001 1111 1011         rorc    %0, %1                          */
1000   ID(rorc); DR(A); SC(1);
1001
1002 /*----------------------------------------------------------------------*/
1003
1004 /* Note that the branch insns need to be listed before the shift
1005    ones, as "shift count of zero" means "branch insn" */
1006
1007 /** 0011 0001 0cnt 1011         sar     %0, %1                          */
1008   ID(sar); DR(A); SC(cnt);
1009
1010 /** 0011 0001 wcnt 1111         sarw    %0, %1                          */
1011   ID(sar); W(); DR(AX); SC(wcnt);
1012
1013 /*----------------------------------------------------------------------*/
1014
1015 /** 0110 0001 11rb 1111         sel     rb%1                            */
1016   ID(sel); SC(rb);
1017
1018 /*----------------------------------------------------------------------*/
1019
1020 /** 0111 0001 0bit 0000         set1    %e0%!0                          */
1021   ID(mov); DM(None, IMMU(2)); DB(bit); SC(1);
1022
1023 /** 0111 0001 1bit 0010         set1    %e0%0                           */
1024   ID(mov); DM(HL, 0); DB(bit); SC(1);
1025
1026 /** 0111 0001 1bit 1010         set1    %0                              */
1027   ID(mov); DR(A); DB(bit); SC(1);
1028
1029 /** 0111 0001 1000 0000         set1    cy                              */
1030   ID(mov); DCY(); SC(1);
1031
1032 /** 0111 0001 0bit 1010         set1    %s0                             */
1033   op0 = SFR;
1034   ID(mov); DM(None, op0); DB(bit); SC(1);
1035   if (op0 == RL78_SFR_PSW && bit == 7)
1036     rl78->syntax = "ei";
1037
1038 /** 0111 0001 0bit 0010         set1    %0                              */
1039   ID(mov); DM(None, SADDR); DB(bit); SC(1);
1040
1041 /*----------------------------------------------------------------------*/
1042
1043 /** 0011 0001 0cnt 1001         shl     %0, %1                          */
1044   ID(shl); DR(A); SC(cnt);
1045
1046 /** 0011 0001 0cnt 1000         shl     %0, %1                          */
1047   ID(shl); DR(B); SC(cnt);
1048
1049 /** 0011 0001 0cnt 0111         shl     %0, %1                          */
1050   ID(shl); DR(C); SC(cnt);
1051
1052 /** 0011 0001 wcnt 1101         shlw    %0, %1                          */
1053   ID(shl); W(); DR(AX); SC(wcnt);
1054
1055 /** 0011 0001 wcnt 1100         shlw    %0, %1                          */
1056   ID(shl); W(); DR(BC); SC(wcnt);
1057
1058 /*----------------------------------------------------------------------*/
1059
1060 /** 0011 0001 0cnt 1010         shr     %0, %1                          */
1061   ID(shr); DR(A); SC(cnt);
1062
1063 /** 0011 0001 wcnt 1110         shrw    %0, %1                          */
1064   ID(shr); W(); DR(AX); SC(wcnt);
1065
1066 /*----------------------------------------------------------------------*/
1067
1068 /** 0110 0001 1100 1000         sk%c1                                   */
1069   ID(skip); COND(C);
1070
1071 /** 0110 0001 1110 0011         sk%c1                                   */
1072   ID(skip); COND(H);
1073
1074 /** 0110 0001 1101 1000         sk%c1                                   */
1075   ID(skip); COND(NC);
1076
1077 /** 0110 0001 1111 0011         sk%c1                                   */
1078   ID(skip); COND(NH);
1079
1080 /** 0110 0001 1111 1000         sk%c1                                   */
1081   ID(skip); COND(NZ);
1082
1083 /** 0110 0001 1110 1000         sk%c1                                   */
1084   ID(skip); COND(Z);
1085
1086 /*----------------------------------------------------------------------*/
1087
1088 /** 0110 0001 1111 1101 stop                                    */
1089   ID(stop);
1090
1091 /*----------------------------------------------------------------------*/
1092
1093 /** 0010 1111                   sub     %0, %e1%!1                      */
1094   ID(sub); DR(A); SM(None, IMMU(2)); Fzac;
1095
1096 /** 0010 1101                   sub     %0, %e1%1                       */
1097   ID(sub); DR(A); SM(HL, 0); Fzac;
1098
1099 /** 0110 0001 1010 000          sub     %0, %e1%1                       */
1100   ID(sub); DR(A); SM2(HL, B, 0); Fzac;
1101
1102 /** 0010 1110                   sub     %0, %e1%1                       */
1103   ID(sub); DR(A); SM(HL, IMMU(1)); Fzac;
1104
1105 /** 0110 0001 1010 0010         sub     %0, %e1%1                       */
1106   ID(sub); DR(A); SM2(HL, C, 0); Fzac;
1107
1108 /** 0010 1100                   sub     %0, #%1                         */
1109   ID(sub); DR(A); SC(IMMU(1)); Fzac;
1110
1111 /** 0110 0001 0010 1rba         sub     %0, %1                          */
1112   ID(sub); DR(A); SRB(rba); Fzac;
1113
1114 /** 0010 1011                   sub     %0, %1                          */
1115   ID(sub); DR(A); SM(None, SADDR); Fzac;
1116
1117 /** 0110 0001 0010 0reg         sub     %0, %1                          */
1118   ID(sub); DRB(reg); SR(A); Fzac;
1119
1120 /** 0010 1010                   sub     %0, #%1                         */
1121   ID(sub); DM(None, SADDR); SC(IMMU(1)); Fzac;
1122
1123 /*----------------------------------------------------------------------*/
1124
1125 /** 0011 1111                   subc    %0, %e1%!1                      */
1126   ID(subc); DR(A); SM(None, IMMU(2)); Fzac;
1127
1128 /** 0011 1101                   subc    %0, %e1%1                       */
1129   ID(subc); DR(A); SM(HL, 0); Fzac;
1130
1131 /** 0110 0001 1011 0000         subc    %0, %e1%1                       */
1132   ID(subc); DR(A); SM2(HL, B, 0); Fzac;
1133
1134 /** 0110 0001 1011 0010         subc    %0, %e1%1                       */
1135   ID(subc); DR(A); SM2(HL, C, 0); Fzac;
1136
1137 /** 0011 1110                   subc    %0, %e1%1                       */
1138   ID(subc); DR(A); SM(HL, IMMU(1)); Fzac;
1139
1140 /** 0011 1100                   subc    %0, #%1                         */
1141   ID(subc); DR(A); SC(IMMU(1)); Fzac;
1142
1143 /** 0110 0001 0011 1rba         subc    %0, %1                          */
1144   ID(subc); DR(A); SRB(rba); Fzac;
1145
1146 /** 0110 0001 0011 0reg         subc    %0, %1                          */
1147   ID(subc); DRB(reg); SR(A); Fzac;
1148
1149 /** 0011 1011                   subc    %0, %1                          */
1150   ID(subc); DR(A); SM(None, SADDR); Fzac;
1151
1152 /** 0011 1010                   subc    %0, #%1                         */
1153   ID(subc); DM(None, SADDR); SC(IMMU(1)); Fzac;
1154
1155 /*----------------------------------------------------------------------*/
1156
1157 /** 0010 0010                   subw    %0, %e1%!1                      */
1158   ID(sub); W(); DR(AX); SM(None, IMMU(2)); Fzac;
1159
1160 /** 0110 0001 0010 1001         subw    %0, %e1%1                       */
1161   ID(sub); W(); DR(AX); SM(HL, IMMU(1)); Fzac;
1162
1163 /** 0010 0100                   subw    %0, #%1                         */
1164   ID(sub); W(); DR(AX); SC(IMMU(2)); Fzac;
1165
1166 /** 0010 0rw1                   subw    %0, %1                          */
1167   ID(sub); W(); DR(AX); SRW(rw); Fzac;
1168
1169 /** 0010 0110                   subw    %0, %1                          */
1170   ID(sub); W(); DR(AX); SM(None, SADDR); Fzac;
1171
1172 /** 0010 0000                   subw    %0, #%1                         */
1173   ID(sub); W(); DR(SP); SC(IMMU(1)); Fzac;
1174
1175 /*----------------------------------------------------------------------*/
1176
1177 /** 0110 0001 1010 1010         xch     %0, %e1%!1                      */
1178   ID(xch); DR(A); SM(None, IMMU(2));
1179
1180 /** 0110 0001 1010 1110         xch     %0, %e1%1                       */
1181   ID(xch); DR(A); SM(DE, 0);
1182
1183 /** 0110 0001 1010 1111         xch     %0, %e1%1                       */
1184   ID(xch); DR(A); SM(DE, IMMU(1));
1185
1186 /** 0110 0001 1010 1100         xch     %0, %e1%1                       */
1187   ID(xch); DR(A); SM(HL, 0);
1188
1189 /** 0110 0001 1011 1001         xch     %0, %e1%1                       */
1190   ID(xch); DR(A); SM2(HL, B, 0);
1191
1192 /** 0110 0001 1010 1101         xch     %0, %e1%1                       */
1193   ID(xch); DR(A); SM(HL, IMMU(1));
1194
1195 /** 0110 0001 1010 1001         xch     %0, %e1%1                       */
1196   ID(xch); DR(A); SM2(HL, C, 0);
1197
1198 /** 0110 0001 1000 1reg         xch     %0, %1                          */
1199   /* Note: DECW uses reg == X, so this must follow DECW */
1200   ID(xch); DR(A); SRB(reg);
1201
1202 /** 0110 0001 1010 1000         xch     %0, %1                          */
1203   ID(xch); DR(A); SM(None, SADDR);
1204
1205 /** 0110 0001 1010 1011         xch     %0, %1                          */
1206   ID(xch); DR(A); SM(None, SFR);
1207
1208 /** 0000 1000                   xch     a, x                            */
1209   ID(xch); DR(A); SR(X);
1210
1211 /*----------------------------------------------------------------------*/
1212
1213 /** 0011 0ra1                   xchw    %0, %1                          */
1214   ID(xch); W(); DR(AX); SRW(ra);
1215
1216 /*----------------------------------------------------------------------*/
1217
1218 /** 0111 1111                   xor     %0, %e1%!1                      */
1219   ID(xor); DR(A); SM(None, IMMU(2)); Fz;
1220
1221 /** 0111 1101                   xor     %0, %e1%1                       */
1222   ID(xor); DR(A); SM(HL, 0); Fz;
1223
1224 /** 0110 0001 1111 0000         xor     %0, %e1%1                       */
1225   ID(xor); DR(A); SM2(HL, B, 0); Fz;
1226
1227 /** 0111 1110                   xor     %0, %e1%1                       */
1228   ID(xor); DR(A); SM(HL, IMMU(1)); Fz;
1229
1230 /** 0110 0001 1111 0010         xor     %0, %e1%1                       */
1231   ID(xor); DR(A); SM2(HL, C, 0); Fz;
1232
1233 /** 0111 1100                   xor     %0, #%1                         */
1234   ID(xor); DR(A); SC(IMMU(1)); Fz;
1235
1236 /** 0110 0001 0111 1rba         xor     %0, %1                          */
1237   ID(xor); DR(A); SRB(rba); Fz;
1238
1239 /** 0110 0001 0111 0reg         xor     %0, %1                          */
1240   ID(xor); DRB(reg); SR(A); Fz;
1241
1242 /** 0111 1011                   xor     %0, %1                          */
1243   ID(xor); DR(A); SM(None, SADDR); Fz;
1244
1245 /** 0111 1010                   xor     %0, #%1                         */
1246   ID(xor); DM(None, SADDR); SC(IMMU(1)); Fz;
1247
1248 /*----------------------------------------------------------------------*/
1249
1250 /** 0111 0001 1bit 0111         xor1    cy, %e1%1                       */
1251   ID(xor); DCY(); SM(HL, 0); SB(bit);
1252
1253 /** 0111 0001 1bit 1111         xor1    cy, %1                          */
1254   ID(xor); DCY(); SR(A); SB(bit);
1255
1256 /** 0111 0001 0bit 1111         xor1    cy, %s1                         */
1257   ID(xor); DCY(); SM(None, SFR); SB(bit);
1258
1259 /** 0111 0001 0bit 0111         xor1    cy, %s1                         */
1260   ID(xor); DCY(); SM(None, SADDR); SB(bit);
1261
1262 /*----------------------------------------------------------------------*/
1263
1264 /** */
1265
1266   return rl78->n_bytes;
1267 }