2 Copyright (C) 2011-2018 Free Software Foundation, Inc.
4 Contributed by Andrew Waterman (andrew@sifive.com).
7 This file is part of the GNU opcodes library.
9 This library is free software; you can redistribute it and/or modify
10 it under the terms of the GNU General Public License as published by
11 the Free Software Foundation; either version 3, or (at your option)
14 It is distributed in the hope that it will be useful, but WITHOUT
15 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
16 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
17 License for more details.
19 You should have received a copy of the GNU General Public License
20 along with this program; see the file COPYING3. If not,
21 see <http://www.gnu.org/licenses/>. */
24 #include "disassemble.h"
25 #include "libiberty.h"
26 #include "opcode/riscv.h"
29 #include "elf/riscv.h"
34 struct riscv_private_data
38 bfd_vma hi_addr[OP_MASK_RD + 1];
41 static const char * const *riscv_gpr_names;
42 static const char * const *riscv_fpr_names;
45 static int no_aliases; /* If set disassemble as most general inst. */
48 set_default_riscv_dis_options (void)
50 riscv_gpr_names = riscv_gpr_names_abi;
51 riscv_fpr_names = riscv_fpr_names_abi;
56 parse_riscv_dis_option (const char *option)
58 if (strcmp (option, "no-aliases") == 0)
60 else if (strcmp (option, "numeric") == 0)
62 riscv_gpr_names = riscv_gpr_names_numeric;
63 riscv_fpr_names = riscv_fpr_names_numeric;
67 /* xgettext:c-format */
68 opcodes_error_handler (_("unrecognized disassembler option: %s"), option);
73 parse_riscv_dis_options (const char *opts_in)
75 char *opts = xstrdup (opts_in), *opt = opts, *opt_end = opts;
77 set_default_riscv_dis_options ();
79 for ( ; opt_end != NULL; opt = opt_end + 1)
81 if ((opt_end = strchr (opt, ',')) != NULL)
83 parse_riscv_dis_option (opt);
89 /* Print one argument from an array. */
92 arg_print (struct disassemble_info *info, unsigned long val,
93 const char* const* array, size_t size)
95 const char *s = val >= size || array[val] == NULL ? "unknown" : array[val];
96 (*info->fprintf_func) (info->stream, "%s", s);
100 maybe_print_address (struct riscv_private_data *pd, int base_reg, int offset)
102 if (pd->hi_addr[base_reg] != (bfd_vma)-1)
104 pd->print_addr = (base_reg != 0 ? pd->hi_addr[base_reg] : 0) + offset;
105 pd->hi_addr[base_reg] = -1;
107 else if (base_reg == X_GP && pd->gp != (bfd_vma)-1)
108 pd->print_addr = pd->gp + offset;
109 else if (base_reg == X_TP || base_reg == 0)
110 pd->print_addr = offset;
113 /* Print insn arguments for 32/64-bit code. */
116 print_insn_args (const char *d, insn_t l, bfd_vma pc, disassemble_info *info)
118 struct riscv_private_data *pd = info->private_data;
119 int rs1 = (l >> OP_SH_RS1) & OP_MASK_RS1;
120 int rd = (l >> OP_SH_RD) & OP_MASK_RD;
121 fprintf_ftype print = info->fprintf_func;
124 print (info->stream, "\t");
126 for (; *d != '\0'; d++)
133 case 's': /* RS1 x8-x15 */
134 case 'w': /* RS1 x8-x15 */
135 print (info->stream, "%s",
136 riscv_gpr_names[EXTRACT_OPERAND (CRS1S, l) + 8]);
138 case 't': /* RS2 x8-x15 */
139 case 'x': /* RS2 x8-x15 */
140 print (info->stream, "%s",
141 riscv_gpr_names[EXTRACT_OPERAND (CRS2S, l) + 8]);
143 case 'U': /* RS1, constrained to equal RD */
144 print (info->stream, "%s", riscv_gpr_names[rd]);
146 case 'c': /* RS1, constrained to equal sp */
147 print (info->stream, "%s", riscv_gpr_names[X_SP]);
150 print (info->stream, "%s",
151 riscv_gpr_names[EXTRACT_OPERAND (CRS2, l)]);
154 print (info->stream, "%d", (int)EXTRACT_RVC_SIMM3 (l));
158 print (info->stream, "%d", (int)EXTRACT_RVC_IMM (l));
161 print (info->stream, "%d", (int)EXTRACT_RVC_LW_IMM (l));
164 print (info->stream, "%d", (int)EXTRACT_RVC_LD_IMM (l));
167 print (info->stream, "%d", (int)EXTRACT_RVC_LWSP_IMM (l));
170 print (info->stream, "%d", (int)EXTRACT_RVC_LDSP_IMM (l));
173 print (info->stream, "%d", (int)EXTRACT_RVC_ADDI4SPN_IMM (l));
176 print (info->stream, "%d", (int)EXTRACT_RVC_ADDI16SP_IMM (l));
179 print (info->stream, "%d", (int)EXTRACT_RVC_SWSP_IMM (l));
182 print (info->stream, "%d", (int)EXTRACT_RVC_SDSP_IMM (l));
185 info->target = EXTRACT_RVC_B_IMM (l) + pc;
186 (*info->print_address_func) (info->target, info);
189 info->target = EXTRACT_RVC_J_IMM (l) + pc;
190 (*info->print_address_func) (info->target, info);
193 print (info->stream, "0x%x",
194 (int)(EXTRACT_RVC_IMM (l) & (RISCV_BIGIMM_REACH-1)));
197 print (info->stream, "0x%x", (int)EXTRACT_RVC_IMM (l) & 0x3f);
200 print (info->stream, "0x%x", (int)EXTRACT_RVC_IMM (l) & 0x1f);
202 case 'T': /* floating-point RS2 */
203 print (info->stream, "%s",
204 riscv_fpr_names[EXTRACT_OPERAND (CRS2, l)]);
206 case 'D': /* floating-point RS2 x8-x15 */
207 print (info->stream, "%s",
208 riscv_fpr_names[EXTRACT_OPERAND (CRS2S, l) + 8]);
218 print (info->stream, "%c", *d);
222 /* Only print constant 0 if it is the last argument */
224 print (info->stream, "0");
229 if ((l & MASK_JALR) == MATCH_JALR)
230 maybe_print_address (pd, rs1, 0);
231 print (info->stream, "%s", riscv_gpr_names[rs1]);
235 print (info->stream, "%s",
236 riscv_gpr_names[EXTRACT_OPERAND (RS2, l)]);
240 print (info->stream, "0x%x",
241 (unsigned)EXTRACT_UTYPE_IMM (l) >> RISCV_IMM_BITS);
245 arg_print (info, EXTRACT_OPERAND (RM, l),
246 riscv_rm, ARRAY_SIZE (riscv_rm));
250 arg_print (info, EXTRACT_OPERAND (PRED, l),
251 riscv_pred_succ, ARRAY_SIZE (riscv_pred_succ));
255 arg_print (info, EXTRACT_OPERAND (SUCC, l),
256 riscv_pred_succ, ARRAY_SIZE (riscv_pred_succ));
260 maybe_print_address (pd, rs1, EXTRACT_ITYPE_IMM (l));
263 if (((l & MASK_ADDI) == MATCH_ADDI && rs1 != 0)
264 || (l & MASK_JALR) == MATCH_JALR)
265 maybe_print_address (pd, rs1, EXTRACT_ITYPE_IMM (l));
266 print (info->stream, "%d", (int)EXTRACT_ITYPE_IMM (l));
270 maybe_print_address (pd, rs1, EXTRACT_STYPE_IMM (l));
271 print (info->stream, "%d", (int)EXTRACT_STYPE_IMM (l));
275 info->target = EXTRACT_UJTYPE_IMM (l) + pc;
276 (*info->print_address_func) (info->target, info);
280 info->target = EXTRACT_SBTYPE_IMM (l) + pc;
281 (*info->print_address_func) (info->target, info);
285 if ((l & MASK_AUIPC) == MATCH_AUIPC)
286 pd->hi_addr[rd] = pc + EXTRACT_UTYPE_IMM (l);
287 else if ((l & MASK_LUI) == MATCH_LUI)
288 pd->hi_addr[rd] = EXTRACT_UTYPE_IMM (l);
289 else if ((l & MASK_C_LUI) == MATCH_C_LUI)
290 pd->hi_addr[rd] = EXTRACT_RVC_LUI_IMM (l);
291 print (info->stream, "%s", riscv_gpr_names[rd]);
295 print (info->stream, "%s", riscv_gpr_names[0]);
299 print (info->stream, "0x%x", (int)EXTRACT_OPERAND (SHAMT, l));
303 print (info->stream, "0x%x", (int)EXTRACT_OPERAND (SHAMTW, l));
308 print (info->stream, "%s", riscv_fpr_names[rs1]);
312 print (info->stream, "%s", riscv_fpr_names[EXTRACT_OPERAND (RS2, l)]);
316 print (info->stream, "%s", riscv_fpr_names[rd]);
320 print (info->stream, "%s", riscv_fpr_names[EXTRACT_OPERAND (RS3, l)]);
325 const char* csr_name = NULL;
326 unsigned int csr = EXTRACT_OPERAND (CSR, l);
329 #define DECLARE_CSR(name, num) case num: csr_name = #name; break;
330 #include "opcode/riscv-opc.h"
334 print (info->stream, "%s", csr_name);
336 print (info->stream, "0x%x", csr);
341 print (info->stream, "%d", rs1);
345 /* xgettext:c-format */
346 print (info->stream, _("# internal error, undefined modifier (%c)"),
353 /* Print the RISC-V instruction at address MEMADDR in debugged memory,
354 on using INFO. Returns length of the instruction, in bytes.
355 BIGENDIAN must be 1 if this is big-endian code, 0 if
356 this is little-endian code. */
359 riscv_disassemble_insn (bfd_vma memaddr, insn_t word, disassemble_info *info)
361 const struct riscv_opcode *op;
362 static bfd_boolean init = 0;
363 static const struct riscv_opcode *riscv_hash[OP_MASK_OP + 1];
364 struct riscv_private_data *pd;
367 #define OP_HASH_IDX(i) ((i) & (riscv_insn_length (i) == 2 ? 0x3 : OP_MASK_OP))
369 /* Build a hash table to shorten the search time. */
372 for (op = riscv_opcodes; op->name; op++)
373 if (!riscv_hash[OP_HASH_IDX (op->match)])
374 riscv_hash[OP_HASH_IDX (op->match)] = op;
379 if (info->private_data == NULL)
383 pd = info->private_data = xcalloc (1, sizeof (struct riscv_private_data));
386 for (i = 0; i < (int)ARRAY_SIZE (pd->hi_addr); i++)
389 for (i = 0; i < info->symtab_size; i++)
390 if (strcmp (bfd_asymbol_name (info->symtab[i]), RISCV_GP_SYMBOL) == 0)
391 pd->gp = bfd_asymbol_value (info->symtab[i]);
394 pd = info->private_data;
396 insnlen = riscv_insn_length (word);
398 info->bytes_per_chunk = insnlen % 4 == 0 ? 4 : 2;
399 info->bytes_per_line = 8;
400 info->display_endian = info->endian;
401 info->insn_info_valid = 1;
402 info->branch_delay_insns = 0;
404 info->insn_type = dis_nonbranch;
408 op = riscv_hash[OP_HASH_IDX (word)];
413 /* If XLEN is not known, get its value from the ELF class. */
414 if (info->mach == bfd_mach_riscv64)
416 else if (info->mach == bfd_mach_riscv32)
418 else if (info->section != NULL)
420 Elf_Internal_Ehdr *ehdr = elf_elfheader (info->section->owner);
421 xlen = ehdr->e_ident[EI_CLASS] == ELFCLASS64 ? 64 : 32;
424 for (; op->name; op++)
426 /* Does the opcode match? */
427 if (! (op->match_func) (op, word))
429 /* Is this a pseudo-instruction and may we print it as such? */
430 if (no_aliases && (op->pinfo & INSN_ALIAS))
432 /* Is this instruction restricted to a certain value of XLEN? */
433 if ((op->xlen_requirement != 0) && (op->xlen_requirement != xlen))
437 (*info->fprintf_func) (info->stream, "%s", op->name);
438 print_insn_args (op->args, word, memaddr, info);
440 /* Try to disassemble multi-instruction addressing sequences. */
441 if (pd->print_addr != (bfd_vma)-1)
443 info->target = pd->print_addr;
444 (*info->fprintf_func) (info->stream, " # ");
445 (*info->print_address_func) (info->target, info);
449 /* Finish filling out insn_info fields. */
450 switch (op->pinfo & INSN_TYPE)
453 info->insn_type = dis_branch;
455 case INSN_CONDBRANCH:
456 info->insn_type = dis_condbranch;
459 info->insn_type = dis_jsr;
462 info->insn_type = dis_dref;
468 if (op->pinfo & INSN_DATA_SIZE)
470 int size = ((op->pinfo & INSN_DATA_SIZE)
471 >> INSN_DATA_SIZE_SHIFT);
472 info->data_size = 1 << (size - 1);
479 /* We did not find a match, so just print the instruction bits. */
480 info->insn_type = dis_noninsn;
481 (*info->fprintf_func) (info->stream, "0x%llx", (unsigned long long)word);
486 print_insn_riscv (bfd_vma memaddr, struct disassemble_info *info)
493 if (info->disassembler_options != NULL)
495 parse_riscv_dis_options (info->disassembler_options);
496 /* Avoid repeatedly parsing the options. */
497 info->disassembler_options = NULL;
499 else if (riscv_gpr_names == NULL)
500 set_default_riscv_dis_options ();
502 /* Instructions are a sequence of 2-byte packets in little-endian order. */
503 for (n = 0; n < sizeof (insn) && n < riscv_insn_length (insn); n += 2)
505 status = (*info->read_memory_func) (memaddr + n, packet, 2, info);
508 /* Don't fail just because we fell off the end. */
511 (*info->memory_error_func) (status, memaddr, info);
515 insn |= ((insn_t) bfd_getl16 (packet)) << (8 * n);
518 return riscv_disassemble_insn (memaddr, insn, info);
522 print_riscv_disassembler_options (FILE *stream)
524 fprintf (stream, _("\n\
525 The following RISC-V-specific disassembler options are supported for use\n\
526 with the -M switch (multiple options should be separated by commas):\n"));
528 fprintf (stream, _("\n\
529 numeric Print numeric register names, rather than ABI names.\n"));
531 fprintf (stream, _("\n\
532 no-aliases Disassemble only into canonical instructions, rather\n\
533 than into pseudoinstructions.\n"));
535 fprintf (stream, _("\n"));