1 /* ppc-opc.c -- PowerPC opcode list
2 Copyright 1994, 1995, 1996, 1997, 1998, 2000, 2001, 2002, 2003
3 Free Software Foundation, Inc.
4 Written by Ian Lance Taylor, Cygnus Support
6 This file is part of GDB, GAS, and the GNU binutils.
8 GDB, GAS, and the GNU binutils are free software; you can redistribute
9 them and/or modify them under the terms of the GNU General Public
10 License as published by the Free Software Foundation; either version
11 2, or (at your option) any later version.
13 GDB, GAS, and the GNU binutils are distributed in the hope that they
14 will be useful, but WITHOUT ANY WARRANTY; without even the implied
15 warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See
16 the GNU General Public License for more details.
18 You should have received a copy of the GNU General Public License
19 along with this file; see the file COPYING. If not, write to the Free
20 Software Foundation, 59 Temple Place - Suite 330, Boston, MA
25 #include "opcode/ppc.h"
28 /* This file holds the PowerPC opcode table. The opcode table
29 includes almost all of the extended instruction mnemonics. This
30 permits the disassembler to use them, and simplifies the assembler
31 logic, at the cost of increasing the table size. The table is
32 strictly constant data, so the compiler should be able to put it in
35 This file also holds the operand table. All knowledge about
36 inserting operands into instructions and vice-versa is kept in this
39 /* Local insertion and extraction functions. */
41 static unsigned long insert_bat
42 PARAMS ((unsigned long, long, int, const char **));
43 static long extract_bat
44 PARAMS ((unsigned long, int, int *));
45 static unsigned long insert_bba
46 PARAMS ((unsigned long, long, int, const char **));
47 static long extract_bba
48 PARAMS ((unsigned long, int, int *));
49 static unsigned long insert_bd
50 PARAMS ((unsigned long, long, int, const char **));
51 static long extract_bd
52 PARAMS ((unsigned long, int, int *));
53 static unsigned long insert_bdm
54 PARAMS ((unsigned long, long, int, const char **));
55 static long extract_bdm
56 PARAMS ((unsigned long, int, int *));
57 static unsigned long insert_bdp
58 PARAMS ((unsigned long, long, int, const char **));
59 static long extract_bdp
60 PARAMS ((unsigned long, int, int *));
63 static unsigned long insert_bo
64 PARAMS ((unsigned long, long, int, const char **));
65 static long extract_bo
66 PARAMS ((unsigned long, int, int *));
67 static unsigned long insert_boe
68 PARAMS ((unsigned long, long, int, const char **));
69 static long extract_boe
70 PARAMS ((unsigned long, int, int *));
71 static unsigned long insert_dq
72 PARAMS ((unsigned long, long, int, const char **));
73 static long extract_dq
74 PARAMS ((unsigned long, int, int *));
75 static unsigned long insert_ds
76 PARAMS ((unsigned long, long, int, const char **));
77 static long extract_ds
78 PARAMS ((unsigned long, int, int *));
79 static unsigned long insert_de
80 PARAMS ((unsigned long, long, int, const char **));
81 static long extract_de
82 PARAMS ((unsigned long, int, int *));
83 static unsigned long insert_des
84 PARAMS ((unsigned long, long, int, const char **));
85 static long extract_des
86 PARAMS ((unsigned long, int, int *));
87 static unsigned long insert_li
88 PARAMS ((unsigned long, long, int, const char **));
89 static long extract_li
90 PARAMS ((unsigned long, int, int *));
91 static unsigned long insert_mbe
92 PARAMS ((unsigned long, long, int, const char **));
93 static long extract_mbe
94 PARAMS ((unsigned long, int, int *));
95 static unsigned long insert_mb6
96 PARAMS ((unsigned long, long, int, const char **));
97 static long extract_mb6
98 PARAMS ((unsigned long, int, int *));
99 static unsigned long insert_nb
100 PARAMS ((unsigned long, long, int, const char **));
101 static long extract_nb
102 PARAMS ((unsigned long, int, int *));
103 static unsigned long insert_nsi
104 PARAMS ((unsigned long, long, int, const char **));
105 static long extract_nsi
106 PARAMS ((unsigned long, int, int *));
107 static unsigned long insert_ral
108 PARAMS ((unsigned long, long, int, const char **));
109 static unsigned long insert_ram
110 PARAMS ((unsigned long, long, int, const char **));
111 static unsigned long insert_raq
112 PARAMS ((unsigned long, long, int, const char **));
113 static unsigned long insert_ras
114 PARAMS ((unsigned long, long, int, const char **));
115 static unsigned long insert_rbs
116 PARAMS ((unsigned long, long, int, const char **));
117 static long extract_rbs
118 PARAMS ((unsigned long, int, int *));
119 static unsigned long insert_rsq
120 PARAMS ((unsigned long, long, int, const char **));
121 static unsigned long insert_rtq
122 PARAMS ((unsigned long, long, int, const char **));
123 static unsigned long insert_sh6
124 PARAMS ((unsigned long, long, int, const char **));
125 static long extract_sh6
126 PARAMS ((unsigned long, int, int *));
127 static unsigned long insert_spr
128 PARAMS ((unsigned long, long, int, const char **));
129 static long extract_spr
130 PARAMS ((unsigned long, int, int *));
131 static unsigned long insert_tbr
132 PARAMS ((unsigned long, long, int, const char **));
133 static long extract_tbr
134 PARAMS ((unsigned long, int, int *));
135 static unsigned long insert_ev2
136 PARAMS ((unsigned long, long, int, const char **));
137 static long extract_ev2
138 PARAMS ((unsigned long, int, int *));
139 static unsigned long insert_ev4
140 PARAMS ((unsigned long, long, int, const char **));
141 static long extract_ev4
142 PARAMS ((unsigned long, int, int *));
143 static unsigned long insert_ev8
144 PARAMS ((unsigned long, long, int, const char **));
145 static long extract_ev8
146 PARAMS ((unsigned long, int, int *));
148 /* The operands table.
150 The fields are bits, shift, insert, extract, flags.
152 We used to put parens around the various additions, like the one
153 for BA just below. However, that caused trouble with feeble
154 compilers with a limit on depth of a parenthesized expression, like
155 (reportedly) the compiler in Microsoft Developer Studio 5. So we
156 omit the parens, since the macros are never used in a context where
157 the addition will be ambiguous. */
159 const struct powerpc_operand powerpc_operands[] =
161 /* The zero index is used to indicate the end of the list of
166 /* The BA field in an XL form instruction. */
167 #define BA UNUSED + 1
168 #define BA_MASK (0x1f << 16)
169 { 5, 16, 0, 0, PPC_OPERAND_CR },
171 /* The BA field in an XL form instruction when it must be the same
172 as the BT field in the same instruction. */
174 { 5, 16, insert_bat, extract_bat, PPC_OPERAND_FAKE },
176 /* The BB field in an XL form instruction. */
178 #define BB_MASK (0x1f << 11)
179 { 5, 11, 0, 0, PPC_OPERAND_CR },
181 /* The BB field in an XL form instruction when it must be the same
182 as the BA field in the same instruction. */
184 { 5, 11, insert_bba, extract_bba, PPC_OPERAND_FAKE },
186 /* The BD field in a B form instruction. The lower two bits are
189 { 16, 0, insert_bd, extract_bd, PPC_OPERAND_RELATIVE | PPC_OPERAND_SIGNED },
191 /* The BD field in a B form instruction when absolute addressing is
194 { 16, 0, insert_bd, extract_bd, PPC_OPERAND_ABSOLUTE | PPC_OPERAND_SIGNED },
196 /* The BD field in a B form instruction when the - modifier is used.
197 This sets the y bit of the BO field appropriately. */
199 { 16, 0, insert_bdm, extract_bdm,
200 PPC_OPERAND_RELATIVE | PPC_OPERAND_SIGNED },
202 /* The BD field in a B form instruction when the - modifier is used
203 and absolute address is used. */
205 { 16, 0, insert_bdm, extract_bdm,
206 PPC_OPERAND_ABSOLUTE | PPC_OPERAND_SIGNED },
208 /* The BD field in a B form instruction when the + modifier is used.
209 This sets the y bit of the BO field appropriately. */
211 { 16, 0, insert_bdp, extract_bdp,
212 PPC_OPERAND_RELATIVE | PPC_OPERAND_SIGNED },
214 /* The BD field in a B form instruction when the + modifier is used
215 and absolute addressing is used. */
217 { 16, 0, insert_bdp, extract_bdp,
218 PPC_OPERAND_ABSOLUTE | PPC_OPERAND_SIGNED },
220 /* The BF field in an X or XL form instruction. */
222 { 3, 23, 0, 0, PPC_OPERAND_CR },
224 /* An optional BF field. This is used for comparison instructions,
225 in which an omitted BF field is taken as zero. */
227 { 3, 23, 0, 0, PPC_OPERAND_CR | PPC_OPERAND_OPTIONAL },
229 /* The BFA field in an X or XL form instruction. */
231 { 3, 18, 0, 0, PPC_OPERAND_CR },
233 /* The BI field in a B form or XL form instruction. */
235 #define BI_MASK (0x1f << 16)
236 { 5, 16, 0, 0, PPC_OPERAND_CR },
238 /* The BO field in a B form instruction. Certain values are
241 #define BO_MASK (0x1f << 21)
242 { 5, 21, insert_bo, extract_bo, 0 },
244 /* The BO field in a B form instruction when the + or - modifier is
245 used. This is like the BO field, but it must be even. */
247 { 5, 21, insert_boe, extract_boe, 0 },
249 /* The BT field in an X or XL form instruction. */
251 { 5, 21, 0, 0, PPC_OPERAND_CR },
253 /* The condition register number portion of the BI field in a B form
254 or XL form instruction. This is used for the extended
255 conditional branch mnemonics, which set the lower two bits of the
256 BI field. This field is optional. */
258 { 3, 18, 0, 0, PPC_OPERAND_CR | PPC_OPERAND_OPTIONAL },
260 /* The CRB field in an X form instruction. */
264 /* The CRFD field in an X form instruction. */
266 { 3, 23, 0, 0, PPC_OPERAND_CR },
268 /* The CRFS field in an X form instruction. */
269 #define CRFS CRFD + 1
270 { 3, 0, 0, 0, PPC_OPERAND_CR },
272 /* The CT field in an X form instruction. */
274 { 5, 21, 0, 0, PPC_OPERAND_OPTIONAL },
276 /* The D field in a D form instruction. This is a displacement off
277 a register, and implies that the next operand is a register in
280 { 16, 0, 0, 0, PPC_OPERAND_PARENS | PPC_OPERAND_SIGNED },
282 /* The DE field in a DE form instruction. This is like D, but is 12
285 { 14, 0, insert_de, extract_de, PPC_OPERAND_PARENS },
287 /* The DES field in a DES form instruction. This is like DS, but is 14
288 bits only (12 stored.) */
290 { 14, 0, insert_des, extract_des, PPC_OPERAND_PARENS | PPC_OPERAND_SIGNED },
292 /* The DQ field in a DQ form instruction. This is like D, but the
293 lower four bits are forced to zero. */
295 { 16, 0, insert_dq, extract_dq,
296 PPC_OPERAND_PARENS | PPC_OPERAND_SIGNED | PPC_OPERAND_DQ },
298 /* The DS field in a DS form instruction. This is like D, but the
299 lower two bits are forced to zero. */
301 { 16, 0, insert_ds, extract_ds,
302 PPC_OPERAND_PARENS | PPC_OPERAND_SIGNED | PPC_OPERAND_DS },
304 /* The E field in a wrteei instruction. */
308 /* The FL1 field in a POWER SC form instruction. */
312 /* The FL2 field in a POWER SC form instruction. */
316 /* The FLM field in an XFL form instruction. */
320 /* The FRA field in an X or A form instruction. */
322 #define FRA_MASK (0x1f << 16)
323 { 5, 16, 0, 0, PPC_OPERAND_FPR },
325 /* The FRB field in an X or A form instruction. */
327 #define FRB_MASK (0x1f << 11)
328 { 5, 11, 0, 0, PPC_OPERAND_FPR },
330 /* The FRC field in an A form instruction. */
332 #define FRC_MASK (0x1f << 6)
333 { 5, 6, 0, 0, PPC_OPERAND_FPR },
335 /* The FRS field in an X form instruction or the FRT field in a D, X
336 or A form instruction. */
339 { 5, 21, 0, 0, PPC_OPERAND_FPR },
341 /* The FXM field in an XFX instruction. */
343 #define FXM_MASK (0xff << 12)
346 /* The L field in a D or X form instruction. */
348 { 1, 21, 0, 0, PPC_OPERAND_OPTIONAL },
350 /* The LEV field in a POWER SC form instruction. */
354 /* The LI field in an I form instruction. The lower two bits are
357 { 26, 0, insert_li, extract_li, PPC_OPERAND_RELATIVE | PPC_OPERAND_SIGNED },
359 /* The LI field in an I form instruction when used as an absolute
362 { 26, 0, insert_li, extract_li, PPC_OPERAND_ABSOLUTE | PPC_OPERAND_SIGNED },
364 /* The LS field in an X (sync) form instruction. */
366 { 2, 21, 0, 0, PPC_OPERAND_OPTIONAL },
368 /* The MB field in an M form instruction. */
370 #define MB_MASK (0x1f << 6)
373 /* The ME field in an M form instruction. */
375 #define ME_MASK (0x1f << 1)
378 /* The MB and ME fields in an M form instruction expressed a single
379 operand which is a bitmask indicating which bits to select. This
380 is a two operand form using PPC_OPERAND_NEXT. See the
381 description in opcode/ppc.h for what this means. */
383 { 5, 6, 0, 0, PPC_OPERAND_OPTIONAL | PPC_OPERAND_NEXT },
384 { 32, 0, insert_mbe, extract_mbe, 0 },
386 /* The MB or ME field in an MD or MDS form instruction. The high
387 bit is wrapped to the low end. */
390 #define MB6_MASK (0x3f << 5)
391 { 6, 5, insert_mb6, extract_mb6, 0 },
393 /* The MO field in an mbar instruction. */
397 /* The NB field in an X form instruction. The value 32 is stored as
400 { 6, 11, insert_nb, extract_nb, 0 },
402 /* The NSI field in a D form instruction. This is the same as the
403 SI field, only negated. */
405 { 16, 0, insert_nsi, extract_nsi,
406 PPC_OPERAND_NEGATIVE | PPC_OPERAND_SIGNED },
408 /* The RA field in an D, DS, DQ, X, XO, M, or MDS form instruction. */
410 #define RA_MASK (0x1f << 16)
411 { 5, 16, 0, 0, PPC_OPERAND_GPR },
413 /* The RA field in the DQ form lq instruction, which has special
414 value restrictions. */
416 { 5, 16, insert_raq, 0, PPC_OPERAND_GPR },
418 /* The RA field in a D or X form instruction which is an updating
419 load, which means that the RA field may not be zero and may not
420 equal the RT field. */
422 { 5, 16, insert_ral, 0, PPC_OPERAND_GPR },
424 /* The RA field in an lmw instruction, which has special value
427 { 5, 16, insert_ram, 0, PPC_OPERAND_GPR },
429 /* The RA field in a D or X form instruction which is an updating
430 store or an updating floating point load, which means that the RA
431 field may not be zero. */
433 { 5, 16, insert_ras, 0, PPC_OPERAND_GPR },
435 /* The RB field in an X, XO, M, or MDS form instruction. */
437 #define RB_MASK (0x1f << 11)
438 { 5, 11, 0, 0, PPC_OPERAND_GPR },
440 /* The RB field in an X form instruction when it must be the same as
441 the RS field in the instruction. This is used for extended
442 mnemonics like mr. */
444 { 5, 1, insert_rbs, extract_rbs, PPC_OPERAND_FAKE },
446 /* The RS field in a D, DS, X, XFX, XS, M, MD or MDS form
447 instruction or the RT field in a D, DS, X, XFX or XO form
451 #define RT_MASK (0x1f << 21)
452 { 5, 21, 0, 0, PPC_OPERAND_GPR },
454 /* The RS field of the DS form stq instruction, which has special
455 value restrictions. */
457 { 5, 21, insert_rsq, 0, PPC_OPERAND_GPR },
459 /* The RT field of the DQ form lq instruction, which has special
460 value restrictions. */
462 { 5, 21, insert_rtq, 0, PPC_OPERAND_GPR },
464 /* The SH field in an X or M form instruction. */
466 #define SH_MASK (0x1f << 11)
469 /* The SH field in an MD form instruction. This is split. */
471 #define SH6_MASK ((0x1f << 11) | (1 << 1))
472 { 6, 1, insert_sh6, extract_sh6, 0 },
474 /* The SI field in a D form instruction. */
476 { 16, 0, 0, 0, PPC_OPERAND_SIGNED },
478 /* The SI field in a D form instruction when we accept a wide range
479 of positive values. */
480 #define SISIGNOPT SI + 1
481 { 16, 0, 0, 0, PPC_OPERAND_SIGNED | PPC_OPERAND_SIGNOPT },
483 /* The SPR field in an XFX form instruction. This is flipped--the
484 lower 5 bits are stored in the upper 5 and vice- versa. */
485 #define SPR SISIGNOPT + 1
487 #define SPR_MASK (0x3ff << 11)
488 { 10, 11, insert_spr, extract_spr, 0 },
490 /* The BAT index number in an XFX form m[ft]ibat[lu] instruction. */
491 #define SPRBAT SPR + 1
492 #define SPRBAT_MASK (0x3 << 17)
495 /* The SPRG register number in an XFX form m[ft]sprg instruction. */
496 #define SPRG SPRBAT + 1
497 #define SPRG_MASK (0x3 << 16)
500 /* The SR field in an X form instruction. */
504 /* The STRM field in an X AltiVec form instruction. */
506 #define STRM_MASK (0x3 << 21)
509 /* The SV field in a POWER SC form instruction. */
513 /* The TBR field in an XFX form instruction. This is like the SPR
514 field, but it is optional. */
516 { 10, 11, insert_tbr, extract_tbr, PPC_OPERAND_OPTIONAL },
518 /* The TO field in a D or X form instruction. */
520 #define TO_MASK (0x1f << 21)
523 /* The U field in an X form instruction. */
527 /* The UI field in a D form instruction. */
531 /* The VA field in a VA, VX or VXR form instruction. */
533 #define VA_MASK (0x1f << 16)
534 { 5, 16, 0, 0, PPC_OPERAND_VR },
536 /* The VB field in a VA, VX or VXR form instruction. */
538 #define VB_MASK (0x1f << 11)
539 { 5, 11, 0, 0, PPC_OPERAND_VR },
541 /* The VC field in a VA form instruction. */
543 #define VC_MASK (0x1f << 6)
544 { 5, 6, 0, 0, PPC_OPERAND_VR },
546 /* The VD or VS field in a VA, VX, VXR or X form instruction. */
549 #define VD_MASK (0x1f << 21)
550 { 5, 21, 0, 0, PPC_OPERAND_VR },
552 /* The SIMM field in a VX form instruction. */
554 { 5, 16, 0, 0, PPC_OPERAND_SIGNED},
556 /* The UIMM field in a VX form instruction. */
557 #define UIMM SIMM + 1
560 /* The SHB field in a VA form instruction. */
564 /* The other UIMM field in a EVX form instruction. */
565 #define EVUIMM SHB + 1
568 /* The other UIMM field in a half word EVX form instruction. */
569 #define EVUIMM_2 EVUIMM + 1
570 { 32, 11, insert_ev2, extract_ev2, PPC_OPERAND_PARENS },
572 /* The other UIMM field in a word EVX form instruction. */
573 #define EVUIMM_4 EVUIMM_2 + 1
574 { 32, 11, insert_ev4, extract_ev4, PPC_OPERAND_PARENS },
576 /* The other UIMM field in a double EVX form instruction. */
577 #define EVUIMM_8 EVUIMM_4 + 1
578 { 32, 11, insert_ev8, extract_ev8, PPC_OPERAND_PARENS },
581 #define WS EVUIMM_8 + 1
582 #define WS_MASK (0x7 << 11)
585 /* The L field in an mtmsrd instruction */
586 #define MTMSRD_L WS + 1
587 { 1, 16, 0, 0, PPC_OPERAND_OPTIONAL },
591 /* The functions used to insert and extract complicated operands. */
593 /* The BA field in an XL form instruction when it must be the same as
594 the BT field in the same instruction. This operand is marked FAKE.
595 The insertion function just copies the BT field into the BA field,
596 and the extraction function just checks that the fields are the
601 insert_bat (insn, value, dialect, errmsg)
603 long value ATTRIBUTE_UNUSED;
604 int dialect ATTRIBUTE_UNUSED;
605 const char **errmsg ATTRIBUTE_UNUSED;
607 return insn | (((insn >> 21) & 0x1f) << 16);
611 extract_bat (insn, dialect, invalid)
613 int dialect ATTRIBUTE_UNUSED;
616 if (invalid != (int *) NULL
617 && ((insn >> 21) & 0x1f) != ((insn >> 16) & 0x1f))
622 /* The BB field in an XL form instruction when it must be the same as
623 the BA field in the same instruction. This operand is marked FAKE.
624 The insertion function just copies the BA field into the BB field,
625 and the extraction function just checks that the fields are the
630 insert_bba (insn, value, dialect, errmsg)
632 long value ATTRIBUTE_UNUSED;
633 int dialect ATTRIBUTE_UNUSED;
634 const char **errmsg ATTRIBUTE_UNUSED;
636 return insn | (((insn >> 16) & 0x1f) << 11);
640 extract_bba (insn, dialect, invalid)
642 int dialect ATTRIBUTE_UNUSED;
645 if (invalid != (int *) NULL
646 && ((insn >> 16) & 0x1f) != ((insn >> 11) & 0x1f))
651 /* The BD field in a B form instruction. The lower two bits are
656 insert_bd (insn, value, dialect, errmsg)
659 int dialect ATTRIBUTE_UNUSED;
660 const char **errmsg ATTRIBUTE_UNUSED;
662 return insn | (value & 0xfffc);
667 extract_bd (insn, dialect, invalid)
669 int dialect ATTRIBUTE_UNUSED;
670 int *invalid ATTRIBUTE_UNUSED;
672 return ((insn & 0xfffc) ^ 0x8000) - 0x8000;
675 /* The BD field in a B form instruction when the - modifier is used.
676 This modifier means that the branch is not expected to be taken.
677 For chips built to versions of the architecture prior to version 2
678 (ie. not Power4 compatible), we set the y bit of the BO field to 1
679 if the offset is negative. When extracting, we require that the y
680 bit be 1 and that the offset be positive, since if the y bit is 0
681 we just want to print the normal form of the instruction.
682 Power4 compatible targets use two bits, "a", and "t", instead of
683 the "y" bit. "at" == 00 => no hint, "at" == 01 => unpredictable,
684 "at" == 10 => not taken, "at" == 11 => taken. The "t" bit is 00001
685 in BO field, the "a" bit is 00010 for branch on CR(BI) and 01000
686 for branch on CTR. We only handle the taken/not-taken hint here. */
690 insert_bdm (insn, value, dialect, errmsg)
694 const char **errmsg ATTRIBUTE_UNUSED;
696 if ((dialect & PPC_OPCODE_POWER4) == 0)
698 if ((value & 0x8000) != 0)
703 if ((insn & (0x14 << 21)) == (0x04 << 21))
705 else if ((insn & (0x14 << 21)) == (0x10 << 21))
708 return insn | (value & 0xfffc);
712 extract_bdm (insn, dialect, invalid)
717 if (invalid != (int *) NULL)
719 if ((dialect & PPC_OPCODE_POWER4) == 0)
721 if (((insn & (1 << 21)) == 0) != ((insn & (1 << 15)) == 0))
726 if ((insn & (0x17 << 21)) != (0x06 << 21)
727 && (insn & (0x1d << 21)) != (0x18 << 21))
731 return ((insn & 0xfffc) ^ 0x8000) - 0x8000;
734 /* The BD field in a B form instruction when the + modifier is used.
735 This is like BDM, above, except that the branch is expected to be
740 insert_bdp (insn, value, dialect, errmsg)
744 const char **errmsg ATTRIBUTE_UNUSED;
746 if ((dialect & PPC_OPCODE_POWER4) == 0)
748 if ((value & 0x8000) == 0)
753 if ((insn & (0x14 << 21)) == (0x04 << 21))
755 else if ((insn & (0x14 << 21)) == (0x10 << 21))
758 return insn | (value & 0xfffc);
762 extract_bdp (insn, dialect, invalid)
767 if (invalid != (int *) NULL)
769 if ((dialect & PPC_OPCODE_POWER4) == 0)
771 if (((insn & (1 << 21)) == 0) == ((insn & (1 << 15)) == 0))
776 if ((insn & (0x17 << 21)) != (0x07 << 21)
777 && (insn & (0x1d << 21)) != (0x19 << 21))
781 return ((insn & 0xfffc) ^ 0x8000) - 0x8000;
784 /* Check for legal values of a BO field. */
787 valid_bo (value, dialect)
791 if ((dialect & PPC_OPCODE_POWER4) == 0)
793 /* Certain encodings have bits that are required to be zero.
794 These are (z must be zero, y may be anything):
801 switch (value & 0x14)
807 return (value & 0x2) == 0;
809 return (value & 0x8) == 0;
811 return value == 0x14;
816 /* Certain encodings have bits that are required to be zero.
817 These are (z must be zero, a & t may be anything):
828 if ((value & 0x14) == 0)
829 return (value & 0x1) == 0;
830 else if ((value & 0x14) == 0x14)
831 return value == 0x14;
837 /* The BO field in a B form instruction. Warn about attempts to set
838 the field to an illegal value. */
841 insert_bo (insn, value, dialect, errmsg)
847 if (errmsg != (const char **) NULL
848 && ! valid_bo (value, dialect))
849 *errmsg = _("invalid conditional option");
850 return insn | ((value & 0x1f) << 21);
854 extract_bo (insn, dialect, invalid)
861 value = (insn >> 21) & 0x1f;
862 if (invalid != (int *) NULL
863 && ! valid_bo (value, dialect))
868 /* The BO field in a B form instruction when the + or - modifier is
869 used. This is like the BO field, but it must be even. When
870 extracting it, we force it to be even. */
873 insert_boe (insn, value, dialect, errmsg)
879 if (errmsg != (const char **) NULL)
881 if (! valid_bo (value, dialect))
882 *errmsg = _("invalid conditional option");
883 else if ((value & 1) != 0)
884 *errmsg = _("attempt to set y bit when using + or - modifier");
886 return insn | ((value & 0x1f) << 21);
890 extract_boe (insn, dialect, invalid)
897 value = (insn >> 21) & 0x1f;
898 if (invalid != (int *) NULL
899 && ! valid_bo (value, dialect))
904 /* The DQ field in a DQ form instruction. This is like D, but the
905 lower four bits are forced to zero. */
909 insert_dq (insn, value, dialect, errmsg)
912 int dialect ATTRIBUTE_UNUSED;
913 const char ** errmsg ATTRIBUTE_UNUSED;
915 if ((value & 0xf) != 0 && errmsg != NULL)
916 *errmsg = _("offset not a multiple of 16");
917 return insn | (value & 0xfff0);
922 extract_dq (insn, dialect, invalid)
924 int dialect ATTRIBUTE_UNUSED;
925 int *invalid ATTRIBUTE_UNUSED;
927 return ((insn & 0xfff0) ^ 0x8000) - 0x8000;
931 insert_ev2 (insn, value, dialect, errmsg)
934 int dialect ATTRIBUTE_UNUSED;
935 const char ** errmsg ATTRIBUTE_UNUSED;
937 if ((value & 1) != 0 && errmsg != NULL)
938 *errmsg = _("offset not a multiple of 2");
939 if ((value > 62) != 0 && errmsg != NULL)
940 *errmsg = _("offset greater than 62");
941 return insn | ((value & 0x3e) << 10);
945 extract_ev2 (insn, dialect, invalid)
947 int dialect ATTRIBUTE_UNUSED;
948 int * invalid ATTRIBUTE_UNUSED;
950 return (insn >> 10) & 0x3e;
954 insert_ev4 (insn, value, dialect, errmsg)
957 int dialect ATTRIBUTE_UNUSED;
958 const char ** errmsg ATTRIBUTE_UNUSED;
960 if ((value & 3) != 0 && errmsg != NULL)
961 *errmsg = _("offset not a multiple of 4");
962 if ((value > 124) != 0 && errmsg != NULL)
963 *errmsg = _("offset greater than 124");
964 return insn | ((value & 0x7c) << 9);
968 extract_ev4 (insn, dialect, invalid)
970 int dialect ATTRIBUTE_UNUSED;
971 int * invalid ATTRIBUTE_UNUSED;
973 return (insn >> 9) & 0x7c;
977 insert_ev8 (insn, value, dialect, errmsg)
980 int dialect ATTRIBUTE_UNUSED;
981 const char ** errmsg ATTRIBUTE_UNUSED;
983 if ((value & 7) != 0 && errmsg != NULL)
984 *errmsg = _("offset not a multiple of 8");
985 if ((value > 248) != 0 && errmsg != NULL)
986 *errmsg = _("offset greater than 248");
987 return insn | ((value & 0xf8) << 8);
991 extract_ev8 (insn, dialect, invalid)
993 int dialect ATTRIBUTE_UNUSED;
994 int * invalid ATTRIBUTE_UNUSED;
996 return (insn >> 8) & 0xf8;
999 /* The DS field in a DS form instruction. This is like D, but the
1000 lower two bits are forced to zero. */
1003 static unsigned long
1004 insert_ds (insn, value, dialect, errmsg)
1007 int dialect ATTRIBUTE_UNUSED;
1008 const char **errmsg;
1010 if ((value & 3) != 0 && errmsg != NULL)
1011 *errmsg = _("offset not a multiple of 4");
1012 return insn | (value & 0xfffc);
1017 extract_ds (insn, dialect, invalid)
1019 int dialect ATTRIBUTE_UNUSED;
1020 int *invalid ATTRIBUTE_UNUSED;
1022 return ((insn & 0xfffc) ^ 0x8000) - 0x8000;
1025 /* The DE field in a DE form instruction. */
1028 static unsigned long
1029 insert_de (insn, value, dialect, errmsg)
1032 int dialect ATTRIBUTE_UNUSED;
1033 const char **errmsg;
1035 if ((value > 2047 || value < -2048) && errmsg != NULL)
1036 *errmsg = _("offset not between -2048 and 2047");
1037 return insn | ((value << 4) & 0xfff0);
1042 extract_de (insn, dialect, invalid)
1044 int dialect ATTRIBUTE_UNUSED;
1045 int *invalid ATTRIBUTE_UNUSED;
1047 return (insn & 0xfff0) >> 4;
1050 /* The DES field in a DES form instruction. */
1053 static unsigned long
1054 insert_des (insn, value, dialect, errmsg)
1057 int dialect ATTRIBUTE_UNUSED;
1058 const char **errmsg;
1060 if ((value > 8191 || value < -8192) && errmsg != NULL)
1061 *errmsg = _("offset not between -8192 and 8191");
1062 else if ((value & 3) != 0 && errmsg != NULL)
1063 *errmsg = _("offset not a multiple of 4");
1064 return insn | ((value << 2) & 0xfff0);
1069 extract_des (insn, dialect, invalid)
1071 int dialect ATTRIBUTE_UNUSED;
1072 int *invalid ATTRIBUTE_UNUSED;
1074 return (((insn >> 2) & 0x3ffc) ^ 0x2000) - 0x2000;
1077 /* The LI field in an I form instruction. The lower two bits are
1081 static unsigned long
1082 insert_li (insn, value, dialect, errmsg)
1085 int dialect ATTRIBUTE_UNUSED;
1086 const char **errmsg;
1088 if ((value & 3) != 0 && errmsg != (const char **) NULL)
1089 *errmsg = _("ignoring least significant bits in branch offset");
1090 return insn | (value & 0x3fffffc);
1095 extract_li (insn, dialect, invalid)
1097 int dialect ATTRIBUTE_UNUSED;
1098 int *invalid ATTRIBUTE_UNUSED;
1100 return ((insn & 0x3fffffc) ^ 0x2000000) - 0x2000000;
1103 /* The MB and ME fields in an M form instruction expressed as a single
1104 operand which is itself a bitmask. The extraction function always
1105 marks it as invalid, since we never want to recognize an
1106 instruction which uses a field of this type. */
1108 static unsigned long
1109 insert_mbe (insn, value, dialect, errmsg)
1112 int dialect ATTRIBUTE_UNUSED;
1113 const char **errmsg;
1115 unsigned long uval, mask;
1116 int mb, me, mx, count, last;
1122 if (errmsg != (const char **) NULL)
1123 *errmsg = _("illegal bitmask");
1129 if ((uval & 1) != 0)
1135 /* mb: location of last 0->1 transition */
1136 /* me: location of last 1->0 transition */
1137 /* count: # transitions */
1139 for (mx = 0, mask = (long) 1 << 31; mx < 32; ++mx, mask >>= 1)
1141 if ((uval & mask) && !last)
1147 else if (!(uval & mask) && last)
1157 if (count != 2 && (count != 0 || ! last))
1159 if (errmsg != (const char **) NULL)
1160 *errmsg = _("illegal bitmask");
1163 return insn | (mb << 6) | ((me - 1) << 1);
1167 extract_mbe (insn, dialect, invalid)
1169 int dialect ATTRIBUTE_UNUSED;
1176 if (invalid != (int *) NULL)
1179 mb = (insn >> 6) & 0x1f;
1180 me = (insn >> 1) & 0x1f;
1184 for (i = mb; i <= me; i++)
1185 ret |= (long) 1 << (31 - i);
1187 else if (mb == me + 1)
1189 else /* (mb > me + 1) */
1192 for (i = me + 1; i < mb; i++)
1193 ret &= ~ ((long) 1 << (31 - i));
1198 /* The MB or ME field in an MD or MDS form instruction. The high bit
1199 is wrapped to the low end. */
1202 static unsigned long
1203 insert_mb6 (insn, value, dialect, errmsg)
1206 int dialect ATTRIBUTE_UNUSED;
1207 const char **errmsg ATTRIBUTE_UNUSED;
1209 return insn | ((value & 0x1f) << 6) | (value & 0x20);
1214 extract_mb6 (insn, dialect, invalid)
1216 int dialect ATTRIBUTE_UNUSED;
1217 int *invalid ATTRIBUTE_UNUSED;
1219 return ((insn >> 6) & 0x1f) | (insn & 0x20);
1222 /* The NB field in an X form instruction. The value 32 is stored as
1225 static unsigned long
1226 insert_nb (insn, value, dialect, errmsg)
1229 int dialect ATTRIBUTE_UNUSED;
1230 const char **errmsg;
1232 if (value < 0 || value > 32)
1233 *errmsg = _("value out of range");
1236 return insn | ((value & 0x1f) << 11);
1241 extract_nb (insn, dialect, invalid)
1243 int dialect ATTRIBUTE_UNUSED;
1244 int *invalid ATTRIBUTE_UNUSED;
1248 ret = (insn >> 11) & 0x1f;
1254 /* The NSI field in a D form instruction. This is the same as the SI
1255 field, only negated. The extraction function always marks it as
1256 invalid, since we never want to recognize an instruction which uses
1257 a field of this type. */
1260 static unsigned long
1261 insert_nsi (insn, value, dialect, errmsg)
1264 int dialect ATTRIBUTE_UNUSED;
1265 const char **errmsg ATTRIBUTE_UNUSED;
1267 return insn | ((- value) & 0xffff);
1271 extract_nsi (insn, dialect, invalid)
1273 int dialect ATTRIBUTE_UNUSED;
1276 if (invalid != (int *) NULL)
1278 return - (((insn & 0xffff) ^ 0x8000) - 0x8000);
1281 /* The RA field in a D or X form instruction which is an updating
1282 load, which means that the RA field may not be zero and may not
1283 equal the RT field. */
1285 static unsigned long
1286 insert_ral (insn, value, dialect, errmsg)
1289 int dialect ATTRIBUTE_UNUSED;
1290 const char **errmsg;
1293 || (unsigned long) value == ((insn >> 21) & 0x1f))
1294 *errmsg = "invalid register operand when updating";
1295 return insn | ((value & 0x1f) << 16);
1298 /* The RA field in an lmw instruction, which has special value
1301 static unsigned long
1302 insert_ram (insn, value, dialect, errmsg)
1305 int dialect ATTRIBUTE_UNUSED;
1306 const char **errmsg;
1308 if ((unsigned long) value >= ((insn >> 21) & 0x1f))
1309 *errmsg = _("index register in load range");
1310 return insn | ((value & 0x1f) << 16);
1313 /* The RA field in the DQ form lq instruction, which has special
1314 value restrictions. */
1317 static unsigned long
1318 insert_raq (insn, value, dialect, errmsg)
1321 int dialect ATTRIBUTE_UNUSED;
1322 const char **errmsg;
1324 long rtvalue = (insn & RT_MASK) >> 21;
1326 if (value == rtvalue && errmsg != NULL)
1327 *errmsg = _("source and target register operands must be different");
1328 return insn | ((value & 0x1f) << 16);
1331 /* The RA field in a D or X form instruction which is an updating
1332 store or an updating floating point load, which means that the RA
1333 field may not be zero. */
1335 static unsigned long
1336 insert_ras (insn, value, dialect, errmsg)
1339 int dialect ATTRIBUTE_UNUSED;
1340 const char **errmsg;
1343 *errmsg = _("invalid register operand when updating");
1344 return insn | ((value & 0x1f) << 16);
1347 /* The RB field in an X form instruction when it must be the same as
1348 the RS field in the instruction. This is used for extended
1349 mnemonics like mr. This operand is marked FAKE. The insertion
1350 function just copies the BT field into the BA field, and the
1351 extraction function just checks that the fields are the same. */
1354 static unsigned long
1355 insert_rbs (insn, value, dialect, errmsg)
1357 long value ATTRIBUTE_UNUSED;
1358 int dialect ATTRIBUTE_UNUSED;
1359 const char **errmsg ATTRIBUTE_UNUSED;
1361 return insn | (((insn >> 21) & 0x1f) << 11);
1365 extract_rbs (insn, dialect, invalid)
1367 int dialect ATTRIBUTE_UNUSED;
1370 if (invalid != (int *) NULL
1371 && ((insn >> 21) & 0x1f) != ((insn >> 11) & 0x1f))
1376 /* The RT field of the DQ form lq instruction, which has special
1377 value restrictions. */
1380 static unsigned long
1381 insert_rtq (insn, value, dialect, errmsg)
1384 int dialect ATTRIBUTE_UNUSED;
1385 const char **errmsg;
1387 if ((value & 1) != 0 && errmsg != NULL)
1388 *errmsg = _("target register operand must be even");
1389 return insn | ((value & 0x1f) << 21);
1392 /* The RS field of the DS form stq instruction, which has special
1393 value restrictions. */
1396 static unsigned long
1397 insert_rsq (insn, value, dialect, errmsg)
1399 long value ATTRIBUTE_UNUSED;
1400 int dialect ATTRIBUTE_UNUSED;
1401 const char **errmsg;
1403 if ((value & 1) != 0 && errmsg != NULL)
1404 *errmsg = _("source register operand must be even");
1405 return insn | ((value & 0x1f) << 21);
1408 /* The SH field in an MD form instruction. This is split. */
1411 static unsigned long
1412 insert_sh6 (insn, value, dialect, errmsg)
1415 int dialect ATTRIBUTE_UNUSED;
1416 const char **errmsg ATTRIBUTE_UNUSED;
1418 return insn | ((value & 0x1f) << 11) | ((value & 0x20) >> 4);
1423 extract_sh6 (insn, dialect, invalid)
1425 int dialect ATTRIBUTE_UNUSED;
1426 int *invalid ATTRIBUTE_UNUSED;
1428 return ((insn >> 11) & 0x1f) | ((insn << 4) & 0x20);
1431 /* The SPR field in an XFX form instruction. This is flipped--the
1432 lower 5 bits are stored in the upper 5 and vice- versa. */
1434 static unsigned long
1435 insert_spr (insn, value, dialect, errmsg)
1438 int dialect ATTRIBUTE_UNUSED;
1439 const char **errmsg ATTRIBUTE_UNUSED;
1441 return insn | ((value & 0x1f) << 16) | ((value & 0x3e0) << 6);
1445 extract_spr (insn, dialect, invalid)
1447 int dialect ATTRIBUTE_UNUSED;
1448 int *invalid ATTRIBUTE_UNUSED;
1450 return ((insn >> 16) & 0x1f) | ((insn >> 6) & 0x3e0);
1453 /* The TBR field in an XFX instruction. This is just like SPR, but it
1454 is optional. When TBR is omitted, it must be inserted as 268 (the
1455 magic number of the TB register). These functions treat 0
1456 (indicating an omitted optional operand) as 268. This means that
1457 ``mftb 4,0'' is not handled correctly. This does not matter very
1458 much, since the architecture manual does not define mftb as
1459 accepting any values other than 268 or 269. */
1463 static unsigned long
1464 insert_tbr (insn, value, dialect, errmsg)
1467 int dialect ATTRIBUTE_UNUSED;
1468 const char **errmsg ATTRIBUTE_UNUSED;
1472 return insn | ((value & 0x1f) << 16) | ((value & 0x3e0) << 6);
1476 extract_tbr (insn, dialect, invalid)
1478 int dialect ATTRIBUTE_UNUSED;
1479 int *invalid ATTRIBUTE_UNUSED;
1483 ret = ((insn >> 16) & 0x1f) | ((insn >> 6) & 0x3e0);
1489 /* Macros used to form opcodes. */
1491 /* The main opcode. */
1492 #define OP(x) ((((unsigned long)(x)) & 0x3f) << 26)
1493 #define OP_MASK OP (0x3f)
1495 /* The main opcode combined with a trap code in the TO field of a D
1496 form instruction. Used for extended mnemonics for the trap
1498 #define OPTO(x,to) (OP (x) | ((((unsigned long)(to)) & 0x1f) << 21))
1499 #define OPTO_MASK (OP_MASK | TO_MASK)
1501 /* The main opcode combined with a comparison size bit in the L field
1502 of a D form or X form instruction. Used for extended mnemonics for
1503 the comparison instructions. */
1504 #define OPL(x,l) (OP (x) | ((((unsigned long)(l)) & 1) << 21))
1505 #define OPL_MASK OPL (0x3f,1)
1507 /* An A form instruction. */
1508 #define A(op, xop, rc) (OP (op) | ((((unsigned long)(xop)) & 0x1f) << 1) | (((unsigned long)(rc)) & 1))
1509 #define A_MASK A (0x3f, 0x1f, 1)
1511 /* An A_MASK with the FRB field fixed. */
1512 #define AFRB_MASK (A_MASK | FRB_MASK)
1514 /* An A_MASK with the FRC field fixed. */
1515 #define AFRC_MASK (A_MASK | FRC_MASK)
1517 /* An A_MASK with the FRA and FRC fields fixed. */
1518 #define AFRAFRC_MASK (A_MASK | FRA_MASK | FRC_MASK)
1520 /* A B form instruction. */
1521 #define B(op, aa, lk) (OP (op) | ((((unsigned long)(aa)) & 1) << 1) | ((lk) & 1))
1522 #define B_MASK B (0x3f, 1, 1)
1524 /* A B form instruction setting the BO field. */
1525 #define BBO(op, bo, aa, lk) (B ((op), (aa), (lk)) | ((((unsigned long)(bo)) & 0x1f) << 21))
1526 #define BBO_MASK BBO (0x3f, 0x1f, 1, 1)
1528 /* A BBO_MASK with the y bit of the BO field removed. This permits
1529 matching a conditional branch regardless of the setting of the y
1530 bit. Similarly for the 'at' bits used for power4 branch hints. */
1531 #define Y_MASK (((unsigned long) 1) << 21)
1532 #define AT1_MASK (((unsigned long) 3) << 21)
1533 #define AT2_MASK (((unsigned long) 9) << 21)
1534 #define BBOY_MASK (BBO_MASK &~ Y_MASK)
1535 #define BBOAT_MASK (BBO_MASK &~ AT1_MASK)
1537 /* A B form instruction setting the BO field and the condition bits of
1539 #define BBOCB(op, bo, cb, aa, lk) \
1540 (BBO ((op), (bo), (aa), (lk)) | ((((unsigned long)(cb)) & 0x3) << 16))
1541 #define BBOCB_MASK BBOCB (0x3f, 0x1f, 0x3, 1, 1)
1543 /* A BBOCB_MASK with the y bit of the BO field removed. */
1544 #define BBOYCB_MASK (BBOCB_MASK &~ Y_MASK)
1545 #define BBOATCB_MASK (BBOCB_MASK &~ AT1_MASK)
1546 #define BBOAT2CB_MASK (BBOCB_MASK &~ AT2_MASK)
1548 /* A BBOYCB_MASK in which the BI field is fixed. */
1549 #define BBOYBI_MASK (BBOYCB_MASK | BI_MASK)
1550 #define BBOATBI_MASK (BBOAT2CB_MASK | BI_MASK)
1552 /* An Context form instruction. */
1553 #define CTX(op, xop) (OP (op) | (((unsigned long)(xop)) & 0x7))
1554 #define CTX_MASK CTX(0x3f, 0x7)
1556 /* An User Context form instruction. */
1557 #define UCTX(op, xop) (OP (op) | (((unsigned long)(xop)) & 0x1f))
1558 #define UCTX_MASK UCTX(0x3f, 0x1f)
1560 /* The main opcode mask with the RA field clear. */
1561 #define DRA_MASK (OP_MASK | RA_MASK)
1563 /* A DS form instruction. */
1564 #define DSO(op, xop) (OP (op) | ((xop) & 0x3))
1565 #define DS_MASK DSO (0x3f, 3)
1567 /* A DE form instruction. */
1568 #define DEO(op, xop) (OP (op) | ((xop) & 0xf))
1569 #define DE_MASK DEO (0x3e, 0xf)
1571 /* An EVSEL form instruction. */
1572 #define EVSEL(op, xop) (OP (op) | (((unsigned long)(xop)) & 0xff) << 3)
1573 #define EVSEL_MASK EVSEL(0x3f, 0xff)
1575 /* An M form instruction. */
1576 #define M(op, rc) (OP (op) | ((rc) & 1))
1577 #define M_MASK M (0x3f, 1)
1579 /* An M form instruction with the ME field specified. */
1580 #define MME(op, me, rc) (M ((op), (rc)) | ((((unsigned long)(me)) & 0x1f) << 1))
1582 /* An M_MASK with the MB and ME fields fixed. */
1583 #define MMBME_MASK (M_MASK | MB_MASK | ME_MASK)
1585 /* An M_MASK with the SH and ME fields fixed. */
1586 #define MSHME_MASK (M_MASK | SH_MASK | ME_MASK)
1588 /* An MD form instruction. */
1589 #define MD(op, xop, rc) (OP (op) | ((((unsigned long)(xop)) & 0x7) << 2) | ((rc) & 1))
1590 #define MD_MASK MD (0x3f, 0x7, 1)
1592 /* An MD_MASK with the MB field fixed. */
1593 #define MDMB_MASK (MD_MASK | MB6_MASK)
1595 /* An MD_MASK with the SH field fixed. */
1596 #define MDSH_MASK (MD_MASK | SH6_MASK)
1598 /* An MDS form instruction. */
1599 #define MDS(op, xop, rc) (OP (op) | ((((unsigned long)(xop)) & 0xf) << 1) | ((rc) & 1))
1600 #define MDS_MASK MDS (0x3f, 0xf, 1)
1602 /* An MDS_MASK with the MB field fixed. */
1603 #define MDSMB_MASK (MDS_MASK | MB6_MASK)
1605 /* An SC form instruction. */
1606 #define SC(op, sa, lk) (OP (op) | ((((unsigned long)(sa)) & 1) << 1) | ((lk) & 1))
1607 #define SC_MASK (OP_MASK | (((unsigned long)0x3ff) << 16) | (((unsigned long)1) << 1) | 1)
1609 /* An VX form instruction. */
1610 #define VX(op, xop) (OP (op) | (((unsigned long)(xop)) & 0x7ff))
1612 /* The mask for an VX form instruction. */
1613 #define VX_MASK VX(0x3f, 0x7ff)
1615 /* An VA form instruction. */
1616 #define VXA(op, xop) (OP (op) | (((unsigned long)(xop)) & 0x03f))
1618 /* The mask for an VA form instruction. */
1619 #define VXA_MASK VXA(0x3f, 0x3f)
1621 /* An VXR form instruction. */
1622 #define VXR(op, xop, rc) (OP (op) | (((rc) & 1) << 10) | (((unsigned long)(xop)) & 0x3ff))
1624 /* The mask for a VXR form instruction. */
1625 #define VXR_MASK VXR(0x3f, 0x3ff, 1)
1627 /* An X form instruction. */
1628 #define X(op, xop) (OP (op) | ((((unsigned long)(xop)) & 0x3ff) << 1))
1630 /* An X form instruction with the RC bit specified. */
1631 #define XRC(op, xop, rc) (X ((op), (xop)) | ((rc) & 1))
1633 /* The mask for an X form instruction. */
1634 #define X_MASK XRC (0x3f, 0x3ff, 1)
1636 /* An X_MASK with the RA field fixed. */
1637 #define XRA_MASK (X_MASK | RA_MASK)
1639 /* An X_MASK with the RB field fixed. */
1640 #define XRB_MASK (X_MASK | RB_MASK)
1642 /* An X_MASK with the RT field fixed. */
1643 #define XRT_MASK (X_MASK | RT_MASK)
1645 /* An X_MASK with the RA and RB fields fixed. */
1646 #define XRARB_MASK (X_MASK | RA_MASK | RB_MASK)
1648 /* An XRARB_MASK, but with the L bit clear. */
1649 #define XRLARB_MASK (XRARB_MASK & ~((unsigned long) 1 << 16))
1651 /* An X_MASK with the RT and RA fields fixed. */
1652 #define XRTRA_MASK (X_MASK | RT_MASK | RA_MASK)
1654 /* An XRTRA_MASK, but with L bit clear. */
1655 #define XRTLRA_MASK (XRTRA_MASK & ~((unsigned long) 1 << 21))
1657 /* An X form comparison instruction. */
1658 #define XCMPL(op, xop, l) (X ((op), (xop)) | ((((unsigned long)(l)) & 1) << 21))
1660 /* The mask for an X form comparison instruction. */
1661 #define XCMP_MASK (X_MASK | (((unsigned long)1) << 22))
1663 /* The mask for an X form comparison instruction with the L field
1665 #define XCMPL_MASK (XCMP_MASK | (((unsigned long)1) << 21))
1667 /* An X form trap instruction with the TO field specified. */
1668 #define XTO(op, xop, to) (X ((op), (xop)) | ((((unsigned long)(to)) & 0x1f) << 21))
1669 #define XTO_MASK (X_MASK | TO_MASK)
1671 /* An X form tlb instruction with the SH field specified. */
1672 #define XTLB(op, xop, sh) (X ((op), (xop)) | ((((unsigned long)(sh)) & 0x1f) << 11))
1673 #define XTLB_MASK (X_MASK | SH_MASK)
1675 /* An X form sync instruction. */
1676 #define XSYNC(op, xop, l) (X ((op), (xop)) | ((((unsigned long)(l)) & 3) << 21))
1678 /* An X form sync instruction with everything filled in except the LS field. */
1679 #define XSYNC_MASK (0xff9fffff)
1681 /* An X form AltiVec dss instruction. */
1682 #define XDSS(op, xop, a) (X ((op), (xop)) | ((((unsigned long)(a)) & 1) << 25))
1683 #define XDSS_MASK XDSS(0x3f, 0x3ff, 1)
1685 /* An XFL form instruction. */
1686 #define XFL(op, xop, rc) (OP (op) | ((((unsigned long)(xop)) & 0x3ff) << 1) | (((unsigned long)(rc)) & 1))
1687 #define XFL_MASK (XFL (0x3f, 0x3ff, 1) | (((unsigned long)1) << 25) | (((unsigned long)1) << 16))
1689 /* An X form isel instruction. */
1690 #define XISEL(op, xop) (OP (op) | ((((unsigned long)(xop)) & 0x1f) << 1))
1691 #define XISEL_MASK XISEL(0x3f, 0x1f)
1693 /* An XL form instruction with the LK field set to 0. */
1694 #define XL(op, xop) (OP (op) | ((((unsigned long)(xop)) & 0x3ff) << 1))
1696 /* An XL form instruction which uses the LK field. */
1697 #define XLLK(op, xop, lk) (XL ((op), (xop)) | ((lk) & 1))
1699 /* The mask for an XL form instruction. */
1700 #define XL_MASK XLLK (0x3f, 0x3ff, 1)
1702 /* An XL form instruction which explicitly sets the BO field. */
1703 #define XLO(op, bo, xop, lk) \
1704 (XLLK ((op), (xop), (lk)) | ((((unsigned long)(bo)) & 0x1f) << 21))
1705 #define XLO_MASK (XL_MASK | BO_MASK)
1707 /* An XL form instruction which explicitly sets the y bit of the BO
1709 #define XLYLK(op, xop, y, lk) (XLLK ((op), (xop), (lk)) | ((((unsigned long)(y)) & 1) << 21))
1710 #define XLYLK_MASK (XL_MASK | Y_MASK)
1712 /* An XL form instruction which sets the BO field and the condition
1713 bits of the BI field. */
1714 #define XLOCB(op, bo, cb, xop, lk) \
1715 (XLO ((op), (bo), (xop), (lk)) | ((((unsigned long)(cb)) & 3) << 16))
1716 #define XLOCB_MASK XLOCB (0x3f, 0x1f, 0x3, 0x3ff, 1)
1718 /* An XL_MASK or XLYLK_MASK or XLOCB_MASK with the BB field fixed. */
1719 #define XLBB_MASK (XL_MASK | BB_MASK)
1720 #define XLYBB_MASK (XLYLK_MASK | BB_MASK)
1721 #define XLBOCBBB_MASK (XLOCB_MASK | BB_MASK)
1723 /* An XL_MASK with the BO and BB fields fixed. */
1724 #define XLBOBB_MASK (XL_MASK | BO_MASK | BB_MASK)
1726 /* An XL_MASK with the BO, BI and BB fields fixed. */
1727 #define XLBOBIBB_MASK (XL_MASK | BO_MASK | BI_MASK | BB_MASK)
1729 /* An XO form instruction. */
1730 #define XO(op, xop, oe, rc) \
1731 (OP (op) | ((((unsigned long)(xop)) & 0x1ff) << 1) | ((((unsigned long)(oe)) & 1) << 10) | (((unsigned long)(rc)) & 1))
1732 #define XO_MASK XO (0x3f, 0x1ff, 1, 1)
1734 /* An XO_MASK with the RB field fixed. */
1735 #define XORB_MASK (XO_MASK | RB_MASK)
1737 /* An XS form instruction. */
1738 #define XS(op, xop, rc) (OP (op) | ((((unsigned long)(xop)) & 0x1ff) << 2) | (((unsigned long)(rc)) & 1))
1739 #define XS_MASK XS (0x3f, 0x1ff, 1)
1741 /* A mask for the FXM version of an XFX form instruction. */
1742 #define XFXFXM_MASK (X_MASK | (((unsigned long)1) << 20) | (((unsigned long)1) << 11))
1744 /* An XFX form instruction with the FXM field filled in. */
1745 #define XFXM(op, xop, fxm) \
1746 (X ((op), (xop)) | ((((unsigned long)(fxm)) & 0xff) << 12))
1748 /* An XFX form instruction with the SPR field filled in. */
1749 #define XSPR(op, xop, spr) \
1750 (X ((op), (xop)) | ((((unsigned long)(spr)) & 0x1f) << 16) | ((((unsigned long)(spr)) & 0x3e0) << 6))
1751 #define XSPR_MASK (X_MASK | SPR_MASK)
1753 /* An XFX form instruction with the SPR field filled in except for the
1755 #define XSPRBAT_MASK (XSPR_MASK &~ SPRBAT_MASK)
1757 /* An XFX form instruction with the SPR field filled in except for the
1759 #define XSPRG_MASK (XSPR_MASK &~ SPRG_MASK)
1761 /* An X form instruction with everything filled in except the E field. */
1762 #define XE_MASK (0xffff7fff)
1764 /* An X form user context instruction. */
1765 #define XUC(op, xop) (OP (op) | (((unsigned long)(xop)) & 0x1f))
1766 #define XUC_MASK XUC(0x3f, 0x1f)
1768 /* The BO encodings used in extended conditional branch mnemonics. */
1769 #define BODNZF (0x0)
1770 #define BODNZFP (0x1)
1772 #define BODZFP (0x3)
1773 #define BODNZT (0x8)
1774 #define BODNZTP (0x9)
1776 #define BODZTP (0xb)
1787 #define BODNZ (0x10)
1788 #define BODNZP (0x11)
1790 #define BODZP (0x13)
1791 #define BODNZM4 (0x18)
1792 #define BODNZP4 (0x19)
1793 #define BODZM4 (0x1a)
1794 #define BODZP4 (0x1b)
1798 /* The BI condition bit encodings used in extended conditional branch
1805 /* The TO encodings used in extended trap mnemonics. */
1822 /* Smaller names for the flags so each entry in the opcodes table will
1823 fit on a single line. */
1825 #define PPC PPC_OPCODE_PPC | PPC_OPCODE_ANY
1826 #define PPCCOM PPC_OPCODE_PPC | PPC_OPCODE_COMMON | PPC_OPCODE_ANY
1827 #define NOPOWER4 PPC_OPCODE_NOPOWER4 | PPCCOM
1828 #define POWER4 PPC_OPCODE_POWER4 | PPCCOM
1829 #define PPC32 PPC_OPCODE_32 | PPC_OPCODE_PPC | PPC_OPCODE_ANY
1830 #define PPC64 PPC_OPCODE_64 | PPC_OPCODE_PPC | PPC_OPCODE_ANY
1831 #define PPCONLY PPC_OPCODE_PPC
1832 #define PPC403 PPC_OPCODE_403
1833 #define PPC405 PPC403
1836 #define PPCVEC PPC_OPCODE_ALTIVEC | PPC_OPCODE_ANY | PPC_OPCODE_PPC
1837 #define POWER PPC_OPCODE_POWER | PPC_OPCODE_ANY
1838 #define POWER2 PPC_OPCODE_POWER | PPC_OPCODE_POWER2 | PPC_OPCODE_ANY
1839 #define PPCPWR2 PPC_OPCODE_PPC | PPC_OPCODE_POWER | PPC_OPCODE_POWER2 | PPC_OPCODE_ANY
1840 #define POWER32 PPC_OPCODE_POWER | PPC_OPCODE_ANY | PPC_OPCODE_32
1841 #define COM PPC_OPCODE_POWER | PPC_OPCODE_PPC | PPC_OPCODE_COMMON | PPC_OPCODE_ANY
1842 #define COM32 PPC_OPCODE_POWER | PPC_OPCODE_PPC | PPC_OPCODE_COMMON | PPC_OPCODE_ANY | PPC_OPCODE_32
1843 #define M601 PPC_OPCODE_POWER | PPC_OPCODE_601 | PPC_OPCODE_ANY
1844 #define PWRCOM PPC_OPCODE_POWER | PPC_OPCODE_601 | PPC_OPCODE_COMMON | PPC_OPCODE_ANY
1845 #define MFDEC1 PPC_OPCODE_POWER
1846 #define MFDEC2 PPC_OPCODE_PPC | PPC_OPCODE_601 | PPC_OPCODE_BOOKE
1847 #define BOOKE PPC_OPCODE_BOOKE
1848 #define BOOKE64 PPC_OPCODE_BOOKE64
1849 #define CLASSIC PPC_OPCODE_CLASSIC
1850 #define PPCSPE PPC_OPCODE_SPE
1851 #define PPCISEL PPC_OPCODE_ISEL
1852 #define PPCEFS PPC_OPCODE_EFS
1853 #define PPCBRLK PPC_OPCODE_BRLOCK
1854 #define PPCPMR PPC_OPCODE_PMR
1855 #define PPCCHLK PPC_OPCODE_CACHELCK
1856 #define PPCCHLK64 PPC_OPCODE_CACHELCK | PPC_OPCODE_BOOKE64
1857 #define PPCRFMCI PPC_OPCODE_RFMCI
1859 /* The opcode table.
1861 The format of the opcode table is:
1863 NAME OPCODE MASK FLAGS { OPERANDS }
1865 NAME is the name of the instruction.
1866 OPCODE is the instruction opcode.
1867 MASK is the opcode mask; this is used to tell the disassembler
1868 which bits in the actual opcode must match OPCODE.
1869 FLAGS are flags indicated what processors support the instruction.
1870 OPERANDS is the list of operands.
1872 The disassembler reads the table in order and prints the first
1873 instruction which matches, so this table is sorted to put more
1874 specific instructions before more general instructions. It is also
1875 sorted by major opcode. */
1877 const struct powerpc_opcode powerpc_opcodes[] = {
1878 { "attn", X(0,256), X_MASK, POWER4, { 0 } },
1879 { "tdlgti", OPTO(2,TOLGT), OPTO_MASK, PPC64, { RA, SI } },
1880 { "tdllti", OPTO(2,TOLLT), OPTO_MASK, PPC64, { RA, SI } },
1881 { "tdeqi", OPTO(2,TOEQ), OPTO_MASK, PPC64, { RA, SI } },
1882 { "tdlgei", OPTO(2,TOLGE), OPTO_MASK, PPC64, { RA, SI } },
1883 { "tdlnli", OPTO(2,TOLNL), OPTO_MASK, PPC64, { RA, SI } },
1884 { "tdllei", OPTO(2,TOLLE), OPTO_MASK, PPC64, { RA, SI } },
1885 { "tdlngi", OPTO(2,TOLNG), OPTO_MASK, PPC64, { RA, SI } },
1886 { "tdgti", OPTO(2,TOGT), OPTO_MASK, PPC64, { RA, SI } },
1887 { "tdgei", OPTO(2,TOGE), OPTO_MASK, PPC64, { RA, SI } },
1888 { "tdnli", OPTO(2,TONL), OPTO_MASK, PPC64, { RA, SI } },
1889 { "tdlti", OPTO(2,TOLT), OPTO_MASK, PPC64, { RA, SI } },
1890 { "tdlei", OPTO(2,TOLE), OPTO_MASK, PPC64, { RA, SI } },
1891 { "tdngi", OPTO(2,TONG), OPTO_MASK, PPC64, { RA, SI } },
1892 { "tdnei", OPTO(2,TONE), OPTO_MASK, PPC64, { RA, SI } },
1893 { "tdi", OP(2), OP_MASK, PPC64, { TO, RA, SI } },
1895 { "twlgti", OPTO(3,TOLGT), OPTO_MASK, PPCCOM, { RA, SI } },
1896 { "tlgti", OPTO(3,TOLGT), OPTO_MASK, PWRCOM, { RA, SI } },
1897 { "twllti", OPTO(3,TOLLT), OPTO_MASK, PPCCOM, { RA, SI } },
1898 { "tllti", OPTO(3,TOLLT), OPTO_MASK, PWRCOM, { RA, SI } },
1899 { "tweqi", OPTO(3,TOEQ), OPTO_MASK, PPCCOM, { RA, SI } },
1900 { "teqi", OPTO(3,TOEQ), OPTO_MASK, PWRCOM, { RA, SI } },
1901 { "twlgei", OPTO(3,TOLGE), OPTO_MASK, PPCCOM, { RA, SI } },
1902 { "tlgei", OPTO(3,TOLGE), OPTO_MASK, PWRCOM, { RA, SI } },
1903 { "twlnli", OPTO(3,TOLNL), OPTO_MASK, PPCCOM, { RA, SI } },
1904 { "tlnli", OPTO(3,TOLNL), OPTO_MASK, PWRCOM, { RA, SI } },
1905 { "twllei", OPTO(3,TOLLE), OPTO_MASK, PPCCOM, { RA, SI } },
1906 { "tllei", OPTO(3,TOLLE), OPTO_MASK, PWRCOM, { RA, SI } },
1907 { "twlngi", OPTO(3,TOLNG), OPTO_MASK, PPCCOM, { RA, SI } },
1908 { "tlngi", OPTO(3,TOLNG), OPTO_MASK, PWRCOM, { RA, SI } },
1909 { "twgti", OPTO(3,TOGT), OPTO_MASK, PPCCOM, { RA, SI } },
1910 { "tgti", OPTO(3,TOGT), OPTO_MASK, PWRCOM, { RA, SI } },
1911 { "twgei", OPTO(3,TOGE), OPTO_MASK, PPCCOM, { RA, SI } },
1912 { "tgei", OPTO(3,TOGE), OPTO_MASK, PWRCOM, { RA, SI } },
1913 { "twnli", OPTO(3,TONL), OPTO_MASK, PPCCOM, { RA, SI } },
1914 { "tnli", OPTO(3,TONL), OPTO_MASK, PWRCOM, { RA, SI } },
1915 { "twlti", OPTO(3,TOLT), OPTO_MASK, PPCCOM, { RA, SI } },
1916 { "tlti", OPTO(3,TOLT), OPTO_MASK, PWRCOM, { RA, SI } },
1917 { "twlei", OPTO(3,TOLE), OPTO_MASK, PPCCOM, { RA, SI } },
1918 { "tlei", OPTO(3,TOLE), OPTO_MASK, PWRCOM, { RA, SI } },
1919 { "twngi", OPTO(3,TONG), OPTO_MASK, PPCCOM, { RA, SI } },
1920 { "tngi", OPTO(3,TONG), OPTO_MASK, PWRCOM, { RA, SI } },
1921 { "twnei", OPTO(3,TONE), OPTO_MASK, PPCCOM, { RA, SI } },
1922 { "tnei", OPTO(3,TONE), OPTO_MASK, PWRCOM, { RA, SI } },
1923 { "twi", OP(3), OP_MASK, PPCCOM, { TO, RA, SI } },
1924 { "ti", OP(3), OP_MASK, PWRCOM, { TO, RA, SI } },
1926 { "macchw", XO(4,172,0,0), XO_MASK, PPC405, { RT, RA, RB } },
1927 { "macchw.", XO(4,172,0,1), XO_MASK, PPC405, { RT, RA, RB } },
1928 { "macchwo", XO(4,172,1,0), XO_MASK, PPC405, { RT, RA, RB } },
1929 { "macchwo.", XO(4,172,1,1), XO_MASK, PPC405, { RT, RA, RB } },
1930 { "macchws", XO(4,236,0,0), XO_MASK, PPC405, { RT, RA, RB } },
1931 { "macchws.", XO(4,236,0,1), XO_MASK, PPC405, { RT, RA, RB } },
1932 { "macchwso", XO(4,236,1,0), XO_MASK, PPC405, { RT, RA, RB } },
1933 { "macchwso.", XO(4,236,1,1), XO_MASK, PPC405, { RT, RA, RB } },
1934 { "macchwsu", XO(4,204,0,0), XO_MASK, PPC405, { RT, RA, RB } },
1935 { "macchwsu.", XO(4,204,0,1), XO_MASK, PPC405, { RT, RA, RB } },
1936 { "macchwsuo", XO(4,204,1,0), XO_MASK, PPC405, { RT, RA, RB } },
1937 { "macchwsuo.", XO(4,204,1,1), XO_MASK, PPC405, { RT, RA, RB } },
1938 { "macchwu", XO(4,140,0,0), XO_MASK, PPC405, { RT, RA, RB } },
1939 { "macchwu.", XO(4,140,0,1), XO_MASK, PPC405, { RT, RA, RB } },
1940 { "macchwuo", XO(4,140,1,0), XO_MASK, PPC405, { RT, RA, RB } },
1941 { "macchwuo.", XO(4,140,1,1), XO_MASK, PPC405, { RT, RA, RB } },
1942 { "machhw", XO(4,44,0,0), XO_MASK, PPC405, { RT, RA, RB } },
1943 { "machhw.", XO(4,44,0,1), XO_MASK, PPC405, { RT, RA, RB } },
1944 { "machhwo", XO(4,44,1,0), XO_MASK, PPC405, { RT, RA, RB } },
1945 { "machhwo.", XO(4,44,1,1), XO_MASK, PPC405, { RT, RA, RB } },
1946 { "machhws", XO(4,108,0,0), XO_MASK, PPC405, { RT, RA, RB } },
1947 { "machhws.", XO(4,108,0,1), XO_MASK, PPC405, { RT, RA, RB } },
1948 { "machhwso", XO(4,108,1,0), XO_MASK, PPC405, { RT, RA, RB } },
1949 { "machhwso.", XO(4,108,1,1), XO_MASK, PPC405, { RT, RA, RB } },
1950 { "machhwsu", XO(4,76,0,0), XO_MASK, PPC405, { RT, RA, RB } },
1951 { "machhwsu.", XO(4,76,0,1), XO_MASK, PPC405, { RT, RA, RB } },
1952 { "machhwsuo", XO(4,76,1,0), XO_MASK, PPC405, { RT, RA, RB } },
1953 { "machhwsuo.", XO(4,76,1,1), XO_MASK, PPC405, { RT, RA, RB } },
1954 { "machhwu", XO(4,12,0,0), XO_MASK, PPC405, { RT, RA, RB } },
1955 { "machhwu.", XO(4,12,0,1), XO_MASK, PPC405, { RT, RA, RB } },
1956 { "machhwuo", XO(4,12,1,0), XO_MASK, PPC405, { RT, RA, RB } },
1957 { "machhwuo.", XO(4,12,1,1), XO_MASK, PPC405, { RT, RA, RB } },
1958 { "maclhw", XO(4,428,0,0), XO_MASK, PPC405, { RT, RA, RB } },
1959 { "maclhw.", XO(4,428,0,1), XO_MASK, PPC405, { RT, RA, RB } },
1960 { "maclhwo", XO(4,428,1,0), XO_MASK, PPC405, { RT, RA, RB } },
1961 { "maclhwo.", XO(4,428,1,1), XO_MASK, PPC405, { RT, RA, RB } },
1962 { "maclhws", XO(4,492,0,0), XO_MASK, PPC405, { RT, RA, RB } },
1963 { "maclhws.", XO(4,492,0,1), XO_MASK, PPC405, { RT, RA, RB } },
1964 { "maclhwso", XO(4,492,1,0), XO_MASK, PPC405, { RT, RA, RB } },
1965 { "maclhwso.", XO(4,492,1,1), XO_MASK, PPC405, { RT, RA, RB } },
1966 { "maclhwsu", XO(4,460,0,0), XO_MASK, PPC405, { RT, RA, RB } },
1967 { "maclhwsu.", XO(4,460,0,1), XO_MASK, PPC405, { RT, RA, RB } },
1968 { "maclhwsuo", XO(4,460,1,0), XO_MASK, PPC405, { RT, RA, RB } },
1969 { "maclhwsuo.", XO(4,460,1,1), XO_MASK, PPC405, { RT, RA, RB } },
1970 { "maclhwu", XO(4,396,0,0), XO_MASK, PPC405, { RT, RA, RB } },
1971 { "maclhwu.", XO(4,396,0,1), XO_MASK, PPC405, { RT, RA, RB } },
1972 { "maclhwuo", XO(4,396,1,0), XO_MASK, PPC405, { RT, RA, RB } },
1973 { "maclhwuo.", XO(4,396,1,1), XO_MASK, PPC405, { RT, RA, RB } },
1974 { "mulchw", XRC(4,168,0), X_MASK, PPC405, { RT, RA, RB } },
1975 { "mulchw.", XRC(4,168,1), X_MASK, PPC405, { RT, RA, RB } },
1976 { "mulchwu", XRC(4,136,0), X_MASK, PPC405, { RT, RA, RB } },
1977 { "mulchwu.", XRC(4,136,1), X_MASK, PPC405, { RT, RA, RB } },
1978 { "mulhhw", XRC(4,40,0), X_MASK, PPC405, { RT, RA, RB } },
1979 { "mulhhw.", XRC(4,40,1), X_MASK, PPC405, { RT, RA, RB } },
1980 { "mulhhwu", XRC(4,8,0), X_MASK, PPC405, { RT, RA, RB } },
1981 { "mulhhwu.", XRC(4,8,1), X_MASK, PPC405, { RT, RA, RB } },
1982 { "mullhw", XRC(4,424,0), X_MASK, PPC405, { RT, RA, RB } },
1983 { "mullhw.", XRC(4,424,1), X_MASK, PPC405, { RT, RA, RB } },
1984 { "mullhwu", XRC(4,392,0), X_MASK, PPC405, { RT, RA, RB } },
1985 { "mullhwu.", XRC(4,392,1), X_MASK, PPC405, { RT, RA, RB } },
1986 { "nmacchw", XO(4,174,0,0), XO_MASK, PPC405, { RT, RA, RB } },
1987 { "nmacchw.", XO(4,174,0,1), XO_MASK, PPC405, { RT, RA, RB } },
1988 { "nmacchwo", XO(4,174,1,0), XO_MASK, PPC405, { RT, RA, RB } },
1989 { "nmacchwo.", XO(4,174,1,1), XO_MASK, PPC405, { RT, RA, RB } },
1990 { "nmacchws", XO(4,238,0,0), XO_MASK, PPC405, { RT, RA, RB } },
1991 { "nmacchws.", XO(4,238,0,1), XO_MASK, PPC405, { RT, RA, RB } },
1992 { "nmacchwso", XO(4,238,1,0), XO_MASK, PPC405, { RT, RA, RB } },
1993 { "nmacchwso.", XO(4,238,1,1), XO_MASK, PPC405, { RT, RA, RB } },
1994 { "nmachhw", XO(4,46,0,0), XO_MASK, PPC405, { RT, RA, RB } },
1995 { "nmachhw.", XO(4,46,0,1), XO_MASK, PPC405, { RT, RA, RB } },
1996 { "nmachhwo", XO(4,46,1,0), XO_MASK, PPC405, { RT, RA, RB } },
1997 { "nmachhwo.", XO(4,46,1,1), XO_MASK, PPC405, { RT, RA, RB } },
1998 { "nmachhws", XO(4,110,0,0), XO_MASK, PPC405, { RT, RA, RB } },
1999 { "nmachhws.", XO(4,110,0,1), XO_MASK, PPC405, { RT, RA, RB } },
2000 { "nmachhwso", XO(4,110,1,0), XO_MASK, PPC405, { RT, RA, RB } },
2001 { "nmachhwso.", XO(4,110,1,1), XO_MASK, PPC405, { RT, RA, RB } },
2002 { "nmaclhw", XO(4,430,0,0), XO_MASK, PPC405, { RT, RA, RB } },
2003 { "nmaclhw.", XO(4,430,0,1), XO_MASK, PPC405, { RT, RA, RB } },
2004 { "nmaclhwo", XO(4,430,1,0), XO_MASK, PPC405, { RT, RA, RB } },
2005 { "nmaclhwo.", XO(4,430,1,1), XO_MASK, PPC405, { RT, RA, RB } },
2006 { "nmaclhws", XO(4,494,0,0), XO_MASK, PPC405, { RT, RA, RB } },
2007 { "nmaclhws.", XO(4,494,0,1), XO_MASK, PPC405, { RT, RA, RB } },
2008 { "nmaclhwso", XO(4,494,1,0), XO_MASK, PPC405, { RT, RA, RB } },
2009 { "nmaclhwso.", XO(4,494,1,1), XO_MASK, PPC405, { RT, RA, RB } },
2010 { "mfvscr", VX(4, 1540), VX_MASK, PPCVEC, { VD } },
2011 { "mtvscr", VX(4, 1604), VX_MASK, PPCVEC, { VB } },
2012 { "vaddcuw", VX(4, 384), VX_MASK, PPCVEC, { VD, VA, VB } },
2013 { "vaddfp", VX(4, 10), VX_MASK, PPCVEC, { VD, VA, VB } },
2014 { "vaddsbs", VX(4, 768), VX_MASK, PPCVEC, { VD, VA, VB } },
2015 { "vaddshs", VX(4, 832), VX_MASK, PPCVEC, { VD, VA, VB } },
2016 { "vaddsws", VX(4, 896), VX_MASK, PPCVEC, { VD, VA, VB } },
2017 { "vaddubm", VX(4, 0), VX_MASK, PPCVEC, { VD, VA, VB } },
2018 { "vaddubs", VX(4, 512), VX_MASK, PPCVEC, { VD, VA, VB } },
2019 { "vadduhm", VX(4, 64), VX_MASK, PPCVEC, { VD, VA, VB } },
2020 { "vadduhs", VX(4, 576), VX_MASK, PPCVEC, { VD, VA, VB } },
2021 { "vadduwm", VX(4, 128), VX_MASK, PPCVEC, { VD, VA, VB } },
2022 { "vadduws", VX(4, 640), VX_MASK, PPCVEC, { VD, VA, VB } },
2023 { "vand", VX(4, 1028), VX_MASK, PPCVEC, { VD, VA, VB } },
2024 { "vandc", VX(4, 1092), VX_MASK, PPCVEC, { VD, VA, VB } },
2025 { "vavgsb", VX(4, 1282), VX_MASK, PPCVEC, { VD, VA, VB } },
2026 { "vavgsh", VX(4, 1346), VX_MASK, PPCVEC, { VD, VA, VB } },
2027 { "vavgsw", VX(4, 1410), VX_MASK, PPCVEC, { VD, VA, VB } },
2028 { "vavgub", VX(4, 1026), VX_MASK, PPCVEC, { VD, VA, VB } },
2029 { "vavguh", VX(4, 1090), VX_MASK, PPCVEC, { VD, VA, VB } },
2030 { "vavguw", VX(4, 1154), VX_MASK, PPCVEC, { VD, VA, VB } },
2031 { "vcfsx", VX(4, 842), VX_MASK, PPCVEC, { VD, VB, UIMM } },
2032 { "vcfux", VX(4, 778), VX_MASK, PPCVEC, { VD, VB, UIMM } },
2033 { "vcmpbfp", VXR(4, 966, 0), VXR_MASK, PPCVEC, { VD, VA, VB } },
2034 { "vcmpbfp.", VXR(4, 966, 1), VXR_MASK, PPCVEC, { VD, VA, VB } },
2035 { "vcmpeqfp", VXR(4, 198, 0), VXR_MASK, PPCVEC, { VD, VA, VB } },
2036 { "vcmpeqfp.", VXR(4, 198, 1), VXR_MASK, PPCVEC, { VD, VA, VB } },
2037 { "vcmpequb", VXR(4, 6, 0), VXR_MASK, PPCVEC, { VD, VA, VB } },
2038 { "vcmpequb.", VXR(4, 6, 1), VXR_MASK, PPCVEC, { VD, VA, VB } },
2039 { "vcmpequh", VXR(4, 70, 0), VXR_MASK, PPCVEC, { VD, VA, VB } },
2040 { "vcmpequh.", VXR(4, 70, 1), VXR_MASK, PPCVEC, { VD, VA, VB } },
2041 { "vcmpequw", VXR(4, 134, 0), VXR_MASK, PPCVEC, { VD, VA, VB } },
2042 { "vcmpequw.", VXR(4, 134, 1), VXR_MASK, PPCVEC, { VD, VA, VB } },
2043 { "vcmpgefp", VXR(4, 454, 0), VXR_MASK, PPCVEC, { VD, VA, VB } },
2044 { "vcmpgefp.", VXR(4, 454, 1), VXR_MASK, PPCVEC, { VD, VA, VB } },
2045 { "vcmpgtfp", VXR(4, 710, 0), VXR_MASK, PPCVEC, { VD, VA, VB } },
2046 { "vcmpgtfp.", VXR(4, 710, 1), VXR_MASK, PPCVEC, { VD, VA, VB } },
2047 { "vcmpgtsb", VXR(4, 774, 0), VXR_MASK, PPCVEC, { VD, VA, VB } },
2048 { "vcmpgtsb.", VXR(4, 774, 1), VXR_MASK, PPCVEC, { VD, VA, VB } },
2049 { "vcmpgtsh", VXR(4, 838, 0), VXR_MASK, PPCVEC, { VD, VA, VB } },
2050 { "vcmpgtsh.", VXR(4, 838, 1), VXR_MASK, PPCVEC, { VD, VA, VB } },
2051 { "vcmpgtsw", VXR(4, 902, 0), VXR_MASK, PPCVEC, { VD, VA, VB } },
2052 { "vcmpgtsw.", VXR(4, 902, 1), VXR_MASK, PPCVEC, { VD, VA, VB } },
2053 { "vcmpgtub", VXR(4, 518, 0), VXR_MASK, PPCVEC, { VD, VA, VB } },
2054 { "vcmpgtub.", VXR(4, 518, 1), VXR_MASK, PPCVEC, { VD, VA, VB } },
2055 { "vcmpgtuh", VXR(4, 582, 0), VXR_MASK, PPCVEC, { VD, VA, VB } },
2056 { "vcmpgtuh.", VXR(4, 582, 1), VXR_MASK, PPCVEC, { VD, VA, VB } },
2057 { "vcmpgtuw", VXR(4, 646, 0), VXR_MASK, PPCVEC, { VD, VA, VB } },
2058 { "vcmpgtuw.", VXR(4, 646, 1), VXR_MASK, PPCVEC, { VD, VA, VB } },
2059 { "vctsxs", VX(4, 970), VX_MASK, PPCVEC, { VD, VB, UIMM } },
2060 { "vctuxs", VX(4, 906), VX_MASK, PPCVEC, { VD, VB, UIMM } },
2061 { "vexptefp", VX(4, 394), VX_MASK, PPCVEC, { VD, VB } },
2062 { "vlogefp", VX(4, 458), VX_MASK, PPCVEC, { VD, VB } },
2063 { "vmaddfp", VXA(4, 46), VXA_MASK, PPCVEC, { VD, VA, VC, VB } },
2064 { "vmaxfp", VX(4, 1034), VX_MASK, PPCVEC, { VD, VA, VB } },
2065 { "vmaxsb", VX(4, 258), VX_MASK, PPCVEC, { VD, VA, VB } },
2066 { "vmaxsh", VX(4, 322), VX_MASK, PPCVEC, { VD, VA, VB } },
2067 { "vmaxsw", VX(4, 386), VX_MASK, PPCVEC, { VD, VA, VB } },
2068 { "vmaxub", VX(4, 2), VX_MASK, PPCVEC, { VD, VA, VB } },
2069 { "vmaxuh", VX(4, 66), VX_MASK, PPCVEC, { VD, VA, VB } },
2070 { "vmaxuw", VX(4, 130), VX_MASK, PPCVEC, { VD, VA, VB } },
2071 { "vmhaddshs", VXA(4, 32), VXA_MASK, PPCVEC, { VD, VA, VB, VC } },
2072 { "vmhraddshs", VXA(4, 33), VXA_MASK, PPCVEC, { VD, VA, VB, VC } },
2073 { "vminfp", VX(4, 1098), VX_MASK, PPCVEC, { VD, VA, VB } },
2074 { "vminsb", VX(4, 770), VX_MASK, PPCVEC, { VD, VA, VB } },
2075 { "vminsh", VX(4, 834), VX_MASK, PPCVEC, { VD, VA, VB } },
2076 { "vminsw", VX(4, 898), VX_MASK, PPCVEC, { VD, VA, VB } },
2077 { "vminub", VX(4, 514), VX_MASK, PPCVEC, { VD, VA, VB } },
2078 { "vminuh", VX(4, 578), VX_MASK, PPCVEC, { VD, VA, VB } },
2079 { "vminuw", VX(4, 642), VX_MASK, PPCVEC, { VD, VA, VB } },
2080 { "vmladduhm", VXA(4, 34), VXA_MASK, PPCVEC, { VD, VA, VB, VC } },
2081 { "vmrghb", VX(4, 12), VX_MASK, PPCVEC, { VD, VA, VB } },
2082 { "vmrghh", VX(4, 76), VX_MASK, PPCVEC, { VD, VA, VB } },
2083 { "vmrghw", VX(4, 140), VX_MASK, PPCVEC, { VD, VA, VB } },
2084 { "vmrglb", VX(4, 268), VX_MASK, PPCVEC, { VD, VA, VB } },
2085 { "vmrglh", VX(4, 332), VX_MASK, PPCVEC, { VD, VA, VB } },
2086 { "vmrglw", VX(4, 396), VX_MASK, PPCVEC, { VD, VA, VB } },
2087 { "vmsummbm", VXA(4, 37), VXA_MASK, PPCVEC, { VD, VA, VB, VC } },
2088 { "vmsumshm", VXA(4, 40), VXA_MASK, PPCVEC, { VD, VA, VB, VC } },
2089 { "vmsumshs", VXA(4, 41), VXA_MASK, PPCVEC, { VD, VA, VB, VC } },
2090 { "vmsumubm", VXA(4, 36), VXA_MASK, PPCVEC, { VD, VA, VB, VC } },
2091 { "vmsumuhm", VXA(4, 38), VXA_MASK, PPCVEC, { VD, VA, VB, VC } },
2092 { "vmsumuhs", VXA(4, 39), VXA_MASK, PPCVEC, { VD, VA, VB, VC } },
2093 { "vmulesb", VX(4, 776), VX_MASK, PPCVEC, { VD, VA, VB } },
2094 { "vmulesh", VX(4, 840), VX_MASK, PPCVEC, { VD, VA, VB } },
2095 { "vmuleub", VX(4, 520), VX_MASK, PPCVEC, { VD, VA, VB } },
2096 { "vmuleuh", VX(4, 584), VX_MASK, PPCVEC, { VD, VA, VB } },
2097 { "vmulosb", VX(4, 264), VX_MASK, PPCVEC, { VD, VA, VB } },
2098 { "vmulosh", VX(4, 328), VX_MASK, PPCVEC, { VD, VA, VB } },
2099 { "vmuloub", VX(4, 8), VX_MASK, PPCVEC, { VD, VA, VB } },
2100 { "vmulouh", VX(4, 72), VX_MASK, PPCVEC, { VD, VA, VB } },
2101 { "vnmsubfp", VXA(4, 47), VXA_MASK, PPCVEC, { VD, VA, VC, VB } },
2102 { "vnor", VX(4, 1284), VX_MASK, PPCVEC, { VD, VA, VB } },
2103 { "vor", VX(4, 1156), VX_MASK, PPCVEC, { VD, VA, VB } },
2104 { "vperm", VXA(4, 43), VXA_MASK, PPCVEC, { VD, VA, VB, VC } },
2105 { "vpkpx", VX(4, 782), VX_MASK, PPCVEC, { VD, VA, VB } },
2106 { "vpkshss", VX(4, 398), VX_MASK, PPCVEC, { VD, VA, VB } },
2107 { "vpkshus", VX(4, 270), VX_MASK, PPCVEC, { VD, VA, VB } },
2108 { "vpkswss", VX(4, 462), VX_MASK, PPCVEC, { VD, VA, VB } },
2109 { "vpkswus", VX(4, 334), VX_MASK, PPCVEC, { VD, VA, VB } },
2110 { "vpkuhum", VX(4, 14), VX_MASK, PPCVEC, { VD, VA, VB } },
2111 { "vpkuhus", VX(4, 142), VX_MASK, PPCVEC, { VD, VA, VB } },
2112 { "vpkuwum", VX(4, 78), VX_MASK, PPCVEC, { VD, VA, VB } },
2113 { "vpkuwus", VX(4, 206), VX_MASK, PPCVEC, { VD, VA, VB } },
2114 { "vrefp", VX(4, 266), VX_MASK, PPCVEC, { VD, VB } },
2115 { "vrfim", VX(4, 714), VX_MASK, PPCVEC, { VD, VB } },
2116 { "vrfin", VX(4, 522), VX_MASK, PPCVEC, { VD, VB } },
2117 { "vrfip", VX(4, 650), VX_MASK, PPCVEC, { VD, VB } },
2118 { "vrfiz", VX(4, 586), VX_MASK, PPCVEC, { VD, VB } },
2119 { "vrlb", VX(4, 4), VX_MASK, PPCVEC, { VD, VA, VB } },
2120 { "vrlh", VX(4, 68), VX_MASK, PPCVEC, { VD, VA, VB } },
2121 { "vrlw", VX(4, 132), VX_MASK, PPCVEC, { VD, VA, VB } },
2122 { "vrsqrtefp", VX(4, 330), VX_MASK, PPCVEC, { VD, VB } },
2123 { "vsel", VXA(4, 42), VXA_MASK, PPCVEC, { VD, VA, VB, VC } },
2124 { "vsl", VX(4, 452), VX_MASK, PPCVEC, { VD, VA, VB } },
2125 { "vslb", VX(4, 260), VX_MASK, PPCVEC, { VD, VA, VB } },
2126 { "vsldoi", VXA(4, 44), VXA_MASK, PPCVEC, { VD, VA, VB, SHB } },
2127 { "vslh", VX(4, 324), VX_MASK, PPCVEC, { VD, VA, VB } },
2128 { "vslo", VX(4, 1036), VX_MASK, PPCVEC, { VD, VA, VB } },
2129 { "vslw", VX(4, 388), VX_MASK, PPCVEC, { VD, VA, VB } },
2130 { "vspltb", VX(4, 524), VX_MASK, PPCVEC, { VD, VB, UIMM } },
2131 { "vsplth", VX(4, 588), VX_MASK, PPCVEC, { VD, VB, UIMM } },
2132 { "vspltisb", VX(4, 780), VX_MASK, PPCVEC, { VD, SIMM } },
2133 { "vspltish", VX(4, 844), VX_MASK, PPCVEC, { VD, SIMM } },
2134 { "vspltisw", VX(4, 908), VX_MASK, PPCVEC, { VD, SIMM } },
2135 { "vspltw", VX(4, 652), VX_MASK, PPCVEC, { VD, VB, UIMM } },
2136 { "vsr", VX(4, 708), VX_MASK, PPCVEC, { VD, VA, VB } },
2137 { "vsrab", VX(4, 772), VX_MASK, PPCVEC, { VD, VA, VB } },
2138 { "vsrah", VX(4, 836), VX_MASK, PPCVEC, { VD, VA, VB } },
2139 { "vsraw", VX(4, 900), VX_MASK, PPCVEC, { VD, VA, VB } },
2140 { "vsrb", VX(4, 516), VX_MASK, PPCVEC, { VD, VA, VB } },
2141 { "vsrh", VX(4, 580), VX_MASK, PPCVEC, { VD, VA, VB } },
2142 { "vsro", VX(4, 1100), VX_MASK, PPCVEC, { VD, VA, VB } },
2143 { "vsrw", VX(4, 644), VX_MASK, PPCVEC, { VD, VA, VB } },
2144 { "vsubcuw", VX(4, 1408), VX_MASK, PPCVEC, { VD, VA, VB } },
2145 { "vsubfp", VX(4, 74), VX_MASK, PPCVEC, { VD, VA, VB } },
2146 { "vsubsbs", VX(4, 1792), VX_MASK, PPCVEC, { VD, VA, VB } },
2147 { "vsubshs", VX(4, 1856), VX_MASK, PPCVEC, { VD, VA, VB } },
2148 { "vsubsws", VX(4, 1920), VX_MASK, PPCVEC, { VD, VA, VB } },
2149 { "vsububm", VX(4, 1024), VX_MASK, PPCVEC, { VD, VA, VB } },
2150 { "vsububs", VX(4, 1536), VX_MASK, PPCVEC, { VD, VA, VB } },
2151 { "vsubuhm", VX(4, 1088), VX_MASK, PPCVEC, { VD, VA, VB } },
2152 { "vsubuhs", VX(4, 1600), VX_MASK, PPCVEC, { VD, VA, VB } },
2153 { "vsubuwm", VX(4, 1152), VX_MASK, PPCVEC, { VD, VA, VB } },
2154 { "vsubuws", VX(4, 1664), VX_MASK, PPCVEC, { VD, VA, VB } },
2155 { "vsumsws", VX(4, 1928), VX_MASK, PPCVEC, { VD, VA, VB } },
2156 { "vsum2sws", VX(4, 1672), VX_MASK, PPCVEC, { VD, VA, VB } },
2157 { "vsum4sbs", VX(4, 1800), VX_MASK, PPCVEC, { VD, VA, VB } },
2158 { "vsum4shs", VX(4, 1608), VX_MASK, PPCVEC, { VD, VA, VB } },
2159 { "vsum4ubs", VX(4, 1544), VX_MASK, PPCVEC, { VD, VA, VB } },
2160 { "vupkhpx", VX(4, 846), VX_MASK, PPCVEC, { VD, VB } },
2161 { "vupkhsb", VX(4, 526), VX_MASK, PPCVEC, { VD, VB } },
2162 { "vupkhsh", VX(4, 590), VX_MASK, PPCVEC, { VD, VB } },
2163 { "vupklpx", VX(4, 974), VX_MASK, PPCVEC, { VD, VB } },
2164 { "vupklsb", VX(4, 654), VX_MASK, PPCVEC, { VD, VB } },
2165 { "vupklsh", VX(4, 718), VX_MASK, PPCVEC, { VD, VB } },
2166 { "vxor", VX(4, 1220), VX_MASK, PPCVEC, { VD, VA, VB } },
2168 { "evaddw", VX(4, 512), VX_MASK, PPCSPE, { RS, RA, RB } },
2169 { "evaddiw", VX(4, 514), VX_MASK, PPCSPE, { RS, RB, UIMM } },
2170 { "evsubfw", VX(4, 516), VX_MASK, PPCSPE, { RS, RA, RB } },
2171 { "evsubw", VX(4, 516), VX_MASK, PPCSPE, { RS, RB, RA } },
2172 { "evsubifw", VX(4, 518), VX_MASK, PPCSPE, { RS, UIMM, RB } },
2173 { "evsubiw", VX(4, 518), VX_MASK, PPCSPE, { RS, RB, UIMM } },
2174 { "evabs", VX(4, 520), VX_MASK, PPCSPE, { RS, RA } },
2175 { "evneg", VX(4, 521), VX_MASK, PPCSPE, { RS, RA } },
2176 { "evextsb", VX(4, 522), VX_MASK, PPCSPE, { RS, RA } },
2177 { "evextsh", VX(4, 523), VX_MASK, PPCSPE, { RS, RA } },
2178 { "evrndw", VX(4, 524), VX_MASK, PPCSPE, { RS, RA } },
2179 { "evcntlzw", VX(4, 525), VX_MASK, PPCSPE, { RS, RA } },
2180 { "evcntlsw", VX(4, 526), VX_MASK, PPCSPE, { RS, RA } },
2182 { "brinc", VX(4, 527), VX_MASK, PPCSPE, { RS, RA, RB } },
2184 { "evand", VX(4, 529), VX_MASK, PPCSPE, { RS, RA, RB } },
2185 { "evandc", VX(4, 530), VX_MASK, PPCSPE, { RS, RA, RB } },
2186 { "evmr", VX(4, 535), VX_MASK, PPCSPE, { RS, RA, BBA } },
2187 { "evor", VX(4, 535), VX_MASK, PPCSPE, { RS, RA, RB } },
2188 { "evorc", VX(4, 539), VX_MASK, PPCSPE, { RS, RA, RB } },
2189 { "evxor", VX(4, 534), VX_MASK, PPCSPE, { RS, RA, RB } },
2190 { "eveqv", VX(4, 537), VX_MASK, PPCSPE, { RS, RA, RB } },
2191 { "evnand", VX(4, 542), VX_MASK, PPCSPE, { RS, RA, RB } },
2192 { "evnot", VX(4, 536), VX_MASK, PPCSPE, { RS, RA, BBA } },
2193 { "evnor", VX(4, 536), VX_MASK, PPCSPE, { RS, RA, RB } },
2195 { "evrlw", VX(4, 552), VX_MASK, PPCSPE, { RS, RA, RB } },
2196 { "evrlwi", VX(4, 554), VX_MASK, PPCSPE, { RS, RA, EVUIMM } },
2197 { "evslw", VX(4, 548), VX_MASK, PPCSPE, { RS, RA, RB } },
2198 { "evslwi", VX(4, 550), VX_MASK, PPCSPE, { RS, RA, EVUIMM } },
2199 { "evsrws", VX(4, 545), VX_MASK, PPCSPE, { RS, RA, RB } },
2200 { "evsrwu", VX(4, 544), VX_MASK, PPCSPE, { RS, RA, RB } },
2201 { "evsrwis", VX(4, 547), VX_MASK, PPCSPE, { RS, RA, EVUIMM } },
2202 { "evsrwiu", VX(4, 546), VX_MASK, PPCSPE, { RS, RA, EVUIMM } },
2203 { "evsplati", VX(4, 553), VX_MASK, PPCSPE, { RS, SIMM } },
2204 { "evsplatfi", VX(4, 555), VX_MASK, PPCSPE, { RS, SIMM } },
2205 { "evmergehi", VX(4, 556), VX_MASK, PPCSPE, { RS, RA, RB } },
2206 { "evmergelo", VX(4, 557), VX_MASK, PPCSPE, { RS, RA, RB } },
2207 { "evmergehilo",VX(4,558), VX_MASK, PPCSPE, { RS, RA, RB } },
2208 { "evmergelohi",VX(4,559), VX_MASK, PPCSPE, { RS, RA, RB } },
2210 { "evcmpgts", VX(4, 561), VX_MASK, PPCSPE, { CRFD, RA, RB } },
2211 { "evcmpgtu", VX(4, 560), VX_MASK, PPCSPE, { CRFD, RA, RB } },
2212 { "evcmplts", VX(4, 563), VX_MASK, PPCSPE, { CRFD, RA, RB } },
2213 { "evcmpltu", VX(4, 562), VX_MASK, PPCSPE, { CRFD, RA, RB } },
2214 { "evcmpeq", VX(4, 564), VX_MASK, PPCSPE, { CRFD, RA, RB } },
2215 { "evsel", EVSEL(4,79),EVSEL_MASK, PPCSPE, { RS, RA, RB, CRFS } },
2217 { "evldd", VX(4, 769), VX_MASK, PPCSPE, { RS, EVUIMM_8, RA } },
2218 { "evlddx", VX(4, 768), VX_MASK, PPCSPE, { RS, RA, RB } },
2219 { "evldw", VX(4, 771), VX_MASK, PPCSPE, { RS, EVUIMM_8, RA } },
2220 { "evldwx", VX(4, 770), VX_MASK, PPCSPE, { RS, RA, RB } },
2221 { "evldh", VX(4, 773), VX_MASK, PPCSPE, { RS, EVUIMM_8, RA } },
2222 { "evldhx", VX(4, 772), VX_MASK, PPCSPE, { RS, RA, RB } },
2223 { "evlwhe", VX(4, 785), VX_MASK, PPCSPE, { RS, EVUIMM_4, RA } },
2224 { "evlwhex", VX(4, 784), VX_MASK, PPCSPE, { RS, RA, RB } },
2225 { "evlwhou", VX(4, 789), VX_MASK, PPCSPE, { RS, EVUIMM_4, RA } },
2226 { "evlwhoux", VX(4, 788), VX_MASK, PPCSPE, { RS, RA, RB } },
2227 { "evlwhos", VX(4, 791), VX_MASK, PPCSPE, { RS, EVUIMM_4, RA } },
2228 { "evlwhosx", VX(4, 790), VX_MASK, PPCSPE, { RS, RA, RB } },
2229 { "evlwwsplat",VX(4, 793), VX_MASK, PPCSPE, { RS, EVUIMM_4, RA } },
2230 { "evlwwsplatx",VX(4, 792), VX_MASK, PPCSPE, { RS, RA, RB } },
2231 { "evlwhsplat",VX(4, 797), VX_MASK, PPCSPE, { RS, EVUIMM_4, RA } },
2232 { "evlwhsplatx",VX(4, 796), VX_MASK, PPCSPE, { RS, RA, RB } },
2233 { "evlhhesplat",VX(4, 777), VX_MASK, PPCSPE, { RS, EVUIMM_2, RA } },
2234 { "evlhhesplatx",VX(4, 776), VX_MASK, PPCSPE, { RS, RA, RB } },
2235 { "evlhhousplat",VX(4, 781), VX_MASK, PPCSPE, { RS, EVUIMM_2, RA } },
2236 { "evlhhousplatx",VX(4, 780), VX_MASK, PPCSPE, { RS, RA, RB } },
2237 { "evlhhossplat",VX(4, 783), VX_MASK, PPCSPE, { RS, EVUIMM_2, RA } },
2238 { "evlhhossplatx",VX(4, 782), VX_MASK, PPCSPE, { RS, RA, RB } },
2240 { "evstdd", VX(4, 801), VX_MASK, PPCSPE, { RS, EVUIMM_8, RA } },
2241 { "evstddx", VX(4, 800), VX_MASK, PPCSPE, { RS, RA, RB } },
2242 { "evstdw", VX(4, 803), VX_MASK, PPCSPE, { RS, EVUIMM_8, RA } },
2243 { "evstdwx", VX(4, 802), VX_MASK, PPCSPE, { RS, RA, RB } },
2244 { "evstdh", VX(4, 805), VX_MASK, PPCSPE, { RS, EVUIMM_8, RA } },
2245 { "evstdhx", VX(4, 804), VX_MASK, PPCSPE, { RS, RA, RB } },
2246 { "evstwwe", VX(4, 825), VX_MASK, PPCSPE, { RS, EVUIMM_4, RA } },
2247 { "evstwwex", VX(4, 824), VX_MASK, PPCSPE, { RS, RA, RB } },
2248 { "evstwwo", VX(4, 829), VX_MASK, PPCSPE, { RS, EVUIMM_4, RA } },
2249 { "evstwwox", VX(4, 828), VX_MASK, PPCSPE, { RS, RA, RB } },
2250 { "evstwhe", VX(4, 817), VX_MASK, PPCSPE, { RS, EVUIMM_4, RA } },
2251 { "evstwhex", VX(4, 816), VX_MASK, PPCSPE, { RS, RA, RB } },
2252 { "evstwho", VX(4, 821), VX_MASK, PPCSPE, { RS, EVUIMM_4, RA } },
2253 { "evstwhox", VX(4, 820), VX_MASK, PPCSPE, { RS, RA, RB } },
2255 { "evfsabs", VX(4, 644), VX_MASK, PPCSPE, { RS, RA } },
2256 { "evfsnabs", VX(4, 645), VX_MASK, PPCSPE, { RS, RA } },
2257 { "evfsneg", VX(4, 646), VX_MASK, PPCSPE, { RS, RA } },
2258 { "evfsadd", VX(4, 640), VX_MASK, PPCSPE, { RS, RA, RB } },
2259 { "evfssub", VX(4, 641), VX_MASK, PPCSPE, { RS, RA, RB } },
2260 { "evfsmul", VX(4, 648), VX_MASK, PPCSPE, { RS, RA, RB } },
2261 { "evfsdiv", VX(4, 649), VX_MASK, PPCSPE, { RS, RA, RB } },
2262 { "evfscmpgt", VX(4, 652), VX_MASK, PPCSPE, { CRFD, RA, RB } },
2263 { "evfscmplt", VX(4, 653), VX_MASK, PPCSPE, { CRFD, RA, RB } },
2264 { "evfscmpeq", VX(4, 654), VX_MASK, PPCSPE, { CRFD, RA, RB } },
2265 { "evfststgt", VX(4, 668), VX_MASK, PPCSPE, { CRFD, RA, RB } },
2266 { "evfststlt", VX(4, 669), VX_MASK, PPCSPE, { CRFD, RA, RB } },
2267 { "evfststeq", VX(4, 670), VX_MASK, PPCSPE, { CRFD, RA, RB } },
2268 { "evfscfui", VX(4, 656), VX_MASK, PPCSPE, { RS, RB } },
2269 { "evfsctuiz", VX(4, 664), VX_MASK, PPCSPE, { RS, RB } },
2270 { "evfscfsi", VX(4, 657), VX_MASK, PPCSPE, { RS, RB } },
2271 { "evfscfuf", VX(4, 658), VX_MASK, PPCSPE, { RS, RB } },
2272 { "evfscfsf", VX(4, 659), VX_MASK, PPCSPE, { RS, RB } },
2273 { "evfsctui", VX(4, 660), VX_MASK, PPCSPE, { RS, RB } },
2274 { "evfsctsi", VX(4, 661), VX_MASK, PPCSPE, { RS, RB } },
2275 { "evfsctsiz", VX(4, 666), VX_MASK, PPCSPE, { RS, RB } },
2276 { "evfsctuf", VX(4, 662), VX_MASK, PPCSPE, { RS, RB } },
2277 { "evfsctsf", VX(4, 663), VX_MASK, PPCSPE, { RS, RB } },
2279 { "efsabs", VX(4, 708), VX_MASK, PPCEFS, { RS, RA } },
2280 { "efsnabs", VX(4, 709), VX_MASK, PPCEFS, { RS, RA } },
2281 { "efsneg", VX(4, 710), VX_MASK, PPCEFS, { RS, RA } },
2282 { "efsadd", VX(4, 704), VX_MASK, PPCEFS, { RS, RA, RB } },
2283 { "efssub", VX(4, 705), VX_MASK, PPCEFS, { RS, RA, RB } },
2284 { "efsmul", VX(4, 712), VX_MASK, PPCEFS, { RS, RA, RB } },
2285 { "efsdiv", VX(4, 713), VX_MASK, PPCEFS, { RS, RA, RB } },
2286 { "efscmpgt", VX(4, 716), VX_MASK, PPCEFS, { CRFD, RA, RB } },
2287 { "efscmplt", VX(4, 717), VX_MASK, PPCEFS, { CRFD, RA, RB } },
2288 { "efscmpeq", VX(4, 718), VX_MASK, PPCEFS, { CRFD, RA, RB } },
2289 { "efststgt", VX(4, 732), VX_MASK, PPCEFS, { CRFD, RA, RB } },
2290 { "efststlt", VX(4, 733), VX_MASK, PPCEFS, { CRFD, RA, RB } },
2291 { "efststeq", VX(4, 734), VX_MASK, PPCEFS, { CRFD, RA, RB } },
2292 { "efscfui", VX(4, 720), VX_MASK, PPCEFS, { RS, RB } },
2293 { "efsctuiz", VX(4, 728), VX_MASK, PPCEFS, { RS, RB } },
2294 { "efscfsi", VX(4, 721), VX_MASK, PPCEFS, { RS, RB } },
2295 { "efscfuf", VX(4, 722), VX_MASK, PPCEFS, { RS, RB } },
2296 { "efscfsf", VX(4, 723), VX_MASK, PPCEFS, { RS, RB } },
2297 { "efsctui", VX(4, 724), VX_MASK, PPCEFS, { RS, RB } },
2298 { "efsctsi", VX(4, 725), VX_MASK, PPCEFS, { RS, RB } },
2299 { "efsctsiz", VX(4, 730), VX_MASK, PPCEFS, { RS, RB } },
2300 { "efsctuf", VX(4, 726), VX_MASK, PPCEFS, { RS, RB } },
2301 { "efsctsf", VX(4, 727), VX_MASK, PPCEFS, { RS, RB } },
2303 { "evmhossf", VX(4, 1031), VX_MASK, PPCSPE, { RS, RA, RB } },
2304 { "evmhossfa", VX(4, 1063), VX_MASK, PPCSPE, { RS, RA, RB } },
2305 { "evmhosmf", VX(4, 1039), VX_MASK, PPCSPE, { RS, RA, RB } },
2306 { "evmhosmfa", VX(4, 1071), VX_MASK, PPCSPE, { RS, RA, RB } },
2307 { "evmhosmi", VX(4, 1037), VX_MASK, PPCSPE, { RS, RA, RB } },
2308 { "evmhosmia", VX(4, 1069), VX_MASK, PPCSPE, { RS, RA, RB } },
2309 { "evmhoumi", VX(4, 1036), VX_MASK, PPCSPE, { RS, RA, RB } },
2310 { "evmhoumia", VX(4, 1068), VX_MASK, PPCSPE, { RS, RA, RB } },
2311 { "evmhessf", VX(4, 1027), VX_MASK, PPCSPE, { RS, RA, RB } },
2312 { "evmhessfa", VX(4, 1059), VX_MASK, PPCSPE, { RS, RA, RB } },
2313 { "evmhesmf", VX(4, 1035), VX_MASK, PPCSPE, { RS, RA, RB } },
2314 { "evmhesmfa", VX(4, 1067), VX_MASK, PPCSPE, { RS, RA, RB } },
2315 { "evmhesmi", VX(4, 1033), VX_MASK, PPCSPE, { RS, RA, RB } },
2316 { "evmhesmia", VX(4, 1065), VX_MASK, PPCSPE, { RS, RA, RB } },
2317 { "evmheumi", VX(4, 1032), VX_MASK, PPCSPE, { RS, RA, RB } },
2318 { "evmheumia", VX(4, 1064), VX_MASK, PPCSPE, { RS, RA, RB } },
2320 { "evmhossfaaw",VX(4, 1287), VX_MASK, PPCSPE, { RS, RA, RB } },
2321 { "evmhossiaaw",VX(4, 1285), VX_MASK, PPCSPE, { RS, RA, RB } },
2322 { "evmhosmfaaw",VX(4, 1295), VX_MASK, PPCSPE, { RS, RA, RB } },
2323 { "evmhosmiaaw",VX(4, 1293), VX_MASK, PPCSPE, { RS, RA, RB } },
2324 { "evmhousiaaw",VX(4, 1284), VX_MASK, PPCSPE, { RS, RA, RB } },
2325 { "evmhoumiaaw",VX(4, 1292), VX_MASK, PPCSPE, { RS, RA, RB } },
2326 { "evmhessfaaw",VX(4, 1283), VX_MASK, PPCSPE, { RS, RA, RB } },
2327 { "evmhessiaaw",VX(4, 1281), VX_MASK, PPCSPE, { RS, RA, RB } },
2328 { "evmhesmfaaw",VX(4, 1291), VX_MASK, PPCSPE, { RS, RA, RB } },
2329 { "evmhesmiaaw",VX(4, 1289), VX_MASK, PPCSPE, { RS, RA, RB } },
2330 { "evmheusiaaw",VX(4, 1280), VX_MASK, PPCSPE, { RS, RA, RB } },
2331 { "evmheumiaaw",VX(4, 1288), VX_MASK, PPCSPE, { RS, RA, RB } },
2333 { "evmhossfanw",VX(4, 1415), VX_MASK, PPCSPE, { RS, RA, RB } },
2334 { "evmhossianw",VX(4, 1413), VX_MASK, PPCSPE, { RS, RA, RB } },
2335 { "evmhosmfanw",VX(4, 1423), VX_MASK, PPCSPE, { RS, RA, RB } },
2336 { "evmhosmianw",VX(4, 1421), VX_MASK, PPCSPE, { RS, RA, RB } },
2337 { "evmhousianw",VX(4, 1412), VX_MASK, PPCSPE, { RS, RA, RB } },
2338 { "evmhoumianw",VX(4, 1420), VX_MASK, PPCSPE, { RS, RA, RB } },
2339 { "evmhessfanw",VX(4, 1411), VX_MASK, PPCSPE, { RS, RA, RB } },
2340 { "evmhessianw",VX(4, 1409), VX_MASK, PPCSPE, { RS, RA, RB } },
2341 { "evmhesmfanw",VX(4, 1419), VX_MASK, PPCSPE, { RS, RA, RB } },
2342 { "evmhesmianw",VX(4, 1417), VX_MASK, PPCSPE, { RS, RA, RB } },
2343 { "evmheusianw",VX(4, 1408), VX_MASK, PPCSPE, { RS, RA, RB } },
2344 { "evmheumianw",VX(4, 1416), VX_MASK, PPCSPE, { RS, RA, RB } },
2346 { "evmhogsmfaa",VX(4, 1327), VX_MASK, PPCSPE, { RS, RA, RB } },
2347 { "evmhogsmiaa",VX(4, 1325), VX_MASK, PPCSPE, { RS, RA, RB } },
2348 { "evmhogumiaa",VX(4, 1324), VX_MASK, PPCSPE, { RS, RA, RB } },
2349 { "evmhegsmfaa",VX(4, 1323), VX_MASK, PPCSPE, { RS, RA, RB } },
2350 { "evmhegsmiaa",VX(4, 1321), VX_MASK, PPCSPE, { RS, RA, RB } },
2351 { "evmhegumiaa",VX(4, 1320), VX_MASK, PPCSPE, { RS, RA, RB } },
2353 { "evmhogsmfan",VX(4, 1455), VX_MASK, PPCSPE, { RS, RA, RB } },
2354 { "evmhogsmian",VX(4, 1453), VX_MASK, PPCSPE, { RS, RA, RB } },
2355 { "evmhogumian",VX(4, 1452), VX_MASK, PPCSPE, { RS, RA, RB } },
2356 { "evmhegsmfan",VX(4, 1451), VX_MASK, PPCSPE, { RS, RA, RB } },
2357 { "evmhegsmian",VX(4, 1449), VX_MASK, PPCSPE, { RS, RA, RB } },
2358 { "evmhegumian",VX(4, 1448), VX_MASK, PPCSPE, { RS, RA, RB } },
2360 { "evmwhssf", VX(4, 1095), VX_MASK, PPCSPE, { RS, RA, RB } },
2361 { "evmwhssfa", VX(4, 1127), VX_MASK, PPCSPE, { RS, RA, RB } },
2362 { "evmwhsmf", VX(4, 1103), VX_MASK, PPCSPE, { RS, RA, RB } },
2363 { "evmwhsmfa", VX(4, 1135), VX_MASK, PPCSPE, { RS, RA, RB } },
2364 { "evmwhsmi", VX(4, 1101), VX_MASK, PPCSPE, { RS, RA, RB } },
2365 { "evmwhsmia", VX(4, 1133), VX_MASK, PPCSPE, { RS, RA, RB } },
2366 { "evmwhumi", VX(4, 1100), VX_MASK, PPCSPE, { RS, RA, RB } },
2367 { "evmwhumia", VX(4, 1132), VX_MASK, PPCSPE, { RS, RA, RB } },
2369 { "evmwlumi", VX(4, 1096), VX_MASK, PPCSPE, { RS, RA, RB } },
2370 { "evmwlumia", VX(4, 1128), VX_MASK, PPCSPE, { RS, RA, RB } },
2372 { "evmwlssiaaw",VX(4, 1345), VX_MASK, PPCSPE, { RS, RA, RB } },
2373 { "evmwlsmiaaw",VX(4, 1353), VX_MASK, PPCSPE, { RS, RA, RB } },
2374 { "evmwlusiaaw",VX(4, 1344), VX_MASK, PPCSPE, { RS, RA, RB } },
2375 { "evmwlumiaaw",VX(4, 1352), VX_MASK, PPCSPE, { RS, RA, RB } },
2377 { "evmwlssianw",VX(4, 1473), VX_MASK, PPCSPE, { RS, RA, RB } },
2378 { "evmwlsmianw",VX(4, 1481), VX_MASK, PPCSPE, { RS, RA, RB } },
2379 { "evmwlusianw",VX(4, 1472), VX_MASK, PPCSPE, { RS, RA, RB } },
2380 { "evmwlumianw",VX(4, 1480), VX_MASK, PPCSPE, { RS, RA, RB } },
2382 { "evmwssf", VX(4, 1107), VX_MASK, PPCSPE, { RS, RA, RB } },
2383 { "evmwssfa", VX(4, 1139), VX_MASK, PPCSPE, { RS, RA, RB } },
2384 { "evmwsmf", VX(4, 1115), VX_MASK, PPCSPE, { RS, RA, RB } },
2385 { "evmwsmfa", VX(4, 1147), VX_MASK, PPCSPE, { RS, RA, RB } },
2386 { "evmwsmi", VX(4, 1113), VX_MASK, PPCSPE, { RS, RA, RB } },
2387 { "evmwsmia", VX(4, 1145), VX_MASK, PPCSPE, { RS, RA, RB } },
2388 { "evmwumi", VX(4, 1112), VX_MASK, PPCSPE, { RS, RA, RB } },
2389 { "evmwumia", VX(4, 1144), VX_MASK, PPCSPE, { RS, RA, RB } },
2391 { "evmwssfaa", VX(4, 1363), VX_MASK, PPCSPE, { RS, RA, RB } },
2392 { "evmwsmfaa", VX(4, 1371), VX_MASK, PPCSPE, { RS, RA, RB } },
2393 { "evmwsmiaa", VX(4, 1369), VX_MASK, PPCSPE, { RS, RA, RB } },
2394 { "evmwumiaa", VX(4, 1368), VX_MASK, PPCSPE, { RS, RA, RB } },
2396 { "evmwssfan", VX(4, 1491), VX_MASK, PPCSPE, { RS, RA, RB } },
2397 { "evmwsmfan", VX(4, 1499), VX_MASK, PPCSPE, { RS, RA, RB } },
2398 { "evmwsmian", VX(4, 1497), VX_MASK, PPCSPE, { RS, RA, RB } },
2399 { "evmwumian", VX(4, 1496), VX_MASK, PPCSPE, { RS, RA, RB } },
2401 { "evaddssiaaw",VX(4, 1217), VX_MASK, PPCSPE, { RS, RA } },
2402 { "evaddsmiaaw",VX(4, 1225), VX_MASK, PPCSPE, { RS, RA } },
2403 { "evaddusiaaw",VX(4, 1216), VX_MASK, PPCSPE, { RS, RA } },
2404 { "evaddumiaaw",VX(4, 1224), VX_MASK, PPCSPE, { RS, RA } },
2406 { "evsubfssiaaw",VX(4, 1219), VX_MASK, PPCSPE, { RS, RA } },
2407 { "evsubfsmiaaw",VX(4, 1227), VX_MASK, PPCSPE, { RS, RA } },
2408 { "evsubfusiaaw",VX(4, 1218), VX_MASK, PPCSPE, { RS, RA } },
2409 { "evsubfumiaaw",VX(4, 1226), VX_MASK, PPCSPE, { RS, RA } },
2411 { "evmra", VX(4, 1220), VX_MASK, PPCSPE, { RS, RA } },
2413 { "evdivws", VX(4, 1222), VX_MASK, PPCSPE, { RS, RA, RB } },
2414 { "evdivwu", VX(4, 1223), VX_MASK, PPCSPE, { RS, RA, RB } },
2416 { "mulli", OP(7), OP_MASK, PPCCOM, { RT, RA, SI } },
2417 { "muli", OP(7), OP_MASK, PWRCOM, { RT, RA, SI } },
2419 { "subfic", OP(8), OP_MASK, PPCCOM, { RT, RA, SI } },
2420 { "sfi", OP(8), OP_MASK, PWRCOM, { RT, RA, SI } },
2422 { "dozi", OP(9), OP_MASK, M601, { RT, RA, SI } },
2424 { "bce", B(9,0,0), B_MASK, BOOKE64, { BO, BI, BD } },
2425 { "bcel", B(9,0,1), B_MASK, BOOKE64, { BO, BI, BD } },
2426 { "bcea", B(9,1,0), B_MASK, BOOKE64, { BO, BI, BDA } },
2427 { "bcela", B(9,1,1), B_MASK, BOOKE64, { BO, BI, BDA } },
2429 { "cmplwi", OPL(10,0), OPL_MASK, PPCCOM, { OBF, RA, UI } },
2430 { "cmpldi", OPL(10,1), OPL_MASK, PPC64, { OBF, RA, UI } },
2431 { "cmpli", OP(10), OP_MASK, PPCONLY, { BF, L, RA, UI } },
2432 { "cmpli", OP(10), OP_MASK, PWRCOM, { BF, RA, UI } },
2434 { "cmpwi", OPL(11,0), OPL_MASK, PPCCOM, { OBF, RA, SI } },
2435 { "cmpdi", OPL(11,1), OPL_MASK, PPC64, { OBF, RA, SI } },
2436 { "cmpi", OP(11), OP_MASK, PPCONLY, { BF, L, RA, SI } },
2437 { "cmpi", OP(11), OP_MASK, PWRCOM, { BF, RA, SI } },
2439 { "addic", OP(12), OP_MASK, PPCCOM, { RT, RA, SI } },
2440 { "ai", OP(12), OP_MASK, PWRCOM, { RT, RA, SI } },
2441 { "subic", OP(12), OP_MASK, PPCCOM, { RT, RA, NSI } },
2443 { "addic.", OP(13), OP_MASK, PPCCOM, { RT, RA, SI } },
2444 { "ai.", OP(13), OP_MASK, PWRCOM, { RT, RA, SI } },
2445 { "subic.", OP(13), OP_MASK, PPCCOM, { RT, RA, NSI } },
2447 { "li", OP(14), DRA_MASK, PPCCOM, { RT, SI } },
2448 { "lil", OP(14), DRA_MASK, PWRCOM, { RT, SI } },
2449 { "addi", OP(14), OP_MASK, PPCCOM, { RT, RA, SI } },
2450 { "cal", OP(14), OP_MASK, PWRCOM, { RT, D, RA } },
2451 { "subi", OP(14), OP_MASK, PPCCOM, { RT, RA, NSI } },
2452 { "la", OP(14), OP_MASK, PPCCOM, { RT, D, RA } },
2454 { "lis", OP(15), DRA_MASK, PPCCOM, { RT, SISIGNOPT } },
2455 { "liu", OP(15), DRA_MASK, PWRCOM, { RT, SISIGNOPT } },
2456 { "addis", OP(15), OP_MASK, PPCCOM, { RT,RA,SISIGNOPT } },
2457 { "cau", OP(15), OP_MASK, PWRCOM, { RT,RA,SISIGNOPT } },
2458 { "subis", OP(15), OP_MASK, PPCCOM, { RT, RA, NSI } },
2460 { "bdnz-", BBO(16,BODNZ,0,0), BBOATBI_MASK, PPCCOM, { BDM } },
2461 { "bdnz+", BBO(16,BODNZ,0,0), BBOATBI_MASK, PPCCOM, { BDP } },
2462 { "bdnz", BBO(16,BODNZ,0,0), BBOATBI_MASK, PPCCOM, { BD } },
2463 { "bdn", BBO(16,BODNZ,0,0), BBOATBI_MASK, PWRCOM, { BD } },
2464 { "bdnzl-", BBO(16,BODNZ,0,1), BBOATBI_MASK, PPCCOM, { BDM } },
2465 { "bdnzl+", BBO(16,BODNZ,0,1), BBOATBI_MASK, PPCCOM, { BDP } },
2466 { "bdnzl", BBO(16,BODNZ,0,1), BBOATBI_MASK, PPCCOM, { BD } },
2467 { "bdnl", BBO(16,BODNZ,0,1), BBOATBI_MASK, PWRCOM, { BD } },
2468 { "bdnza-", BBO(16,BODNZ,1,0), BBOATBI_MASK, PPCCOM, { BDMA } },
2469 { "bdnza+", BBO(16,BODNZ,1,0), BBOATBI_MASK, PPCCOM, { BDPA } },
2470 { "bdnza", BBO(16,BODNZ,1,0), BBOATBI_MASK, PPCCOM, { BDA } },
2471 { "bdna", BBO(16,BODNZ,1,0), BBOATBI_MASK, PWRCOM, { BDA } },
2472 { "bdnzla-", BBO(16,BODNZ,1,1), BBOATBI_MASK, PPCCOM, { BDMA } },
2473 { "bdnzla+", BBO(16,BODNZ,1,1), BBOATBI_MASK, PPCCOM, { BDPA } },
2474 { "bdnzla", BBO(16,BODNZ,1,1), BBOATBI_MASK, PPCCOM, { BDA } },
2475 { "bdnla", BBO(16,BODNZ,1,1), BBOATBI_MASK, PWRCOM, { BDA } },
2476 { "bdz-", BBO(16,BODZ,0,0), BBOATBI_MASK, PPCCOM, { BDM } },
2477 { "bdz+", BBO(16,BODZ,0,0), BBOATBI_MASK, PPCCOM, { BDP } },
2478 { "bdz", BBO(16,BODZ,0,0), BBOATBI_MASK, COM, { BD } },
2479 { "bdzl-", BBO(16,BODZ,0,1), BBOATBI_MASK, PPCCOM, { BDM } },
2480 { "bdzl+", BBO(16,BODZ,0,1), BBOATBI_MASK, PPCCOM, { BDP } },
2481 { "bdzl", BBO(16,BODZ,0,1), BBOATBI_MASK, COM, { BD } },
2482 { "bdza-", BBO(16,BODZ,1,0), BBOATBI_MASK, PPCCOM, { BDMA } },
2483 { "bdza+", BBO(16,BODZ,1,0), BBOATBI_MASK, PPCCOM, { BDPA } },
2484 { "bdza", BBO(16,BODZ,1,0), BBOATBI_MASK, COM, { BDA } },
2485 { "bdzla-", BBO(16,BODZ,1,1), BBOATBI_MASK, PPCCOM, { BDMA } },
2486 { "bdzla+", BBO(16,BODZ,1,1), BBOATBI_MASK, PPCCOM, { BDPA } },
2487 { "bdzla", BBO(16,BODZ,1,1), BBOATBI_MASK, COM, { BDA } },
2488 { "blt-", BBOCB(16,BOT,CBLT,0,0), BBOATCB_MASK, PPCCOM, { CR, BDM } },
2489 { "blt+", BBOCB(16,BOT,CBLT,0,0), BBOATCB_MASK, PPCCOM, { CR, BDP } },
2490 { "blt", BBOCB(16,BOT,CBLT,0,0), BBOATCB_MASK, COM, { CR, BD } },
2491 { "bltl-", BBOCB(16,BOT,CBLT,0,1), BBOATCB_MASK, PPCCOM, { CR, BDM } },
2492 { "bltl+", BBOCB(16,BOT,CBLT,0,1), BBOATCB_MASK, PPCCOM, { CR, BDP } },
2493 { "bltl", BBOCB(16,BOT,CBLT,0,1), BBOATCB_MASK, COM, { CR, BD } },
2494 { "blta-", BBOCB(16,BOT,CBLT,1,0), BBOATCB_MASK, PPCCOM, { CR, BDMA } },
2495 { "blta+", BBOCB(16,BOT,CBLT,1,0), BBOATCB_MASK, PPCCOM, { CR, BDPA } },
2496 { "blta", BBOCB(16,BOT,CBLT,1,0), BBOATCB_MASK, COM, { CR, BDA } },
2497 { "bltla-", BBOCB(16,BOT,CBLT,1,1), BBOATCB_MASK, PPCCOM, { CR, BDMA } },
2498 { "bltla+", BBOCB(16,BOT,CBLT,1,1), BBOATCB_MASK, PPCCOM, { CR, BDPA } },
2499 { "bltla", BBOCB(16,BOT,CBLT,1,1), BBOATCB_MASK, COM, { CR, BDA } },
2500 { "bgt-", BBOCB(16,BOT,CBGT,0,0), BBOATCB_MASK, PPCCOM, { CR, BDM } },
2501 { "bgt+", BBOCB(16,BOT,CBGT,0,0), BBOATCB_MASK, PPCCOM, { CR, BDP } },
2502 { "bgt", BBOCB(16,BOT,CBGT,0,0), BBOATCB_MASK, COM, { CR, BD } },
2503 { "bgtl-", BBOCB(16,BOT,CBGT,0,1), BBOATCB_MASK, PPCCOM, { CR, BDM } },
2504 { "bgtl+", BBOCB(16,BOT,CBGT,0,1), BBOATCB_MASK, PPCCOM, { CR, BDP } },
2505 { "bgtl", BBOCB(16,BOT,CBGT,0,1), BBOATCB_MASK, COM, { CR, BD } },
2506 { "bgta-", BBOCB(16,BOT,CBGT,1,0), BBOATCB_MASK, PPCCOM, { CR, BDMA } },
2507 { "bgta+", BBOCB(16,BOT,CBGT,1,0), BBOATCB_MASK, PPCCOM, { CR, BDPA } },
2508 { "bgta", BBOCB(16,BOT,CBGT,1,0), BBOATCB_MASK, COM, { CR, BDA } },
2509 { "bgtla-", BBOCB(16,BOT,CBGT,1,1), BBOATCB_MASK, PPCCOM, { CR, BDMA } },
2510 { "bgtla+", BBOCB(16,BOT,CBGT,1,1), BBOATCB_MASK, PPCCOM, { CR, BDPA } },
2511 { "bgtla", BBOCB(16,BOT,CBGT,1,1), BBOATCB_MASK, COM, { CR, BDA } },
2512 { "beq-", BBOCB(16,BOT,CBEQ,0,0), BBOATCB_MASK, PPCCOM, { CR, BDM } },
2513 { "beq+", BBOCB(16,BOT,CBEQ,0,0), BBOATCB_MASK, PPCCOM, { CR, BDP } },
2514 { "beq", BBOCB(16,BOT,CBEQ,0,0), BBOATCB_MASK, COM, { CR, BD } },
2515 { "beql-", BBOCB(16,BOT,CBEQ,0,1), BBOATCB_MASK, PPCCOM, { CR, BDM } },
2516 { "beql+", BBOCB(16,BOT,CBEQ,0,1), BBOATCB_MASK, PPCCOM, { CR, BDP } },
2517 { "beql", BBOCB(16,BOT,CBEQ,0,1), BBOATCB_MASK, COM, { CR, BD } },
2518 { "beqa-", BBOCB(16,BOT,CBEQ,1,0), BBOATCB_MASK, PPCCOM, { CR, BDMA } },
2519 { "beqa+", BBOCB(16,BOT,CBEQ,1,0), BBOATCB_MASK, PPCCOM, { CR, BDPA } },
2520 { "beqa", BBOCB(16,BOT,CBEQ,1,0), BBOATCB_MASK, COM, { CR, BDA } },
2521 { "beqla-", BBOCB(16,BOT,CBEQ,1,1), BBOATCB_MASK, PPCCOM, { CR, BDMA } },
2522 { "beqla+", BBOCB(16,BOT,CBEQ,1,1), BBOATCB_MASK, PPCCOM, { CR, BDPA } },
2523 { "beqla", BBOCB(16,BOT,CBEQ,1,1), BBOATCB_MASK, COM, { CR, BDA } },
2524 { "bso-", BBOCB(16,BOT,CBSO,0,0), BBOATCB_MASK, PPCCOM, { CR, BDM } },
2525 { "bso+", BBOCB(16,BOT,CBSO,0,0), BBOATCB_MASK, PPCCOM, { CR, BDP } },
2526 { "bso", BBOCB(16,BOT,CBSO,0,0), BBOATCB_MASK, COM, { CR, BD } },
2527 { "bsol-", BBOCB(16,BOT,CBSO,0,1), BBOATCB_MASK, PPCCOM, { CR, BDM } },
2528 { "bsol+", BBOCB(16,BOT,CBSO,0,1), BBOATCB_MASK, PPCCOM, { CR, BDP } },
2529 { "bsol", BBOCB(16,BOT,CBSO,0,1), BBOATCB_MASK, COM, { CR, BD } },
2530 { "bsoa-", BBOCB(16,BOT,CBSO,1,0), BBOATCB_MASK, PPCCOM, { CR, BDMA } },
2531 { "bsoa+", BBOCB(16,BOT,CBSO,1,0), BBOATCB_MASK, PPCCOM, { CR, BDPA } },
2532 { "bsoa", BBOCB(16,BOT,CBSO,1,0), BBOATCB_MASK, COM, { CR, BDA } },
2533 { "bsola-", BBOCB(16,BOT,CBSO,1,1), BBOATCB_MASK, PPCCOM, { CR, BDMA } },
2534 { "bsola+", BBOCB(16,BOT,CBSO,1,1), BBOATCB_MASK, PPCCOM, { CR, BDPA } },
2535 { "bsola", BBOCB(16,BOT,CBSO,1,1), BBOATCB_MASK, COM, { CR, BDA } },
2536 { "bun-", BBOCB(16,BOT,CBSO,0,0), BBOATCB_MASK, PPCCOM, { CR, BDM } },
2537 { "bun+", BBOCB(16,BOT,CBSO,0,0), BBOATCB_MASK, PPCCOM, { CR, BDP } },
2538 { "bun", BBOCB(16,BOT,CBSO,0,0), BBOATCB_MASK, PPCCOM, { CR, BD } },
2539 { "bunl-", BBOCB(16,BOT,CBSO,0,1), BBOATCB_MASK, PPCCOM, { CR, BDM } },
2540 { "bunl+", BBOCB(16,BOT,CBSO,0,1), BBOATCB_MASK, PPCCOM, { CR, BDP } },
2541 { "bunl", BBOCB(16,BOT,CBSO,0,1), BBOATCB_MASK, PPCCOM, { CR, BD } },
2542 { "buna-", BBOCB(16,BOT,CBSO,1,0), BBOATCB_MASK, PPCCOM, { CR, BDMA } },
2543 { "buna+", BBOCB(16,BOT,CBSO,1,0), BBOATCB_MASK, PPCCOM, { CR, BDPA } },
2544 { "buna", BBOCB(16,BOT,CBSO,1,0), BBOATCB_MASK, PPCCOM, { CR, BDA } },
2545 { "bunla-", BBOCB(16,BOT,CBSO,1,1), BBOATCB_MASK, PPCCOM, { CR, BDMA } },
2546 { "bunla+", BBOCB(16,BOT,CBSO,1,1), BBOATCB_MASK, PPCCOM, { CR, BDPA } },
2547 { "bunla", BBOCB(16,BOT,CBSO,1,1), BBOATCB_MASK, PPCCOM, { CR, BDA } },
2548 { "bge-", BBOCB(16,BOF,CBLT,0,0), BBOATCB_MASK, PPCCOM, { CR, BDM } },
2549 { "bge+", BBOCB(16,BOF,CBLT,0,0), BBOATCB_MASK, PPCCOM, { CR, BDP } },
2550 { "bge", BBOCB(16,BOF,CBLT,0,0), BBOATCB_MASK, COM, { CR, BD } },
2551 { "bgel-", BBOCB(16,BOF,CBLT,0,1), BBOATCB_MASK, PPCCOM, { CR, BDM } },
2552 { "bgel+", BBOCB(16,BOF,CBLT,0,1), BBOATCB_MASK, PPCCOM, { CR, BDP } },
2553 { "bgel", BBOCB(16,BOF,CBLT,0,1), BBOATCB_MASK, COM, { CR, BD } },
2554 { "bgea-", BBOCB(16,BOF,CBLT,1,0), BBOATCB_MASK, PPCCOM, { CR, BDMA } },
2555 { "bgea+", BBOCB(16,BOF,CBLT,1,0), BBOATCB_MASK, PPCCOM, { CR, BDPA } },
2556 { "bgea", BBOCB(16,BOF,CBLT,1,0), BBOATCB_MASK, COM, { CR, BDA } },
2557 { "bgela-", BBOCB(16,BOF,CBLT,1,1), BBOATCB_MASK, PPCCOM, { CR, BDMA } },
2558 { "bgela+", BBOCB(16,BOF,CBLT,1,1), BBOATCB_MASK, PPCCOM, { CR, BDPA } },
2559 { "bgela", BBOCB(16,BOF,CBLT,1,1), BBOATCB_MASK, COM, { CR, BDA } },
2560 { "bnl-", BBOCB(16,BOF,CBLT,0,0), BBOATCB_MASK, PPCCOM, { CR, BDM } },
2561 { "bnl+", BBOCB(16,BOF,CBLT,0,0), BBOATCB_MASK, PPCCOM, { CR, BDP } },
2562 { "bnl", BBOCB(16,BOF,CBLT,0,0), BBOATCB_MASK, COM, { CR, BD } },
2563 { "bnll-", BBOCB(16,BOF,CBLT,0,1), BBOATCB_MASK, PPCCOM, { CR, BDM } },
2564 { "bnll+", BBOCB(16,BOF,CBLT,0,1), BBOATCB_MASK, PPCCOM, { CR, BDP } },
2565 { "bnll", BBOCB(16,BOF,CBLT,0,1), BBOATCB_MASK, COM, { CR, BD } },
2566 { "bnla-", BBOCB(16,BOF,CBLT,1,0), BBOATCB_MASK, PPCCOM, { CR, BDMA } },
2567 { "bnla+", BBOCB(16,BOF,CBLT,1,0), BBOATCB_MASK, PPCCOM, { CR, BDPA } },
2568 { "bnla", BBOCB(16,BOF,CBLT,1,0), BBOATCB_MASK, COM, { CR, BDA } },
2569 { "bnlla-", BBOCB(16,BOF,CBLT,1,1), BBOATCB_MASK, PPCCOM, { CR, BDMA } },
2570 { "bnlla+", BBOCB(16,BOF,CBLT,1,1), BBOATCB_MASK, PPCCOM, { CR, BDPA } },
2571 { "bnlla", BBOCB(16,BOF,CBLT,1,1), BBOATCB_MASK, COM, { CR, BDA } },
2572 { "ble-", BBOCB(16,BOF,CBGT,0,0), BBOATCB_MASK, PPCCOM, { CR, BDM } },
2573 { "ble+", BBOCB(16,BOF,CBGT,0,0), BBOATCB_MASK, PPCCOM, { CR, BDP } },
2574 { "ble", BBOCB(16,BOF,CBGT,0,0), BBOATCB_MASK, COM, { CR, BD } },
2575 { "blel-", BBOCB(16,BOF,CBGT,0,1), BBOATCB_MASK, PPCCOM, { CR, BDM } },
2576 { "blel+", BBOCB(16,BOF,CBGT,0,1), BBOATCB_MASK, PPCCOM, { CR, BDP } },
2577 { "blel", BBOCB(16,BOF,CBGT,0,1), BBOATCB_MASK, COM, { CR, BD } },
2578 { "blea-", BBOCB(16,BOF,CBGT,1,0), BBOATCB_MASK, PPCCOM, { CR, BDMA } },
2579 { "blea+", BBOCB(16,BOF,CBGT,1,0), BBOATCB_MASK, PPCCOM, { CR, BDPA } },
2580 { "blea", BBOCB(16,BOF,CBGT,1,0), BBOATCB_MASK, COM, { CR, BDA } },
2581 { "blela-", BBOCB(16,BOF,CBGT,1,1), BBOATCB_MASK, PPCCOM, { CR, BDMA } },
2582 { "blela+", BBOCB(16,BOF,CBGT,1,1), BBOATCB_MASK, PPCCOM, { CR, BDPA } },
2583 { "blela", BBOCB(16,BOF,CBGT,1,1), BBOATCB_MASK, COM, { CR, BDA } },
2584 { "bng-", BBOCB(16,BOF,CBGT,0,0), BBOATCB_MASK, PPCCOM, { CR, BDM } },
2585 { "bng+", BBOCB(16,BOF,CBGT,0,0), BBOATCB_MASK, PPCCOM, { CR, BDP } },
2586 { "bng", BBOCB(16,BOF,CBGT,0,0), BBOATCB_MASK, COM, { CR, BD } },
2587 { "bngl-", BBOCB(16,BOF,CBGT,0,1), BBOATCB_MASK, PPCCOM, { CR, BDM } },
2588 { "bngl+", BBOCB(16,BOF,CBGT,0,1), BBOATCB_MASK, PPCCOM, { CR, BDP } },
2589 { "bngl", BBOCB(16,BOF,CBGT,0,1), BBOATCB_MASK, COM, { CR, BD } },
2590 { "bnga-", BBOCB(16,BOF,CBGT,1,0), BBOATCB_MASK, PPCCOM, { CR, BDMA } },
2591 { "bnga+", BBOCB(16,BOF,CBGT,1,0), BBOATCB_MASK, PPCCOM, { CR, BDPA } },
2592 { "bnga", BBOCB(16,BOF,CBGT,1,0), BBOATCB_MASK, COM, { CR, BDA } },
2593 { "bngla-", BBOCB(16,BOF,CBGT,1,1), BBOATCB_MASK, PPCCOM, { CR, BDMA } },
2594 { "bngla+", BBOCB(16,BOF,CBGT,1,1), BBOATCB_MASK, PPCCOM, { CR, BDPA } },
2595 { "bngla", BBOCB(16,BOF,CBGT,1,1), BBOATCB_MASK, COM, { CR, BDA } },
2596 { "bne-", BBOCB(16,BOF,CBEQ,0,0), BBOATCB_MASK, PPCCOM, { CR, BDM } },
2597 { "bne+", BBOCB(16,BOF,CBEQ,0,0), BBOATCB_MASK, PPCCOM, { CR, BDP } },
2598 { "bne", BBOCB(16,BOF,CBEQ,0,0), BBOATCB_MASK, COM, { CR, BD } },
2599 { "bnel-", BBOCB(16,BOF,CBEQ,0,1), BBOATCB_MASK, PPCCOM, { CR, BDM } },
2600 { "bnel+", BBOCB(16,BOF,CBEQ,0,1), BBOATCB_MASK, PPCCOM, { CR, BDP } },
2601 { "bnel", BBOCB(16,BOF,CBEQ,0,1), BBOATCB_MASK, COM, { CR, BD } },
2602 { "bnea-", BBOCB(16,BOF,CBEQ,1,0), BBOATCB_MASK, PPCCOM, { CR, BDMA } },
2603 { "bnea+", BBOCB(16,BOF,CBEQ,1,0), BBOATCB_MASK, PPCCOM, { CR, BDPA } },
2604 { "bnea", BBOCB(16,BOF,CBEQ,1,0), BBOATCB_MASK, COM, { CR, BDA } },
2605 { "bnela-", BBOCB(16,BOF,CBEQ,1,1), BBOATCB_MASK, PPCCOM, { CR, BDMA } },
2606 { "bnela+", BBOCB(16,BOF,CBEQ,1,1), BBOATCB_MASK, PPCCOM, { CR, BDPA } },
2607 { "bnela", BBOCB(16,BOF,CBEQ,1,1), BBOATCB_MASK, COM, { CR, BDA } },
2608 { "bns-", BBOCB(16,BOF,CBSO,0,0), BBOATCB_MASK, PPCCOM, { CR, BDM } },
2609 { "bns+", BBOCB(16,BOF,CBSO,0,0), BBOATCB_MASK, PPCCOM, { CR, BDP } },
2610 { "bns", BBOCB(16,BOF,CBSO,0,0), BBOATCB_MASK, COM, { CR, BD } },
2611 { "bnsl-", BBOCB(16,BOF,CBSO,0,1), BBOATCB_MASK, PPCCOM, { CR, BDM } },
2612 { "bnsl+", BBOCB(16,BOF,CBSO,0,1), BBOATCB_MASK, PPCCOM, { CR, BDP } },
2613 { "bnsl", BBOCB(16,BOF,CBSO,0,1), BBOATCB_MASK, COM, { CR, BD } },
2614 { "bnsa-", BBOCB(16,BOF,CBSO,1,0), BBOATCB_MASK, PPCCOM, { CR, BDMA } },
2615 { "bnsa+", BBOCB(16,BOF,CBSO,1,0), BBOATCB_MASK, PPCCOM, { CR, BDPA } },
2616 { "bnsa", BBOCB(16,BOF,CBSO,1,0), BBOATCB_MASK, COM, { CR, BDA } },
2617 { "bnsla-", BBOCB(16,BOF,CBSO,1,1), BBOATCB_MASK, PPCCOM, { CR, BDMA } },
2618 { "bnsla+", BBOCB(16,BOF,CBSO,1,1), BBOATCB_MASK, PPCCOM, { CR, BDPA } },
2619 { "bnsla", BBOCB(16,BOF,CBSO,1,1), BBOATCB_MASK, COM, { CR, BDA } },
2620 { "bnu-", BBOCB(16,BOF,CBSO,0,0), BBOATCB_MASK, PPCCOM, { CR, BDM } },
2621 { "bnu+", BBOCB(16,BOF,CBSO,0,0), BBOATCB_MASK, PPCCOM, { CR, BDP } },
2622 { "bnu", BBOCB(16,BOF,CBSO,0,0), BBOATCB_MASK, PPCCOM, { CR, BD } },
2623 { "bnul-", BBOCB(16,BOF,CBSO,0,1), BBOATCB_MASK, PPCCOM, { CR, BDM } },
2624 { "bnul+", BBOCB(16,BOF,CBSO,0,1), BBOATCB_MASK, PPCCOM, { CR, BDP } },
2625 { "bnul", BBOCB(16,BOF,CBSO,0,1), BBOATCB_MASK, PPCCOM, { CR, BD } },
2626 { "bnua-", BBOCB(16,BOF,CBSO,1,0), BBOATCB_MASK, PPCCOM, { CR, BDMA } },
2627 { "bnua+", BBOCB(16,BOF,CBSO,1,0), BBOATCB_MASK, PPCCOM, { CR, BDPA } },
2628 { "bnua", BBOCB(16,BOF,CBSO,1,0), BBOATCB_MASK, PPCCOM, { CR, BDA } },
2629 { "bnula-", BBOCB(16,BOF,CBSO,1,1), BBOATCB_MASK, PPCCOM, { CR, BDMA } },
2630 { "bnula+", BBOCB(16,BOF,CBSO,1,1), BBOATCB_MASK, PPCCOM, { CR, BDPA } },
2631 { "bnula", BBOCB(16,BOF,CBSO,1,1), BBOATCB_MASK, PPCCOM, { CR, BDA } },
2632 { "bdnzt-", BBO(16,BODNZT,0,0), BBOY_MASK, NOPOWER4, { BI, BDM } },
2633 { "bdnzt+", BBO(16,BODNZT,0,0), BBOY_MASK, NOPOWER4, { BI, BDP } },
2634 { "bdnzt", BBO(16,BODNZT,0,0), BBOY_MASK, PPCCOM, { BI, BD } },
2635 { "bdnztl-", BBO(16,BODNZT,0,1), BBOY_MASK, NOPOWER4, { BI, BDM } },
2636 { "bdnztl+", BBO(16,BODNZT,0,1), BBOY_MASK, NOPOWER4, { BI, BDP } },
2637 { "bdnztl", BBO(16,BODNZT,0,1), BBOY_MASK, PPCCOM, { BI, BD } },
2638 { "bdnzta-", BBO(16,BODNZT,1,0), BBOY_MASK, NOPOWER4, { BI, BDMA } },
2639 { "bdnzta+", BBO(16,BODNZT,1,0), BBOY_MASK, NOPOWER4, { BI, BDPA } },
2640 { "bdnzta", BBO(16,BODNZT,1,0), BBOY_MASK, PPCCOM, { BI, BDA } },
2641 { "bdnztla-",BBO(16,BODNZT,1,1), BBOY_MASK, NOPOWER4, { BI, BDMA } },
2642 { "bdnztla+",BBO(16,BODNZT,1,1), BBOY_MASK, NOPOWER4, { BI, BDPA } },
2643 { "bdnztla", BBO(16,BODNZT,1,1), BBOY_MASK, PPCCOM, { BI, BDA } },
2644 { "bdnzf-", BBO(16,BODNZF,0,0), BBOY_MASK, NOPOWER4, { BI, BDM } },
2645 { "bdnzf+", BBO(16,BODNZF,0,0), BBOY_MASK, NOPOWER4, { BI, BDP } },
2646 { "bdnzf", BBO(16,BODNZF,0,0), BBOY_MASK, PPCCOM, { BI, BD } },
2647 { "bdnzfl-", BBO(16,BODNZF,0,1), BBOY_MASK, NOPOWER4, { BI, BDM } },
2648 { "bdnzfl+", BBO(16,BODNZF,0,1), BBOY_MASK, NOPOWER4, { BI, BDP } },
2649 { "bdnzfl", BBO(16,BODNZF,0,1), BBOY_MASK, PPCCOM, { BI, BD } },
2650 { "bdnzfa-", BBO(16,BODNZF,1,0), BBOY_MASK, NOPOWER4, { BI, BDMA } },
2651 { "bdnzfa+", BBO(16,BODNZF,1,0), BBOY_MASK, NOPOWER4, { BI, BDPA } },
2652 { "bdnzfa", BBO(16,BODNZF,1,0), BBOY_MASK, PPCCOM, { BI, BDA } },
2653 { "bdnzfla-",BBO(16,BODNZF,1,1), BBOY_MASK, NOPOWER4, { BI, BDMA } },
2654 { "bdnzfla+",BBO(16,BODNZF,1,1), BBOY_MASK, NOPOWER4, { BI, BDPA } },
2655 { "bdnzfla", BBO(16,BODNZF,1,1), BBOY_MASK, PPCCOM, { BI, BDA } },
2656 { "bt-", BBO(16,BOT,0,0), BBOAT_MASK, PPCCOM, { BI, BDM } },
2657 { "bt+", BBO(16,BOT,0,0), BBOAT_MASK, PPCCOM, { BI, BDP } },
2658 { "bt", BBO(16,BOT,0,0), BBOAT_MASK, PPCCOM, { BI, BD } },
2659 { "bbt", BBO(16,BOT,0,0), BBOAT_MASK, PWRCOM, { BI, BD } },
2660 { "btl-", BBO(16,BOT,0,1), BBOAT_MASK, PPCCOM, { BI, BDM } },
2661 { "btl+", BBO(16,BOT,0,1), BBOAT_MASK, PPCCOM, { BI, BDP } },
2662 { "btl", BBO(16,BOT,0,1), BBOAT_MASK, PPCCOM, { BI, BD } },
2663 { "bbtl", BBO(16,BOT,0,1), BBOAT_MASK, PWRCOM, { BI, BD } },
2664 { "bta-", BBO(16,BOT,1,0), BBOAT_MASK, PPCCOM, { BI, BDMA } },
2665 { "bta+", BBO(16,BOT,1,0), BBOAT_MASK, PPCCOM, { BI, BDPA } },
2666 { "bta", BBO(16,BOT,1,0), BBOAT_MASK, PPCCOM, { BI, BDA } },
2667 { "bbta", BBO(16,BOT,1,0), BBOAT_MASK, PWRCOM, { BI, BDA } },
2668 { "btla-", BBO(16,BOT,1,1), BBOAT_MASK, PPCCOM, { BI, BDMA } },
2669 { "btla+", BBO(16,BOT,1,1), BBOAT_MASK, PPCCOM, { BI, BDPA } },
2670 { "btla", BBO(16,BOT,1,1), BBOAT_MASK, PPCCOM, { BI, BDA } },
2671 { "bbtla", BBO(16,BOT,1,1), BBOAT_MASK, PWRCOM, { BI, BDA } },
2672 { "bf-", BBO(16,BOF,0,0), BBOAT_MASK, PPCCOM, { BI, BDM } },
2673 { "bf+", BBO(16,BOF,0,0), BBOAT_MASK, PPCCOM, { BI, BDP } },
2674 { "bf", BBO(16,BOF,0,0), BBOAT_MASK, PPCCOM, { BI, BD } },
2675 { "bbf", BBO(16,BOF,0,0), BBOAT_MASK, PWRCOM, { BI, BD } },
2676 { "bfl-", BBO(16,BOF,0,1), BBOAT_MASK, PPCCOM, { BI, BDM } },
2677 { "bfl+", BBO(16,BOF,0,1), BBOAT_MASK, PPCCOM, { BI, BDP } },
2678 { "bfl", BBO(16,BOF,0,1), BBOAT_MASK, PPCCOM, { BI, BD } },
2679 { "bbfl", BBO(16,BOF,0,1), BBOAT_MASK, PWRCOM, { BI, BD } },
2680 { "bfa-", BBO(16,BOF,1,0), BBOAT_MASK, PPCCOM, { BI, BDMA } },
2681 { "bfa+", BBO(16,BOF,1,0), BBOAT_MASK, PPCCOM, { BI, BDPA } },
2682 { "bfa", BBO(16,BOF,1,0), BBOAT_MASK, PPCCOM, { BI, BDA } },
2683 { "bbfa", BBO(16,BOF,1,0), BBOAT_MASK, PWRCOM, { BI, BDA } },
2684 { "bfla-", BBO(16,BOF,1,1), BBOAT_MASK, PPCCOM, { BI, BDMA } },
2685 { "bfla+", BBO(16,BOF,1,1), BBOAT_MASK, PPCCOM, { BI, BDPA } },
2686 { "bfla", BBO(16,BOF,1,1), BBOAT_MASK, PPCCOM, { BI, BDA } },
2687 { "bbfla", BBO(16,BOF,1,1), BBOAT_MASK, PWRCOM, { BI, BDA } },
2688 { "bdzt-", BBO(16,BODZT,0,0), BBOY_MASK, NOPOWER4, { BI, BDM } },
2689 { "bdzt+", BBO(16,BODZT,0,0), BBOY_MASK, NOPOWER4, { BI, BDP } },
2690 { "bdzt", BBO(16,BODZT,0,0), BBOY_MASK, PPCCOM, { BI, BD } },
2691 { "bdztl-", BBO(16,BODZT,0,1), BBOY_MASK, NOPOWER4, { BI, BDM } },
2692 { "bdztl+", BBO(16,BODZT,0,1), BBOY_MASK, NOPOWER4, { BI, BDP } },
2693 { "bdztl", BBO(16,BODZT,0,1), BBOY_MASK, PPCCOM, { BI, BD } },
2694 { "bdzta-", BBO(16,BODZT,1,0), BBOY_MASK, NOPOWER4, { BI, BDMA } },
2695 { "bdzta+", BBO(16,BODZT,1,0), BBOY_MASK, NOPOWER4, { BI, BDPA } },
2696 { "bdzta", BBO(16,BODZT,1,0), BBOY_MASK, PPCCOM, { BI, BDA } },
2697 { "bdztla-", BBO(16,BODZT,1,1), BBOY_MASK, NOPOWER4, { BI, BDMA } },
2698 { "bdztla+", BBO(16,BODZT,1,1), BBOY_MASK, NOPOWER4, { BI, BDPA } },
2699 { "bdztla", BBO(16,BODZT,1,1), BBOY_MASK, PPCCOM, { BI, BDA } },
2700 { "bdzf-", BBO(16,BODZF,0,0), BBOY_MASK, NOPOWER4, { BI, BDM } },
2701 { "bdzf+", BBO(16,BODZF,0,0), BBOY_MASK, NOPOWER4, { BI, BDP } },
2702 { "bdzf", BBO(16,BODZF,0,0), BBOY_MASK, PPCCOM, { BI, BD } },
2703 { "bdzfl-", BBO(16,BODZF,0,1), BBOY_MASK, NOPOWER4, { BI, BDM } },
2704 { "bdzfl+", BBO(16,BODZF,0,1), BBOY_MASK, NOPOWER4, { BI, BDP } },
2705 { "bdzfl", BBO(16,BODZF,0,1), BBOY_MASK, PPCCOM, { BI, BD } },
2706 { "bdzfa-", BBO(16,BODZF,1,0), BBOY_MASK, NOPOWER4, { BI, BDMA } },
2707 { "bdzfa+", BBO(16,BODZF,1,0), BBOY_MASK, NOPOWER4, { BI, BDPA } },
2708 { "bdzfa", BBO(16,BODZF,1,0), BBOY_MASK, PPCCOM, { BI, BDA } },
2709 { "bdzfla-", BBO(16,BODZF,1,1), BBOY_MASK, NOPOWER4, { BI, BDMA } },
2710 { "bdzfla+", BBO(16,BODZF,1,1), BBOY_MASK, NOPOWER4, { BI, BDPA } },
2711 { "bdzfla", BBO(16,BODZF,1,1), BBOY_MASK, PPCCOM, { BI, BDA } },
2712 { "bc-", B(16,0,0), B_MASK, PPCCOM, { BOE, BI, BDM } },
2713 { "bc+", B(16,0,0), B_MASK, PPCCOM, { BOE, BI, BDP } },
2714 { "bc", B(16,0,0), B_MASK, COM, { BO, BI, BD } },
2715 { "bcl-", B(16,0,1), B_MASK, PPCCOM, { BOE, BI, BDM } },
2716 { "bcl+", B(16,0,1), B_MASK, PPCCOM, { BOE, BI, BDP } },
2717 { "bcl", B(16,0,1), B_MASK, COM, { BO, BI, BD } },
2718 { "bca-", B(16,1,0), B_MASK, PPCCOM, { BOE, BI, BDMA } },
2719 { "bca+", B(16,1,0), B_MASK, PPCCOM, { BOE, BI, BDPA } },
2720 { "bca", B(16,1,0), B_MASK, COM, { BO, BI, BDA } },
2721 { "bcla-", B(16,1,1), B_MASK, PPCCOM, { BOE, BI, BDMA } },
2722 { "bcla+", B(16,1,1), B_MASK, PPCCOM, { BOE, BI, BDPA } },
2723 { "bcla", B(16,1,1), B_MASK, COM, { BO, BI, BDA } },
2725 { "sc", SC(17,1,0), 0xffffffff, PPC, { 0 } },
2726 { "svc", SC(17,0,0), SC_MASK, POWER, { LEV, FL1, FL2 } },
2727 { "svcl", SC(17,0,1), SC_MASK, POWER, { LEV, FL1, FL2 } },
2728 { "svca", SC(17,1,0), SC_MASK, PWRCOM, { SV } },
2729 { "svcla", SC(17,1,1), SC_MASK, POWER, { SV } },
2731 { "b", B(18,0,0), B_MASK, COM, { LI } },
2732 { "bl", B(18,0,1), B_MASK, COM, { LI } },
2733 { "ba", B(18,1,0), B_MASK, COM, { LIA } },
2734 { "bla", B(18,1,1), B_MASK, COM, { LIA } },
2736 { "mcrf", XL(19,0), XLBB_MASK|(3 << 21)|(3 << 16), COM, { BF, BFA } },
2738 { "blr", XLO(19,BOU,16,0), XLBOBIBB_MASK, PPCCOM, { 0 } },
2739 { "br", XLO(19,BOU,16,0), XLBOBIBB_MASK, PWRCOM, { 0 } },
2740 { "blrl", XLO(19,BOU,16,1), XLBOBIBB_MASK, PPCCOM, { 0 } },
2741 { "brl", XLO(19,BOU,16,1), XLBOBIBB_MASK, PWRCOM, { 0 } },
2742 { "bdnzlr", XLO(19,BODNZ,16,0), XLBOBIBB_MASK, PPCCOM, { 0 } },
2743 { "bdnzlr-", XLO(19,BODNZ,16,0), XLBOBIBB_MASK, NOPOWER4, { 0 } },
2744 { "bdnzlr+", XLO(19,BODNZP,16,0), XLBOBIBB_MASK, NOPOWER4, { 0 } },
2745 { "bdnzlr-", XLO(19,BODNZM4,16,0), XLBOBIBB_MASK, POWER4, { 0 } },
2746 { "bdnzlr+", XLO(19,BODNZP4,16,0), XLBOBIBB_MASK, POWER4, { 0 } },
2747 { "bdnzlrl", XLO(19,BODNZ,16,1), XLBOBIBB_MASK, PPCCOM, { 0 } },
2748 { "bdnzlrl-",XLO(19,BODNZ,16,1), XLBOBIBB_MASK, NOPOWER4, { 0 } },
2749 { "bdnzlrl+",XLO(19,BODNZP,16,1), XLBOBIBB_MASK, NOPOWER4, { 0 } },
2750 { "bdnzlrl-",XLO(19,BODNZM4,16,1), XLBOBIBB_MASK, POWER4, { 0 } },
2751 { "bdnzlrl+",XLO(19,BODNZP4,16,1), XLBOBIBB_MASK, POWER4, { 0 } },
2752 { "bdzlr", XLO(19,BODZ,16,0), XLBOBIBB_MASK, PPCCOM, { 0 } },
2753 { "bdzlr-", XLO(19,BODZ,16,0), XLBOBIBB_MASK, NOPOWER4, { 0 } },
2754 { "bdzlr+", XLO(19,BODZP,16,0), XLBOBIBB_MASK, NOPOWER4, { 0 } },
2755 { "bdzlr-", XLO(19,BODZM4,16,0), XLBOBIBB_MASK, POWER4, { 0 } },
2756 { "bdzlr+", XLO(19,BODZP4,16,0), XLBOBIBB_MASK, POWER4, { 0 } },
2757 { "bdzlrl", XLO(19,BODZ,16,1), XLBOBIBB_MASK, PPCCOM, { 0 } },
2758 { "bdzlrl-", XLO(19,BODZ,16,1), XLBOBIBB_MASK, NOPOWER4, { 0 } },
2759 { "bdzlrl+", XLO(19,BODZP,16,1), XLBOBIBB_MASK, NOPOWER4, { 0 } },
2760 { "bdzlrl-", XLO(19,BODZM4,16,1), XLBOBIBB_MASK, POWER4, { 0 } },
2761 { "bdzlrl+", XLO(19,BODZP4,16,1), XLBOBIBB_MASK, POWER4, { 0 } },
2762 { "bltlr", XLOCB(19,BOT,CBLT,16,0), XLBOCBBB_MASK, PPCCOM, { CR } },
2763 { "bltlr-", XLOCB(19,BOT,CBLT,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2764 { "bltlr+", XLOCB(19,BOTP,CBLT,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2765 { "bltlr-", XLOCB(19,BOTM4,CBLT,16,0), XLBOCBBB_MASK, POWER4, { CR } },
2766 { "bltlr+", XLOCB(19,BOTP4,CBLT,16,0), XLBOCBBB_MASK, POWER4, { CR } },
2767 { "bltr", XLOCB(19,BOT,CBLT,16,0), XLBOCBBB_MASK, PWRCOM, { CR } },
2768 { "bltlrl", XLOCB(19,BOT,CBLT,16,1), XLBOCBBB_MASK, PPCCOM, { CR } },
2769 { "bltlrl-", XLOCB(19,BOT,CBLT,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2770 { "bltlrl+", XLOCB(19,BOTP,CBLT,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2771 { "bltlrl-", XLOCB(19,BOTM4,CBLT,16,1), XLBOCBBB_MASK, POWER4, { CR } },
2772 { "bltlrl+", XLOCB(19,BOTP4,CBLT,16,1), XLBOCBBB_MASK, POWER4, { CR } },
2773 { "bltrl", XLOCB(19,BOT,CBLT,16,1), XLBOCBBB_MASK, PWRCOM, { CR } },
2774 { "bgtlr", XLOCB(19,BOT,CBGT,16,0), XLBOCBBB_MASK, PPCCOM, { CR } },
2775 { "bgtlr-", XLOCB(19,BOT,CBGT,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2776 { "bgtlr+", XLOCB(19,BOTP,CBGT,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2777 { "bgtlr-", XLOCB(19,BOTM4,CBGT,16,0), XLBOCBBB_MASK, POWER4, { CR } },
2778 { "bgtlr+", XLOCB(19,BOTP4,CBGT,16,0), XLBOCBBB_MASK, POWER4, { CR } },
2779 { "bgtr", XLOCB(19,BOT,CBGT,16,0), XLBOCBBB_MASK, PWRCOM, { CR } },
2780 { "bgtlrl", XLOCB(19,BOT,CBGT,16,1), XLBOCBBB_MASK, PPCCOM, { CR } },
2781 { "bgtlrl-", XLOCB(19,BOT,CBGT,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2782 { "bgtlrl+", XLOCB(19,BOTP,CBGT,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2783 { "bgtlrl-", XLOCB(19,BOTM4,CBGT,16,1), XLBOCBBB_MASK, POWER4, { CR } },
2784 { "bgtlrl+", XLOCB(19,BOTP4,CBGT,16,1), XLBOCBBB_MASK, POWER4, { CR } },
2785 { "bgtrl", XLOCB(19,BOT,CBGT,16,1), XLBOCBBB_MASK, PWRCOM, { CR } },
2786 { "beqlr", XLOCB(19,BOT,CBEQ,16,0), XLBOCBBB_MASK, PPCCOM, { CR } },
2787 { "beqlr-", XLOCB(19,BOT,CBEQ,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2788 { "beqlr+", XLOCB(19,BOTP,CBEQ,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2789 { "beqlr-", XLOCB(19,BOTM4,CBEQ,16,0), XLBOCBBB_MASK, POWER4, { CR } },
2790 { "beqlr+", XLOCB(19,BOTP4,CBEQ,16,0), XLBOCBBB_MASK, POWER4, { CR } },
2791 { "beqr", XLOCB(19,BOT,CBEQ,16,0), XLBOCBBB_MASK, PWRCOM, { CR } },
2792 { "beqlrl", XLOCB(19,BOT,CBEQ,16,1), XLBOCBBB_MASK, PPCCOM, { CR } },
2793 { "beqlrl-", XLOCB(19,BOT,CBEQ,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2794 { "beqlrl+", XLOCB(19,BOTP,CBEQ,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2795 { "beqlrl-", XLOCB(19,BOTM4,CBEQ,16,1), XLBOCBBB_MASK, POWER4, { CR } },
2796 { "beqlrl+", XLOCB(19,BOTP4,CBEQ,16,1), XLBOCBBB_MASK, POWER4, { CR } },
2797 { "beqrl", XLOCB(19,BOT,CBEQ,16,1), XLBOCBBB_MASK, PWRCOM, { CR } },
2798 { "bsolr", XLOCB(19,BOT,CBSO,16,0), XLBOCBBB_MASK, PPCCOM, { CR } },
2799 { "bsolr-", XLOCB(19,BOT,CBSO,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2800 { "bsolr+", XLOCB(19,BOTP,CBSO,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2801 { "bsolr-", XLOCB(19,BOTM4,CBSO,16,0), XLBOCBBB_MASK, POWER4, { CR } },
2802 { "bsolr+", XLOCB(19,BOTP4,CBSO,16,0), XLBOCBBB_MASK, POWER4, { CR } },
2803 { "bsor", XLOCB(19,BOT,CBSO,16,0), XLBOCBBB_MASK, PWRCOM, { CR } },
2804 { "bsolrl", XLOCB(19,BOT,CBSO,16,1), XLBOCBBB_MASK, PPCCOM, { CR } },
2805 { "bsolrl-", XLOCB(19,BOT,CBSO,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2806 { "bsolrl+", XLOCB(19,BOTP,CBSO,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2807 { "bsolrl-", XLOCB(19,BOTM4,CBSO,16,1), XLBOCBBB_MASK, POWER4, { CR } },
2808 { "bsolrl+", XLOCB(19,BOTP4,CBSO,16,1), XLBOCBBB_MASK, POWER4, { CR } },
2809 { "bsorl", XLOCB(19,BOT,CBSO,16,1), XLBOCBBB_MASK, PWRCOM, { CR } },
2810 { "bunlr", XLOCB(19,BOT,CBSO,16,0), XLBOCBBB_MASK, PPCCOM, { CR } },
2811 { "bunlr-", XLOCB(19,BOT,CBSO,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2812 { "bunlr+", XLOCB(19,BOTP,CBSO,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2813 { "bunlr-", XLOCB(19,BOTM4,CBSO,16,0), XLBOCBBB_MASK, POWER4, { CR } },
2814 { "bunlr+", XLOCB(19,BOTP4,CBSO,16,0), XLBOCBBB_MASK, POWER4, { CR } },
2815 { "bunlrl", XLOCB(19,BOT,CBSO,16,1), XLBOCBBB_MASK, PPCCOM, { CR } },
2816 { "bunlrl-", XLOCB(19,BOT,CBSO,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2817 { "bunlrl+", XLOCB(19,BOTP,CBSO,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2818 { "bunlrl-", XLOCB(19,BOTM4,CBSO,16,1), XLBOCBBB_MASK, POWER4, { CR } },
2819 { "bunlrl+", XLOCB(19,BOTP4,CBSO,16,1), XLBOCBBB_MASK, POWER4, { CR } },
2820 { "bgelr", XLOCB(19,BOF,CBLT,16,0), XLBOCBBB_MASK, PPCCOM, { CR } },
2821 { "bgelr-", XLOCB(19,BOF,CBLT,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2822 { "bgelr+", XLOCB(19,BOFP,CBLT,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2823 { "bgelr-", XLOCB(19,BOFM4,CBLT,16,0), XLBOCBBB_MASK, POWER4, { CR } },
2824 { "bgelr+", XLOCB(19,BOFP4,CBLT,16,0), XLBOCBBB_MASK, POWER4, { CR } },
2825 { "bger", XLOCB(19,BOF,CBLT,16,0), XLBOCBBB_MASK, PWRCOM, { CR } },
2826 { "bgelrl", XLOCB(19,BOF,CBLT,16,1), XLBOCBBB_MASK, PPCCOM, { CR } },
2827 { "bgelrl-", XLOCB(19,BOF,CBLT,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2828 { "bgelrl+", XLOCB(19,BOFP,CBLT,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2829 { "bgelrl-", XLOCB(19,BOFM4,CBLT,16,1), XLBOCBBB_MASK, POWER4, { CR } },
2830 { "bgelrl+", XLOCB(19,BOFP4,CBLT,16,1), XLBOCBBB_MASK, POWER4, { CR } },
2831 { "bgerl", XLOCB(19,BOF,CBLT,16,1), XLBOCBBB_MASK, PWRCOM, { CR } },
2832 { "bnllr", XLOCB(19,BOF,CBLT,16,0), XLBOCBBB_MASK, PPCCOM, { CR } },
2833 { "bnllr-", XLOCB(19,BOF,CBLT,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2834 { "bnllr+", XLOCB(19,BOFP,CBLT,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2835 { "bnllr-", XLOCB(19,BOFM4,CBLT,16,0), XLBOCBBB_MASK, POWER4, { CR } },
2836 { "bnllr+", XLOCB(19,BOFP4,CBLT,16,0), XLBOCBBB_MASK, POWER4, { CR } },
2837 { "bnlr", XLOCB(19,BOF,CBLT,16,0), XLBOCBBB_MASK, PWRCOM, { CR } },
2838 { "bnllrl", XLOCB(19,BOF,CBLT,16,1), XLBOCBBB_MASK, PPCCOM, { CR } },
2839 { "bnllrl-", XLOCB(19,BOF,CBLT,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2840 { "bnllrl+", XLOCB(19,BOFP,CBLT,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2841 { "bnllrl-", XLOCB(19,BOFM4,CBLT,16,1), XLBOCBBB_MASK, POWER4, { CR } },
2842 { "bnllrl+", XLOCB(19,BOFP4,CBLT,16,1), XLBOCBBB_MASK, POWER4, { CR } },
2843 { "bnlrl", XLOCB(19,BOF,CBLT,16,1), XLBOCBBB_MASK, PWRCOM, { CR } },
2844 { "blelr", XLOCB(19,BOF,CBGT,16,0), XLBOCBBB_MASK, PPCCOM, { CR } },
2845 { "blelr-", XLOCB(19,BOF,CBGT,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2846 { "blelr+", XLOCB(19,BOFP,CBGT,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2847 { "blelr-", XLOCB(19,BOFM4,CBGT,16,0), XLBOCBBB_MASK, POWER4, { CR } },
2848 { "blelr+", XLOCB(19,BOFP4,CBGT,16,0), XLBOCBBB_MASK, POWER4, { CR } },
2849 { "bler", XLOCB(19,BOF,CBGT,16,0), XLBOCBBB_MASK, PWRCOM, { CR } },
2850 { "blelrl", XLOCB(19,BOF,CBGT,16,1), XLBOCBBB_MASK, PPCCOM, { CR } },
2851 { "blelrl-", XLOCB(19,BOF,CBGT,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2852 { "blelrl+", XLOCB(19,BOFP,CBGT,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2853 { "blelrl-", XLOCB(19,BOFM4,CBGT,16,1), XLBOCBBB_MASK, POWER4, { CR } },
2854 { "blelrl+", XLOCB(19,BOFP4,CBGT,16,1), XLBOCBBB_MASK, POWER4, { CR } },
2855 { "blerl", XLOCB(19,BOF,CBGT,16,1), XLBOCBBB_MASK, PWRCOM, { CR } },
2856 { "bnglr", XLOCB(19,BOF,CBGT,16,0), XLBOCBBB_MASK, PPCCOM, { CR } },
2857 { "bnglr-", XLOCB(19,BOF,CBGT,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2858 { "bnglr+", XLOCB(19,BOFP,CBGT,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2859 { "bnglr-", XLOCB(19,BOFM4,CBGT,16,0), XLBOCBBB_MASK, POWER4, { CR } },
2860 { "bnglr+", XLOCB(19,BOFP4,CBGT,16,0), XLBOCBBB_MASK, POWER4, { CR } },
2861 { "bngr", XLOCB(19,BOF,CBGT,16,0), XLBOCBBB_MASK, PWRCOM, { CR } },
2862 { "bnglrl", XLOCB(19,BOF,CBGT,16,1), XLBOCBBB_MASK, PPCCOM, { CR } },
2863 { "bnglrl-", XLOCB(19,BOF,CBGT,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2864 { "bnglrl+", XLOCB(19,BOFP,CBGT,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2865 { "bnglrl-", XLOCB(19,BOFM4,CBGT,16,1), XLBOCBBB_MASK, POWER4, { CR } },
2866 { "bnglrl+", XLOCB(19,BOFP4,CBGT,16,1), XLBOCBBB_MASK, POWER4, { CR } },
2867 { "bngrl", XLOCB(19,BOF,CBGT,16,1), XLBOCBBB_MASK, PWRCOM, { CR } },
2868 { "bnelr", XLOCB(19,BOF,CBEQ,16,0), XLBOCBBB_MASK, PPCCOM, { CR } },
2869 { "bnelr-", XLOCB(19,BOF,CBEQ,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2870 { "bnelr+", XLOCB(19,BOFP,CBEQ,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2871 { "bnelr-", XLOCB(19,BOFM4,CBEQ,16,0), XLBOCBBB_MASK, POWER4, { CR } },
2872 { "bnelr+", XLOCB(19,BOFP4,CBEQ,16,0), XLBOCBBB_MASK, POWER4, { CR } },
2873 { "bner", XLOCB(19,BOF,CBEQ,16,0), XLBOCBBB_MASK, PWRCOM, { CR } },
2874 { "bnelrl", XLOCB(19,BOF,CBEQ,16,1), XLBOCBBB_MASK, PPCCOM, { CR } },
2875 { "bnelrl-", XLOCB(19,BOF,CBEQ,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2876 { "bnelrl+", XLOCB(19,BOFP,CBEQ,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2877 { "bnelrl-", XLOCB(19,BOFM4,CBEQ,16,1), XLBOCBBB_MASK, POWER4, { CR } },
2878 { "bnelrl+", XLOCB(19,BOFP4,CBEQ,16,1), XLBOCBBB_MASK, POWER4, { CR } },
2879 { "bnerl", XLOCB(19,BOF,CBEQ,16,1), XLBOCBBB_MASK, PWRCOM, { CR } },
2880 { "bnslr", XLOCB(19,BOF,CBSO,16,0), XLBOCBBB_MASK, PPCCOM, { CR } },
2881 { "bnslr-", XLOCB(19,BOF,CBSO,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2882 { "bnslr+", XLOCB(19,BOFP,CBSO,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2883 { "bnslr-", XLOCB(19,BOFM4,CBSO,16,0), XLBOCBBB_MASK, POWER4, { CR } },
2884 { "bnslr+", XLOCB(19,BOFP4,CBSO,16,0), XLBOCBBB_MASK, POWER4, { CR } },
2885 { "bnsr", XLOCB(19,BOF,CBSO,16,0), XLBOCBBB_MASK, PWRCOM, { CR } },
2886 { "bnslrl", XLOCB(19,BOF,CBSO,16,1), XLBOCBBB_MASK, PPCCOM, { CR } },
2887 { "bnslrl-", XLOCB(19,BOF,CBSO,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2888 { "bnslrl+", XLOCB(19,BOFP,CBSO,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2889 { "bnslrl-", XLOCB(19,BOFM4,CBSO,16,1), XLBOCBBB_MASK, POWER4, { CR } },
2890 { "bnslrl+", XLOCB(19,BOFP4,CBSO,16,1), XLBOCBBB_MASK, POWER4, { CR } },
2891 { "bnsrl", XLOCB(19,BOF,CBSO,16,1), XLBOCBBB_MASK, PWRCOM, { CR } },
2892 { "bnulr", XLOCB(19,BOF,CBSO,16,0), XLBOCBBB_MASK, PPCCOM, { CR } },
2893 { "bnulr-", XLOCB(19,BOF,CBSO,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2894 { "bnulr+", XLOCB(19,BOFP,CBSO,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2895 { "bnulr-", XLOCB(19,BOFM4,CBSO,16,0), XLBOCBBB_MASK, POWER4, { CR } },
2896 { "bnulr+", XLOCB(19,BOFP4,CBSO,16,0), XLBOCBBB_MASK, POWER4, { CR } },
2897 { "bnulrl", XLOCB(19,BOF,CBSO,16,1), XLBOCBBB_MASK, PPCCOM, { CR } },
2898 { "bnulrl-", XLOCB(19,BOF,CBSO,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2899 { "bnulrl+", XLOCB(19,BOFP,CBSO,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2900 { "bnulrl-", XLOCB(19,BOFM4,CBSO,16,1), XLBOCBBB_MASK, POWER4, { CR } },
2901 { "bnulrl+", XLOCB(19,BOFP4,CBSO,16,1), XLBOCBBB_MASK, POWER4, { CR } },
2902 { "btlr", XLO(19,BOT,16,0), XLBOBB_MASK, PPCCOM, { BI } },
2903 { "btlr-", XLO(19,BOT,16,0), XLBOBB_MASK, NOPOWER4, { BI } },
2904 { "btlr+", XLO(19,BOTP,16,0), XLBOBB_MASK, NOPOWER4, { BI } },
2905 { "btlr-", XLO(19,BOTM4,16,0), XLBOBB_MASK, POWER4, { BI } },
2906 { "btlr+", XLO(19,BOTP4,16,0), XLBOBB_MASK, POWER4, { BI } },
2907 { "bbtr", XLO(19,BOT,16,0), XLBOBB_MASK, PWRCOM, { BI } },
2908 { "btlrl", XLO(19,BOT,16,1), XLBOBB_MASK, PPCCOM, { BI } },
2909 { "btlrl-", XLO(19,BOT,16,1), XLBOBB_MASK, NOPOWER4, { BI } },
2910 { "btlrl+", XLO(19,BOTP,16,1), XLBOBB_MASK, NOPOWER4, { BI } },
2911 { "btlrl-", XLO(19,BOTM4,16,1), XLBOBB_MASK, POWER4, { BI } },
2912 { "btlrl+", XLO(19,BOTP4,16,1), XLBOBB_MASK, POWER4, { BI } },
2913 { "bbtrl", XLO(19,BOT,16,1), XLBOBB_MASK, PWRCOM, { BI } },
2914 { "bflr", XLO(19,BOF,16,0), XLBOBB_MASK, PPCCOM, { BI } },
2915 { "bflr-", XLO(19,BOF,16,0), XLBOBB_MASK, NOPOWER4, { BI } },
2916 { "bflr+", XLO(19,BOFP,16,0), XLBOBB_MASK, NOPOWER4, { BI } },
2917 { "bflr-", XLO(19,BOFM4,16,0), XLBOBB_MASK, POWER4, { BI } },
2918 { "bflr+", XLO(19,BOFP4,16,0), XLBOBB_MASK, POWER4, { BI } },
2919 { "bbfr", XLO(19,BOF,16,0), XLBOBB_MASK, PWRCOM, { BI } },
2920 { "bflrl", XLO(19,BOF,16,1), XLBOBB_MASK, PPCCOM, { BI } },
2921 { "bflrl-", XLO(19,BOF,16,1), XLBOBB_MASK, NOPOWER4, { BI } },
2922 { "bflrl+", XLO(19,BOFP,16,1), XLBOBB_MASK, NOPOWER4, { BI } },
2923 { "bflrl-", XLO(19,BOFM4,16,1), XLBOBB_MASK, POWER4, { BI } },
2924 { "bflrl+", XLO(19,BOFP4,16,1), XLBOBB_MASK, POWER4, { BI } },
2925 { "bbfrl", XLO(19,BOF,16,1), XLBOBB_MASK, PWRCOM, { BI } },
2926 { "bdnztlr", XLO(19,BODNZT,16,0), XLBOBB_MASK, PPCCOM, { BI } },
2927 { "bdnztlr-",XLO(19,BODNZT,16,0), XLBOBB_MASK, NOPOWER4, { BI } },
2928 { "bdnztlr+",XLO(19,BODNZTP,16,0), XLBOBB_MASK, NOPOWER4, { BI } },
2929 { "bdnztlrl",XLO(19,BODNZT,16,1), XLBOBB_MASK, PPCCOM, { BI } },
2930 { "bdnztlrl-",XLO(19,BODNZT,16,1), XLBOBB_MASK, NOPOWER4, { BI } },
2931 { "bdnztlrl+",XLO(19,BODNZTP,16,1), XLBOBB_MASK, NOPOWER4, { BI } },
2932 { "bdnzflr", XLO(19,BODNZF,16,0), XLBOBB_MASK, PPCCOM, { BI } },
2933 { "bdnzflr-",XLO(19,BODNZF,16,0), XLBOBB_MASK, NOPOWER4, { BI } },
2934 { "bdnzflr+",XLO(19,BODNZFP,16,0), XLBOBB_MASK, NOPOWER4, { BI } },
2935 { "bdnzflrl",XLO(19,BODNZF,16,1), XLBOBB_MASK, PPCCOM, { BI } },
2936 { "bdnzflrl-",XLO(19,BODNZF,16,1), XLBOBB_MASK, NOPOWER4, { BI } },
2937 { "bdnzflrl+",XLO(19,BODNZFP,16,1), XLBOBB_MASK, NOPOWER4, { BI } },
2938 { "bdztlr", XLO(19,BODZT,16,0), XLBOBB_MASK, PPCCOM, { BI } },
2939 { "bdztlr-", XLO(19,BODZT,16,0), XLBOBB_MASK, NOPOWER4, { BI } },
2940 { "bdztlr+", XLO(19,BODZTP,16,0), XLBOBB_MASK, NOPOWER4, { BI } },
2941 { "bdztlrl", XLO(19,BODZT,16,1), XLBOBB_MASK, PPCCOM, { BI } },
2942 { "bdztlrl-",XLO(19,BODZT,16,1), XLBOBB_MASK, NOPOWER4, { BI } },
2943 { "bdztlrl+",XLO(19,BODZTP,16,1), XLBOBB_MASK, NOPOWER4, { BI } },
2944 { "bdzflr", XLO(19,BODZF,16,0), XLBOBB_MASK, PPCCOM, { BI } },
2945 { "bdzflr-", XLO(19,BODZF,16,0), XLBOBB_MASK, NOPOWER4, { BI } },
2946 { "bdzflr+", XLO(19,BODZFP,16,0), XLBOBB_MASK, NOPOWER4, { BI } },
2947 { "bdzflrl", XLO(19,BODZF,16,1), XLBOBB_MASK, PPCCOM, { BI } },
2948 { "bdzflrl-",XLO(19,BODZF,16,1), XLBOBB_MASK, NOPOWER4, { BI } },
2949 { "bdzflrl+",XLO(19,BODZFP,16,1), XLBOBB_MASK, NOPOWER4, { BI } },
2950 { "bclr", XLLK(19,16,0), XLYBB_MASK, PPCCOM, { BO, BI } },
2951 { "bclrl", XLLK(19,16,1), XLYBB_MASK, PPCCOM, { BO, BI } },
2952 { "bclr+", XLYLK(19,16,1,0), XLYBB_MASK, PPCCOM, { BOE, BI } },
2953 { "bclrl+", XLYLK(19,16,1,1), XLYBB_MASK, PPCCOM, { BOE, BI } },
2954 { "bclr-", XLYLK(19,16,0,0), XLYBB_MASK, PPCCOM, { BOE, BI } },
2955 { "bclrl-", XLYLK(19,16,0,1), XLYBB_MASK, PPCCOM, { BOE, BI } },
2956 { "bcr", XLLK(19,16,0), XLBB_MASK, PWRCOM, { BO, BI } },
2957 { "bcrl", XLLK(19,16,1), XLBB_MASK, PWRCOM, { BO, BI } },
2958 { "bclre", XLLK(19,17,0), XLBB_MASK, BOOKE64, { BO, BI } },
2959 { "bclrel", XLLK(19,17,1), XLBB_MASK, BOOKE64, { BO, BI } },
2961 { "rfid", XL(19,18), 0xffffffff, PPC64, { 0 } },
2963 { "crnot", XL(19,33), XL_MASK, PPCCOM, { BT, BA, BBA } },
2964 { "crnor", XL(19,33), XL_MASK, COM, { BT, BA, BB } },
2965 { "rfmci", X(19,38), 0xffffffff, PPCRFMCI, { 0 } },
2967 { "rfi", XL(19,50), 0xffffffff, COM, { 0 } },
2968 { "rfci", XL(19,51), 0xffffffff, PPC403, { 0 } },
2969 { "rfci", XL(19,51), 0xffffffff, BOOKE, { 0 } },
2971 { "rfsvc", XL(19,82), 0xffffffff, POWER, { 0 } },
2973 { "crandc", XL(19,129), XL_MASK, COM, { BT, BA, BB } },
2975 { "isync", XL(19,150), 0xffffffff, PPCCOM, { 0 } },
2976 { "ics", XL(19,150), 0xffffffff, PWRCOM, { 0 } },
2978 { "crclr", XL(19,193), XL_MASK, PPCCOM, { BT, BAT, BBA } },
2979 { "crxor", XL(19,193), XL_MASK, COM, { BT, BA, BB } },
2981 { "crnand", XL(19,225), XL_MASK, COM, { BT, BA, BB } },
2983 { "crand", XL(19,257), XL_MASK, COM, { BT, BA, BB } },
2985 { "crset", XL(19,289), XL_MASK, PPCCOM, { BT, BAT, BBA } },
2986 { "creqv", XL(19,289), XL_MASK, COM, { BT, BA, BB } },
2988 { "crorc", XL(19,417), XL_MASK, COM, { BT, BA, BB } },
2990 { "crmove", XL(19,449), XL_MASK, PPCCOM, { BT, BA, BBA } },
2991 { "cror", XL(19,449), XL_MASK, COM, { BT, BA, BB } },
2993 { "bctr", XLO(19,BOU,528,0), XLBOBIBB_MASK, COM, { 0 } },
2994 { "bctrl", XLO(19,BOU,528,1), XLBOBIBB_MASK, COM, { 0 } },
2995 { "bltctr", XLOCB(19,BOT,CBLT,528,0), XLBOCBBB_MASK, PPCCOM, { CR } },
2996 { "bltctr-", XLOCB(19,BOT,CBLT,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2997 { "bltctr+", XLOCB(19,BOTP,CBLT,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2998 { "bltctr-", XLOCB(19,BOTM4,CBLT,528,0), XLBOCBBB_MASK, POWER4, { CR } },
2999 { "bltctr+", XLOCB(19,BOTP4,CBLT,528,0), XLBOCBBB_MASK, POWER4, { CR } },
3000 { "bltctrl", XLOCB(19,BOT,CBLT,528,1), XLBOCBBB_MASK, PPCCOM, { CR } },
3001 { "bltctrl-",XLOCB(19,BOT,CBLT,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
3002 { "bltctrl+",XLOCB(19,BOTP,CBLT,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
3003 { "bltctrl-",XLOCB(19,BOTM4,CBLT,528,1), XLBOCBBB_MASK, POWER4, { CR } },
3004 { "bltctrl+",XLOCB(19,BOTP4,CBLT,528,1), XLBOCBBB_MASK, POWER4, { CR } },
3005 { "bgtctr", XLOCB(19,BOT,CBGT,528,0), XLBOCBBB_MASK, PPCCOM, { CR } },
3006 { "bgtctr-", XLOCB(19,BOT,CBGT,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
3007 { "bgtctr+", XLOCB(19,BOTP,CBGT,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
3008 { "bgtctr-", XLOCB(19,BOTM4,CBGT,528,0), XLBOCBBB_MASK, POWER4, { CR } },
3009 { "bgtctr+", XLOCB(19,BOTP4,CBGT,528,0), XLBOCBBB_MASK, POWER4, { CR } },
3010 { "bgtctrl", XLOCB(19,BOT,CBGT,528,1), XLBOCBBB_MASK, PPCCOM, { CR } },
3011 { "bgtctrl-",XLOCB(19,BOT,CBGT,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
3012 { "bgtctrl+",XLOCB(19,BOTP,CBGT,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
3013 { "bgtctrl-",XLOCB(19,BOTM4,CBGT,528,1), XLBOCBBB_MASK, POWER4, { CR } },
3014 { "bgtctrl+",XLOCB(19,BOTP4,CBGT,528,1), XLBOCBBB_MASK, POWER4, { CR } },
3015 { "beqctr", XLOCB(19,BOT,CBEQ,528,0), XLBOCBBB_MASK, PPCCOM, { CR } },
3016 { "beqctr-", XLOCB(19,BOT,CBEQ,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
3017 { "beqctr+", XLOCB(19,BOTP,CBEQ,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
3018 { "beqctr-", XLOCB(19,BOTM4,CBEQ,528,0), XLBOCBBB_MASK, POWER4, { CR } },
3019 { "beqctr+", XLOCB(19,BOTP4,CBEQ,528,0), XLBOCBBB_MASK, POWER4, { CR } },
3020 { "beqctrl", XLOCB(19,BOT,CBEQ,528,1), XLBOCBBB_MASK, PPCCOM, { CR } },
3021 { "beqctrl-",XLOCB(19,BOT,CBEQ,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
3022 { "beqctrl+",XLOCB(19,BOTP,CBEQ,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
3023 { "beqctrl-",XLOCB(19,BOTM4,CBEQ,528,1), XLBOCBBB_MASK, POWER4, { CR } },
3024 { "beqctrl+",XLOCB(19,BOTP4,CBEQ,528,1), XLBOCBBB_MASK, POWER4, { CR } },
3025 { "bsoctr", XLOCB(19,BOT,CBSO,528,0), XLBOCBBB_MASK, PPCCOM, { CR } },
3026 { "bsoctr-", XLOCB(19,BOT,CBSO,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
3027 { "bsoctr+", XLOCB(19,BOTP,CBSO,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
3028 { "bsoctr-", XLOCB(19,BOTM4,CBSO,528,0), XLBOCBBB_MASK, POWER4, { CR } },
3029 { "bsoctr+", XLOCB(19,BOTP4,CBSO,528,0), XLBOCBBB_MASK, POWER4, { CR } },
3030 { "bsoctrl", XLOCB(19,BOT,CBSO,528,1), XLBOCBBB_MASK, PPCCOM, { CR } },
3031 { "bsoctrl-",XLOCB(19,BOT,CBSO,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
3032 { "bsoctrl+",XLOCB(19,BOTP,CBSO,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
3033 { "bsoctrl-",XLOCB(19,BOTM4,CBSO,528,1), XLBOCBBB_MASK, POWER4, { CR } },
3034 { "bsoctrl+",XLOCB(19,BOTP4,CBSO,528,1), XLBOCBBB_MASK, POWER4, { CR } },
3035 { "bunctr", XLOCB(19,BOT,CBSO,528,0), XLBOCBBB_MASK, PPCCOM, { CR } },
3036 { "bunctr-", XLOCB(19,BOT,CBSO,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
3037 { "bunctr+", XLOCB(19,BOTP,CBSO,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
3038 { "bunctr-", XLOCB(19,BOTM4,CBSO,528,0), XLBOCBBB_MASK, POWER4, { CR } },
3039 { "bunctr+", XLOCB(19,BOTP4,CBSO,528,0), XLBOCBBB_MASK, POWER4, { CR } },
3040 { "bunctrl", XLOCB(19,BOT,CBSO,528,1), XLBOCBBB_MASK, PPCCOM, { CR } },
3041 { "bunctrl-",XLOCB(19,BOT,CBSO,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
3042 { "bunctrl+",XLOCB(19,BOTP,CBSO,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
3043 { "bunctrl-",XLOCB(19,BOTM4,CBSO,528,1), XLBOCBBB_MASK, POWER4, { CR } },
3044 { "bunctrl+",XLOCB(19,BOTP4,CBSO,528,1), XLBOCBBB_MASK, POWER4, { CR } },
3045 { "bgectr", XLOCB(19,BOF,CBLT,528,0), XLBOCBBB_MASK, PPCCOM, { CR } },
3046 { "bgectr-", XLOCB(19,BOF,CBLT,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
3047 { "bgectr+", XLOCB(19,BOFP,CBLT,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
3048 { "bgectr-", XLOCB(19,BOFM4,CBLT,528,0), XLBOCBBB_MASK, POWER4, { CR } },
3049 { "bgectr+", XLOCB(19,BOFP4,CBLT,528,0), XLBOCBBB_MASK, POWER4, { CR } },
3050 { "bgectrl", XLOCB(19,BOF,CBLT,528,1), XLBOCBBB_MASK, PPCCOM, { CR } },
3051 { "bgectrl-",XLOCB(19,BOF,CBLT,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
3052 { "bgectrl+",XLOCB(19,BOFP,CBLT,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
3053 { "bgectrl-",XLOCB(19,BOFM4,CBLT,528,1), XLBOCBBB_MASK, POWER4, { CR } },
3054 { "bgectrl+",XLOCB(19,BOFP4,CBLT,528,1), XLBOCBBB_MASK, POWER4, { CR } },
3055 { "bnlctr", XLOCB(19,BOF,CBLT,528,0), XLBOCBBB_MASK, PPCCOM, { CR } },
3056 { "bnlctr-", XLOCB(19,BOF,CBLT,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
3057 { "bnlctr+", XLOCB(19,BOFP,CBLT,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
3058 { "bnlctr-", XLOCB(19,BOFM4,CBLT,528,0), XLBOCBBB_MASK, POWER4, { CR } },
3059 { "bnlctr+", XLOCB(19,BOFP4,CBLT,528,0), XLBOCBBB_MASK, POWER4, { CR } },
3060 { "bnlctrl", XLOCB(19,BOF,CBLT,528,1), XLBOCBBB_MASK, PPCCOM, { CR } },
3061 { "bnlctrl-",XLOCB(19,BOF,CBLT,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
3062 { "bnlctrl+",XLOCB(19,BOFP,CBLT,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
3063 { "bnlctrl-",XLOCB(19,BOFM4,CBLT,528,1), XLBOCBBB_MASK, POWER4, { CR } },
3064 { "bnlctrl+",XLOCB(19,BOFP4,CBLT,528,1), XLBOCBBB_MASK, POWER4, { CR } },
3065 { "blectr", XLOCB(19,BOF,CBGT,528,0), XLBOCBBB_MASK, PPCCOM, { CR } },
3066 { "blectr-", XLOCB(19,BOF,CBGT,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
3067 { "blectr+", XLOCB(19,BOFP,CBGT,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
3068 { "blectr-", XLOCB(19,BOFM4,CBGT,528,0), XLBOCBBB_MASK, POWER4, { CR } },
3069 { "blectr+", XLOCB(19,BOFP4,CBGT,528,0), XLBOCBBB_MASK, POWER4, { CR } },
3070 { "blectrl", XLOCB(19,BOF,CBGT,528,1), XLBOCBBB_MASK, PPCCOM, { CR } },
3071 { "blectrl-",XLOCB(19,BOF,CBGT,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
3072 { "blectrl+",XLOCB(19,BOFP,CBGT,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
3073 { "blectrl-",XLOCB(19,BOFM4,CBGT,528,1), XLBOCBBB_MASK, POWER4, { CR } },
3074 { "blectrl+",XLOCB(19,BOFP4,CBGT,528,1), XLBOCBBB_MASK, POWER4, { CR } },
3075 { "bngctr", XLOCB(19,BOF,CBGT,528,0), XLBOCBBB_MASK, PPCCOM, { CR } },
3076 { "bngctr-", XLOCB(19,BOF,CBGT,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
3077 { "bngctr+", XLOCB(19,BOFP,CBGT,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
3078 { "bngctr-", XLOCB(19,BOFM4,CBGT,528,0), XLBOCBBB_MASK, POWER4, { CR } },
3079 { "bngctr+", XLOCB(19,BOFP4,CBGT,528,0), XLBOCBBB_MASK, POWER4, { CR } },
3080 { "bngctrl", XLOCB(19,BOF,CBGT,528,1), XLBOCBBB_MASK, PPCCOM, { CR } },
3081 { "bngctrl-",XLOCB(19,BOF,CBGT,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
3082 { "bngctrl+",XLOCB(19,BOFP,CBGT,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
3083 { "bngctrl-",XLOCB(19,BOFM4,CBGT,528,1), XLBOCBBB_MASK, POWER4, { CR } },
3084 { "bngctrl+",XLOCB(19,BOFP4,CBGT,528,1), XLBOCBBB_MASK, POWER4, { CR } },
3085 { "bnectr", XLOCB(19,BOF,CBEQ,528,0), XLBOCBBB_MASK, PPCCOM, { CR } },
3086 { "bnectr-", XLOCB(19,BOF,CBEQ,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
3087 { "bnectr+", XLOCB(19,BOFP,CBEQ,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
3088 { "bnectr-", XLOCB(19,BOFM4,CBEQ,528,0), XLBOCBBB_MASK, POWER4, { CR } },
3089 { "bnectr+", XLOCB(19,BOFP4,CBEQ,528,0), XLBOCBBB_MASK, POWER4, { CR } },
3090 { "bnectrl", XLOCB(19,BOF,CBEQ,528,1), XLBOCBBB_MASK, PPCCOM, { CR } },
3091 { "bnectrl-",XLOCB(19,BOF,CBEQ,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
3092 { "bnectrl+",XLOCB(19,BOFP,CBEQ,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
3093 { "bnectrl-",XLOCB(19,BOFM4,CBEQ,528,1), XLBOCBBB_MASK, POWER4, { CR } },
3094 { "bnectrl+",XLOCB(19,BOFP4,CBEQ,528,1), XLBOCBBB_MASK, POWER4, { CR } },
3095 { "bnsctr", XLOCB(19,BOF,CBSO,528,0), XLBOCBBB_MASK, PPCCOM, { CR } },
3096 { "bnsctr-", XLOCB(19,BOF,CBSO,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
3097 { "bnsctr+", XLOCB(19,BOFP,CBSO,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
3098 { "bnsctr-", XLOCB(19,BOFM4,CBSO,528,0), XLBOCBBB_MASK, POWER4, { CR } },
3099 { "bnsctr+", XLOCB(19,BOFP4,CBSO,528,0), XLBOCBBB_MASK, POWER4, { CR } },
3100 { "bnsctrl", XLOCB(19,BOF,CBSO,528,1), XLBOCBBB_MASK, PPCCOM, { CR } },
3101 { "bnsctrl-",XLOCB(19,BOF,CBSO,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
3102 { "bnsctrl+",XLOCB(19,BOFP,CBSO,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
3103 { "bnsctrl-",XLOCB(19,BOFM4,CBSO,528,1), XLBOCBBB_MASK, POWER4, { CR } },
3104 { "bnsctrl+",XLOCB(19,BOFP4,CBSO,528,1), XLBOCBBB_MASK, POWER4, { CR } },
3105 { "bnuctr", XLOCB(19,BOF,CBSO,528,0), XLBOCBBB_MASK, PPCCOM, { CR } },
3106 { "bnuctr-", XLOCB(19,BOF,CBSO,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
3107 { "bnuctr+", XLOCB(19,BOFP,CBSO,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
3108 { "bnuctr-", XLOCB(19,BOFM4,CBSO,528,0), XLBOCBBB_MASK, POWER4, { CR } },
3109 { "bnuctr+", XLOCB(19,BOFP4,CBSO,528,0), XLBOCBBB_MASK, POWER4, { CR } },
3110 { "bnuctrl", XLOCB(19,BOF,CBSO,528,1), XLBOCBBB_MASK, PPCCOM, { CR } },
3111 { "bnuctrl-",XLOCB(19,BOF,CBSO,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
3112 { "bnuctrl+",XLOCB(19,BOFP,CBSO,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
3113 { "bnuctrl-",XLOCB(19,BOFM4,CBSO,528,1), XLBOCBBB_MASK, POWER4, { CR } },
3114 { "bnuctrl+",XLOCB(19,BOFP4,CBSO,528,1), XLBOCBBB_MASK, POWER4, { CR } },
3115 { "btctr", XLO(19,BOT,528,0), XLBOBB_MASK, PPCCOM, { BI } },
3116 { "btctr-", XLO(19,BOT,528,0), XLBOBB_MASK, NOPOWER4, { BI } },
3117 { "btctr+", XLO(19,BOTP,528,0), XLBOBB_MASK, NOPOWER4, { BI } },
3118 { "btctr-", XLO(19,BOTM4,528,0), XLBOBB_MASK, POWER4, { BI } },
3119 { "btctr+", XLO(19,BOTP4,528,0), XLBOBB_MASK, POWER4, { BI } },
3120 { "btctrl", XLO(19,BOT,528,1), XLBOBB_MASK, PPCCOM, { BI } },
3121 { "btctrl-", XLO(19,BOT,528,1), XLBOBB_MASK, NOPOWER4, { BI } },
3122 { "btctrl+", XLO(19,BOTP,528,1), XLBOBB_MASK, NOPOWER4, { BI } },
3123 { "btctrl-", XLO(19,BOTM4,528,1), XLBOBB_MASK, POWER4, { BI } },
3124 { "btctrl+", XLO(19,BOTP4,528,1), XLBOBB_MASK, POWER4, { BI } },
3125 { "bfctr", XLO(19,BOF,528,0), XLBOBB_MASK, PPCCOM, { BI } },
3126 { "bfctr-", XLO(19,BOF,528,0), XLBOBB_MASK, NOPOWER4, { BI } },
3127 { "bfctr+", XLO(19,BOFP,528,0), XLBOBB_MASK, NOPOWER4, { BI } },
3128 { "bfctr-", XLO(19,BOFM4,528,0), XLBOBB_MASK, POWER4, { BI } },
3129 { "bfctr+", XLO(19,BOFP4,528,0), XLBOBB_MASK, POWER4, { BI } },
3130 { "bfctrl", XLO(19,BOF,528,1), XLBOBB_MASK, PPCCOM, { BI } },
3131 { "bfctrl-", XLO(19,BOF,528,1), XLBOBB_MASK, NOPOWER4, { BI } },
3132 { "bfctrl+", XLO(19,BOFP,528,1), XLBOBB_MASK, NOPOWER4, { BI } },
3133 { "bfctrl-", XLO(19,BOFM4,528,1), XLBOBB_MASK, POWER4, { BI } },
3134 { "bfctrl+", XLO(19,BOFP4,528,1), XLBOBB_MASK, POWER4, { BI } },
3135 { "bcctr", XLLK(19,528,0), XLYBB_MASK, PPCCOM, { BO, BI } },
3136 { "bcctr-", XLYLK(19,528,0,0), XLYBB_MASK, PPCCOM, { BOE, BI } },
3137 { "bcctr+", XLYLK(19,528,1,0), XLYBB_MASK, PPCCOM, { BOE, BI } },
3138 { "bcctrl", XLLK(19,528,1), XLYBB_MASK, PPCCOM, { BO, BI } },
3139 { "bcctrl-", XLYLK(19,528,0,1), XLYBB_MASK, PPCCOM, { BOE, BI } },
3140 { "bcctrl+", XLYLK(19,528,1,1), XLYBB_MASK, PPCCOM, { BOE, BI } },
3141 { "bcc", XLLK(19,528,0), XLBB_MASK, PWRCOM, { BO, BI } },
3142 { "bccl", XLLK(19,528,1), XLBB_MASK, PWRCOM, { BO, BI } },
3143 { "bcctre", XLLK(19,529,0), XLYBB_MASK, BOOKE64, { BO, BI } },
3144 { "bcctrel", XLLK(19,529,1), XLYBB_MASK, BOOKE64, { BO, BI } },
3146 { "rlwimi", M(20,0), M_MASK, PPCCOM, { RA,RS,SH,MBE,ME } },
3147 { "rlimi", M(20,0), M_MASK, PWRCOM, { RA,RS,SH,MBE,ME } },
3149 { "rlwimi.", M(20,1), M_MASK, PPCCOM, { RA,RS,SH,MBE,ME } },
3150 { "rlimi.", M(20,1), M_MASK, PWRCOM, { RA,RS,SH,MBE,ME } },
3152 { "rotlwi", MME(21,31,0), MMBME_MASK, PPCCOM, { RA, RS, SH } },
3153 { "clrlwi", MME(21,31,0), MSHME_MASK, PPCCOM, { RA, RS, MB } },
3154 { "rlwinm", M(21,0), M_MASK, PPCCOM, { RA,RS,SH,MBE,ME } },
3155 { "rlinm", M(21,0), M_MASK, PWRCOM, { RA,RS,SH,MBE,ME } },
3156 { "rotlwi.", MME(21,31,1), MMBME_MASK, PPCCOM, { RA,RS,SH } },
3157 { "clrlwi.", MME(21,31,1), MSHME_MASK, PPCCOM, { RA, RS, MB } },
3158 { "rlwinm.", M(21,1), M_MASK, PPCCOM, { RA,RS,SH,MBE,ME } },
3159 { "rlinm.", M(21,1), M_MASK, PWRCOM, { RA,RS,SH,MBE,ME } },
3161 { "rlmi", M(22,0), M_MASK, M601, { RA,RS,RB,MBE,ME } },
3162 { "rlmi.", M(22,1), M_MASK, M601, { RA,RS,RB,MBE,ME } },
3164 { "be", B(22,0,0), B_MASK, BOOKE64, { LI } },
3165 { "bel", B(22,0,1), B_MASK, BOOKE64, { LI } },
3166 { "bea", B(22,1,0), B_MASK, BOOKE64, { LIA } },
3167 { "bela", B(22,1,1), B_MASK, BOOKE64, { LIA } },
3169 { "rotlw", MME(23,31,0), MMBME_MASK, PPCCOM, { RA, RS, RB } },
3170 { "rlwnm", M(23,0), M_MASK, PPCCOM, { RA,RS,RB,MBE,ME } },
3171 { "rlnm", M(23,0), M_MASK, PWRCOM, { RA,RS,RB,MBE,ME } },
3172 { "rotlw.", MME(23,31,1), MMBME_MASK, PPCCOM, { RA, RS, RB } },
3173 { "rlwnm.", M(23,1), M_MASK, PPCCOM, { RA,RS,RB,MBE,ME } },
3174 { "rlnm.", M(23,1), M_MASK, PWRCOM, { RA,RS,RB,MBE,ME } },
3176 { "nop", OP(24), 0xffffffff, PPCCOM, { 0 } },
3177 { "ori", OP(24), OP_MASK, PPCCOM, { RA, RS, UI } },
3178 { "oril", OP(24), OP_MASK, PWRCOM, { RA, RS, UI } },
3180 { "oris", OP(25), OP_MASK, PPCCOM, { RA, RS, UI } },
3181 { "oriu", OP(25), OP_MASK, PWRCOM, { RA, RS, UI } },
3183 { "xori", OP(26), OP_MASK, PPCCOM, { RA, RS, UI } },
3184 { "xoril", OP(26), OP_MASK, PWRCOM, { RA, RS, UI } },
3186 { "xoris", OP(27), OP_MASK, PPCCOM, { RA, RS, UI } },
3187 { "xoriu", OP(27), OP_MASK, PWRCOM, { RA, RS, UI } },
3189 { "andi.", OP(28), OP_MASK, PPCCOM, { RA, RS, UI } },
3190 { "andil.", OP(28), OP_MASK, PWRCOM, { RA, RS, UI } },
3192 { "andis.", OP(29), OP_MASK, PPCCOM, { RA, RS, UI } },
3193 { "andiu.", OP(29), OP_MASK, PWRCOM, { RA, RS, UI } },
3195 { "rotldi", MD(30,0,0), MDMB_MASK, PPC64, { RA, RS, SH6 } },
3196 { "clrldi", MD(30,0,0), MDSH_MASK, PPC64, { RA, RS, MB6 } },
3197 { "rldicl", MD(30,0,0), MD_MASK, PPC64, { RA, RS, SH6, MB6 } },
3198 { "rotldi.", MD(30,0,1), MDMB_MASK, PPC64, { RA, RS, SH6 } },
3199 { "clrldi.", MD(30,0,1), MDSH_MASK, PPC64, { RA, RS, MB6 } },
3200 { "rldicl.", MD(30,0,1), MD_MASK, PPC64, { RA, RS, SH6, MB6 } },
3202 { "rldicr", MD(30,1,0), MD_MASK, PPC64, { RA, RS, SH6, ME6 } },
3203 { "rldicr.", MD(30,1,1), MD_MASK, PPC64, { RA, RS, SH6, ME6 } },
3205 { "rldic", MD(30,2,0), MD_MASK, PPC64, { RA, RS, SH6, MB6 } },
3206 { "rldic.", MD(30,2,1), MD_MASK, PPC64, { RA, RS, SH6, MB6 } },
3208 { "rldimi", MD(30,3,0), MD_MASK, PPC64, { RA, RS, SH6, MB6 } },
3209 { "rldimi.", MD(30,3,1), MD_MASK, PPC64, { RA, RS, SH6, MB6 } },
3211 { "rotld", MDS(30,8,0), MDSMB_MASK, PPC64, { RA, RS, RB } },
3212 { "rldcl", MDS(30,8,0), MDS_MASK, PPC64, { RA, RS, RB, MB6 } },
3213 { "rotld.", MDS(30,8,1), MDSMB_MASK, PPC64, { RA, RS, RB } },
3214 { "rldcl.", MDS(30,8,1), MDS_MASK, PPC64, { RA, RS, RB, MB6 } },
3216 { "rldcr", MDS(30,9,0), MDS_MASK, PPC64, { RA, RS, RB, ME6 } },
3217 { "rldcr.", MDS(30,9,1), MDS_MASK, PPC64, { RA, RS, RB, ME6 } },
3219 { "cmpw", XCMPL(31,0,0), XCMPL_MASK, PPCCOM, { OBF, RA, RB } },
3220 { "cmpd", XCMPL(31,0,1), XCMPL_MASK, PPC64, { OBF, RA, RB } },
3221 { "cmp", X(31,0), XCMP_MASK, PPCONLY, { BF, L, RA, RB } },
3222 { "cmp", X(31,0), XCMPL_MASK, PWRCOM, { BF, RA, RB } },
3224 { "twlgt", XTO(31,4,TOLGT), XTO_MASK, PPCCOM, { RA, RB } },
3225 { "tlgt", XTO(31,4,TOLGT), XTO_MASK, PWRCOM, { RA, RB } },
3226 { "twllt", XTO(31,4,TOLLT), XTO_MASK, PPCCOM, { RA, RB } },
3227 { "tllt", XTO(31,4,TOLLT), XTO_MASK, PWRCOM, { RA, RB } },
3228 { "tweq", XTO(31,4,TOEQ), XTO_MASK, PPCCOM, { RA, RB } },
3229 { "teq", XTO(31,4,TOEQ), XTO_MASK, PWRCOM, { RA, RB } },
3230 { "twlge", XTO(31,4,TOLGE), XTO_MASK, PPCCOM, { RA, RB } },
3231 { "tlge", XTO(31,4,TOLGE), XTO_MASK, PWRCOM, { RA, RB } },
3232 { "twlnl", XTO(31,4,TOLNL), XTO_MASK, PPCCOM, { RA, RB } },
3233 { "tlnl", XTO(31,4,TOLNL), XTO_MASK, PWRCOM, { RA, RB } },
3234 { "twlle", XTO(31,4,TOLLE), XTO_MASK, PPCCOM, { RA, RB } },
3235 { "tlle", XTO(31,4,TOLLE), XTO_MASK, PWRCOM, { RA, RB } },
3236 { "twlng", XTO(31,4,TOLNG), XTO_MASK, PPCCOM, { RA, RB } },
3237 { "tlng", XTO(31,4,TOLNG), XTO_MASK, PWRCOM, { RA, RB } },
3238 { "twgt", XTO(31,4,TOGT), XTO_MASK, PPCCOM, { RA, RB } },
3239 { "tgt", XTO(31,4,TOGT), XTO_MASK, PWRCOM, { RA, RB } },
3240 { "twge", XTO(31,4,TOGE), XTO_MASK, PPCCOM, { RA, RB } },
3241 { "tge", XTO(31,4,TOGE), XTO_MASK, PWRCOM, { RA, RB } },
3242 { "twnl", XTO(31,4,TONL), XTO_MASK, PPCCOM, { RA, RB } },
3243 { "tnl", XTO(31,4,TONL), XTO_MASK, PWRCOM, { RA, RB } },
3244 { "twlt", XTO(31,4,TOLT), XTO_MASK, PPCCOM, { RA, RB } },
3245 { "tlt", XTO(31,4,TOLT), XTO_MASK, PWRCOM, { RA, RB } },
3246 { "twle", XTO(31,4,TOLE), XTO_MASK, PPCCOM, { RA, RB } },
3247 { "tle", XTO(31,4,TOLE), XTO_MASK, PWRCOM, { RA, RB } },
3248 { "twng", XTO(31,4,TONG), XTO_MASK, PPCCOM, { RA, RB } },
3249 { "tng", XTO(31,4,TONG), XTO_MASK, PWRCOM, { RA, RB } },
3250 { "twne", XTO(31,4,TONE), XTO_MASK, PPCCOM, { RA, RB } },
3251 { "tne", XTO(31,4,TONE), XTO_MASK, PWRCOM, { RA, RB } },
3252 { "trap", XTO(31,4,TOU), 0xffffffff, PPCCOM, { 0 } },
3253 { "tw", X(31,4), X_MASK, PPCCOM, { TO, RA, RB } },
3254 { "t", X(31,4), X_MASK, PWRCOM, { TO, RA, RB } },
3256 { "subfc", XO(31,8,0,0), XO_MASK, PPCCOM, { RT, RA, RB } },
3257 { "sf", XO(31,8,0,0), XO_MASK, PWRCOM, { RT, RA, RB } },
3258 { "subc", XO(31,8,0,0), XO_MASK, PPC, { RT, RB, RA } },
3259 { "subfc.", XO(31,8,0,1), XO_MASK, PPCCOM, { RT, RA, RB } },
3260 { "sf.", XO(31,8,0,1), XO_MASK, PWRCOM, { RT, RA, RB } },
3261 { "subc.", XO(31,8,0,1), XO_MASK, PPCCOM, { RT, RB, RA } },
3262 { "subfco", XO(31,8,1,0), XO_MASK, PPCCOM, { RT, RA, RB } },
3263 { "sfo", XO(31,8,1,0), XO_MASK, PWRCOM, { RT, RA, RB } },
3264 { "subco", XO(31,8,1,0), XO_MASK, PPC, { RT, RB, RA } },
3265 { "subfco.", XO(31,8,1,1), XO_MASK, PPCCOM, { RT, RA, RB } },
3266 { "sfo.", XO(31,8,1,1), XO_MASK, PWRCOM, { RT, RA, RB } },
3267 { "subco.", XO(31,8,1,1), XO_MASK, PPC, { RT, RB, RA } },
3269 { "mulhdu", XO(31,9,0,0), XO_MASK, PPC64, { RT, RA, RB } },
3270 { "mulhdu.", XO(31,9,0,1), XO_MASK, PPC64, { RT, RA, RB } },
3272 { "addc", XO(31,10,0,0), XO_MASK, PPCCOM, { RT, RA, RB } },
3273 { "a", XO(31,10,0,0), XO_MASK, PWRCOM, { RT, RA, RB } },
3274 { "addc.", XO(31,10,0,1), XO_MASK, PPCCOM, { RT, RA, RB } },
3275 { "a.", XO(31,10,0,1), XO_MASK, PWRCOM, { RT, RA, RB } },
3276 { "addco", XO(31,10,1,0), XO_MASK, PPCCOM, { RT, RA, RB } },
3277 { "ao", XO(31,10,1,0), XO_MASK, PWRCOM, { RT, RA, RB } },
3278 { "addco.", XO(31,10,1,1), XO_MASK, PPCCOM, { RT, RA, RB } },
3279 { "ao.", XO(31,10,1,1), XO_MASK, PWRCOM, { RT, RA, RB } },
3281 { "mulhwu", XO(31,11,0,0), XO_MASK, PPC, { RT, RA, RB } },
3282 { "mulhwu.", XO(31,11,0,1), XO_MASK, PPC, { RT, RA, RB } },
3284 { "isellt", X(31,15), X_MASK, PPCISEL, { RT, RA, RB } },
3285 { "iselgt", X(31,47), X_MASK, PPCISEL, { RT, RA, RB } },
3286 { "iseleq", X(31,79), X_MASK, PPCISEL, { RT, RA, RB } },
3287 { "isel", XISEL(31,15), XISEL_MASK, PPCISEL, { RT, RA, RB, CRB } },
3289 { "mfcr", X(31,19), XRARB_MASK, COM, { RT } },
3291 { "lwarx", X(31,20), X_MASK, PPC, { RT, RA, RB } },
3293 { "ldx", X(31,21), X_MASK, PPC64, { RT, RA, RB } },
3295 { "icbt", X(31,22), X_MASK, BOOKE, { CT, RA, RB } },
3297 { "lwzx", X(31,23), X_MASK, PPCCOM, { RT, RA, RB } },
3298 { "lx", X(31,23), X_MASK, PWRCOM, { RT, RA, RB } },
3300 { "slw", XRC(31,24,0), X_MASK, PPCCOM, { RA, RS, RB } },
3301 { "sl", XRC(31,24,0), X_MASK, PWRCOM, { RA, RS, RB } },
3302 { "slw.", XRC(31,24,1), X_MASK, PPCCOM, { RA, RS, RB } },
3303 { "sl.", XRC(31,24,1), X_MASK, PWRCOM, { RA, RS, RB } },
3305 { "cntlzw", XRC(31,26,0), XRB_MASK, PPCCOM, { RA, RS } },
3306 { "cntlz", XRC(31,26,0), XRB_MASK, PWRCOM, { RA, RS } },
3307 { "cntlzw.", XRC(31,26,1), XRB_MASK, PPCCOM, { RA, RS } },
3308 { "cntlz.", XRC(31,26,1), XRB_MASK, PWRCOM, { RA, RS } },
3310 { "sld", XRC(31,27,0), X_MASK, PPC64, { RA, RS, RB } },
3311 { "sld.", XRC(31,27,1), X_MASK, PPC64, { RA, RS, RB } },
3313 { "and", XRC(31,28,0), X_MASK, COM, { RA, RS, RB } },
3314 { "and.", XRC(31,28,1), X_MASK, COM, { RA, RS, RB } },
3316 { "maskg", XRC(31,29,0), X_MASK, M601, { RA, RS, RB } },
3317 { "maskg.", XRC(31,29,1), X_MASK, M601, { RA, RS, RB } },
3319 { "icbte", X(31,30), X_MASK, BOOKE64, { CT, RA, RB } },
3321 { "lwzxe", X(31,31), X_MASK, BOOKE64, { RT, RA, RB } },
3323 { "cmplw", XCMPL(31,32,0), XCMPL_MASK, PPCCOM, { OBF, RA, RB } },
3324 { "cmpld", XCMPL(31,32,1), XCMPL_MASK, PPC64, { OBF, RA, RB } },
3325 { "cmpl", X(31,32), XCMP_MASK, PPCONLY, { BF, L, RA, RB } },
3326 { "cmpl", X(31,32), XCMPL_MASK, PWRCOM, { BF, RA, RB } },
3328 { "subf", XO(31,40,0,0), XO_MASK, PPC, { RT, RA, RB } },
3329 { "sub", XO(31,40,0,0), XO_MASK, PPC, { RT, RB, RA } },
3330 { "subf.", XO(31,40,0,1), XO_MASK, PPC, { RT, RA, RB } },
3331 { "sub.", XO(31,40,0,1), XO_MASK, PPC, { RT, RB, RA } },
3332 { "subfo", XO(31,40,1,0), XO_MASK, PPC, { RT, RA, RB } },
3333 { "subo", XO(31,40,1,0), XO_MASK, PPC, { RT, RB, RA } },
3334 { "subfo.", XO(31,40,1,1), XO_MASK, PPC, { RT, RA, RB } },
3335 { "subo.", XO(31,40,1,1), XO_MASK, PPC, { RT, RB, RA } },
3337 { "ldux", X(31,53), X_MASK, PPC64, { RT, RAL, RB } },
3339 { "dcbst", X(31,54), XRT_MASK, PPC, { RA, RB } },
3341 { "lwzux", X(31,55), X_MASK, PPCCOM, { RT, RAL, RB } },
3342 { "lux", X(31,55), X_MASK, PWRCOM, { RT, RA, RB } },
3344 { "dcbste", X(31,62), XRT_MASK, BOOKE64, { RA, RB } },
3346 { "lwzuxe", X(31,63), X_MASK, BOOKE64, { RT, RAL, RB } },
3348 { "cntlzd", XRC(31,58,0), XRB_MASK, PPC64, { RA, RS } },
3349 { "cntlzd.", XRC(31,58,1), XRB_MASK, PPC64, { RA, RS } },
3351 { "andc", XRC(31,60,0), X_MASK, COM, { RA, RS, RB } },
3352 { "andc.", XRC(31,60,1), X_MASK, COM, { RA, RS, RB } },
3354 { "tdlgt", XTO(31,68,TOLGT), XTO_MASK, PPC64, { RA, RB } },
3355 { "tdllt", XTO(31,68,TOLLT), XTO_MASK, PPC64, { RA, RB } },
3356 { "tdeq", XTO(31,68,TOEQ), XTO_MASK, PPC64, { RA, RB } },
3357 { "tdlge", XTO(31,68,TOLGE), XTO_MASK, PPC64, { RA, RB } },
3358 { "tdlnl", XTO(31,68,TOLNL), XTO_MASK, PPC64, { RA, RB } },
3359 { "tdlle", XTO(31,68,TOLLE), XTO_MASK, PPC64, { RA, RB } },
3360 { "tdlng", XTO(31,68,TOLNG), XTO_MASK, PPC64, { RA, RB } },
3361 { "tdgt", XTO(31,68,TOGT), XTO_MASK, PPC64, { RA, RB } },
3362 { "tdge", XTO(31,68,TOGE), XTO_MASK, PPC64, { RA, RB } },
3363 { "tdnl", XTO(31,68,TONL), XTO_MASK, PPC64, { RA, RB } },
3364 { "tdlt", XTO(31,68,TOLT), XTO_MASK, PPC64, { RA, RB } },
3365 { "tdle", XTO(31,68,TOLE), XTO_MASK, PPC64, { RA, RB } },
3366 { "tdng", XTO(31,68,TONG), XTO_MASK, PPC64, { RA, RB } },
3367 { "tdne", XTO(31,68,TONE), XTO_MASK, PPC64, { RA, RB } },
3368 { "td", X(31,68), X_MASK, PPC64, { TO, RA, RB } },
3370 { "mulhd", XO(31,73,0,0), XO_MASK, PPC64, { RT, RA, RB } },
3371 { "mulhd.", XO(31,73,0,1), XO_MASK, PPC64, { RT, RA, RB } },
3373 { "mulhw", XO(31,75,0,0), XO_MASK, PPC, { RT, RA, RB } },
3374 { "mulhw.", XO(31,75,0,1), XO_MASK, PPC, { RT, RA, RB } },
3376 { "mtsrd", X(31,82), XRB_MASK|(1<<20), PPC64, { SR, RS } },
3378 { "mfmsr", X(31,83), XRARB_MASK, COM, { RT } },
3380 { "ldarx", X(31,84), X_MASK, PPC64, { RT, RA, RB } },
3382 { "dcbf", X(31,86), XRT_MASK, PPC, { RA, RB } },
3384 { "lbzx", X(31,87), X_MASK, COM, { RT, RA, RB } },
3386 { "dcbfe", X(31,94), XRT_MASK, BOOKE64, { RA, RB } },
3388 { "lbzxe", X(31,95), X_MASK, BOOKE64, { RT, RA, RB } },
3390 { "neg", XO(31,104,0,0), XORB_MASK, COM, { RT, RA } },
3391 { "neg.", XO(31,104,0,1), XORB_MASK, COM, { RT, RA } },
3392 { "nego", XO(31,104,1,0), XORB_MASK, COM, { RT, RA } },
3393 { "nego.", XO(31,104,1,1), XORB_MASK, COM, { RT, RA } },
3395 { "mul", XO(31,107,0,0), XO_MASK, M601, { RT, RA, RB } },
3396 { "mul.", XO(31,107,0,1), XO_MASK, M601, { RT, RA, RB } },
3397 { "mulo", XO(31,107,1,0), XO_MASK, M601, { RT, RA, RB } },
3398 { "mulo.", XO(31,107,1,1), XO_MASK, M601, { RT, RA, RB } },
3400 { "mtsrdin", X(31,114), XRA_MASK, PPC64, { RS, RB } },
3402 { "clf", X(31,118), XTO_MASK, POWER, { RA, RB } },
3404 { "lbzux", X(31,119), X_MASK, COM, { RT, RAL, RB } },
3406 { "not", XRC(31,124,0), X_MASK, COM, { RA, RS, RBS } },
3407 { "nor", XRC(31,124,0), X_MASK, COM, { RA, RS, RB } },
3408 { "not.", XRC(31,124,1), X_MASK, COM, { RA, RS, RBS } },
3409 { "nor.", XRC(31,124,1), X_MASK, COM, { RA, RS, RB } },
3411 { "lwarxe", X(31,126), X_MASK, BOOKE64, { RT, RA, RB } },
3413 { "lbzuxe", X(31,127), X_MASK, BOOKE64, { RT, RAL, RB } },
3415 { "wrtee", X(31,131), XRARB_MASK, PPC403, { RS } },
3416 { "wrtee", X(31,131), XRARB_MASK, BOOKE, { RS } },
3418 { "dcbtstls",X(31,134), X_MASK, PPCCHLK, { CT, RA, RB }},
3420 { "subfe", XO(31,136,0,0), XO_MASK, PPCCOM, { RT, RA, RB } },
3421 { "sfe", XO(31,136,0,0), XO_MASK, PWRCOM, { RT, RA, RB } },
3422 { "subfe.", XO(31,136,0,1), XO_MASK, PPCCOM, { RT, RA, RB } },
3423 { "sfe.", XO(31,136,0,1), XO_MASK, PWRCOM, { RT, RA, RB } },
3424 { "subfeo", XO(31,136,1,0), XO_MASK, PPCCOM, { RT, RA, RB } },
3425 { "sfeo", XO(31,136,1,0), XO_MASK, PWRCOM, { RT, RA, RB } },
3426 { "subfeo.", XO(31,136,1,1), XO_MASK, PPCCOM, { RT, RA, RB } },
3427 { "sfeo.", XO(31,136,1,1), XO_MASK, PWRCOM, { RT, RA, RB } },
3429 { "adde", XO(31,138,0,0), XO_MASK, PPCCOM, { RT, RA, RB } },
3430 { "ae", XO(31,138,0,0), XO_MASK, PWRCOM, { RT, RA, RB } },
3431 { "adde.", XO(31,138,0,1), XO_MASK, PPCCOM, { RT, RA, RB } },
3432 { "ae.", XO(31,138,0,1), XO_MASK, PWRCOM, { RT, RA, RB } },
3433 { "addeo", XO(31,138,1,0), XO_MASK, PPCCOM, { RT, RA, RB } },
3434 { "aeo", XO(31,138,1,0), XO_MASK, PWRCOM, { RT, RA, RB } },
3435 { "addeo.", XO(31,138,1,1), XO_MASK, PPCCOM, { RT, RA, RB } },
3436 { "aeo.", XO(31,138,1,1), XO_MASK, PWRCOM, { RT, RA, RB } },
3438 { "dcbtstlse",X(31,142),X_MASK, PPCCHLK64, { CT, RA, RB }},
3440 { "mtcr", XFXM(31,144,0xff), XFXFXM_MASK|FXM_MASK, COM, { RS }},
3441 { "mtcrf", X(31,144), XFXFXM_MASK, COM, { FXM, RS } },
3443 { "mtmsr", X(31,146), XRARB_MASK, COM, { RS } },
3445 { "stdx", X(31,149), X_MASK, PPC64, { RS, RA, RB } },
3447 { "stwcx.", XRC(31,150,1), X_MASK, PPC, { RS, RA, RB } },
3449 { "stwx", X(31,151), X_MASK, PPCCOM, { RS, RA, RB } },
3450 { "stx", X(31,151), X_MASK, PWRCOM, { RS, RA, RB } },
3452 { "stwcxe.", XRC(31,158,1), X_MASK, BOOKE64, { RS, RA, RB } },
3454 { "stwxe", X(31,159), X_MASK, BOOKE64, { RS, RA, RB } },
3456 { "slq", XRC(31,152,0), X_MASK, M601, { RA, RS, RB } },
3457 { "slq.", XRC(31,152,1), X_MASK, M601, { RA, RS, RB } },
3459 { "sle", XRC(31,153,0), X_MASK, M601, { RA, RS, RB } },
3460 { "sle.", XRC(31,153,1), X_MASK, M601, { RA, RS, RB } },
3462 { "wrteei", X(31,163), XE_MASK, PPC403, { E } },
3463 { "wrteei", X(31,163), XE_MASK, BOOKE, { E } },
3465 { "dcbtls", X(31,166), X_MASK, PPCCHLK, { CT, RA, RB }},
3466 { "dcbtlse", X(31,174), X_MASK, PPCCHLK64, { CT, RA, RB }},
3468 { "mtmsrd", X(31,178), XRLARB_MASK, PPC64, { RS, MTMSRD_L } },
3470 { "stdux", X(31,181), X_MASK, PPC64, { RS, RAS, RB } },
3472 { "stwux", X(31,183), X_MASK, PPCCOM, { RS, RAS, RB } },
3473 { "stux", X(31,183), X_MASK, PWRCOM, { RS, RA, RB } },
3475 { "sliq", XRC(31,184,0), X_MASK, M601, { RA, RS, SH } },
3476 { "sliq.", XRC(31,184,1), X_MASK, M601, { RA, RS, SH } },
3478 { "stwuxe", X(31,191), X_MASK, BOOKE64, { RS, RAS, RB } },
3480 { "subfze", XO(31,200,0,0), XORB_MASK, PPCCOM, { RT, RA } },
3481 { "sfze", XO(31,200,0,0), XORB_MASK, PWRCOM, { RT, RA } },
3482 { "subfze.", XO(31,200,0,1), XORB_MASK, PPCCOM, { RT, RA } },
3483 { "sfze.", XO(31,200,0,1), XORB_MASK, PWRCOM, { RT, RA } },
3484 { "subfzeo", XO(31,200,1,0), XORB_MASK, PPCCOM, { RT, RA } },
3485 { "sfzeo", XO(31,200,1,0), XORB_MASK, PWRCOM, { RT, RA } },
3486 { "subfzeo.",XO(31,200,1,1), XORB_MASK, PPCCOM, { RT, RA } },
3487 { "sfzeo.", XO(31,200,1,1), XORB_MASK, PWRCOM, { RT, RA } },
3489 { "addze", XO(31,202,0,0), XORB_MASK, PPCCOM, { RT, RA } },
3490 { "aze", XO(31,202,0,0), XORB_MASK, PWRCOM, { RT, RA } },
3491 { "addze.", XO(31,202,0,1), XORB_MASK, PPCCOM, { RT, RA } },
3492 { "aze.", XO(31,202,0,1), XORB_MASK, PWRCOM, { RT, RA } },
3493 { "addzeo", XO(31,202,1,0), XORB_MASK, PPCCOM, { RT, RA } },
3494 { "azeo", XO(31,202,1,0), XORB_MASK, PWRCOM, { RT, RA } },
3495 { "addzeo.", XO(31,202,1,1), XORB_MASK, PPCCOM, { RT, RA } },
3496 { "azeo.", XO(31,202,1,1), XORB_MASK, PWRCOM, { RT, RA } },
3498 { "mtsr", X(31,210), XRB_MASK|(1<<20), COM32, { SR, RS } },
3500 { "stdcx.", XRC(31,214,1), X_MASK, PPC64, { RS, RA, RB } },
3502 { "stbx", X(31,215), X_MASK, COM, { RS, RA, RB } },
3504 { "sllq", XRC(31,216,0), X_MASK, M601, { RA, RS, RB } },
3505 { "sllq.", XRC(31,216,1), X_MASK, M601, { RA, RS, RB } },
3507 { "sleq", XRC(31,217,0), X_MASK, M601, { RA, RS, RB } },
3508 { "sleq.", XRC(31,217,1), X_MASK, M601, { RA, RS, RB } },
3510 { "stbxe", X(31,223), X_MASK, BOOKE64, { RS, RA, RB } },
3512 { "icblc", X(31,230), X_MASK, PPCCHLK, { CT, RA, RB }},
3514 { "subfme", XO(31,232,0,0), XORB_MASK, PPCCOM, { RT, RA } },
3515 { "sfme", XO(31,232,0,0), XORB_MASK, PWRCOM, { RT, RA } },
3516 { "subfme.", XO(31,232,0,1), XORB_MASK, PPCCOM, { RT, RA } },
3517 { "sfme.", XO(31,232,0,1), XORB_MASK, PWRCOM, { RT, RA } },
3518 { "subfmeo", XO(31,232,1,0), XORB_MASK, PPCCOM, { RT, RA } },
3519 { "sfmeo", XO(31,232,1,0), XORB_MASK, PWRCOM, { RT, RA } },
3520 { "subfmeo.",XO(31,232,1,1), XORB_MASK, PPCCOM, { RT, RA } },
3521 { "sfmeo.", XO(31,232,1,1), XORB_MASK, PWRCOM, { RT, RA } },
3523 { "mulld", XO(31,233,0,0), XO_MASK, PPC64, { RT, RA, RB } },
3524 { "mulld.", XO(31,233,0,1), XO_MASK, PPC64, { RT, RA, RB } },
3525 { "mulldo", XO(31,233,1,0), XO_MASK, PPC64, { RT, RA, RB } },
3526 { "mulldo.", XO(31,233,1,1), XO_MASK, PPC64, { RT, RA, RB } },
3528 { "addme", XO(31,234,0,0), XORB_MASK, PPCCOM, { RT, RA } },
3529 { "ame", XO(31,234,0,0), XORB_MASK, PWRCOM, { RT, RA } },
3530 { "addme.", XO(31,234,0,1), XORB_MASK, PPCCOM, { RT, RA } },
3531 { "ame.", XO(31,234,0,1), XORB_MASK, PWRCOM, { RT, RA } },
3532 { "addmeo", XO(31,234,1,0), XORB_MASK, PPCCOM, { RT, RA } },
3533 { "ameo", XO(31,234,1,0), XORB_MASK, PWRCOM, { RT, RA } },
3534 { "addmeo.", XO(31,234,1,1), XORB_MASK, PPCCOM, { RT, RA } },
3535 { "ameo.", XO(31,234,1,1), XORB_MASK, PWRCOM, { RT, RA } },
3537 { "mullw", XO(31,235,0,0), XO_MASK, PPCCOM, { RT, RA, RB } },
3538 { "muls", XO(31,235,0,0), XO_MASK, PWRCOM, { RT, RA, RB } },
3539 { "mullw.", XO(31,235,0,1), XO_MASK, PPCCOM, { RT, RA, RB } },
3540 { "muls.", XO(31,235,0,1), XO_MASK, PWRCOM, { RT, RA, RB } },
3541 { "mullwo", XO(31,235,1,0), XO_MASK, PPCCOM, { RT, RA, RB } },
3542 { "mulso", XO(31,235,1,0), XO_MASK, PWRCOM, { RT, RA, RB } },
3543 { "mullwo.", XO(31,235,1,1), XO_MASK, PPCCOM, { RT, RA, RB } },
3544 { "mulso.", XO(31,235,1,1), XO_MASK, PWRCOM, { RT, RA, RB } },
3546 { "icblce", X(31,238), X_MASK, PPCCHLK64, { CT, RA, RB }},
3547 { "mtsrin", X(31,242), XRA_MASK, PPC32, { RS, RB } },
3548 { "mtsri", X(31,242), XRA_MASK, POWER32, { RS, RB } },
3550 { "dcbtst", X(31,246), XRT_MASK, PPC, { CT, RA, RB } },
3552 { "stbux", X(31,247), X_MASK, COM, { RS, RAS, RB } },
3554 { "slliq", XRC(31,248,0), X_MASK, M601, { RA, RS, SH } },
3555 { "slliq.", XRC(31,248,1), X_MASK, M601, { RA, RS, SH } },
3557 { "dcbtste", X(31,253), X_MASK, BOOKE64, { CT, RA, RB } },
3559 { "stbuxe", X(31,255), X_MASK, BOOKE64, { RS, RAS, RB } },
3561 { "mfdcrx", X(31,259), X_MASK, BOOKE, { RS, RA } },
3563 { "icbt", X(31,262), XRT_MASK, PPC403, { RA, RB } },
3565 { "doz", XO(31,264,0,0), XO_MASK, M601, { RT, RA, RB } },
3566 { "doz.", XO(31,264,0,1), XO_MASK, M601, { RT, RA, RB } },
3567 { "dozo", XO(31,264,1,0), XO_MASK, M601, { RT, RA, RB } },
3568 { "dozo.", XO(31,264,1,1), XO_MASK, M601, { RT, RA, RB } },
3570 { "add", XO(31,266,0,0), XO_MASK, PPCCOM, { RT, RA, RB } },
3571 { "cax", XO(31,266,0,0), XO_MASK, PWRCOM, { RT, RA, RB } },
3572 { "add.", XO(31,266,0,1), XO_MASK, PPCCOM, { RT, RA, RB } },
3573 { "cax.", XO(31,266,0,1), XO_MASK, PWRCOM, { RT, RA, RB } },
3574 { "addo", XO(31,266,1,0), XO_MASK, PPCCOM, { RT, RA, RB } },
3575 { "caxo", XO(31,266,1,0), XO_MASK, PWRCOM, { RT, RA, RB } },
3576 { "addo.", XO(31,266,1,1), XO_MASK, PPCCOM, { RT, RA, RB } },
3577 { "caxo.", XO(31,266,1,1), XO_MASK, PWRCOM, { RT, RA, RB } },
3579 { "tlbiel", X(31,274), XRTRA_MASK, POWER4, { RB } },
3581 { "mfapidi", X(31,275), X_MASK, BOOKE, { RT, RA } },
3583 { "lscbx", XRC(31,277,0), X_MASK, M601, { RT, RA, RB } },
3584 { "lscbx.", XRC(31,277,1), X_MASK, M601, { RT, RA, RB } },
3586 { "dcbt", X(31,278), XRT_MASK, PPC, { CT, RA, RB } },
3588 { "lhzx", X(31,279), X_MASK, COM, { RT, RA, RB } },
3590 { "eqv", XRC(31,284,0), X_MASK, COM, { RA, RS, RB } },
3591 { "eqv.", XRC(31,284,1), X_MASK, COM, { RA, RS, RB } },
3593 { "dcbte", X(31,286), X_MASK, BOOKE64, { CT, RA, RB } },
3595 { "lhzxe", X(31,287), X_MASK, BOOKE64, { RT, RA, RB } },
3597 { "tlbie", X(31,306), XRTLRA_MASK, PPC, { RB, L } },
3598 { "tlbi", X(31,306), XRT_MASK, POWER, { RA, RB } },
3600 { "eciwx", X(31,310), X_MASK, PPC, { RT, RA, RB } },
3602 { "lhzux", X(31,311), X_MASK, COM, { RT, RAL, RB } },
3604 { "xor", XRC(31,316,0), X_MASK, COM, { RA, RS, RB } },
3605 { "xor.", XRC(31,316,1), X_MASK, COM, { RA, RS, RB } },
3607 { "lhzuxe", X(31,319), X_MASK, BOOKE64, { RT, RAL, RB } },
3609 { "mfexisr", XSPR(31,323,64), XSPR_MASK, PPC403, { RT } },
3610 { "mfexier", XSPR(31,323,66), XSPR_MASK, PPC403, { RT } },
3611 { "mfbr0", XSPR(31,323,128), XSPR_MASK, PPC403, { RT } },
3612 { "mfbr1", XSPR(31,323,129), XSPR_MASK, PPC403, { RT } },
3613 { "mfbr2", XSPR(31,323,130), XSPR_MASK, PPC403, { RT } },
3614 { "mfbr3", XSPR(31,323,131), XSPR_MASK, PPC403, { RT } },
3615 { "mfbr4", XSPR(31,323,132), XSPR_MASK, PPC403, { RT } },
3616 { "mfbr5", XSPR(31,323,133), XSPR_MASK, PPC403, { RT } },
3617 { "mfbr6", XSPR(31,323,134), XSPR_MASK, PPC403, { RT } },
3618 { "mfbr7", XSPR(31,323,135), XSPR_MASK, PPC403, { RT } },
3619 { "mfbear", XSPR(31,323,144), XSPR_MASK, PPC403, { RT } },
3620 { "mfbesr", XSPR(31,323,145), XSPR_MASK, PPC403, { RT } },
3621 { "mfiocr", XSPR(31,323,160), XSPR_MASK, PPC403, { RT } },
3622 { "mfdmacr0", XSPR(31,323,192), XSPR_MASK, PPC403, { RT } },
3623 { "mfdmact0", XSPR(31,323,193), XSPR_MASK, PPC403, { RT } },
3624 { "mfdmada0", XSPR(31,323,194), XSPR_MASK, PPC403, { RT } },
3625 { "mfdmasa0", XSPR(31,323,195), XSPR_MASK, PPC403, { RT } },
3626 { "mfdmacc0", XSPR(31,323,196), XSPR_MASK, PPC403, { RT } },
3627 { "mfdmacr1", XSPR(31,323,200), XSPR_MASK, PPC403, { RT } },
3628 { "mfdmact1", XSPR(31,323,201), XSPR_MASK, PPC403, { RT } },
3629 { "mfdmada1", XSPR(31,323,202), XSPR_MASK, PPC403, { RT } },
3630 { "mfdmasa1", XSPR(31,323,203), XSPR_MASK, PPC403, { RT } },
3631 { "mfdmacc1", XSPR(31,323,204), XSPR_MASK, PPC403, { RT } },
3632 { "mfdmacr2", XSPR(31,323,208), XSPR_MASK, PPC403, { RT } },
3633 { "mfdmact2", XSPR(31,323,209), XSPR_MASK, PPC403, { RT } },
3634 { "mfdmada2", XSPR(31,323,210), XSPR_MASK, PPC403, { RT } },
3635 { "mfdmasa2", XSPR(31,323,211), XSPR_MASK, PPC403, { RT } },
3636 { "mfdmacc2", XSPR(31,323,212), XSPR_MASK, PPC403, { RT } },
3637 { "mfdmacr3", XSPR(31,323,216), XSPR_MASK, PPC403, { RT } },
3638 { "mfdmact3", XSPR(31,323,217), XSPR_MASK, PPC403, { RT } },
3639 { "mfdmada3", XSPR(31,323,218), XSPR_MASK, PPC403, { RT } },
3640 { "mfdmasa3", XSPR(31,323,219), XSPR_MASK, PPC403, { RT } },
3641 { "mfdmacc3", XSPR(31,323,220), XSPR_MASK, PPC403, { RT } },
3642 { "mfdmasr", XSPR(31,323,224), XSPR_MASK, PPC403, { RT } },
3643 { "mfdcr", X(31,323), X_MASK, PPC403, { RT, SPR } },
3644 { "mfdcr", X(31,323), X_MASK, BOOKE, { RT, SPR } },
3646 { "div", XO(31,331,0,0), XO_MASK, M601, { RT, RA, RB } },
3647 { "div.", XO(31,331,0,1), XO_MASK, M601, { RT, RA, RB } },
3648 { "divo", XO(31,331,1,0), XO_MASK, M601, { RT, RA, RB } },
3649 { "divo.", XO(31,331,1,1), XO_MASK, M601, { RT, RA, RB } },
3651 { "mfpmr", X(31,334), X_MASK, PPCPMR, { RT, PMR }},
3653 { "mfmq", XSPR(31,339,0), XSPR_MASK, M601, { RT } },
3654 { "mfxer", XSPR(31,339,1), XSPR_MASK, COM, { RT } },
3655 { "mfrtcu", XSPR(31,339,4), XSPR_MASK, COM, { RT } },
3656 { "mfrtcl", XSPR(31,339,5), XSPR_MASK, COM, { RT } },
3657 { "mfdec", XSPR(31,339,6), XSPR_MASK, MFDEC1, { RT } },
3658 { "mflr", XSPR(31,339,8), XSPR_MASK, COM, { RT } },
3659 { "mfctr", XSPR(31,339,9), XSPR_MASK, COM, { RT } },
3660 { "mftid", XSPR(31,339,17), XSPR_MASK, POWER, { RT } },
3661 { "mfdsisr", XSPR(31,339,18), XSPR_MASK, COM, { RT } },
3662 { "mfdar", XSPR(31,339,19), XSPR_MASK, COM, { RT } },
3663 { "mfdec", XSPR(31,339,22), XSPR_MASK, MFDEC2, { RT } },
3664 { "mfsdr0", XSPR(31,339,24), XSPR_MASK, POWER, { RT } },
3665 { "mfsdr1", XSPR(31,339,25), XSPR_MASK, COM, { RT } },
3666 { "mfsrr0", XSPR(31,339,26), XSPR_MASK, COM, { RT } },
3667 { "mfsrr1", XSPR(31,339,27), XSPR_MASK, COM, { RT } },
3668 { "mfpid", XSPR(31,339,48), XSPR_MASK, BOOKE, { RT } },
3669 { "mfcsrr0", XSPR(31,339,58), XSPR_MASK, BOOKE, { RT } },
3670 { "mfcsrr1", XSPR(31,339,59), XSPR_MASK, BOOKE, { RT } },
3671 { "mfdear", XSPR(31,339,61), XSPR_MASK, BOOKE, { RT } },
3672 { "mfesr", XSPR(31,339,62), XSPR_MASK, BOOKE, { RT } },
3673 { "mfivpr", XSPR(31,339,63), XSPR_MASK, BOOKE, { RT } },
3674 { "mfcmpa", XSPR(31,339,144), XSPR_MASK, PPC860, { RT } },
3675 { "mfcmpb", XSPR(31,339,145), XSPR_MASK, PPC860, { RT } },
3676 { "mfcmpc", XSPR(31,339,146), XSPR_MASK, PPC860, { RT } },
3677 { "mfcmpd", XSPR(31,339,147), XSPR_MASK, PPC860, { RT } },
3678 { "mficr", XSPR(31,339,148), XSPR_MASK, PPC860, { RT } },
3679 { "mfder", XSPR(31,339,149), XSPR_MASK, PPC860, { RT } },
3680 { "mfcounta", XSPR(31,339,150), XSPR_MASK, PPC860, { RT } },
3681 { "mfcountb", XSPR(31,339,151), XSPR_MASK, PPC860, { RT } },
3682 { "mfcmpe", XSPR(31,339,152), XSPR_MASK, PPC860, { RT } },
3683 { "mfcmpf", XSPR(31,339,153), XSPR_MASK, PPC860, { RT } },
3684 { "mfcmpg", XSPR(31,339,154), XSPR_MASK, PPC860, { RT } },
3685 { "mfcmph", XSPR(31,339,155), XSPR_MASK, PPC860, { RT } },
3686 { "mflctrl1", XSPR(31,339,156), XSPR_MASK, PPC860, { RT } },
3687 { "mflctrl2", XSPR(31,339,157), XSPR_MASK, PPC860, { RT } },
3688 { "mfictrl", XSPR(31,339,158), XSPR_MASK, PPC860, { RT } },
3689 { "mfbar", XSPR(31,339,159), XSPR_MASK, PPC860, { RT } },
3690 { "mfvrsave", XSPR(31,339,256), XSPR_MASK, PPCVEC, { RT } },
3691 { "mfusprg0", XSPR(31,339,256), XSPR_MASK, BOOKE, { RT } },
3692 { "mfsprg4", XSPR(31,339,260), XSPR_MASK, PPC405, { RT } },
3693 { "mfsprg5", XSPR(31,339,261), XSPR_MASK, PPC405, { RT } },
3694 { "mfsprg6", XSPR(31,339,262), XSPR_MASK, PPC405, { RT } },
3695 { "mfsprg7", XSPR(31,339,263), XSPR_MASK, PPC405, { RT } },
3696 { "mftb", XSPR(31,339,268), XSPR_MASK, BOOKE, { RT } },
3697 { "mftbl", XSPR(31,339,268), XSPR_MASK, BOOKE, { RT } },
3698 { "mftbu", XSPR(31,339,269), XSPR_MASK, BOOKE, { RT } },
3699 { "mfsprg", XSPR(31,339,272), XSPRG_MASK, PPC, { RT, SPRG } },
3700 { "mfsprg0", XSPR(31,339,272), XSPR_MASK, PPC, { RT } },
3701 { "mfsprg1", XSPR(31,339,273), XSPR_MASK, PPC, { RT } },
3702 { "mfsprg2", XSPR(31,339,274), XSPR_MASK, PPC, { RT } },
3703 { "mfsprg3", XSPR(31,339,275), XSPR_MASK, PPC, { RT } },
3704 { "mfasr", XSPR(31,339,280), XSPR_MASK, PPC64, { RT } },
3705 { "mfear", XSPR(31,339,282), XSPR_MASK, PPC, { RT } },
3706 { "mfpir", XSPR(31,339,286), XSPR_MASK, BOOKE, { RT } },
3707 { "mfpvr", XSPR(31,339,287), XSPR_MASK, PPC, { RT } },
3708 { "mfdbsr", XSPR(31,339,304), XSPR_MASK, BOOKE, { RT } },
3709 { "mfdbcr0", XSPR(31,339,308), XSPR_MASK, BOOKE, { RT } },
3710 { "mfdbcr1", XSPR(31,339,309), XSPR_MASK, BOOKE, { RT } },
3711 { "mfdbcr2", XSPR(31,339,310), XSPR_MASK, BOOKE, { RT } },
3712 { "mfiac1", XSPR(31,339,312), XSPR_MASK, BOOKE, { RT } },
3713 { "mfiac2", XSPR(31,339,313), XSPR_MASK, BOOKE, { RT } },
3714 { "mfiac3", XSPR(31,339,314), XSPR_MASK, BOOKE, { RT } },
3715 { "mfiac4", XSPR(31,339,315), XSPR_MASK, BOOKE, { RT } },
3716 { "mfdac1", XSPR(31,339,316), XSPR_MASK, BOOKE, { RT } },
3717 { "mfdac2", XSPR(31,339,317), XSPR_MASK, BOOKE, { RT } },
3718 { "mfdvc1", XSPR(31,339,318), XSPR_MASK, BOOKE, { RT } },
3719 { "mfdvc2", XSPR(31,339,319), XSPR_MASK, BOOKE, { RT } },
3720 { "mftsr", XSPR(31,339,336), XSPR_MASK, BOOKE, { RT } },
3721 { "mftcr", XSPR(31,339,340), XSPR_MASK, BOOKE, { RT } },
3722 { "mfivor0", XSPR(31,339,400), XSPR_MASK, BOOKE, { RT } },
3723 { "mfivor1", XSPR(31,339,401), XSPR_MASK, BOOKE, { RT } },
3724 { "mfivor2", XSPR(31,339,402), XSPR_MASK, BOOKE, { RT } },
3725 { "mfivor3", XSPR(31,339,403), XSPR_MASK, BOOKE, { RT } },
3726 { "mfivor4", XSPR(31,339,404), XSPR_MASK, BOOKE, { RT } },
3727 { "mfivor5", XSPR(31,339,405), XSPR_MASK, BOOKE, { RT } },
3728 { "mfivor6", XSPR(31,339,406), XSPR_MASK, BOOKE, { RT } },
3729 { "mfivor7", XSPR(31,339,407), XSPR_MASK, BOOKE, { RT } },
3730 { "mfivor8", XSPR(31,339,408), XSPR_MASK, BOOKE, { RT } },
3731 { "mfivor9", XSPR(31,339,409), XSPR_MASK, BOOKE, { RT } },
3732 { "mfivor10", XSPR(31,339,410), XSPR_MASK, BOOKE, { RT } },
3733 { "mfivor11", XSPR(31,339,411), XSPR_MASK, BOOKE, { RT } },
3734 { "mfivor12", XSPR(31,339,412), XSPR_MASK, BOOKE, { RT } },
3735 { "mfivor13", XSPR(31,339,413), XSPR_MASK, BOOKE, { RT } },
3736 { "mfivor14", XSPR(31,339,414), XSPR_MASK, BOOKE, { RT } },
3737 { "mfivor15", XSPR(31,339,415), XSPR_MASK, BOOKE, { RT } },
3738 { "mfspefscr", XSPR(31,339,512), XSPR_MASK, PPCSPE, { RT } },
3739 { "mfbbear", XSPR(31,339,513), XSPR_MASK, PPCBRLK, { RT } },
3740 { "mfbbtar", XSPR(31,339,514), XSPR_MASK, PPCBRLK, { RT } },
3741 { "mfibatu", XSPR(31,339,528), XSPRBAT_MASK, PPC, { RT, SPRBAT } },
3742 { "mfibatl", XSPR(31,339,529), XSPRBAT_MASK, PPC, { RT, SPRBAT } },
3743 { "mfdbatu", XSPR(31,339,536), XSPRBAT_MASK, PPC, { RT, SPRBAT } },
3744 { "mfdbatl", XSPR(31,339,537), XSPRBAT_MASK, PPC, { RT, SPRBAT } },
3745 { "mfic_cst", XSPR(31,339,560), XSPR_MASK, PPC860, { RT } },
3746 { "mfic_adr", XSPR(31,339,561), XSPR_MASK, PPC860, { RT } },
3747 { "mfic_dat", XSPR(31,339,562), XSPR_MASK, PPC860, { RT } },
3748 { "mfdc_cst", XSPR(31,339,568), XSPR_MASK, PPC860, { RT } },
3749 { "mfdc_adr", XSPR(31,339,569), XSPR_MASK, PPC860, { RT } },
3750 { "mfdc_dat", XSPR(31,339,570), XSPR_MASK, PPC860, { RT } },
3751 { "mfmcsrr0", XSPR(31,339,570), XSPR_MASK, PPCRFMCI, { RT } },
3752 { "mfmcsrr1", XSPR(31,339,571), XSPR_MASK, PPCRFMCI, { RT } },
3753 { "mfmcsr", XSPR(31,339,572), XSPR_MASK, PPCRFMCI, { RT } },
3754 { "mfdpdr", XSPR(31,339,630), XSPR_MASK, PPC860, { RT } },
3755 { "mfdpir", XSPR(31,339,631), XSPR_MASK, PPC860, { RT } },
3756 { "mfimmr", XSPR(31,339,638), XSPR_MASK, PPC860, { RT } },
3757 { "mfmi_ctr", XSPR(31,339,784), XSPR_MASK, PPC860, { RT } },
3758 { "mfmi_ap", XSPR(31,339,786), XSPR_MASK, PPC860, { RT } },
3759 { "mfmi_epn", XSPR(31,339,787), XSPR_MASK, PPC860, { RT } },
3760 { "mfmi_twc", XSPR(31,339,789), XSPR_MASK, PPC860, { RT } },
3761 { "mfmi_rpn", XSPR(31,339,790), XSPR_MASK, PPC860, { RT } },
3762 { "mfmd_ctr", XSPR(31,339,792), XSPR_MASK, PPC860, { RT } },
3763 { "mfm_casid", XSPR(31,339,793), XSPR_MASK, PPC860, { RT } },
3764 { "mfmd_ap", XSPR(31,339,794), XSPR_MASK, PPC860, { RT } },
3765 { "mfmd_epn", XSPR(31,339,795), XSPR_MASK, PPC860, { RT } },
3766 { "mfmd_twb", XSPR(31,339,796), XSPR_MASK, PPC860, { RT } },
3767 { "mfmd_twc", XSPR(31,339,797), XSPR_MASK, PPC860, { RT } },
3768 { "mfmd_rpn", XSPR(31,339,798), XSPR_MASK, PPC860, { RT } },
3769 { "mfm_tw", XSPR(31,339,799), XSPR_MASK, PPC860, { RT } },
3770 { "mfmi_dbcam", XSPR(31,339,816), XSPR_MASK, PPC860, { RT } },
3771 { "mfmi_dbram0",XSPR(31,339,817), XSPR_MASK, PPC860, { RT } },
3772 { "mfmi_dbram1",XSPR(31,339,818), XSPR_MASK, PPC860, { RT } },
3773 { "mfmd_dbcam", XSPR(31,339,824), XSPR_MASK, PPC860, { RT } },
3774 { "mfmd_dbram0",XSPR(31,339,825), XSPR_MASK, PPC860, { RT } },
3775 { "mfmd_dbram1",XSPR(31,339,826), XSPR_MASK, PPC860, { RT } },
3776 { "mfummcr0", XSPR(31,339,936), XSPR_MASK, PPC750, { RT } },
3777 { "mfupmc1", XSPR(31,339,937), XSPR_MASK, PPC750, { RT } },
3778 { "mfupmc2", XSPR(31,339,938), XSPR_MASK, PPC750, { RT } },
3779 { "mfusia", XSPR(31,339,939), XSPR_MASK, PPC750, { RT } },
3780 { "mfummcr1", XSPR(31,339,940), XSPR_MASK, PPC750, { RT } },
3781 { "mfupmc3", XSPR(31,339,941), XSPR_MASK, PPC750, { RT } },
3782 { "mfupmc4", XSPR(31,339,942), XSPR_MASK, PPC750, { RT } },
3783 { "mfzpr", XSPR(31,339,944), XSPR_MASK, PPC403, { RT } },
3784 { "mfpid", XSPR(31,339,945), XSPR_MASK, PPC403, { RT } },
3785 { "mfccr0", XSPR(31,339,947), XSPR_MASK, PPC405, { RT } },
3786 { "mfiac3", XSPR(31,339,948), XSPR_MASK, PPC405, { RT } },
3787 { "mfiac4", XSPR(31,339,949), XSPR_MASK, PPC405, { RT } },
3788 { "mfdvc1", XSPR(31,339,950), XSPR_MASK, PPC405, { RT } },
3789 { "mfdvc2", XSPR(31,339,951), XSPR_MASK, PPC405, { RT } },
3790 { "mfmmcr0", XSPR(31,339,952), XSPR_MASK, PPC750, { RT } },
3791 { "mfpmc1", XSPR(31,339,953), XSPR_MASK, PPC750, { RT } },
3792 { "mfsgr", XSPR(31,339,953), XSPR_MASK, PPC403, { RT } },
3793 { "mfpmc2", XSPR(31,339,954), XSPR_MASK, PPC750, { RT } },
3794 { "mfdcwr", XSPR(31,339,954), XSPR_MASK, PPC403, { RT } },
3795 { "mfsia", XSPR(31,339,955), XSPR_MASK, PPC750, { RT } },
3796 { "mfsler", XSPR(31,339,955), XSPR_MASK, PPC405, { RT } },
3797 { "mfmmcr1", XSPR(31,339,956), XSPR_MASK, PPC750, { RT } },
3798 { "mfsu0r", XSPR(31,339,956), XSPR_MASK, PPC405, { RT } },
3799 { "mfpmc3", XSPR(31,339,957), XSPR_MASK, PPC750, { RT } },
3800 { "mfdbcr1", XSPR(31,339,957), XSPR_MASK, PPC405, { RT } },
3801 { "mfpmc4", XSPR(31,339,958), XSPR_MASK, PPC750, { RT } },
3802 { "mficdbdr", XSPR(31,339,979), XSPR_MASK, PPC403, { RT } },
3803 { "mfesr", XSPR(31,339,980), XSPR_MASK, PPC403, { RT } },
3804 { "mfdear", XSPR(31,339,981), XSPR_MASK, PPC403, { RT } },
3805 { "mfevpr", XSPR(31,339,982), XSPR_MASK, PPC403, { RT } },
3806 { "mfcdbcr", XSPR(31,339,983), XSPR_MASK, PPC403, { RT } },
3807 { "mftsr", XSPR(31,339,984), XSPR_MASK, PPC403, { RT } },
3808 { "mftcr", XSPR(31,339,986), XSPR_MASK, PPC403, { RT } },
3809 { "mfpit", XSPR(31,339,987), XSPR_MASK, PPC403, { RT } },
3810 { "mftbhi", XSPR(31,339,988), XSPR_MASK, PPC403, { RT } },
3811 { "mftblo", XSPR(31,339,989), XSPR_MASK, PPC403, { RT } },
3812 { "mfsrr2", XSPR(31,339,990), XSPR_MASK, PPC403, { RT } },
3813 { "mfsrr3", XSPR(31,339,991), XSPR_MASK, PPC403, { RT } },
3814 { "mfdbsr", XSPR(31,339,1008), XSPR_MASK, PPC403, { RT } },
3815 { "mfdbcr0", XSPR(31,339,1010), XSPR_MASK, PPC405, { RT } },
3816 { "mfiac1", XSPR(31,339,1012), XSPR_MASK, PPC403, { RT } },
3817 { "mfiac2", XSPR(31,339,1013), XSPR_MASK, PPC403, { RT } },
3818 { "mfdac1", XSPR(31,339,1014), XSPR_MASK, PPC403, { RT } },
3819 { "mfdac2", XSPR(31,339,1015), XSPR_MASK, PPC403, { RT } },
3820 { "mfl2cr", XSPR(31,339,1017), XSPR_MASK, PPC750, { RT } },
3821 { "mfdccr", XSPR(31,339,1018), XSPR_MASK, PPC403, { RT } },
3822 { "mficcr", XSPR(31,339,1019), XSPR_MASK, PPC403, { RT } },
3823 { "mfictc", XSPR(31,339,1019), XSPR_MASK, PPC750, { RT } },
3824 { "mfpbl1", XSPR(31,339,1020), XSPR_MASK, PPC403, { RT } },
3825 { "mfthrm1", XSPR(31,339,1020), XSPR_MASK, PPC750, { RT } },
3826 { "mfpbu1", XSPR(31,339,1021), XSPR_MASK, PPC403, { RT } },
3827 { "mfthrm2", XSPR(31,339,1021), XSPR_MASK, PPC750, { RT } },
3828 { "mfpbl2", XSPR(31,339,1022), XSPR_MASK, PPC403, { RT } },
3829 { "mfthrm3", XSPR(31,339,1022), XSPR_MASK, PPC750, { RT } },
3830 { "mfpbu2", XSPR(31,339,1023), XSPR_MASK, PPC403, { RT } },
3831 { "mfspr", X(31,339), X_MASK, COM, { RT, SPR } },
3833 { "lwax", X(31,341), X_MASK, PPC64, { RT, RA, RB } },
3835 { "dst", XDSS(31,342,0), XDSS_MASK, PPCVEC, { RA, RB, STRM } },
3836 { "dstt", XDSS(31,342,1), XDSS_MASK, PPCVEC, { RA, RB, STRM } },
3838 { "lhax", X(31,343), X_MASK, COM, { RT, RA, RB } },
3840 { "lhaxe", X(31,351), X_MASK, BOOKE64, { RT, RA, RB } },
3842 { "dstst", XDSS(31,374,0), XDSS_MASK, PPCVEC, { RA, RB, STRM } },
3843 { "dststt", XDSS(31,374,1), XDSS_MASK, PPCVEC, { RA, RB, STRM } },
3845 { "dccci", X(31,454), XRT_MASK, PPC403, { RA, RB } },
3847 { "abs", XO(31,360,0,0), XORB_MASK, M601, { RT, RA } },
3848 { "abs.", XO(31,360,0,1), XORB_MASK, M601, { RT, RA } },
3849 { "abso", XO(31,360,1,0), XORB_MASK, M601, { RT, RA } },
3850 { "abso.", XO(31,360,1,1), XORB_MASK, M601, { RT, RA } },
3852 { "divs", XO(31,363,0,0), XO_MASK, M601, { RT, RA, RB } },
3853 { "divs.", XO(31,363,0,1), XO_MASK, M601, { RT, RA, RB } },
3854 { "divso", XO(31,363,1,0), XO_MASK, M601, { RT, RA, RB } },
3855 { "divso.", XO(31,363,1,1), XO_MASK, M601, { RT, RA, RB } },
3857 { "tlbia", X(31,370), 0xffffffff, PPC, { 0 } },
3859 { "mftbl", XSPR(31,371,268), XSPR_MASK, CLASSIC, { RT } },
3860 { "mftbu", XSPR(31,371,269), XSPR_MASK, CLASSIC, { RT } },
3861 { "mftb", X(31,371), X_MASK, CLASSIC, { RT, TBR } },
3863 { "lwaux", X(31,373), X_MASK, PPC64, { RT, RAL, RB } },
3865 { "lhaux", X(31,375), X_MASK, COM, { RT, RAL, RB } },
3867 { "lhauxe", X(31,383), X_MASK, BOOKE64, { RT, RAL, RB } },
3869 { "mtdcrx", X(31,387), X_MASK, BOOKE, { RA, RS } },
3871 { "dcblc", X(31,390), X_MASK, PPCCHLK, { CT, RA, RB }},
3873 { "subfe64", XO(31,392,0,0), XO_MASK, BOOKE64, { RT, RA, RB } },
3874 { "subfe64o",XO(31,392,1,0), XO_MASK, BOOKE64, { RT, RA, RB } },
3876 { "adde64", XO(31,394,0,0), XO_MASK, BOOKE64, { RT, RA, RB } },
3877 { "adde64o", XO(31,394,1,0), XO_MASK, BOOKE64, { RT, RA, RB } },
3879 { "dcblce", X(31,398), X_MASK, PPCCHLK64, { CT, RA, RB }},
3881 { "slbmte", X(31,402), XRA_MASK, PPC64, { RS, RB } },
3883 { "sthx", X(31,407), X_MASK, COM, { RS, RA, RB } },
3885 { "lfqx", X(31,791), X_MASK, POWER2, { FRT, RA, RB } },
3887 { "lfqux", X(31,823), X_MASK, POWER2, { FRT, RA, RB } },
3889 { "stfqx", X(31,919), X_MASK, POWER2, { FRS, RA, RB } },
3891 { "stfqux", X(31,951), X_MASK, POWER2, { FRS, RA, RB } },
3893 { "orc", XRC(31,412,0), X_MASK, COM, { RA, RS, RB } },
3894 { "orc.", XRC(31,412,1), X_MASK, COM, { RA, RS, RB } },
3896 { "sradi", XS(31,413,0), XS_MASK, PPC64, { RA, RS, SH6 } },
3897 { "sradi.", XS(31,413,1), XS_MASK, PPC64, { RA, RS, SH6 } },
3899 { "sthxe", X(31,415), X_MASK, BOOKE64, { RS, RA, RB } },
3901 { "slbie", X(31,434), XRTRA_MASK, PPC64, { RB } },
3903 { "ecowx", X(31,438), X_MASK, PPC, { RT, RA, RB } },
3905 { "sthux", X(31,439), X_MASK, COM, { RS, RAS, RB } },
3907 { "sthuxe", X(31,447), X_MASK, BOOKE64, { RS, RAS, RB } },
3909 { "mr", XRC(31,444,0), X_MASK, COM, { RA, RS, RBS } },
3910 { "or", XRC(31,444,0), X_MASK, COM, { RA, RS, RB } },
3911 { "mr.", XRC(31,444,1), X_MASK, COM, { RA, RS, RBS } },
3912 { "or.", XRC(31,444,1), X_MASK, COM, { RA, RS, RB } },
3914 { "mtexisr", XSPR(31,451,64), XSPR_MASK, PPC403, { RT } },
3915 { "mtexier", XSPR(31,451,66), XSPR_MASK, PPC403, { RT } },
3916 { "mtbr0", XSPR(31,451,128), XSPR_MASK, PPC403, { RT } },
3917 { "mtbr1", XSPR(31,451,129), XSPR_MASK, PPC403, { RT } },
3918 { "mtbr2", XSPR(31,451,130), XSPR_MASK, PPC403, { RT } },
3919 { "mtbr3", XSPR(31,451,131), XSPR_MASK, PPC403, { RT } },
3920 { "mtbr4", XSPR(31,451,132), XSPR_MASK, PPC403, { RT } },
3921 { "mtbr5", XSPR(31,451,133), XSPR_MASK, PPC403, { RT } },
3922 { "mtbr6", XSPR(31,451,134), XSPR_MASK, PPC403, { RT } },
3923 { "mtbr7", XSPR(31,451,135), XSPR_MASK, PPC403, { RT } },
3924 { "mtbear", XSPR(31,451,144), XSPR_MASK, PPC403, { RT } },
3925 { "mtbesr", XSPR(31,451,145), XSPR_MASK, PPC403, { RT } },
3926 { "mtiocr", XSPR(31,451,160), XSPR_MASK, PPC403, { RT } },
3927 { "mtdmacr0", XSPR(31,451,192), XSPR_MASK, PPC403, { RT } },
3928 { "mtdmact0", XSPR(31,451,193), XSPR_MASK, PPC403, { RT } },
3929 { "mtdmada0", XSPR(31,451,194), XSPR_MASK, PPC403, { RT } },
3930 { "mtdmasa0", XSPR(31,451,195), XSPR_MASK, PPC403, { RT } },
3931 { "mtdmacc0", XSPR(31,451,196), XSPR_MASK, PPC403, { RT } },
3932 { "mtdmacr1", XSPR(31,451,200), XSPR_MASK, PPC403, { RT } },
3933 { "mtdmact1", XSPR(31,451,201), XSPR_MASK, PPC403, { RT } },
3934 { "mtdmada1", XSPR(31,451,202), XSPR_MASK, PPC403, { RT } },
3935 { "mtdmasa1", XSPR(31,451,203), XSPR_MASK, PPC403, { RT } },
3936 { "mtdmacc1", XSPR(31,451,204), XSPR_MASK, PPC403, { RT } },
3937 { "mtdmacr2", XSPR(31,451,208), XSPR_MASK, PPC403, { RT } },
3938 { "mtdmact2", XSPR(31,451,209), XSPR_MASK, PPC403, { RT } },
3939 { "mtdmada2", XSPR(31,451,210), XSPR_MASK, PPC403, { RT } },
3940 { "mtdmasa2", XSPR(31,451,211), XSPR_MASK, PPC403, { RT } },
3941 { "mtdmacc2", XSPR(31,451,212), XSPR_MASK, PPC403, { RT } },
3942 { "mtdmacr3", XSPR(31,451,216), XSPR_MASK, PPC403, { RT } },
3943 { "mtdmact3", XSPR(31,451,217), XSPR_MASK, PPC403, { RT } },
3944 { "mtdmada3", XSPR(31,451,218), XSPR_MASK, PPC403, { RT } },
3945 { "mtdmasa3", XSPR(31,451,219), XSPR_MASK, PPC403, { RT } },
3946 { "mtdmacc3", XSPR(31,451,220), XSPR_MASK, PPC403, { RT } },
3947 { "mtdmasr", XSPR(31,451,224), XSPR_MASK, PPC403, { RT } },
3948 { "mtdcr", X(31,451), X_MASK, PPC403, { SPR, RS } },
3949 { "mtdcr", X(31,451), X_MASK, BOOKE, { SPR, RS } },
3951 { "subfze64",XO(31,456,0,0), XORB_MASK, BOOKE64, { RT, RA } },
3952 { "subfze64o",XO(31,456,1,0), XORB_MASK, BOOKE64, { RT, RA } },
3954 { "divdu", XO(31,457,0,0), XO_MASK, PPC64, { RT, RA, RB } },
3955 { "divdu.", XO(31,457,0,1), XO_MASK, PPC64, { RT, RA, RB } },
3956 { "divduo", XO(31,457,1,0), XO_MASK, PPC64, { RT, RA, RB } },
3957 { "divduo.", XO(31,457,1,1), XO_MASK, PPC64, { RT, RA, RB } },
3959 { "addze64", XO(31,458,0,0), XORB_MASK, BOOKE64, { RT, RA } },
3960 { "addze64o",XO(31,458,1,0), XORB_MASK, BOOKE64, { RT, RA } },
3962 { "divwu", XO(31,459,0,0), XO_MASK, PPC, { RT, RA, RB } },
3963 { "divwu.", XO(31,459,0,1), XO_MASK, PPC, { RT, RA, RB } },
3964 { "divwuo", XO(31,459,1,0), XO_MASK, PPC, { RT, RA, RB } },
3965 { "divwuo.", XO(31,459,1,1), XO_MASK, PPC, { RT, RA, RB } },
3967 { "mtmq", XSPR(31,467,0), XSPR_MASK, M601, { RS } },
3968 { "mtxer", XSPR(31,467,1), XSPR_MASK, COM, { RS } },
3969 { "mtlr", XSPR(31,467,8), XSPR_MASK, COM, { RS } },
3970 { "mtctr", XSPR(31,467,9), XSPR_MASK, COM, { RS } },
3971 { "mttid", XSPR(31,467,17), XSPR_MASK, POWER, { RS } },
3972 { "mtdsisr", XSPR(31,467,18), XSPR_MASK, COM, { RS } },
3973 { "mtdar", XSPR(31,467,19), XSPR_MASK, COM, { RS } },
3974 { "mtrtcu", XSPR(31,467,20), XSPR_MASK, COM, { RS } },
3975 { "mtrtcl", XSPR(31,467,21), XSPR_MASK, COM, { RS } },
3976 { "mtdec", XSPR(31,467,22), XSPR_MASK, COM, { RS } },
3977 { "mtsdr0", XSPR(31,467,24), XSPR_MASK, POWER, { RS } },
3978 { "mtsdr1", XSPR(31,467,25), XSPR_MASK, COM, { RS } },
3979 { "mtsrr0", XSPR(31,467,26), XSPR_MASK, COM, { RS } },
3980 { "mtsrr1", XSPR(31,467,27), XSPR_MASK, COM, { RS } },
3981 { "mtpid", XSPR(31,467,48), XSPR_MASK, BOOKE, { RS } },
3982 { "mtdecar", XSPR(31,467,54), XSPR_MASK, BOOKE, { RS } },
3983 { "mtcsrr0", XSPR(31,467,58), XSPR_MASK, BOOKE, { RS } },
3984 { "mtcsrr1", XSPR(31,467,59), XSPR_MASK, BOOKE, { RS } },
3985 { "mtdear", XSPR(31,467,61), XSPR_MASK, BOOKE, { RS } },
3986 { "mtesr", XSPR(31,467,62), XSPR_MASK, BOOKE, { RS } },
3987 { "mtivpr", XSPR(31,467,63), XSPR_MASK, BOOKE, { RS } },
3988 { "mtcmpa", XSPR(31,467,144), XSPR_MASK, PPC860, { RT } },
3989 { "mtcmpb", XSPR(31,467,145), XSPR_MASK, PPC860, { RT } },
3990 { "mtcmpc", XSPR(31,467,146), XSPR_MASK, PPC860, { RT } },
3991 { "mtcmpd", XSPR(31,467,147), XSPR_MASK, PPC860, { RT } },
3992 { "mticr", XSPR(31,467,148), XSPR_MASK, PPC860, { RT } },
3993 { "mtder", XSPR(31,467,149), XSPR_MASK, PPC860, { RT } },
3994 { "mtcounta", XSPR(31,467,150), XSPR_MASK, PPC860, { RT } },
3995 { "mtcountb", XSPR(31,467,151), XSPR_MASK, PPC860, { RT } },
3996 { "mtcmpe", XSPR(31,467,152), XSPR_MASK, PPC860, { RT } },
3997 { "mtcmpf", XSPR(31,467,153), XSPR_MASK, PPC860, { RT } },
3998 { "mtcmpg", XSPR(31,467,154), XSPR_MASK, PPC860, { RT } },
3999 { "mtcmph", XSPR(31,467,155), XSPR_MASK, PPC860, { RT } },
4000 { "mtlctrl1", XSPR(31,467,156), XSPR_MASK, PPC860, { RT } },
4001 { "mtlctrl2", XSPR(31,467,157), XSPR_MASK, PPC860, { RT } },
4002 { "mtictrl", XSPR(31,467,158), XSPR_MASK, PPC860, { RT } },
4003 { "mtbar", XSPR(31,467,159), XSPR_MASK, PPC860, { RT } },
4004 { "mtvrsave", XSPR(31,467,256), XSPR_MASK, PPCVEC, { RT } },
4005 { "mtusprg0", XSPR(31,467,256), XSPR_MASK, BOOKE, { RS } },
4006 { "mtsprg", XSPR(31,467,272), XSPRG_MASK,PPC, { SPRG, RS } },
4007 { "mtsprg0", XSPR(31,467,272), XSPR_MASK, PPC, { RT } },
4008 { "mtsprg1", XSPR(31,467,273), XSPR_MASK, PPC, { RT } },
4009 { "mtsprg2", XSPR(31,467,274), XSPR_MASK, PPC, { RT } },
4010 { "mtsprg3", XSPR(31,467,275), XSPR_MASK, PPC, { RT } },
4011 { "mtsprg4", XSPR(31,467,276), XSPR_MASK, PPC405, { RT } },
4012 { "mtsprg4", XSPR(31,467,276), XSPR_MASK, BOOKE, { RS } },
4013 { "mtsprg5", XSPR(31,467,277), XSPR_MASK, PPC405, { RT } },
4014 { "mtsprg5", XSPR(31,467,277), XSPR_MASK, BOOKE, { RS } },
4015 { "mtsprg6", XSPR(31,467,278), XSPR_MASK, PPC405, { RT } },
4016 { "mtsprg6", XSPR(31,467,278), XSPR_MASK, BOOKE, { RS } },
4017 { "mtsprg7", XSPR(31,467,279), XSPR_MASK, PPC405, { RT } },
4018 { "mtsprg7", XSPR(31,467,279), XSPR_MASK, BOOKE, { RS } },
4019 { "mtasr", XSPR(31,467,280), XSPR_MASK, PPC64, { RS } },
4020 { "mtear", XSPR(31,467,282), XSPR_MASK, PPC, { RS } },
4021 { "mttbl", XSPR(31,467,284), XSPR_MASK, PPC, { RS } },
4022 { "mttbu", XSPR(31,467,285), XSPR_MASK, PPC, { RS } },
4023 { "mtdbsr", XSPR(31,467,304), XSPR_MASK, BOOKE, { RS } },
4024 { "mtdbcr0", XSPR(31,467,308), XSPR_MASK, BOOKE, { RS } },
4025 { "mtdbcr1", XSPR(31,467,309), XSPR_MASK, BOOKE, { RS } },
4026 { "mtdbcr2", XSPR(31,467,310), XSPR_MASK, BOOKE, { RS } },
4027 { "mtiac1", XSPR(31,467,312), XSPR_MASK, BOOKE, { RS } },
4028 { "mtiac2", XSPR(31,467,313), XSPR_MASK, BOOKE, { RS } },
4029 { "mtiac3", XSPR(31,467,314), XSPR_MASK, BOOKE, { RS } },
4030 { "mtiac4", XSPR(31,467,315), XSPR_MASK, BOOKE, { RS } },
4031 { "mtdac1", XSPR(31,467,316), XSPR_MASK, BOOKE, { RS } },
4032 { "mtdac2", XSPR(31,467,317), XSPR_MASK, BOOKE, { RS } },
4033 { "mtdvc1", XSPR(31,467,318), XSPR_MASK, BOOKE, { RS } },
4034 { "mtdvc2", XSPR(31,467,319), XSPR_MASK, BOOKE, { RS } },
4035 { "mttsr", XSPR(31,467,336), XSPR_MASK, BOOKE, { RS } },
4036 { "mttcr", XSPR(31,467,340), XSPR_MASK, BOOKE, { RS } },
4037 { "mtivor0", XSPR(31,467,400), XSPR_MASK, BOOKE, { RS } },
4038 { "mtivor1", XSPR(31,467,401), XSPR_MASK, BOOKE, { RS } },
4039 { "mtivor2", XSPR(31,467,402), XSPR_MASK, BOOKE, { RS } },
4040 { "mtivor3", XSPR(31,467,403), XSPR_MASK, BOOKE, { RS } },
4041 { "mtivor4", XSPR(31,467,404), XSPR_MASK, BOOKE, { RS } },
4042 { "mtivor5", XSPR(31,467,405), XSPR_MASK, BOOKE, { RS } },
4043 { "mtivor6", XSPR(31,467,406), XSPR_MASK, BOOKE, { RS } },
4044 { "mtivor7", XSPR(31,467,407), XSPR_MASK, BOOKE, { RS } },
4045 { "mtivor8", XSPR(31,467,408), XSPR_MASK, BOOKE, { RS } },
4046 { "mtivor9", XSPR(31,467,409), XSPR_MASK, BOOKE, { RS } },
4047 { "mtivor10", XSPR(31,467,410), XSPR_MASK, BOOKE, { RS } },
4048 { "mtivor11", XSPR(31,467,411), XSPR_MASK, BOOKE, { RS } },
4049 { "mtivor12", XSPR(31,467,412), XSPR_MASK, BOOKE, { RS } },
4050 { "mtivor13", XSPR(31,467,413), XSPR_MASK, BOOKE, { RS } },
4051 { "mtivor14", XSPR(31,467,414), XSPR_MASK, BOOKE, { RS } },
4052 { "mtivor15", XSPR(31,467,415), XSPR_MASK, BOOKE, { RS } },
4053 { "mtspefscr", XSPR(31,467,512), XSPR_MASK, PPCSPE, { RS } },
4054 { "mtbbear", XSPR(31,467,513), XSPR_MASK, PPCBRLK, { RS } },
4055 { "mtbbtar", XSPR(31,467,514), XSPR_MASK, PPCBRLK, { RS } },
4056 { "mtibatu", XSPR(31,467,528), XSPRBAT_MASK, PPC, { SPRBAT, RS } },
4057 { "mtibatl", XSPR(31,467,529), XSPRBAT_MASK, PPC, { SPRBAT, RS } },
4058 { "mtdbatu", XSPR(31,467,536), XSPRBAT_MASK, PPC, { SPRBAT, RS } },
4059 { "mtdbatl", XSPR(31,467,537), XSPRBAT_MASK, PPC, { SPRBAT, RS } },
4060 { "mtmcsrr0", XSPR(31,467,570), XSPR_MASK, PPCRFMCI, { RS } },
4061 { "mtmcsrr1", XSPR(31,467,571), XSPR_MASK, PPCRFMCI, { RS } },
4062 { "mtmcsr", XSPR(31,467,572), XSPR_MASK, PPCRFMCI, { RS } },
4063 { "mtummcr0", XSPR(31,467,936), XSPR_MASK, PPC750, { RT } },
4064 { "mtupmc1", XSPR(31,467,937), XSPR_MASK, PPC750, { RT } },
4065 { "mtupmc2", XSPR(31,467,938), XSPR_MASK, PPC750, { RT } },
4066 { "mtusia", XSPR(31,467,939), XSPR_MASK, PPC750, { RT } },
4067 { "mtummcr1", XSPR(31,467,940), XSPR_MASK, PPC750, { RT } },
4068 { "mtupmc3", XSPR(31,467,941), XSPR_MASK, PPC750, { RT } },
4069 { "mtupmc4", XSPR(31,467,942), XSPR_MASK, PPC750, { RT } },
4070 { "mtzpr", XSPR(31,467,944), XSPR_MASK, PPC403, { RT } },
4071 { "mtpid", XSPR(31,467,945), XSPR_MASK, PPC403, { RT } },
4072 { "mtccr0", XSPR(31,467,947), XSPR_MASK, PPC405, { RT } },
4073 { "mtiac3", XSPR(31,467,948), XSPR_MASK, PPC405, { RT } },
4074 { "mtiac4", XSPR(31,467,949), XSPR_MASK, PPC405, { RT } },
4075 { "mtdvc1", XSPR(31,467,950), XSPR_MASK, PPC405, { RT } },
4076 { "mtdvc2", XSPR(31,467,951), XSPR_MASK, PPC405, { RT } },
4077 { "mtmmcr0", XSPR(31,467,952), XSPR_MASK, PPC750, { RT } },
4078 { "mtsgr", XSPR(31,467,953), XSPR_MASK, PPC403, { RT } },
4079 { "mtpmc1", XSPR(31,467,953), XSPR_MASK, PPC750, { RT } },
4080 { "mtdcwr", XSPR(31,467,954), XSPR_MASK, PPC403, { RT } },
4081 { "mtpmc2", XSPR(31,467,954), XSPR_MASK, PPC750, { RT } },
4082 { "mtsler", XSPR(31,467,955), XSPR_MASK, PPC405, { RT } },
4083 { "mtsia", XSPR(31,467,955), XSPR_MASK, PPC750, { RT } },
4084 { "mtsu0r", XSPR(31,467,956), XSPR_MASK, PPC405, { RT } },
4085 { "mtmmcr1", XSPR(31,467,956), XSPR_MASK, PPC750, { RT } },
4086 { "mtdbcr1", XSPR(31,467,957), XSPR_MASK, PPC405, { RT } },
4087 { "mtpmc3", XSPR(31,467,957), XSPR_MASK, PPC750, { RT } },
4088 { "mtpmc4", XSPR(31,467,958), XSPR_MASK, PPC750, { RT } },
4089 { "mticdbdr", XSPR(31,467,979), XSPR_MASK, PPC403, { RT } },
4090 { "mtesr", XSPR(31,467,980), XSPR_MASK, PPC403, { RT } },
4091 { "mtdear", XSPR(31,467,981), XSPR_MASK, PPC403, { RT } },
4092 { "mtevpr", XSPR(31,467,982), XSPR_MASK, PPC403, { RT } },
4093 { "mtcdbcr", XSPR(31,467,983), XSPR_MASK, PPC403, { RT } },
4094 { "mttsr", XSPR(31,467,984), XSPR_MASK, PPC403, { RT } },
4095 { "mttcr", XSPR(31,467,986), XSPR_MASK, PPC403, { RT } },
4096 { "mtpit", XSPR(31,467,987), XSPR_MASK, PPC403, { RT } },
4097 { "mttbhi", XSPR(31,467,988), XSPR_MASK, PPC403, { RT } },
4098 { "mttblo", XSPR(31,467,989), XSPR_MASK, PPC403, { RT } },
4099 { "mtsrr2", XSPR(31,467,990), XSPR_MASK, PPC403, { RT } },
4100 { "mtsrr3", XSPR(31,467,991), XSPR_MASK, PPC403, { RT } },
4101 { "mtdbsr", XSPR(31,467,1008), XSPR_MASK, PPC403, { RT } },
4102 { "mtdbcr0", XSPR(31,467,1010), XSPR_MASK, PPC405, { RT } },
4103 { "mtiac1", XSPR(31,467,1012), XSPR_MASK, PPC403, { RT } },
4104 { "mtiac2", XSPR(31,467,1013), XSPR_MASK, PPC403, { RT } },
4105 { "mtdac1", XSPR(31,467,1014), XSPR_MASK, PPC403, { RT } },
4106 { "mtdac2", XSPR(31,467,1015), XSPR_MASK, PPC403, { RT } },
4107 { "mtl2cr", XSPR(31,467,1017), XSPR_MASK, PPC750, { RT } },
4108 { "mtdccr", XSPR(31,467,1018), XSPR_MASK, PPC403, { RT } },
4109 { "mticcr", XSPR(31,467,1019), XSPR_MASK, PPC403, { RT } },
4110 { "mtictc", XSPR(31,467,1019), XSPR_MASK, PPC750, { RT } },
4111 { "mtpbl1", XSPR(31,467,1020), XSPR_MASK, PPC403, { RT } },
4112 { "mtthrm1", XSPR(31,467,1020), XSPR_MASK, PPC750, { RT } },
4113 { "mtpbu1", XSPR(31,467,1021), XSPR_MASK, PPC403, { RT } },
4114 { "mtthrm2", XSPR(31,467,1021), XSPR_MASK, PPC750, { RT } },
4115 { "mtpbl2", XSPR(31,467,1022), XSPR_MASK, PPC403, { RT } },
4116 { "mtthrm3", XSPR(31,467,1022), XSPR_MASK, PPC750, { RT } },
4117 { "mtpbu2", XSPR(31,467,1023), XSPR_MASK, PPC403, { RT } },
4118 { "mtspr", X(31,467), X_MASK, COM, { SPR, RS } },
4120 { "dcbi", X(31,470), XRT_MASK, PPC, { RA, RB } },
4122 { "nand", XRC(31,476,0), X_MASK, COM, { RA, RS, RB } },
4123 { "nand.", XRC(31,476,1), X_MASK, COM, { RA, RS, RB } },
4125 { "dcbie", X(31,478), XRT_MASK, BOOKE64, { RA, RB } },
4127 { "dcread", X(31,486), X_MASK, PPC403, { RT, RA, RB }},
4129 { "mtpmr", X(31,462), X_MASK, PPCPMR, { PMR, RS }},
4131 { "icbtls", X(31,486), X_MASK, PPCCHLK, { CT, RA, RB }},
4133 { "nabs", XO(31,488,0,0), XORB_MASK, M601, { RT, RA } },
4134 { "subfme64",XO(31,488,0,0), XORB_MASK, BOOKE64, { RT, RA } },
4135 { "nabs.", XO(31,488,0,1), XORB_MASK, M601, { RT, RA } },
4136 { "nabso", XO(31,488,1,0), XORB_MASK, M601, { RT, RA } },
4137 { "subfme64o",XO(31,488,1,0), XORB_MASK, BOOKE64, { RT, RA } },
4138 { "nabso.", XO(31,488,1,1), XORB_MASK, M601, { RT, RA } },
4140 { "divd", XO(31,489,0,0), XO_MASK, PPC64, { RT, RA, RB } },
4141 { "divd.", XO(31,489,0,1), XO_MASK, PPC64, { RT, RA, RB } },
4142 { "divdo", XO(31,489,1,0), XO_MASK, PPC64, { RT, RA, RB } },
4143 { "divdo.", XO(31,489,1,1), XO_MASK, PPC64, { RT, RA, RB } },
4145 { "addme64", XO(31,490,0,0), XORB_MASK, BOOKE64, { RT, RA } },
4146 { "addme64o",XO(31,490,1,0), XORB_MASK, BOOKE64, { RT, RA } },
4148 { "divw", XO(31,491,0,0), XO_MASK, PPC, { RT, RA, RB } },
4149 { "divw.", XO(31,491,0,1), XO_MASK, PPC, { RT, RA, RB } },
4150 { "divwo", XO(31,491,1,0), XO_MASK, PPC, { RT, RA, RB } },
4151 { "divwo.", XO(31,491,1,1), XO_MASK, PPC, { RT, RA, RB } },
4153 { "icbtlse", X(31,494), X_MASK, PPCCHLK64, { CT, RA, RB }},
4155 { "slbia", X(31,498), 0xffffffff, PPC64, { 0 } },
4157 { "cli", X(31,502), XRB_MASK, POWER, { RT, RA } },
4159 { "stdcxe.", XRC(31,511,1), X_MASK, BOOKE64, { RS, RA, RB } },
4161 { "mcrxr", X(31,512), XRARB_MASK|(3<<21), COM, { BF } },
4163 { "bblels", X(31,518), X_MASK, PPCBRLK, { 0 }},
4164 { "mcrxr64", X(31,544), XRARB_MASK|(3<<21), BOOKE64, { BF } },
4166 { "clcs", X(31,531), XRB_MASK, M601, { RT, RA } },
4168 { "lswx", X(31,533), X_MASK, PPCCOM, { RT, RA, RB } },
4169 { "lsx", X(31,533), X_MASK, PWRCOM, { RT, RA, RB } },
4171 { "lwbrx", X(31,534), X_MASK, PPCCOM, { RT, RA, RB } },
4172 { "lbrx", X(31,534), X_MASK, PWRCOM, { RT, RA, RB } },
4174 { "lfsx", X(31,535), X_MASK, COM, { FRT, RA, RB } },
4176 { "srw", XRC(31,536,0), X_MASK, PPCCOM, { RA, RS, RB } },
4177 { "sr", XRC(31,536,0), X_MASK, PWRCOM, { RA, RS, RB } },
4178 { "srw.", XRC(31,536,1), X_MASK, PPCCOM, { RA, RS, RB } },
4179 { "sr.", XRC(31,536,1), X_MASK, PWRCOM, { RA, RS, RB } },
4181 { "rrib", XRC(31,537,0), X_MASK, M601, { RA, RS, RB } },
4182 { "rrib.", XRC(31,537,1), X_MASK, M601, { RA, RS, RB } },
4184 { "srd", XRC(31,539,0), X_MASK, PPC64, { RA, RS, RB } },
4185 { "srd.", XRC(31,539,1), X_MASK, PPC64, { RA, RS, RB } },
4187 { "maskir", XRC(31,541,0), X_MASK, M601, { RA, RS, RB } },
4188 { "maskir.", XRC(31,541,1), X_MASK, M601, { RA, RS, RB } },
4190 { "lwbrxe", X(31,542), X_MASK, BOOKE64, { RT, RA, RB } },
4192 { "lfsxe", X(31,543), X_MASK, BOOKE64, { FRT, RA, RB } },
4194 { "bbelr", X(31,550), X_MASK, PPCBRLK, { 0 }},
4195 { "tlbsync", X(31,566), 0xffffffff, PPC, { 0 } },
4197 { "lfsux", X(31,567), X_MASK, COM, { FRT, RAS, RB } },
4199 { "lfsuxe", X(31,575), X_MASK, BOOKE64, { FRT, RAS, RB } },
4201 { "mfsr", X(31,595), XRB_MASK|(1<<20), COM32, { RT, SR } },
4203 { "lswi", X(31,597), X_MASK, PPCCOM, { RT, RA, NB } },
4204 { "lsi", X(31,597), X_MASK, PWRCOM, { RT, RA, NB } },
4206 { "lwsync", XSYNC(31,598,1), 0xffffffff, PPCONLY, { 0 } },
4207 { "ptesync", XSYNC(31,598,2), 0xffffffff, PPC64, { 0 } },
4208 { "msync", X(31,598), 0xffffffff, BOOKE, { 0 } },
4209 { "sync", X(31,598), XSYNC_MASK, PPCCOM, { LS } },
4210 { "dcs", X(31,598), 0xffffffff, PWRCOM, { 0 } },
4212 { "lfdx", X(31,599), X_MASK, COM, { FRT, RA, RB } },
4214 { "lfdxe", X(31,607), X_MASK, BOOKE64, { FRT, RA, RB } },
4216 { "mfsri", X(31,627), X_MASK, PWRCOM, { RT, RA, RB } },
4218 { "dclst", X(31,630), XRB_MASK, PWRCOM, { RS, RA } },
4220 { "lfdux", X(31,631), X_MASK, COM, { FRT, RAS, RB } },
4222 { "lfduxe", X(31,639), X_MASK, BOOKE64, { FRT, RAS, RB } },
4224 { "mfsrin", X(31,659), XRA_MASK, PPC32, { RT, RB } },
4226 { "stswx", X(31,661), X_MASK, PPCCOM, { RS, RA, RB } },
4227 { "stsx", X(31,661), X_MASK, PWRCOM, { RS, RA, RB } },
4229 { "stwbrx", X(31,662), X_MASK, PPCCOM, { RS, RA, RB } },
4230 { "stbrx", X(31,662), X_MASK, PWRCOM, { RS, RA, RB } },
4232 { "stfsx", X(31,663), X_MASK, COM, { FRS, RA, RB } },
4234 { "srq", XRC(31,664,0), X_MASK, M601, { RA, RS, RB } },
4235 { "srq.", XRC(31,664,1), X_MASK, M601, { RA, RS, RB } },
4237 { "sre", XRC(31,665,0), X_MASK, M601, { RA, RS, RB } },
4238 { "sre.", XRC(31,665,1), X_MASK, M601, { RA, RS, RB } },
4240 { "stwbrxe", X(31,670), X_MASK, BOOKE64, { RS, RA, RB } },
4242 { "stfsxe", X(31,671), X_MASK, BOOKE64, { FRS, RA, RB } },
4244 { "stfsux", X(31,695), X_MASK, COM, { FRS, RAS, RB } },
4246 { "sriq", XRC(31,696,0), X_MASK, M601, { RA, RS, SH } },
4247 { "sriq.", XRC(31,696,1), X_MASK, M601, { RA, RS, SH } },
4249 { "stfsuxe", X(31,703), X_MASK, BOOKE64, { FRS, RAS, RB } },
4251 { "stswi", X(31,725), X_MASK, PPCCOM, { RS, RA, NB } },
4252 { "stsi", X(31,725), X_MASK, PWRCOM, { RS, RA, NB } },
4254 { "stfdx", X(31,727), X_MASK, COM, { FRS, RA, RB } },
4256 { "srlq", XRC(31,728,0), X_MASK, M601, { RA, RS, RB } },
4257 { "srlq.", XRC(31,728,1), X_MASK, M601, { RA, RS, RB } },
4259 { "sreq", XRC(31,729,0), X_MASK, M601, { RA, RS, RB } },
4260 { "sreq.", XRC(31,729,1), X_MASK, M601, { RA, RS, RB } },
4262 { "stfdxe", X(31,735), X_MASK, BOOKE64, { FRS, RA, RB } },
4264 { "dcba", X(31,758), XRT_MASK, PPC405, { RA, RB } },
4265 { "dcba", X(31,758), XRT_MASK, BOOKE, { RA, RB } },
4267 { "stfdux", X(31,759), X_MASK, COM, { FRS, RAS, RB } },
4269 { "srliq", XRC(31,760,0), X_MASK, M601, { RA, RS, SH } },
4270 { "srliq.", XRC(31,760,1), X_MASK, M601, { RA, RS, SH } },
4272 { "dcbae", X(31,766), XRT_MASK, BOOKE64, { RA, RB } },
4274 { "stfduxe", X(31,767), X_MASK, BOOKE64, { FRS, RAS, RB } },
4276 { "tlbivax", X(31,786), XRT_MASK, BOOKE, { RA, RB } },
4277 { "tlbivaxe",X(31,787), XRT_MASK, BOOKE64, { RA, RB } },
4279 { "lhbrx", X(31,790), X_MASK, COM, { RT, RA, RB } },
4281 { "sraw", XRC(31,792,0), X_MASK, PPCCOM, { RA, RS, RB } },
4282 { "sra", XRC(31,792,0), X_MASK, PWRCOM, { RA, RS, RB } },
4283 { "sraw.", XRC(31,792,1), X_MASK, PPCCOM, { RA, RS, RB } },
4284 { "sra.", XRC(31,792,1), X_MASK, PWRCOM, { RA, RS, RB } },
4286 { "srad", XRC(31,794,0), X_MASK, PPC64, { RA, RS, RB } },
4287 { "srad.", XRC(31,794,1), X_MASK, PPC64, { RA, RS, RB } },
4289 { "lhbrxe", X(31,798), X_MASK, BOOKE64, { RT, RA, RB } },
4291 { "ldxe", X(31,799), X_MASK, BOOKE64, { RT, RA, RB } },
4292 { "lduxe", X(31,831), X_MASK, BOOKE64, { RT, RA, RB } },
4294 { "rac", X(31,818), X_MASK, PWRCOM, { RT, RA, RB } },
4296 { "dss", XDSS(31,822,0), XDSS_MASK, PPCVEC, { STRM } },
4297 { "dssall", XDSS(31,822,1), XDSS_MASK, PPCVEC, { 0 } },
4299 { "srawi", XRC(31,824,0), X_MASK, PPCCOM, { RA, RS, SH } },
4300 { "srai", XRC(31,824,0), X_MASK, PWRCOM, { RA, RS, SH } },
4301 { "srawi.", XRC(31,824,1), X_MASK, PPCCOM, { RA, RS, SH } },
4302 { "srai.", XRC(31,824,1), X_MASK, PWRCOM, { RA, RS, SH } },
4304 { "slbmfev", X(31,851), XRA_MASK, PPC64, { RT, RB } },
4306 { "mbar", X(31,854), X_MASK, BOOKE, { MO } },
4307 { "eieio", X(31,854), 0xffffffff, PPC, { 0 } },
4309 { "tlbsx", XRC(31,914,0), X_MASK, PPC403, { RT, RA, RB } },
4310 { "tlbsx.", XRC(31,914,1), X_MASK, PPC403, { RT, RA, RB } },
4312 { "tlbsx", XRC(31,914,0), X_MASK, BOOKE, { RA, RB } },
4313 { "tlbsx.", XRC(31,914,1), X_MASK, BOOKE, { RA, RB } },
4314 { "tlbsxe", XRC(31,915,0), X_MASK, BOOKE64, { RA, RB } },
4315 { "tlbsxe.", XRC(31,915,1), X_MASK, BOOKE64, { RA, RB } },
4317 { "slbmfee", X(31,915), XRA_MASK, PPC64, { RT, RB } },
4319 { "sthbrx", X(31,918), X_MASK, COM, { RS, RA, RB } },
4321 { "sraq", XRC(31,920,0), X_MASK, M601, { RA, RS, RB } },
4322 { "sraq.", XRC(31,920,1), X_MASK, M601, { RA, RS, RB } },
4324 { "srea", XRC(31,921,0), X_MASK, M601, { RA, RS, RB } },
4325 { "srea.", XRC(31,921,1), X_MASK, M601, { RA, RS, RB } },
4327 { "extsh", XRC(31,922,0), XRB_MASK, PPCCOM, { RA, RS } },
4328 { "exts", XRC(31,922,0), XRB_MASK, PWRCOM, { RA, RS } },
4329 { "extsh.", XRC(31,922,1), XRB_MASK, PPCCOM, { RA, RS } },
4330 { "exts.", XRC(31,922,1), XRB_MASK, PWRCOM, { RA, RS } },
4332 { "sthbrxe", X(31,926), X_MASK, BOOKE64, { RS, RA, RB } },
4334 { "stdxe", X(31,927), X_MASK, BOOKE64, { RS, RA, RB } },
4336 { "tlbre", X(31,946), X_MASK, BOOKE, { 0 } },
4338 { "tlbrehi", XTLB(31,946,0), XTLB_MASK, PPC403, { RT, RA } },
4339 { "tlbrelo", XTLB(31,946,1), XTLB_MASK, PPC403, { RT, RA } },
4340 { "tlbre", X(31,946), X_MASK, PPC403, { RS, RA, SH } },
4342 { "sraiq", XRC(31,952,0), X_MASK, M601, { RA, RS, SH } },
4343 { "sraiq.", XRC(31,952,1), X_MASK, M601, { RA, RS, SH } },
4345 { "extsb", XRC(31,954,0), XRB_MASK, PPC, { RA, RS} },
4346 { "extsb.", XRC(31,954,1), XRB_MASK, PPC, { RA, RS} },
4348 { "stduxe", X(31,959), X_MASK, BOOKE64, { RS, RAS, RB } },
4350 { "iccci", X(31,966), XRT_MASK, PPC403, { RA, RB } },
4352 { "tlbwe", X(31,978), X_MASK, BOOKE, { 0 } },
4354 { "tlbld", X(31,978), XRTRA_MASK, PPC, { RB } },
4356 { "tlbwehi", XTLB(31,978,0), XTLB_MASK, PPC403, { RT, RA } },
4357 { "tlbwelo", XTLB(31,978,1), XTLB_MASK, PPC403, { RT, RA } },
4358 { "tlbwe", X(31,978), X_MASK, PPC403, { RS, RA, SH } },
4360 { "icbi", X(31,982), XRT_MASK, PPC, { RA, RB } },
4362 { "stfiwx", X(31,983), X_MASK, PPC, { FRS, RA, RB } },
4364 { "extsw", XRC(31,986,0), XRB_MASK, PPC64 | BOOKE64,{ RA, RS } },
4365 { "extsw.", XRC(31,986,1), XRB_MASK, PPC64, { RA, RS } },
4367 { "icread", X(31,998), XRT_MASK, PPC403, { RA, RB } },
4369 { "icbie", X(31,990), XRT_MASK, BOOKE64, { RA, RB } },
4370 { "stfiwxe", X(31,991), X_MASK, BOOKE64, { FRS, RA, RB } },
4372 { "tlbli", X(31,1010), XRTRA_MASK, PPC, { RB } },
4374 { "dcbz", X(31,1014), XRT_MASK, PPC, { RA, RB } },
4375 { "dclz", X(31,1014), XRT_MASK, PPC, { RA, RB } },
4377 { "dcbze", X(31,1022), XRT_MASK, BOOKE64, { RA, RB } },
4379 { "lvebx", X(31, 7), X_MASK, PPCVEC, { VD, RA, RB } },
4380 { "lvehx", X(31, 39), X_MASK, PPCVEC, { VD, RA, RB } },
4381 { "lvewx", X(31, 71), X_MASK, PPCVEC, { VD, RA, RB } },
4382 { "lvsl", X(31, 6), X_MASK, PPCVEC, { VD, RA, RB } },
4383 { "lvsr", X(31, 38), X_MASK, PPCVEC, { VD, RA, RB } },
4384 { "lvx", X(31, 103), X_MASK, PPCVEC, { VD, RA, RB } },
4385 { "lvxl", X(31, 359), X_MASK, PPCVEC, { VD, RA, RB } },
4386 { "stvebx", X(31, 135), X_MASK, PPCVEC, { VS, RA, RB } },
4387 { "stvehx", X(31, 167), X_MASK, PPCVEC, { VS, RA, RB } },
4388 { "stvewx", X(31, 199), X_MASK, PPCVEC, { VS, RA, RB } },
4389 { "stvx", X(31, 231), X_MASK, PPCVEC, { VS, RA, RB } },
4390 { "stvxl", X(31, 487), X_MASK, PPCVEC, { VS, RA, RB } },
4392 { "lwz", OP(32), OP_MASK, PPCCOM, { RT, D, RA } },
4393 { "l", OP(32), OP_MASK, PWRCOM, { RT, D, RA } },
4395 { "lwzu", OP(33), OP_MASK, PPCCOM, { RT, D, RAL } },
4396 { "lu", OP(33), OP_MASK, PWRCOM, { RT, D, RA } },
4398 { "lbz", OP(34), OP_MASK, COM, { RT, D, RA } },
4400 { "lbzu", OP(35), OP_MASK, COM, { RT, D, RAL } },
4402 { "stw", OP(36), OP_MASK, PPCCOM, { RS, D, RA } },
4403 { "st", OP(36), OP_MASK, PWRCOM, { RS, D, RA } },
4405 { "stwu", OP(37), OP_MASK, PPCCOM, { RS, D, RAS } },
4406 { "stu", OP(37), OP_MASK, PWRCOM, { RS, D, RA } },
4408 { "stb", OP(38), OP_MASK, COM, { RS, D, RA } },
4410 { "stbu", OP(39), OP_MASK, COM, { RS, D, RAS } },
4412 { "lhz", OP(40), OP_MASK, COM, { RT, D, RA } },
4414 { "lhzu", OP(41), OP_MASK, COM, { RT, D, RAL } },
4416 { "lha", OP(42), OP_MASK, COM, { RT, D, RA } },
4418 { "lhau", OP(43), OP_MASK, COM, { RT, D, RAL } },
4420 { "sth", OP(44), OP_MASK, COM, { RS, D, RA } },
4422 { "sthu", OP(45), OP_MASK, COM, { RS, D, RAS } },
4424 { "lmw", OP(46), OP_MASK, PPCCOM, { RT, D, RAM } },
4425 { "lm", OP(46), OP_MASK, PWRCOM, { RT, D, RA } },
4427 { "stmw", OP(47), OP_MASK, PPCCOM, { RS, D, RA } },
4428 { "stm", OP(47), OP_MASK, PWRCOM, { RS, D, RA } },
4430 { "lfs", OP(48), OP_MASK, COM, { FRT, D, RA } },
4432 { "lfsu", OP(49), OP_MASK, COM, { FRT, D, RAS } },
4434 { "lfd", OP(50), OP_MASK, COM, { FRT, D, RA } },
4436 { "lfdu", OP(51), OP_MASK, COM, { FRT, D, RAS } },
4438 { "stfs", OP(52), OP_MASK, COM, { FRS, D, RA } },
4440 { "stfsu", OP(53), OP_MASK, COM, { FRS, D, RAS } },
4442 { "stfd", OP(54), OP_MASK, COM, { FRS, D, RA } },
4444 { "stfdu", OP(55), OP_MASK, COM, { FRS, D, RAS } },
4446 { "lq", OP(56), OP_MASK, POWER4, { RTQ, DQ, RAQ } },
4448 { "lfq", OP(56), OP_MASK, POWER2, { FRT, D, RA } },
4450 { "lfqu", OP(57), OP_MASK, POWER2, { FRT, D, RA } },
4452 { "lbze", DEO(58,0), DE_MASK, BOOKE64, { RT, DE, RA } },
4453 { "lbzue", DEO(58,1), DE_MASK, BOOKE64, { RT, DE, RAL } },
4454 { "lhze", DEO(58,2), DE_MASK, BOOKE64, { RT, DE, RA } },
4455 { "lhzue", DEO(58,3), DE_MASK, BOOKE64, { RT, DE, RAL } },
4456 { "lhae", DEO(58,4), DE_MASK, BOOKE64, { RT, DE, RA } },
4457 { "lhaue", DEO(58,5), DE_MASK, BOOKE64, { RT, DE, RAL } },
4458 { "lwze", DEO(58,6), DE_MASK, BOOKE64, { RT, DE, RA } },
4459 { "lwzue", DEO(58,7), DE_MASK, BOOKE64, { RT, DE, RAL } },
4460 { "stbe", DEO(58,8), DE_MASK, BOOKE64, { RS, DE, RA } },
4461 { "stbue", DEO(58,9), DE_MASK, BOOKE64, { RS, DE, RAS } },
4462 { "sthe", DEO(58,10), DE_MASK, BOOKE64, { RS, DE, RA } },
4463 { "sthue", DEO(58,11), DE_MASK, BOOKE64, { RS, DE, RAS } },
4464 { "stwe", DEO(58,14), DE_MASK, BOOKE64, { RS, DE, RA } },
4465 { "stwue", DEO(58,15), DE_MASK, BOOKE64, { RS, DE, RAS } },
4467 { "ld", DSO(58,0), DS_MASK, PPC64, { RT, DS, RA } },
4469 { "ldu", DSO(58,1), DS_MASK, PPC64, { RT, DS, RAL } },
4471 { "lwa", DSO(58,2), DS_MASK, PPC64, { RT, DS, RA } },
4473 { "fdivs", A(59,18,0), AFRC_MASK, PPC, { FRT, FRA, FRB } },
4474 { "fdivs.", A(59,18,1), AFRC_MASK, PPC, { FRT, FRA, FRB } },
4476 { "fsubs", A(59,20,0), AFRC_MASK, PPC, { FRT, FRA, FRB } },
4477 { "fsubs.", A(59,20,1), AFRC_MASK, PPC, { FRT, FRA, FRB } },
4479 { "fadds", A(59,21,0), AFRC_MASK, PPC, { FRT, FRA, FRB } },
4480 { "fadds.", A(59,21,1), AFRC_MASK, PPC, { FRT, FRA, FRB } },
4482 { "fsqrts", A(59,22,0), AFRAFRC_MASK, PPC, { FRT, FRB } },
4483 { "fsqrts.", A(59,22,1), AFRAFRC_MASK, PPC, { FRT, FRB } },
4485 { "fres", A(59,24,0), AFRAFRC_MASK, PPC, { FRT, FRB } },
4486 { "fres.", A(59,24,1), AFRAFRC_MASK, PPC, { FRT, FRB } },
4488 { "fmuls", A(59,25,0), AFRB_MASK, PPC, { FRT, FRA, FRC } },
4489 { "fmuls.", A(59,25,1), AFRB_MASK, PPC, { FRT, FRA, FRC } },
4491 { "fmsubs", A(59,28,0), A_MASK, PPC, { FRT,FRA,FRC,FRB } },
4492 { "fmsubs.", A(59,28,1), A_MASK, PPC, { FRT,FRA,FRC,FRB } },
4494 { "fmadds", A(59,29,0), A_MASK, PPC, { FRT,FRA,FRC,FRB } },
4495 { "fmadds.", A(59,29,1), A_MASK, PPC, { FRT,FRA,FRC,FRB } },
4497 { "fnmsubs", A(59,30,0), A_MASK, PPC, { FRT,FRA,FRC,FRB } },
4498 { "fnmsubs.",A(59,30,1), A_MASK, PPC, { FRT,FRA,FRC,FRB } },
4500 { "fnmadds", A(59,31,0), A_MASK, PPC, { FRT,FRA,FRC,FRB } },
4501 { "fnmadds.",A(59,31,1), A_MASK, PPC, { FRT,FRA,FRC,FRB } },
4503 { "stfq", OP(60), OP_MASK, POWER2, { FRS, D, RA } },
4505 { "stfqu", OP(61), OP_MASK, POWER2, { FRS, D, RA } },
4507 { "lde", DEO(62,0), DE_MASK, BOOKE64, { RT, DES, RA } },
4508 { "ldue", DEO(62,1), DE_MASK, BOOKE64, { RT, DES, RA } },
4509 { "lfse", DEO(62,4), DE_MASK, BOOKE64, { FRT, DES, RA } },
4510 { "lfsue", DEO(62,5), DE_MASK, BOOKE64, { FRT, DES, RAS } },
4511 { "lfde", DEO(62,6), DE_MASK, BOOKE64, { FRT, DES, RA } },
4512 { "lfdue", DEO(62,7), DE_MASK, BOOKE64, { FRT, DES, RAS } },
4513 { "stde", DEO(62,8), DE_MASK, BOOKE64, { RS, DES, RA } },
4514 { "stdue", DEO(62,9), DE_MASK, BOOKE64, { RS, DES, RAS } },
4515 { "stfse", DEO(62,12), DE_MASK, BOOKE64, { FRS, DES, RA } },
4516 { "stfsue", DEO(62,13), DE_MASK, BOOKE64, { FRS, DES, RAS } },
4517 { "stfde", DEO(62,14), DE_MASK, BOOKE64, { FRS, DES, RA } },
4518 { "stfdue", DEO(62,15), DE_MASK, BOOKE64, { FRS, DES, RAS } },
4520 { "std", DSO(62,0), DS_MASK, PPC64, { RS, DS, RA } },
4522 { "stdu", DSO(62,1), DS_MASK, PPC64, { RS, DS, RAS } },
4524 { "stq", DSO(62,2), DS_MASK, POWER4, { RSQ, DS, RA } },
4526 { "fcmpu", X(63,0), X_MASK|(3<<21), COM, { BF, FRA, FRB } },
4528 { "frsp", XRC(63,12,0), XRA_MASK, COM, { FRT, FRB } },
4529 { "frsp.", XRC(63,12,1), XRA_MASK, COM, { FRT, FRB } },
4531 { "fctiw", XRC(63,14,0), XRA_MASK, PPCCOM, { FRT, FRB } },
4532 { "fcir", XRC(63,14,0), XRA_MASK, POWER2, { FRT, FRB } },
4533 { "fctiw.", XRC(63,14,1), XRA_MASK, PPCCOM, { FRT, FRB } },
4534 { "fcir.", XRC(63,14,1), XRA_MASK, POWER2, { FRT, FRB } },
4536 { "fctiwz", XRC(63,15,0), XRA_MASK, PPCCOM, { FRT, FRB } },
4537 { "fcirz", XRC(63,15,0), XRA_MASK, POWER2, { FRT, FRB } },
4538 { "fctiwz.", XRC(63,15,1), XRA_MASK, PPCCOM, { FRT, FRB } },
4539 { "fcirz.", XRC(63,15,1), XRA_MASK, POWER2, { FRT, FRB } },
4541 { "fdiv", A(63,18,0), AFRC_MASK, PPCCOM, { FRT, FRA, FRB } },
4542 { "fd", A(63,18,0), AFRC_MASK, PWRCOM, { FRT, FRA, FRB } },
4543 { "fdiv.", A(63,18,1), AFRC_MASK, PPCCOM, { FRT, FRA, FRB } },
4544 { "fd.", A(63,18,1), AFRC_MASK, PWRCOM, { FRT, FRA, FRB } },
4546 { "fsub", A(63,20,0), AFRC_MASK, PPCCOM, { FRT, FRA, FRB } },
4547 { "fs", A(63,20,0), AFRC_MASK, PWRCOM, { FRT, FRA, FRB } },
4548 { "fsub.", A(63,20,1), AFRC_MASK, PPCCOM, { FRT, FRA, FRB } },
4549 { "fs.", A(63,20,1), AFRC_MASK, PWRCOM, { FRT, FRA, FRB } },
4551 { "fadd", A(63,21,0), AFRC_MASK, PPCCOM, { FRT, FRA, FRB } },
4552 { "fa", A(63,21,0), AFRC_MASK, PWRCOM, { FRT, FRA, FRB } },
4553 { "fadd.", A(63,21,1), AFRC_MASK, PPCCOM, { FRT, FRA, FRB } },
4554 { "fa.", A(63,21,1), AFRC_MASK, PWRCOM, { FRT, FRA, FRB } },
4556 { "fsqrt", A(63,22,0), AFRAFRC_MASK, PPCPWR2, { FRT, FRB } },
4557 { "fsqrt.", A(63,22,1), AFRAFRC_MASK, PPCPWR2, { FRT, FRB } },
4559 { "fsel", A(63,23,0), A_MASK, PPC, { FRT,FRA,FRC,FRB } },
4560 { "fsel.", A(63,23,1), A_MASK, PPC, { FRT,FRA,FRC,FRB } },
4562 { "fmul", A(63,25,0), AFRB_MASK, PPCCOM, { FRT, FRA, FRC } },
4563 { "fm", A(63,25,0), AFRB_MASK, PWRCOM, { FRT, FRA, FRC } },
4564 { "fmul.", A(63,25,1), AFRB_MASK, PPCCOM, { FRT, FRA, FRC } },
4565 { "fm.", A(63,25,1), AFRB_MASK, PWRCOM, { FRT, FRA, FRC } },
4567 { "frsqrte", A(63,26,0), AFRAFRC_MASK, PPC, { FRT, FRB } },
4568 { "frsqrte.",A(63,26,1), AFRAFRC_MASK, PPC, { FRT, FRB } },
4570 { "fmsub", A(63,28,0), A_MASK, PPCCOM, { FRT,FRA,FRC,FRB } },
4571 { "fms", A(63,28,0), A_MASK, PWRCOM, { FRT,FRA,FRC,FRB } },
4572 { "fmsub.", A(63,28,1), A_MASK, PPCCOM, { FRT,FRA,FRC,FRB } },
4573 { "fms.", A(63,28,1), A_MASK, PWRCOM, { FRT,FRA,FRC,FRB } },
4575 { "fmadd", A(63,29,0), A_MASK, PPCCOM, { FRT,FRA,FRC,FRB } },
4576 { "fma", A(63,29,0), A_MASK, PWRCOM, { FRT,FRA,FRC,FRB } },
4577 { "fmadd.", A(63,29,1), A_MASK, PPCCOM, { FRT,FRA,FRC,FRB } },
4578 { "fma.", A(63,29,1), A_MASK, PWRCOM, { FRT,FRA,FRC,FRB } },
4580 { "fnmsub", A(63,30,0), A_MASK, PPCCOM, { FRT,FRA,FRC,FRB } },
4581 { "fnms", A(63,30,0), A_MASK, PWRCOM, { FRT,FRA,FRC,FRB } },
4582 { "fnmsub.", A(63,30,1), A_MASK, PPCCOM, { FRT,FRA,FRC,FRB } },
4583 { "fnms.", A(63,30,1), A_MASK, PWRCOM, { FRT,FRA,FRC,FRB } },
4585 { "fnmadd", A(63,31,0), A_MASK, PPCCOM, { FRT,FRA,FRC,FRB } },
4586 { "fnma", A(63,31,0), A_MASK, PWRCOM, { FRT,FRA,FRC,FRB } },
4587 { "fnmadd.", A(63,31,1), A_MASK, PPCCOM, { FRT,FRA,FRC,FRB } },
4588 { "fnma.", A(63,31,1), A_MASK, PWRCOM, { FRT,FRA,FRC,FRB } },
4590 { "fcmpo", X(63,32), X_MASK|(3<<21), COM, { BF, FRA, FRB } },
4592 { "mtfsb1", XRC(63,38,0), XRARB_MASK, COM, { BT } },
4593 { "mtfsb1.", XRC(63,38,1), XRARB_MASK, COM, { BT } },
4595 { "fneg", XRC(63,40,0), XRA_MASK, COM, { FRT, FRB } },
4596 { "fneg.", XRC(63,40,1), XRA_MASK, COM, { FRT, FRB } },
4598 { "mcrfs", X(63,64), XRB_MASK|(3<<21)|(3<<16), COM, { BF, BFA } },
4600 { "mtfsb0", XRC(63,70,0), XRARB_MASK, COM, { BT } },
4601 { "mtfsb0.", XRC(63,70,1), XRARB_MASK, COM, { BT } },
4603 { "fmr", XRC(63,72,0), XRA_MASK, COM, { FRT, FRB } },
4604 { "fmr.", XRC(63,72,1), XRA_MASK, COM, { FRT, FRB } },
4606 { "mtfsfi", XRC(63,134,0), XRA_MASK|(3<<21)|(1<<11), COM, { BF, U } },
4607 { "mtfsfi.", XRC(63,134,1), XRA_MASK|(3<<21)|(1<<11), COM, { BF, U } },
4609 { "fnabs", XRC(63,136,0), XRA_MASK, COM, { FRT, FRB } },
4610 { "fnabs.", XRC(63,136,1), XRA_MASK, COM, { FRT, FRB } },
4612 { "fabs", XRC(63,264,0), XRA_MASK, COM, { FRT, FRB } },
4613 { "fabs.", XRC(63,264,1), XRA_MASK, COM, { FRT, FRB } },
4615 { "mffs", XRC(63,583,0), XRARB_MASK, COM, { FRT } },
4616 { "mffs.", XRC(63,583,1), XRARB_MASK, COM, { FRT } },
4618 { "mtfsf", XFL(63,711,0), XFL_MASK, COM, { FLM, FRB } },
4619 { "mtfsf.", XFL(63,711,1), XFL_MASK, COM, { FLM, FRB } },
4621 { "fctid", XRC(63,814,0), XRA_MASK, PPC64, { FRT, FRB } },
4622 { "fctid.", XRC(63,814,1), XRA_MASK, PPC64, { FRT, FRB } },
4624 { "fctidz", XRC(63,815,0), XRA_MASK, PPC64, { FRT, FRB } },
4625 { "fctidz.", XRC(63,815,1), XRA_MASK, PPC64, { FRT, FRB } },
4627 { "fcfid", XRC(63,846,0), XRA_MASK, PPC64, { FRT, FRB } },
4628 { "fcfid.", XRC(63,846,1), XRA_MASK, PPC64, { FRT, FRB } },
4632 const int powerpc_num_opcodes =
4633 sizeof (powerpc_opcodes) / sizeof (powerpc_opcodes[0]);
4635 /* The macro table. This is only used by the assembler. */
4637 /* The expressions of the form (-x ! 31) & (x | 31) have the value 0
4638 when x=0; 32-x when x is between 1 and 31; are negative if x is
4639 negative; and are 32 or more otherwise. This is what you want
4640 when, for instance, you are emulating a right shift by a
4641 rotate-left-and-mask, because the underlying instructions support
4642 shifts of size 0 but not shifts of size 32. By comparison, when
4643 extracting x bits from some word you want to use just 32-x, because
4644 the underlying instructions don't support extracting 0 bits but do
4645 support extracting the whole word (32 bits in this case). */
4647 const struct powerpc_macro powerpc_macros[] = {
4648 { "extldi", 4, PPC64, "rldicr %0,%1,%3,(%2)-1" },
4649 { "extldi.", 4, PPC64, "rldicr. %0,%1,%3,(%2)-1" },
4650 { "extrdi", 4, PPC64, "rldicl %0,%1,(%2)+(%3),64-(%2)" },
4651 { "extrdi.", 4, PPC64, "rldicl. %0,%1,(%2)+(%3),64-(%2)" },
4652 { "insrdi", 4, PPC64, "rldimi %0,%1,64-((%2)+(%3)),%3" },
4653 { "insrdi.", 4, PPC64, "rldimi. %0,%1,64-((%2)+(%3)),%3" },
4654 { "rotrdi", 3, PPC64, "rldicl %0,%1,(-(%2)!63)&((%2)|63),0" },
4655 { "rotrdi.", 3, PPC64, "rldicl. %0,%1,(-(%2)!63)&((%2)|63),0" },
4656 { "sldi", 3, PPC64, "rldicr %0,%1,%2,63-(%2)" },
4657 { "sldi.", 3, PPC64, "rldicr. %0,%1,%2,63-(%2)" },
4658 { "srdi", 3, PPC64, "rldicl %0,%1,(-(%2)!63)&((%2)|63),%2" },
4659 { "srdi.", 3, PPC64, "rldicl. %0,%1,(-(%2)!63)&((%2)|63),%2" },
4660 { "clrrdi", 3, PPC64, "rldicr %0,%1,0,63-(%2)" },
4661 { "clrrdi.", 3, PPC64, "rldicr. %0,%1,0,63-(%2)" },
4662 { "clrlsldi",4, PPC64, "rldic %0,%1,%3,(%2)-(%3)" },
4663 { "clrlsldi.",4, PPC64, "rldic. %0,%1,%3,(%2)-(%3)" },
4665 { "extlwi", 4, PPCCOM, "rlwinm %0,%1,%3,0,(%2)-1" },
4666 { "extlwi.", 4, PPCCOM, "rlwinm. %0,%1,%3,0,(%2)-1" },
4667 { "extrwi", 4, PPCCOM, "rlwinm %0,%1,((%2)+(%3))&((%2)+(%3)<>32),32-(%2),31" },
4668 { "extrwi.", 4, PPCCOM, "rlwinm. %0,%1,((%2)+(%3))&((%2)+(%3)<>32),32-(%2),31" },
4669 { "inslwi", 4, PPCCOM, "rlwimi %0,%1,(-(%3)!31)&((%3)|31),%3,(%2)+(%3)-1" },
4670 { "inslwi.", 4, PPCCOM, "rlwimi. %0,%1,(-(%3)!31)&((%3)|31),%3,(%2)+(%3)-1"},
4671 { "insrwi", 4, PPCCOM, "rlwimi %0,%1,32-((%2)+(%3)),%3,(%2)+(%3)-1" },
4672 { "insrwi.", 4, PPCCOM, "rlwimi. %0,%1,32-((%2)+(%3)),%3,(%2)+(%3)-1"},
4673 { "rotrwi", 3, PPCCOM, "rlwinm %0,%1,(-(%2)!31)&((%2)|31),0,31" },
4674 { "rotrwi.", 3, PPCCOM, "rlwinm. %0,%1,(-(%2)!31)&((%2)|31),0,31" },
4675 { "slwi", 3, PPCCOM, "rlwinm %0,%1,%2,0,31-(%2)" },
4676 { "sli", 3, PWRCOM, "rlinm %0,%1,%2,0,31-(%2)" },
4677 { "slwi.", 3, PPCCOM, "rlwinm. %0,%1,%2,0,31-(%2)" },
4678 { "sli.", 3, PWRCOM, "rlinm. %0,%1,%2,0,31-(%2)" },
4679 { "srwi", 3, PPCCOM, "rlwinm %0,%1,(-(%2)!31)&((%2)|31),%2,31" },
4680 { "sri", 3, PWRCOM, "rlinm %0,%1,(-(%2)!31)&((%2)|31),%2,31" },
4681 { "srwi.", 3, PPCCOM, "rlwinm. %0,%1,(-(%2)!31)&((%2)|31),%2,31" },
4682 { "sri.", 3, PWRCOM, "rlinm. %0,%1,(-(%2)!31)&((%2)|31),%2,31" },
4683 { "clrrwi", 3, PPCCOM, "rlwinm %0,%1,0,0,31-(%2)" },
4684 { "clrrwi.", 3, PPCCOM, "rlwinm. %0,%1,0,0,31-(%2)" },
4685 { "clrlslwi",4, PPCCOM, "rlwinm %0,%1,%3,(%2)-(%3),31-(%3)" },
4686 { "clrlslwi.",4, PPCCOM, "rlwinm. %0,%1,%3,(%2)-(%3),31-(%3)" },
4689 const int powerpc_num_macros =
4690 sizeof (powerpc_macros) / sizeof (powerpc_macros[0]);