1 /* ppc-opc.c -- PowerPC opcode list
2 Copyright 1994, 1995, 1996, 1997, 1998, 2000, 2001, 2002
3 Free Software Foundation, Inc.
4 Written by Ian Lance Taylor, Cygnus Support
6 This file is part of GDB, GAS, and the GNU binutils.
8 GDB, GAS, and the GNU binutils are free software; you can redistribute
9 them and/or modify them under the terms of the GNU General Public
10 License as published by the Free Software Foundation; either version
11 2, or (at your option) any later version.
13 GDB, GAS, and the GNU binutils are distributed in the hope that they
14 will be useful, but WITHOUT ANY WARRANTY; without even the implied
15 warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See
16 the GNU General Public License for more details.
18 You should have received a copy of the GNU General Public License
19 along with this file; see the file COPYING. If not, write to the Free
20 Software Foundation, 59 Temple Place - Suite 330, Boston, MA
25 #include "opcode/ppc.h"
28 /* This file holds the PowerPC opcode table. The opcode table
29 includes almost all of the extended instruction mnemonics. This
30 permits the disassembler to use them, and simplifies the assembler
31 logic, at the cost of increasing the table size. The table is
32 strictly constant data, so the compiler should be able to put it in
35 This file also holds the operand table. All knowledge about
36 inserting operands into instructions and vice-versa is kept in this
39 /* Local insertion and extraction functions. */
41 static unsigned long insert_bat
42 PARAMS ((unsigned long, long, int, const char **));
43 static long extract_bat
44 PARAMS ((unsigned long, int, int *));
45 static unsigned long insert_bba
46 PARAMS ((unsigned long, long, int, const char **));
47 static long extract_bba
48 PARAMS ((unsigned long, int, int *));
49 static unsigned long insert_bd
50 PARAMS ((unsigned long, long, int, const char **));
51 static long extract_bd
52 PARAMS ((unsigned long, int, int *));
53 static unsigned long insert_bdm
54 PARAMS ((unsigned long, long, int, const char **));
55 static long extract_bdm
56 PARAMS ((unsigned long, int, int *));
57 static unsigned long insert_bdp
58 PARAMS ((unsigned long, long, int, const char **));
59 static long extract_bdp
60 PARAMS ((unsigned long, int, int *));
63 static unsigned long insert_bo
64 PARAMS ((unsigned long, long, int, const char **));
65 static long extract_bo
66 PARAMS ((unsigned long, int, int *));
67 static unsigned long insert_boe
68 PARAMS ((unsigned long, long, int, const char **));
69 static long extract_boe
70 PARAMS ((unsigned long, int, int *));
71 static unsigned long insert_ds
72 PARAMS ((unsigned long, long, int, const char **));
73 static long extract_ds
74 PARAMS ((unsigned long, int, int *));
75 static unsigned long insert_de
76 PARAMS ((unsigned long, long, int, const char **));
77 static long extract_de
78 PARAMS ((unsigned long, int, int *));
79 static unsigned long insert_des
80 PARAMS ((unsigned long, long, int, const char **));
81 static long extract_des
82 PARAMS ((unsigned long, int, int *));
83 static unsigned long insert_li
84 PARAMS ((unsigned long, long, int, const char **));
85 static long extract_li
86 PARAMS ((unsigned long, int, int *));
87 static unsigned long insert_mbe
88 PARAMS ((unsigned long, long, int, const char **));
89 static long extract_mbe
90 PARAMS ((unsigned long, int, int *));
91 static unsigned long insert_mb6
92 PARAMS ((unsigned long, long, int, const char **));
93 static long extract_mb6
94 PARAMS ((unsigned long, int, int *));
95 static unsigned long insert_nb
96 PARAMS ((unsigned long, long, int, const char **));
97 static long extract_nb
98 PARAMS ((unsigned long, int, int *));
99 static unsigned long insert_nsi
100 PARAMS ((unsigned long, long, int, const char **));
101 static long extract_nsi
102 PARAMS ((unsigned long, int, int *));
103 static unsigned long insert_ral
104 PARAMS ((unsigned long, long, int, const char **));
105 static unsigned long insert_ram
106 PARAMS ((unsigned long, long, int, const char **));
107 static unsigned long insert_ras
108 PARAMS ((unsigned long, long, int, const char **));
109 static unsigned long insert_rbs
110 PARAMS ((unsigned long, long, int, const char **));
111 static long extract_rbs
112 PARAMS ((unsigned long, int, int *));
113 static unsigned long insert_sh6
114 PARAMS ((unsigned long, long, int, const char **));
115 static long extract_sh6
116 PARAMS ((unsigned long, int, int *));
117 static unsigned long insert_spr
118 PARAMS ((unsigned long, long, int, const char **));
119 static long extract_spr
120 PARAMS ((unsigned long, int, int *));
121 static unsigned long insert_tbr
122 PARAMS ((unsigned long, long, int, const char **));
123 static long extract_tbr
124 PARAMS ((unsigned long, int, int *));
126 /* The operands table.
128 The fields are bits, shift, insert, extract, flags.
130 We used to put parens around the various additions, like the one
131 for BA just below. However, that caused trouble with feeble
132 compilers with a limit on depth of a parenthesized expression, like
133 (reportedly) the compiler in Microsoft Developer Studio 5. So we
134 omit the parens, since the macros are never used in a context where
135 the addition will be ambiguous. */
137 const struct powerpc_operand powerpc_operands[] =
139 /* The zero index is used to indicate the end of the list of
144 /* The BA field in an XL form instruction. */
145 #define BA UNUSED + 1
146 #define BA_MASK (0x1f << 16)
147 { 5, 16, 0, 0, PPC_OPERAND_CR },
149 /* The BA field in an XL form instruction when it must be the same
150 as the BT field in the same instruction. */
152 { 5, 16, insert_bat, extract_bat, PPC_OPERAND_FAKE },
154 /* The BB field in an XL form instruction. */
156 #define BB_MASK (0x1f << 11)
157 { 5, 11, 0, 0, PPC_OPERAND_CR },
159 /* The BB field in an XL form instruction when it must be the same
160 as the BA field in the same instruction. */
162 { 5, 11, insert_bba, extract_bba, PPC_OPERAND_FAKE },
164 /* The BD field in a B form instruction. The lower two bits are
167 { 16, 0, insert_bd, extract_bd, PPC_OPERAND_RELATIVE | PPC_OPERAND_SIGNED },
169 /* The BD field in a B form instruction when absolute addressing is
172 { 16, 0, insert_bd, extract_bd, PPC_OPERAND_ABSOLUTE | PPC_OPERAND_SIGNED },
174 /* The BD field in a B form instruction when the - modifier is used.
175 This sets the y bit of the BO field appropriately. */
177 { 16, 0, insert_bdm, extract_bdm,
178 PPC_OPERAND_RELATIVE | PPC_OPERAND_SIGNED },
180 /* The BD field in a B form instruction when the - modifier is used
181 and absolute address is used. */
183 { 16, 0, insert_bdm, extract_bdm,
184 PPC_OPERAND_ABSOLUTE | PPC_OPERAND_SIGNED },
186 /* The BD field in a B form instruction when the + modifier is used.
187 This sets the y bit of the BO field appropriately. */
189 { 16, 0, insert_bdp, extract_bdp,
190 PPC_OPERAND_RELATIVE | PPC_OPERAND_SIGNED },
192 /* The BD field in a B form instruction when the + modifier is used
193 and absolute addressing is used. */
195 { 16, 0, insert_bdp, extract_bdp,
196 PPC_OPERAND_ABSOLUTE | PPC_OPERAND_SIGNED },
198 /* The BF field in an X or XL form instruction. */
200 { 3, 23, 0, 0, PPC_OPERAND_CR },
202 /* An optional BF field. This is used for comparison instructions,
203 in which an omitted BF field is taken as zero. */
205 { 3, 23, 0, 0, PPC_OPERAND_CR | PPC_OPERAND_OPTIONAL },
207 /* The BFA field in an X or XL form instruction. */
209 { 3, 18, 0, 0, PPC_OPERAND_CR },
211 /* The BI field in a B form or XL form instruction. */
213 #define BI_MASK (0x1f << 16)
214 { 5, 16, 0, 0, PPC_OPERAND_CR },
216 /* The BO field in a B form instruction. Certain values are
219 #define BO_MASK (0x1f << 21)
220 { 5, 21, insert_bo, extract_bo, 0 },
222 /* The BO field in a B form instruction when the + or - modifier is
223 used. This is like the BO field, but it must be even. */
225 { 5, 21, insert_boe, extract_boe, 0 },
227 /* The BT field in an X or XL form instruction. */
229 { 5, 21, 0, 0, PPC_OPERAND_CR },
231 /* The condition register number portion of the BI field in a B form
232 or XL form instruction. This is used for the extended
233 conditional branch mnemonics, which set the lower two bits of the
234 BI field. This field is optional. */
236 { 3, 18, 0, 0, PPC_OPERAND_CR | PPC_OPERAND_OPTIONAL },
238 /* The CT field in an X form instruction. */
240 { 5, 21, 0, 0, PPC_OPERAND_OPTIONAL },
242 /* The D field in a D form instruction. This is a displacement off
243 a register, and implies that the next operand is a register in
246 { 16, 0, 0, 0, PPC_OPERAND_PARENS | PPC_OPERAND_SIGNED },
248 /* The DE field in a DE form instruction. This is like D, but is 12
251 { 14, 0, insert_de, extract_de, PPC_OPERAND_PARENS },
253 /* The DES field in a DES form instruction. This is like DS, but is 14
254 bits only (12 stored.) */
256 { 14, 0, insert_des, extract_des, PPC_OPERAND_PARENS | PPC_OPERAND_SIGNED },
258 /* The DS field in a DS form instruction. This is like D, but the
259 lower two bits are forced to zero. */
261 { 16, 0, insert_ds, extract_ds,
262 PPC_OPERAND_PARENS | PPC_OPERAND_SIGNED | PPC_OPERAND_DS },
264 /* The E field in a wrteei instruction. */
268 /* The FL1 field in a POWER SC form instruction. */
272 /* The FL2 field in a POWER SC form instruction. */
276 /* The FLM field in an XFL form instruction. */
280 /* The FRA field in an X or A form instruction. */
282 #define FRA_MASK (0x1f << 16)
283 { 5, 16, 0, 0, PPC_OPERAND_FPR },
285 /* The FRB field in an X or A form instruction. */
287 #define FRB_MASK (0x1f << 11)
288 { 5, 11, 0, 0, PPC_OPERAND_FPR },
290 /* The FRC field in an A form instruction. */
292 #define FRC_MASK (0x1f << 6)
293 { 5, 6, 0, 0, PPC_OPERAND_FPR },
295 /* The FRS field in an X form instruction or the FRT field in a D, X
296 or A form instruction. */
299 { 5, 21, 0, 0, PPC_OPERAND_FPR },
301 /* The FXM field in an XFX instruction. */
303 #define FXM_MASK (0xff << 12)
306 /* The L field in a D or X form instruction. */
308 { 1, 21, 0, 0, PPC_OPERAND_OPTIONAL },
310 /* The LEV field in a POWER SC form instruction. */
314 /* The LI field in an I form instruction. The lower two bits are
317 { 26, 0, insert_li, extract_li, PPC_OPERAND_RELATIVE | PPC_OPERAND_SIGNED },
319 /* The LI field in an I form instruction when used as an absolute
322 { 26, 0, insert_li, extract_li, PPC_OPERAND_ABSOLUTE | PPC_OPERAND_SIGNED },
324 /* The LS field in an X (sync) form instruction. */
326 { 2, 21, 0, 0, PPC_OPERAND_OPTIONAL },
328 /* The MB field in an M form instruction. */
330 #define MB_MASK (0x1f << 6)
333 /* The ME field in an M form instruction. */
335 #define ME_MASK (0x1f << 1)
338 /* The MB and ME fields in an M form instruction expressed a single
339 operand which is a bitmask indicating which bits to select. This
340 is a two operand form using PPC_OPERAND_NEXT. See the
341 description in opcode/ppc.h for what this means. */
343 { 5, 6, 0, 0, PPC_OPERAND_OPTIONAL | PPC_OPERAND_NEXT },
344 { 32, 0, insert_mbe, extract_mbe, 0 },
346 /* The MB or ME field in an MD or MDS form instruction. The high
347 bit is wrapped to the low end. */
350 #define MB6_MASK (0x3f << 5)
351 { 6, 5, insert_mb6, extract_mb6, 0 },
353 /* The MO field in an mbar instruction. */
357 /* The NB field in an X form instruction. The value 32 is stored as
360 { 6, 11, insert_nb, extract_nb, 0 },
362 /* The NSI field in a D form instruction. This is the same as the
363 SI field, only negated. */
365 { 16, 0, insert_nsi, extract_nsi,
366 PPC_OPERAND_NEGATIVE | PPC_OPERAND_SIGNED },
368 /* The RA field in an D, DS, X, XO, M, or MDS form instruction. */
370 #define RA_MASK (0x1f << 16)
371 { 5, 16, 0, 0, PPC_OPERAND_GPR },
373 /* The RA field in a D or X form instruction which is an updating
374 load, which means that the RA field may not be zero and may not
375 equal the RT field. */
377 { 5, 16, insert_ral, 0, PPC_OPERAND_GPR },
379 /* The RA field in an lmw instruction, which has special value
382 { 5, 16, insert_ram, 0, PPC_OPERAND_GPR },
384 /* The RA field in a D or X form instruction which is an updating
385 store or an updating floating point load, which means that the RA
386 field may not be zero. */
388 { 5, 16, insert_ras, 0, PPC_OPERAND_GPR },
390 /* The RB field in an X, XO, M, or MDS form instruction. */
392 #define RB_MASK (0x1f << 11)
393 { 5, 11, 0, 0, PPC_OPERAND_GPR },
395 /* The RB field in an X form instruction when it must be the same as
396 the RS field in the instruction. This is used for extended
397 mnemonics like mr. */
399 { 5, 1, insert_rbs, extract_rbs, PPC_OPERAND_FAKE },
401 /* The RS field in a D, DS, X, XFX, XS, M, MD or MDS form
402 instruction or the RT field in a D, DS, X, XFX or XO form
406 #define RT_MASK (0x1f << 21)
407 { 5, 21, 0, 0, PPC_OPERAND_GPR },
409 /* The SH field in an X or M form instruction. */
411 #define SH_MASK (0x1f << 11)
414 /* The SH field in an MD form instruction. This is split. */
416 #define SH6_MASK ((0x1f << 11) | (1 << 1))
417 { 6, 1, insert_sh6, extract_sh6, 0 },
419 /* The SI field in a D form instruction. */
421 { 16, 0, 0, 0, PPC_OPERAND_SIGNED },
423 /* The SI field in a D form instruction when we accept a wide range
424 of positive values. */
425 #define SISIGNOPT SI + 1
426 { 16, 0, 0, 0, PPC_OPERAND_SIGNED | PPC_OPERAND_SIGNOPT },
428 /* The SPR field in an XFX form instruction. This is flipped--the
429 lower 5 bits are stored in the upper 5 and vice- versa. */
430 #define SPR SISIGNOPT + 1
431 #define SPR_MASK (0x3ff << 11)
432 { 10, 11, insert_spr, extract_spr, 0 },
434 /* The BAT index number in an XFX form m[ft]ibat[lu] instruction. */
435 #define SPRBAT SPR + 1
436 #define SPRBAT_MASK (0x3 << 17)
439 /* The SPRG register number in an XFX form m[ft]sprg instruction. */
440 #define SPRG SPRBAT + 1
441 #define SPRG_MASK (0x3 << 16)
444 /* The SR field in an X form instruction. */
448 /* The STRM field in an X AltiVec form instruction. */
450 #define STRM_MASK (0x3 << 21)
453 /* The SV field in a POWER SC form instruction. */
457 /* The TBR field in an XFX form instruction. This is like the SPR
458 field, but it is optional. */
460 { 10, 11, insert_tbr, extract_tbr, PPC_OPERAND_OPTIONAL },
462 /* The TO field in a D or X form instruction. */
464 #define TO_MASK (0x1f << 21)
467 /* The U field in an X form instruction. */
471 /* The UI field in a D form instruction. */
475 /* The VA field in a VA, VX or VXR form instruction. */
477 #define VA_MASK (0x1f << 16)
478 { 5, 16, 0, 0, PPC_OPERAND_VR },
480 /* The VB field in a VA, VX or VXR form instruction. */
482 #define VB_MASK (0x1f << 11)
483 { 5, 11, 0, 0, PPC_OPERAND_VR },
485 /* The VC field in a VA form instruction. */
487 #define VC_MASK (0x1f << 6)
488 { 5, 6, 0, 0, PPC_OPERAND_VR },
490 /* The VD or VS field in a VA, VX, VXR or X form instruction. */
493 #define VD_MASK (0x1f << 21)
494 { 5, 21, 0, 0, PPC_OPERAND_VR },
496 /* The SIMM field in a VX form instruction. */
498 { 5, 16, 0, 0, PPC_OPERAND_SIGNED},
500 /* The UIMM field in a VX form instruction. */
501 #define UIMM SIMM + 1
504 /* The SHB field in a VA form instruction. */
510 #define WS_MASK (0x7 << 11)
515 /* The functions used to insert and extract complicated operands. */
517 /* The BA field in an XL form instruction when it must be the same as
518 the BT field in the same instruction. This operand is marked FAKE.
519 The insertion function just copies the BT field into the BA field,
520 and the extraction function just checks that the fields are the
525 insert_bat (insn, value, dialect, errmsg)
527 long value ATTRIBUTE_UNUSED;
528 int dialect ATTRIBUTE_UNUSED;
529 const char **errmsg ATTRIBUTE_UNUSED;
531 return insn | (((insn >> 21) & 0x1f) << 16);
535 extract_bat (insn, dialect, invalid)
537 int dialect ATTRIBUTE_UNUSED;
540 if (invalid != (int *) NULL
541 && ((insn >> 21) & 0x1f) != ((insn >> 16) & 0x1f))
546 /* The BB field in an XL form instruction when it must be the same as
547 the BA field in the same instruction. This operand is marked FAKE.
548 The insertion function just copies the BA field into the BB field,
549 and the extraction function just checks that the fields are the
554 insert_bba (insn, value, dialect, errmsg)
556 long value ATTRIBUTE_UNUSED;
557 int dialect ATTRIBUTE_UNUSED;
558 const char **errmsg ATTRIBUTE_UNUSED;
560 return insn | (((insn >> 16) & 0x1f) << 11);
564 extract_bba (insn, dialect, invalid)
566 int dialect ATTRIBUTE_UNUSED;
569 if (invalid != (int *) NULL
570 && ((insn >> 16) & 0x1f) != ((insn >> 11) & 0x1f))
575 /* The BD field in a B form instruction. The lower two bits are
580 insert_bd (insn, value, dialect, errmsg)
583 int dialect ATTRIBUTE_UNUSED;
584 const char **errmsg ATTRIBUTE_UNUSED;
586 return insn | (value & 0xfffc);
591 extract_bd (insn, dialect, invalid)
593 int dialect ATTRIBUTE_UNUSED;
594 int *invalid ATTRIBUTE_UNUSED;
596 return ((insn & 0xfffc) ^ 0x8000) - 0x8000;
599 /* The BD field in a B form instruction when the - modifier is used.
600 This modifier means that the branch is not expected to be taken.
601 For chips built to versions of the architecture prior to version 2
602 (ie. not Power4 compatible), we set the y bit of the BO field to 1
603 if the offset is negative. When extracting, we require that the y
604 bit be 1 and that the offset be positive, since if the y bit is 0
605 we just want to print the normal form of the instruction.
606 Power4 compatible targets use two bits, "a", and "t", instead of
607 the "y" bit. "at" == 00 => no hint, "at" == 01 => unpredictable,
608 "at" == 10 => not taken, "at" == 11 => taken. The "t" bit is 00001
609 in BO field, the "a" bit is 00010 for branch on CR(BI) and 01000
610 for branch on CTR. We only handle the taken/not-taken hint here. */
614 insert_bdm (insn, value, dialect, errmsg)
618 const char **errmsg ATTRIBUTE_UNUSED;
620 if ((dialect & PPC_OPCODE_POWER4) == 0)
622 if ((value & 0x8000) != 0)
627 if ((insn & (0x14 << 21)) == (0x04 << 21))
629 else if ((insn & (0x14 << 21)) == (0x10 << 21))
632 return insn | (value & 0xfffc);
636 extract_bdm (insn, dialect, invalid)
641 if (invalid != (int *) NULL)
643 if ((dialect & PPC_OPCODE_POWER4) == 0)
645 if (((insn & (1 << 21)) == 0) != ((insn & (1 << 15)) == 0))
650 if ((insn & (0x17 << 21)) != (0x06 << 21)
651 && (insn & (0x1d << 21)) != (0x18 << 21))
655 return ((insn & 0xfffc) ^ 0x8000) - 0x8000;
658 /* The BD field in a B form instruction when the + modifier is used.
659 This is like BDM, above, except that the branch is expected to be
664 insert_bdp (insn, value, dialect, errmsg)
668 const char **errmsg ATTRIBUTE_UNUSED;
670 if ((dialect & PPC_OPCODE_POWER4) == 0)
672 if ((value & 0x8000) == 0)
677 if ((insn & (0x14 << 21)) == (0x04 << 21))
679 else if ((insn & (0x14 << 21)) == (0x10 << 21))
682 return insn | (value & 0xfffc);
686 extract_bdp (insn, dialect, invalid)
691 if (invalid != (int *) NULL)
693 if ((dialect & PPC_OPCODE_POWER4) == 0)
695 if (((insn & (1 << 21)) == 0) == ((insn & (1 << 15)) == 0))
700 if ((insn & (0x17 << 21)) != (0x07 << 21)
701 && (insn & (0x1d << 21)) != (0x19 << 21))
705 return ((insn & 0xfffc) ^ 0x8000) - 0x8000;
708 /* Check for legal values of a BO field. */
711 valid_bo (value, dialect)
715 if ((dialect & PPC_OPCODE_POWER4) == 0)
717 /* Certain encodings have bits that are required to be zero.
718 These are (z must be zero, y may be anything):
725 switch (value & 0x14)
731 return (value & 0x2) == 0;
733 return (value & 0x8) == 0;
735 return value == 0x14;
740 /* Certain encodings have bits that are required to be zero.
741 These are (z must be zero, a & t may be anything):
752 if ((value & 0x14) == 0)
753 return (value & 0x1) == 0;
754 else if ((value & 0x14) == 0x14)
755 return value == 0x14;
761 /* The BO field in a B form instruction. Warn about attempts to set
762 the field to an illegal value. */
765 insert_bo (insn, value, dialect, errmsg)
771 if (errmsg != (const char **) NULL
772 && ! valid_bo (value, dialect))
773 *errmsg = _("invalid conditional option");
774 return insn | ((value & 0x1f) << 21);
778 extract_bo (insn, dialect, invalid)
785 value = (insn >> 21) & 0x1f;
786 if (invalid != (int *) NULL
787 && ! valid_bo (value, dialect))
792 /* The BO field in a B form instruction when the + or - modifier is
793 used. This is like the BO field, but it must be even. When
794 extracting it, we force it to be even. */
797 insert_boe (insn, value, dialect, errmsg)
803 if (errmsg != (const char **) NULL)
805 if (! valid_bo (value, dialect))
806 *errmsg = _("invalid conditional option");
807 else if ((value & 1) != 0)
808 *errmsg = _("attempt to set y bit when using + or - modifier");
810 return insn | ((value & 0x1f) << 21);
814 extract_boe (insn, dialect, invalid)
821 value = (insn >> 21) & 0x1f;
822 if (invalid != (int *) NULL
823 && ! valid_bo (value, dialect))
828 /* The DS field in a DS form instruction. This is like D, but the
829 lower two bits are forced to zero. */
833 insert_ds (insn, value, dialect, errmsg)
836 int dialect ATTRIBUTE_UNUSED;
839 if ((value & 3) != 0 && errmsg != NULL)
840 *errmsg = _("offset not a multiple of 4");
841 return insn | (value & 0xfffc);
846 extract_ds (insn, dialect, invalid)
848 int dialect ATTRIBUTE_UNUSED;
849 int *invalid ATTRIBUTE_UNUSED;
851 return ((insn & 0xfffc) ^ 0x8000) - 0x8000;
854 /* The DE field in a DE form instruction. */
858 insert_de (insn, value, dialect, errmsg)
861 int dialect ATTRIBUTE_UNUSED;
864 if ((value > 2047 || value < -2048) && errmsg != NULL)
865 *errmsg = _("offset not between -2048 and 2047");
866 return insn | ((value << 4) & 0xfff0);
871 extract_de (insn, dialect, invalid)
873 int dialect ATTRIBUTE_UNUSED;
874 int *invalid ATTRIBUTE_UNUSED;
876 return (insn & 0xfff0) >> 4;
879 /* The DES field in a DES form instruction. */
883 insert_des (insn, value, dialect, errmsg)
886 int dialect ATTRIBUTE_UNUSED;
889 if ((value > 8191 || value < -8192) && errmsg != NULL)
890 *errmsg = _("offset not between -8192 and 8191");
891 else if ((value & 3) != 0 && errmsg != NULL)
892 *errmsg = _("offset not a multiple of 4");
893 return insn | ((value << 2) & 0xfff0);
898 extract_des (insn, dialect, invalid)
900 int dialect ATTRIBUTE_UNUSED;
901 int *invalid ATTRIBUTE_UNUSED;
903 return (((insn >> 2) & 0x3ffc) ^ 0x2000) - 0x2000;
906 /* The LI field in an I form instruction. The lower two bits are
911 insert_li (insn, value, dialect, errmsg)
914 int dialect ATTRIBUTE_UNUSED;
917 if ((value & 3) != 0 && errmsg != (const char **) NULL)
918 *errmsg = _("ignoring least significant bits in branch offset");
919 return insn | (value & 0x3fffffc);
924 extract_li (insn, dialect, invalid)
926 int dialect ATTRIBUTE_UNUSED;
927 int *invalid ATTRIBUTE_UNUSED;
929 return ((insn & 0x3fffffc) ^ 0x2000000) - 0x2000000;
932 /* The MB and ME fields in an M form instruction expressed as a single
933 operand which is itself a bitmask. The extraction function always
934 marks it as invalid, since we never want to recognize an
935 instruction which uses a field of this type. */
938 insert_mbe (insn, value, dialect, errmsg)
941 int dialect ATTRIBUTE_UNUSED;
944 unsigned long uval, mask;
945 int mb, me, mx, count, last;
951 if (errmsg != (const char **) NULL)
952 *errmsg = _("illegal bitmask");
964 /* mb: location of last 0->1 transition */
965 /* me: location of last 1->0 transition */
966 /* count: # transitions */
968 for (mx = 0, mask = (long) 1 << 31; mx < 32; ++mx, mask >>= 1)
970 if ((uval & mask) && !last)
976 else if (!(uval & mask) && last)
986 if (count != 2 && (count != 0 || ! last))
988 if (errmsg != (const char **) NULL)
989 *errmsg = _("illegal bitmask");
992 return insn | (mb << 6) | ((me - 1) << 1);
996 extract_mbe (insn, dialect, invalid)
998 int dialect ATTRIBUTE_UNUSED;
1005 if (invalid != (int *) NULL)
1008 mb = (insn >> 6) & 0x1f;
1009 me = (insn >> 1) & 0x1f;
1013 for (i = mb; i <= me; i++)
1014 ret |= (long) 1 << (31 - i);
1016 else if (mb == me + 1)
1018 else /* (mb > me + 1) */
1021 for (i = me + 1; i < mb; i++)
1022 ret &= ~ ((long) 1 << (31 - i));
1027 /* The MB or ME field in an MD or MDS form instruction. The high bit
1028 is wrapped to the low end. */
1031 static unsigned long
1032 insert_mb6 (insn, value, dialect, errmsg)
1035 int dialect ATTRIBUTE_UNUSED;
1036 const char **errmsg ATTRIBUTE_UNUSED;
1038 return insn | ((value & 0x1f) << 6) | (value & 0x20);
1043 extract_mb6 (insn, dialect, invalid)
1045 int dialect ATTRIBUTE_UNUSED;
1046 int *invalid ATTRIBUTE_UNUSED;
1048 return ((insn >> 6) & 0x1f) | (insn & 0x20);
1051 /* The NB field in an X form instruction. The value 32 is stored as
1054 static unsigned long
1055 insert_nb (insn, value, dialect, errmsg)
1058 int dialect ATTRIBUTE_UNUSED;
1059 const char **errmsg;
1061 if (value < 0 || value > 32)
1062 *errmsg = _("value out of range");
1065 return insn | ((value & 0x1f) << 11);
1070 extract_nb (insn, dialect, invalid)
1072 int dialect ATTRIBUTE_UNUSED;
1073 int *invalid ATTRIBUTE_UNUSED;
1077 ret = (insn >> 11) & 0x1f;
1083 /* The NSI field in a D form instruction. This is the same as the SI
1084 field, only negated. The extraction function always marks it as
1085 invalid, since we never want to recognize an instruction which uses
1086 a field of this type. */
1089 static unsigned long
1090 insert_nsi (insn, value, dialect, errmsg)
1093 int dialect ATTRIBUTE_UNUSED;
1094 const char **errmsg ATTRIBUTE_UNUSED;
1096 return insn | ((- value) & 0xffff);
1100 extract_nsi (insn, dialect, invalid)
1102 int dialect ATTRIBUTE_UNUSED;
1105 if (invalid != (int *) NULL)
1107 return - (((insn & 0xffff) ^ 0x8000) - 0x8000);
1110 /* The RA field in a D or X form instruction which is an updating
1111 load, which means that the RA field may not be zero and may not
1112 equal the RT field. */
1114 static unsigned long
1115 insert_ral (insn, value, dialect, errmsg)
1118 int dialect ATTRIBUTE_UNUSED;
1119 const char **errmsg;
1122 || (unsigned long) value == ((insn >> 21) & 0x1f))
1123 *errmsg = "invalid register operand when updating";
1124 return insn | ((value & 0x1f) << 16);
1127 /* The RA field in an lmw instruction, which has special value
1130 static unsigned long
1131 insert_ram (insn, value, dialect, errmsg)
1134 int dialect ATTRIBUTE_UNUSED;
1135 const char **errmsg;
1137 if ((unsigned long) value >= ((insn >> 21) & 0x1f))
1138 *errmsg = _("index register in load range");
1139 return insn | ((value & 0x1f) << 16);
1142 /* The RA field in a D or X form instruction which is an updating
1143 store or an updating floating point load, which means that the RA
1144 field may not be zero. */
1146 static unsigned long
1147 insert_ras (insn, value, dialect, errmsg)
1150 int dialect ATTRIBUTE_UNUSED;
1151 const char **errmsg;
1154 *errmsg = _("invalid register operand when updating");
1155 return insn | ((value & 0x1f) << 16);
1158 /* The RB field in an X form instruction when it must be the same as
1159 the RS field in the instruction. This is used for extended
1160 mnemonics like mr. This operand is marked FAKE. The insertion
1161 function just copies the BT field into the BA field, and the
1162 extraction function just checks that the fields are the same. */
1165 static unsigned long
1166 insert_rbs (insn, value, dialect, errmsg)
1168 long value ATTRIBUTE_UNUSED;
1169 int dialect ATTRIBUTE_UNUSED;
1170 const char **errmsg ATTRIBUTE_UNUSED;
1172 return insn | (((insn >> 21) & 0x1f) << 11);
1176 extract_rbs (insn, dialect, invalid)
1178 int dialect ATTRIBUTE_UNUSED;
1181 if (invalid != (int *) NULL
1182 && ((insn >> 21) & 0x1f) != ((insn >> 11) & 0x1f))
1187 /* The SH field in an MD form instruction. This is split. */
1190 static unsigned long
1191 insert_sh6 (insn, value, dialect, errmsg)
1194 int dialect ATTRIBUTE_UNUSED;
1195 const char **errmsg ATTRIBUTE_UNUSED;
1197 return insn | ((value & 0x1f) << 11) | ((value & 0x20) >> 4);
1202 extract_sh6 (insn, dialect, invalid)
1204 int dialect ATTRIBUTE_UNUSED;
1205 int *invalid ATTRIBUTE_UNUSED;
1207 return ((insn >> 11) & 0x1f) | ((insn << 4) & 0x20);
1210 /* The SPR field in an XFX form instruction. This is flipped--the
1211 lower 5 bits are stored in the upper 5 and vice- versa. */
1213 static unsigned long
1214 insert_spr (insn, value, dialect, errmsg)
1217 int dialect ATTRIBUTE_UNUSED;
1218 const char **errmsg ATTRIBUTE_UNUSED;
1220 return insn | ((value & 0x1f) << 16) | ((value & 0x3e0) << 6);
1224 extract_spr (insn, dialect, invalid)
1226 int dialect ATTRIBUTE_UNUSED;
1227 int *invalid ATTRIBUTE_UNUSED;
1229 return ((insn >> 16) & 0x1f) | ((insn >> 6) & 0x3e0);
1232 /* The TBR field in an XFX instruction. This is just like SPR, but it
1233 is optional. When TBR is omitted, it must be inserted as 268 (the
1234 magic number of the TB register). These functions treat 0
1235 (indicating an omitted optional operand) as 268. This means that
1236 ``mftb 4,0'' is not handled correctly. This does not matter very
1237 much, since the architecture manual does not define mftb as
1238 accepting any values other than 268 or 269. */
1242 static unsigned long
1243 insert_tbr (insn, value, dialect, errmsg)
1246 int dialect ATTRIBUTE_UNUSED;
1247 const char **errmsg ATTRIBUTE_UNUSED;
1251 return insn | ((value & 0x1f) << 16) | ((value & 0x3e0) << 6);
1255 extract_tbr (insn, dialect, invalid)
1257 int dialect ATTRIBUTE_UNUSED;
1258 int *invalid ATTRIBUTE_UNUSED;
1262 ret = ((insn >> 16) & 0x1f) | ((insn >> 6) & 0x3e0);
1268 /* Macros used to form opcodes. */
1270 /* The main opcode. */
1271 #define OP(x) ((((unsigned long)(x)) & 0x3f) << 26)
1272 #define OP_MASK OP (0x3f)
1274 /* The main opcode combined with a trap code in the TO field of a D
1275 form instruction. Used for extended mnemonics for the trap
1277 #define OPTO(x,to) (OP (x) | ((((unsigned long)(to)) & 0x1f) << 21))
1278 #define OPTO_MASK (OP_MASK | TO_MASK)
1280 /* The main opcode combined with a comparison size bit in the L field
1281 of a D form or X form instruction. Used for extended mnemonics for
1282 the comparison instructions. */
1283 #define OPL(x,l) (OP (x) | ((((unsigned long)(l)) & 1) << 21))
1284 #define OPL_MASK OPL (0x3f,1)
1286 /* An A form instruction. */
1287 #define A(op, xop, rc) (OP (op) | ((((unsigned long)(xop)) & 0x1f) << 1) | (((unsigned long)(rc)) & 1))
1288 #define A_MASK A (0x3f, 0x1f, 1)
1290 /* An A_MASK with the FRB field fixed. */
1291 #define AFRB_MASK (A_MASK | FRB_MASK)
1293 /* An A_MASK with the FRC field fixed. */
1294 #define AFRC_MASK (A_MASK | FRC_MASK)
1296 /* An A_MASK with the FRA and FRC fields fixed. */
1297 #define AFRAFRC_MASK (A_MASK | FRA_MASK | FRC_MASK)
1299 /* A B form instruction. */
1300 #define B(op, aa, lk) (OP (op) | ((((unsigned long)(aa)) & 1) << 1) | ((lk) & 1))
1301 #define B_MASK B (0x3f, 1, 1)
1303 /* A B form instruction setting the BO field. */
1304 #define BBO(op, bo, aa, lk) (B ((op), (aa), (lk)) | ((((unsigned long)(bo)) & 0x1f) << 21))
1305 #define BBO_MASK BBO (0x3f, 0x1f, 1, 1)
1307 /* A BBO_MASK with the y bit of the BO field removed. This permits
1308 matching a conditional branch regardless of the setting of the y
1309 bit. Similarly for the 'at' bits used for power4 branch hints. */
1310 #define Y_MASK (((unsigned long) 1) << 21)
1311 #define AT1_MASK (((unsigned long) 3) << 21)
1312 #define AT2_MASK (((unsigned long) 9) << 21)
1313 #define BBOY_MASK (BBO_MASK &~ Y_MASK)
1314 #define BBOAT_MASK (BBO_MASK &~ AT1_MASK)
1316 /* A B form instruction setting the BO field and the condition bits of
1318 #define BBOCB(op, bo, cb, aa, lk) \
1319 (BBO ((op), (bo), (aa), (lk)) | ((((unsigned long)(cb)) & 0x3) << 16))
1320 #define BBOCB_MASK BBOCB (0x3f, 0x1f, 0x3, 1, 1)
1322 /* A BBOCB_MASK with the y bit of the BO field removed. */
1323 #define BBOYCB_MASK (BBOCB_MASK &~ Y_MASK)
1324 #define BBOATCB_MASK (BBOCB_MASK &~ AT1_MASK)
1325 #define BBOAT2CB_MASK (BBOCB_MASK &~ AT2_MASK)
1327 /* A BBOYCB_MASK in which the BI field is fixed. */
1328 #define BBOYBI_MASK (BBOYCB_MASK | BI_MASK)
1329 #define BBOATBI_MASK (BBOAT2CB_MASK | BI_MASK)
1331 /* The main opcode mask with the RA field clear. */
1332 #define DRA_MASK (OP_MASK | RA_MASK)
1334 /* A DS form instruction. */
1335 #define DSO(op, xop) (OP (op) | ((xop) & 0x3))
1336 #define DS_MASK DSO (0x3f, 3)
1338 /* A DE form instruction. */
1339 #define DEO(op, xop) (OP (op) | ((xop) & 0xf))
1340 #define DE_MASK DEO (0x3e, 0xf)
1342 /* An M form instruction. */
1343 #define M(op, rc) (OP (op) | ((rc) & 1))
1344 #define M_MASK M (0x3f, 1)
1346 /* An M form instruction with the ME field specified. */
1347 #define MME(op, me, rc) (M ((op), (rc)) | ((((unsigned long)(me)) & 0x1f) << 1))
1349 /* An M_MASK with the MB and ME fields fixed. */
1350 #define MMBME_MASK (M_MASK | MB_MASK | ME_MASK)
1352 /* An M_MASK with the SH and ME fields fixed. */
1353 #define MSHME_MASK (M_MASK | SH_MASK | ME_MASK)
1355 /* An MD form instruction. */
1356 #define MD(op, xop, rc) (OP (op) | ((((unsigned long)(xop)) & 0x7) << 2) | ((rc) & 1))
1357 #define MD_MASK MD (0x3f, 0x7, 1)
1359 /* An MD_MASK with the MB field fixed. */
1360 #define MDMB_MASK (MD_MASK | MB6_MASK)
1362 /* An MD_MASK with the SH field fixed. */
1363 #define MDSH_MASK (MD_MASK | SH6_MASK)
1365 /* An MDS form instruction. */
1366 #define MDS(op, xop, rc) (OP (op) | ((((unsigned long)(xop)) & 0xf) << 1) | ((rc) & 1))
1367 #define MDS_MASK MDS (0x3f, 0xf, 1)
1369 /* An MDS_MASK with the MB field fixed. */
1370 #define MDSMB_MASK (MDS_MASK | MB6_MASK)
1372 /* An SC form instruction. */
1373 #define SC(op, sa, lk) (OP (op) | ((((unsigned long)(sa)) & 1) << 1) | ((lk) & 1))
1374 #define SC_MASK (OP_MASK | (((unsigned long)0x3ff) << 16) | (((unsigned long)1) << 1) | 1)
1376 /* An VX form instruction. */
1377 #define VX(op, xop) (OP (op) | (((unsigned long)(xop)) & 0x7ff))
1379 /* The mask for an VX form instruction. */
1380 #define VX_MASK VX(0x3f, 0x7ff)
1382 /* An VA form instruction. */
1383 #define VXA(op, xop) (OP (op) | (((unsigned long)(xop)) & 0x03f))
1385 /* The mask for an VA form instruction. */
1386 #define VXA_MASK VXA(0x3f, 0x3f)
1388 /* An VXR form instruction. */
1389 #define VXR(op, xop, rc) (OP (op) | (((rc) & 1) << 10) | (((unsigned long)(xop)) & 0x3ff))
1391 /* The mask for a VXR form instruction. */
1392 #define VXR_MASK VXR(0x3f, 0x3ff, 1)
1394 /* An X form instruction. */
1395 #define X(op, xop) (OP (op) | ((((unsigned long)(xop)) & 0x3ff) << 1))
1397 /* An X form instruction with the RC bit specified. */
1398 #define XRC(op, xop, rc) (X ((op), (xop)) | ((rc) & 1))
1400 /* The mask for an X form instruction. */
1401 #define X_MASK XRC (0x3f, 0x3ff, 1)
1403 /* An X_MASK with the RA field fixed. */
1404 #define XRA_MASK (X_MASK | RA_MASK)
1406 /* An X_MASK with the RB field fixed. */
1407 #define XRB_MASK (X_MASK | RB_MASK)
1409 /* An X_MASK with the RT field fixed. */
1410 #define XRT_MASK (X_MASK | RT_MASK)
1412 /* An X_MASK with the RA and RB fields fixed. */
1413 #define XRARB_MASK (X_MASK | RA_MASK | RB_MASK)
1415 /* An X_MASK with the RT and RA fields fixed. */
1416 #define XRTRA_MASK (X_MASK | RT_MASK | RA_MASK)
1418 /* An XRTRA_MASK, but with L bit clear. */
1419 #define XRTLRA_MASK (XRTRA_MASK & ~((unsigned long) 1 << 21))
1421 /* An X form comparison instruction. */
1422 #define XCMPL(op, xop, l) (X ((op), (xop)) | ((((unsigned long)(l)) & 1) << 21))
1424 /* The mask for an X form comparison instruction. */
1425 #define XCMP_MASK (X_MASK | (((unsigned long)1) << 22))
1427 /* The mask for an X form comparison instruction with the L field
1429 #define XCMPL_MASK (XCMP_MASK | (((unsigned long)1) << 21))
1431 /* An X form trap instruction with the TO field specified. */
1432 #define XTO(op, xop, to) (X ((op), (xop)) | ((((unsigned long)(to)) & 0x1f) << 21))
1433 #define XTO_MASK (X_MASK | TO_MASK)
1435 /* An X form tlb instruction with the SH field specified. */
1436 #define XTLB(op, xop, sh) (X ((op), (xop)) | ((((unsigned long)(sh)) & 0x1f) << 11))
1437 #define XTLB_MASK (X_MASK | SH_MASK)
1439 /* An X form sync instruction. */
1440 #define XSYNC(op, xop, l) (X ((op), (xop)) | ((((unsigned long)(l)) & 3) << 21))
1442 /* An X form sync instruction with everything filled in except the LS field. */
1443 #define XSYNC_MASK (0xff9fffff)
1445 /* An X form AltiVec dss instruction. */
1446 #define XDSS(op, xop, a) (X ((op), (xop)) | ((((unsigned long)(a)) & 1) << 25))
1447 #define XDSS_MASK XDSS(0x3f, 0x3ff, 1)
1449 /* An XFL form instruction. */
1450 #define XFL(op, xop, rc) (OP (op) | ((((unsigned long)(xop)) & 0x3ff) << 1) | (((unsigned long)(rc)) & 1))
1451 #define XFL_MASK (XFL (0x3f, 0x3ff, 1) | (((unsigned long)1) << 25) | (((unsigned long)1) << 16))
1453 /* An XL form instruction with the LK field set to 0. */
1454 #define XL(op, xop) (OP (op) | ((((unsigned long)(xop)) & 0x3ff) << 1))
1456 /* An XL form instruction which uses the LK field. */
1457 #define XLLK(op, xop, lk) (XL ((op), (xop)) | ((lk) & 1))
1459 /* The mask for an XL form instruction. */
1460 #define XL_MASK XLLK (0x3f, 0x3ff, 1)
1462 /* An XL form instruction which explicitly sets the BO field. */
1463 #define XLO(op, bo, xop, lk) \
1464 (XLLK ((op), (xop), (lk)) | ((((unsigned long)(bo)) & 0x1f) << 21))
1465 #define XLO_MASK (XL_MASK | BO_MASK)
1467 /* An XL form instruction which explicitly sets the y bit of the BO
1469 #define XLYLK(op, xop, y, lk) (XLLK ((op), (xop), (lk)) | ((((unsigned long)(y)) & 1) << 21))
1470 #define XLYLK_MASK (XL_MASK | Y_MASK)
1472 /* An XL form instruction which sets the BO field and the condition
1473 bits of the BI field. */
1474 #define XLOCB(op, bo, cb, xop, lk) \
1475 (XLO ((op), (bo), (xop), (lk)) | ((((unsigned long)(cb)) & 3) << 16))
1476 #define XLOCB_MASK XLOCB (0x3f, 0x1f, 0x3, 0x3ff, 1)
1478 /* An XL_MASK or XLYLK_MASK or XLOCB_MASK with the BB field fixed. */
1479 #define XLBB_MASK (XL_MASK | BB_MASK)
1480 #define XLYBB_MASK (XLYLK_MASK | BB_MASK)
1481 #define XLBOCBBB_MASK (XLOCB_MASK | BB_MASK)
1483 /* An XL_MASK with the BO and BB fields fixed. */
1484 #define XLBOBB_MASK (XL_MASK | BO_MASK | BB_MASK)
1486 /* An XL_MASK with the BO, BI and BB fields fixed. */
1487 #define XLBOBIBB_MASK (XL_MASK | BO_MASK | BI_MASK | BB_MASK)
1489 /* An XO form instruction. */
1490 #define XO(op, xop, oe, rc) \
1491 (OP (op) | ((((unsigned long)(xop)) & 0x1ff) << 1) | ((((unsigned long)(oe)) & 1) << 10) | (((unsigned long)(rc)) & 1))
1492 #define XO_MASK XO (0x3f, 0x1ff, 1, 1)
1494 /* An XO_MASK with the RB field fixed. */
1495 #define XORB_MASK (XO_MASK | RB_MASK)
1497 /* An XS form instruction. */
1498 #define XS(op, xop, rc) (OP (op) | ((((unsigned long)(xop)) & 0x1ff) << 2) | (((unsigned long)(rc)) & 1))
1499 #define XS_MASK XS (0x3f, 0x1ff, 1)
1501 /* A mask for the FXM version of an XFX form instruction. */
1502 #define XFXFXM_MASK (X_MASK | (((unsigned long)1) << 20) | (((unsigned long)1) << 11))
1504 /* An XFX form instruction with the FXM field filled in. */
1505 #define XFXM(op, xop, fxm) \
1506 (X ((op), (xop)) | ((((unsigned long)(fxm)) & 0xff) << 12))
1508 /* An XFX form instruction with the SPR field filled in. */
1509 #define XSPR(op, xop, spr) \
1510 (X ((op), (xop)) | ((((unsigned long)(spr)) & 0x1f) << 16) | ((((unsigned long)(spr)) & 0x3e0) << 6))
1511 #define XSPR_MASK (X_MASK | SPR_MASK)
1513 /* An XFX form instruction with the SPR field filled in except for the
1515 #define XSPRBAT_MASK (XSPR_MASK &~ SPRBAT_MASK)
1517 /* An XFX form instruction with the SPR field filled in except for the
1519 #define XSPRG_MASK (XSPR_MASK &~ SPRG_MASK)
1521 /* An X form instruction with everything filled in except the E field. */
1522 #define XE_MASK (0xffff7fff)
1524 /* The BO encodings used in extended conditional branch mnemonics. */
1525 #define BODNZF (0x0)
1526 #define BODNZFP (0x1)
1528 #define BODZFP (0x3)
1529 #define BODNZT (0x8)
1530 #define BODNZTP (0x9)
1532 #define BODZTP (0xb)
1543 #define BODNZ (0x10)
1544 #define BODNZP (0x11)
1546 #define BODZP (0x13)
1547 #define BODNZM4 (0x18)
1548 #define BODNZP4 (0x19)
1549 #define BODZM4 (0x1a)
1550 #define BODZP4 (0x1b)
1554 /* The BI condition bit encodings used in extended conditional branch
1561 /* The TO encodings used in extended trap mnemonics. */
1578 /* Smaller names for the flags so each entry in the opcodes table will
1579 fit on a single line. */
1581 #define PPC PPC_OPCODE_PPC | PPC_OPCODE_ANY
1582 #define PPCCOM PPC_OPCODE_PPC | PPC_OPCODE_COMMON | PPC_OPCODE_ANY
1583 #define NOPOWER4 PPC_OPCODE_NOPOWER4 | PPCCOM
1584 #define POWER4 PPC_OPCODE_POWER4 | PPCCOM
1585 #define PPC32 PPC_OPCODE_32 | PPC_OPCODE_PPC | PPC_OPCODE_ANY
1586 #define PPC64 PPC_OPCODE_64 | PPC_OPCODE_PPC | PPC_OPCODE_ANY
1587 #define PPCONLY PPC_OPCODE_PPC
1588 #define PPC403 PPC_OPCODE_403
1589 #define PPC405 PPC403
1592 #define PPCVEC PPC_OPCODE_ALTIVEC | PPC_OPCODE_ANY | PPC_OPCODE_PPC
1593 #define POWER PPC_OPCODE_POWER | PPC_OPCODE_ANY
1594 #define POWER2 PPC_OPCODE_POWER | PPC_OPCODE_POWER2 | PPC_OPCODE_ANY
1595 #define PPCPWR2 PPC_OPCODE_PPC | PPC_OPCODE_POWER | PPC_OPCODE_POWER2 | PPC_OPCODE_ANY
1596 #define POWER32 PPC_OPCODE_POWER | PPC_OPCODE_ANY | PPC_OPCODE_32
1597 #define COM PPC_OPCODE_POWER | PPC_OPCODE_PPC | PPC_OPCODE_COMMON | PPC_OPCODE_ANY
1598 #define COM32 PPC_OPCODE_POWER | PPC_OPCODE_PPC | PPC_OPCODE_COMMON | PPC_OPCODE_ANY | PPC_OPCODE_32
1599 #define M601 PPC_OPCODE_POWER | PPC_OPCODE_601 | PPC_OPCODE_ANY
1600 #define PWRCOM PPC_OPCODE_POWER | PPC_OPCODE_601 | PPC_OPCODE_COMMON | PPC_OPCODE_ANY
1601 #define MFDEC1 PPC_OPCODE_POWER
1602 #define MFDEC2 PPC_OPCODE_PPC | PPC_OPCODE_601
1603 #define BOOKE PPC_OPCODE_BOOKE
1604 #define BOOKE64 PPC_OPCODE_BOOKE64
1606 /* The opcode table.
1608 The format of the opcode table is:
1610 NAME OPCODE MASK FLAGS { OPERANDS }
1612 NAME is the name of the instruction.
1613 OPCODE is the instruction opcode.
1614 MASK is the opcode mask; this is used to tell the disassembler
1615 which bits in the actual opcode must match OPCODE.
1616 FLAGS are flags indicated what processors support the instruction.
1617 OPERANDS is the list of operands.
1619 The disassembler reads the table in order and prints the first
1620 instruction which matches, so this table is sorted to put more
1621 specific instructions before more general instructions. It is also
1622 sorted by major opcode. */
1624 const struct powerpc_opcode powerpc_opcodes[] = {
1625 { "tdlgti", OPTO(2,TOLGT), OPTO_MASK, PPC64, { RA, SI } },
1626 { "tdllti", OPTO(2,TOLLT), OPTO_MASK, PPC64, { RA, SI } },
1627 { "tdeqi", OPTO(2,TOEQ), OPTO_MASK, PPC64, { RA, SI } },
1628 { "tdlgei", OPTO(2,TOLGE), OPTO_MASK, PPC64, { RA, SI } },
1629 { "tdlnli", OPTO(2,TOLNL), OPTO_MASK, PPC64, { RA, SI } },
1630 { "tdllei", OPTO(2,TOLLE), OPTO_MASK, PPC64, { RA, SI } },
1631 { "tdlngi", OPTO(2,TOLNG), OPTO_MASK, PPC64, { RA, SI } },
1632 { "tdgti", OPTO(2,TOGT), OPTO_MASK, PPC64, { RA, SI } },
1633 { "tdgei", OPTO(2,TOGE), OPTO_MASK, PPC64, { RA, SI } },
1634 { "tdnli", OPTO(2,TONL), OPTO_MASK, PPC64, { RA, SI } },
1635 { "tdlti", OPTO(2,TOLT), OPTO_MASK, PPC64, { RA, SI } },
1636 { "tdlei", OPTO(2,TOLE), OPTO_MASK, PPC64, { RA, SI } },
1637 { "tdngi", OPTO(2,TONG), OPTO_MASK, PPC64, { RA, SI } },
1638 { "tdnei", OPTO(2,TONE), OPTO_MASK, PPC64, { RA, SI } },
1639 { "tdi", OP(2), OP_MASK, PPC64, { TO, RA, SI } },
1641 { "twlgti", OPTO(3,TOLGT), OPTO_MASK, PPCCOM, { RA, SI } },
1642 { "tlgti", OPTO(3,TOLGT), OPTO_MASK, PWRCOM, { RA, SI } },
1643 { "twllti", OPTO(3,TOLLT), OPTO_MASK, PPCCOM, { RA, SI } },
1644 { "tllti", OPTO(3,TOLLT), OPTO_MASK, PWRCOM, { RA, SI } },
1645 { "tweqi", OPTO(3,TOEQ), OPTO_MASK, PPCCOM, { RA, SI } },
1646 { "teqi", OPTO(3,TOEQ), OPTO_MASK, PWRCOM, { RA, SI } },
1647 { "twlgei", OPTO(3,TOLGE), OPTO_MASK, PPCCOM, { RA, SI } },
1648 { "tlgei", OPTO(3,TOLGE), OPTO_MASK, PWRCOM, { RA, SI } },
1649 { "twlnli", OPTO(3,TOLNL), OPTO_MASK, PPCCOM, { RA, SI } },
1650 { "tlnli", OPTO(3,TOLNL), OPTO_MASK, PWRCOM, { RA, SI } },
1651 { "twllei", OPTO(3,TOLLE), OPTO_MASK, PPCCOM, { RA, SI } },
1652 { "tllei", OPTO(3,TOLLE), OPTO_MASK, PWRCOM, { RA, SI } },
1653 { "twlngi", OPTO(3,TOLNG), OPTO_MASK, PPCCOM, { RA, SI } },
1654 { "tlngi", OPTO(3,TOLNG), OPTO_MASK, PWRCOM, { RA, SI } },
1655 { "twgti", OPTO(3,TOGT), OPTO_MASK, PPCCOM, { RA, SI } },
1656 { "tgti", OPTO(3,TOGT), OPTO_MASK, PWRCOM, { RA, SI } },
1657 { "twgei", OPTO(3,TOGE), OPTO_MASK, PPCCOM, { RA, SI } },
1658 { "tgei", OPTO(3,TOGE), OPTO_MASK, PWRCOM, { RA, SI } },
1659 { "twnli", OPTO(3,TONL), OPTO_MASK, PPCCOM, { RA, SI } },
1660 { "tnli", OPTO(3,TONL), OPTO_MASK, PWRCOM, { RA, SI } },
1661 { "twlti", OPTO(3,TOLT), OPTO_MASK, PPCCOM, { RA, SI } },
1662 { "tlti", OPTO(3,TOLT), OPTO_MASK, PWRCOM, { RA, SI } },
1663 { "twlei", OPTO(3,TOLE), OPTO_MASK, PPCCOM, { RA, SI } },
1664 { "tlei", OPTO(3,TOLE), OPTO_MASK, PWRCOM, { RA, SI } },
1665 { "twngi", OPTO(3,TONG), OPTO_MASK, PPCCOM, { RA, SI } },
1666 { "tngi", OPTO(3,TONG), OPTO_MASK, PWRCOM, { RA, SI } },
1667 { "twnei", OPTO(3,TONE), OPTO_MASK, PPCCOM, { RA, SI } },
1668 { "tnei", OPTO(3,TONE), OPTO_MASK, PWRCOM, { RA, SI } },
1669 { "twi", OP(3), OP_MASK, PPCCOM, { TO, RA, SI } },
1670 { "ti", OP(3), OP_MASK, PWRCOM, { TO, RA, SI } },
1672 { "macchw", XO(4,172,0,0), XO_MASK, PPC405, { RT, RA, RB } },
1673 { "macchw.", XO(4,172,0,1), XO_MASK, PPC405, { RT, RA, RB } },
1674 { "macchwo", XO(4,172,1,0), XO_MASK, PPC405, { RT, RA, RB } },
1675 { "macchwo.", XO(4,172,1,1), XO_MASK, PPC405, { RT, RA, RB } },
1676 { "macchws", XO(4,236,0,0), XO_MASK, PPC405, { RT, RA, RB } },
1677 { "macchws.", XO(4,236,0,1), XO_MASK, PPC405, { RT, RA, RB } },
1678 { "macchwso", XO(4,236,1,0), XO_MASK, PPC405, { RT, RA, RB } },
1679 { "macchwso.", XO(4,236,1,1), XO_MASK, PPC405, { RT, RA, RB } },
1680 { "macchwsu", XO(4,204,0,0), XO_MASK, PPC405, { RT, RA, RB } },
1681 { "macchwsu.", XO(4,204,0,1), XO_MASK, PPC405, { RT, RA, RB } },
1682 { "macchwsuo", XO(4,204,1,0), XO_MASK, PPC405, { RT, RA, RB } },
1683 { "macchwsuo.", XO(4,204,1,1), XO_MASK, PPC405, { RT, RA, RB } },
1684 { "macchwu", XO(4,140,0,0), XO_MASK, PPC405, { RT, RA, RB } },
1685 { "macchwu.", XO(4,140,0,1), XO_MASK, PPC405, { RT, RA, RB } },
1686 { "macchwuo", XO(4,140,1,0), XO_MASK, PPC405, { RT, RA, RB } },
1687 { "macchwuo.", XO(4,140,1,1), XO_MASK, PPC405, { RT, RA, RB } },
1688 { "machhw", XO(4,44,0,0), XO_MASK, PPC405, { RT, RA, RB } },
1689 { "machhw.", XO(4,44,0,1), XO_MASK, PPC405, { RT, RA, RB } },
1690 { "machhwo", XO(4,44,1,0), XO_MASK, PPC405, { RT, RA, RB } },
1691 { "machhwo.", XO(4,44,1,1), XO_MASK, PPC405, { RT, RA, RB } },
1692 { "machhws", XO(4,108,0,0), XO_MASK, PPC405, { RT, RA, RB } },
1693 { "machhws.", XO(4,108,0,1), XO_MASK, PPC405, { RT, RA, RB } },
1694 { "machhwso", XO(4,108,1,0), XO_MASK, PPC405, { RT, RA, RB } },
1695 { "machhwso.", XO(4,108,1,1), XO_MASK, PPC405, { RT, RA, RB } },
1696 { "machhwsu", XO(4,76,0,0), XO_MASK, PPC405, { RT, RA, RB } },
1697 { "machhwsu.", XO(4,76,0,1), XO_MASK, PPC405, { RT, RA, RB } },
1698 { "machhwsuo", XO(4,76,1,0), XO_MASK, PPC405, { RT, RA, RB } },
1699 { "machhwsuo.", XO(4,76,1,1), XO_MASK, PPC405, { RT, RA, RB } },
1700 { "machhwu", XO(4,12,0,0), XO_MASK, PPC405, { RT, RA, RB } },
1701 { "machhwu.", XO(4,12,0,1), XO_MASK, PPC405, { RT, RA, RB } },
1702 { "machhwuo", XO(4,12,1,0), XO_MASK, PPC405, { RT, RA, RB } },
1703 { "machhwuo.", XO(4,12,1,1), XO_MASK, PPC405, { RT, RA, RB } },
1704 { "maclhw", XO(4,428,0,0), XO_MASK, PPC405, { RT, RA, RB } },
1705 { "maclhw.", XO(4,428,0,1), XO_MASK, PPC405, { RT, RA, RB } },
1706 { "maclhwo", XO(4,428,1,0), XO_MASK, PPC405, { RT, RA, RB } },
1707 { "maclhwo.", XO(4,428,1,1), XO_MASK, PPC405, { RT, RA, RB } },
1708 { "maclhws", XO(4,492,0,0), XO_MASK, PPC405, { RT, RA, RB } },
1709 { "maclhws.", XO(4,492,0,1), XO_MASK, PPC405, { RT, RA, RB } },
1710 { "maclhwso", XO(4,492,1,0), XO_MASK, PPC405, { RT, RA, RB } },
1711 { "maclhwso.", XO(4,492,1,1), XO_MASK, PPC405, { RT, RA, RB } },
1712 { "maclhwsu", XO(4,460,0,0), XO_MASK, PPC405, { RT, RA, RB } },
1713 { "maclhwsu.", XO(4,460,0,1), XO_MASK, PPC405, { RT, RA, RB } },
1714 { "maclhwsuo", XO(4,460,1,0), XO_MASK, PPC405, { RT, RA, RB } },
1715 { "maclhwsuo.", XO(4,460,1,1), XO_MASK, PPC405, { RT, RA, RB } },
1716 { "maclhwu", XO(4,396,0,0), XO_MASK, PPC405, { RT, RA, RB } },
1717 { "maclhwu.", XO(4,396,0,1), XO_MASK, PPC405, { RT, RA, RB } },
1718 { "maclhwuo", XO(4,396,1,0), XO_MASK, PPC405, { RT, RA, RB } },
1719 { "maclhwuo.", XO(4,396,1,1), XO_MASK, PPC405, { RT, RA, RB } },
1720 { "mulchw", XRC(4,168,0), X_MASK, PPC405, { RT, RA, RB } },
1721 { "mulchw.", XRC(4,168,1), X_MASK, PPC405, { RT, RA, RB } },
1722 { "mulchwu", XRC(4,136,0), X_MASK, PPC405, { RT, RA, RB } },
1723 { "mulchwu.", XRC(4,136,1), X_MASK, PPC405, { RT, RA, RB } },
1724 { "mulhhw", XRC(4,40,0), X_MASK, PPC405, { RT, RA, RB } },
1725 { "mulhhw.", XRC(4,40,1), X_MASK, PPC405, { RT, RA, RB } },
1726 { "mulhhwu", XRC(4,8,0), X_MASK, PPC405, { RT, RA, RB } },
1727 { "mulhhwu.", XRC(4,8,1), X_MASK, PPC405, { RT, RA, RB } },
1728 { "mullhw", XRC(4,424,0), X_MASK, PPC405, { RT, RA, RB } },
1729 { "mullhw.", XRC(4,424,1), X_MASK, PPC405, { RT, RA, RB } },
1730 { "mullhwu", XRC(4,392,0), X_MASK, PPC405, { RT, RA, RB } },
1731 { "mullhwu.", XRC(4,392,1), X_MASK, PPC405, { RT, RA, RB } },
1732 { "nmacchw", XO(4,174,0,0), XO_MASK, PPC405, { RT, RA, RB } },
1733 { "nmacchw.", XO(4,174,0,1), XO_MASK, PPC405, { RT, RA, RB } },
1734 { "nmacchwo", XO(4,174,1,0), XO_MASK, PPC405, { RT, RA, RB } },
1735 { "nmacchwo.", XO(4,174,1,1), XO_MASK, PPC405, { RT, RA, RB } },
1736 { "nmacchws", XO(4,238,0,0), XO_MASK, PPC405, { RT, RA, RB } },
1737 { "nmacchws.", XO(4,238,0,1), XO_MASK, PPC405, { RT, RA, RB } },
1738 { "nmacchwso", XO(4,238,1,0), XO_MASK, PPC405, { RT, RA, RB } },
1739 { "nmacchwso.", XO(4,238,1,1), XO_MASK, PPC405, { RT, RA, RB } },
1740 { "nmachhw", XO(4,46,0,0), XO_MASK, PPC405, { RT, RA, RB } },
1741 { "nmachhw.", XO(4,46,0,1), XO_MASK, PPC405, { RT, RA, RB } },
1742 { "nmachhwo", XO(4,46,1,0), XO_MASK, PPC405, { RT, RA, RB } },
1743 { "nmachhwo.", XO(4,46,1,1), XO_MASK, PPC405, { RT, RA, RB } },
1744 { "nmachhws", XO(4,110,0,0), XO_MASK, PPC405, { RT, RA, RB } },
1745 { "nmachhws.", XO(4,110,0,1), XO_MASK, PPC405, { RT, RA, RB } },
1746 { "nmachhwso", XO(4,110,1,0), XO_MASK, PPC405, { RT, RA, RB } },
1747 { "nmachhwso.", XO(4,110,1,1), XO_MASK, PPC405, { RT, RA, RB } },
1748 { "nmaclhw", XO(4,430,0,0), XO_MASK, PPC405, { RT, RA, RB } },
1749 { "nmaclhw.", XO(4,430,0,1), XO_MASK, PPC405, { RT, RA, RB } },
1750 { "nmaclhwo", XO(4,430,1,0), XO_MASK, PPC405, { RT, RA, RB } },
1751 { "nmaclhwo.", XO(4,430,1,1), XO_MASK, PPC405, { RT, RA, RB } },
1752 { "nmaclhws", XO(4,494,0,0), XO_MASK, PPC405, { RT, RA, RB } },
1753 { "nmaclhws.", XO(4,494,0,1), XO_MASK, PPC405, { RT, RA, RB } },
1754 { "nmaclhwso", XO(4,494,1,0), XO_MASK, PPC405, { RT, RA, RB } },
1755 { "nmaclhwso.", XO(4,494,1,1), XO_MASK, PPC405, { RT, RA, RB } },
1756 { "mfvscr", VX(4, 1540), VX_MASK, PPCVEC, { VD } },
1757 { "mtvscr", VX(4, 1604), VX_MASK, PPCVEC, { VB } },
1758 { "vaddcuw", VX(4, 384), VX_MASK, PPCVEC, { VD, VA, VB } },
1759 { "vaddfp", VX(4, 10), VX_MASK, PPCVEC, { VD, VA, VB } },
1760 { "vaddsbs", VX(4, 768), VX_MASK, PPCVEC, { VD, VA, VB } },
1761 { "vaddshs", VX(4, 832), VX_MASK, PPCVEC, { VD, VA, VB } },
1762 { "vaddsws", VX(4, 896), VX_MASK, PPCVEC, { VD, VA, VB } },
1763 { "vaddubm", VX(4, 0), VX_MASK, PPCVEC, { VD, VA, VB } },
1764 { "vaddubs", VX(4, 512), VX_MASK, PPCVEC, { VD, VA, VB } },
1765 { "vadduhm", VX(4, 64), VX_MASK, PPCVEC, { VD, VA, VB } },
1766 { "vadduhs", VX(4, 576), VX_MASK, PPCVEC, { VD, VA, VB } },
1767 { "vadduwm", VX(4, 128), VX_MASK, PPCVEC, { VD, VA, VB } },
1768 { "vadduws", VX(4, 640), VX_MASK, PPCVEC, { VD, VA, VB } },
1769 { "vand", VX(4, 1028), VX_MASK, PPCVEC, { VD, VA, VB } },
1770 { "vandc", VX(4, 1092), VX_MASK, PPCVEC, { VD, VA, VB } },
1771 { "vavgsb", VX(4, 1282), VX_MASK, PPCVEC, { VD, VA, VB } },
1772 { "vavgsh", VX(4, 1346), VX_MASK, PPCVEC, { VD, VA, VB } },
1773 { "vavgsw", VX(4, 1410), VX_MASK, PPCVEC, { VD, VA, VB } },
1774 { "vavgub", VX(4, 1026), VX_MASK, PPCVEC, { VD, VA, VB } },
1775 { "vavguh", VX(4, 1090), VX_MASK, PPCVEC, { VD, VA, VB } },
1776 { "vavguw", VX(4, 1154), VX_MASK, PPCVEC, { VD, VA, VB } },
1777 { "vcfsx", VX(4, 842), VX_MASK, PPCVEC, { VD, VB, UIMM } },
1778 { "vcfux", VX(4, 778), VX_MASK, PPCVEC, { VD, VB, UIMM } },
1779 { "vcmpbfp", VXR(4, 966, 0), VXR_MASK, PPCVEC, { VD, VA, VB } },
1780 { "vcmpbfp.", VXR(4, 966, 1), VXR_MASK, PPCVEC, { VD, VA, VB } },
1781 { "vcmpeqfp", VXR(4, 198, 0), VXR_MASK, PPCVEC, { VD, VA, VB } },
1782 { "vcmpeqfp.", VXR(4, 198, 1), VXR_MASK, PPCVEC, { VD, VA, VB } },
1783 { "vcmpequb", VXR(4, 6, 0), VXR_MASK, PPCVEC, { VD, VA, VB } },
1784 { "vcmpequb.", VXR(4, 6, 1), VXR_MASK, PPCVEC, { VD, VA, VB } },
1785 { "vcmpequh", VXR(4, 70, 0), VXR_MASK, PPCVEC, { VD, VA, VB } },
1786 { "vcmpequh.", VXR(4, 70, 1), VXR_MASK, PPCVEC, { VD, VA, VB } },
1787 { "vcmpequw", VXR(4, 134, 0), VXR_MASK, PPCVEC, { VD, VA, VB } },
1788 { "vcmpequw.", VXR(4, 134, 1), VXR_MASK, PPCVEC, { VD, VA, VB } },
1789 { "vcmpgefp", VXR(4, 454, 0), VXR_MASK, PPCVEC, { VD, VA, VB } },
1790 { "vcmpgefp.", VXR(4, 454, 1), VXR_MASK, PPCVEC, { VD, VA, VB } },
1791 { "vcmpgtfp", VXR(4, 710, 0), VXR_MASK, PPCVEC, { VD, VA, VB } },
1792 { "vcmpgtfp.", VXR(4, 710, 1), VXR_MASK, PPCVEC, { VD, VA, VB } },
1793 { "vcmpgtsb", VXR(4, 774, 0), VXR_MASK, PPCVEC, { VD, VA, VB } },
1794 { "vcmpgtsb.", VXR(4, 774, 1), VXR_MASK, PPCVEC, { VD, VA, VB } },
1795 { "vcmpgtsh", VXR(4, 838, 0), VXR_MASK, PPCVEC, { VD, VA, VB } },
1796 { "vcmpgtsh.", VXR(4, 838, 1), VXR_MASK, PPCVEC, { VD, VA, VB } },
1797 { "vcmpgtsw", VXR(4, 902, 0), VXR_MASK, PPCVEC, { VD, VA, VB } },
1798 { "vcmpgtsw.", VXR(4, 902, 1), VXR_MASK, PPCVEC, { VD, VA, VB } },
1799 { "vcmpgtub", VXR(4, 518, 0), VXR_MASK, PPCVEC, { VD, VA, VB } },
1800 { "vcmpgtub.", VXR(4, 518, 1), VXR_MASK, PPCVEC, { VD, VA, VB } },
1801 { "vcmpgtuh", VXR(4, 582, 0), VXR_MASK, PPCVEC, { VD, VA, VB } },
1802 { "vcmpgtuh.", VXR(4, 582, 1), VXR_MASK, PPCVEC, { VD, VA, VB } },
1803 { "vcmpgtuw", VXR(4, 646, 0), VXR_MASK, PPCVEC, { VD, VA, VB } },
1804 { "vcmpgtuw.", VXR(4, 646, 1), VXR_MASK, PPCVEC, { VD, VA, VB } },
1805 { "vctsxs", VX(4, 970), VX_MASK, PPCVEC, { VD, VB, UIMM } },
1806 { "vctuxs", VX(4, 906), VX_MASK, PPCVEC, { VD, VB, UIMM } },
1807 { "vexptefp", VX(4, 394), VX_MASK, PPCVEC, { VD, VB } },
1808 { "vlogefp", VX(4, 458), VX_MASK, PPCVEC, { VD, VB } },
1809 { "vmaddfp", VXA(4, 46), VXA_MASK, PPCVEC, { VD, VA, VB, VC } },
1810 { "vmaxfp", VX(4, 1034), VX_MASK, PPCVEC, { VD, VA, VB } },
1811 { "vmaxsb", VX(4, 258), VX_MASK, PPCVEC, { VD, VA, VB } },
1812 { "vmaxsh", VX(4, 322), VX_MASK, PPCVEC, { VD, VA, VB } },
1813 { "vmaxsw", VX(4, 386), VX_MASK, PPCVEC, { VD, VA, VB } },
1814 { "vmaxub", VX(4, 2), VX_MASK, PPCVEC, { VD, VA, VB } },
1815 { "vmaxuh", VX(4, 66), VX_MASK, PPCVEC, { VD, VA, VB } },
1816 { "vmaxuw", VX(4, 130), VX_MASK, PPCVEC, { VD, VA, VB } },
1817 { "vmhaddshs", VXA(4, 32), VXA_MASK, PPCVEC, { VD, VA, VB, VC } },
1818 { "vmhraddshs", VXA(4, 33), VXA_MASK, PPCVEC, { VD, VA, VB, VC } },
1819 { "vminfp", VX(4, 1098), VX_MASK, PPCVEC, { VD, VA, VB } },
1820 { "vminsb", VX(4, 770), VX_MASK, PPCVEC, { VD, VA, VB } },
1821 { "vminsh", VX(4, 834), VX_MASK, PPCVEC, { VD, VA, VB } },
1822 { "vminsw", VX(4, 898), VX_MASK, PPCVEC, { VD, VA, VB } },
1823 { "vminub", VX(4, 514), VX_MASK, PPCVEC, { VD, VA, VB } },
1824 { "vminuh", VX(4, 578), VX_MASK, PPCVEC, { VD, VA, VB } },
1825 { "vminuw", VX(4, 642), VX_MASK, PPCVEC, { VD, VA, VB } },
1826 { "vmladduhm", VXA(4, 34), VXA_MASK, PPCVEC, { VD, VA, VB, VC } },
1827 { "vmrghb", VX(4, 12), VX_MASK, PPCVEC, { VD, VA, VB } },
1828 { "vmrghh", VX(4, 76), VX_MASK, PPCVEC, { VD, VA, VB } },
1829 { "vmrghw", VX(4, 140), VX_MASK, PPCVEC, { VD, VA, VB } },
1830 { "vmrglb", VX(4, 268), VX_MASK, PPCVEC, { VD, VA, VB } },
1831 { "vmrglh", VX(4, 332), VX_MASK, PPCVEC, { VD, VA, VB } },
1832 { "vmrglw", VX(4, 396), VX_MASK, PPCVEC, { VD, VA, VB } },
1833 { "vmsummbm", VXA(4, 37), VXA_MASK, PPCVEC, { VD, VA, VB, VC } },
1834 { "vmsumshm", VXA(4, 40), VXA_MASK, PPCVEC, { VD, VA, VB, VC } },
1835 { "vmsumshs", VXA(4, 41), VXA_MASK, PPCVEC, { VD, VA, VB, VC } },
1836 { "vmsumubm", VXA(4, 36), VXA_MASK, PPCVEC, { VD, VA, VB, VC } },
1837 { "vmsumuhm", VXA(4, 38), VXA_MASK, PPCVEC, { VD, VA, VB, VC } },
1838 { "vmsumuhs", VXA(4, 39), VXA_MASK, PPCVEC, { VD, VA, VB, VC } },
1839 { "vmulesb", VX(4, 776), VX_MASK, PPCVEC, { VD, VA, VB } },
1840 { "vmulesh", VX(4, 840), VX_MASK, PPCVEC, { VD, VA, VB } },
1841 { "vmuleub", VX(4, 520), VX_MASK, PPCVEC, { VD, VA, VB } },
1842 { "vmuleuh", VX(4, 584), VX_MASK, PPCVEC, { VD, VA, VB } },
1843 { "vmulosb", VX(4, 264), VX_MASK, PPCVEC, { VD, VA, VB } },
1844 { "vmulosh", VX(4, 328), VX_MASK, PPCVEC, { VD, VA, VB } },
1845 { "vmuloub", VX(4, 8), VX_MASK, PPCVEC, { VD, VA, VB } },
1846 { "vmulouh", VX(4, 72), VX_MASK, PPCVEC, { VD, VA, VB } },
1847 { "vnmsubfp", VXA(4, 47), VXA_MASK, PPCVEC, { VD, VA, VC, VB } },
1848 { "vnor", VX(4, 1284), VX_MASK, PPCVEC, { VD, VA, VB } },
1849 { "vor", VX(4, 1156), VX_MASK, PPCVEC, { VD, VA, VB } },
1850 { "vperm", VXA(4, 43), VXA_MASK, PPCVEC, { VD, VA, VB, VC } },
1851 { "vpkpx", VX(4, 782), VX_MASK, PPCVEC, { VD, VA, VB } },
1852 { "vpkshss", VX(4, 398), VX_MASK, PPCVEC, { VD, VA, VB } },
1853 { "vpkshus", VX(4, 270), VX_MASK, PPCVEC, { VD, VA, VB } },
1854 { "vpkswss", VX(4, 462), VX_MASK, PPCVEC, { VD, VA, VB } },
1855 { "vpkswus", VX(4, 334), VX_MASK, PPCVEC, { VD, VA, VB } },
1856 { "vpkuhum", VX(4, 14), VX_MASK, PPCVEC, { VD, VA, VB } },
1857 { "vpkuhus", VX(4, 142), VX_MASK, PPCVEC, { VD, VA, VB } },
1858 { "vpkuwum", VX(4, 78), VX_MASK, PPCVEC, { VD, VA, VB } },
1859 { "vpkuwus", VX(4, 206), VX_MASK, PPCVEC, { VD, VA, VB } },
1860 { "vrefp", VX(4, 266), VX_MASK, PPCVEC, { VD, VB } },
1861 { "vrfim", VX(4, 714), VX_MASK, PPCVEC, { VD, VB } },
1862 { "vrfin", VX(4, 522), VX_MASK, PPCVEC, { VD, VB } },
1863 { "vrfip", VX(4, 650), VX_MASK, PPCVEC, { VD, VB } },
1864 { "vrfiz", VX(4, 586), VX_MASK, PPCVEC, { VD, VB } },
1865 { "vrlb", VX(4, 4), VX_MASK, PPCVEC, { VD, VA, VB } },
1866 { "vrlh", VX(4, 68), VX_MASK, PPCVEC, { VD, VA, VB } },
1867 { "vrlw", VX(4, 132), VX_MASK, PPCVEC, { VD, VA, VB } },
1868 { "vrsqrtefp", VX(4, 330), VX_MASK, PPCVEC, { VD, VB } },
1869 { "vsel", VXA(4, 42), VXA_MASK, PPCVEC, { VD, VA, VB, VC } },
1870 { "vsl", VX(4, 452), VX_MASK, PPCVEC, { VD, VA, VB } },
1871 { "vslb", VX(4, 260), VX_MASK, PPCVEC, { VD, VA, VB } },
1872 { "vsldoi", VXA(4, 44), VXA_MASK, PPCVEC, { VD, VA, VB, SHB } },
1873 { "vslh", VX(4, 324), VX_MASK, PPCVEC, { VD, VA, VB } },
1874 { "vslo", VX(4, 1036), VX_MASK, PPCVEC, { VD, VA, VB } },
1875 { "vslw", VX(4, 388), VX_MASK, PPCVEC, { VD, VA, VB } },
1876 { "vspltb", VX(4, 524), VX_MASK, PPCVEC, { VD, VB, UIMM } },
1877 { "vsplth", VX(4, 588), VX_MASK, PPCVEC, { VD, VB, UIMM } },
1878 { "vspltisb", VX(4, 780), VX_MASK, PPCVEC, { VD, SIMM } },
1879 { "vspltish", VX(4, 844), VX_MASK, PPCVEC, { VD, SIMM } },
1880 { "vspltisw", VX(4, 908), VX_MASK, PPCVEC, { VD, SIMM } },
1881 { "vspltw", VX(4, 652), VX_MASK, PPCVEC, { VD, VB, UIMM } },
1882 { "vsr", VX(4, 708), VX_MASK, PPCVEC, { VD, VA, VB } },
1883 { "vsrab", VX(4, 772), VX_MASK, PPCVEC, { VD, VA, VB } },
1884 { "vsrah", VX(4, 836), VX_MASK, PPCVEC, { VD, VA, VB } },
1885 { "vsraw", VX(4, 900), VX_MASK, PPCVEC, { VD, VA, VB } },
1886 { "vsrb", VX(4, 516), VX_MASK, PPCVEC, { VD, VA, VB } },
1887 { "vsrh", VX(4, 580), VX_MASK, PPCVEC, { VD, VA, VB } },
1888 { "vsro", VX(4, 1100), VX_MASK, PPCVEC, { VD, VA, VB } },
1889 { "vsrw", VX(4, 644), VX_MASK, PPCVEC, { VD, VA, VB } },
1890 { "vsubcuw", VX(4, 1408), VX_MASK, PPCVEC, { VD, VA, VB } },
1891 { "vsubfp", VX(4, 74), VX_MASK, PPCVEC, { VD, VA, VB } },
1892 { "vsubsbs", VX(4, 1792), VX_MASK, PPCVEC, { VD, VA, VB } },
1893 { "vsubshs", VX(4, 1856), VX_MASK, PPCVEC, { VD, VA, VB } },
1894 { "vsubsws", VX(4, 1920), VX_MASK, PPCVEC, { VD, VA, VB } },
1895 { "vsububm", VX(4, 1024), VX_MASK, PPCVEC, { VD, VA, VB } },
1896 { "vsububs", VX(4, 1536), VX_MASK, PPCVEC, { VD, VA, VB } },
1897 { "vsubuhm", VX(4, 1088), VX_MASK, PPCVEC, { VD, VA, VB } },
1898 { "vsubuhs", VX(4, 1600), VX_MASK, PPCVEC, { VD, VA, VB } },
1899 { "vsubuwm", VX(4, 1152), VX_MASK, PPCVEC, { VD, VA, VB } },
1900 { "vsubuws", VX(4, 1664), VX_MASK, PPCVEC, { VD, VA, VB } },
1901 { "vsumsws", VX(4, 1928), VX_MASK, PPCVEC, { VD, VA, VB } },
1902 { "vsum2sws", VX(4, 1672), VX_MASK, PPCVEC, { VD, VA, VB } },
1903 { "vsum4sbs", VX(4, 1800), VX_MASK, PPCVEC, { VD, VA, VB } },
1904 { "vsum4shs", VX(4, 1608), VX_MASK, PPCVEC, { VD, VA, VB } },
1905 { "vsum4ubs", VX(4, 1544), VX_MASK, PPCVEC, { VD, VA, VB } },
1906 { "vupkhpx", VX(4, 846), VX_MASK, PPCVEC, { VD, VB } },
1907 { "vupkhsb", VX(4, 526), VX_MASK, PPCVEC, { VD, VB } },
1908 { "vupkhsh", VX(4, 590), VX_MASK, PPCVEC, { VD, VB } },
1909 { "vupklpx", VX(4, 974), VX_MASK, PPCVEC, { VD, VB } },
1910 { "vupklsb", VX(4, 654), VX_MASK, PPCVEC, { VD, VB } },
1911 { "vupklsh", VX(4, 718), VX_MASK, PPCVEC, { VD, VB } },
1912 { "vxor", VX(4, 1220), VX_MASK, PPCVEC, { VD, VA, VB } },
1914 { "mulli", OP(7), OP_MASK, PPCCOM, { RT, RA, SI } },
1915 { "muli", OP(7), OP_MASK, PWRCOM, { RT, RA, SI } },
1917 { "subfic", OP(8), OP_MASK, PPCCOM, { RT, RA, SI } },
1918 { "sfi", OP(8), OP_MASK, PWRCOM, { RT, RA, SI } },
1920 { "dozi", OP(9), OP_MASK, M601, { RT, RA, SI } },
1922 { "bce", B(9,0,0), B_MASK, BOOKE64, { BO, BI, BD } },
1923 { "bcel", B(9,0,1), B_MASK, BOOKE64, { BO, BI, BD } },
1924 { "bcea", B(9,1,0), B_MASK, BOOKE64, { BO, BI, BDA } },
1925 { "bcela", B(9,1,1), B_MASK, BOOKE64, { BO, BI, BDA } },
1927 { "cmplwi", OPL(10,0), OPL_MASK, PPCCOM, { OBF, RA, UI } },
1928 { "cmpldi", OPL(10,1), OPL_MASK, PPC64, { OBF, RA, UI } },
1929 { "cmpli", OP(10), OP_MASK, PPCONLY, { BF, L, RA, UI } },
1930 { "cmpli", OP(10), OP_MASK, PWRCOM, { BF, RA, UI } },
1932 { "cmpwi", OPL(11,0), OPL_MASK, PPCCOM, { OBF, RA, SI } },
1933 { "cmpdi", OPL(11,1), OPL_MASK, PPC64, { OBF, RA, SI } },
1934 { "cmpi", OP(11), OP_MASK, PPCONLY, { BF, L, RA, SI } },
1935 { "cmpi", OP(11), OP_MASK, PWRCOM, { BF, RA, SI } },
1937 { "addic", OP(12), OP_MASK, PPCCOM, { RT, RA, SI } },
1938 { "ai", OP(12), OP_MASK, PWRCOM, { RT, RA, SI } },
1939 { "subic", OP(12), OP_MASK, PPCCOM, { RT, RA, NSI } },
1941 { "addic.", OP(13), OP_MASK, PPCCOM, { RT, RA, SI } },
1942 { "ai.", OP(13), OP_MASK, PWRCOM, { RT, RA, SI } },
1943 { "subic.", OP(13), OP_MASK, PPCCOM, { RT, RA, NSI } },
1945 { "li", OP(14), DRA_MASK, PPCCOM, { RT, SI } },
1946 { "lil", OP(14), DRA_MASK, PWRCOM, { RT, SI } },
1947 { "addi", OP(14), OP_MASK, PPCCOM, { RT, RA, SI } },
1948 { "cal", OP(14), OP_MASK, PWRCOM, { RT, D, RA } },
1949 { "subi", OP(14), OP_MASK, PPCCOM, { RT, RA, NSI } },
1950 { "la", OP(14), OP_MASK, PPCCOM, { RT, D, RA } },
1952 { "lis", OP(15), DRA_MASK, PPCCOM, { RT, SISIGNOPT } },
1953 { "liu", OP(15), DRA_MASK, PWRCOM, { RT, SISIGNOPT } },
1954 { "addis", OP(15), OP_MASK, PPCCOM, { RT,RA,SISIGNOPT } },
1955 { "cau", OP(15), OP_MASK, PWRCOM, { RT,RA,SISIGNOPT } },
1956 { "subis", OP(15), OP_MASK, PPCCOM, { RT, RA, NSI } },
1958 { "bdnz-", BBO(16,BODNZ,0,0), BBOATBI_MASK, PPCCOM, { BDM } },
1959 { "bdnz+", BBO(16,BODNZ,0,0), BBOATBI_MASK, PPCCOM, { BDP } },
1960 { "bdnz", BBO(16,BODNZ,0,0), BBOATBI_MASK, PPCCOM, { BD } },
1961 { "bdn", BBO(16,BODNZ,0,0), BBOATBI_MASK, PWRCOM, { BD } },
1962 { "bdnzl-", BBO(16,BODNZ,0,1), BBOATBI_MASK, PPCCOM, { BDM } },
1963 { "bdnzl+", BBO(16,BODNZ,0,1), BBOATBI_MASK, PPCCOM, { BDP } },
1964 { "bdnzl", BBO(16,BODNZ,0,1), BBOATBI_MASK, PPCCOM, { BD } },
1965 { "bdnl", BBO(16,BODNZ,0,1), BBOATBI_MASK, PWRCOM, { BD } },
1966 { "bdnza-", BBO(16,BODNZ,1,0), BBOATBI_MASK, PPCCOM, { BDMA } },
1967 { "bdnza+", BBO(16,BODNZ,1,0), BBOATBI_MASK, PPCCOM, { BDPA } },
1968 { "bdnza", BBO(16,BODNZ,1,0), BBOATBI_MASK, PPCCOM, { BDA } },
1969 { "bdna", BBO(16,BODNZ,1,0), BBOATBI_MASK, PWRCOM, { BDA } },
1970 { "bdnzla-", BBO(16,BODNZ,1,1), BBOATBI_MASK, PPCCOM, { BDMA } },
1971 { "bdnzla+", BBO(16,BODNZ,1,1), BBOATBI_MASK, PPCCOM, { BDPA } },
1972 { "bdnzla", BBO(16,BODNZ,1,1), BBOATBI_MASK, PPCCOM, { BDA } },
1973 { "bdnla", BBO(16,BODNZ,1,1), BBOATBI_MASK, PWRCOM, { BDA } },
1974 { "bdz-", BBO(16,BODZ,0,0), BBOATBI_MASK, PPCCOM, { BDM } },
1975 { "bdz+", BBO(16,BODZ,0,0), BBOATBI_MASK, PPCCOM, { BDP } },
1976 { "bdz", BBO(16,BODZ,0,0), BBOATBI_MASK, COM, { BD } },
1977 { "bdzl-", BBO(16,BODZ,0,1), BBOATBI_MASK, PPCCOM, { BDM } },
1978 { "bdzl+", BBO(16,BODZ,0,1), BBOATBI_MASK, PPCCOM, { BDP } },
1979 { "bdzl", BBO(16,BODZ,0,1), BBOATBI_MASK, COM, { BD } },
1980 { "bdza-", BBO(16,BODZ,1,0), BBOATBI_MASK, PPCCOM, { BDMA } },
1981 { "bdza+", BBO(16,BODZ,1,0), BBOATBI_MASK, PPCCOM, { BDPA } },
1982 { "bdza", BBO(16,BODZ,1,0), BBOATBI_MASK, COM, { BDA } },
1983 { "bdzla-", BBO(16,BODZ,1,1), BBOATBI_MASK, PPCCOM, { BDMA } },
1984 { "bdzla+", BBO(16,BODZ,1,1), BBOATBI_MASK, PPCCOM, { BDPA } },
1985 { "bdzla", BBO(16,BODZ,1,1), BBOATBI_MASK, COM, { BDA } },
1986 { "blt-", BBOCB(16,BOT,CBLT,0,0), BBOATCB_MASK, PPCCOM, { CR, BDM } },
1987 { "blt+", BBOCB(16,BOT,CBLT,0,0), BBOATCB_MASK, PPCCOM, { CR, BDP } },
1988 { "blt", BBOCB(16,BOT,CBLT,0,0), BBOATCB_MASK, COM, { CR, BD } },
1989 { "bltl-", BBOCB(16,BOT,CBLT,0,1), BBOATCB_MASK, PPCCOM, { CR, BDM } },
1990 { "bltl+", BBOCB(16,BOT,CBLT,0,1), BBOATCB_MASK, PPCCOM, { CR, BDP } },
1991 { "bltl", BBOCB(16,BOT,CBLT,0,1), BBOATCB_MASK, COM, { CR, BD } },
1992 { "blta-", BBOCB(16,BOT,CBLT,1,0), BBOATCB_MASK, PPCCOM, { CR, BDMA } },
1993 { "blta+", BBOCB(16,BOT,CBLT,1,0), BBOATCB_MASK, PPCCOM, { CR, BDPA } },
1994 { "blta", BBOCB(16,BOT,CBLT,1,0), BBOATCB_MASK, COM, { CR, BDA } },
1995 { "bltla-", BBOCB(16,BOT,CBLT,1,1), BBOATCB_MASK, PPCCOM, { CR, BDMA } },
1996 { "bltla+", BBOCB(16,BOT,CBLT,1,1), BBOATCB_MASK, PPCCOM, { CR, BDPA } },
1997 { "bltla", BBOCB(16,BOT,CBLT,1,1), BBOATCB_MASK, COM, { CR, BDA } },
1998 { "bgt-", BBOCB(16,BOT,CBGT,0,0), BBOATCB_MASK, PPCCOM, { CR, BDM } },
1999 { "bgt+", BBOCB(16,BOT,CBGT,0,0), BBOATCB_MASK, PPCCOM, { CR, BDP } },
2000 { "bgt", BBOCB(16,BOT,CBGT,0,0), BBOATCB_MASK, COM, { CR, BD } },
2001 { "bgtl-", BBOCB(16,BOT,CBGT,0,1), BBOATCB_MASK, PPCCOM, { CR, BDM } },
2002 { "bgtl+", BBOCB(16,BOT,CBGT,0,1), BBOATCB_MASK, PPCCOM, { CR, BDP } },
2003 { "bgtl", BBOCB(16,BOT,CBGT,0,1), BBOATCB_MASK, COM, { CR, BD } },
2004 { "bgta-", BBOCB(16,BOT,CBGT,1,0), BBOATCB_MASK, PPCCOM, { CR, BDMA } },
2005 { "bgta+", BBOCB(16,BOT,CBGT,1,0), BBOATCB_MASK, PPCCOM, { CR, BDPA } },
2006 { "bgta", BBOCB(16,BOT,CBGT,1,0), BBOATCB_MASK, COM, { CR, BDA } },
2007 { "bgtla-", BBOCB(16,BOT,CBGT,1,1), BBOATCB_MASK, PPCCOM, { CR, BDMA } },
2008 { "bgtla+", BBOCB(16,BOT,CBGT,1,1), BBOATCB_MASK, PPCCOM, { CR, BDPA } },
2009 { "bgtla", BBOCB(16,BOT,CBGT,1,1), BBOATCB_MASK, COM, { CR, BDA } },
2010 { "beq-", BBOCB(16,BOT,CBEQ,0,0), BBOATCB_MASK, PPCCOM, { CR, BDM } },
2011 { "beq+", BBOCB(16,BOT,CBEQ,0,0), BBOATCB_MASK, PPCCOM, { CR, BDP } },
2012 { "beq", BBOCB(16,BOT,CBEQ,0,0), BBOATCB_MASK, COM, { CR, BD } },
2013 { "beql-", BBOCB(16,BOT,CBEQ,0,1), BBOATCB_MASK, PPCCOM, { CR, BDM } },
2014 { "beql+", BBOCB(16,BOT,CBEQ,0,1), BBOATCB_MASK, PPCCOM, { CR, BDP } },
2015 { "beql", BBOCB(16,BOT,CBEQ,0,1), BBOATCB_MASK, COM, { CR, BD } },
2016 { "beqa-", BBOCB(16,BOT,CBEQ,1,0), BBOATCB_MASK, PPCCOM, { CR, BDMA } },
2017 { "beqa+", BBOCB(16,BOT,CBEQ,1,0), BBOATCB_MASK, PPCCOM, { CR, BDPA } },
2018 { "beqa", BBOCB(16,BOT,CBEQ,1,0), BBOATCB_MASK, COM, { CR, BDA } },
2019 { "beqla-", BBOCB(16,BOT,CBEQ,1,1), BBOATCB_MASK, PPCCOM, { CR, BDMA } },
2020 { "beqla+", BBOCB(16,BOT,CBEQ,1,1), BBOATCB_MASK, PPCCOM, { CR, BDPA } },
2021 { "beqla", BBOCB(16,BOT,CBEQ,1,1), BBOATCB_MASK, COM, { CR, BDA } },
2022 { "bso-", BBOCB(16,BOT,CBSO,0,0), BBOATCB_MASK, PPCCOM, { CR, BDM } },
2023 { "bso+", BBOCB(16,BOT,CBSO,0,0), BBOATCB_MASK, PPCCOM, { CR, BDP } },
2024 { "bso", BBOCB(16,BOT,CBSO,0,0), BBOATCB_MASK, COM, { CR, BD } },
2025 { "bsol-", BBOCB(16,BOT,CBSO,0,1), BBOATCB_MASK, PPCCOM, { CR, BDM } },
2026 { "bsol+", BBOCB(16,BOT,CBSO,0,1), BBOATCB_MASK, PPCCOM, { CR, BDP } },
2027 { "bsol", BBOCB(16,BOT,CBSO,0,1), BBOATCB_MASK, COM, { CR, BD } },
2028 { "bsoa-", BBOCB(16,BOT,CBSO,1,0), BBOATCB_MASK, PPCCOM, { CR, BDMA } },
2029 { "bsoa+", BBOCB(16,BOT,CBSO,1,0), BBOATCB_MASK, PPCCOM, { CR, BDPA } },
2030 { "bsoa", BBOCB(16,BOT,CBSO,1,0), BBOATCB_MASK, COM, { CR, BDA } },
2031 { "bsola-", BBOCB(16,BOT,CBSO,1,1), BBOATCB_MASK, PPCCOM, { CR, BDMA } },
2032 { "bsola+", BBOCB(16,BOT,CBSO,1,1), BBOATCB_MASK, PPCCOM, { CR, BDPA } },
2033 { "bsola", BBOCB(16,BOT,CBSO,1,1), BBOATCB_MASK, COM, { CR, BDA } },
2034 { "bun-", BBOCB(16,BOT,CBSO,0,0), BBOATCB_MASK, PPCCOM, { CR, BDM } },
2035 { "bun+", BBOCB(16,BOT,CBSO,0,0), BBOATCB_MASK, PPCCOM, { CR, BDP } },
2036 { "bun", BBOCB(16,BOT,CBSO,0,0), BBOATCB_MASK, PPCCOM, { CR, BD } },
2037 { "bunl-", BBOCB(16,BOT,CBSO,0,1), BBOATCB_MASK, PPCCOM, { CR, BDM } },
2038 { "bunl+", BBOCB(16,BOT,CBSO,0,1), BBOATCB_MASK, PPCCOM, { CR, BDP } },
2039 { "bunl", BBOCB(16,BOT,CBSO,0,1), BBOATCB_MASK, PPCCOM, { CR, BD } },
2040 { "buna-", BBOCB(16,BOT,CBSO,1,0), BBOATCB_MASK, PPCCOM, { CR, BDMA } },
2041 { "buna+", BBOCB(16,BOT,CBSO,1,0), BBOATCB_MASK, PPCCOM, { CR, BDPA } },
2042 { "buna", BBOCB(16,BOT,CBSO,1,0), BBOATCB_MASK, PPCCOM, { CR, BDA } },
2043 { "bunla-", BBOCB(16,BOT,CBSO,1,1), BBOATCB_MASK, PPCCOM, { CR, BDMA } },
2044 { "bunla+", BBOCB(16,BOT,CBSO,1,1), BBOATCB_MASK, PPCCOM, { CR, BDPA } },
2045 { "bunla", BBOCB(16,BOT,CBSO,1,1), BBOATCB_MASK, PPCCOM, { CR, BDA } },
2046 { "bge-", BBOCB(16,BOF,CBLT,0,0), BBOATCB_MASK, PPCCOM, { CR, BDM } },
2047 { "bge+", BBOCB(16,BOF,CBLT,0,0), BBOATCB_MASK, PPCCOM, { CR, BDP } },
2048 { "bge", BBOCB(16,BOF,CBLT,0,0), BBOATCB_MASK, COM, { CR, BD } },
2049 { "bgel-", BBOCB(16,BOF,CBLT,0,1), BBOATCB_MASK, PPCCOM, { CR, BDM } },
2050 { "bgel+", BBOCB(16,BOF,CBLT,0,1), BBOATCB_MASK, PPCCOM, { CR, BDP } },
2051 { "bgel", BBOCB(16,BOF,CBLT,0,1), BBOATCB_MASK, COM, { CR, BD } },
2052 { "bgea-", BBOCB(16,BOF,CBLT,1,0), BBOATCB_MASK, PPCCOM, { CR, BDMA } },
2053 { "bgea+", BBOCB(16,BOF,CBLT,1,0), BBOATCB_MASK, PPCCOM, { CR, BDPA } },
2054 { "bgea", BBOCB(16,BOF,CBLT,1,0), BBOATCB_MASK, COM, { CR, BDA } },
2055 { "bgela-", BBOCB(16,BOF,CBLT,1,1), BBOATCB_MASK, PPCCOM, { CR, BDMA } },
2056 { "bgela+", BBOCB(16,BOF,CBLT,1,1), BBOATCB_MASK, PPCCOM, { CR, BDPA } },
2057 { "bgela", BBOCB(16,BOF,CBLT,1,1), BBOATCB_MASK, COM, { CR, BDA } },
2058 { "bnl-", BBOCB(16,BOF,CBLT,0,0), BBOATCB_MASK, PPCCOM, { CR, BDM } },
2059 { "bnl+", BBOCB(16,BOF,CBLT,0,0), BBOATCB_MASK, PPCCOM, { CR, BDP } },
2060 { "bnl", BBOCB(16,BOF,CBLT,0,0), BBOATCB_MASK, COM, { CR, BD } },
2061 { "bnll-", BBOCB(16,BOF,CBLT,0,1), BBOATCB_MASK, PPCCOM, { CR, BDM } },
2062 { "bnll+", BBOCB(16,BOF,CBLT,0,1), BBOATCB_MASK, PPCCOM, { CR, BDP } },
2063 { "bnll", BBOCB(16,BOF,CBLT,0,1), BBOATCB_MASK, COM, { CR, BD } },
2064 { "bnla-", BBOCB(16,BOF,CBLT,1,0), BBOATCB_MASK, PPCCOM, { CR, BDMA } },
2065 { "bnla+", BBOCB(16,BOF,CBLT,1,0), BBOATCB_MASK, PPCCOM, { CR, BDPA } },
2066 { "bnla", BBOCB(16,BOF,CBLT,1,0), BBOATCB_MASK, COM, { CR, BDA } },
2067 { "bnlla-", BBOCB(16,BOF,CBLT,1,1), BBOATCB_MASK, PPCCOM, { CR, BDMA } },
2068 { "bnlla+", BBOCB(16,BOF,CBLT,1,1), BBOATCB_MASK, PPCCOM, { CR, BDPA } },
2069 { "bnlla", BBOCB(16,BOF,CBLT,1,1), BBOATCB_MASK, COM, { CR, BDA } },
2070 { "ble-", BBOCB(16,BOF,CBGT,0,0), BBOATCB_MASK, PPCCOM, { CR, BDM } },
2071 { "ble+", BBOCB(16,BOF,CBGT,0,0), BBOATCB_MASK, PPCCOM, { CR, BDP } },
2072 { "ble", BBOCB(16,BOF,CBGT,0,0), BBOATCB_MASK, COM, { CR, BD } },
2073 { "blel-", BBOCB(16,BOF,CBGT,0,1), BBOATCB_MASK, PPCCOM, { CR, BDM } },
2074 { "blel+", BBOCB(16,BOF,CBGT,0,1), BBOATCB_MASK, PPCCOM, { CR, BDP } },
2075 { "blel", BBOCB(16,BOF,CBGT,0,1), BBOATCB_MASK, COM, { CR, BD } },
2076 { "blea-", BBOCB(16,BOF,CBGT,1,0), BBOATCB_MASK, PPCCOM, { CR, BDMA } },
2077 { "blea+", BBOCB(16,BOF,CBGT,1,0), BBOATCB_MASK, PPCCOM, { CR, BDPA } },
2078 { "blea", BBOCB(16,BOF,CBGT,1,0), BBOATCB_MASK, COM, { CR, BDA } },
2079 { "blela-", BBOCB(16,BOF,CBGT,1,1), BBOATCB_MASK, PPCCOM, { CR, BDMA } },
2080 { "blela+", BBOCB(16,BOF,CBGT,1,1), BBOATCB_MASK, PPCCOM, { CR, BDPA } },
2081 { "blela", BBOCB(16,BOF,CBGT,1,1), BBOATCB_MASK, COM, { CR, BDA } },
2082 { "bng-", BBOCB(16,BOF,CBGT,0,0), BBOATCB_MASK, PPCCOM, { CR, BDM } },
2083 { "bng+", BBOCB(16,BOF,CBGT,0,0), BBOATCB_MASK, PPCCOM, { CR, BDP } },
2084 { "bng", BBOCB(16,BOF,CBGT,0,0), BBOATCB_MASK, COM, { CR, BD } },
2085 { "bngl-", BBOCB(16,BOF,CBGT,0,1), BBOATCB_MASK, PPCCOM, { CR, BDM } },
2086 { "bngl+", BBOCB(16,BOF,CBGT,0,1), BBOATCB_MASK, PPCCOM, { CR, BDP } },
2087 { "bngl", BBOCB(16,BOF,CBGT,0,1), BBOATCB_MASK, COM, { CR, BD } },
2088 { "bnga-", BBOCB(16,BOF,CBGT,1,0), BBOATCB_MASK, PPCCOM, { CR, BDMA } },
2089 { "bnga+", BBOCB(16,BOF,CBGT,1,0), BBOATCB_MASK, PPCCOM, { CR, BDPA } },
2090 { "bnga", BBOCB(16,BOF,CBGT,1,0), BBOATCB_MASK, COM, { CR, BDA } },
2091 { "bngla-", BBOCB(16,BOF,CBGT,1,1), BBOATCB_MASK, PPCCOM, { CR, BDMA } },
2092 { "bngla+", BBOCB(16,BOF,CBGT,1,1), BBOATCB_MASK, PPCCOM, { CR, BDPA } },
2093 { "bngla", BBOCB(16,BOF,CBGT,1,1), BBOATCB_MASK, COM, { CR, BDA } },
2094 { "bne-", BBOCB(16,BOF,CBEQ,0,0), BBOATCB_MASK, PPCCOM, { CR, BDM } },
2095 { "bne+", BBOCB(16,BOF,CBEQ,0,0), BBOATCB_MASK, PPCCOM, { CR, BDP } },
2096 { "bne", BBOCB(16,BOF,CBEQ,0,0), BBOATCB_MASK, COM, { CR, BD } },
2097 { "bnel-", BBOCB(16,BOF,CBEQ,0,1), BBOATCB_MASK, PPCCOM, { CR, BDM } },
2098 { "bnel+", BBOCB(16,BOF,CBEQ,0,1), BBOATCB_MASK, PPCCOM, { CR, BDP } },
2099 { "bnel", BBOCB(16,BOF,CBEQ,0,1), BBOATCB_MASK, COM, { CR, BD } },
2100 { "bnea-", BBOCB(16,BOF,CBEQ,1,0), BBOATCB_MASK, PPCCOM, { CR, BDMA } },
2101 { "bnea+", BBOCB(16,BOF,CBEQ,1,0), BBOATCB_MASK, PPCCOM, { CR, BDPA } },
2102 { "bnea", BBOCB(16,BOF,CBEQ,1,0), BBOATCB_MASK, COM, { CR, BDA } },
2103 { "bnela-", BBOCB(16,BOF,CBEQ,1,1), BBOATCB_MASK, PPCCOM, { CR, BDMA } },
2104 { "bnela+", BBOCB(16,BOF,CBEQ,1,1), BBOATCB_MASK, PPCCOM, { CR, BDPA } },
2105 { "bnela", BBOCB(16,BOF,CBEQ,1,1), BBOATCB_MASK, COM, { CR, BDA } },
2106 { "bns-", BBOCB(16,BOF,CBSO,0,0), BBOATCB_MASK, PPCCOM, { CR, BDM } },
2107 { "bns+", BBOCB(16,BOF,CBSO,0,0), BBOATCB_MASK, PPCCOM, { CR, BDP } },
2108 { "bns", BBOCB(16,BOF,CBSO,0,0), BBOATCB_MASK, COM, { CR, BD } },
2109 { "bnsl-", BBOCB(16,BOF,CBSO,0,1), BBOATCB_MASK, PPCCOM, { CR, BDM } },
2110 { "bnsl+", BBOCB(16,BOF,CBSO,0,1), BBOATCB_MASK, PPCCOM, { CR, BDP } },
2111 { "bnsl", BBOCB(16,BOF,CBSO,0,1), BBOATCB_MASK, COM, { CR, BD } },
2112 { "bnsa-", BBOCB(16,BOF,CBSO,1,0), BBOATCB_MASK, PPCCOM, { CR, BDMA } },
2113 { "bnsa+", BBOCB(16,BOF,CBSO,1,0), BBOATCB_MASK, PPCCOM, { CR, BDPA } },
2114 { "bnsa", BBOCB(16,BOF,CBSO,1,0), BBOATCB_MASK, COM, { CR, BDA } },
2115 { "bnsla-", BBOCB(16,BOF,CBSO,1,1), BBOATCB_MASK, PPCCOM, { CR, BDMA } },
2116 { "bnsla+", BBOCB(16,BOF,CBSO,1,1), BBOATCB_MASK, PPCCOM, { CR, BDPA } },
2117 { "bnsla", BBOCB(16,BOF,CBSO,1,1), BBOATCB_MASK, COM, { CR, BDA } },
2118 { "bnu-", BBOCB(16,BOF,CBSO,0,0), BBOATCB_MASK, PPCCOM, { CR, BDM } },
2119 { "bnu+", BBOCB(16,BOF,CBSO,0,0), BBOATCB_MASK, PPCCOM, { CR, BDP } },
2120 { "bnu", BBOCB(16,BOF,CBSO,0,0), BBOATCB_MASK, PPCCOM, { CR, BD } },
2121 { "bnul-", BBOCB(16,BOF,CBSO,0,1), BBOATCB_MASK, PPCCOM, { CR, BDM } },
2122 { "bnul+", BBOCB(16,BOF,CBSO,0,1), BBOATCB_MASK, PPCCOM, { CR, BDP } },
2123 { "bnul", BBOCB(16,BOF,CBSO,0,1), BBOATCB_MASK, PPCCOM, { CR, BD } },
2124 { "bnua-", BBOCB(16,BOF,CBSO,1,0), BBOATCB_MASK, PPCCOM, { CR, BDMA } },
2125 { "bnua+", BBOCB(16,BOF,CBSO,1,0), BBOATCB_MASK, PPCCOM, { CR, BDPA } },
2126 { "bnua", BBOCB(16,BOF,CBSO,1,0), BBOATCB_MASK, PPCCOM, { CR, BDA } },
2127 { "bnula-", BBOCB(16,BOF,CBSO,1,1), BBOATCB_MASK, PPCCOM, { CR, BDMA } },
2128 { "bnula+", BBOCB(16,BOF,CBSO,1,1), BBOATCB_MASK, PPCCOM, { CR, BDPA } },
2129 { "bnula", BBOCB(16,BOF,CBSO,1,1), BBOATCB_MASK, PPCCOM, { CR, BDA } },
2130 { "bdnzt-", BBO(16,BODNZT,0,0), BBOY_MASK, NOPOWER4, { BI, BDM } },
2131 { "bdnzt+", BBO(16,BODNZT,0,0), BBOY_MASK, NOPOWER4, { BI, BDP } },
2132 { "bdnzt", BBO(16,BODNZT,0,0), BBOY_MASK, PPCCOM, { BI, BD } },
2133 { "bdnztl-", BBO(16,BODNZT,0,1), BBOY_MASK, NOPOWER4, { BI, BDM } },
2134 { "bdnztl+", BBO(16,BODNZT,0,1), BBOY_MASK, NOPOWER4, { BI, BDP } },
2135 { "bdnztl", BBO(16,BODNZT,0,1), BBOY_MASK, PPCCOM, { BI, BD } },
2136 { "bdnzta-", BBO(16,BODNZT,1,0), BBOY_MASK, NOPOWER4, { BI, BDMA } },
2137 { "bdnzta+", BBO(16,BODNZT,1,0), BBOY_MASK, NOPOWER4, { BI, BDPA } },
2138 { "bdnzta", BBO(16,BODNZT,1,0), BBOY_MASK, PPCCOM, { BI, BDA } },
2139 { "bdnztla-",BBO(16,BODNZT,1,1), BBOY_MASK, NOPOWER4, { BI, BDMA } },
2140 { "bdnztla+",BBO(16,BODNZT,1,1), BBOY_MASK, NOPOWER4, { BI, BDPA } },
2141 { "bdnztla", BBO(16,BODNZT,1,1), BBOY_MASK, PPCCOM, { BI, BDA } },
2142 { "bdnzf-", BBO(16,BODNZF,0,0), BBOY_MASK, NOPOWER4, { BI, BDM } },
2143 { "bdnzf+", BBO(16,BODNZF,0,0), BBOY_MASK, NOPOWER4, { BI, BDP } },
2144 { "bdnzf", BBO(16,BODNZF,0,0), BBOY_MASK, PPCCOM, { BI, BD } },
2145 { "bdnzfl-", BBO(16,BODNZF,0,1), BBOY_MASK, NOPOWER4, { BI, BDM } },
2146 { "bdnzfl+", BBO(16,BODNZF,0,1), BBOY_MASK, NOPOWER4, { BI, BDP } },
2147 { "bdnzfl", BBO(16,BODNZF,0,1), BBOY_MASK, PPCCOM, { BI, BD } },
2148 { "bdnzfa-", BBO(16,BODNZF,1,0), BBOY_MASK, NOPOWER4, { BI, BDMA } },
2149 { "bdnzfa+", BBO(16,BODNZF,1,0), BBOY_MASK, NOPOWER4, { BI, BDPA } },
2150 { "bdnzfa", BBO(16,BODNZF,1,0), BBOY_MASK, PPCCOM, { BI, BDA } },
2151 { "bdnzfla-",BBO(16,BODNZF,1,1), BBOY_MASK, NOPOWER4, { BI, BDMA } },
2152 { "bdnzfla+",BBO(16,BODNZF,1,1), BBOY_MASK, NOPOWER4, { BI, BDPA } },
2153 { "bdnzfla", BBO(16,BODNZF,1,1), BBOY_MASK, PPCCOM, { BI, BDA } },
2154 { "bt-", BBO(16,BOT,0,0), BBOAT_MASK, PPCCOM, { BI, BDM } },
2155 { "bt+", BBO(16,BOT,0,0), BBOAT_MASK, PPCCOM, { BI, BDP } },
2156 { "bt", BBO(16,BOT,0,0), BBOAT_MASK, PPCCOM, { BI, BD } },
2157 { "bbt", BBO(16,BOT,0,0), BBOAT_MASK, PWRCOM, { BI, BD } },
2158 { "btl-", BBO(16,BOT,0,1), BBOAT_MASK, PPCCOM, { BI, BDM } },
2159 { "btl+", BBO(16,BOT,0,1), BBOAT_MASK, PPCCOM, { BI, BDP } },
2160 { "btl", BBO(16,BOT,0,1), BBOAT_MASK, PPCCOM, { BI, BD } },
2161 { "bbtl", BBO(16,BOT,0,1), BBOAT_MASK, PWRCOM, { BI, BD } },
2162 { "bta-", BBO(16,BOT,1,0), BBOAT_MASK, PPCCOM, { BI, BDMA } },
2163 { "bta+", BBO(16,BOT,1,0), BBOAT_MASK, PPCCOM, { BI, BDPA } },
2164 { "bta", BBO(16,BOT,1,0), BBOAT_MASK, PPCCOM, { BI, BDA } },
2165 { "bbta", BBO(16,BOT,1,0), BBOAT_MASK, PWRCOM, { BI, BDA } },
2166 { "btla-", BBO(16,BOT,1,1), BBOAT_MASK, PPCCOM, { BI, BDMA } },
2167 { "btla+", BBO(16,BOT,1,1), BBOAT_MASK, PPCCOM, { BI, BDPA } },
2168 { "btla", BBO(16,BOT,1,1), BBOAT_MASK, PPCCOM, { BI, BDA } },
2169 { "bbtla", BBO(16,BOT,1,1), BBOAT_MASK, PWRCOM, { BI, BDA } },
2170 { "bf-", BBO(16,BOF,0,0), BBOAT_MASK, PPCCOM, { BI, BDM } },
2171 { "bf+", BBO(16,BOF,0,0), BBOAT_MASK, PPCCOM, { BI, BDP } },
2172 { "bf", BBO(16,BOF,0,0), BBOAT_MASK, PPCCOM, { BI, BD } },
2173 { "bbf", BBO(16,BOF,0,0), BBOAT_MASK, PWRCOM, { BI, BD } },
2174 { "bfl-", BBO(16,BOF,0,1), BBOAT_MASK, PPCCOM, { BI, BDM } },
2175 { "bfl+", BBO(16,BOF,0,1), BBOAT_MASK, PPCCOM, { BI, BDP } },
2176 { "bfl", BBO(16,BOF,0,1), BBOAT_MASK, PPCCOM, { BI, BD } },
2177 { "bbfl", BBO(16,BOF,0,1), BBOAT_MASK, PWRCOM, { BI, BD } },
2178 { "bfa-", BBO(16,BOF,1,0), BBOAT_MASK, PPCCOM, { BI, BDMA } },
2179 { "bfa+", BBO(16,BOF,1,0), BBOAT_MASK, PPCCOM, { BI, BDPA } },
2180 { "bfa", BBO(16,BOF,1,0), BBOAT_MASK, PPCCOM, { BI, BDA } },
2181 { "bbfa", BBO(16,BOF,1,0), BBOAT_MASK, PWRCOM, { BI, BDA } },
2182 { "bfla-", BBO(16,BOF,1,1), BBOAT_MASK, PPCCOM, { BI, BDMA } },
2183 { "bfla+", BBO(16,BOF,1,1), BBOAT_MASK, PPCCOM, { BI, BDPA } },
2184 { "bfla", BBO(16,BOF,1,1), BBOAT_MASK, PPCCOM, { BI, BDA } },
2185 { "bbfla", BBO(16,BOF,1,1), BBOAT_MASK, PWRCOM, { BI, BDA } },
2186 { "bdzt-", BBO(16,BODZT,0,0), BBOY_MASK, NOPOWER4, { BI, BDM } },
2187 { "bdzt+", BBO(16,BODZT,0,0), BBOY_MASK, NOPOWER4, { BI, BDP } },
2188 { "bdzt", BBO(16,BODZT,0,0), BBOY_MASK, PPCCOM, { BI, BD } },
2189 { "bdztl-", BBO(16,BODZT,0,1), BBOY_MASK, NOPOWER4, { BI, BDM } },
2190 { "bdztl+", BBO(16,BODZT,0,1), BBOY_MASK, NOPOWER4, { BI, BDP } },
2191 { "bdztl", BBO(16,BODZT,0,1), BBOY_MASK, PPCCOM, { BI, BD } },
2192 { "bdzta-", BBO(16,BODZT,1,0), BBOY_MASK, NOPOWER4, { BI, BDMA } },
2193 { "bdzta+", BBO(16,BODZT,1,0), BBOY_MASK, NOPOWER4, { BI, BDPA } },
2194 { "bdzta", BBO(16,BODZT,1,0), BBOY_MASK, PPCCOM, { BI, BDA } },
2195 { "bdztla-", BBO(16,BODZT,1,1), BBOY_MASK, NOPOWER4, { BI, BDMA } },
2196 { "bdztla+", BBO(16,BODZT,1,1), BBOY_MASK, NOPOWER4, { BI, BDPA } },
2197 { "bdztla", BBO(16,BODZT,1,1), BBOY_MASK, PPCCOM, { BI, BDA } },
2198 { "bdzf-", BBO(16,BODZF,0,0), BBOY_MASK, NOPOWER4, { BI, BDM } },
2199 { "bdzf+", BBO(16,BODZF,0,0), BBOY_MASK, NOPOWER4, { BI, BDP } },
2200 { "bdzf", BBO(16,BODZF,0,0), BBOY_MASK, PPCCOM, { BI, BD } },
2201 { "bdzfl-", BBO(16,BODZF,0,1), BBOY_MASK, NOPOWER4, { BI, BDM } },
2202 { "bdzfl+", BBO(16,BODZF,0,1), BBOY_MASK, NOPOWER4, { BI, BDP } },
2203 { "bdzfl", BBO(16,BODZF,0,1), BBOY_MASK, PPCCOM, { BI, BD } },
2204 { "bdzfa-", BBO(16,BODZF,1,0), BBOY_MASK, NOPOWER4, { BI, BDMA } },
2205 { "bdzfa+", BBO(16,BODZF,1,0), BBOY_MASK, NOPOWER4, { BI, BDPA } },
2206 { "bdzfa", BBO(16,BODZF,1,0), BBOY_MASK, PPCCOM, { BI, BDA } },
2207 { "bdzfla-", BBO(16,BODZF,1,1), BBOY_MASK, NOPOWER4, { BI, BDMA } },
2208 { "bdzfla+", BBO(16,BODZF,1,1), BBOY_MASK, NOPOWER4, { BI, BDPA } },
2209 { "bdzfla", BBO(16,BODZF,1,1), BBOY_MASK, PPCCOM, { BI, BDA } },
2210 { "bc-", B(16,0,0), B_MASK, PPCCOM, { BOE, BI, BDM } },
2211 { "bc+", B(16,0,0), B_MASK, PPCCOM, { BOE, BI, BDP } },
2212 { "bc", B(16,0,0), B_MASK, COM, { BO, BI, BD } },
2213 { "bcl-", B(16,0,1), B_MASK, PPCCOM, { BOE, BI, BDM } },
2214 { "bcl+", B(16,0,1), B_MASK, PPCCOM, { BOE, BI, BDP } },
2215 { "bcl", B(16,0,1), B_MASK, COM, { BO, BI, BD } },
2216 { "bca-", B(16,1,0), B_MASK, PPCCOM, { BOE, BI, BDMA } },
2217 { "bca+", B(16,1,0), B_MASK, PPCCOM, { BOE, BI, BDPA } },
2218 { "bca", B(16,1,0), B_MASK, COM, { BO, BI, BDA } },
2219 { "bcla-", B(16,1,1), B_MASK, PPCCOM, { BOE, BI, BDMA } },
2220 { "bcla+", B(16,1,1), B_MASK, PPCCOM, { BOE, BI, BDPA } },
2221 { "bcla", B(16,1,1), B_MASK, COM, { BO, BI, BDA } },
2223 { "sc", SC(17,1,0), 0xffffffff, PPC, { 0 } },
2224 { "svc", SC(17,0,0), SC_MASK, POWER, { LEV, FL1, FL2 } },
2225 { "svcl", SC(17,0,1), SC_MASK, POWER, { LEV, FL1, FL2 } },
2226 { "svca", SC(17,1,0), SC_MASK, PWRCOM, { SV } },
2227 { "svcla", SC(17,1,1), SC_MASK, POWER, { SV } },
2229 { "b", B(18,0,0), B_MASK, COM, { LI } },
2230 { "bl", B(18,0,1), B_MASK, COM, { LI } },
2231 { "ba", B(18,1,0), B_MASK, COM, { LIA } },
2232 { "bla", B(18,1,1), B_MASK, COM, { LIA } },
2234 { "mcrf", XL(19,0), XLBB_MASK|(3<<21)|(3<<16), COM, { BF, BFA } },
2236 { "blr", XLO(19,BOU,16,0), XLBOBIBB_MASK, PPCCOM, { 0 } },
2237 { "br", XLO(19,BOU,16,0), XLBOBIBB_MASK, PWRCOM, { 0 } },
2238 { "blrl", XLO(19,BOU,16,1), XLBOBIBB_MASK, PPCCOM, { 0 } },
2239 { "brl", XLO(19,BOU,16,1), XLBOBIBB_MASK, PWRCOM, { 0 } },
2240 { "bdnzlr", XLO(19,BODNZ,16,0), XLBOBIBB_MASK, PPCCOM, { 0 } },
2241 { "bdnzlr-", XLO(19,BODNZ,16,0), XLBOBIBB_MASK, NOPOWER4, { 0 } },
2242 { "bdnzlr+", XLO(19,BODNZP,16,0), XLBOBIBB_MASK, NOPOWER4, { 0 } },
2243 { "bdnzlr-", XLO(19,BODNZM4,16,0), XLBOBIBB_MASK, POWER4, { 0 } },
2244 { "bdnzlr+", XLO(19,BODNZP4,16,0), XLBOBIBB_MASK, POWER4, { 0 } },
2245 { "bdnzlrl", XLO(19,BODNZ,16,1), XLBOBIBB_MASK, PPCCOM, { 0 } },
2246 { "bdnzlrl-",XLO(19,BODNZ,16,1), XLBOBIBB_MASK, NOPOWER4, { 0 } },
2247 { "bdnzlrl+",XLO(19,BODNZP,16,1), XLBOBIBB_MASK, NOPOWER4, { 0 } },
2248 { "bdnzlrl-",XLO(19,BODNZM4,16,1), XLBOBIBB_MASK, POWER4, { 0 } },
2249 { "bdnzlrl+",XLO(19,BODNZP4,16,1), XLBOBIBB_MASK, POWER4, { 0 } },
2250 { "bdzlr", XLO(19,BODZ,16,0), XLBOBIBB_MASK, PPCCOM, { 0 } },
2251 { "bdzlr-", XLO(19,BODZ,16,0), XLBOBIBB_MASK, NOPOWER4, { 0 } },
2252 { "bdzlr+", XLO(19,BODZP,16,0), XLBOBIBB_MASK, NOPOWER4, { 0 } },
2253 { "bdzlr-", XLO(19,BODZM4,16,0), XLBOBIBB_MASK, POWER4, { 0 } },
2254 { "bdzlr+", XLO(19,BODZP4,16,0), XLBOBIBB_MASK, POWER4, { 0 } },
2255 { "bdzlrl", XLO(19,BODZ,16,1), XLBOBIBB_MASK, PPCCOM, { 0 } },
2256 { "bdzlrl-", XLO(19,BODZ,16,1), XLBOBIBB_MASK, NOPOWER4, { 0 } },
2257 { "bdzlrl+", XLO(19,BODZP,16,1), XLBOBIBB_MASK, NOPOWER4, { 0 } },
2258 { "bdzlrl-", XLO(19,BODZM4,16,1), XLBOBIBB_MASK, POWER4, { 0 } },
2259 { "bdzlrl+", XLO(19,BODZP4,16,1), XLBOBIBB_MASK, POWER4, { 0 } },
2260 { "bltlr", XLOCB(19,BOT,CBLT,16,0), XLBOCBBB_MASK, PPCCOM, { CR } },
2261 { "bltlr-", XLOCB(19,BOT,CBLT,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2262 { "bltlr+", XLOCB(19,BOTP,CBLT,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2263 { "bltlr-", XLOCB(19,BOTM4,CBLT,16,0), XLBOCBBB_MASK, POWER4, { CR } },
2264 { "bltlr+", XLOCB(19,BOTP4,CBLT,16,0), XLBOCBBB_MASK, POWER4, { CR } },
2265 { "bltr", XLOCB(19,BOT,CBLT,16,0), XLBOCBBB_MASK, PWRCOM, { CR } },
2266 { "bltlrl", XLOCB(19,BOT,CBLT,16,1), XLBOCBBB_MASK, PPCCOM, { CR } },
2267 { "bltlrl-", XLOCB(19,BOT,CBLT,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2268 { "bltlrl+", XLOCB(19,BOTP,CBLT,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2269 { "bltlrl-", XLOCB(19,BOTM4,CBLT,16,1), XLBOCBBB_MASK, POWER4, { CR } },
2270 { "bltlrl+", XLOCB(19,BOTP4,CBLT,16,1), XLBOCBBB_MASK, POWER4, { CR } },
2271 { "bltrl", XLOCB(19,BOT,CBLT,16,1), XLBOCBBB_MASK, PWRCOM, { CR } },
2272 { "bgtlr", XLOCB(19,BOT,CBGT,16,0), XLBOCBBB_MASK, PPCCOM, { CR } },
2273 { "bgtlr-", XLOCB(19,BOT,CBGT,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2274 { "bgtlr+", XLOCB(19,BOTP,CBGT,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2275 { "bgtlr-", XLOCB(19,BOTM4,CBGT,16,0), XLBOCBBB_MASK, POWER4, { CR } },
2276 { "bgtlr+", XLOCB(19,BOTP4,CBGT,16,0), XLBOCBBB_MASK, POWER4, { CR } },
2277 { "bgtr", XLOCB(19,BOT,CBGT,16,0), XLBOCBBB_MASK, PWRCOM, { CR } },
2278 { "bgtlrl", XLOCB(19,BOT,CBGT,16,1), XLBOCBBB_MASK, PPCCOM, { CR } },
2279 { "bgtlrl-", XLOCB(19,BOT,CBGT,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2280 { "bgtlrl+", XLOCB(19,BOTP,CBGT,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2281 { "bgtlrl-", XLOCB(19,BOTM4,CBGT,16,1), XLBOCBBB_MASK, POWER4, { CR } },
2282 { "bgtlrl+", XLOCB(19,BOTP4,CBGT,16,1), XLBOCBBB_MASK, POWER4, { CR } },
2283 { "bgtrl", XLOCB(19,BOT,CBGT,16,1), XLBOCBBB_MASK, PWRCOM, { CR } },
2284 { "beqlr", XLOCB(19,BOT,CBEQ,16,0), XLBOCBBB_MASK, PPCCOM, { CR } },
2285 { "beqlr-", XLOCB(19,BOT,CBEQ,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2286 { "beqlr+", XLOCB(19,BOTP,CBEQ,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2287 { "beqlr-", XLOCB(19,BOTM4,CBEQ,16,0), XLBOCBBB_MASK, POWER4, { CR } },
2288 { "beqlr+", XLOCB(19,BOTP4,CBEQ,16,0), XLBOCBBB_MASK, POWER4, { CR } },
2289 { "beqr", XLOCB(19,BOT,CBEQ,16,0), XLBOCBBB_MASK, PWRCOM, { CR } },
2290 { "beqlrl", XLOCB(19,BOT,CBEQ,16,1), XLBOCBBB_MASK, PPCCOM, { CR } },
2291 { "beqlrl-", XLOCB(19,BOT,CBEQ,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2292 { "beqlrl+", XLOCB(19,BOTP,CBEQ,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2293 { "beqlrl-", XLOCB(19,BOTM4,CBEQ,16,1), XLBOCBBB_MASK, POWER4, { CR } },
2294 { "beqlrl+", XLOCB(19,BOTP4,CBEQ,16,1), XLBOCBBB_MASK, POWER4, { CR } },
2295 { "beqrl", XLOCB(19,BOT,CBEQ,16,1), XLBOCBBB_MASK, PWRCOM, { CR } },
2296 { "bsolr", XLOCB(19,BOT,CBSO,16,0), XLBOCBBB_MASK, PPCCOM, { CR } },
2297 { "bsolr-", XLOCB(19,BOT,CBSO,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2298 { "bsolr+", XLOCB(19,BOTP,CBSO,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2299 { "bsolr-", XLOCB(19,BOTM4,CBSO,16,0), XLBOCBBB_MASK, POWER4, { CR } },
2300 { "bsolr+", XLOCB(19,BOTP4,CBSO,16,0), XLBOCBBB_MASK, POWER4, { CR } },
2301 { "bsor", XLOCB(19,BOT,CBSO,16,0), XLBOCBBB_MASK, PWRCOM, { CR } },
2302 { "bsolrl", XLOCB(19,BOT,CBSO,16,1), XLBOCBBB_MASK, PPCCOM, { CR } },
2303 { "bsolrl-", XLOCB(19,BOT,CBSO,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2304 { "bsolrl+", XLOCB(19,BOTP,CBSO,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2305 { "bsolrl-", XLOCB(19,BOTM4,CBSO,16,1), XLBOCBBB_MASK, POWER4, { CR } },
2306 { "bsolrl+", XLOCB(19,BOTP4,CBSO,16,1), XLBOCBBB_MASK, POWER4, { CR } },
2307 { "bsorl", XLOCB(19,BOT,CBSO,16,1), XLBOCBBB_MASK, PWRCOM, { CR } },
2308 { "bunlr", XLOCB(19,BOT,CBSO,16,0), XLBOCBBB_MASK, PPCCOM, { CR } },
2309 { "bunlr-", XLOCB(19,BOT,CBSO,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2310 { "bunlr+", XLOCB(19,BOTP,CBSO,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2311 { "bunlr-", XLOCB(19,BOTM4,CBSO,16,0), XLBOCBBB_MASK, POWER4, { CR } },
2312 { "bunlr+", XLOCB(19,BOTP4,CBSO,16,0), XLBOCBBB_MASK, POWER4, { CR } },
2313 { "bunlrl", XLOCB(19,BOT,CBSO,16,1), XLBOCBBB_MASK, PPCCOM, { CR } },
2314 { "bunlrl-", XLOCB(19,BOT,CBSO,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2315 { "bunlrl+", XLOCB(19,BOTP,CBSO,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2316 { "bunlrl-", XLOCB(19,BOTM4,CBSO,16,1), XLBOCBBB_MASK, POWER4, { CR } },
2317 { "bunlrl+", XLOCB(19,BOTP4,CBSO,16,1), XLBOCBBB_MASK, POWER4, { CR } },
2318 { "bgelr", XLOCB(19,BOF,CBLT,16,0), XLBOCBBB_MASK, PPCCOM, { CR } },
2319 { "bgelr-", XLOCB(19,BOF,CBLT,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2320 { "bgelr+", XLOCB(19,BOFP,CBLT,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2321 { "bgelr-", XLOCB(19,BOFM4,CBLT,16,0), XLBOCBBB_MASK, POWER4, { CR } },
2322 { "bgelr+", XLOCB(19,BOFP4,CBLT,16,0), XLBOCBBB_MASK, POWER4, { CR } },
2323 { "bger", XLOCB(19,BOF,CBLT,16,0), XLBOCBBB_MASK, PWRCOM, { CR } },
2324 { "bgelrl", XLOCB(19,BOF,CBLT,16,1), XLBOCBBB_MASK, PPCCOM, { CR } },
2325 { "bgelrl-", XLOCB(19,BOF,CBLT,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2326 { "bgelrl+", XLOCB(19,BOFP,CBLT,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2327 { "bgelrl-", XLOCB(19,BOFM4,CBLT,16,1), XLBOCBBB_MASK, POWER4, { CR } },
2328 { "bgelrl+", XLOCB(19,BOFP4,CBLT,16,1), XLBOCBBB_MASK, POWER4, { CR } },
2329 { "bgerl", XLOCB(19,BOF,CBLT,16,1), XLBOCBBB_MASK, PWRCOM, { CR } },
2330 { "bnllr", XLOCB(19,BOF,CBLT,16,0), XLBOCBBB_MASK, PPCCOM, { CR } },
2331 { "bnllr-", XLOCB(19,BOF,CBLT,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2332 { "bnllr+", XLOCB(19,BOFP,CBLT,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2333 { "bnllr-", XLOCB(19,BOFM4,CBLT,16,0), XLBOCBBB_MASK, POWER4, { CR } },
2334 { "bnllr+", XLOCB(19,BOFP4,CBLT,16,0), XLBOCBBB_MASK, POWER4, { CR } },
2335 { "bnlr", XLOCB(19,BOF,CBLT,16,0), XLBOCBBB_MASK, PWRCOM, { CR } },
2336 { "bnllrl", XLOCB(19,BOF,CBLT,16,1), XLBOCBBB_MASK, PPCCOM, { CR } },
2337 { "bnllrl-", XLOCB(19,BOF,CBLT,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2338 { "bnllrl+", XLOCB(19,BOFP,CBLT,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2339 { "bnllrl-", XLOCB(19,BOFM4,CBLT,16,1), XLBOCBBB_MASK, POWER4, { CR } },
2340 { "bnllrl+", XLOCB(19,BOFP4,CBLT,16,1), XLBOCBBB_MASK, POWER4, { CR } },
2341 { "bnlrl", XLOCB(19,BOF,CBLT,16,1), XLBOCBBB_MASK, PWRCOM, { CR } },
2342 { "blelr", XLOCB(19,BOF,CBGT,16,0), XLBOCBBB_MASK, PPCCOM, { CR } },
2343 { "blelr-", XLOCB(19,BOF,CBGT,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2344 { "blelr+", XLOCB(19,BOFP,CBGT,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2345 { "blelr-", XLOCB(19,BOFM4,CBGT,16,0), XLBOCBBB_MASK, POWER4, { CR } },
2346 { "blelr+", XLOCB(19,BOFP4,CBGT,16,0), XLBOCBBB_MASK, POWER4, { CR } },
2347 { "bler", XLOCB(19,BOF,CBGT,16,0), XLBOCBBB_MASK, PWRCOM, { CR } },
2348 { "blelrl", XLOCB(19,BOF,CBGT,16,1), XLBOCBBB_MASK, PPCCOM, { CR } },
2349 { "blelrl-", XLOCB(19,BOF,CBGT,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2350 { "blelrl+", XLOCB(19,BOFP,CBGT,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2351 { "blelrl-", XLOCB(19,BOFM4,CBGT,16,1), XLBOCBBB_MASK, POWER4, { CR } },
2352 { "blelrl+", XLOCB(19,BOFP4,CBGT,16,1), XLBOCBBB_MASK, POWER4, { CR } },
2353 { "blerl", XLOCB(19,BOF,CBGT,16,1), XLBOCBBB_MASK, PWRCOM, { CR } },
2354 { "bnglr", XLOCB(19,BOF,CBGT,16,0), XLBOCBBB_MASK, PPCCOM, { CR } },
2355 { "bnglr-", XLOCB(19,BOF,CBGT,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2356 { "bnglr+", XLOCB(19,BOFP,CBGT,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2357 { "bnglr-", XLOCB(19,BOFM4,CBGT,16,0), XLBOCBBB_MASK, POWER4, { CR } },
2358 { "bnglr+", XLOCB(19,BOFP4,CBGT,16,0), XLBOCBBB_MASK, POWER4, { CR } },
2359 { "bngr", XLOCB(19,BOF,CBGT,16,0), XLBOCBBB_MASK, PWRCOM, { CR } },
2360 { "bnglrl", XLOCB(19,BOF,CBGT,16,1), XLBOCBBB_MASK, PPCCOM, { CR } },
2361 { "bnglrl-", XLOCB(19,BOF,CBGT,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2362 { "bnglrl+", XLOCB(19,BOFP,CBGT,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2363 { "bnglrl-", XLOCB(19,BOFM4,CBGT,16,1), XLBOCBBB_MASK, POWER4, { CR } },
2364 { "bnglrl+", XLOCB(19,BOFP4,CBGT,16,1), XLBOCBBB_MASK, POWER4, { CR } },
2365 { "bngrl", XLOCB(19,BOF,CBGT,16,1), XLBOCBBB_MASK, PWRCOM, { CR } },
2366 { "bnelr", XLOCB(19,BOF,CBEQ,16,0), XLBOCBBB_MASK, PPCCOM, { CR } },
2367 { "bnelr-", XLOCB(19,BOF,CBEQ,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2368 { "bnelr+", XLOCB(19,BOFP,CBEQ,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2369 { "bnelr-", XLOCB(19,BOFM4,CBEQ,16,0), XLBOCBBB_MASK, POWER4, { CR } },
2370 { "bnelr+", XLOCB(19,BOFP4,CBEQ,16,0), XLBOCBBB_MASK, POWER4, { CR } },
2371 { "bner", XLOCB(19,BOF,CBEQ,16,0), XLBOCBBB_MASK, PWRCOM, { CR } },
2372 { "bnelrl", XLOCB(19,BOF,CBEQ,16,1), XLBOCBBB_MASK, PPCCOM, { CR } },
2373 { "bnelrl-", XLOCB(19,BOF,CBEQ,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2374 { "bnelrl+", XLOCB(19,BOFP,CBEQ,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2375 { "bnelrl-", XLOCB(19,BOFM4,CBEQ,16,1), XLBOCBBB_MASK, POWER4, { CR } },
2376 { "bnelrl+", XLOCB(19,BOFP4,CBEQ,16,1), XLBOCBBB_MASK, POWER4, { CR } },
2377 { "bnerl", XLOCB(19,BOF,CBEQ,16,1), XLBOCBBB_MASK, PWRCOM, { CR } },
2378 { "bnslr", XLOCB(19,BOF,CBSO,16,0), XLBOCBBB_MASK, PPCCOM, { CR } },
2379 { "bnslr-", XLOCB(19,BOF,CBSO,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2380 { "bnslr+", XLOCB(19,BOFP,CBSO,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2381 { "bnslr-", XLOCB(19,BOFM4,CBSO,16,0), XLBOCBBB_MASK, POWER4, { CR } },
2382 { "bnslr+", XLOCB(19,BOFP4,CBSO,16,0), XLBOCBBB_MASK, POWER4, { CR } },
2383 { "bnsr", XLOCB(19,BOF,CBSO,16,0), XLBOCBBB_MASK, PWRCOM, { CR } },
2384 { "bnslrl", XLOCB(19,BOF,CBSO,16,1), XLBOCBBB_MASK, PPCCOM, { CR } },
2385 { "bnslrl-", XLOCB(19,BOF,CBSO,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2386 { "bnslrl+", XLOCB(19,BOFP,CBSO,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2387 { "bnslrl-", XLOCB(19,BOFM4,CBSO,16,1), XLBOCBBB_MASK, POWER4, { CR } },
2388 { "bnslrl+", XLOCB(19,BOFP4,CBSO,16,1), XLBOCBBB_MASK, POWER4, { CR } },
2389 { "bnsrl", XLOCB(19,BOF,CBSO,16,1), XLBOCBBB_MASK, PWRCOM, { CR } },
2390 { "bnulr", XLOCB(19,BOF,CBSO,16,0), XLBOCBBB_MASK, PPCCOM, { CR } },
2391 { "bnulr-", XLOCB(19,BOF,CBSO,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2392 { "bnulr+", XLOCB(19,BOFP,CBSO,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2393 { "bnulr-", XLOCB(19,BOFM4,CBSO,16,0), XLBOCBBB_MASK, POWER4, { CR } },
2394 { "bnulr+", XLOCB(19,BOFP4,CBSO,16,0), XLBOCBBB_MASK, POWER4, { CR } },
2395 { "bnulrl", XLOCB(19,BOF,CBSO,16,1), XLBOCBBB_MASK, PPCCOM, { CR } },
2396 { "bnulrl-", XLOCB(19,BOF,CBSO,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2397 { "bnulrl+", XLOCB(19,BOFP,CBSO,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2398 { "bnulrl-", XLOCB(19,BOFM4,CBSO,16,1), XLBOCBBB_MASK, POWER4, { CR } },
2399 { "bnulrl+", XLOCB(19,BOFP4,CBSO,16,1), XLBOCBBB_MASK, POWER4, { CR } },
2400 { "btlr", XLO(19,BOT,16,0), XLBOBB_MASK, PPCCOM, { BI } },
2401 { "btlr-", XLO(19,BOT,16,0), XLBOBB_MASK, NOPOWER4, { BI } },
2402 { "btlr+", XLO(19,BOTP,16,0), XLBOBB_MASK, NOPOWER4, { BI } },
2403 { "btlr-", XLO(19,BOTM4,16,0), XLBOBB_MASK, POWER4, { BI } },
2404 { "btlr+", XLO(19,BOTP4,16,0), XLBOBB_MASK, POWER4, { BI } },
2405 { "bbtr", XLO(19,BOT,16,0), XLBOBB_MASK, PWRCOM, { BI } },
2406 { "btlrl", XLO(19,BOT,16,1), XLBOBB_MASK, PPCCOM, { BI } },
2407 { "btlrl-", XLO(19,BOT,16,1), XLBOBB_MASK, NOPOWER4, { BI } },
2408 { "btlrl+", XLO(19,BOTP,16,1), XLBOBB_MASK, NOPOWER4, { BI } },
2409 { "btlrl-", XLO(19,BOTM4,16,1), XLBOBB_MASK, POWER4, { BI } },
2410 { "btlrl+", XLO(19,BOTP4,16,1), XLBOBB_MASK, POWER4, { BI } },
2411 { "bbtrl", XLO(19,BOT,16,1), XLBOBB_MASK, PWRCOM, { BI } },
2412 { "bflr", XLO(19,BOF,16,0), XLBOBB_MASK, PPCCOM, { BI } },
2413 { "bflr-", XLO(19,BOF,16,0), XLBOBB_MASK, NOPOWER4, { BI } },
2414 { "bflr+", XLO(19,BOFP,16,0), XLBOBB_MASK, NOPOWER4, { BI } },
2415 { "bflr-", XLO(19,BOFM4,16,0), XLBOBB_MASK, POWER4, { BI } },
2416 { "bflr+", XLO(19,BOFP4,16,0), XLBOBB_MASK, POWER4, { BI } },
2417 { "bbfr", XLO(19,BOF,16,0), XLBOBB_MASK, PWRCOM, { BI } },
2418 { "bflrl", XLO(19,BOF,16,1), XLBOBB_MASK, PPCCOM, { BI } },
2419 { "bflrl-", XLO(19,BOF,16,1), XLBOBB_MASK, NOPOWER4, { BI } },
2420 { "bflrl+", XLO(19,BOFP,16,1), XLBOBB_MASK, NOPOWER4, { BI } },
2421 { "bflrl-", XLO(19,BOFM4,16,1), XLBOBB_MASK, POWER4, { BI } },
2422 { "bflrl+", XLO(19,BOFP4,16,1), XLBOBB_MASK, POWER4, { BI } },
2423 { "bbfrl", XLO(19,BOF,16,1), XLBOBB_MASK, PWRCOM, { BI } },
2424 { "bdnztlr", XLO(19,BODNZT,16,0), XLBOBB_MASK, PPCCOM, { BI } },
2425 { "bdnztlr-",XLO(19,BODNZT,16,0), XLBOBB_MASK, NOPOWER4, { BI } },
2426 { "bdnztlr+",XLO(19,BODNZTP,16,0), XLBOBB_MASK, NOPOWER4, { BI } },
2427 { "bdnztlrl",XLO(19,BODNZT,16,1), XLBOBB_MASK, PPCCOM, { BI } },
2428 { "bdnztlrl-",XLO(19,BODNZT,16,1), XLBOBB_MASK, NOPOWER4, { BI } },
2429 { "bdnztlrl+",XLO(19,BODNZTP,16,1), XLBOBB_MASK, NOPOWER4, { BI } },
2430 { "bdnzflr", XLO(19,BODNZF,16,0), XLBOBB_MASK, PPCCOM, { BI } },
2431 { "bdnzflr-",XLO(19,BODNZF,16,0), XLBOBB_MASK, NOPOWER4, { BI } },
2432 { "bdnzflr+",XLO(19,BODNZFP,16,0), XLBOBB_MASK, NOPOWER4, { BI } },
2433 { "bdnzflrl",XLO(19,BODNZF,16,1), XLBOBB_MASK, PPCCOM, { BI } },
2434 { "bdnzflrl-",XLO(19,BODNZF,16,1), XLBOBB_MASK, NOPOWER4, { BI } },
2435 { "bdnzflrl+",XLO(19,BODNZFP,16,1), XLBOBB_MASK, NOPOWER4, { BI } },
2436 { "bdztlr", XLO(19,BODZT,16,0), XLBOBB_MASK, PPCCOM, { BI } },
2437 { "bdztlr-", XLO(19,BODZT,16,0), XLBOBB_MASK, NOPOWER4, { BI } },
2438 { "bdztlr+", XLO(19,BODZTP,16,0), XLBOBB_MASK, NOPOWER4, { BI } },
2439 { "bdztlrl", XLO(19,BODZT,16,1), XLBOBB_MASK, PPCCOM, { BI } },
2440 { "bdztlrl-",XLO(19,BODZT,16,1), XLBOBB_MASK, NOPOWER4, { BI } },
2441 { "bdztlrl+",XLO(19,BODZTP,16,1), XLBOBB_MASK, NOPOWER4, { BI } },
2442 { "bdzflr", XLO(19,BODZF,16,0), XLBOBB_MASK, PPCCOM, { BI } },
2443 { "bdzflr-", XLO(19,BODZF,16,0), XLBOBB_MASK, NOPOWER4, { BI } },
2444 { "bdzflr+", XLO(19,BODZFP,16,0), XLBOBB_MASK, NOPOWER4, { BI } },
2445 { "bdzflrl", XLO(19,BODZF,16,1), XLBOBB_MASK, PPCCOM, { BI } },
2446 { "bdzflrl-",XLO(19,BODZF,16,1), XLBOBB_MASK, NOPOWER4, { BI } },
2447 { "bdzflrl+",XLO(19,BODZFP,16,1), XLBOBB_MASK, NOPOWER4, { BI } },
2448 { "bclr", XLLK(19,16,0), XLYBB_MASK, PPCCOM, { BO, BI } },
2449 { "bclrl", XLLK(19,16,1), XLYBB_MASK, PPCCOM, { BO, BI } },
2450 { "bclr+", XLYLK(19,16,1,0), XLYBB_MASK, PPCCOM, { BOE, BI } },
2451 { "bclrl+", XLYLK(19,16,1,1), XLYBB_MASK, PPCCOM, { BOE, BI } },
2452 { "bclr-", XLYLK(19,16,0,0), XLYBB_MASK, PPCCOM, { BOE, BI } },
2453 { "bclrl-", XLYLK(19,16,0,1), XLYBB_MASK, PPCCOM, { BOE, BI } },
2454 { "bcr", XLLK(19,16,0), XLBB_MASK, PWRCOM, { BO, BI } },
2455 { "bcrl", XLLK(19,16,1), XLBB_MASK, PWRCOM, { BO, BI } },
2456 { "bclre", XLLK(19,17,0), XLBB_MASK, BOOKE64, { BO, BI } },
2457 { "bclrel", XLLK(19,17,1), XLBB_MASK, BOOKE64, { BO, BI } },
2459 { "rfid", XL(19,18), 0xffffffff, PPC64, { 0 } },
2461 { "crnot", XL(19,33), XL_MASK, PPCCOM, { BT, BA, BBA } },
2462 { "crnor", XL(19,33), XL_MASK, COM, { BT, BA, BB } },
2464 { "rfi", XL(19,50), 0xffffffff, COM, { 0 } },
2465 { "rfci", XL(19,51), 0xffffffff, PPC403, { 0 } },
2466 { "rfci", XL(19,51), 0xffffffff, BOOKE, { 0 } },
2468 { "rfsvc", XL(19,82), 0xffffffff, POWER, { 0 } },
2470 { "crandc", XL(19,129), XL_MASK, COM, { BT, BA, BB } },
2472 { "isync", XL(19,150), 0xffffffff, PPCCOM, { 0 } },
2473 { "ics", XL(19,150), 0xffffffff, PWRCOM, { 0 } },
2475 { "crclr", XL(19,193), XL_MASK, PPCCOM, { BT, BAT, BBA } },
2476 { "crxor", XL(19,193), XL_MASK, COM, { BT, BA, BB } },
2478 { "crnand", XL(19,225), XL_MASK, COM, { BT, BA, BB } },
2480 { "crand", XL(19,257), XL_MASK, COM, { BT, BA, BB } },
2482 { "crset", XL(19,289), XL_MASK, PPCCOM, { BT, BAT, BBA } },
2483 { "creqv", XL(19,289), XL_MASK, COM, { BT, BA, BB } },
2485 { "crorc", XL(19,417), XL_MASK, COM, { BT, BA, BB } },
2487 { "crmove", XL(19,449), XL_MASK, PPCCOM, { BT, BA, BBA } },
2488 { "cror", XL(19,449), XL_MASK, COM, { BT, BA, BB } },
2490 { "bctr", XLO(19,BOU,528,0), XLBOBIBB_MASK, COM, { 0 } },
2491 { "bctrl", XLO(19,BOU,528,1), XLBOBIBB_MASK, COM, { 0 } },
2492 { "bltctr", XLOCB(19,BOT,CBLT,528,0), XLBOCBBB_MASK, PPCCOM, { CR } },
2493 { "bltctr-", XLOCB(19,BOT,CBLT,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2494 { "bltctr+", XLOCB(19,BOTP,CBLT,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2495 { "bltctr-", XLOCB(19,BOTM4,CBLT,528,0), XLBOCBBB_MASK, POWER4, { CR } },
2496 { "bltctr+", XLOCB(19,BOTP4,CBLT,528,0), XLBOCBBB_MASK, POWER4, { CR } },
2497 { "bltctrl", XLOCB(19,BOT,CBLT,528,1), XLBOCBBB_MASK, PPCCOM, { CR } },
2498 { "bltctrl-",XLOCB(19,BOT,CBLT,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2499 { "bltctrl+",XLOCB(19,BOTP,CBLT,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2500 { "bltctrl-",XLOCB(19,BOTM4,CBLT,528,1), XLBOCBBB_MASK, POWER4, { CR } },
2501 { "bltctrl+",XLOCB(19,BOTP4,CBLT,528,1), XLBOCBBB_MASK, POWER4, { CR } },
2502 { "bgtctr", XLOCB(19,BOT,CBGT,528,0), XLBOCBBB_MASK, PPCCOM, { CR } },
2503 { "bgtctr-", XLOCB(19,BOT,CBGT,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2504 { "bgtctr+", XLOCB(19,BOTP,CBGT,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2505 { "bgtctr-", XLOCB(19,BOTM4,CBGT,528,0), XLBOCBBB_MASK, POWER4, { CR } },
2506 { "bgtctr+", XLOCB(19,BOTP4,CBGT,528,0), XLBOCBBB_MASK, POWER4, { CR } },
2507 { "bgtctrl", XLOCB(19,BOT,CBGT,528,1), XLBOCBBB_MASK, PPCCOM, { CR } },
2508 { "bgtctrl-",XLOCB(19,BOT,CBGT,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2509 { "bgtctrl+",XLOCB(19,BOTP,CBGT,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2510 { "bgtctrl-",XLOCB(19,BOTM4,CBGT,528,1), XLBOCBBB_MASK, POWER4, { CR } },
2511 { "bgtctrl+",XLOCB(19,BOTP4,CBGT,528,1), XLBOCBBB_MASK, POWER4, { CR } },
2512 { "beqctr", XLOCB(19,BOT,CBEQ,528,0), XLBOCBBB_MASK, PPCCOM, { CR } },
2513 { "beqctr-", XLOCB(19,BOT,CBEQ,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2514 { "beqctr+", XLOCB(19,BOTP,CBEQ,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2515 { "beqctr-", XLOCB(19,BOTM4,CBEQ,528,0), XLBOCBBB_MASK, POWER4, { CR } },
2516 { "beqctr+", XLOCB(19,BOTP4,CBEQ,528,0), XLBOCBBB_MASK, POWER4, { CR } },
2517 { "beqctrl", XLOCB(19,BOT,CBEQ,528,1), XLBOCBBB_MASK, PPCCOM, { CR } },
2518 { "beqctrl-",XLOCB(19,BOT,CBEQ,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2519 { "beqctrl+",XLOCB(19,BOTP,CBEQ,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2520 { "beqctrl-",XLOCB(19,BOTM4,CBEQ,528,1), XLBOCBBB_MASK, POWER4, { CR } },
2521 { "beqctrl+",XLOCB(19,BOTP4,CBEQ,528,1), XLBOCBBB_MASK, POWER4, { CR } },
2522 { "bsoctr", XLOCB(19,BOT,CBSO,528,0), XLBOCBBB_MASK, PPCCOM, { CR } },
2523 { "bsoctr-", XLOCB(19,BOT,CBSO,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2524 { "bsoctr+", XLOCB(19,BOTP,CBSO,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2525 { "bsoctr-", XLOCB(19,BOTM4,CBSO,528,0), XLBOCBBB_MASK, POWER4, { CR } },
2526 { "bsoctr+", XLOCB(19,BOTP4,CBSO,528,0), XLBOCBBB_MASK, POWER4, { CR } },
2527 { "bsoctrl", XLOCB(19,BOT,CBSO,528,1), XLBOCBBB_MASK, PPCCOM, { CR } },
2528 { "bsoctrl-",XLOCB(19,BOT,CBSO,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2529 { "bsoctrl+",XLOCB(19,BOTP,CBSO,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2530 { "bsoctrl-",XLOCB(19,BOTM4,CBSO,528,1), XLBOCBBB_MASK, POWER4, { CR } },
2531 { "bsoctrl+",XLOCB(19,BOTP4,CBSO,528,1), XLBOCBBB_MASK, POWER4, { CR } },
2532 { "bunctr", XLOCB(19,BOT,CBSO,528,0), XLBOCBBB_MASK, PPCCOM, { CR } },
2533 { "bunctr-", XLOCB(19,BOT,CBSO,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2534 { "bunctr+", XLOCB(19,BOTP,CBSO,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2535 { "bunctr-", XLOCB(19,BOTM4,CBSO,528,0), XLBOCBBB_MASK, POWER4, { CR } },
2536 { "bunctr+", XLOCB(19,BOTP4,CBSO,528,0), XLBOCBBB_MASK, POWER4, { CR } },
2537 { "bunctrl", XLOCB(19,BOT,CBSO,528,1), XLBOCBBB_MASK, PPCCOM, { CR } },
2538 { "bunctrl-",XLOCB(19,BOT,CBSO,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2539 { "bunctrl+",XLOCB(19,BOTP,CBSO,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2540 { "bunctrl-",XLOCB(19,BOTM4,CBSO,528,1), XLBOCBBB_MASK, POWER4, { CR } },
2541 { "bunctrl+",XLOCB(19,BOTP4,CBSO,528,1), XLBOCBBB_MASK, POWER4, { CR } },
2542 { "bgectr", XLOCB(19,BOF,CBLT,528,0), XLBOCBBB_MASK, PPCCOM, { CR } },
2543 { "bgectr-", XLOCB(19,BOF,CBLT,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2544 { "bgectr+", XLOCB(19,BOFP,CBLT,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2545 { "bgectr-", XLOCB(19,BOFM4,CBLT,528,0), XLBOCBBB_MASK, POWER4, { CR } },
2546 { "bgectr+", XLOCB(19,BOFP4,CBLT,528,0), XLBOCBBB_MASK, POWER4, { CR } },
2547 { "bgectrl", XLOCB(19,BOF,CBLT,528,1), XLBOCBBB_MASK, PPCCOM, { CR } },
2548 { "bgectrl-",XLOCB(19,BOF,CBLT,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2549 { "bgectrl+",XLOCB(19,BOFP,CBLT,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2550 { "bgectrl-",XLOCB(19,BOFM4,CBLT,528,1), XLBOCBBB_MASK, POWER4, { CR } },
2551 { "bgectrl+",XLOCB(19,BOFP4,CBLT,528,1), XLBOCBBB_MASK, POWER4, { CR } },
2552 { "bnlctr", XLOCB(19,BOF,CBLT,528,0), XLBOCBBB_MASK, PPCCOM, { CR } },
2553 { "bnlctr-", XLOCB(19,BOF,CBLT,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2554 { "bnlctr+", XLOCB(19,BOFP,CBLT,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2555 { "bnlctr-", XLOCB(19,BOFM4,CBLT,528,0), XLBOCBBB_MASK, POWER4, { CR } },
2556 { "bnlctr+", XLOCB(19,BOFP4,CBLT,528,0), XLBOCBBB_MASK, POWER4, { CR } },
2557 { "bnlctrl", XLOCB(19,BOF,CBLT,528,1), XLBOCBBB_MASK, PPCCOM, { CR } },
2558 { "bnlctrl-",XLOCB(19,BOF,CBLT,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2559 { "bnlctrl+",XLOCB(19,BOFP,CBLT,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2560 { "bnlctrl-",XLOCB(19,BOFM4,CBLT,528,1), XLBOCBBB_MASK, POWER4, { CR } },
2561 { "bnlctrl+",XLOCB(19,BOFP4,CBLT,528,1), XLBOCBBB_MASK, POWER4, { CR } },
2562 { "blectr", XLOCB(19,BOF,CBGT,528,0), XLBOCBBB_MASK, PPCCOM, { CR } },
2563 { "blectr-", XLOCB(19,BOF,CBGT,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2564 { "blectr+", XLOCB(19,BOFP,CBGT,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2565 { "blectr-", XLOCB(19,BOFM4,CBGT,528,0), XLBOCBBB_MASK, POWER4, { CR } },
2566 { "blectr+", XLOCB(19,BOFP4,CBGT,528,0), XLBOCBBB_MASK, POWER4, { CR } },
2567 { "blectrl", XLOCB(19,BOF,CBGT,528,1), XLBOCBBB_MASK, PPCCOM, { CR } },
2568 { "blectrl-",XLOCB(19,BOF,CBGT,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2569 { "blectrl+",XLOCB(19,BOFP,CBGT,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2570 { "blectrl-",XLOCB(19,BOFM4,CBGT,528,1), XLBOCBBB_MASK, POWER4, { CR } },
2571 { "blectrl+",XLOCB(19,BOFP4,CBGT,528,1), XLBOCBBB_MASK, POWER4, { CR } },
2572 { "bngctr", XLOCB(19,BOF,CBGT,528,0), XLBOCBBB_MASK, PPCCOM, { CR } },
2573 { "bngctr-", XLOCB(19,BOF,CBGT,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2574 { "bngctr+", XLOCB(19,BOFP,CBGT,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2575 { "bngctr-", XLOCB(19,BOFM4,CBGT,528,0), XLBOCBBB_MASK, POWER4, { CR } },
2576 { "bngctr+", XLOCB(19,BOFP4,CBGT,528,0), XLBOCBBB_MASK, POWER4, { CR } },
2577 { "bngctrl", XLOCB(19,BOF,CBGT,528,1), XLBOCBBB_MASK, PPCCOM, { CR } },
2578 { "bngctrl-",XLOCB(19,BOF,CBGT,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2579 { "bngctrl+",XLOCB(19,BOFP,CBGT,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2580 { "bngctrl-",XLOCB(19,BOFM4,CBGT,528,1), XLBOCBBB_MASK, POWER4, { CR } },
2581 { "bngctrl+",XLOCB(19,BOFP4,CBGT,528,1), XLBOCBBB_MASK, POWER4, { CR } },
2582 { "bnectr", XLOCB(19,BOF,CBEQ,528,0), XLBOCBBB_MASK, PPCCOM, { CR } },
2583 { "bnectr-", XLOCB(19,BOF,CBEQ,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2584 { "bnectr+", XLOCB(19,BOFP,CBEQ,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2585 { "bnectr-", XLOCB(19,BOFM4,CBEQ,528,0), XLBOCBBB_MASK, POWER4, { CR } },
2586 { "bnectr+", XLOCB(19,BOFP4,CBEQ,528,0), XLBOCBBB_MASK, POWER4, { CR } },
2587 { "bnectrl", XLOCB(19,BOF,CBEQ,528,1), XLBOCBBB_MASK, PPCCOM, { CR } },
2588 { "bnectrl-",XLOCB(19,BOF,CBEQ,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2589 { "bnectrl+",XLOCB(19,BOFP,CBEQ,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2590 { "bnectrl-",XLOCB(19,BOFM4,CBEQ,528,1), XLBOCBBB_MASK, POWER4, { CR } },
2591 { "bnectrl+",XLOCB(19,BOFP4,CBEQ,528,1), XLBOCBBB_MASK, POWER4, { CR } },
2592 { "bnsctr", XLOCB(19,BOF,CBSO,528,0), XLBOCBBB_MASK, PPCCOM, { CR } },
2593 { "bnsctr-", XLOCB(19,BOF,CBSO,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2594 { "bnsctr+", XLOCB(19,BOFP,CBSO,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2595 { "bnsctr-", XLOCB(19,BOFM4,CBSO,528,0), XLBOCBBB_MASK, POWER4, { CR } },
2596 { "bnsctr+", XLOCB(19,BOFP4,CBSO,528,0), XLBOCBBB_MASK, POWER4, { CR } },
2597 { "bnsctrl", XLOCB(19,BOF,CBSO,528,1), XLBOCBBB_MASK, PPCCOM, { CR } },
2598 { "bnsctrl-",XLOCB(19,BOF,CBSO,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2599 { "bnsctrl+",XLOCB(19,BOFP,CBSO,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2600 { "bnsctrl-",XLOCB(19,BOFM4,CBSO,528,1), XLBOCBBB_MASK, POWER4, { CR } },
2601 { "bnsctrl+",XLOCB(19,BOFP4,CBSO,528,1), XLBOCBBB_MASK, POWER4, { CR } },
2602 { "bnuctr", XLOCB(19,BOF,CBSO,528,0), XLBOCBBB_MASK, PPCCOM, { CR } },
2603 { "bnuctr-", XLOCB(19,BOF,CBSO,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2604 { "bnuctr+", XLOCB(19,BOFP,CBSO,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2605 { "bnuctr-", XLOCB(19,BOFM4,CBSO,528,0), XLBOCBBB_MASK, POWER4, { CR } },
2606 { "bnuctr+", XLOCB(19,BOFP4,CBSO,528,0), XLBOCBBB_MASK, POWER4, { CR } },
2607 { "bnuctrl", XLOCB(19,BOF,CBSO,528,1), XLBOCBBB_MASK, PPCCOM, { CR } },
2608 { "bnuctrl-",XLOCB(19,BOF,CBSO,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2609 { "bnuctrl+",XLOCB(19,BOFP,CBSO,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2610 { "bnuctrl-",XLOCB(19,BOFM4,CBSO,528,1), XLBOCBBB_MASK, POWER4, { CR } },
2611 { "bnuctrl+",XLOCB(19,BOFP4,CBSO,528,1), XLBOCBBB_MASK, POWER4, { CR } },
2612 { "btctr", XLO(19,BOT,528,0), XLBOBB_MASK, PPCCOM, { BI } },
2613 { "btctr-", XLO(19,BOT,528,0), XLBOBB_MASK, NOPOWER4, { BI } },
2614 { "btctr+", XLO(19,BOTP,528,0), XLBOBB_MASK, NOPOWER4, { BI } },
2615 { "btctr-", XLO(19,BOTM4,528,0), XLBOBB_MASK, POWER4, { BI } },
2616 { "btctr+", XLO(19,BOTP4,528,0), XLBOBB_MASK, POWER4, { BI } },
2617 { "btctrl", XLO(19,BOT,528,1), XLBOBB_MASK, PPCCOM, { BI } },
2618 { "btctrl-", XLO(19,BOT,528,1), XLBOBB_MASK, NOPOWER4, { BI } },
2619 { "btctrl+", XLO(19,BOTP,528,1), XLBOBB_MASK, NOPOWER4, { BI } },
2620 { "btctrl-", XLO(19,BOTM4,528,1), XLBOBB_MASK, POWER4, { BI } },
2621 { "btctrl+", XLO(19,BOTP4,528,1), XLBOBB_MASK, POWER4, { BI } },
2622 { "bfctr", XLO(19,BOF,528,0), XLBOBB_MASK, PPCCOM, { BI } },
2623 { "bfctr-", XLO(19,BOF,528,0), XLBOBB_MASK, NOPOWER4, { BI } },
2624 { "bfctr+", XLO(19,BOFP,528,0), XLBOBB_MASK, NOPOWER4, { BI } },
2625 { "bfctr-", XLO(19,BOFM4,528,0), XLBOBB_MASK, POWER4, { BI } },
2626 { "bfctr+", XLO(19,BOFP4,528,0), XLBOBB_MASK, POWER4, { BI } },
2627 { "bfctrl", XLO(19,BOF,528,1), XLBOBB_MASK, PPCCOM, { BI } },
2628 { "bfctrl-", XLO(19,BOF,528,1), XLBOBB_MASK, NOPOWER4, { BI } },
2629 { "bfctrl+", XLO(19,BOFP,528,1), XLBOBB_MASK, NOPOWER4, { BI } },
2630 { "bfctrl-", XLO(19,BOFM4,528,1), XLBOBB_MASK, POWER4, { BI } },
2631 { "bfctrl+", XLO(19,BOFP4,528,1), XLBOBB_MASK, POWER4, { BI } },
2632 { "bcctr", XLLK(19,528,0), XLYBB_MASK, PPCCOM, { BO, BI } },
2633 { "bcctr-", XLYLK(19,528,0,0), XLYBB_MASK, PPCCOM, { BOE, BI } },
2634 { "bcctr+", XLYLK(19,528,1,0), XLYBB_MASK, PPCCOM, { BOE, BI } },
2635 { "bcctrl", XLLK(19,528,1), XLYBB_MASK, PPCCOM, { BO, BI } },
2636 { "bcctrl-", XLYLK(19,528,0,1), XLYBB_MASK, PPCCOM, { BOE, BI } },
2637 { "bcctrl+", XLYLK(19,528,1,1), XLYBB_MASK, PPCCOM, { BOE, BI } },
2638 { "bcc", XLLK(19,528,0), XLBB_MASK, PWRCOM, { BO, BI } },
2639 { "bccl", XLLK(19,528,1), XLBB_MASK, PWRCOM, { BO, BI } },
2640 { "bcctre", XLLK(19,529,0), XLYBB_MASK, BOOKE64, { BO, BI } },
2641 { "bcctrel", XLLK(19,529,1), XLYBB_MASK, BOOKE64, { BO, BI } },
2643 { "rlwimi", M(20,0), M_MASK, PPCCOM, { RA,RS,SH,MBE,ME } },
2644 { "rlimi", M(20,0), M_MASK, PWRCOM, { RA,RS,SH,MBE,ME } },
2646 { "rlwimi.", M(20,1), M_MASK, PPCCOM, { RA,RS,SH,MBE,ME } },
2647 { "rlimi.", M(20,1), M_MASK, PWRCOM, { RA,RS,SH,MBE,ME } },
2649 { "rotlwi", MME(21,31,0), MMBME_MASK, PPCCOM, { RA, RS, SH } },
2650 { "clrlwi", MME(21,31,0), MSHME_MASK, PPCCOM, { RA, RS, MB } },
2651 { "rlwinm", M(21,0), M_MASK, PPCCOM, { RA,RS,SH,MBE,ME } },
2652 { "rlinm", M(21,0), M_MASK, PWRCOM, { RA,RS,SH,MBE,ME } },
2653 { "rotlwi.", MME(21,31,1), MMBME_MASK, PPCCOM, { RA,RS,SH } },
2654 { "clrlwi.", MME(21,31,1), MSHME_MASK, PPCCOM, { RA, RS, MB } },
2655 { "rlwinm.", M(21,1), M_MASK, PPCCOM, { RA,RS,SH,MBE,ME } },
2656 { "rlinm.", M(21,1), M_MASK, PWRCOM, { RA,RS,SH,MBE,ME } },
2658 { "rlmi", M(22,0), M_MASK, M601, { RA,RS,RB,MBE,ME } },
2659 { "rlmi.", M(22,1), M_MASK, M601, { RA,RS,RB,MBE,ME } },
2661 { "be", B(22,0,0), B_MASK, BOOKE64, { LI } },
2662 { "bel", B(22,0,1), B_MASK, BOOKE64, { LI } },
2663 { "bea", B(22,1,0), B_MASK, BOOKE64, { LIA } },
2664 { "bela", B(22,1,1), B_MASK, BOOKE64, { LIA } },
2666 { "rotlw", MME(23,31,0), MMBME_MASK, PPCCOM, { RA, RS, RB } },
2667 { "rlwnm", M(23,0), M_MASK, PPCCOM, { RA,RS,RB,MBE,ME } },
2668 { "rlnm", M(23,0), M_MASK, PWRCOM, { RA,RS,RB,MBE,ME } },
2669 { "rotlw.", MME(23,31,1), MMBME_MASK, PPCCOM, { RA, RS, RB } },
2670 { "rlwnm.", M(23,1), M_MASK, PPCCOM, { RA,RS,RB,MBE,ME } },
2671 { "rlnm.", M(23,1), M_MASK, PWRCOM, { RA,RS,RB,MBE,ME } },
2673 { "nop", OP(24), 0xffffffff, PPCCOM, { 0 } },
2674 { "ori", OP(24), OP_MASK, PPCCOM, { RA, RS, UI } },
2675 { "oril", OP(24), OP_MASK, PWRCOM, { RA, RS, UI } },
2677 { "oris", OP(25), OP_MASK, PPCCOM, { RA, RS, UI } },
2678 { "oriu", OP(25), OP_MASK, PWRCOM, { RA, RS, UI } },
2680 { "xori", OP(26), OP_MASK, PPCCOM, { RA, RS, UI } },
2681 { "xoril", OP(26), OP_MASK, PWRCOM, { RA, RS, UI } },
2683 { "xoris", OP(27), OP_MASK, PPCCOM, { RA, RS, UI } },
2684 { "xoriu", OP(27), OP_MASK, PWRCOM, { RA, RS, UI } },
2686 { "andi.", OP(28), OP_MASK, PPCCOM, { RA, RS, UI } },
2687 { "andil.", OP(28), OP_MASK, PWRCOM, { RA, RS, UI } },
2689 { "andis.", OP(29), OP_MASK, PPCCOM, { RA, RS, UI } },
2690 { "andiu.", OP(29), OP_MASK, PWRCOM, { RA, RS, UI } },
2692 { "rotldi", MD(30,0,0), MDMB_MASK, PPC64, { RA, RS, SH6 } },
2693 { "clrldi", MD(30,0,0), MDSH_MASK, PPC64, { RA, RS, MB6 } },
2694 { "rldicl", MD(30,0,0), MD_MASK, PPC64, { RA, RS, SH6, MB6 } },
2695 { "rotldi.", MD(30,0,1), MDMB_MASK, PPC64, { RA, RS, SH6 } },
2696 { "clrldi.", MD(30,0,1), MDSH_MASK, PPC64, { RA, RS, MB6 } },
2697 { "rldicl.", MD(30,0,1), MD_MASK, PPC64, { RA, RS, SH6, MB6 } },
2699 { "rldicr", MD(30,1,0), MD_MASK, PPC64, { RA, RS, SH6, ME6 } },
2700 { "rldicr.", MD(30,1,1), MD_MASK, PPC64, { RA, RS, SH6, ME6 } },
2702 { "rldic", MD(30,2,0), MD_MASK, PPC64, { RA, RS, SH6, MB6 } },
2703 { "rldic.", MD(30,2,1), MD_MASK, PPC64, { RA, RS, SH6, MB6 } },
2705 { "rldimi", MD(30,3,0), MD_MASK, PPC64, { RA, RS, SH6, MB6 } },
2706 { "rldimi.", MD(30,3,1), MD_MASK, PPC64, { RA, RS, SH6, MB6 } },
2708 { "rotld", MDS(30,8,0), MDSMB_MASK, PPC64, { RA, RS, RB } },
2709 { "rldcl", MDS(30,8,0), MDS_MASK, PPC64, { RA, RS, RB, MB6 } },
2710 { "rotld.", MDS(30,8,1), MDSMB_MASK, PPC64, { RA, RS, RB } },
2711 { "rldcl.", MDS(30,8,1), MDS_MASK, PPC64, { RA, RS, RB, MB6 } },
2713 { "rldcr", MDS(30,9,0), MDS_MASK, PPC64, { RA, RS, RB, ME6 } },
2714 { "rldcr.", MDS(30,9,1), MDS_MASK, PPC64, { RA, RS, RB, ME6 } },
2716 { "cmpw", XCMPL(31,0,0), XCMPL_MASK, PPCCOM, { OBF, RA, RB } },
2717 { "cmpd", XCMPL(31,0,1), XCMPL_MASK, PPC64, { OBF, RA, RB } },
2718 { "cmp", X(31,0), XCMP_MASK, PPCONLY, { BF, L, RA, RB } },
2719 { "cmp", X(31,0), XCMPL_MASK, PWRCOM, { BF, RA, RB } },
2721 { "twlgt", XTO(31,4,TOLGT), XTO_MASK, PPCCOM, { RA, RB } },
2722 { "tlgt", XTO(31,4,TOLGT), XTO_MASK, PWRCOM, { RA, RB } },
2723 { "twllt", XTO(31,4,TOLLT), XTO_MASK, PPCCOM, { RA, RB } },
2724 { "tllt", XTO(31,4,TOLLT), XTO_MASK, PWRCOM, { RA, RB } },
2725 { "tweq", XTO(31,4,TOEQ), XTO_MASK, PPCCOM, { RA, RB } },
2726 { "teq", XTO(31,4,TOEQ), XTO_MASK, PWRCOM, { RA, RB } },
2727 { "twlge", XTO(31,4,TOLGE), XTO_MASK, PPCCOM, { RA, RB } },
2728 { "tlge", XTO(31,4,TOLGE), XTO_MASK, PWRCOM, { RA, RB } },
2729 { "twlnl", XTO(31,4,TOLNL), XTO_MASK, PPCCOM, { RA, RB } },
2730 { "tlnl", XTO(31,4,TOLNL), XTO_MASK, PWRCOM, { RA, RB } },
2731 { "twlle", XTO(31,4,TOLLE), XTO_MASK, PPCCOM, { RA, RB } },
2732 { "tlle", XTO(31,4,TOLLE), XTO_MASK, PWRCOM, { RA, RB } },
2733 { "twlng", XTO(31,4,TOLNG), XTO_MASK, PPCCOM, { RA, RB } },
2734 { "tlng", XTO(31,4,TOLNG), XTO_MASK, PWRCOM, { RA, RB } },
2735 { "twgt", XTO(31,4,TOGT), XTO_MASK, PPCCOM, { RA, RB } },
2736 { "tgt", XTO(31,4,TOGT), XTO_MASK, PWRCOM, { RA, RB } },
2737 { "twge", XTO(31,4,TOGE), XTO_MASK, PPCCOM, { RA, RB } },
2738 { "tge", XTO(31,4,TOGE), XTO_MASK, PWRCOM, { RA, RB } },
2739 { "twnl", XTO(31,4,TONL), XTO_MASK, PPCCOM, { RA, RB } },
2740 { "tnl", XTO(31,4,TONL), XTO_MASK, PWRCOM, { RA, RB } },
2741 { "twlt", XTO(31,4,TOLT), XTO_MASK, PPCCOM, { RA, RB } },
2742 { "tlt", XTO(31,4,TOLT), XTO_MASK, PWRCOM, { RA, RB } },
2743 { "twle", XTO(31,4,TOLE), XTO_MASK, PPCCOM, { RA, RB } },
2744 { "tle", XTO(31,4,TOLE), XTO_MASK, PWRCOM, { RA, RB } },
2745 { "twng", XTO(31,4,TONG), XTO_MASK, PPCCOM, { RA, RB } },
2746 { "tng", XTO(31,4,TONG), XTO_MASK, PWRCOM, { RA, RB } },
2747 { "twne", XTO(31,4,TONE), XTO_MASK, PPCCOM, { RA, RB } },
2748 { "tne", XTO(31,4,TONE), XTO_MASK, PWRCOM, { RA, RB } },
2749 { "trap", XTO(31,4,TOU), 0xffffffff, PPCCOM, { 0 } },
2750 { "tw", X(31,4), X_MASK, PPCCOM, { TO, RA, RB } },
2751 { "t", X(31,4), X_MASK, PWRCOM, { TO, RA, RB } },
2753 { "subfc", XO(31,8,0,0), XO_MASK, PPCCOM, { RT, RA, RB } },
2754 { "sf", XO(31,8,0,0), XO_MASK, PWRCOM, { RT, RA, RB } },
2755 { "subc", XO(31,8,0,0), XO_MASK, PPC, { RT, RB, RA } },
2756 { "subfc.", XO(31,8,0,1), XO_MASK, PPCCOM, { RT, RA, RB } },
2757 { "sf.", XO(31,8,0,1), XO_MASK, PWRCOM, { RT, RA, RB } },
2758 { "subc.", XO(31,8,0,1), XO_MASK, PPCCOM, { RT, RB, RA } },
2759 { "subfco", XO(31,8,1,0), XO_MASK, PPCCOM, { RT, RA, RB } },
2760 { "sfo", XO(31,8,1,0), XO_MASK, PWRCOM, { RT, RA, RB } },
2761 { "subco", XO(31,8,1,0), XO_MASK, PPC, { RT, RB, RA } },
2762 { "subfco.", XO(31,8,1,1), XO_MASK, PPCCOM, { RT, RA, RB } },
2763 { "sfo.", XO(31,8,1,1), XO_MASK, PWRCOM, { RT, RA, RB } },
2764 { "subco.", XO(31,8,1,1), XO_MASK, PPC, { RT, RB, RA } },
2766 { "mulhdu", XO(31,9,0,0), XO_MASK, PPC64, { RT, RA, RB } },
2767 { "mulhdu.", XO(31,9,0,1), XO_MASK, PPC64, { RT, RA, RB } },
2769 { "addc", XO(31,10,0,0), XO_MASK, PPCCOM, { RT, RA, RB } },
2770 { "a", XO(31,10,0,0), XO_MASK, PWRCOM, { RT, RA, RB } },
2771 { "addc.", XO(31,10,0,1), XO_MASK, PPCCOM, { RT, RA, RB } },
2772 { "a.", XO(31,10,0,1), XO_MASK, PWRCOM, { RT, RA, RB } },
2773 { "addco", XO(31,10,1,0), XO_MASK, PPCCOM, { RT, RA, RB } },
2774 { "ao", XO(31,10,1,0), XO_MASK, PWRCOM, { RT, RA, RB } },
2775 { "addco.", XO(31,10,1,1), XO_MASK, PPCCOM, { RT, RA, RB } },
2776 { "ao.", XO(31,10,1,1), XO_MASK, PWRCOM, { RT, RA, RB } },
2778 { "mulhwu", XO(31,11,0,0), XO_MASK, PPC, { RT, RA, RB } },
2779 { "mulhwu.", XO(31,11,0,1), XO_MASK, PPC, { RT, RA, RB } },
2781 { "mfcr", X(31,19), XRARB_MASK, COM, { RT } },
2783 { "lwarx", X(31,20), X_MASK, PPC, { RT, RA, RB } },
2785 { "ldx", X(31,21), X_MASK, PPC64, { RT, RA, RB } },
2787 { "icbt", X(31,22), X_MASK, BOOKE, { CT, RA, RB } },
2789 { "lwzx", X(31,23), X_MASK, PPCCOM, { RT, RA, RB } },
2790 { "lx", X(31,23), X_MASK, PWRCOM, { RT, RA, RB } },
2792 { "slw", XRC(31,24,0), X_MASK, PPCCOM, { RA, RS, RB } },
2793 { "sl", XRC(31,24,0), X_MASK, PWRCOM, { RA, RS, RB } },
2794 { "slw.", XRC(31,24,1), X_MASK, PPCCOM, { RA, RS, RB } },
2795 { "sl.", XRC(31,24,1), X_MASK, PWRCOM, { RA, RS, RB } },
2797 { "cntlzw", XRC(31,26,0), XRB_MASK, PPCCOM, { RA, RS } },
2798 { "cntlz", XRC(31,26,0), XRB_MASK, PWRCOM, { RA, RS } },
2799 { "cntlzw.", XRC(31,26,1), XRB_MASK, PPCCOM, { RA, RS } },
2800 { "cntlz.", XRC(31,26,1), XRB_MASK, PWRCOM, { RA, RS } },
2802 { "sld", XRC(31,27,0), X_MASK, PPC64, { RA, RS, RB } },
2803 { "sld.", XRC(31,27,1), X_MASK, PPC64, { RA, RS, RB } },
2805 { "and", XRC(31,28,0), X_MASK, COM, { RA, RS, RB } },
2806 { "and.", XRC(31,28,1), X_MASK, COM, { RA, RS, RB } },
2808 { "maskg", XRC(31,29,0), X_MASK, M601, { RA, RS, RB } },
2809 { "maskg.", XRC(31,29,1), X_MASK, M601, { RA, RS, RB } },
2811 { "icbte", X(31,30), X_MASK, BOOKE64, { CT, RA, RB } },
2813 { "lwzxe", X(31,31), X_MASK, BOOKE64, { RT, RA, RB } },
2815 { "cmplw", XCMPL(31,32,0), XCMPL_MASK, PPCCOM, { OBF, RA, RB } },
2816 { "cmpld", XCMPL(31,32,1), XCMPL_MASK, PPC64, { OBF, RA, RB } },
2817 { "cmpl", X(31,32), XCMP_MASK, PPCONLY, { BF, L, RA, RB } },
2818 { "cmpl", X(31,32), XCMPL_MASK, PWRCOM, { BF, RA, RB } },
2820 { "subf", XO(31,40,0,0), XO_MASK, PPC, { RT, RA, RB } },
2821 { "sub", XO(31,40,0,0), XO_MASK, PPC, { RT, RB, RA } },
2822 { "subf.", XO(31,40,0,1), XO_MASK, PPC, { RT, RA, RB } },
2823 { "sub.", XO(31,40,0,1), XO_MASK, PPC, { RT, RB, RA } },
2824 { "subfo", XO(31,40,1,0), XO_MASK, PPC, { RT, RA, RB } },
2825 { "subo", XO(31,40,1,0), XO_MASK, PPC, { RT, RB, RA } },
2826 { "subfo.", XO(31,40,1,1), XO_MASK, PPC, { RT, RA, RB } },
2827 { "subo.", XO(31,40,1,1), XO_MASK, PPC, { RT, RB, RA } },
2829 { "ldux", X(31,53), X_MASK, PPC64, { RT, RAL, RB } },
2831 { "dcbst", X(31,54), XRT_MASK, PPC, { RA, RB } },
2833 { "lwzux", X(31,55), X_MASK, PPCCOM, { RT, RAL, RB } },
2834 { "lux", X(31,55), X_MASK, PWRCOM, { RT, RA, RB } },
2836 { "dcbste", X(31,62), XRT_MASK, BOOKE64, { RA, RB } },
2838 { "lwzuxe", X(31,63), X_MASK, BOOKE64, { RT, RAL, RB } },
2840 { "cntlzd", XRC(31,58,0), XRB_MASK, PPC64, { RA, RS } },
2841 { "cntlzd.", XRC(31,58,1), XRB_MASK, PPC64, { RA, RS } },
2843 { "andc", XRC(31,60,0), X_MASK, COM, { RA, RS, RB } },
2844 { "andc.", XRC(31,60,1), X_MASK, COM, { RA, RS, RB } },
2846 { "tdlgt", XTO(31,68,TOLGT), XTO_MASK, PPC64, { RA, RB } },
2847 { "tdllt", XTO(31,68,TOLLT), XTO_MASK, PPC64, { RA, RB } },
2848 { "tdeq", XTO(31,68,TOEQ), XTO_MASK, PPC64, { RA, RB } },
2849 { "tdlge", XTO(31,68,TOLGE), XTO_MASK, PPC64, { RA, RB } },
2850 { "tdlnl", XTO(31,68,TOLNL), XTO_MASK, PPC64, { RA, RB } },
2851 { "tdlle", XTO(31,68,TOLLE), XTO_MASK, PPC64, { RA, RB } },
2852 { "tdlng", XTO(31,68,TOLNG), XTO_MASK, PPC64, { RA, RB } },
2853 { "tdgt", XTO(31,68,TOGT), XTO_MASK, PPC64, { RA, RB } },
2854 { "tdge", XTO(31,68,TOGE), XTO_MASK, PPC64, { RA, RB } },
2855 { "tdnl", XTO(31,68,TONL), XTO_MASK, PPC64, { RA, RB } },
2856 { "tdlt", XTO(31,68,TOLT), XTO_MASK, PPC64, { RA, RB } },
2857 { "tdle", XTO(31,68,TOLE), XTO_MASK, PPC64, { RA, RB } },
2858 { "tdng", XTO(31,68,TONG), XTO_MASK, PPC64, { RA, RB } },
2859 { "tdne", XTO(31,68,TONE), XTO_MASK, PPC64, { RA, RB } },
2860 { "td", X(31,68), X_MASK, PPC64, { TO, RA, RB } },
2862 { "mulhd", XO(31,73,0,0), XO_MASK, PPC64, { RT, RA, RB } },
2863 { "mulhd.", XO(31,73,0,1), XO_MASK, PPC64, { RT, RA, RB } },
2865 { "mulhw", XO(31,75,0,0), XO_MASK, PPC, { RT, RA, RB } },
2866 { "mulhw.", XO(31,75,0,1), XO_MASK, PPC, { RT, RA, RB } },
2868 { "mtsrd", X(31,82), XRB_MASK|(1<<20), PPC64, { SR, RS } },
2870 { "mfmsr", X(31,83), XRARB_MASK, COM, { RT } },
2872 { "ldarx", X(31,84), X_MASK, PPC64, { RT, RA, RB } },
2874 { "dcbf", X(31,86), XRT_MASK, PPC, { RA, RB } },
2876 { "lbzx", X(31,87), X_MASK, COM, { RT, RA, RB } },
2878 { "dcbfe", X(31,94), XRT_MASK, BOOKE64, { RA, RB } },
2880 { "lbzxe", X(31,95), X_MASK, BOOKE64, { RT, RA, RB } },
2882 { "neg", XO(31,104,0,0), XORB_MASK, COM, { RT, RA } },
2883 { "neg.", XO(31,104,0,1), XORB_MASK, COM, { RT, RA } },
2884 { "nego", XO(31,104,1,0), XORB_MASK, COM, { RT, RA } },
2885 { "nego.", XO(31,104,1,1), XORB_MASK, COM, { RT, RA } },
2887 { "mul", XO(31,107,0,0), XO_MASK, M601, { RT, RA, RB } },
2888 { "mul.", XO(31,107,0,1), XO_MASK, M601, { RT, RA, RB } },
2889 { "mulo", XO(31,107,1,0), XO_MASK, M601, { RT, RA, RB } },
2890 { "mulo.", XO(31,107,1,1), XO_MASK, M601, { RT, RA, RB } },
2892 { "mtsrdin", X(31,114), XRA_MASK, PPC64, { RS, RB } },
2894 { "clf", X(31,118), XTO_MASK, POWER, { RA, RB } },
2896 { "lbzux", X(31,119), X_MASK, COM, { RT, RAL, RB } },
2898 { "not", XRC(31,124,0), X_MASK, COM, { RA, RS, RBS } },
2899 { "nor", XRC(31,124,0), X_MASK, COM, { RA, RS, RB } },
2900 { "not.", XRC(31,124,1), X_MASK, COM, { RA, RS, RBS } },
2901 { "nor.", XRC(31,124,1), X_MASK, COM, { RA, RS, RB } },
2903 { "lwarxe", X(31,126), X_MASK, BOOKE64, { RT, RA, RB } },
2905 { "lbzuxe", X(31,127), X_MASK, BOOKE64, { RT, RAL, RB } },
2907 { "wrtee", X(31,131), XRARB_MASK, PPC403, { RS } },
2908 { "wrtee", X(31,131), XRARB_MASK, BOOKE, { RS } },
2910 { "subfe", XO(31,136,0,0), XO_MASK, PPCCOM, { RT, RA, RB } },
2911 { "sfe", XO(31,136,0,0), XO_MASK, PWRCOM, { RT, RA, RB } },
2912 { "subfe.", XO(31,136,0,1), XO_MASK, PPCCOM, { RT, RA, RB } },
2913 { "sfe.", XO(31,136,0,1), XO_MASK, PWRCOM, { RT, RA, RB } },
2914 { "subfeo", XO(31,136,1,0), XO_MASK, PPCCOM, { RT, RA, RB } },
2915 { "sfeo", XO(31,136,1,0), XO_MASK, PWRCOM, { RT, RA, RB } },
2916 { "subfeo.", XO(31,136,1,1), XO_MASK, PPCCOM, { RT, RA, RB } },
2917 { "sfeo.", XO(31,136,1,1), XO_MASK, PWRCOM, { RT, RA, RB } },
2919 { "adde", XO(31,138,0,0), XO_MASK, PPCCOM, { RT, RA, RB } },
2920 { "ae", XO(31,138,0,0), XO_MASK, PWRCOM, { RT, RA, RB } },
2921 { "adde.", XO(31,138,0,1), XO_MASK, PPCCOM, { RT, RA, RB } },
2922 { "ae.", XO(31,138,0,1), XO_MASK, PWRCOM, { RT, RA, RB } },
2923 { "addeo", XO(31,138,1,0), XO_MASK, PPCCOM, { RT, RA, RB } },
2924 { "aeo", XO(31,138,1,0), XO_MASK, PWRCOM, { RT, RA, RB } },
2925 { "addeo.", XO(31,138,1,1), XO_MASK, PPCCOM, { RT, RA, RB } },
2926 { "aeo.", XO(31,138,1,1), XO_MASK, PWRCOM, { RT, RA, RB } },
2928 { "mtcr", XFXM(31,144,0xff), XFXFXM_MASK|FXM_MASK, COM, { RS }},
2929 { "mtcrf", X(31,144), XFXFXM_MASK, COM, { FXM, RS } },
2931 { "mtmsr", X(31,146), XRARB_MASK, COM, { RS } },
2933 { "stdx", X(31,149), X_MASK, PPC64, { RS, RA, RB } },
2935 { "stwcx.", XRC(31,150,1), X_MASK, PPC, { RS, RA, RB } },
2937 { "stwx", X(31,151), X_MASK, PPCCOM, { RS, RA, RB } },
2938 { "stx", X(31,151), X_MASK, PWRCOM, { RS, RA, RB } },
2940 { "stwcxe.", XRC(31,158,1), X_MASK, BOOKE64, { RS, RA, RB } },
2942 { "stwxe", X(31,159), X_MASK, BOOKE64, { RS, RA, RB } },
2944 { "slq", XRC(31,152,0), X_MASK, M601, { RA, RS, RB } },
2945 { "slq.", XRC(31,152,1), X_MASK, M601, { RA, RS, RB } },
2947 { "sle", XRC(31,153,0), X_MASK, M601, { RA, RS, RB } },
2948 { "sle.", XRC(31,153,1), X_MASK, M601, { RA, RS, RB } },
2950 { "wrteei", X(31,163), XE_MASK, PPC403, { E } },
2951 { "wrteei", X(31,163), XE_MASK, BOOKE, { E } },
2953 { "mtmsrd", X(31,178), XRARB_MASK, PPC64, { RS } },
2955 { "stdux", X(31,181), X_MASK, PPC64, { RS, RAS, RB } },
2957 { "stwux", X(31,183), X_MASK, PPCCOM, { RS, RAS, RB } },
2958 { "stux", X(31,183), X_MASK, PWRCOM, { RS, RA, RB } },
2960 { "sliq", XRC(31,184,0), X_MASK, M601, { RA, RS, SH } },
2961 { "sliq.", XRC(31,184,1), X_MASK, M601, { RA, RS, SH } },
2963 { "stwuxe", X(31,191), X_MASK, BOOKE64, { RS, RAS, RB } },
2965 { "subfze", XO(31,200,0,0), XORB_MASK, PPCCOM, { RT, RA } },
2966 { "sfze", XO(31,200,0,0), XORB_MASK, PWRCOM, { RT, RA } },
2967 { "subfze.", XO(31,200,0,1), XORB_MASK, PPCCOM, { RT, RA } },
2968 { "sfze.", XO(31,200,0,1), XORB_MASK, PWRCOM, { RT, RA } },
2969 { "subfzeo", XO(31,200,1,0), XORB_MASK, PPCCOM, { RT, RA } },
2970 { "sfzeo", XO(31,200,1,0), XORB_MASK, PWRCOM, { RT, RA } },
2971 { "subfzeo.",XO(31,200,1,1), XORB_MASK, PPCCOM, { RT, RA } },
2972 { "sfzeo.", XO(31,200,1,1), XORB_MASK, PWRCOM, { RT, RA } },
2974 { "addze", XO(31,202,0,0), XORB_MASK, PPCCOM, { RT, RA } },
2975 { "aze", XO(31,202,0,0), XORB_MASK, PWRCOM, { RT, RA } },
2976 { "addze.", XO(31,202,0,1), XORB_MASK, PPCCOM, { RT, RA } },
2977 { "aze.", XO(31,202,0,1), XORB_MASK, PWRCOM, { RT, RA } },
2978 { "addzeo", XO(31,202,1,0), XORB_MASK, PPCCOM, { RT, RA } },
2979 { "azeo", XO(31,202,1,0), XORB_MASK, PWRCOM, { RT, RA } },
2980 { "addzeo.", XO(31,202,1,1), XORB_MASK, PPCCOM, { RT, RA } },
2981 { "azeo.", XO(31,202,1,1), XORB_MASK, PWRCOM, { RT, RA } },
2983 { "mtsr", X(31,210), XRB_MASK|(1<<20), COM32, { SR, RS } },
2985 { "stdcx.", XRC(31,214,1), X_MASK, PPC64, { RS, RA, RB } },
2987 { "stbx", X(31,215), X_MASK, COM, { RS, RA, RB } },
2989 { "sllq", XRC(31,216,0), X_MASK, M601, { RA, RS, RB } },
2990 { "sllq.", XRC(31,216,1), X_MASK, M601, { RA, RS, RB } },
2992 { "sleq", XRC(31,217,0), X_MASK, M601, { RA, RS, RB } },
2993 { "sleq.", XRC(31,217,1), X_MASK, M601, { RA, RS, RB } },
2995 { "stbxe", X(31,223), X_MASK, BOOKE64, { RS, RA, RB } },
2997 { "subfme", XO(31,232,0,0), XORB_MASK, PPCCOM, { RT, RA } },
2998 { "sfme", XO(31,232,0,0), XORB_MASK, PWRCOM, { RT, RA } },
2999 { "subfme.", XO(31,232,0,1), XORB_MASK, PPCCOM, { RT, RA } },
3000 { "sfme.", XO(31,232,0,1), XORB_MASK, PWRCOM, { RT, RA } },
3001 { "subfmeo", XO(31,232,1,0), XORB_MASK, PPCCOM, { RT, RA } },
3002 { "sfmeo", XO(31,232,1,0), XORB_MASK, PWRCOM, { RT, RA } },
3003 { "subfmeo.",XO(31,232,1,1), XORB_MASK, PPCCOM, { RT, RA } },
3004 { "sfmeo.", XO(31,232,1,1), XORB_MASK, PWRCOM, { RT, RA } },
3006 { "mulld", XO(31,233,0,0), XO_MASK, PPC64, { RT, RA, RB } },
3007 { "mulld.", XO(31,233,0,1), XO_MASK, PPC64, { RT, RA, RB } },
3008 { "mulldo", XO(31,233,1,0), XO_MASK, PPC64, { RT, RA, RB } },
3009 { "mulldo.", XO(31,233,1,1), XO_MASK, PPC64, { RT, RA, RB } },
3011 { "addme", XO(31,234,0,0), XORB_MASK, PPCCOM, { RT, RA } },
3012 { "ame", XO(31,234,0,0), XORB_MASK, PWRCOM, { RT, RA } },
3013 { "addme.", XO(31,234,0,1), XORB_MASK, PPCCOM, { RT, RA } },
3014 { "ame.", XO(31,234,0,1), XORB_MASK, PWRCOM, { RT, RA } },
3015 { "addmeo", XO(31,234,1,0), XORB_MASK, PPCCOM, { RT, RA } },
3016 { "ameo", XO(31,234,1,0), XORB_MASK, PWRCOM, { RT, RA } },
3017 { "addmeo.", XO(31,234,1,1), XORB_MASK, PPCCOM, { RT, RA } },
3018 { "ameo.", XO(31,234,1,1), XORB_MASK, PWRCOM, { RT, RA } },
3020 { "mullw", XO(31,235,0,0), XO_MASK, PPCCOM, { RT, RA, RB } },
3021 { "muls", XO(31,235,0,0), XO_MASK, PWRCOM, { RT, RA, RB } },
3022 { "mullw.", XO(31,235,0,1), XO_MASK, PPCCOM, { RT, RA, RB } },
3023 { "muls.", XO(31,235,0,1), XO_MASK, PWRCOM, { RT, RA, RB } },
3024 { "mullwo", XO(31,235,1,0), XO_MASK, PPCCOM, { RT, RA, RB } },
3025 { "mulso", XO(31,235,1,0), XO_MASK, PWRCOM, { RT, RA, RB } },
3026 { "mullwo.", XO(31,235,1,1), XO_MASK, PPCCOM, { RT, RA, RB } },
3027 { "mulso.", XO(31,235,1,1), XO_MASK, PWRCOM, { RT, RA, RB } },
3029 { "mtsrin", X(31,242), XRA_MASK, PPC32, { RS, RB } },
3030 { "mtsri", X(31,242), XRA_MASK, POWER32, { RS, RB } },
3032 { "dcbtst", X(31,246), XRT_MASK, PPC, { CT, RA, RB } },
3034 { "stbux", X(31,247), X_MASK, COM, { RS, RAS, RB } },
3036 { "slliq", XRC(31,248,0), X_MASK, M601, { RA, RS, SH } },
3037 { "slliq.", XRC(31,248,1), X_MASK, M601, { RA, RS, SH } },
3039 { "dcbtste", X(31,253), X_MASK, BOOKE64, { CT, RA, RB } },
3041 { "stbuxe", X(31,255), X_MASK, BOOKE64, { RS, RAS, RB } },
3043 { "mfdcrx", X(31,259), X_MASK, BOOKE, { RS, RA } },
3045 { "icbt", X(31,262), XRT_MASK, PPC403, { RA, RB } },
3047 { "doz", XO(31,264,0,0), XO_MASK, M601, { RT, RA, RB } },
3048 { "doz.", XO(31,264,0,1), XO_MASK, M601, { RT, RA, RB } },
3049 { "dozo", XO(31,264,1,0), XO_MASK, M601, { RT, RA, RB } },
3050 { "dozo.", XO(31,264,1,1), XO_MASK, M601, { RT, RA, RB } },
3052 { "add", XO(31,266,0,0), XO_MASK, PPCCOM, { RT, RA, RB } },
3053 { "cax", XO(31,266,0,0), XO_MASK, PWRCOM, { RT, RA, RB } },
3054 { "add.", XO(31,266,0,1), XO_MASK, PPCCOM, { RT, RA, RB } },
3055 { "cax.", XO(31,266,0,1), XO_MASK, PWRCOM, { RT, RA, RB } },
3056 { "addo", XO(31,266,1,0), XO_MASK, PPCCOM, { RT, RA, RB } },
3057 { "caxo", XO(31,266,1,0), XO_MASK, PWRCOM, { RT, RA, RB } },
3058 { "addo.", XO(31,266,1,1), XO_MASK, PPCCOM, { RT, RA, RB } },
3059 { "caxo.", XO(31,266,1,1), XO_MASK, PWRCOM, { RT, RA, RB } },
3061 { "mfapidi", X(31,275), X_MASK, BOOKE, { RT, RA } },
3063 { "lscbx", XRC(31,277,0), X_MASK, M601, { RT, RA, RB } },
3064 { "lscbx.", XRC(31,277,1), X_MASK, M601, { RT, RA, RB } },
3066 { "dcbt", X(31,278), XRT_MASK, PPC, { CT, RA, RB } },
3068 { "lhzx", X(31,279), X_MASK, COM, { RT, RA, RB } },
3070 { "eqv", XRC(31,284,0), X_MASK, COM, { RA, RS, RB } },
3071 { "eqv.", XRC(31,284,1), X_MASK, COM, { RA, RS, RB } },
3073 { "dcbte", X(31,286), X_MASK, BOOKE64, { CT, RA, RB } },
3075 { "lhzxe", X(31,287), X_MASK, BOOKE64, { RT, RA, RB } },
3077 { "tlbie", X(31,306), XRTLRA_MASK, PPC, { RB, L } },
3078 { "tlbi", X(31,306), XRT_MASK, POWER, { RA, RB } },
3080 { "eciwx", X(31,310), X_MASK, PPC, { RT, RA, RB } },
3082 { "lhzux", X(31,311), X_MASK, COM, { RT, RAL, RB } },
3084 { "xor", XRC(31,316,0), X_MASK, COM, { RA, RS, RB } },
3085 { "xor.", XRC(31,316,1), X_MASK, COM, { RA, RS, RB } },
3087 { "lhzuxe", X(31,319), X_MASK, BOOKE64, { RT, RAL, RB } },
3089 { "mfexisr", XSPR(31,323,64), XSPR_MASK, PPC403, { RT } },
3090 { "mfexier", XSPR(31,323,66), XSPR_MASK, PPC403, { RT } },
3091 { "mfbr0", XSPR(31,323,128), XSPR_MASK, PPC403, { RT } },
3092 { "mfbr1", XSPR(31,323,129), XSPR_MASK, PPC403, { RT } },
3093 { "mfbr2", XSPR(31,323,130), XSPR_MASK, PPC403, { RT } },
3094 { "mfbr3", XSPR(31,323,131), XSPR_MASK, PPC403, { RT } },
3095 { "mfbr4", XSPR(31,323,132), XSPR_MASK, PPC403, { RT } },
3096 { "mfbr5", XSPR(31,323,133), XSPR_MASK, PPC403, { RT } },
3097 { "mfbr6", XSPR(31,323,134), XSPR_MASK, PPC403, { RT } },
3098 { "mfbr7", XSPR(31,323,135), XSPR_MASK, PPC403, { RT } },
3099 { "mfbear", XSPR(31,323,144), XSPR_MASK, PPC403, { RT } },
3100 { "mfbesr", XSPR(31,323,145), XSPR_MASK, PPC403, { RT } },
3101 { "mfiocr", XSPR(31,323,160), XSPR_MASK, PPC403, { RT } },
3102 { "mfdmacr0", XSPR(31,323,192), XSPR_MASK, PPC403, { RT } },
3103 { "mfdmact0", XSPR(31,323,193), XSPR_MASK, PPC403, { RT } },
3104 { "mfdmada0", XSPR(31,323,194), XSPR_MASK, PPC403, { RT } },
3105 { "mfdmasa0", XSPR(31,323,195), XSPR_MASK, PPC403, { RT } },
3106 { "mfdmacc0", XSPR(31,323,196), XSPR_MASK, PPC403, { RT } },
3107 { "mfdmacr1", XSPR(31,323,200), XSPR_MASK, PPC403, { RT } },
3108 { "mfdmact1", XSPR(31,323,201), XSPR_MASK, PPC403, { RT } },
3109 { "mfdmada1", XSPR(31,323,202), XSPR_MASK, PPC403, { RT } },
3110 { "mfdmasa1", XSPR(31,323,203), XSPR_MASK, PPC403, { RT } },
3111 { "mfdmacc1", XSPR(31,323,204), XSPR_MASK, PPC403, { RT } },
3112 { "mfdmacr2", XSPR(31,323,208), XSPR_MASK, PPC403, { RT } },
3113 { "mfdmact2", XSPR(31,323,209), XSPR_MASK, PPC403, { RT } },
3114 { "mfdmada2", XSPR(31,323,210), XSPR_MASK, PPC403, { RT } },
3115 { "mfdmasa2", XSPR(31,323,211), XSPR_MASK, PPC403, { RT } },
3116 { "mfdmacc2", XSPR(31,323,212), XSPR_MASK, PPC403, { RT } },
3117 { "mfdmacr3", XSPR(31,323,216), XSPR_MASK, PPC403, { RT } },
3118 { "mfdmact3", XSPR(31,323,217), XSPR_MASK, PPC403, { RT } },
3119 { "mfdmada3", XSPR(31,323,218), XSPR_MASK, PPC403, { RT } },
3120 { "mfdmasa3", XSPR(31,323,219), XSPR_MASK, PPC403, { RT } },
3121 { "mfdmacc3", XSPR(31,323,220), XSPR_MASK, PPC403, { RT } },
3122 { "mfdmasr", XSPR(31,323,224), XSPR_MASK, PPC403, { RT } },
3123 { "mfdcr", X(31,323), X_MASK, PPC403, { RT, SPR } },
3124 { "mfdcr", X(31,323), X_MASK, BOOKE, { RT, SPR } },
3126 { "div", XO(31,331,0,0), XO_MASK, M601, { RT, RA, RB } },
3127 { "div.", XO(31,331,0,1), XO_MASK, M601, { RT, RA, RB } },
3128 { "divo", XO(31,331,1,0), XO_MASK, M601, { RT, RA, RB } },
3129 { "divo.", XO(31,331,1,1), XO_MASK, M601, { RT, RA, RB } },
3131 { "mfmq", XSPR(31,339,0), XSPR_MASK, M601, { RT } },
3132 { "mfxer", XSPR(31,339,1), XSPR_MASK, COM, { RT } },
3133 { "mfrtcu", XSPR(31,339,4), XSPR_MASK, COM, { RT } },
3134 { "mfrtcl", XSPR(31,339,5), XSPR_MASK, COM, { RT } },
3135 { "mfdec", XSPR(31,339,6), XSPR_MASK, MFDEC1, { RT } },
3136 { "mflr", XSPR(31,339,8), XSPR_MASK, COM, { RT } },
3137 { "mfctr", XSPR(31,339,9), XSPR_MASK, COM, { RT } },
3138 { "mftid", XSPR(31,339,17), XSPR_MASK, POWER, { RT } },
3139 { "mfdsisr", XSPR(31,339,18), XSPR_MASK, COM, { RT } },
3140 { "mfdar", XSPR(31,339,19), XSPR_MASK, COM, { RT } },
3141 { "mfdec", XSPR(31,339,22), XSPR_MASK, MFDEC2, { RT } },
3142 { "mfsdr0", XSPR(31,339,24), XSPR_MASK, POWER, { RT } },
3143 { "mfsdr1", XSPR(31,339,25), XSPR_MASK, COM, { RT } },
3144 { "mfsrr0", XSPR(31,339,26), XSPR_MASK, COM, { RT } },
3145 { "mfsrr1", XSPR(31,339,27), XSPR_MASK, COM, { RT } },
3146 { "mfcmpa", XSPR(31,339,144), XSPR_MASK, PPC860, { RT } },
3147 { "mfcmpb", XSPR(31,339,145), XSPR_MASK, PPC860, { RT } },
3148 { "mfcmpc", XSPR(31,339,146), XSPR_MASK, PPC860, { RT } },
3149 { "mfcmpd", XSPR(31,339,147), XSPR_MASK, PPC860, { RT } },
3150 { "mficr", XSPR(31,339,148), XSPR_MASK, PPC860, { RT } },
3151 { "mfder", XSPR(31,339,149), XSPR_MASK, PPC860, { RT } },
3152 { "mfcounta", XSPR(31,339,150), XSPR_MASK, PPC860, { RT } },
3153 { "mfcountb", XSPR(31,339,151), XSPR_MASK, PPC860, { RT } },
3154 { "mfcmpe", XSPR(31,339,152), XSPR_MASK, PPC860, { RT } },
3155 { "mfcmpf", XSPR(31,339,153), XSPR_MASK, PPC860, { RT } },
3156 { "mfcmpg", XSPR(31,339,154), XSPR_MASK, PPC860, { RT } },
3157 { "mfcmph", XSPR(31,339,155), XSPR_MASK, PPC860, { RT } },
3158 { "mflctrl1", XSPR(31,339,156), XSPR_MASK, PPC860, { RT } },
3159 { "mflctrl2", XSPR(31,339,157), XSPR_MASK, PPC860, { RT } },
3160 { "mfictrl", XSPR(31,339,158), XSPR_MASK, PPC860, { RT } },
3161 { "mfbar", XSPR(31,339,159), XSPR_MASK, PPC860, { RT } },
3162 { "mfvrsave", XSPR(31,339,256), XSPR_MASK, PPCVEC, { RT } },
3163 { "mfsprg4", XSPR(31,339,260), XSPR_MASK, PPC405, { RT } },
3164 { "mfsprg5", XSPR(31,339,261), XSPR_MASK, PPC405, { RT } },
3165 { "mfsprg6", XSPR(31,339,262), XSPR_MASK, PPC405, { RT } },
3166 { "mfsprg7", XSPR(31,339,263), XSPR_MASK, PPC405, { RT } },
3167 { "mfsprg", XSPR(31,339,272), XSPRG_MASK, PPC, { RT, SPRG } },
3168 { "mfsprg0", XSPR(31,339,272), XSPR_MASK, PPC, { RT } },
3169 { "mfsprg1", XSPR(31,339,273), XSPR_MASK, PPC, { RT } },
3170 { "mfsprg2", XSPR(31,339,274), XSPR_MASK, PPC, { RT } },
3171 { "mfsprg3", XSPR(31,339,275), XSPR_MASK, PPC, { RT } },
3172 { "mfasr", XSPR(31,339,280), XSPR_MASK, PPC64, { RT } },
3173 { "mfear", XSPR(31,339,282), XSPR_MASK, PPC, { RT } },
3174 { "mfpvr", XSPR(31,339,287), XSPR_MASK, PPC, { RT } },
3175 { "mfibatu", XSPR(31,339,528), XSPRBAT_MASK, PPC, { RT, SPRBAT } },
3176 { "mfibatl", XSPR(31,339,529), XSPRBAT_MASK, PPC, { RT, SPRBAT } },
3177 { "mfdbatu", XSPR(31,339,536), XSPRBAT_MASK, PPC, { RT, SPRBAT } },
3178 { "mfdbatl", XSPR(31,339,537), XSPRBAT_MASK, PPC, { RT, SPRBAT } },
3179 { "mfic_cst", XSPR(31,339,560), XSPR_MASK, PPC860, { RT } },
3180 { "mfic_adr", XSPR(31,339,561), XSPR_MASK, PPC860, { RT } },
3181 { "mfic_dat", XSPR(31,339,562), XSPR_MASK, PPC860, { RT } },
3182 { "mfdc_cst", XSPR(31,339,568), XSPR_MASK, PPC860, { RT } },
3183 { "mfdc_adr", XSPR(31,339,569), XSPR_MASK, PPC860, { RT } },
3184 { "mfdc_dat", XSPR(31,339,570), XSPR_MASK, PPC860, { RT } },
3185 { "mfdpdr", XSPR(31,339,630), XSPR_MASK, PPC860, { RT } },
3186 { "mfdpir", XSPR(31,339,631), XSPR_MASK, PPC860, { RT } },
3187 { "mfimmr", XSPR(31,339,638), XSPR_MASK, PPC860, { RT } },
3188 { "mfmi_ctr", XSPR(31,339,784), XSPR_MASK, PPC860, { RT } },
3189 { "mfmi_ap", XSPR(31,339,786), XSPR_MASK, PPC860, { RT } },
3190 { "mfmi_epn", XSPR(31,339,787), XSPR_MASK, PPC860, { RT } },
3191 { "mfmi_twc", XSPR(31,339,789), XSPR_MASK, PPC860, { RT } },
3192 { "mfmi_rpn", XSPR(31,339,790), XSPR_MASK, PPC860, { RT } },
3193 { "mfmd_ctr", XSPR(31,339,792), XSPR_MASK, PPC860, { RT } },
3194 { "mfm_casid",XSPR(31,339,793), XSPR_MASK, PPC860, { RT } },
3195 { "mfmd_ap", XSPR(31,339,794), XSPR_MASK, PPC860, { RT } },
3196 { "mfmd_epn", XSPR(31,339,795), XSPR_MASK, PPC860, { RT } },
3197 { "mfmd_twb", XSPR(31,339,796), XSPR_MASK, PPC860, { RT } },
3198 { "mfmd_twc", XSPR(31,339,797), XSPR_MASK, PPC860, { RT } },
3199 { "mfmd_rpn", XSPR(31,339,798), XSPR_MASK, PPC860, { RT } },
3200 { "mfm_tw", XSPR(31,339,799), XSPR_MASK, PPC860, { RT } },
3201 { "mfmi_dbcam",XSPR(31,339,816), XSPR_MASK, PPC860, { RT } },
3202 { "mfmi_dbram0",XSPR(31,339,817), XSPR_MASK, PPC860, { RT } },
3203 { "mfmi_dbram1",XSPR(31,339,818), XSPR_MASK, PPC860, { RT } },
3204 { "mfmd_dbcam", XSPR(31,339,824), XSPR_MASK, PPC860, { RT } },
3205 { "mfmd_dbram0",XSPR(31,339,825), XSPR_MASK, PPC860, { RT } },
3206 { "mfmd_dbram1",XSPR(31,339,826), XSPR_MASK, PPC860, { RT } },
3207 { "mfzpr", XSPR(31,339,944), XSPR_MASK, PPC403, { RT } },
3208 { "mfpid", XSPR(31,339,945), XSPR_MASK, PPC403, { RT } },
3209 { "mfccr0", XSPR(31,339,947), XSPR_MASK, PPC405, { RT } },
3210 { "mficdbdr", XSPR(31,339,979), XSPR_MASK, PPC403, { RT } },
3211 { "mfummcr0", XSPR(31,339,936), XSPR_MASK, PPC750, { RT } },
3212 { "mfupmc1", XSPR(31,339,937), XSPR_MASK, PPC750, { RT } },
3213 { "mfupmc2", XSPR(31,339,938), XSPR_MASK, PPC750, { RT } },
3214 { "mfusia", XSPR(31,339,939), XSPR_MASK, PPC750, { RT } },
3215 { "mfummcr1", XSPR(31,339,940), XSPR_MASK, PPC750, { RT } },
3216 { "mfupmc3", XSPR(31,339,941), XSPR_MASK, PPC750, { RT } },
3217 { "mfupmc4", XSPR(31,339,942), XSPR_MASK, PPC750, { RT } },
3218 { "mfiac3", XSPR(31,339,948), XSPR_MASK, PPC405, { RT } },
3219 { "mfiac4", XSPR(31,339,949), XSPR_MASK, PPC405, { RT } },
3220 { "mfdvc1", XSPR(31,339,950), XSPR_MASK, PPC405, { RT } },
3221 { "mfdvc2", XSPR(31,339,951), XSPR_MASK, PPC405, { RT } },
3222 { "mfmmcr0", XSPR(31,339,952), XSPR_MASK, PPC750, { RT } },
3223 { "mfpmc1", XSPR(31,339,953), XSPR_MASK, PPC750, { RT } },
3224 { "mfsgr", XSPR(31,339,953), XSPR_MASK, PPC403, { RT } },
3225 { "mfpmc2", XSPR(31,339,954), XSPR_MASK, PPC750, { RT } },
3226 { "mfdcwr", XSPR(31,339,954), XSPR_MASK, PPC403, { RT } },
3227 { "mfsia", XSPR(31,339,955), XSPR_MASK, PPC750, { RT } },
3228 { "mfsler", XSPR(31,339,955), XSPR_MASK, PPC405, { RT } },
3229 { "mfmmcr1", XSPR(31,339,956), XSPR_MASK, PPC750, { RT } },
3230 { "mfsu0r", XSPR(31,339,956), XSPR_MASK, PPC405, { RT } },
3231 { "mfpmc3", XSPR(31,339,957), XSPR_MASK, PPC750, { RT } },
3232 { "mfdbcr1", XSPR(31,339,957), XSPR_MASK, PPC405, { RT } },
3233 { "mfpmc4", XSPR(31,339,958), XSPR_MASK, PPC750, { RT } },
3234 { "mfesr", XSPR(31,339,980), XSPR_MASK, PPC403, { RT } },
3235 { "mfdear", XSPR(31,339,981), XSPR_MASK, PPC403, { RT } },
3236 { "mfevpr", XSPR(31,339,982), XSPR_MASK, PPC403, { RT } },
3237 { "mfcdbcr", XSPR(31,339,983), XSPR_MASK, PPC403, { RT } },
3238 { "mftsr", XSPR(31,339,984), XSPR_MASK, PPC403, { RT } },
3239 { "mftcr", XSPR(31,339,986), XSPR_MASK, PPC403, { RT } },
3240 { "mfpit", XSPR(31,339,987), XSPR_MASK, PPC403, { RT } },
3241 { "mftbhi", XSPR(31,339,988), XSPR_MASK, PPC403, { RT } },
3242 { "mftblo", XSPR(31,339,989), XSPR_MASK, PPC403, { RT } },
3243 { "mfsrr2", XSPR(31,339,990), XSPR_MASK, PPC403, { RT } },
3244 { "mfsrr3", XSPR(31,339,991), XSPR_MASK, PPC403, { RT } },
3245 { "mfdbsr", XSPR(31,339,1008), XSPR_MASK, PPC403, { RT } },
3246 { "mfdbcr0", XSPR(31,339,1010), XSPR_MASK, PPC405, { RT } },
3247 { "mfiac1", XSPR(31,339,1012), XSPR_MASK, PPC403, { RT } },
3248 { "mfiac2", XSPR(31,339,1013), XSPR_MASK, PPC403, { RT } },
3249 { "mfdac1", XSPR(31,339,1014), XSPR_MASK, PPC403, { RT } },
3250 { "mfdac2", XSPR(31,339,1015), XSPR_MASK, PPC403, { RT } },
3251 { "mfdccr", XSPR(31,339,1018), XSPR_MASK, PPC403, { RT } },
3252 { "mficcr", XSPR(31,339,1019), XSPR_MASK, PPC403, { RT } },
3253 { "mfpbl1", XSPR(31,339,1020), XSPR_MASK, PPC403, { RT } },
3254 { "mfpbu1", XSPR(31,339,1021), XSPR_MASK, PPC403, { RT } },
3255 { "mfpbl2", XSPR(31,339,1022), XSPR_MASK, PPC403, { RT } },
3256 { "mfpbu2", XSPR(31,339,1023), XSPR_MASK, PPC403, { RT } },
3257 { "mfl2cr", XSPR(31,339,1017), XSPR_MASK, PPC750, { RT } },
3258 { "mfictc", XSPR(31,339,1019), XSPR_MASK, PPC750, { RT } },
3259 { "mfthrm1", XSPR(31,339,1020), XSPR_MASK, PPC750, { RT } },
3260 { "mfthrm2", XSPR(31,339,1021), XSPR_MASK, PPC750, { RT } },
3261 { "mfthrm3", XSPR(31,339,1022), XSPR_MASK, PPC750, { RT } },
3262 { "mfspr", X(31,339), X_MASK, COM, { RT, SPR } },
3264 { "lwax", X(31,341), X_MASK, PPC64, { RT, RA, RB } },
3266 { "dst", XDSS(31,342,0), XDSS_MASK, PPCVEC, { RA, RB, STRM } },
3267 { "dstt", XDSS(31,342,1), XDSS_MASK, PPCVEC, { RA, RB, STRM } },
3269 { "lhax", X(31,343), X_MASK, COM, { RT, RA, RB } },
3271 { "lhaxe", X(31,351), X_MASK, BOOKE64, { RT, RA, RB } },
3273 { "dstst", XDSS(31,374,0), XDSS_MASK, PPCVEC, { RA, RB, STRM } },
3274 { "dststt", XDSS(31,374,1), XDSS_MASK, PPCVEC, { RA, RB, STRM } },
3276 { "dccci", X(31,454), XRT_MASK, PPC403, { RA, RB } },
3278 { "abs", XO(31,360,0,0), XORB_MASK, M601, { RT, RA } },
3279 { "abs.", XO(31,360,0,1), XORB_MASK, M601, { RT, RA } },
3280 { "abso", XO(31,360,1,0), XORB_MASK, M601, { RT, RA } },
3281 { "abso.", XO(31,360,1,1), XORB_MASK, M601, { RT, RA } },
3283 { "divs", XO(31,363,0,0), XO_MASK, M601, { RT, RA, RB } },
3284 { "divs.", XO(31,363,0,1), XO_MASK, M601, { RT, RA, RB } },
3285 { "divso", XO(31,363,1,0), XO_MASK, M601, { RT, RA, RB } },
3286 { "divso.", XO(31,363,1,1), XO_MASK, M601, { RT, RA, RB } },
3288 { "tlbia", X(31,370), 0xffffffff, PPC, { 0 } },
3290 { "mftbl", XSPR(31,371,268), XSPR_MASK, PPC, { RT } },
3291 { "mftbu", XSPR(31,371,269), XSPR_MASK, PPC, { RT } },
3292 { "mftb", X(31,371), X_MASK, PPC, { RT, TBR } },
3294 { "lwaux", X(31,373), X_MASK, PPC64, { RT, RAL, RB } },
3296 { "lhaux", X(31,375), X_MASK, COM, { RT, RAL, RB } },
3298 { "lhauxe", X(31,383), X_MASK, BOOKE64, { RT, RAL, RB } },
3300 { "mtdcrx", X(31,387), X_MASK, BOOKE, { RA, RS } },
3302 { "subfe64", XO(31,392,0,0), XO_MASK, BOOKE64, { RT, RA, RB } },
3303 { "subfe64o",XO(31,392,1,0), XO_MASK, BOOKE64, { RT, RA, RB } },
3305 { "adde64", XO(31,394,0,0), XO_MASK, BOOKE64, { RT, RA, RB } },
3306 { "adde64o", XO(31,394,1,0), XO_MASK, BOOKE64, { RT, RA, RB } },
3308 { "slbmte", X(31,402), XRA_MASK, PPC64, { RS, RB } },
3310 { "sthx", X(31,407), X_MASK, COM, { RS, RA, RB } },
3312 { "lfqx", X(31,791), X_MASK, POWER2, { FRT, RA, RB } },
3314 { "lfqux", X(31,823), X_MASK, POWER2, { FRT, RA, RB } },
3316 { "stfqx", X(31,919), X_MASK, POWER2, { FRS, RA, RB } },
3318 { "stfqux", X(31,951), X_MASK, POWER2, { FRS, RA, RB } },
3320 { "orc", XRC(31,412,0), X_MASK, COM, { RA, RS, RB } },
3321 { "orc.", XRC(31,412,1), X_MASK, COM, { RA, RS, RB } },
3323 { "sradi", XS(31,413,0), XS_MASK, PPC64, { RA, RS, SH6 } },
3324 { "sradi.", XS(31,413,1), XS_MASK, PPC64, { RA, RS, SH6 } },
3326 { "sthxe", X(31,415), X_MASK, BOOKE64, { RS, RA, RB } },
3328 { "slbie", X(31,434), XRTRA_MASK, PPC64, { RB } },
3330 { "ecowx", X(31,438), X_MASK, PPC, { RT, RA, RB } },
3332 { "sthux", X(31,439), X_MASK, COM, { RS, RAS, RB } },
3334 { "sthuxe", X(31,447), X_MASK, BOOKE64, { RS, RAS, RB } },
3336 { "mr", XRC(31,444,0), X_MASK, COM, { RA, RS, RBS } },
3337 { "or", XRC(31,444,0), X_MASK, COM, { RA, RS, RB } },
3338 { "mr.", XRC(31,444,1), X_MASK, COM, { RA, RS, RBS } },
3339 { "or.", XRC(31,444,1), X_MASK, COM, { RA, RS, RB } },
3341 { "mtexisr", XSPR(31,451,64), XSPR_MASK, PPC403, { RT } },
3342 { "mtexier", XSPR(31,451,66), XSPR_MASK, PPC403, { RT } },
3343 { "mtbr0", XSPR(31,451,128), XSPR_MASK, PPC403, { RT } },
3344 { "mtbr1", XSPR(31,451,129), XSPR_MASK, PPC403, { RT } },
3345 { "mtbr2", XSPR(31,451,130), XSPR_MASK, PPC403, { RT } },
3346 { "mtbr3", XSPR(31,451,131), XSPR_MASK, PPC403, { RT } },
3347 { "mtbr4", XSPR(31,451,132), XSPR_MASK, PPC403, { RT } },
3348 { "mtbr5", XSPR(31,451,133), XSPR_MASK, PPC403, { RT } },
3349 { "mtbr6", XSPR(31,451,134), XSPR_MASK, PPC403, { RT } },
3350 { "mtbr7", XSPR(31,451,135), XSPR_MASK, PPC403, { RT } },
3351 { "mtbear", XSPR(31,451,144), XSPR_MASK, PPC403, { RT } },
3352 { "mtbesr", XSPR(31,451,145), XSPR_MASK, PPC403, { RT } },
3353 { "mtiocr", XSPR(31,451,160), XSPR_MASK, PPC403, { RT } },
3354 { "mtdmacr0", XSPR(31,451,192), XSPR_MASK, PPC403, { RT } },
3355 { "mtdmact0", XSPR(31,451,193), XSPR_MASK, PPC403, { RT } },
3356 { "mtdmada0", XSPR(31,451,194), XSPR_MASK, PPC403, { RT } },
3357 { "mtdmasa0", XSPR(31,451,195), XSPR_MASK, PPC403, { RT } },
3358 { "mtdmacc0", XSPR(31,451,196), XSPR_MASK, PPC403, { RT } },
3359 { "mtdmacr1", XSPR(31,451,200), XSPR_MASK, PPC403, { RT } },
3360 { "mtdmact1", XSPR(31,451,201), XSPR_MASK, PPC403, { RT } },
3361 { "mtdmada1", XSPR(31,451,202), XSPR_MASK, PPC403, { RT } },
3362 { "mtdmasa1", XSPR(31,451,203), XSPR_MASK, PPC403, { RT } },
3363 { "mtdmacc1", XSPR(31,451,204), XSPR_MASK, PPC403, { RT } },
3364 { "mtdmacr2", XSPR(31,451,208), XSPR_MASK, PPC403, { RT } },
3365 { "mtdmact2", XSPR(31,451,209), XSPR_MASK, PPC403, { RT } },
3366 { "mtdmada2", XSPR(31,451,210), XSPR_MASK, PPC403, { RT } },
3367 { "mtdmasa2", XSPR(31,451,211), XSPR_MASK, PPC403, { RT } },
3368 { "mtdmacc2", XSPR(31,451,212), XSPR_MASK, PPC403, { RT } },
3369 { "mtdmacr3", XSPR(31,451,216), XSPR_MASK, PPC403, { RT } },
3370 { "mtdmact3", XSPR(31,451,217), XSPR_MASK, PPC403, { RT } },
3371 { "mtdmada3", XSPR(31,451,218), XSPR_MASK, PPC403, { RT } },
3372 { "mtdmasa3", XSPR(31,451,219), XSPR_MASK, PPC403, { RT } },
3373 { "mtdmacc3", XSPR(31,451,220), XSPR_MASK, PPC403, { RT } },
3374 { "mtdmasr", XSPR(31,451,224), XSPR_MASK, PPC403, { RT } },
3375 { "mtdcr", X(31,451), X_MASK, PPC403, { SPR, RS } },
3376 { "mtdcr", X(31,451), X_MASK, BOOKE, { SPR, RS } },
3378 { "subfze64",XO(31,456,0,0), XORB_MASK, BOOKE64, { RT, RA } },
3379 { "subfze64o",XO(31,456,1,0), XORB_MASK, BOOKE64, { RT, RA } },
3381 { "divdu", XO(31,457,0,0), XO_MASK, PPC64, { RT, RA, RB } },
3382 { "divdu.", XO(31,457,0,1), XO_MASK, PPC64, { RT, RA, RB } },
3383 { "divduo", XO(31,457,1,0), XO_MASK, PPC64, { RT, RA, RB } },
3384 { "divduo.", XO(31,457,1,1), XO_MASK, PPC64, { RT, RA, RB } },
3386 { "addze64", XO(31,458,0,0), XORB_MASK, BOOKE64, { RT, RA } },
3387 { "addze64o",XO(31,458,1,0), XORB_MASK, BOOKE64, { RT, RA } },
3389 { "divwu", XO(31,459,0,0), XO_MASK, PPC, { RT, RA, RB } },
3390 { "divwu.", XO(31,459,0,1), XO_MASK, PPC, { RT, RA, RB } },
3391 { "divwuo", XO(31,459,1,0), XO_MASK, PPC, { RT, RA, RB } },
3392 { "divwuo.", XO(31,459,1,1), XO_MASK, PPC, { RT, RA, RB } },
3394 { "mtmq", XSPR(31,467,0), XSPR_MASK, M601, { RS } },
3395 { "mtxer", XSPR(31,467,1), XSPR_MASK, COM, { RS } },
3396 { "mtlr", XSPR(31,467,8), XSPR_MASK, COM, { RS } },
3397 { "mtctr", XSPR(31,467,9), XSPR_MASK, COM, { RS } },
3398 { "mttid", XSPR(31,467,17), XSPR_MASK, POWER, { RS } },
3399 { "mtdsisr", XSPR(31,467,18), XSPR_MASK, COM, { RS } },
3400 { "mtdar", XSPR(31,467,19), XSPR_MASK, COM, { RS } },
3401 { "mtrtcu", XSPR(31,467,20), XSPR_MASK, COM, { RS } },
3402 { "mtrtcl", XSPR(31,467,21), XSPR_MASK, COM, { RS } },
3403 { "mtdec", XSPR(31,467,22), XSPR_MASK, COM, { RS } },
3404 { "mtsdr0", XSPR(31,467,24), XSPR_MASK, POWER, { RS } },
3405 { "mtsdr1", XSPR(31,467,25), XSPR_MASK, COM, { RS } },
3406 { "mtsrr0", XSPR(31,467,26), XSPR_MASK, COM, { RS } },
3407 { "mtsrr1", XSPR(31,467,27), XSPR_MASK, COM, { RS } },
3408 { "mtcmpa", XSPR(31,467,144), XSPR_MASK, PPC860, { RT } },
3409 { "mtcmpb", XSPR(31,467,145), XSPR_MASK, PPC860, { RT } },
3410 { "mtcmpc", XSPR(31,467,146), XSPR_MASK, PPC860, { RT } },
3411 { "mtcmpd", XSPR(31,467,147), XSPR_MASK, PPC860, { RT } },
3412 { "mticr", XSPR(31,467,148), XSPR_MASK, PPC860, { RT } },
3413 { "mtder", XSPR(31,467,149), XSPR_MASK, PPC860, { RT } },
3414 { "mtcounta", XSPR(31,467,150), XSPR_MASK, PPC860, { RT } },
3415 { "mtcountb", XSPR(31,467,151), XSPR_MASK, PPC860, { RT } },
3416 { "mtcmpe", XSPR(31,467,152), XSPR_MASK, PPC860, { RT } },
3417 { "mtcmpf", XSPR(31,467,153), XSPR_MASK, PPC860, { RT } },
3418 { "mtcmpg", XSPR(31,467,154), XSPR_MASK, PPC860, { RT } },
3419 { "mtcmph", XSPR(31,467,155), XSPR_MASK, PPC860, { RT } },
3420 { "mtlctrl1", XSPR(31,467,156), XSPR_MASK, PPC860, { RT } },
3421 { "mtlctrl2", XSPR(31,467,157), XSPR_MASK, PPC860, { RT } },
3422 { "mtictrl", XSPR(31,467,158), XSPR_MASK, PPC860, { RT } },
3423 { "mtbar", XSPR(31,467,159), XSPR_MASK, PPC860, { RT } },
3424 { "mtvrsave",XSPR(31,467,256), XSPR_MASK, PPCVEC, { RT } },
3425 { "mtsprg", XSPR(31,467,272), XSPRG_MASK, PPC, { SPRG, RS } },
3426 { "mtsprg0", XSPR(31,467,272), XSPR_MASK, PPC, { RT } },
3427 { "mtsprg1", XSPR(31,467,273), XSPR_MASK, PPC, { RT } },
3428 { "mtsprg2", XSPR(31,467,274), XSPR_MASK, PPC, { RT } },
3429 { "mtsprg3", XSPR(31,467,275), XSPR_MASK, PPC, { RT } },
3430 { "mtsprg4", XSPR(31,467,276), XSPR_MASK, PPC405, { RT } },
3431 { "mtsprg5", XSPR(31,467,277), XSPR_MASK, PPC405, { RT } },
3432 { "mtsprg6", XSPR(31,467,278), XSPR_MASK, PPC405, { RT } },
3433 { "mtsprg7", XSPR(31,467,279), XSPR_MASK, PPC405, { RT } },
3434 { "mtasr", XSPR(31,467,280), XSPR_MASK, PPC64, { RS } },
3435 { "mtear", XSPR(31,467,282), XSPR_MASK, PPC, { RS } },
3436 { "mttbl", XSPR(31,467,284), XSPR_MASK, PPC, { RS } },
3437 { "mttbu", XSPR(31,467,285), XSPR_MASK, PPC, { RS } },
3438 { "mtibatu", XSPR(31,467,528), XSPRBAT_MASK, PPC, { SPRBAT, RS } },
3439 { "mtibatl", XSPR(31,467,529), XSPRBAT_MASK, PPC, { SPRBAT, RS } },
3440 { "mtdbatu", XSPR(31,467,536), XSPRBAT_MASK, PPC, { SPRBAT, RS } },
3441 { "mtdbatl", XSPR(31,467,537), XSPRBAT_MASK, PPC, { SPRBAT, RS } },
3442 { "mtzpr", XSPR(31,467,944), XSPR_MASK, PPC403, { RT } },
3443 { "mtpid", XSPR(31,467,945), XSPR_MASK, PPC403, { RT } },
3444 { "mtccr0", XSPR(31,467,947), XSPR_MASK, PPC405, { RT } },
3445 { "mtiac3", XSPR(31,467,948), XSPR_MASK, PPC405, { RT } },
3446 { "mtiac4", XSPR(31,467,949), XSPR_MASK, PPC405, { RT } },
3447 { "mtdvc1", XSPR(31,467,950), XSPR_MASK, PPC405, { RT } },
3448 { "mtdvc2", XSPR(31,467,951), XSPR_MASK, PPC405, { RT } },
3449 { "mtsgr", XSPR(31,467,953), XSPR_MASK, PPC403, { RT } },
3450 { "mtdcwr", XSPR(31,467,954), XSPR_MASK, PPC403, { RT } },
3451 { "mtsler", XSPR(31,467,955), XSPR_MASK, PPC405, { RT } },
3452 { "mtsu0r", XSPR(31,467,956), XSPR_MASK, PPC405, { RT } },
3453 { "mtdbcr1", XSPR(31,467,957), XSPR_MASK, PPC405, { RT } },
3454 { "mticdbdr",XSPR(31,467,979), XSPR_MASK, PPC403, { RT } },
3455 { "mtesr", XSPR(31,467,980), XSPR_MASK, PPC403, { RT } },
3456 { "mtdear", XSPR(31,467,981), XSPR_MASK, PPC403, { RT } },
3457 { "mtevpr", XSPR(31,467,982), XSPR_MASK, PPC403, { RT } },
3458 { "mtcdbcr", XSPR(31,467,983), XSPR_MASK, PPC403, { RT } },
3459 { "mttsr", XSPR(31,467,984), XSPR_MASK, PPC403, { RT } },
3460 { "mttcr", XSPR(31,467,986), XSPR_MASK, PPC403, { RT } },
3461 { "mtpit", XSPR(31,467,987), XSPR_MASK, PPC403, { RT } },
3462 { "mttbhi", XSPR(31,467,988), XSPR_MASK, PPC403, { RT } },
3463 { "mttblo", XSPR(31,467,989), XSPR_MASK, PPC403, { RT } },
3464 { "mtsrr2", XSPR(31,467,990), XSPR_MASK, PPC403, { RT } },
3465 { "mtsrr3", XSPR(31,467,991), XSPR_MASK, PPC403, { RT } },
3466 { "mtdbsr", XSPR(31,467,1008), XSPR_MASK, PPC403, { RT } },
3467 { "mtdbcr0", XSPR(31,467,1010), XSPR_MASK, PPC405, { RT } },
3468 { "mtiac1", XSPR(31,467,1012), XSPR_MASK, PPC403, { RT } },
3469 { "mtiac2", XSPR(31,467,1013), XSPR_MASK, PPC403, { RT } },
3470 { "mtdac1", XSPR(31,467,1014), XSPR_MASK, PPC403, { RT } },
3471 { "mtdac2", XSPR(31,467,1015), XSPR_MASK, PPC403, { RT } },
3472 { "mtdccr", XSPR(31,467,1018), XSPR_MASK, PPC403, { RT } },
3473 { "mticcr", XSPR(31,467,1019), XSPR_MASK, PPC403, { RT } },
3474 { "mtpbl1", XSPR(31,467,1020), XSPR_MASK, PPC403, { RT } },
3475 { "mtpbu1", XSPR(31,467,1021), XSPR_MASK, PPC403, { RT } },
3476 { "mtpbl2", XSPR(31,467,1022), XSPR_MASK, PPC403, { RT } },
3477 { "mtpbu2", XSPR(31,467,1023), XSPR_MASK, PPC403, { RT } },
3478 { "mtummcr0", XSPR(31,467,936), XSPR_MASK, PPC750, { RT } },
3479 { "mtupmc1", XSPR(31,467,937), XSPR_MASK, PPC750, { RT } },
3480 { "mtupmc2", XSPR(31,467,938), XSPR_MASK, PPC750, { RT } },
3481 { "mtusia", XSPR(31,467,939), XSPR_MASK, PPC750, { RT } },
3482 { "mtummcr1", XSPR(31,467,940), XSPR_MASK, PPC750, { RT } },
3483 { "mtupmc3", XSPR(31,467,941), XSPR_MASK, PPC750, { RT } },
3484 { "mtupmc4", XSPR(31,467,942), XSPR_MASK, PPC750, { RT } },
3485 { "mtmmcr0", XSPR(31,467,952), XSPR_MASK, PPC750, { RT } },
3486 { "mtpmc1", XSPR(31,467,953), XSPR_MASK, PPC750, { RT } },
3487 { "mtpmc2", XSPR(31,467,954), XSPR_MASK, PPC750, { RT } },
3488 { "mtsia", XSPR(31,467,955), XSPR_MASK, PPC750, { RT } },
3489 { "mtmmcr1", XSPR(31,467,956), XSPR_MASK, PPC750, { RT } },
3490 { "mtpmc3", XSPR(31,467,957), XSPR_MASK, PPC750, { RT } },
3491 { "mtpmc4", XSPR(31,467,958), XSPR_MASK, PPC750, { RT } },
3492 { "mtl2cr", XSPR(31,467,1017), XSPR_MASK, PPC750, { RT } },
3493 { "mtictc", XSPR(31,467,1019), XSPR_MASK, PPC750, { RT } },
3494 { "mtthrm1", XSPR(31,467,1020), XSPR_MASK, PPC750, { RT } },
3495 { "mtthrm2", XSPR(31,467,1021), XSPR_MASK, PPC750, { RT } },
3496 { "mtthrm3", XSPR(31,467,1022), XSPR_MASK, PPC750, { RT } },
3497 { "mtspr", X(31,467), X_MASK, COM, { SPR, RS } },
3499 { "dcbi", X(31,470), XRT_MASK, PPC, { RA, RB } },
3501 { "nand", XRC(31,476,0), X_MASK, COM, { RA, RS, RB } },
3502 { "nand.", XRC(31,476,1), X_MASK, COM, { RA, RS, RB } },
3504 { "dcbie", X(31,478), XRT_MASK, BOOKE64, { RA, RB } },
3506 { "dcread", X(31,486), X_MASK, PPC403, { RT, RA, RB }},
3508 { "nabs", XO(31,488,0,0), XORB_MASK, M601, { RT, RA } },
3509 { "subfme64",XO(31,488,0,0), XORB_MASK, BOOKE64, { RT, RA } },
3510 { "nabs.", XO(31,488,0,1), XORB_MASK, M601, { RT, RA } },
3511 { "nabso", XO(31,488,1,0), XORB_MASK, M601, { RT, RA } },
3512 { "subfme64o",XO(31,488,1,0), XORB_MASK, BOOKE64, { RT, RA } },
3513 { "nabso.", XO(31,488,1,1), XORB_MASK, M601, { RT, RA } },
3515 { "divd", XO(31,489,0,0), XO_MASK, PPC64, { RT, RA, RB } },
3516 { "divd.", XO(31,489,0,1), XO_MASK, PPC64, { RT, RA, RB } },
3517 { "divdo", XO(31,489,1,0), XO_MASK, PPC64, { RT, RA, RB } },
3518 { "divdo.", XO(31,489,1,1), XO_MASK, PPC64, { RT, RA, RB } },
3520 { "addme64", XO(31,490,0,0), XORB_MASK, BOOKE64, { RT, RA } },
3521 { "addme64o",XO(31,490,1,0), XORB_MASK, BOOKE64, { RT, RA } },
3523 { "divw", XO(31,491,0,0), XO_MASK, PPC, { RT, RA, RB } },
3524 { "divw.", XO(31,491,0,1), XO_MASK, PPC, { RT, RA, RB } },
3525 { "divwo", XO(31,491,1,0), XO_MASK, PPC, { RT, RA, RB } },
3526 { "divwo.", XO(31,491,1,1), XO_MASK, PPC, { RT, RA, RB } },
3528 { "slbia", X(31,498), 0xffffffff, PPC64, { 0 } },
3530 { "cli", X(31,502), XRB_MASK, POWER, { RT, RA } },
3532 { "stdcxe.", XRC(31,511,1), X_MASK, BOOKE64, { RS, RA, RB } },
3534 { "mcrxr", X(31,512), XRARB_MASK|(3<<21), COM, { BF } },
3536 { "mcrxr64", X(31,544), XRARB_MASK|(3<<21), BOOKE, { BF } },
3538 { "clcs", X(31,531), XRB_MASK, M601, { RT, RA } },
3540 { "lswx", X(31,533), X_MASK, PPCCOM, { RT, RA, RB } },
3541 { "lsx", X(31,533), X_MASK, PWRCOM, { RT, RA, RB } },
3543 { "lwbrx", X(31,534), X_MASK, PPCCOM, { RT, RA, RB } },
3544 { "lbrx", X(31,534), X_MASK, PWRCOM, { RT, RA, RB } },
3546 { "lfsx", X(31,535), X_MASK, COM, { FRT, RA, RB } },
3548 { "srw", XRC(31,536,0), X_MASK, PPCCOM, { RA, RS, RB } },
3549 { "sr", XRC(31,536,0), X_MASK, PWRCOM, { RA, RS, RB } },
3550 { "srw.", XRC(31,536,1), X_MASK, PPCCOM, { RA, RS, RB } },
3551 { "sr.", XRC(31,536,1), X_MASK, PWRCOM, { RA, RS, RB } },
3553 { "rrib", XRC(31,537,0), X_MASK, M601, { RA, RS, RB } },
3554 { "rrib.", XRC(31,537,1), X_MASK, M601, { RA, RS, RB } },
3556 { "srd", XRC(31,539,0), X_MASK, PPC64, { RA, RS, RB } },
3557 { "srd.", XRC(31,539,1), X_MASK, PPC64, { RA, RS, RB } },
3559 { "maskir", XRC(31,541,0), X_MASK, M601, { RA, RS, RB } },
3560 { "maskir.", XRC(31,541,1), X_MASK, M601, { RA, RS, RB } },
3562 { "lwbrxe", X(31,542), X_MASK, BOOKE64, { RT, RA, RB } },
3564 { "lfsxe", X(31,543), X_MASK, BOOKE64, { FRT, RA, RB } },
3566 { "tlbsync", X(31,566), 0xffffffff, PPC, { 0 } },
3568 { "lfsux", X(31,567), X_MASK, COM, { FRT, RAS, RB } },
3570 { "lfsuxe", X(31,575), X_MASK, BOOKE64, { FRT, RAS, RB } },
3572 { "mfsr", X(31,595), XRB_MASK|(1<<20), COM32, { RT, SR } },
3574 { "lswi", X(31,597), X_MASK, PPCCOM, { RT, RA, NB } },
3575 { "lsi", X(31,597), X_MASK, PWRCOM, { RT, RA, NB } },
3577 { "lwsync", XSYNC(31,598,1), 0xffffffff, PPCONLY, { 0 } },
3578 { "ptesync", XSYNC(31,598,2), 0xffffffff, PPC64, { 0 } },
3579 { "sync", X(31,598), XSYNC_MASK, PPCCOM, { LS } },
3580 { "dcs", X(31,598), 0xffffffff, PWRCOM, { 0 } },
3581 { "msync", X(31,598), 0xf80007fe, BOOKE, { 0 } },
3583 { "lfdx", X(31,599), X_MASK, COM, { FRT, RA, RB } },
3585 { "lfdxe", X(31,607), X_MASK, BOOKE64, { FRT, RA, RB } },
3587 { "mfsri", X(31,627), X_MASK, PWRCOM, { RT, RA, RB } },
3589 { "dclst", X(31,630), XRB_MASK, PWRCOM, { RS, RA } },
3591 { "lfdux", X(31,631), X_MASK, COM, { FRT, RAS, RB } },
3593 { "lfduxe", X(31,639), X_MASK, BOOKE64, { FRT, RAS, RB } },
3595 { "mfsrin", X(31,659), XRA_MASK, PPC32, { RT, RB } },
3597 { "stswx", X(31,661), X_MASK, PPCCOM, { RS, RA, RB } },
3598 { "stsx", X(31,661), X_MASK, PWRCOM, { RS, RA, RB } },
3600 { "stwbrx", X(31,662), X_MASK, PPCCOM, { RS, RA, RB } },
3601 { "stbrx", X(31,662), X_MASK, PWRCOM, { RS, RA, RB } },
3603 { "stfsx", X(31,663), X_MASK, COM, { FRS, RA, RB } },
3605 { "srq", XRC(31,664,0), X_MASK, M601, { RA, RS, RB } },
3606 { "srq.", XRC(31,664,1), X_MASK, M601, { RA, RS, RB } },
3608 { "sre", XRC(31,665,0), X_MASK, M601, { RA, RS, RB } },
3609 { "sre.", XRC(31,665,1), X_MASK, M601, { RA, RS, RB } },
3611 { "stwbrxe", X(31,670), X_MASK, BOOKE64, { RS, RA, RB } },
3613 { "stfsxe", X(31,671), X_MASK, BOOKE64, { FRS, RA, RB } },
3615 { "stfsux", X(31,695), X_MASK, COM, { FRS, RAS, RB } },
3617 { "sriq", XRC(31,696,0), X_MASK, M601, { RA, RS, SH } },
3618 { "sriq.", XRC(31,696,1), X_MASK, M601, { RA, RS, SH } },
3620 { "stfsuxe", X(31,703), X_MASK, BOOKE64, { FRS, RAS, RB } },
3622 { "stswi", X(31,725), X_MASK, PPCCOM, { RS, RA, NB } },
3623 { "stsi", X(31,725), X_MASK, PWRCOM, { RS, RA, NB } },
3625 { "stfdx", X(31,727), X_MASK, COM, { FRS, RA, RB } },
3627 { "srlq", XRC(31,728,0), X_MASK, M601, { RA, RS, RB } },
3628 { "srlq.", XRC(31,728,1), X_MASK, M601, { RA, RS, RB } },
3630 { "sreq", XRC(31,729,0), X_MASK, M601, { RA, RS, RB } },
3631 { "sreq.", XRC(31,729,1), X_MASK, M601, { RA, RS, RB } },
3633 { "stfdxe", X(31,735), X_MASK, BOOKE64, { FRS, RA, RB } },
3635 { "dcba", X(31,758), XRT_MASK, PPC405, { RA, RB } },
3636 { "dcba", X(31,758), XRT_MASK, BOOKE, { RA, RB } },
3638 { "stfdux", X(31,759), X_MASK, COM, { FRS, RAS, RB } },
3640 { "srliq", XRC(31,760,0), X_MASK, M601, { RA, RS, SH } },
3641 { "srliq.", XRC(31,760,1), X_MASK, M601, { RA, RS, SH } },
3643 { "dcbae", X(31,766), XRT_MASK, BOOKE64, { RA, RB } },
3645 { "stfduxe", X(31,767), X_MASK, BOOKE64, { FRS, RAS, RB } },
3647 { "tlbivax", X(31,786), XRT_MASK, BOOKE, { RA, RB } },
3648 { "tlbivaxe",X(31,787), XRT_MASK, BOOKE, { RA, RB } },
3650 { "lhbrx", X(31,790), X_MASK, COM, { RT, RA, RB } },
3652 { "sraw", XRC(31,792,0), X_MASK, PPCCOM, { RA, RS, RB } },
3653 { "sra", XRC(31,792,0), X_MASK, PWRCOM, { RA, RS, RB } },
3654 { "sraw.", XRC(31,792,1), X_MASK, PPCCOM, { RA, RS, RB } },
3655 { "sra.", XRC(31,792,1), X_MASK, PWRCOM, { RA, RS, RB } },
3657 { "srad", XRC(31,794,0), X_MASK, PPC64, { RA, RS, RB } },
3658 { "srad.", XRC(31,794,1), X_MASK, PPC64, { RA, RS, RB } },
3660 { "lhbrxe", X(31,798), X_MASK, BOOKE64, { RT, RA, RB } },
3662 { "ldxe", X(31,799), X_MASK, BOOKE64, { RT, RA, RB } },
3663 { "lduxe", X(31,831), X_MASK, BOOKE64, { RT, RA, RB } },
3665 { "rac", X(31,818), X_MASK, PWRCOM, { RT, RA, RB } },
3667 { "dss", XDSS(31,822,0), XDSS_MASK, PPCVEC, { STRM } },
3668 { "dssall", XDSS(31,822,1), XDSS_MASK, PPCVEC, { STRM } },
3670 { "srawi", XRC(31,824,0), X_MASK, PPCCOM, { RA, RS, SH } },
3671 { "srai", XRC(31,824,0), X_MASK, PWRCOM, { RA, RS, SH } },
3672 { "srawi.", XRC(31,824,1), X_MASK, PPCCOM, { RA, RS, SH } },
3673 { "srai.", XRC(31,824,1), X_MASK, PWRCOM, { RA, RS, SH } },
3675 { "slbmfev", X(31,851), XRA_MASK, PPC64, { RT, RB } },
3677 { "eieio", X(31,854), 0xffffffff, PPC, { 0 } },
3678 { "mbar", X(31,854), 0xffffffff, BOOKE, { MO } },
3680 { "tlbsx", XRC(31,914,0), X_MASK, PPC403, { RT, RA, RB } },
3681 { "tlbsx.", XRC(31,914,1), X_MASK, PPC403, { RT, RA, RB } },
3683 { "tlbsx", XRC(31,914,0), X_MASK, BOOKE, { RA, RB } },
3684 { "tlbsxe", XRC(31,915,0), X_MASK, BOOKE, { RA, RB } },
3686 { "slbmfee", X(31,915), XRA_MASK, PPC64, { RT, RB } },
3688 { "sthbrx", X(31,918), X_MASK, COM, { RS, RA, RB } },
3690 { "sraq", XRC(31,920,0), X_MASK, M601, { RA, RS, RB } },
3691 { "sraq.", XRC(31,920,1), X_MASK, M601, { RA, RS, RB } },
3693 { "srea", XRC(31,921,0), X_MASK, M601, { RA, RS, RB } },
3694 { "srea.", XRC(31,921,1), X_MASK, M601, { RA, RS, RB } },
3696 { "extsh", XRC(31,922,0), XRB_MASK, PPCCOM, { RA, RS } },
3697 { "exts", XRC(31,922,0), XRB_MASK, PWRCOM, { RA, RS } },
3698 { "extsh.", XRC(31,922,1), XRB_MASK, PPCCOM, { RA, RS } },
3699 { "exts.", XRC(31,922,1), XRB_MASK, PWRCOM, { RA, RS } },
3701 { "sthbrxe", X(31,926), X_MASK, BOOKE64, { RS, RA, RB } },
3703 { "stdxe", X(31,927), X_MASK, BOOKE64, { RS, RA, RB } },
3705 { "tlbre", X(31,946), X_MASK, BOOKE, { RT, RA, WS } },
3707 { "tlbrehi", XTLB(31,946,0), XTLB_MASK, PPC403, { RT, RA } },
3708 { "tlbrelo", XTLB(31,946,1), XTLB_MASK, PPC403, { RT, RA } },
3710 { "sraiq", XRC(31,952,0), X_MASK, M601, { RA, RS, SH } },
3711 { "sraiq.", XRC(31,952,1), X_MASK, M601, { RA, RS, SH } },
3713 { "extsb", XRC(31,954,0), XRB_MASK, PPC, { RA, RS} },
3714 { "extsb.", XRC(31,954,1), XRB_MASK, PPC, { RA, RS} },
3716 { "stduxe", X(31,959), X_MASK, BOOKE64, { RS, RAS, RB } },
3718 { "iccci", X(31,966), XRT_MASK, PPC403, { RA, RB } },
3720 { "tlbld", X(31,978), XRTRA_MASK, PPC, { RB } },
3722 { "tlbwehi", XTLB(31,978,0), XTLB_MASK, PPC403, { RT, RA } },
3723 { "tlbwelo", XTLB(31,978,1), XTLB_MASK, PPC403, { RT, RA } },
3724 { "tlbwe", X(31,978), X_MASK, PPC403, { RS, RA, SH } },
3726 { "tlbwe", X(31,978), X_MASK, BOOKE, { RT, RA, WS } },
3728 { "icbi", X(31,982), XRT_MASK, PPC, { RA, RB } },
3730 { "stfiwx", X(31,983), X_MASK, PPC, { FRS, RA, RB } },
3732 { "extsw", XRC(31,986,0), XRB_MASK, PPC, { RA, RS } },
3733 { "extsw.", XRC(31,986,1), XRB_MASK, PPC, { RA, RS } },
3735 { "icread", X(31,998), XRT_MASK, PPC403, { RA, RB } },
3737 { "icbie", X(31,990), XRT_MASK, BOOKE64, { RA, RB } },
3738 { "stfiwxe", X(31,991), X_MASK, BOOKE64, { FRS, RA, RB } },
3740 { "tlbli", X(31,1010), XRTRA_MASK, PPC, { RB } },
3742 { "dcbz", X(31,1014), XRT_MASK, PPC, { RA, RB } },
3743 { "dclz", X(31,1014), XRT_MASK, PPC, { RA, RB } },
3745 { "dcbze", X(31,1022), XRT_MASK, BOOKE64, { RA, RB } },
3747 { "lvebx", X(31, 7), X_MASK, PPCVEC, { VD, RA, RB } },
3748 { "lvehx", X(31, 39), X_MASK, PPCVEC, { VD, RA, RB } },
3749 { "lvewx", X(31, 71), X_MASK, PPCVEC, { VD, RA, RB } },
3750 { "lvsl", X(31, 6), X_MASK, PPCVEC, { VD, RA, RB } },
3751 { "lvsr", X(31, 38), X_MASK, PPCVEC, { VD, RA, RB } },
3752 { "lvx", X(31, 103), X_MASK, PPCVEC, { VD, RA, RB } },
3753 { "lvxl", X(31, 359), X_MASK, PPCVEC, { VD, RA, RB } },
3754 { "stvebx", X(31, 135), X_MASK, PPCVEC, { VS, RA, RB } },
3755 { "stvehx", X(31, 167), X_MASK, PPCVEC, { VS, RA, RB } },
3756 { "stvewx", X(31, 199), X_MASK, PPCVEC, { VS, RA, RB } },
3757 { "stvx", X(31, 231), X_MASK, PPCVEC, { VS, RA, RB } },
3758 { "stvxl", X(31, 487), X_MASK, PPCVEC, { VS, RA, RB } },
3760 { "lwz", OP(32), OP_MASK, PPCCOM, { RT, D, RA } },
3761 { "l", OP(32), OP_MASK, PWRCOM, { RT, D, RA } },
3763 { "lwzu", OP(33), OP_MASK, PPCCOM, { RT, D, RAL } },
3764 { "lu", OP(33), OP_MASK, PWRCOM, { RT, D, RA } },
3766 { "lbz", OP(34), OP_MASK, COM, { RT, D, RA } },
3768 { "lbzu", OP(35), OP_MASK, COM, { RT, D, RAL } },
3770 { "stw", OP(36), OP_MASK, PPCCOM, { RS, D, RA } },
3771 { "st", OP(36), OP_MASK, PWRCOM, { RS, D, RA } },
3773 { "stwu", OP(37), OP_MASK, PPCCOM, { RS, D, RAS } },
3774 { "stu", OP(37), OP_MASK, PWRCOM, { RS, D, RA } },
3776 { "stb", OP(38), OP_MASK, COM, { RS, D, RA } },
3778 { "stbu", OP(39), OP_MASK, COM, { RS, D, RAS } },
3780 { "lhz", OP(40), OP_MASK, COM, { RT, D, RA } },
3782 { "lhzu", OP(41), OP_MASK, COM, { RT, D, RAL } },
3784 { "lha", OP(42), OP_MASK, COM, { RT, D, RA } },
3786 { "lhau", OP(43), OP_MASK, COM, { RT, D, RAL } },
3788 { "sth", OP(44), OP_MASK, COM, { RS, D, RA } },
3790 { "sthu", OP(45), OP_MASK, COM, { RS, D, RAS } },
3792 { "lmw", OP(46), OP_MASK, PPCCOM, { RT, D, RAM } },
3793 { "lm", OP(46), OP_MASK, PWRCOM, { RT, D, RA } },
3795 { "stmw", OP(47), OP_MASK, PPCCOM, { RS, D, RA } },
3796 { "stm", OP(47), OP_MASK, PWRCOM, { RS, D, RA } },
3798 { "lfs", OP(48), OP_MASK, COM, { FRT, D, RA } },
3800 { "lfsu", OP(49), OP_MASK, COM, { FRT, D, RAS } },
3802 { "lfd", OP(50), OP_MASK, COM, { FRT, D, RA } },
3804 { "lfdu", OP(51), OP_MASK, COM, { FRT, D, RAS } },
3806 { "stfs", OP(52), OP_MASK, COM, { FRS, D, RA } },
3808 { "stfsu", OP(53), OP_MASK, COM, { FRS, D, RAS } },
3810 { "stfd", OP(54), OP_MASK, COM, { FRS, D, RA } },
3812 { "stfdu", OP(55), OP_MASK, COM, { FRS, D, RAS } },
3814 { "lfq", OP(56), OP_MASK, POWER2, { FRT, D, RA } },
3816 { "lfqu", OP(57), OP_MASK, POWER2, { FRT, D, RA } },
3818 { "lbze", DEO(58,0), DE_MASK, BOOKE64, { RT, DE, RA } },
3819 { "lbzue", DEO(58,1), DE_MASK, BOOKE64, { RT, DE, RAL } },
3820 { "lhze", DEO(58,2), DE_MASK, BOOKE64, { RT, DE, RA } },
3821 { "lhzue", DEO(58,3), DE_MASK, BOOKE64, { RT, DE, RAL } },
3822 { "lhae", DEO(58,4), DE_MASK, BOOKE64, { RT, DE, RA } },
3823 { "lhaue", DEO(58,5), DE_MASK, BOOKE64, { RT, DE, RAL } },
3824 { "lwze", DEO(58,6), DE_MASK, BOOKE64, { RT, DE, RA } },
3825 { "lwzue", DEO(58,7), DE_MASK, BOOKE64, { RT, DE, RAL } },
3826 { "stbe", DEO(58,8), DE_MASK, BOOKE64, { RS, DE, RA } },
3827 { "stbue", DEO(58,9), DE_MASK, BOOKE64, { RS, DE, RAS } },
3828 { "sthe", DEO(58,10), DE_MASK, BOOKE64, { RS, DE, RA } },
3829 { "sthue", DEO(58,11), DE_MASK, BOOKE64, { RS, DE, RAS } },
3830 { "stwe", DEO(58,14), DE_MASK, BOOKE64, { RS, DE, RA } },
3831 { "stwue", DEO(58,15), DE_MASK, BOOKE64, { RS, DE, RAS } },
3833 { "ld", DSO(58,0), DS_MASK, PPC64, { RT, DS, RA } },
3835 { "ldu", DSO(58,1), DS_MASK, PPC64, { RT, DS, RAL } },
3837 { "lwa", DSO(58,2), DS_MASK, PPC64, { RT, DS, RA } },
3839 { "fdivs", A(59,18,0), AFRC_MASK, PPC, { FRT, FRA, FRB } },
3840 { "fdivs.", A(59,18,1), AFRC_MASK, PPC, { FRT, FRA, FRB } },
3842 { "fsubs", A(59,20,0), AFRC_MASK, PPC, { FRT, FRA, FRB } },
3843 { "fsubs.", A(59,20,1), AFRC_MASK, PPC, { FRT, FRA, FRB } },
3845 { "fadds", A(59,21,0), AFRC_MASK, PPC, { FRT, FRA, FRB } },
3846 { "fadds.", A(59,21,1), AFRC_MASK, PPC, { FRT, FRA, FRB } },
3848 { "fsqrts", A(59,22,0), AFRAFRC_MASK, PPC, { FRT, FRB } },
3849 { "fsqrts.", A(59,22,1), AFRAFRC_MASK, PPC, { FRT, FRB } },
3851 { "fres", A(59,24,0), AFRAFRC_MASK, PPC, { FRT, FRB } },
3852 { "fres.", A(59,24,1), AFRAFRC_MASK, PPC, { FRT, FRB } },
3854 { "fmuls", A(59,25,0), AFRB_MASK, PPC, { FRT, FRA, FRC } },
3855 { "fmuls.", A(59,25,1), AFRB_MASK, PPC, { FRT, FRA, FRC } },
3857 { "fmsubs", A(59,28,0), A_MASK, PPC, { FRT,FRA,FRC,FRB } },
3858 { "fmsubs.", A(59,28,1), A_MASK, PPC, { FRT,FRA,FRC,FRB } },
3860 { "fmadds", A(59,29,0), A_MASK, PPC, { FRT,FRA,FRC,FRB } },
3861 { "fmadds.", A(59,29,1), A_MASK, PPC, { FRT,FRA,FRC,FRB } },
3863 { "fnmsubs", A(59,30,0), A_MASK, PPC, { FRT,FRA,FRC,FRB } },
3864 { "fnmsubs.",A(59,30,1), A_MASK, PPC, { FRT,FRA,FRC,FRB } },
3866 { "fnmadds", A(59,31,0), A_MASK, PPC, { FRT,FRA,FRC,FRB } },
3867 { "fnmadds.",A(59,31,1), A_MASK, PPC, { FRT,FRA,FRC,FRB } },
3869 { "stfq", OP(60), OP_MASK, POWER2, { FRS, D, RA } },
3871 { "stfqu", OP(61), OP_MASK, POWER2, { FRS, D, RA } },
3873 { "lde", DEO(62,0), DE_MASK, BOOKE64, { RT, DES, RA } },
3874 { "ldue", DEO(62,1), DE_MASK, BOOKE64, { RT, DES, RA } },
3875 { "lfse", DEO(62,4), DE_MASK, BOOKE64, { FRT, DES, RA } },
3876 { "lfsue", DEO(62,5), DE_MASK, BOOKE64, { FRT, DES, RAS } },
3877 { "lfde", DEO(62,6), DE_MASK, BOOKE64, { FRT, DES, RA } },
3878 { "lfdue", DEO(62,7), DE_MASK, BOOKE64, { FRT, DES, RAS } },
3879 { "stde", DEO(62,8), DE_MASK, BOOKE64, { RS, DES, RA } },
3880 { "stdue", DEO(62,9), DE_MASK, BOOKE64, { RS, DES, RAS } },
3881 { "stfse", DEO(62,12), DE_MASK, BOOKE64, { FRS, DES, RA } },
3882 { "stfsue", DEO(62,13), DE_MASK, BOOKE64, { FRS, DES, RAS } },
3883 { "stfde", DEO(62,14), DE_MASK, BOOKE64, { FRS, DES, RA } },
3884 { "stfdue", DEO(62,15), DE_MASK, BOOKE64, { FRS, DES, RAS } },
3886 { "std", DSO(62,0), DS_MASK, PPC64, { RS, DS, RA } },
3888 { "stdu", DSO(62,1), DS_MASK, PPC64, { RS, DS, RAS } },
3890 { "fcmpu", X(63,0), X_MASK|(3<<21), COM, { BF, FRA, FRB } },
3892 { "frsp", XRC(63,12,0), XRA_MASK, COM, { FRT, FRB } },
3893 { "frsp.", XRC(63,12,1), XRA_MASK, COM, { FRT, FRB } },
3895 { "fctiw", XRC(63,14,0), XRA_MASK, PPCCOM, { FRT, FRB } },
3896 { "fcir", XRC(63,14,0), XRA_MASK, POWER2, { FRT, FRB } },
3897 { "fctiw.", XRC(63,14,1), XRA_MASK, PPCCOM, { FRT, FRB } },
3898 { "fcir.", XRC(63,14,1), XRA_MASK, POWER2, { FRT, FRB } },
3900 { "fctiwz", XRC(63,15,0), XRA_MASK, PPCCOM, { FRT, FRB } },
3901 { "fcirz", XRC(63,15,0), XRA_MASK, POWER2, { FRT, FRB } },
3902 { "fctiwz.", XRC(63,15,1), XRA_MASK, PPCCOM, { FRT, FRB } },
3903 { "fcirz.", XRC(63,15,1), XRA_MASK, POWER2, { FRT, FRB } },
3905 { "fdiv", A(63,18,0), AFRC_MASK, PPCCOM, { FRT, FRA, FRB } },
3906 { "fd", A(63,18,0), AFRC_MASK, PWRCOM, { FRT, FRA, FRB } },
3907 { "fdiv.", A(63,18,1), AFRC_MASK, PPCCOM, { FRT, FRA, FRB } },
3908 { "fd.", A(63,18,1), AFRC_MASK, PWRCOM, { FRT, FRA, FRB } },
3910 { "fsub", A(63,20,0), AFRC_MASK, PPCCOM, { FRT, FRA, FRB } },
3911 { "fs", A(63,20,0), AFRC_MASK, PWRCOM, { FRT, FRA, FRB } },
3912 { "fsub.", A(63,20,1), AFRC_MASK, PPCCOM, { FRT, FRA, FRB } },
3913 { "fs.", A(63,20,1), AFRC_MASK, PWRCOM, { FRT, FRA, FRB } },
3915 { "fadd", A(63,21,0), AFRC_MASK, PPCCOM, { FRT, FRA, FRB } },
3916 { "fa", A(63,21,0), AFRC_MASK, PWRCOM, { FRT, FRA, FRB } },
3917 { "fadd.", A(63,21,1), AFRC_MASK, PPCCOM, { FRT, FRA, FRB } },
3918 { "fa.", A(63,21,1), AFRC_MASK, PWRCOM, { FRT, FRA, FRB } },
3920 { "fsqrt", A(63,22,0), AFRAFRC_MASK, PPCPWR2, { FRT, FRB } },
3921 { "fsqrt.", A(63,22,1), AFRAFRC_MASK, PPCPWR2, { FRT, FRB } },
3923 { "fsel", A(63,23,0), A_MASK, PPC, { FRT,FRA,FRC,FRB } },
3924 { "fsel.", A(63,23,1), A_MASK, PPC, { FRT,FRA,FRC,FRB } },
3926 { "fmul", A(63,25,0), AFRB_MASK, PPCCOM, { FRT, FRA, FRC } },
3927 { "fm", A(63,25,0), AFRB_MASK, PWRCOM, { FRT, FRA, FRC } },
3928 { "fmul.", A(63,25,1), AFRB_MASK, PPCCOM, { FRT, FRA, FRC } },
3929 { "fm.", A(63,25,1), AFRB_MASK, PWRCOM, { FRT, FRA, FRC } },
3931 { "frsqrte", A(63,26,0), AFRAFRC_MASK, PPC, { FRT, FRB } },
3932 { "frsqrte.",A(63,26,1), AFRAFRC_MASK, PPC, { FRT, FRB } },
3934 { "fmsub", A(63,28,0), A_MASK, PPCCOM, { FRT,FRA,FRC,FRB } },
3935 { "fms", A(63,28,0), A_MASK, PWRCOM, { FRT,FRA,FRC,FRB } },
3936 { "fmsub.", A(63,28,1), A_MASK, PPCCOM, { FRT,FRA,FRC,FRB } },
3937 { "fms.", A(63,28,1), A_MASK, PWRCOM, { FRT,FRA,FRC,FRB } },
3939 { "fmadd", A(63,29,0), A_MASK, PPCCOM, { FRT,FRA,FRC,FRB } },
3940 { "fma", A(63,29,0), A_MASK, PWRCOM, { FRT,FRA,FRC,FRB } },
3941 { "fmadd.", A(63,29,1), A_MASK, PPCCOM, { FRT,FRA,FRC,FRB } },
3942 { "fma.", A(63,29,1), A_MASK, PWRCOM, { FRT,FRA,FRC,FRB } },
3944 { "fnmsub", A(63,30,0), A_MASK, PPCCOM, { FRT,FRA,FRC,FRB } },
3945 { "fnms", A(63,30,0), A_MASK, PWRCOM, { FRT,FRA,FRC,FRB } },
3946 { "fnmsub.", A(63,30,1), A_MASK, PPCCOM, { FRT,FRA,FRC,FRB } },
3947 { "fnms.", A(63,30,1), A_MASK, PWRCOM, { FRT,FRA,FRC,FRB } },
3949 { "fnmadd", A(63,31,0), A_MASK, PPCCOM, { FRT,FRA,FRC,FRB } },
3950 { "fnma", A(63,31,0), A_MASK, PWRCOM, { FRT,FRA,FRC,FRB } },
3951 { "fnmadd.", A(63,31,1), A_MASK, PPCCOM, { FRT,FRA,FRC,FRB } },
3952 { "fnma.", A(63,31,1), A_MASK, PWRCOM, { FRT,FRA,FRC,FRB } },
3954 { "fcmpo", X(63,32), X_MASK|(3<<21), COM, { BF, FRA, FRB } },
3956 { "mtfsb1", XRC(63,38,0), XRARB_MASK, COM, { BT } },
3957 { "mtfsb1.", XRC(63,38,1), XRARB_MASK, COM, { BT } },
3959 { "fneg", XRC(63,40,0), XRA_MASK, COM, { FRT, FRB } },
3960 { "fneg.", XRC(63,40,1), XRA_MASK, COM, { FRT, FRB } },
3962 { "mcrfs", X(63,64), XRB_MASK|(3<<21)|(3<<16), COM, { BF, BFA } },
3964 { "mtfsb0", XRC(63,70,0), XRARB_MASK, COM, { BT } },
3965 { "mtfsb0.", XRC(63,70,1), XRARB_MASK, COM, { BT } },
3967 { "fmr", XRC(63,72,0), XRA_MASK, COM, { FRT, FRB } },
3968 { "fmr.", XRC(63,72,1), XRA_MASK, COM, { FRT, FRB } },
3970 { "mtfsfi", XRC(63,134,0), XRA_MASK|(3<<21)|(1<<11), COM, { BF, U } },
3971 { "mtfsfi.", XRC(63,134,1), XRA_MASK|(3<<21)|(1<<11), COM, { BF, U } },
3973 { "fnabs", XRC(63,136,0), XRA_MASK, COM, { FRT, FRB } },
3974 { "fnabs.", XRC(63,136,1), XRA_MASK, COM, { FRT, FRB } },
3976 { "fabs", XRC(63,264,0), XRA_MASK, COM, { FRT, FRB } },
3977 { "fabs.", XRC(63,264,1), XRA_MASK, COM, { FRT, FRB } },
3979 { "mffs", XRC(63,583,0), XRARB_MASK, COM, { FRT } },
3980 { "mffs.", XRC(63,583,1), XRARB_MASK, COM, { FRT } },
3982 { "mtfsf", XFL(63,711,0), XFL_MASK, COM, { FLM, FRB } },
3983 { "mtfsf.", XFL(63,711,1), XFL_MASK, COM, { FLM, FRB } },
3985 { "fctid", XRC(63,814,0), XRA_MASK, PPC64, { FRT, FRB } },
3986 { "fctid.", XRC(63,814,1), XRA_MASK, PPC64, { FRT, FRB } },
3988 { "fctidz", XRC(63,815,0), XRA_MASK, PPC64, { FRT, FRB } },
3989 { "fctidz.", XRC(63,815,1), XRA_MASK, PPC64, { FRT, FRB } },
3991 { "fcfid", XRC(63,846,0), XRA_MASK, PPC64, { FRT, FRB } },
3992 { "fcfid.", XRC(63,846,1), XRA_MASK, PPC64, { FRT, FRB } },
3996 const int powerpc_num_opcodes =
3997 sizeof (powerpc_opcodes) / sizeof (powerpc_opcodes[0]);
3999 /* The macro table. This is only used by the assembler. */
4001 /* The expressions of the form (-x ! 31) & (x | 31) have the value 0
4002 when x=0; 32-x when x is between 1 and 31; are negative if x is
4003 negative; and are 32 or more otherwise. This is what you want
4004 when, for instance, you are emulating a right shift by a
4005 rotate-left-and-mask, because the underlying instructions support
4006 shifts of size 0 but not shifts of size 32. By comparison, when
4007 extracting x bits from some word you want to use just 32-x, because
4008 the underlying instructions don't support extracting 0 bits but do
4009 support extracting the whole word (32 bits in this case). */
4011 const struct powerpc_macro powerpc_macros[] = {
4012 { "extldi", 4, PPC64, "rldicr %0,%1,%3,(%2)-1" },
4013 { "extldi.", 4, PPC64, "rldicr. %0,%1,%3,(%2)-1" },
4014 { "extrdi", 4, PPC64, "rldicl %0,%1,(%2)+(%3),64-(%2)" },
4015 { "extrdi.", 4, PPC64, "rldicl. %0,%1,(%2)+(%3),64-(%2)" },
4016 { "insrdi", 4, PPC64, "rldimi %0,%1,64-((%2)+(%3)),%3" },
4017 { "insrdi.", 4, PPC64, "rldimi. %0,%1,64-((%2)+(%3)),%3" },
4018 { "rotrdi", 3, PPC64, "rldicl %0,%1,(-(%2)!63)&((%2)|63),0" },
4019 { "rotrdi.", 3, PPC64, "rldicl. %0,%1,(-(%2)!63)&((%2)|63),0" },
4020 { "sldi", 3, PPC64, "rldicr %0,%1,%2,63-(%2)" },
4021 { "sldi.", 3, PPC64, "rldicr. %0,%1,%2,63-(%2)" },
4022 { "srdi", 3, PPC64, "rldicl %0,%1,(-(%2)!63)&((%2)|63),%2" },
4023 { "srdi.", 3, PPC64, "rldicl. %0,%1,(-(%2)!63)&((%2)|63),%2" },
4024 { "clrrdi", 3, PPC64, "rldicr %0,%1,0,63-(%2)" },
4025 { "clrrdi.", 3, PPC64, "rldicr. %0,%1,0,63-(%2)" },
4026 { "clrlsldi",4, PPC64, "rldic %0,%1,%3,(%2)-(%3)" },
4027 { "clrlsldi.",4, PPC64, "rldic. %0,%1,%3,(%2)-(%3)" },
4029 { "extlwi", 4, PPCCOM, "rlwinm %0,%1,%3,0,(%2)-1" },
4030 { "extlwi.", 4, PPCCOM, "rlwinm. %0,%1,%3,0,(%2)-1" },
4031 { "extrwi", 4, PPCCOM, "rlwinm %0,%1,(%2)+(%3),32-(%2),31" },
4032 { "extrwi.", 4, PPCCOM, "rlwinm. %0,%1,(%2)+(%3),32-(%2),31" },
4033 { "inslwi", 4, PPCCOM, "rlwimi %0,%1,(-(%3)!31)&((%3)|31),%3,(%2)+(%3)-1" },
4034 { "inslwi.", 4, PPCCOM, "rlwimi. %0,%1,(-(%3)!31)&((%3)|31),%3,(%2)+(%3)-1"},
4035 { "insrwi", 4, PPCCOM, "rlwimi %0,%1,32-((%2)+(%3)),%3,(%2)+(%3)-1" },
4036 { "insrwi.", 4, PPCCOM, "rlwimi. %0,%1,32-((%2)+(%3)),%3,(%2)+(%3)-1"},
4037 { "rotrwi", 3, PPCCOM, "rlwinm %0,%1,(-(%2)!31)&((%2)|31),0,31" },
4038 { "rotrwi.", 3, PPCCOM, "rlwinm. %0,%1,(-(%2)!31)&((%2)|31),0,31" },
4039 { "slwi", 3, PPCCOM, "rlwinm %0,%1,%2,0,31-(%2)" },
4040 { "sli", 3, PWRCOM, "rlinm %0,%1,%2,0,31-(%2)" },
4041 { "slwi.", 3, PPCCOM, "rlwinm. %0,%1,%2,0,31-(%2)" },
4042 { "sli.", 3, PWRCOM, "rlinm. %0,%1,%2,0,31-(%2)" },
4043 { "srwi", 3, PPCCOM, "rlwinm %0,%1,(-(%2)!31)&((%2)|31),%2,31" },
4044 { "sri", 3, PWRCOM, "rlinm %0,%1,(-(%2)!31)&((%2)|31),%2,31" },
4045 { "srwi.", 3, PPCCOM, "rlwinm. %0,%1,(-(%2)!31)&((%2)|31),%2,31" },
4046 { "sri.", 3, PWRCOM, "rlinm. %0,%1,(-(%2)!31)&((%2)|31),%2,31" },
4047 { "clrrwi", 3, PPCCOM, "rlwinm %0,%1,0,0,31-(%2)" },
4048 { "clrrwi.", 3, PPCCOM, "rlwinm. %0,%1,0,0,31-(%2)" },
4049 { "clrlslwi",4, PPCCOM, "rlwinm %0,%1,%3,(%2)-(%3),31-(%3)" },
4050 { "clrlslwi.",4, PPCCOM, "rlwinm. %0,%1,%3,(%2)-(%3),31-(%3)" },
4054 const int powerpc_num_macros =
4055 sizeof (powerpc_macros) / sizeof (powerpc_macros[0]);