1 /* ppc-opc.c -- PowerPC opcode list
2 Copyright 1994, 1995, 1996, 1997, 1998, 2000, 2001, 2002, 2003
3 Free Software Foundation, Inc.
4 Written by Ian Lance Taylor, Cygnus Support
6 This file is part of GDB, GAS, and the GNU binutils.
8 GDB, GAS, and the GNU binutils are free software; you can redistribute
9 them and/or modify them under the terms of the GNU General Public
10 License as published by the Free Software Foundation; either version
11 2, or (at your option) any later version.
13 GDB, GAS, and the GNU binutils are distributed in the hope that they
14 will be useful, but WITHOUT ANY WARRANTY; without even the implied
15 warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See
16 the GNU General Public License for more details.
18 You should have received a copy of the GNU General Public License
19 along with this file; see the file COPYING. If not, write to the Free
20 Software Foundation, 59 Temple Place - Suite 330, Boston, MA
25 #include "opcode/ppc.h"
28 /* This file holds the PowerPC opcode table. The opcode table
29 includes almost all of the extended instruction mnemonics. This
30 permits the disassembler to use them, and simplifies the assembler
31 logic, at the cost of increasing the table size. The table is
32 strictly constant data, so the compiler should be able to put it in
35 This file also holds the operand table. All knowledge about
36 inserting operands into instructions and vice-versa is kept in this
39 /* Local insertion and extraction functions. */
41 static unsigned long insert_bat (unsigned long, long, int, const char **);
42 static long extract_bat (unsigned long, int, int *);
43 static unsigned long insert_bba (unsigned long, long, int, const char **);
44 static long extract_bba (unsigned long, int, int *);
45 static unsigned long insert_bd (unsigned long, long, int, const char **);
46 static long extract_bd (unsigned long, int, int *);
47 static unsigned long insert_bdm (unsigned long, long, int, const char **);
48 static long extract_bdm (unsigned long, int, int *);
49 static unsigned long insert_bdp (unsigned long, long, int, const char **);
50 static long extract_bdp (unsigned long, int, int *);
51 static unsigned long insert_bo (unsigned long, long, int, const char **);
52 static long extract_bo (unsigned long, int, int *);
53 static unsigned long insert_boe (unsigned long, long, int, const char **);
54 static long extract_boe (unsigned long, int, int *);
55 static unsigned long insert_dq (unsigned long, long, int, const char **);
56 static long extract_dq (unsigned long, int, int *);
57 static unsigned long insert_ds (unsigned long, long, int, const char **);
58 static long extract_ds (unsigned long, int, int *);
59 static unsigned long insert_de (unsigned long, long, int, const char **);
60 static long extract_de (unsigned long, int, int *);
61 static unsigned long insert_des (unsigned long, long, int, const char **);
62 static long extract_des (unsigned long, int, int *);
63 static unsigned long insert_fxm (unsigned long, long, int, const char **);
64 static long extract_fxm (unsigned long, int, int *);
65 static unsigned long insert_li (unsigned long, long, int, const char **);
66 static long extract_li (unsigned long, int, int *);
67 static unsigned long insert_mbe (unsigned long, long, int, const char **);
68 static long extract_mbe (unsigned long, int, int *);
69 static unsigned long insert_mb6 (unsigned long, long, int, const char **);
70 static long extract_mb6 (unsigned long, int, int *);
71 static unsigned long insert_nb (unsigned long, long, int, const char **);
72 static long extract_nb (unsigned long, int, int *);
73 static unsigned long insert_nsi (unsigned long, long, int, const char **);
74 static long extract_nsi (unsigned long, int, int *);
75 static unsigned long insert_ral (unsigned long, long, int, const char **);
76 static unsigned long insert_ram (unsigned long, long, int, const char **);
77 static unsigned long insert_raq (unsigned long, long, int, const char **);
78 static unsigned long insert_ras (unsigned long, long, int, const char **);
79 static unsigned long insert_rbs (unsigned long, long, int, const char **);
80 static long extract_rbs (unsigned long, int, int *);
81 static unsigned long insert_rsq (unsigned long, long, int, const char **);
82 static unsigned long insert_rtq (unsigned long, long, int, const char **);
83 static unsigned long insert_sh6 (unsigned long, long, int, const char **);
84 static long extract_sh6 (unsigned long, int, int *);
85 static unsigned long insert_spr (unsigned long, long, int, const char **);
86 static long extract_spr (unsigned long, int, int *);
87 static unsigned long insert_tbr (unsigned long, long, int, const char **);
88 static long extract_tbr (unsigned long, int, int *);
89 static unsigned long insert_ev2 (unsigned long, long, int, const char **);
90 static long extract_ev2 (unsigned long, int, int *);
91 static unsigned long insert_ev4 (unsigned long, long, int, const char **);
92 static long extract_ev4 (unsigned long, int, int *);
93 static unsigned long insert_ev8 (unsigned long, long, int, const char **);
94 static long extract_ev8 (unsigned long, int, int *);
96 /* The operands table.
98 The fields are bits, shift, insert, extract, flags.
100 We used to put parens around the various additions, like the one
101 for BA just below. However, that caused trouble with feeble
102 compilers with a limit on depth of a parenthesized expression, like
103 (reportedly) the compiler in Microsoft Developer Studio 5. So we
104 omit the parens, since the macros are never used in a context where
105 the addition will be ambiguous. */
107 const struct powerpc_operand powerpc_operands[] =
109 /* The zero index is used to indicate the end of the list of
114 /* The BA field in an XL form instruction. */
115 #define BA UNUSED + 1
116 #define BA_MASK (0x1f << 16)
117 { 5, 16, 0, 0, PPC_OPERAND_CR },
119 /* The BA field in an XL form instruction when it must be the same
120 as the BT field in the same instruction. */
122 { 5, 16, insert_bat, extract_bat, PPC_OPERAND_FAKE },
124 /* The BB field in an XL form instruction. */
126 #define BB_MASK (0x1f << 11)
127 { 5, 11, 0, 0, PPC_OPERAND_CR },
129 /* The BB field in an XL form instruction when it must be the same
130 as the BA field in the same instruction. */
132 { 5, 11, insert_bba, extract_bba, PPC_OPERAND_FAKE },
134 /* The BD field in a B form instruction. The lower two bits are
137 { 16, 0, insert_bd, extract_bd, PPC_OPERAND_RELATIVE | PPC_OPERAND_SIGNED },
139 /* The BD field in a B form instruction when absolute addressing is
142 { 16, 0, insert_bd, extract_bd, PPC_OPERAND_ABSOLUTE | PPC_OPERAND_SIGNED },
144 /* The BD field in a B form instruction when the - modifier is used.
145 This sets the y bit of the BO field appropriately. */
147 { 16, 0, insert_bdm, extract_bdm,
148 PPC_OPERAND_RELATIVE | PPC_OPERAND_SIGNED },
150 /* The BD field in a B form instruction when the - modifier is used
151 and absolute address is used. */
153 { 16, 0, insert_bdm, extract_bdm,
154 PPC_OPERAND_ABSOLUTE | PPC_OPERAND_SIGNED },
156 /* The BD field in a B form instruction when the + modifier is used.
157 This sets the y bit of the BO field appropriately. */
159 { 16, 0, insert_bdp, extract_bdp,
160 PPC_OPERAND_RELATIVE | PPC_OPERAND_SIGNED },
162 /* The BD field in a B form instruction when the + modifier is used
163 and absolute addressing is used. */
165 { 16, 0, insert_bdp, extract_bdp,
166 PPC_OPERAND_ABSOLUTE | PPC_OPERAND_SIGNED },
168 /* The BF field in an X or XL form instruction. */
170 { 3, 23, 0, 0, PPC_OPERAND_CR },
172 /* An optional BF field. This is used for comparison instructions,
173 in which an omitted BF field is taken as zero. */
175 { 3, 23, 0, 0, PPC_OPERAND_CR | PPC_OPERAND_OPTIONAL },
177 /* The BFA field in an X or XL form instruction. */
179 { 3, 18, 0, 0, PPC_OPERAND_CR },
181 /* The BI field in a B form or XL form instruction. */
183 #define BI_MASK (0x1f << 16)
184 { 5, 16, 0, 0, PPC_OPERAND_CR },
186 /* The BO field in a B form instruction. Certain values are
189 #define BO_MASK (0x1f << 21)
190 { 5, 21, insert_bo, extract_bo, 0 },
192 /* The BO field in a B form instruction when the + or - modifier is
193 used. This is like the BO field, but it must be even. */
195 { 5, 21, insert_boe, extract_boe, 0 },
197 /* The BT field in an X or XL form instruction. */
199 { 5, 21, 0, 0, PPC_OPERAND_CR },
201 /* The condition register number portion of the BI field in a B form
202 or XL form instruction. This is used for the extended
203 conditional branch mnemonics, which set the lower two bits of the
204 BI field. This field is optional. */
206 { 3, 18, 0, 0, PPC_OPERAND_CR | PPC_OPERAND_OPTIONAL },
208 /* The CRB field in an X form instruction. */
212 /* The CRFD field in an X form instruction. */
214 { 3, 23, 0, 0, PPC_OPERAND_CR },
216 /* The CRFS field in an X form instruction. */
217 #define CRFS CRFD + 1
218 { 3, 0, 0, 0, PPC_OPERAND_CR },
220 /* The CT field in an X form instruction. */
222 { 5, 21, 0, 0, PPC_OPERAND_OPTIONAL },
224 /* The D field in a D form instruction. This is a displacement off
225 a register, and implies that the next operand is a register in
228 { 16, 0, 0, 0, PPC_OPERAND_PARENS | PPC_OPERAND_SIGNED },
230 /* The DE field in a DE form instruction. This is like D, but is 12
233 { 14, 0, insert_de, extract_de, PPC_OPERAND_PARENS },
235 /* The DES field in a DES form instruction. This is like DS, but is 14
236 bits only (12 stored.) */
238 { 14, 0, insert_des, extract_des, PPC_OPERAND_PARENS | PPC_OPERAND_SIGNED },
240 /* The DQ field in a DQ form instruction. This is like D, but the
241 lower four bits are forced to zero. */
243 { 16, 0, insert_dq, extract_dq,
244 PPC_OPERAND_PARENS | PPC_OPERAND_SIGNED | PPC_OPERAND_DQ },
246 /* The DS field in a DS form instruction. This is like D, but the
247 lower two bits are forced to zero. */
249 { 16, 0, insert_ds, extract_ds,
250 PPC_OPERAND_PARENS | PPC_OPERAND_SIGNED | PPC_OPERAND_DS },
252 /* The E field in a wrteei instruction. */
256 /* The FL1 field in a POWER SC form instruction. */
260 /* The FL2 field in a POWER SC form instruction. */
264 /* The FLM field in an XFL form instruction. */
268 /* The FRA field in an X or A form instruction. */
270 #define FRA_MASK (0x1f << 16)
271 { 5, 16, 0, 0, PPC_OPERAND_FPR },
273 /* The FRB field in an X or A form instruction. */
275 #define FRB_MASK (0x1f << 11)
276 { 5, 11, 0, 0, PPC_OPERAND_FPR },
278 /* The FRC field in an A form instruction. */
280 #define FRC_MASK (0x1f << 6)
281 { 5, 6, 0, 0, PPC_OPERAND_FPR },
283 /* The FRS field in an X form instruction or the FRT field in a D, X
284 or A form instruction. */
287 { 5, 21, 0, 0, PPC_OPERAND_FPR },
289 /* The FXM field in an XFX instruction. */
291 #define FXM_MASK (0xff << 12)
292 { 8, 12, insert_fxm, extract_fxm, 0 },
294 /* Power4 version for mfcr. */
296 { 8, 12, insert_fxm, extract_fxm, PPC_OPERAND_OPTIONAL },
298 /* The L field in a D or X form instruction. */
300 { 1, 21, 0, 0, PPC_OPERAND_OPTIONAL },
302 /* The LEV field in a POWER SC form instruction. */
306 /* The LI field in an I form instruction. The lower two bits are
309 { 26, 0, insert_li, extract_li, PPC_OPERAND_RELATIVE | PPC_OPERAND_SIGNED },
311 /* The LI field in an I form instruction when used as an absolute
314 { 26, 0, insert_li, extract_li, PPC_OPERAND_ABSOLUTE | PPC_OPERAND_SIGNED },
316 /* The LS field in an X (sync) form instruction. */
318 { 2, 21, 0, 0, PPC_OPERAND_OPTIONAL },
320 /* The MB field in an M form instruction. */
322 #define MB_MASK (0x1f << 6)
325 /* The ME field in an M form instruction. */
327 #define ME_MASK (0x1f << 1)
330 /* The MB and ME fields in an M form instruction expressed a single
331 operand which is a bitmask indicating which bits to select. This
332 is a two operand form using PPC_OPERAND_NEXT. See the
333 description in opcode/ppc.h for what this means. */
335 { 5, 6, 0, 0, PPC_OPERAND_OPTIONAL | PPC_OPERAND_NEXT },
336 { 32, 0, insert_mbe, extract_mbe, 0 },
338 /* The MB or ME field in an MD or MDS form instruction. The high
339 bit is wrapped to the low end. */
342 #define MB6_MASK (0x3f << 5)
343 { 6, 5, insert_mb6, extract_mb6, 0 },
345 /* The MO field in an mbar instruction. */
349 /* The NB field in an X form instruction. The value 32 is stored as
352 { 6, 11, insert_nb, extract_nb, 0 },
354 /* The NSI field in a D form instruction. This is the same as the
355 SI field, only negated. */
357 { 16, 0, insert_nsi, extract_nsi,
358 PPC_OPERAND_NEGATIVE | PPC_OPERAND_SIGNED },
360 /* The RA field in an D, DS, DQ, X, XO, M, or MDS form instruction. */
362 #define RA_MASK (0x1f << 16)
363 { 5, 16, 0, 0, PPC_OPERAND_GPR },
365 /* The RA field in the DQ form lq instruction, which has special
366 value restrictions. */
368 { 5, 16, insert_raq, 0, PPC_OPERAND_GPR },
370 /* The RA field in a D or X form instruction which is an updating
371 load, which means that the RA field may not be zero and may not
372 equal the RT field. */
374 { 5, 16, insert_ral, 0, PPC_OPERAND_GPR },
376 /* The RA field in an lmw instruction, which has special value
379 { 5, 16, insert_ram, 0, PPC_OPERAND_GPR },
381 /* The RA field in a D or X form instruction which is an updating
382 store or an updating floating point load, which means that the RA
383 field may not be zero. */
385 { 5, 16, insert_ras, 0, PPC_OPERAND_GPR },
387 /* The RB field in an X, XO, M, or MDS form instruction. */
389 #define RB_MASK (0x1f << 11)
390 { 5, 11, 0, 0, PPC_OPERAND_GPR },
392 /* The RB field in an X form instruction when it must be the same as
393 the RS field in the instruction. This is used for extended
394 mnemonics like mr. */
396 { 5, 1, insert_rbs, extract_rbs, PPC_OPERAND_FAKE },
398 /* The RS field in a D, DS, X, XFX, XS, M, MD or MDS form
399 instruction or the RT field in a D, DS, X, XFX or XO form
403 #define RT_MASK (0x1f << 21)
404 { 5, 21, 0, 0, PPC_OPERAND_GPR },
406 /* The RS field of the DS form stq instruction, which has special
407 value restrictions. */
409 { 5, 21, insert_rsq, 0, PPC_OPERAND_GPR },
411 /* The RT field of the DQ form lq instruction, which has special
412 value restrictions. */
414 { 5, 21, insert_rtq, 0, PPC_OPERAND_GPR },
416 /* The SH field in an X or M form instruction. */
418 #define SH_MASK (0x1f << 11)
421 /* The SH field in an MD form instruction. This is split. */
423 #define SH6_MASK ((0x1f << 11) | (1 << 1))
424 { 6, 1, insert_sh6, extract_sh6, 0 },
426 /* The SI field in a D form instruction. */
428 { 16, 0, 0, 0, PPC_OPERAND_SIGNED },
430 /* The SI field in a D form instruction when we accept a wide range
431 of positive values. */
432 #define SISIGNOPT SI + 1
433 { 16, 0, 0, 0, PPC_OPERAND_SIGNED | PPC_OPERAND_SIGNOPT },
435 /* The SPR field in an XFX form instruction. This is flipped--the
436 lower 5 bits are stored in the upper 5 and vice- versa. */
437 #define SPR SISIGNOPT + 1
439 #define SPR_MASK (0x3ff << 11)
440 { 10, 11, insert_spr, extract_spr, 0 },
442 /* The BAT index number in an XFX form m[ft]ibat[lu] instruction. */
443 #define SPRBAT SPR + 1
444 #define SPRBAT_MASK (0x3 << 17)
447 /* The SPRG register number in an XFX form m[ft]sprg instruction. */
448 #define SPRG SPRBAT + 1
449 #define SPRG_MASK (0x3 << 16)
452 /* The SR field in an X form instruction. */
456 /* The STRM field in an X AltiVec form instruction. */
458 #define STRM_MASK (0x3 << 21)
461 /* The SV field in a POWER SC form instruction. */
465 /* The TBR field in an XFX form instruction. This is like the SPR
466 field, but it is optional. */
468 { 10, 11, insert_tbr, extract_tbr, PPC_OPERAND_OPTIONAL },
470 /* The TO field in a D or X form instruction. */
472 #define TO_MASK (0x1f << 21)
475 /* The U field in an X form instruction. */
479 /* The UI field in a D form instruction. */
483 /* The VA field in a VA, VX or VXR form instruction. */
485 #define VA_MASK (0x1f << 16)
486 { 5, 16, 0, 0, PPC_OPERAND_VR },
488 /* The VB field in a VA, VX or VXR form instruction. */
490 #define VB_MASK (0x1f << 11)
491 { 5, 11, 0, 0, PPC_OPERAND_VR },
493 /* The VC field in a VA form instruction. */
495 #define VC_MASK (0x1f << 6)
496 { 5, 6, 0, 0, PPC_OPERAND_VR },
498 /* The VD or VS field in a VA, VX, VXR or X form instruction. */
501 #define VD_MASK (0x1f << 21)
502 { 5, 21, 0, 0, PPC_OPERAND_VR },
504 /* The SIMM field in a VX form instruction. */
506 { 5, 16, 0, 0, PPC_OPERAND_SIGNED},
508 /* The UIMM field in a VX form instruction. */
509 #define UIMM SIMM + 1
512 /* The SHB field in a VA form instruction. */
516 /* The other UIMM field in a EVX form instruction. */
517 #define EVUIMM SHB + 1
520 /* The other UIMM field in a half word EVX form instruction. */
521 #define EVUIMM_2 EVUIMM + 1
522 { 32, 11, insert_ev2, extract_ev2, PPC_OPERAND_PARENS },
524 /* The other UIMM field in a word EVX form instruction. */
525 #define EVUIMM_4 EVUIMM_2 + 1
526 { 32, 11, insert_ev4, extract_ev4, PPC_OPERAND_PARENS },
528 /* The other UIMM field in a double EVX form instruction. */
529 #define EVUIMM_8 EVUIMM_4 + 1
530 { 32, 11, insert_ev8, extract_ev8, PPC_OPERAND_PARENS },
533 #define WS EVUIMM_8 + 1
534 #define WS_MASK (0x7 << 11)
537 /* The L field in an mtmsrd instruction */
538 #define MTMSRD_L WS + 1
539 { 1, 16, 0, 0, PPC_OPERAND_OPTIONAL },
543 /* The functions used to insert and extract complicated operands. */
545 /* The BA field in an XL form instruction when it must be the same as
546 the BT field in the same instruction. This operand is marked FAKE.
547 The insertion function just copies the BT field into the BA field,
548 and the extraction function just checks that the fields are the
553 insert_bat (unsigned long insn,
554 long value ATTRIBUTE_UNUSED,
555 int dialect ATTRIBUTE_UNUSED,
556 const char **errmsg ATTRIBUTE_UNUSED)
558 return insn | (((insn >> 21) & 0x1f) << 16);
562 extract_bat (unsigned long insn,
563 int dialect ATTRIBUTE_UNUSED,
567 && ((insn >> 21) & 0x1f) != ((insn >> 16) & 0x1f))
572 /* The BB field in an XL form instruction when it must be the same as
573 the BA field in the same instruction. This operand is marked FAKE.
574 The insertion function just copies the BA field into the BB field,
575 and the extraction function just checks that the fields are the
580 insert_bba (unsigned long insn,
581 long value ATTRIBUTE_UNUSED,
582 int dialect ATTRIBUTE_UNUSED,
583 const char **errmsg ATTRIBUTE_UNUSED)
585 return insn | (((insn >> 16) & 0x1f) << 11);
589 extract_bba (unsigned long insn,
590 int dialect ATTRIBUTE_UNUSED,
594 && ((insn >> 16) & 0x1f) != ((insn >> 11) & 0x1f))
599 /* The BD field in a B form instruction. The lower two bits are
604 insert_bd (unsigned long insn,
606 int dialect ATTRIBUTE_UNUSED,
607 const char **errmsg ATTRIBUTE_UNUSED)
609 return insn | (value & 0xfffc);
614 extract_bd (unsigned long insn,
615 int dialect ATTRIBUTE_UNUSED,
616 int *invalid ATTRIBUTE_UNUSED)
618 return ((insn & 0xfffc) ^ 0x8000) - 0x8000;
621 /* The BD field in a B form instruction when the - modifier is used.
622 This modifier means that the branch is not expected to be taken.
623 For chips built to versions of the architecture prior to version 2
624 (ie. not Power4 compatible), we set the y bit of the BO field to 1
625 if the offset is negative. When extracting, we require that the y
626 bit be 1 and that the offset be positive, since if the y bit is 0
627 we just want to print the normal form of the instruction.
628 Power4 compatible targets use two bits, "a", and "t", instead of
629 the "y" bit. "at" == 00 => no hint, "at" == 01 => unpredictable,
630 "at" == 10 => not taken, "at" == 11 => taken. The "t" bit is 00001
631 in BO field, the "a" bit is 00010 for branch on CR(BI) and 01000
632 for branch on CTR. We only handle the taken/not-taken hint here. */
636 insert_bdm (unsigned long insn,
639 const char **errmsg ATTRIBUTE_UNUSED)
641 if ((dialect & PPC_OPCODE_POWER4) == 0)
643 if ((value & 0x8000) != 0)
648 if ((insn & (0x14 << 21)) == (0x04 << 21))
650 else if ((insn & (0x14 << 21)) == (0x10 << 21))
653 return insn | (value & 0xfffc);
657 extract_bdm (unsigned long insn,
663 if ((dialect & PPC_OPCODE_POWER4) == 0)
665 if (((insn & (1 << 21)) == 0) != ((insn & (1 << 15)) == 0))
670 if ((insn & (0x17 << 21)) != (0x06 << 21)
671 && (insn & (0x1d << 21)) != (0x18 << 21))
675 return ((insn & 0xfffc) ^ 0x8000) - 0x8000;
678 /* The BD field in a B form instruction when the + modifier is used.
679 This is like BDM, above, except that the branch is expected to be
684 insert_bdp (unsigned long insn,
687 const char **errmsg ATTRIBUTE_UNUSED)
689 if ((dialect & PPC_OPCODE_POWER4) == 0)
691 if ((value & 0x8000) == 0)
696 if ((insn & (0x14 << 21)) == (0x04 << 21))
698 else if ((insn & (0x14 << 21)) == (0x10 << 21))
701 return insn | (value & 0xfffc);
705 extract_bdp (unsigned long insn,
711 if ((dialect & PPC_OPCODE_POWER4) == 0)
713 if (((insn & (1 << 21)) == 0) == ((insn & (1 << 15)) == 0))
718 if ((insn & (0x17 << 21)) != (0x07 << 21)
719 && (insn & (0x1d << 21)) != (0x19 << 21))
723 return ((insn & 0xfffc) ^ 0x8000) - 0x8000;
726 /* Check for legal values of a BO field. */
729 valid_bo (long value, int dialect)
731 if ((dialect & PPC_OPCODE_POWER4) == 0)
733 /* Certain encodings have bits that are required to be zero.
734 These are (z must be zero, y may be anything):
741 switch (value & 0x14)
747 return (value & 0x2) == 0;
749 return (value & 0x8) == 0;
751 return value == 0x14;
756 /* Certain encodings have bits that are required to be zero.
757 These are (z must be zero, a & t may be anything):
768 if ((value & 0x14) == 0)
769 return (value & 0x1) == 0;
770 else if ((value & 0x14) == 0x14)
771 return value == 0x14;
777 /* The BO field in a B form instruction. Warn about attempts to set
778 the field to an illegal value. */
781 insert_bo (unsigned long insn,
787 && ! valid_bo (value, dialect))
788 *errmsg = _("invalid conditional option");
789 return insn | ((value & 0x1f) << 21);
793 extract_bo (unsigned long insn,
799 value = (insn >> 21) & 0x1f;
801 && ! valid_bo (value, dialect))
806 /* The BO field in a B form instruction when the + or - modifier is
807 used. This is like the BO field, but it must be even. When
808 extracting it, we force it to be even. */
811 insert_boe (unsigned long insn,
818 if (! valid_bo (value, dialect))
819 *errmsg = _("invalid conditional option");
820 else if ((value & 1) != 0)
821 *errmsg = _("attempt to set y bit when using + or - modifier");
823 return insn | ((value & 0x1f) << 21);
827 extract_boe (unsigned long insn,
833 value = (insn >> 21) & 0x1f;
835 && ! valid_bo (value, dialect))
840 /* The DQ field in a DQ form instruction. This is like D, but the
841 lower four bits are forced to zero. */
845 insert_dq (unsigned long insn,
847 int dialect ATTRIBUTE_UNUSED,
848 const char ** errmsg ATTRIBUTE_UNUSED)
850 if ((value & 0xf) != 0 && errmsg != NULL)
851 *errmsg = _("offset not a multiple of 16");
852 return insn | (value & 0xfff0);
857 extract_dq (unsigned long insn,
858 int dialect ATTRIBUTE_UNUSED,
859 int *invalid ATTRIBUTE_UNUSED)
861 return ((insn & 0xfff0) ^ 0x8000) - 0x8000;
865 insert_ev2 (unsigned long insn,
867 int dialect ATTRIBUTE_UNUSED,
868 const char ** errmsg ATTRIBUTE_UNUSED)
870 if ((value & 1) != 0 && errmsg != NULL)
871 *errmsg = _("offset not a multiple of 2");
872 if ((value > 62) != 0 && errmsg != NULL)
873 *errmsg = _("offset greater than 62");
874 return insn | ((value & 0x3e) << 10);
878 extract_ev2 (unsigned long insn,
879 int dialect ATTRIBUTE_UNUSED,
880 int *invalid ATTRIBUTE_UNUSED)
882 return (insn >> 10) & 0x3e;
886 insert_ev4 (unsigned long insn,
888 int dialect ATTRIBUTE_UNUSED,
889 const char **errmsg ATTRIBUTE_UNUSED)
891 if ((value & 3) != 0 && errmsg != NULL)
892 *errmsg = _("offset not a multiple of 4");
893 if ((value > 124) != 0 && errmsg != NULL)
894 *errmsg = _("offset greater than 124");
895 return insn | ((value & 0x7c) << 9);
899 extract_ev4 (unsigned long insn,
900 int dialect ATTRIBUTE_UNUSED,
901 int *invalid ATTRIBUTE_UNUSED)
903 return (insn >> 9) & 0x7c;
907 insert_ev8 (unsigned long insn,
909 int dialect ATTRIBUTE_UNUSED,
910 const char **errmsg ATTRIBUTE_UNUSED)
912 if ((value & 7) != 0 && errmsg != NULL)
913 *errmsg = _("offset not a multiple of 8");
914 if ((value > 248) != 0 && errmsg != NULL)
915 *errmsg = _("offset greater than 248");
916 return insn | ((value & 0xf8) << 8);
920 extract_ev8 (unsigned long insn,
921 int dialect ATTRIBUTE_UNUSED,
922 int * invalid ATTRIBUTE_UNUSED)
924 return (insn >> 8) & 0xf8;
927 /* The DS field in a DS form instruction. This is like D, but the
928 lower two bits are forced to zero. */
932 insert_ds (unsigned long insn,
934 int dialect ATTRIBUTE_UNUSED,
937 if ((value & 3) != 0 && errmsg != NULL)
938 *errmsg = _("offset not a multiple of 4");
939 return insn | (value & 0xfffc);
944 extract_ds (unsigned long insn,
945 int dialect ATTRIBUTE_UNUSED,
946 int *invalid ATTRIBUTE_UNUSED)
948 return ((insn & 0xfffc) ^ 0x8000) - 0x8000;
951 /* The DE field in a DE form instruction. */
955 insert_de (unsigned long insn,
957 int dialect ATTRIBUTE_UNUSED,
960 if ((value > 2047 || value < -2048) && errmsg != NULL)
961 *errmsg = _("offset not between -2048 and 2047");
962 return insn | ((value << 4) & 0xfff0);
967 extract_de (unsigned long insn,
968 int dialect ATTRIBUTE_UNUSED,
969 int *invalid ATTRIBUTE_UNUSED)
971 return (insn & 0xfff0) >> 4;
974 /* The DES field in a DES form instruction. */
978 insert_des (unsigned long insn,
980 int dialect ATTRIBUTE_UNUSED,
983 if ((value > 8191 || value < -8192) && errmsg != NULL)
984 *errmsg = _("offset not between -8192 and 8191");
985 else if ((value & 3) != 0 && errmsg != NULL)
986 *errmsg = _("offset not a multiple of 4");
987 return insn | ((value << 2) & 0xfff0);
992 extract_des (unsigned long insn,
993 int dialect ATTRIBUTE_UNUSED,
994 int *invalid ATTRIBUTE_UNUSED)
996 return (((insn >> 2) & 0x3ffc) ^ 0x2000) - 0x2000;
999 /* FXM mask in mfcr and mtcrf instructions. */
1001 static unsigned long
1002 insert_fxm (unsigned long insn,
1005 const char **errmsg)
1007 /* If the optional field on mfcr is missing that means we want to use
1008 the old form of the instruction that moves the whole cr. In that
1009 case we'll have VALUE zero. There doesn't seem to be a way to
1010 distinguish this from the case where someone writes mfcr %r3,0. */
1014 /* If only one bit of the FXM field is set, we can use the new form
1015 of the instruction, which is faster. */
1016 else if ((dialect & PPC_OPCODE_POWER4) != 0 && (value & -value) == value)
1019 /* Any other value on mfcr is an error. */
1020 else if ((insn & (0x3ff << 1)) == 19 << 1)
1023 *errmsg = _("ignoring invalid mfcr mask");
1027 return insn | ((value & 0xff) << 12);
1031 extract_fxm (unsigned long insn,
1035 long mask = (insn >> 12) & 0xff;
1037 /* Is this a Power4 insn? */
1038 if ((insn & (1 << 20)) != 0)
1040 if ((dialect & PPC_OPCODE_POWER4) == 0)
1042 if (invalid != NULL)
1047 /* Exactly one bit of MASK should be set. */
1048 if ((mask == 0 || (mask & -mask) != mask) && invalid != NULL)
1053 /* Check that non-power4 form of mfcr has a zero MASK. */
1054 else if ((insn & (0x3ff << 1)) == 19 << 1)
1056 if (mask != 0 && invalid != NULL)
1063 /* The LI field in an I form instruction. The lower two bits are
1067 static unsigned long
1068 insert_li (unsigned long insn,
1070 int dialect ATTRIBUTE_UNUSED,
1071 const char **errmsg)
1073 if ((value & 3) != 0 && errmsg != NULL)
1074 *errmsg = _("ignoring least significant bits in branch offset");
1075 return insn | (value & 0x3fffffc);
1080 extract_li (unsigned long insn,
1081 int dialect ATTRIBUTE_UNUSED,
1082 int *invalid ATTRIBUTE_UNUSED)
1084 return ((insn & 0x3fffffc) ^ 0x2000000) - 0x2000000;
1087 /* The MB and ME fields in an M form instruction expressed as a single
1088 operand which is itself a bitmask. The extraction function always
1089 marks it as invalid, since we never want to recognize an
1090 instruction which uses a field of this type. */
1092 static unsigned long
1093 insert_mbe (unsigned long insn,
1095 int dialect ATTRIBUTE_UNUSED,
1096 const char **errmsg)
1098 unsigned long uval, mask;
1099 int mb, me, mx, count, last;
1106 *errmsg = _("illegal bitmask");
1112 if ((uval & 1) != 0)
1118 /* mb: location of last 0->1 transition */
1119 /* me: location of last 1->0 transition */
1120 /* count: # transitions */
1122 for (mx = 0, mask = 1 << 31; mx < 32; ++mx, mask >>= 1)
1124 if ((uval & mask) && !last)
1130 else if (!(uval & mask) && last)
1140 if (count != 2 && (count != 0 || ! last))
1143 *errmsg = _("illegal bitmask");
1146 return insn | (mb << 6) | ((me - 1) << 1);
1150 extract_mbe (unsigned long insn,
1151 int dialect ATTRIBUTE_UNUSED,
1158 if (invalid != NULL)
1161 mb = (insn >> 6) & 0x1f;
1162 me = (insn >> 1) & 0x1f;
1166 for (i = mb; i <= me; i++)
1167 ret |= 1 << (31 - i);
1169 else if (mb == me + 1)
1171 else /* (mb > me + 1) */
1174 for (i = me + 1; i < mb; i++)
1175 ret &= ~ (1 << (31 - i));
1180 /* The MB or ME field in an MD or MDS form instruction. The high bit
1181 is wrapped to the low end. */
1184 static unsigned long
1185 insert_mb6 (unsigned long insn,
1187 int dialect ATTRIBUTE_UNUSED,
1188 const char **errmsg ATTRIBUTE_UNUSED)
1190 return insn | ((value & 0x1f) << 6) | (value & 0x20);
1195 extract_mb6 (unsigned long insn,
1196 int dialect ATTRIBUTE_UNUSED,
1197 int *invalid ATTRIBUTE_UNUSED)
1199 return ((insn >> 6) & 0x1f) | (insn & 0x20);
1202 /* The NB field in an X form instruction. The value 32 is stored as
1205 static unsigned long
1206 insert_nb (unsigned long insn,
1208 int dialect ATTRIBUTE_UNUSED,
1209 const char **errmsg)
1211 if (value < 0 || value > 32)
1212 *errmsg = _("value out of range");
1215 return insn | ((value & 0x1f) << 11);
1220 extract_nb (unsigned long insn,
1221 int dialect ATTRIBUTE_UNUSED,
1222 int *invalid ATTRIBUTE_UNUSED)
1226 ret = (insn >> 11) & 0x1f;
1232 /* The NSI field in a D form instruction. This is the same as the SI
1233 field, only negated. The extraction function always marks it as
1234 invalid, since we never want to recognize an instruction which uses
1235 a field of this type. */
1238 static unsigned long
1239 insert_nsi (unsigned long insn,
1241 int dialect ATTRIBUTE_UNUSED,
1242 const char **errmsg ATTRIBUTE_UNUSED)
1244 return insn | (-value & 0xffff);
1248 extract_nsi (unsigned long insn,
1249 int dialect ATTRIBUTE_UNUSED,
1252 if (invalid != NULL)
1254 return -(((insn & 0xffff) ^ 0x8000) - 0x8000);
1257 /* The RA field in a D or X form instruction which is an updating
1258 load, which means that the RA field may not be zero and may not
1259 equal the RT field. */
1261 static unsigned long
1262 insert_ral (unsigned long insn,
1264 int dialect ATTRIBUTE_UNUSED,
1265 const char **errmsg)
1268 || (unsigned long) value == ((insn >> 21) & 0x1f))
1269 *errmsg = "invalid register operand when updating";
1270 return insn | ((value & 0x1f) << 16);
1273 /* The RA field in an lmw instruction, which has special value
1276 static unsigned long
1277 insert_ram (unsigned long insn,
1279 int dialect ATTRIBUTE_UNUSED,
1280 const char **errmsg)
1282 if ((unsigned long) value >= ((insn >> 21) & 0x1f))
1283 *errmsg = _("index register in load range");
1284 return insn | ((value & 0x1f) << 16);
1287 /* The RA field in the DQ form lq instruction, which has special
1288 value restrictions. */
1291 static unsigned long
1292 insert_raq (unsigned long insn,
1294 int dialect ATTRIBUTE_UNUSED,
1295 const char **errmsg)
1297 long rtvalue = (insn & RT_MASK) >> 21;
1299 if (value == rtvalue && errmsg != NULL)
1300 *errmsg = _("source and target register operands must be different");
1301 return insn | ((value & 0x1f) << 16);
1304 /* The RA field in a D or X form instruction which is an updating
1305 store or an updating floating point load, which means that the RA
1306 field may not be zero. */
1308 static unsigned long
1309 insert_ras (unsigned long insn,
1311 int dialect ATTRIBUTE_UNUSED,
1312 const char **errmsg)
1315 *errmsg = _("invalid register operand when updating");
1316 return insn | ((value & 0x1f) << 16);
1319 /* The RB field in an X form instruction when it must be the same as
1320 the RS field in the instruction. This is used for extended
1321 mnemonics like mr. This operand is marked FAKE. The insertion
1322 function just copies the BT field into the BA field, and the
1323 extraction function just checks that the fields are the same. */
1326 static unsigned long
1327 insert_rbs (unsigned long insn,
1328 long value ATTRIBUTE_UNUSED,
1329 int dialect ATTRIBUTE_UNUSED,
1330 const char **errmsg ATTRIBUTE_UNUSED)
1332 return insn | (((insn >> 21) & 0x1f) << 11);
1336 extract_rbs (unsigned long insn,
1337 int dialect ATTRIBUTE_UNUSED,
1341 && ((insn >> 21) & 0x1f) != ((insn >> 11) & 0x1f))
1346 /* The RT field of the DQ form lq instruction, which has special
1347 value restrictions. */
1350 static unsigned long
1351 insert_rtq (unsigned long insn,
1353 int dialect ATTRIBUTE_UNUSED,
1354 const char **errmsg)
1356 if ((value & 1) != 0 && errmsg != NULL)
1357 *errmsg = _("target register operand must be even");
1358 return insn | ((value & 0x1f) << 21);
1361 /* The RS field of the DS form stq instruction, which has special
1362 value restrictions. */
1365 static unsigned long
1366 insert_rsq (unsigned long insn,
1367 long value ATTRIBUTE_UNUSED,
1368 int dialect ATTRIBUTE_UNUSED,
1369 const char **errmsg)
1371 if ((value & 1) != 0 && errmsg != NULL)
1372 *errmsg = _("source register operand must be even");
1373 return insn | ((value & 0x1f) << 21);
1376 /* The SH field in an MD form instruction. This is split. */
1379 static unsigned long
1380 insert_sh6 (unsigned long insn,
1382 int dialect ATTRIBUTE_UNUSED,
1383 const char **errmsg ATTRIBUTE_UNUSED)
1385 return insn | ((value & 0x1f) << 11) | ((value & 0x20) >> 4);
1390 extract_sh6 (unsigned long insn,
1391 int dialect ATTRIBUTE_UNUSED,
1392 int *invalid ATTRIBUTE_UNUSED)
1394 return ((insn >> 11) & 0x1f) | ((insn << 4) & 0x20);
1397 /* The SPR field in an XFX form instruction. This is flipped--the
1398 lower 5 bits are stored in the upper 5 and vice- versa. */
1400 static unsigned long
1401 insert_spr (unsigned long insn,
1403 int dialect ATTRIBUTE_UNUSED,
1404 const char **errmsg ATTRIBUTE_UNUSED)
1406 return insn | ((value & 0x1f) << 16) | ((value & 0x3e0) << 6);
1410 extract_spr (unsigned long insn,
1411 int dialect ATTRIBUTE_UNUSED,
1412 int *invalid ATTRIBUTE_UNUSED)
1414 return ((insn >> 16) & 0x1f) | ((insn >> 6) & 0x3e0);
1417 /* The TBR field in an XFX instruction. This is just like SPR, but it
1418 is optional. When TBR is omitted, it must be inserted as 268 (the
1419 magic number of the TB register). These functions treat 0
1420 (indicating an omitted optional operand) as 268. This means that
1421 ``mftb 4,0'' is not handled correctly. This does not matter very
1422 much, since the architecture manual does not define mftb as
1423 accepting any values other than 268 or 269. */
1427 static unsigned long
1428 insert_tbr (unsigned long insn,
1430 int dialect ATTRIBUTE_UNUSED,
1431 const char **errmsg ATTRIBUTE_UNUSED)
1435 return insn | ((value & 0x1f) << 16) | ((value & 0x3e0) << 6);
1439 extract_tbr (unsigned long insn,
1440 int dialect ATTRIBUTE_UNUSED,
1441 int *invalid ATTRIBUTE_UNUSED)
1445 ret = ((insn >> 16) & 0x1f) | ((insn >> 6) & 0x3e0);
1451 /* Macros used to form opcodes. */
1453 /* The main opcode. */
1454 #define OP(x) ((((unsigned long)(x)) & 0x3f) << 26)
1455 #define OP_MASK OP (0x3f)
1457 /* The main opcode combined with a trap code in the TO field of a D
1458 form instruction. Used for extended mnemonics for the trap
1460 #define OPTO(x,to) (OP (x) | ((((unsigned long)(to)) & 0x1f) << 21))
1461 #define OPTO_MASK (OP_MASK | TO_MASK)
1463 /* The main opcode combined with a comparison size bit in the L field
1464 of a D form or X form instruction. Used for extended mnemonics for
1465 the comparison instructions. */
1466 #define OPL(x,l) (OP (x) | ((((unsigned long)(l)) & 1) << 21))
1467 #define OPL_MASK OPL (0x3f,1)
1469 /* An A form instruction. */
1470 #define A(op, xop, rc) (OP (op) | ((((unsigned long)(xop)) & 0x1f) << 1) | (((unsigned long)(rc)) & 1))
1471 #define A_MASK A (0x3f, 0x1f, 1)
1473 /* An A_MASK with the FRB field fixed. */
1474 #define AFRB_MASK (A_MASK | FRB_MASK)
1476 /* An A_MASK with the FRC field fixed. */
1477 #define AFRC_MASK (A_MASK | FRC_MASK)
1479 /* An A_MASK with the FRA and FRC fields fixed. */
1480 #define AFRAFRC_MASK (A_MASK | FRA_MASK | FRC_MASK)
1482 /* A B form instruction. */
1483 #define B(op, aa, lk) (OP (op) | ((((unsigned long)(aa)) & 1) << 1) | ((lk) & 1))
1484 #define B_MASK B (0x3f, 1, 1)
1486 /* A B form instruction setting the BO field. */
1487 #define BBO(op, bo, aa, lk) (B ((op), (aa), (lk)) | ((((unsigned long)(bo)) & 0x1f) << 21))
1488 #define BBO_MASK BBO (0x3f, 0x1f, 1, 1)
1490 /* A BBO_MASK with the y bit of the BO field removed. This permits
1491 matching a conditional branch regardless of the setting of the y
1492 bit. Similarly for the 'at' bits used for power4 branch hints. */
1493 #define Y_MASK (((unsigned long) 1) << 21)
1494 #define AT1_MASK (((unsigned long) 3) << 21)
1495 #define AT2_MASK (((unsigned long) 9) << 21)
1496 #define BBOY_MASK (BBO_MASK &~ Y_MASK)
1497 #define BBOAT_MASK (BBO_MASK &~ AT1_MASK)
1499 /* A B form instruction setting the BO field and the condition bits of
1501 #define BBOCB(op, bo, cb, aa, lk) \
1502 (BBO ((op), (bo), (aa), (lk)) | ((((unsigned long)(cb)) & 0x3) << 16))
1503 #define BBOCB_MASK BBOCB (0x3f, 0x1f, 0x3, 1, 1)
1505 /* A BBOCB_MASK with the y bit of the BO field removed. */
1506 #define BBOYCB_MASK (BBOCB_MASK &~ Y_MASK)
1507 #define BBOATCB_MASK (BBOCB_MASK &~ AT1_MASK)
1508 #define BBOAT2CB_MASK (BBOCB_MASK &~ AT2_MASK)
1510 /* A BBOYCB_MASK in which the BI field is fixed. */
1511 #define BBOYBI_MASK (BBOYCB_MASK | BI_MASK)
1512 #define BBOATBI_MASK (BBOAT2CB_MASK | BI_MASK)
1514 /* An Context form instruction. */
1515 #define CTX(op, xop) (OP (op) | (((unsigned long)(xop)) & 0x7))
1516 #define CTX_MASK CTX(0x3f, 0x7)
1518 /* An User Context form instruction. */
1519 #define UCTX(op, xop) (OP (op) | (((unsigned long)(xop)) & 0x1f))
1520 #define UCTX_MASK UCTX(0x3f, 0x1f)
1522 /* The main opcode mask with the RA field clear. */
1523 #define DRA_MASK (OP_MASK | RA_MASK)
1525 /* A DS form instruction. */
1526 #define DSO(op, xop) (OP (op) | ((xop) & 0x3))
1527 #define DS_MASK DSO (0x3f, 3)
1529 /* A DE form instruction. */
1530 #define DEO(op, xop) (OP (op) | ((xop) & 0xf))
1531 #define DE_MASK DEO (0x3e, 0xf)
1533 /* An EVSEL form instruction. */
1534 #define EVSEL(op, xop) (OP (op) | (((unsigned long)(xop)) & 0xff) << 3)
1535 #define EVSEL_MASK EVSEL(0x3f, 0xff)
1537 /* An M form instruction. */
1538 #define M(op, rc) (OP (op) | ((rc) & 1))
1539 #define M_MASK M (0x3f, 1)
1541 /* An M form instruction with the ME field specified. */
1542 #define MME(op, me, rc) (M ((op), (rc)) | ((((unsigned long)(me)) & 0x1f) << 1))
1544 /* An M_MASK with the MB and ME fields fixed. */
1545 #define MMBME_MASK (M_MASK | MB_MASK | ME_MASK)
1547 /* An M_MASK with the SH and ME fields fixed. */
1548 #define MSHME_MASK (M_MASK | SH_MASK | ME_MASK)
1550 /* An MD form instruction. */
1551 #define MD(op, xop, rc) (OP (op) | ((((unsigned long)(xop)) & 0x7) << 2) | ((rc) & 1))
1552 #define MD_MASK MD (0x3f, 0x7, 1)
1554 /* An MD_MASK with the MB field fixed. */
1555 #define MDMB_MASK (MD_MASK | MB6_MASK)
1557 /* An MD_MASK with the SH field fixed. */
1558 #define MDSH_MASK (MD_MASK | SH6_MASK)
1560 /* An MDS form instruction. */
1561 #define MDS(op, xop, rc) (OP (op) | ((((unsigned long)(xop)) & 0xf) << 1) | ((rc) & 1))
1562 #define MDS_MASK MDS (0x3f, 0xf, 1)
1564 /* An MDS_MASK with the MB field fixed. */
1565 #define MDSMB_MASK (MDS_MASK | MB6_MASK)
1567 /* An SC form instruction. */
1568 #define SC(op, sa, lk) (OP (op) | ((((unsigned long)(sa)) & 1) << 1) | ((lk) & 1))
1569 #define SC_MASK (OP_MASK | (((unsigned long)0x3ff) << 16) | (((unsigned long)1) << 1) | 1)
1571 /* An VX form instruction. */
1572 #define VX(op, xop) (OP (op) | (((unsigned long)(xop)) & 0x7ff))
1574 /* The mask for an VX form instruction. */
1575 #define VX_MASK VX(0x3f, 0x7ff)
1577 /* An VA form instruction. */
1578 #define VXA(op, xop) (OP (op) | (((unsigned long)(xop)) & 0x03f))
1580 /* The mask for an VA form instruction. */
1581 #define VXA_MASK VXA(0x3f, 0x3f)
1583 /* An VXR form instruction. */
1584 #define VXR(op, xop, rc) (OP (op) | (((rc) & 1) << 10) | (((unsigned long)(xop)) & 0x3ff))
1586 /* The mask for a VXR form instruction. */
1587 #define VXR_MASK VXR(0x3f, 0x3ff, 1)
1589 /* An X form instruction. */
1590 #define X(op, xop) (OP (op) | ((((unsigned long)(xop)) & 0x3ff) << 1))
1592 /* An X form instruction with the RC bit specified. */
1593 #define XRC(op, xop, rc) (X ((op), (xop)) | ((rc) & 1))
1595 /* The mask for an X form instruction. */
1596 #define X_MASK XRC (0x3f, 0x3ff, 1)
1598 /* An X_MASK with the RA field fixed. */
1599 #define XRA_MASK (X_MASK | RA_MASK)
1601 /* An X_MASK with the RB field fixed. */
1602 #define XRB_MASK (X_MASK | RB_MASK)
1604 /* An X_MASK with the RT field fixed. */
1605 #define XRT_MASK (X_MASK | RT_MASK)
1607 /* An X_MASK with the RA and RB fields fixed. */
1608 #define XRARB_MASK (X_MASK | RA_MASK | RB_MASK)
1610 /* An XRARB_MASK, but with the L bit clear. */
1611 #define XRLARB_MASK (XRARB_MASK & ~((unsigned long) 1 << 16))
1613 /* An X_MASK with the RT and RA fields fixed. */
1614 #define XRTRA_MASK (X_MASK | RT_MASK | RA_MASK)
1616 /* An XRTRA_MASK, but with L bit clear. */
1617 #define XRTLRA_MASK (XRTRA_MASK & ~((unsigned long) 1 << 21))
1619 /* An X form comparison instruction. */
1620 #define XCMPL(op, xop, l) (X ((op), (xop)) | ((((unsigned long)(l)) & 1) << 21))
1622 /* The mask for an X form comparison instruction. */
1623 #define XCMP_MASK (X_MASK | (((unsigned long)1) << 22))
1625 /* The mask for an X form comparison instruction with the L field
1627 #define XCMPL_MASK (XCMP_MASK | (((unsigned long)1) << 21))
1629 /* An X form trap instruction with the TO field specified. */
1630 #define XTO(op, xop, to) (X ((op), (xop)) | ((((unsigned long)(to)) & 0x1f) << 21))
1631 #define XTO_MASK (X_MASK | TO_MASK)
1633 /* An X form tlb instruction with the SH field specified. */
1634 #define XTLB(op, xop, sh) (X ((op), (xop)) | ((((unsigned long)(sh)) & 0x1f) << 11))
1635 #define XTLB_MASK (X_MASK | SH_MASK)
1637 /* An X form sync instruction. */
1638 #define XSYNC(op, xop, l) (X ((op), (xop)) | ((((unsigned long)(l)) & 3) << 21))
1640 /* An X form sync instruction with everything filled in except the LS field. */
1641 #define XSYNC_MASK (0xff9fffff)
1643 /* An X form AltiVec dss instruction. */
1644 #define XDSS(op, xop, a) (X ((op), (xop)) | ((((unsigned long)(a)) & 1) << 25))
1645 #define XDSS_MASK XDSS(0x3f, 0x3ff, 1)
1647 /* An XFL form instruction. */
1648 #define XFL(op, xop, rc) (OP (op) | ((((unsigned long)(xop)) & 0x3ff) << 1) | (((unsigned long)(rc)) & 1))
1649 #define XFL_MASK (XFL (0x3f, 0x3ff, 1) | (((unsigned long)1) << 25) | (((unsigned long)1) << 16))
1651 /* An X form isel instruction. */
1652 #define XISEL(op, xop) (OP (op) | ((((unsigned long)(xop)) & 0x1f) << 1))
1653 #define XISEL_MASK XISEL(0x3f, 0x1f)
1655 /* An XL form instruction with the LK field set to 0. */
1656 #define XL(op, xop) (OP (op) | ((((unsigned long)(xop)) & 0x3ff) << 1))
1658 /* An XL form instruction which uses the LK field. */
1659 #define XLLK(op, xop, lk) (XL ((op), (xop)) | ((lk) & 1))
1661 /* The mask for an XL form instruction. */
1662 #define XL_MASK XLLK (0x3f, 0x3ff, 1)
1664 /* An XL form instruction which explicitly sets the BO field. */
1665 #define XLO(op, bo, xop, lk) \
1666 (XLLK ((op), (xop), (lk)) | ((((unsigned long)(bo)) & 0x1f) << 21))
1667 #define XLO_MASK (XL_MASK | BO_MASK)
1669 /* An XL form instruction which explicitly sets the y bit of the BO
1671 #define XLYLK(op, xop, y, lk) (XLLK ((op), (xop), (lk)) | ((((unsigned long)(y)) & 1) << 21))
1672 #define XLYLK_MASK (XL_MASK | Y_MASK)
1674 /* An XL form instruction which sets the BO field and the condition
1675 bits of the BI field. */
1676 #define XLOCB(op, bo, cb, xop, lk) \
1677 (XLO ((op), (bo), (xop), (lk)) | ((((unsigned long)(cb)) & 3) << 16))
1678 #define XLOCB_MASK XLOCB (0x3f, 0x1f, 0x3, 0x3ff, 1)
1680 /* An XL_MASK or XLYLK_MASK or XLOCB_MASK with the BB field fixed. */
1681 #define XLBB_MASK (XL_MASK | BB_MASK)
1682 #define XLYBB_MASK (XLYLK_MASK | BB_MASK)
1683 #define XLBOCBBB_MASK (XLOCB_MASK | BB_MASK)
1685 /* An XL_MASK with the BO and BB fields fixed. */
1686 #define XLBOBB_MASK (XL_MASK | BO_MASK | BB_MASK)
1688 /* An XL_MASK with the BO, BI and BB fields fixed. */
1689 #define XLBOBIBB_MASK (XL_MASK | BO_MASK | BI_MASK | BB_MASK)
1691 /* An XO form instruction. */
1692 #define XO(op, xop, oe, rc) \
1693 (OP (op) | ((((unsigned long)(xop)) & 0x1ff) << 1) | ((((unsigned long)(oe)) & 1) << 10) | (((unsigned long)(rc)) & 1))
1694 #define XO_MASK XO (0x3f, 0x1ff, 1, 1)
1696 /* An XO_MASK with the RB field fixed. */
1697 #define XORB_MASK (XO_MASK | RB_MASK)
1699 /* An XS form instruction. */
1700 #define XS(op, xop, rc) (OP (op) | ((((unsigned long)(xop)) & 0x1ff) << 2) | (((unsigned long)(rc)) & 1))
1701 #define XS_MASK XS (0x3f, 0x1ff, 1)
1703 /* A mask for the FXM version of an XFX form instruction. */
1704 #define XFXFXM_MASK (X_MASK | (1 << 11))
1706 /* An XFX form instruction with the FXM field filled in. */
1707 #define XFXM(op, xop, fxm) \
1708 (X ((op), (xop)) | ((((unsigned long)(fxm)) & 0xff) << 12))
1710 /* An XFX form instruction with the SPR field filled in. */
1711 #define XSPR(op, xop, spr) \
1712 (X ((op), (xop)) | ((((unsigned long)(spr)) & 0x1f) << 16) | ((((unsigned long)(spr)) & 0x3e0) << 6))
1713 #define XSPR_MASK (X_MASK | SPR_MASK)
1715 /* An XFX form instruction with the SPR field filled in except for the
1717 #define XSPRBAT_MASK (XSPR_MASK &~ SPRBAT_MASK)
1719 /* An XFX form instruction with the SPR field filled in except for the
1721 #define XSPRG_MASK (XSPR_MASK &~ SPRG_MASK)
1723 /* An X form instruction with everything filled in except the E field. */
1724 #define XE_MASK (0xffff7fff)
1726 /* An X form user context instruction. */
1727 #define XUC(op, xop) (OP (op) | (((unsigned long)(xop)) & 0x1f))
1728 #define XUC_MASK XUC(0x3f, 0x1f)
1730 /* The BO encodings used in extended conditional branch mnemonics. */
1731 #define BODNZF (0x0)
1732 #define BODNZFP (0x1)
1734 #define BODZFP (0x3)
1735 #define BODNZT (0x8)
1736 #define BODNZTP (0x9)
1738 #define BODZTP (0xb)
1749 #define BODNZ (0x10)
1750 #define BODNZP (0x11)
1752 #define BODZP (0x13)
1753 #define BODNZM4 (0x18)
1754 #define BODNZP4 (0x19)
1755 #define BODZM4 (0x1a)
1756 #define BODZP4 (0x1b)
1760 /* The BI condition bit encodings used in extended conditional branch
1767 /* The TO encodings used in extended trap mnemonics. */
1784 /* Smaller names for the flags so each entry in the opcodes table will
1785 fit on a single line. */
1787 #define PPC PPC_OPCODE_PPC | PPC_OPCODE_ANY
1788 #define PPCCOM PPC_OPCODE_PPC | PPC_OPCODE_COMMON | PPC_OPCODE_ANY
1789 #define NOPOWER4 PPC_OPCODE_NOPOWER4 | PPCCOM
1790 #define POWER4 PPC_OPCODE_POWER4 | PPCCOM
1791 #define PPC32 PPC_OPCODE_32 | PPC_OPCODE_PPC | PPC_OPCODE_ANY
1792 #define PPC64 PPC_OPCODE_64 | PPC_OPCODE_PPC | PPC_OPCODE_ANY
1793 #define PPCONLY PPC_OPCODE_PPC
1794 #define PPC403 PPC_OPCODE_403
1795 #define PPC405 PPC403
1798 #define PPCVEC PPC_OPCODE_ALTIVEC | PPC_OPCODE_ANY | PPC_OPCODE_PPC
1799 #define POWER PPC_OPCODE_POWER | PPC_OPCODE_ANY
1800 #define POWER2 PPC_OPCODE_POWER | PPC_OPCODE_POWER2 | PPC_OPCODE_ANY
1801 #define PPCPWR2 PPC_OPCODE_PPC | PPC_OPCODE_POWER | PPC_OPCODE_POWER2 | PPC_OPCODE_ANY
1802 #define POWER32 PPC_OPCODE_POWER | PPC_OPCODE_ANY | PPC_OPCODE_32
1803 #define COM PPC_OPCODE_POWER | PPC_OPCODE_PPC | PPC_OPCODE_COMMON | PPC_OPCODE_ANY
1804 #define COM32 PPC_OPCODE_POWER | PPC_OPCODE_PPC | PPC_OPCODE_COMMON | PPC_OPCODE_ANY | PPC_OPCODE_32
1805 #define M601 PPC_OPCODE_POWER | PPC_OPCODE_601 | PPC_OPCODE_ANY
1806 #define PWRCOM PPC_OPCODE_POWER | PPC_OPCODE_601 | PPC_OPCODE_COMMON | PPC_OPCODE_ANY
1807 #define MFDEC1 PPC_OPCODE_POWER
1808 #define MFDEC2 PPC_OPCODE_PPC | PPC_OPCODE_601 | PPC_OPCODE_BOOKE
1809 #define BOOKE PPC_OPCODE_BOOKE
1810 #define BOOKE64 PPC_OPCODE_BOOKE64
1811 #define CLASSIC PPC_OPCODE_CLASSIC
1812 #define PPCSPE PPC_OPCODE_SPE
1813 #define PPCISEL PPC_OPCODE_ISEL
1814 #define PPCEFS PPC_OPCODE_EFS
1815 #define PPCBRLK PPC_OPCODE_BRLOCK
1816 #define PPCPMR PPC_OPCODE_PMR
1817 #define PPCCHLK PPC_OPCODE_CACHELCK
1818 #define PPCCHLK64 PPC_OPCODE_CACHELCK | PPC_OPCODE_BOOKE64
1819 #define PPCRFMCI PPC_OPCODE_RFMCI
1821 /* The opcode table.
1823 The format of the opcode table is:
1825 NAME OPCODE MASK FLAGS { OPERANDS }
1827 NAME is the name of the instruction.
1828 OPCODE is the instruction opcode.
1829 MASK is the opcode mask; this is used to tell the disassembler
1830 which bits in the actual opcode must match OPCODE.
1831 FLAGS are flags indicated what processors support the instruction.
1832 OPERANDS is the list of operands.
1834 The disassembler reads the table in order and prints the first
1835 instruction which matches, so this table is sorted to put more
1836 specific instructions before more general instructions. It is also
1837 sorted by major opcode. */
1839 const struct powerpc_opcode powerpc_opcodes[] = {
1840 { "attn", X(0,256), X_MASK, POWER4, { 0 } },
1841 { "tdlgti", OPTO(2,TOLGT), OPTO_MASK, PPC64, { RA, SI } },
1842 { "tdllti", OPTO(2,TOLLT), OPTO_MASK, PPC64, { RA, SI } },
1843 { "tdeqi", OPTO(2,TOEQ), OPTO_MASK, PPC64, { RA, SI } },
1844 { "tdlgei", OPTO(2,TOLGE), OPTO_MASK, PPC64, { RA, SI } },
1845 { "tdlnli", OPTO(2,TOLNL), OPTO_MASK, PPC64, { RA, SI } },
1846 { "tdllei", OPTO(2,TOLLE), OPTO_MASK, PPC64, { RA, SI } },
1847 { "tdlngi", OPTO(2,TOLNG), OPTO_MASK, PPC64, { RA, SI } },
1848 { "tdgti", OPTO(2,TOGT), OPTO_MASK, PPC64, { RA, SI } },
1849 { "tdgei", OPTO(2,TOGE), OPTO_MASK, PPC64, { RA, SI } },
1850 { "tdnli", OPTO(2,TONL), OPTO_MASK, PPC64, { RA, SI } },
1851 { "tdlti", OPTO(2,TOLT), OPTO_MASK, PPC64, { RA, SI } },
1852 { "tdlei", OPTO(2,TOLE), OPTO_MASK, PPC64, { RA, SI } },
1853 { "tdngi", OPTO(2,TONG), OPTO_MASK, PPC64, { RA, SI } },
1854 { "tdnei", OPTO(2,TONE), OPTO_MASK, PPC64, { RA, SI } },
1855 { "tdi", OP(2), OP_MASK, PPC64, { TO, RA, SI } },
1857 { "twlgti", OPTO(3,TOLGT), OPTO_MASK, PPCCOM, { RA, SI } },
1858 { "tlgti", OPTO(3,TOLGT), OPTO_MASK, PWRCOM, { RA, SI } },
1859 { "twllti", OPTO(3,TOLLT), OPTO_MASK, PPCCOM, { RA, SI } },
1860 { "tllti", OPTO(3,TOLLT), OPTO_MASK, PWRCOM, { RA, SI } },
1861 { "tweqi", OPTO(3,TOEQ), OPTO_MASK, PPCCOM, { RA, SI } },
1862 { "teqi", OPTO(3,TOEQ), OPTO_MASK, PWRCOM, { RA, SI } },
1863 { "twlgei", OPTO(3,TOLGE), OPTO_MASK, PPCCOM, { RA, SI } },
1864 { "tlgei", OPTO(3,TOLGE), OPTO_MASK, PWRCOM, { RA, SI } },
1865 { "twlnli", OPTO(3,TOLNL), OPTO_MASK, PPCCOM, { RA, SI } },
1866 { "tlnli", OPTO(3,TOLNL), OPTO_MASK, PWRCOM, { RA, SI } },
1867 { "twllei", OPTO(3,TOLLE), OPTO_MASK, PPCCOM, { RA, SI } },
1868 { "tllei", OPTO(3,TOLLE), OPTO_MASK, PWRCOM, { RA, SI } },
1869 { "twlngi", OPTO(3,TOLNG), OPTO_MASK, PPCCOM, { RA, SI } },
1870 { "tlngi", OPTO(3,TOLNG), OPTO_MASK, PWRCOM, { RA, SI } },
1871 { "twgti", OPTO(3,TOGT), OPTO_MASK, PPCCOM, { RA, SI } },
1872 { "tgti", OPTO(3,TOGT), OPTO_MASK, PWRCOM, { RA, SI } },
1873 { "twgei", OPTO(3,TOGE), OPTO_MASK, PPCCOM, { RA, SI } },
1874 { "tgei", OPTO(3,TOGE), OPTO_MASK, PWRCOM, { RA, SI } },
1875 { "twnli", OPTO(3,TONL), OPTO_MASK, PPCCOM, { RA, SI } },
1876 { "tnli", OPTO(3,TONL), OPTO_MASK, PWRCOM, { RA, SI } },
1877 { "twlti", OPTO(3,TOLT), OPTO_MASK, PPCCOM, { RA, SI } },
1878 { "tlti", OPTO(3,TOLT), OPTO_MASK, PWRCOM, { RA, SI } },
1879 { "twlei", OPTO(3,TOLE), OPTO_MASK, PPCCOM, { RA, SI } },
1880 { "tlei", OPTO(3,TOLE), OPTO_MASK, PWRCOM, { RA, SI } },
1881 { "twngi", OPTO(3,TONG), OPTO_MASK, PPCCOM, { RA, SI } },
1882 { "tngi", OPTO(3,TONG), OPTO_MASK, PWRCOM, { RA, SI } },
1883 { "twnei", OPTO(3,TONE), OPTO_MASK, PPCCOM, { RA, SI } },
1884 { "tnei", OPTO(3,TONE), OPTO_MASK, PWRCOM, { RA, SI } },
1885 { "twi", OP(3), OP_MASK, PPCCOM, { TO, RA, SI } },
1886 { "ti", OP(3), OP_MASK, PWRCOM, { TO, RA, SI } },
1888 { "macchw", XO(4,172,0,0), XO_MASK, PPC405, { RT, RA, RB } },
1889 { "macchw.", XO(4,172,0,1), XO_MASK, PPC405, { RT, RA, RB } },
1890 { "macchwo", XO(4,172,1,0), XO_MASK, PPC405, { RT, RA, RB } },
1891 { "macchwo.", XO(4,172,1,1), XO_MASK, PPC405, { RT, RA, RB } },
1892 { "macchws", XO(4,236,0,0), XO_MASK, PPC405, { RT, RA, RB } },
1893 { "macchws.", XO(4,236,0,1), XO_MASK, PPC405, { RT, RA, RB } },
1894 { "macchwso", XO(4,236,1,0), XO_MASK, PPC405, { RT, RA, RB } },
1895 { "macchwso.", XO(4,236,1,1), XO_MASK, PPC405, { RT, RA, RB } },
1896 { "macchwsu", XO(4,204,0,0), XO_MASK, PPC405, { RT, RA, RB } },
1897 { "macchwsu.", XO(4,204,0,1), XO_MASK, PPC405, { RT, RA, RB } },
1898 { "macchwsuo", XO(4,204,1,0), XO_MASK, PPC405, { RT, RA, RB } },
1899 { "macchwsuo.", XO(4,204,1,1), XO_MASK, PPC405, { RT, RA, RB } },
1900 { "macchwu", XO(4,140,0,0), XO_MASK, PPC405, { RT, RA, RB } },
1901 { "macchwu.", XO(4,140,0,1), XO_MASK, PPC405, { RT, RA, RB } },
1902 { "macchwuo", XO(4,140,1,0), XO_MASK, PPC405, { RT, RA, RB } },
1903 { "macchwuo.", XO(4,140,1,1), XO_MASK, PPC405, { RT, RA, RB } },
1904 { "machhw", XO(4,44,0,0), XO_MASK, PPC405, { RT, RA, RB } },
1905 { "machhw.", XO(4,44,0,1), XO_MASK, PPC405, { RT, RA, RB } },
1906 { "machhwo", XO(4,44,1,0), XO_MASK, PPC405, { RT, RA, RB } },
1907 { "machhwo.", XO(4,44,1,1), XO_MASK, PPC405, { RT, RA, RB } },
1908 { "machhws", XO(4,108,0,0), XO_MASK, PPC405, { RT, RA, RB } },
1909 { "machhws.", XO(4,108,0,1), XO_MASK, PPC405, { RT, RA, RB } },
1910 { "machhwso", XO(4,108,1,0), XO_MASK, PPC405, { RT, RA, RB } },
1911 { "machhwso.", XO(4,108,1,1), XO_MASK, PPC405, { RT, RA, RB } },
1912 { "machhwsu", XO(4,76,0,0), XO_MASK, PPC405, { RT, RA, RB } },
1913 { "machhwsu.", XO(4,76,0,1), XO_MASK, PPC405, { RT, RA, RB } },
1914 { "machhwsuo", XO(4,76,1,0), XO_MASK, PPC405, { RT, RA, RB } },
1915 { "machhwsuo.", XO(4,76,1,1), XO_MASK, PPC405, { RT, RA, RB } },
1916 { "machhwu", XO(4,12,0,0), XO_MASK, PPC405, { RT, RA, RB } },
1917 { "machhwu.", XO(4,12,0,1), XO_MASK, PPC405, { RT, RA, RB } },
1918 { "machhwuo", XO(4,12,1,0), XO_MASK, PPC405, { RT, RA, RB } },
1919 { "machhwuo.", XO(4,12,1,1), XO_MASK, PPC405, { RT, RA, RB } },
1920 { "maclhw", XO(4,428,0,0), XO_MASK, PPC405, { RT, RA, RB } },
1921 { "maclhw.", XO(4,428,0,1), XO_MASK, PPC405, { RT, RA, RB } },
1922 { "maclhwo", XO(4,428,1,0), XO_MASK, PPC405, { RT, RA, RB } },
1923 { "maclhwo.", XO(4,428,1,1), XO_MASK, PPC405, { RT, RA, RB } },
1924 { "maclhws", XO(4,492,0,0), XO_MASK, PPC405, { RT, RA, RB } },
1925 { "maclhws.", XO(4,492,0,1), XO_MASK, PPC405, { RT, RA, RB } },
1926 { "maclhwso", XO(4,492,1,0), XO_MASK, PPC405, { RT, RA, RB } },
1927 { "maclhwso.", XO(4,492,1,1), XO_MASK, PPC405, { RT, RA, RB } },
1928 { "maclhwsu", XO(4,460,0,0), XO_MASK, PPC405, { RT, RA, RB } },
1929 { "maclhwsu.", XO(4,460,0,1), XO_MASK, PPC405, { RT, RA, RB } },
1930 { "maclhwsuo", XO(4,460,1,0), XO_MASK, PPC405, { RT, RA, RB } },
1931 { "maclhwsuo.", XO(4,460,1,1), XO_MASK, PPC405, { RT, RA, RB } },
1932 { "maclhwu", XO(4,396,0,0), XO_MASK, PPC405, { RT, RA, RB } },
1933 { "maclhwu.", XO(4,396,0,1), XO_MASK, PPC405, { RT, RA, RB } },
1934 { "maclhwuo", XO(4,396,1,0), XO_MASK, PPC405, { RT, RA, RB } },
1935 { "maclhwuo.", XO(4,396,1,1), XO_MASK, PPC405, { RT, RA, RB } },
1936 { "mulchw", XRC(4,168,0), X_MASK, PPC405, { RT, RA, RB } },
1937 { "mulchw.", XRC(4,168,1), X_MASK, PPC405, { RT, RA, RB } },
1938 { "mulchwu", XRC(4,136,0), X_MASK, PPC405, { RT, RA, RB } },
1939 { "mulchwu.", XRC(4,136,1), X_MASK, PPC405, { RT, RA, RB } },
1940 { "mulhhw", XRC(4,40,0), X_MASK, PPC405, { RT, RA, RB } },
1941 { "mulhhw.", XRC(4,40,1), X_MASK, PPC405, { RT, RA, RB } },
1942 { "mulhhwu", XRC(4,8,0), X_MASK, PPC405, { RT, RA, RB } },
1943 { "mulhhwu.", XRC(4,8,1), X_MASK, PPC405, { RT, RA, RB } },
1944 { "mullhw", XRC(4,424,0), X_MASK, PPC405, { RT, RA, RB } },
1945 { "mullhw.", XRC(4,424,1), X_MASK, PPC405, { RT, RA, RB } },
1946 { "mullhwu", XRC(4,392,0), X_MASK, PPC405, { RT, RA, RB } },
1947 { "mullhwu.", XRC(4,392,1), X_MASK, PPC405, { RT, RA, RB } },
1948 { "nmacchw", XO(4,174,0,0), XO_MASK, PPC405, { RT, RA, RB } },
1949 { "nmacchw.", XO(4,174,0,1), XO_MASK, PPC405, { RT, RA, RB } },
1950 { "nmacchwo", XO(4,174,1,0), XO_MASK, PPC405, { RT, RA, RB } },
1951 { "nmacchwo.", XO(4,174,1,1), XO_MASK, PPC405, { RT, RA, RB } },
1952 { "nmacchws", XO(4,238,0,0), XO_MASK, PPC405, { RT, RA, RB } },
1953 { "nmacchws.", XO(4,238,0,1), XO_MASK, PPC405, { RT, RA, RB } },
1954 { "nmacchwso", XO(4,238,1,0), XO_MASK, PPC405, { RT, RA, RB } },
1955 { "nmacchwso.", XO(4,238,1,1), XO_MASK, PPC405, { RT, RA, RB } },
1956 { "nmachhw", XO(4,46,0,0), XO_MASK, PPC405, { RT, RA, RB } },
1957 { "nmachhw.", XO(4,46,0,1), XO_MASK, PPC405, { RT, RA, RB } },
1958 { "nmachhwo", XO(4,46,1,0), XO_MASK, PPC405, { RT, RA, RB } },
1959 { "nmachhwo.", XO(4,46,1,1), XO_MASK, PPC405, { RT, RA, RB } },
1960 { "nmachhws", XO(4,110,0,0), XO_MASK, PPC405, { RT, RA, RB } },
1961 { "nmachhws.", XO(4,110,0,1), XO_MASK, PPC405, { RT, RA, RB } },
1962 { "nmachhwso", XO(4,110,1,0), XO_MASK, PPC405, { RT, RA, RB } },
1963 { "nmachhwso.", XO(4,110,1,1), XO_MASK, PPC405, { RT, RA, RB } },
1964 { "nmaclhw", XO(4,430,0,0), XO_MASK, PPC405, { RT, RA, RB } },
1965 { "nmaclhw.", XO(4,430,0,1), XO_MASK, PPC405, { RT, RA, RB } },
1966 { "nmaclhwo", XO(4,430,1,0), XO_MASK, PPC405, { RT, RA, RB } },
1967 { "nmaclhwo.", XO(4,430,1,1), XO_MASK, PPC405, { RT, RA, RB } },
1968 { "nmaclhws", XO(4,494,0,0), XO_MASK, PPC405, { RT, RA, RB } },
1969 { "nmaclhws.", XO(4,494,0,1), XO_MASK, PPC405, { RT, RA, RB } },
1970 { "nmaclhwso", XO(4,494,1,0), XO_MASK, PPC405, { RT, RA, RB } },
1971 { "nmaclhwso.", XO(4,494,1,1), XO_MASK, PPC405, { RT, RA, RB } },
1972 { "mfvscr", VX(4, 1540), VX_MASK, PPCVEC, { VD } },
1973 { "mtvscr", VX(4, 1604), VX_MASK, PPCVEC, { VB } },
1974 { "vaddcuw", VX(4, 384), VX_MASK, PPCVEC, { VD, VA, VB } },
1975 { "vaddfp", VX(4, 10), VX_MASK, PPCVEC, { VD, VA, VB } },
1976 { "vaddsbs", VX(4, 768), VX_MASK, PPCVEC, { VD, VA, VB } },
1977 { "vaddshs", VX(4, 832), VX_MASK, PPCVEC, { VD, VA, VB } },
1978 { "vaddsws", VX(4, 896), VX_MASK, PPCVEC, { VD, VA, VB } },
1979 { "vaddubm", VX(4, 0), VX_MASK, PPCVEC, { VD, VA, VB } },
1980 { "vaddubs", VX(4, 512), VX_MASK, PPCVEC, { VD, VA, VB } },
1981 { "vadduhm", VX(4, 64), VX_MASK, PPCVEC, { VD, VA, VB } },
1982 { "vadduhs", VX(4, 576), VX_MASK, PPCVEC, { VD, VA, VB } },
1983 { "vadduwm", VX(4, 128), VX_MASK, PPCVEC, { VD, VA, VB } },
1984 { "vadduws", VX(4, 640), VX_MASK, PPCVEC, { VD, VA, VB } },
1985 { "vand", VX(4, 1028), VX_MASK, PPCVEC, { VD, VA, VB } },
1986 { "vandc", VX(4, 1092), VX_MASK, PPCVEC, { VD, VA, VB } },
1987 { "vavgsb", VX(4, 1282), VX_MASK, PPCVEC, { VD, VA, VB } },
1988 { "vavgsh", VX(4, 1346), VX_MASK, PPCVEC, { VD, VA, VB } },
1989 { "vavgsw", VX(4, 1410), VX_MASK, PPCVEC, { VD, VA, VB } },
1990 { "vavgub", VX(4, 1026), VX_MASK, PPCVEC, { VD, VA, VB } },
1991 { "vavguh", VX(4, 1090), VX_MASK, PPCVEC, { VD, VA, VB } },
1992 { "vavguw", VX(4, 1154), VX_MASK, PPCVEC, { VD, VA, VB } },
1993 { "vcfsx", VX(4, 842), VX_MASK, PPCVEC, { VD, VB, UIMM } },
1994 { "vcfux", VX(4, 778), VX_MASK, PPCVEC, { VD, VB, UIMM } },
1995 { "vcmpbfp", VXR(4, 966, 0), VXR_MASK, PPCVEC, { VD, VA, VB } },
1996 { "vcmpbfp.", VXR(4, 966, 1), VXR_MASK, PPCVEC, { VD, VA, VB } },
1997 { "vcmpeqfp", VXR(4, 198, 0), VXR_MASK, PPCVEC, { VD, VA, VB } },
1998 { "vcmpeqfp.", VXR(4, 198, 1), VXR_MASK, PPCVEC, { VD, VA, VB } },
1999 { "vcmpequb", VXR(4, 6, 0), VXR_MASK, PPCVEC, { VD, VA, VB } },
2000 { "vcmpequb.", VXR(4, 6, 1), VXR_MASK, PPCVEC, { VD, VA, VB } },
2001 { "vcmpequh", VXR(4, 70, 0), VXR_MASK, PPCVEC, { VD, VA, VB } },
2002 { "vcmpequh.", VXR(4, 70, 1), VXR_MASK, PPCVEC, { VD, VA, VB } },
2003 { "vcmpequw", VXR(4, 134, 0), VXR_MASK, PPCVEC, { VD, VA, VB } },
2004 { "vcmpequw.", VXR(4, 134, 1), VXR_MASK, PPCVEC, { VD, VA, VB } },
2005 { "vcmpgefp", VXR(4, 454, 0), VXR_MASK, PPCVEC, { VD, VA, VB } },
2006 { "vcmpgefp.", VXR(4, 454, 1), VXR_MASK, PPCVEC, { VD, VA, VB } },
2007 { "vcmpgtfp", VXR(4, 710, 0), VXR_MASK, PPCVEC, { VD, VA, VB } },
2008 { "vcmpgtfp.", VXR(4, 710, 1), VXR_MASK, PPCVEC, { VD, VA, VB } },
2009 { "vcmpgtsb", VXR(4, 774, 0), VXR_MASK, PPCVEC, { VD, VA, VB } },
2010 { "vcmpgtsb.", VXR(4, 774, 1), VXR_MASK, PPCVEC, { VD, VA, VB } },
2011 { "vcmpgtsh", VXR(4, 838, 0), VXR_MASK, PPCVEC, { VD, VA, VB } },
2012 { "vcmpgtsh.", VXR(4, 838, 1), VXR_MASK, PPCVEC, { VD, VA, VB } },
2013 { "vcmpgtsw", VXR(4, 902, 0), VXR_MASK, PPCVEC, { VD, VA, VB } },
2014 { "vcmpgtsw.", VXR(4, 902, 1), VXR_MASK, PPCVEC, { VD, VA, VB } },
2015 { "vcmpgtub", VXR(4, 518, 0), VXR_MASK, PPCVEC, { VD, VA, VB } },
2016 { "vcmpgtub.", VXR(4, 518, 1), VXR_MASK, PPCVEC, { VD, VA, VB } },
2017 { "vcmpgtuh", VXR(4, 582, 0), VXR_MASK, PPCVEC, { VD, VA, VB } },
2018 { "vcmpgtuh.", VXR(4, 582, 1), VXR_MASK, PPCVEC, { VD, VA, VB } },
2019 { "vcmpgtuw", VXR(4, 646, 0), VXR_MASK, PPCVEC, { VD, VA, VB } },
2020 { "vcmpgtuw.", VXR(4, 646, 1), VXR_MASK, PPCVEC, { VD, VA, VB } },
2021 { "vctsxs", VX(4, 970), VX_MASK, PPCVEC, { VD, VB, UIMM } },
2022 { "vctuxs", VX(4, 906), VX_MASK, PPCVEC, { VD, VB, UIMM } },
2023 { "vexptefp", VX(4, 394), VX_MASK, PPCVEC, { VD, VB } },
2024 { "vlogefp", VX(4, 458), VX_MASK, PPCVEC, { VD, VB } },
2025 { "vmaddfp", VXA(4, 46), VXA_MASK, PPCVEC, { VD, VA, VC, VB } },
2026 { "vmaxfp", VX(4, 1034), VX_MASK, PPCVEC, { VD, VA, VB } },
2027 { "vmaxsb", VX(4, 258), VX_MASK, PPCVEC, { VD, VA, VB } },
2028 { "vmaxsh", VX(4, 322), VX_MASK, PPCVEC, { VD, VA, VB } },
2029 { "vmaxsw", VX(4, 386), VX_MASK, PPCVEC, { VD, VA, VB } },
2030 { "vmaxub", VX(4, 2), VX_MASK, PPCVEC, { VD, VA, VB } },
2031 { "vmaxuh", VX(4, 66), VX_MASK, PPCVEC, { VD, VA, VB } },
2032 { "vmaxuw", VX(4, 130), VX_MASK, PPCVEC, { VD, VA, VB } },
2033 { "vmhaddshs", VXA(4, 32), VXA_MASK, PPCVEC, { VD, VA, VB, VC } },
2034 { "vmhraddshs", VXA(4, 33), VXA_MASK, PPCVEC, { VD, VA, VB, VC } },
2035 { "vminfp", VX(4, 1098), VX_MASK, PPCVEC, { VD, VA, VB } },
2036 { "vminsb", VX(4, 770), VX_MASK, PPCVEC, { VD, VA, VB } },
2037 { "vminsh", VX(4, 834), VX_MASK, PPCVEC, { VD, VA, VB } },
2038 { "vminsw", VX(4, 898), VX_MASK, PPCVEC, { VD, VA, VB } },
2039 { "vminub", VX(4, 514), VX_MASK, PPCVEC, { VD, VA, VB } },
2040 { "vminuh", VX(4, 578), VX_MASK, PPCVEC, { VD, VA, VB } },
2041 { "vminuw", VX(4, 642), VX_MASK, PPCVEC, { VD, VA, VB } },
2042 { "vmladduhm", VXA(4, 34), VXA_MASK, PPCVEC, { VD, VA, VB, VC } },
2043 { "vmrghb", VX(4, 12), VX_MASK, PPCVEC, { VD, VA, VB } },
2044 { "vmrghh", VX(4, 76), VX_MASK, PPCVEC, { VD, VA, VB } },
2045 { "vmrghw", VX(4, 140), VX_MASK, PPCVEC, { VD, VA, VB } },
2046 { "vmrglb", VX(4, 268), VX_MASK, PPCVEC, { VD, VA, VB } },
2047 { "vmrglh", VX(4, 332), VX_MASK, PPCVEC, { VD, VA, VB } },
2048 { "vmrglw", VX(4, 396), VX_MASK, PPCVEC, { VD, VA, VB } },
2049 { "vmsummbm", VXA(4, 37), VXA_MASK, PPCVEC, { VD, VA, VB, VC } },
2050 { "vmsumshm", VXA(4, 40), VXA_MASK, PPCVEC, { VD, VA, VB, VC } },
2051 { "vmsumshs", VXA(4, 41), VXA_MASK, PPCVEC, { VD, VA, VB, VC } },
2052 { "vmsumubm", VXA(4, 36), VXA_MASK, PPCVEC, { VD, VA, VB, VC } },
2053 { "vmsumuhm", VXA(4, 38), VXA_MASK, PPCVEC, { VD, VA, VB, VC } },
2054 { "vmsumuhs", VXA(4, 39), VXA_MASK, PPCVEC, { VD, VA, VB, VC } },
2055 { "vmulesb", VX(4, 776), VX_MASK, PPCVEC, { VD, VA, VB } },
2056 { "vmulesh", VX(4, 840), VX_MASK, PPCVEC, { VD, VA, VB } },
2057 { "vmuleub", VX(4, 520), VX_MASK, PPCVEC, { VD, VA, VB } },
2058 { "vmuleuh", VX(4, 584), VX_MASK, PPCVEC, { VD, VA, VB } },
2059 { "vmulosb", VX(4, 264), VX_MASK, PPCVEC, { VD, VA, VB } },
2060 { "vmulosh", VX(4, 328), VX_MASK, PPCVEC, { VD, VA, VB } },
2061 { "vmuloub", VX(4, 8), VX_MASK, PPCVEC, { VD, VA, VB } },
2062 { "vmulouh", VX(4, 72), VX_MASK, PPCVEC, { VD, VA, VB } },
2063 { "vnmsubfp", VXA(4, 47), VXA_MASK, PPCVEC, { VD, VA, VC, VB } },
2064 { "vnor", VX(4, 1284), VX_MASK, PPCVEC, { VD, VA, VB } },
2065 { "vor", VX(4, 1156), VX_MASK, PPCVEC, { VD, VA, VB } },
2066 { "vperm", VXA(4, 43), VXA_MASK, PPCVEC, { VD, VA, VB, VC } },
2067 { "vpkpx", VX(4, 782), VX_MASK, PPCVEC, { VD, VA, VB } },
2068 { "vpkshss", VX(4, 398), VX_MASK, PPCVEC, { VD, VA, VB } },
2069 { "vpkshus", VX(4, 270), VX_MASK, PPCVEC, { VD, VA, VB } },
2070 { "vpkswss", VX(4, 462), VX_MASK, PPCVEC, { VD, VA, VB } },
2071 { "vpkswus", VX(4, 334), VX_MASK, PPCVEC, { VD, VA, VB } },
2072 { "vpkuhum", VX(4, 14), VX_MASK, PPCVEC, { VD, VA, VB } },
2073 { "vpkuhus", VX(4, 142), VX_MASK, PPCVEC, { VD, VA, VB } },
2074 { "vpkuwum", VX(4, 78), VX_MASK, PPCVEC, { VD, VA, VB } },
2075 { "vpkuwus", VX(4, 206), VX_MASK, PPCVEC, { VD, VA, VB } },
2076 { "vrefp", VX(4, 266), VX_MASK, PPCVEC, { VD, VB } },
2077 { "vrfim", VX(4, 714), VX_MASK, PPCVEC, { VD, VB } },
2078 { "vrfin", VX(4, 522), VX_MASK, PPCVEC, { VD, VB } },
2079 { "vrfip", VX(4, 650), VX_MASK, PPCVEC, { VD, VB } },
2080 { "vrfiz", VX(4, 586), VX_MASK, PPCVEC, { VD, VB } },
2081 { "vrlb", VX(4, 4), VX_MASK, PPCVEC, { VD, VA, VB } },
2082 { "vrlh", VX(4, 68), VX_MASK, PPCVEC, { VD, VA, VB } },
2083 { "vrlw", VX(4, 132), VX_MASK, PPCVEC, { VD, VA, VB } },
2084 { "vrsqrtefp", VX(4, 330), VX_MASK, PPCVEC, { VD, VB } },
2085 { "vsel", VXA(4, 42), VXA_MASK, PPCVEC, { VD, VA, VB, VC } },
2086 { "vsl", VX(4, 452), VX_MASK, PPCVEC, { VD, VA, VB } },
2087 { "vslb", VX(4, 260), VX_MASK, PPCVEC, { VD, VA, VB } },
2088 { "vsldoi", VXA(4, 44), VXA_MASK, PPCVEC, { VD, VA, VB, SHB } },
2089 { "vslh", VX(4, 324), VX_MASK, PPCVEC, { VD, VA, VB } },
2090 { "vslo", VX(4, 1036), VX_MASK, PPCVEC, { VD, VA, VB } },
2091 { "vslw", VX(4, 388), VX_MASK, PPCVEC, { VD, VA, VB } },
2092 { "vspltb", VX(4, 524), VX_MASK, PPCVEC, { VD, VB, UIMM } },
2093 { "vsplth", VX(4, 588), VX_MASK, PPCVEC, { VD, VB, UIMM } },
2094 { "vspltisb", VX(4, 780), VX_MASK, PPCVEC, { VD, SIMM } },
2095 { "vspltish", VX(4, 844), VX_MASK, PPCVEC, { VD, SIMM } },
2096 { "vspltisw", VX(4, 908), VX_MASK, PPCVEC, { VD, SIMM } },
2097 { "vspltw", VX(4, 652), VX_MASK, PPCVEC, { VD, VB, UIMM } },
2098 { "vsr", VX(4, 708), VX_MASK, PPCVEC, { VD, VA, VB } },
2099 { "vsrab", VX(4, 772), VX_MASK, PPCVEC, { VD, VA, VB } },
2100 { "vsrah", VX(4, 836), VX_MASK, PPCVEC, { VD, VA, VB } },
2101 { "vsraw", VX(4, 900), VX_MASK, PPCVEC, { VD, VA, VB } },
2102 { "vsrb", VX(4, 516), VX_MASK, PPCVEC, { VD, VA, VB } },
2103 { "vsrh", VX(4, 580), VX_MASK, PPCVEC, { VD, VA, VB } },
2104 { "vsro", VX(4, 1100), VX_MASK, PPCVEC, { VD, VA, VB } },
2105 { "vsrw", VX(4, 644), VX_MASK, PPCVEC, { VD, VA, VB } },
2106 { "vsubcuw", VX(4, 1408), VX_MASK, PPCVEC, { VD, VA, VB } },
2107 { "vsubfp", VX(4, 74), VX_MASK, PPCVEC, { VD, VA, VB } },
2108 { "vsubsbs", VX(4, 1792), VX_MASK, PPCVEC, { VD, VA, VB } },
2109 { "vsubshs", VX(4, 1856), VX_MASK, PPCVEC, { VD, VA, VB } },
2110 { "vsubsws", VX(4, 1920), VX_MASK, PPCVEC, { VD, VA, VB } },
2111 { "vsububm", VX(4, 1024), VX_MASK, PPCVEC, { VD, VA, VB } },
2112 { "vsububs", VX(4, 1536), VX_MASK, PPCVEC, { VD, VA, VB } },
2113 { "vsubuhm", VX(4, 1088), VX_MASK, PPCVEC, { VD, VA, VB } },
2114 { "vsubuhs", VX(4, 1600), VX_MASK, PPCVEC, { VD, VA, VB } },
2115 { "vsubuwm", VX(4, 1152), VX_MASK, PPCVEC, { VD, VA, VB } },
2116 { "vsubuws", VX(4, 1664), VX_MASK, PPCVEC, { VD, VA, VB } },
2117 { "vsumsws", VX(4, 1928), VX_MASK, PPCVEC, { VD, VA, VB } },
2118 { "vsum2sws", VX(4, 1672), VX_MASK, PPCVEC, { VD, VA, VB } },
2119 { "vsum4sbs", VX(4, 1800), VX_MASK, PPCVEC, { VD, VA, VB } },
2120 { "vsum4shs", VX(4, 1608), VX_MASK, PPCVEC, { VD, VA, VB } },
2121 { "vsum4ubs", VX(4, 1544), VX_MASK, PPCVEC, { VD, VA, VB } },
2122 { "vupkhpx", VX(4, 846), VX_MASK, PPCVEC, { VD, VB } },
2123 { "vupkhsb", VX(4, 526), VX_MASK, PPCVEC, { VD, VB } },
2124 { "vupkhsh", VX(4, 590), VX_MASK, PPCVEC, { VD, VB } },
2125 { "vupklpx", VX(4, 974), VX_MASK, PPCVEC, { VD, VB } },
2126 { "vupklsb", VX(4, 654), VX_MASK, PPCVEC, { VD, VB } },
2127 { "vupklsh", VX(4, 718), VX_MASK, PPCVEC, { VD, VB } },
2128 { "vxor", VX(4, 1220), VX_MASK, PPCVEC, { VD, VA, VB } },
2130 { "evaddw", VX(4, 512), VX_MASK, PPCSPE, { RS, RA, RB } },
2131 { "evaddiw", VX(4, 514), VX_MASK, PPCSPE, { RS, RB, UIMM } },
2132 { "evsubfw", VX(4, 516), VX_MASK, PPCSPE, { RS, RA, RB } },
2133 { "evsubw", VX(4, 516), VX_MASK, PPCSPE, { RS, RB, RA } },
2134 { "evsubifw", VX(4, 518), VX_MASK, PPCSPE, { RS, UIMM, RB } },
2135 { "evsubiw", VX(4, 518), VX_MASK, PPCSPE, { RS, RB, UIMM } },
2136 { "evabs", VX(4, 520), VX_MASK, PPCSPE, { RS, RA } },
2137 { "evneg", VX(4, 521), VX_MASK, PPCSPE, { RS, RA } },
2138 { "evextsb", VX(4, 522), VX_MASK, PPCSPE, { RS, RA } },
2139 { "evextsh", VX(4, 523), VX_MASK, PPCSPE, { RS, RA } },
2140 { "evrndw", VX(4, 524), VX_MASK, PPCSPE, { RS, RA } },
2141 { "evcntlzw", VX(4, 525), VX_MASK, PPCSPE, { RS, RA } },
2142 { "evcntlsw", VX(4, 526), VX_MASK, PPCSPE, { RS, RA } },
2144 { "brinc", VX(4, 527), VX_MASK, PPCSPE, { RS, RA, RB } },
2146 { "evand", VX(4, 529), VX_MASK, PPCSPE, { RS, RA, RB } },
2147 { "evandc", VX(4, 530), VX_MASK, PPCSPE, { RS, RA, RB } },
2148 { "evmr", VX(4, 535), VX_MASK, PPCSPE, { RS, RA, BBA } },
2149 { "evor", VX(4, 535), VX_MASK, PPCSPE, { RS, RA, RB } },
2150 { "evorc", VX(4, 539), VX_MASK, PPCSPE, { RS, RA, RB } },
2151 { "evxor", VX(4, 534), VX_MASK, PPCSPE, { RS, RA, RB } },
2152 { "eveqv", VX(4, 537), VX_MASK, PPCSPE, { RS, RA, RB } },
2153 { "evnand", VX(4, 542), VX_MASK, PPCSPE, { RS, RA, RB } },
2154 { "evnot", VX(4, 536), VX_MASK, PPCSPE, { RS, RA, BBA } },
2155 { "evnor", VX(4, 536), VX_MASK, PPCSPE, { RS, RA, RB } },
2157 { "evrlw", VX(4, 552), VX_MASK, PPCSPE, { RS, RA, RB } },
2158 { "evrlwi", VX(4, 554), VX_MASK, PPCSPE, { RS, RA, EVUIMM } },
2159 { "evslw", VX(4, 548), VX_MASK, PPCSPE, { RS, RA, RB } },
2160 { "evslwi", VX(4, 550), VX_MASK, PPCSPE, { RS, RA, EVUIMM } },
2161 { "evsrws", VX(4, 545), VX_MASK, PPCSPE, { RS, RA, RB } },
2162 { "evsrwu", VX(4, 544), VX_MASK, PPCSPE, { RS, RA, RB } },
2163 { "evsrwis", VX(4, 547), VX_MASK, PPCSPE, { RS, RA, EVUIMM } },
2164 { "evsrwiu", VX(4, 546), VX_MASK, PPCSPE, { RS, RA, EVUIMM } },
2165 { "evsplati", VX(4, 553), VX_MASK, PPCSPE, { RS, SIMM } },
2166 { "evsplatfi", VX(4, 555), VX_MASK, PPCSPE, { RS, SIMM } },
2167 { "evmergehi", VX(4, 556), VX_MASK, PPCSPE, { RS, RA, RB } },
2168 { "evmergelo", VX(4, 557), VX_MASK, PPCSPE, { RS, RA, RB } },
2169 { "evmergehilo",VX(4,558), VX_MASK, PPCSPE, { RS, RA, RB } },
2170 { "evmergelohi",VX(4,559), VX_MASK, PPCSPE, { RS, RA, RB } },
2172 { "evcmpgts", VX(4, 561), VX_MASK, PPCSPE, { CRFD, RA, RB } },
2173 { "evcmpgtu", VX(4, 560), VX_MASK, PPCSPE, { CRFD, RA, RB } },
2174 { "evcmplts", VX(4, 563), VX_MASK, PPCSPE, { CRFD, RA, RB } },
2175 { "evcmpltu", VX(4, 562), VX_MASK, PPCSPE, { CRFD, RA, RB } },
2176 { "evcmpeq", VX(4, 564), VX_MASK, PPCSPE, { CRFD, RA, RB } },
2177 { "evsel", EVSEL(4,79),EVSEL_MASK, PPCSPE, { RS, RA, RB, CRFS } },
2179 { "evldd", VX(4, 769), VX_MASK, PPCSPE, { RS, EVUIMM_8, RA } },
2180 { "evlddx", VX(4, 768), VX_MASK, PPCSPE, { RS, RA, RB } },
2181 { "evldw", VX(4, 771), VX_MASK, PPCSPE, { RS, EVUIMM_8, RA } },
2182 { "evldwx", VX(4, 770), VX_MASK, PPCSPE, { RS, RA, RB } },
2183 { "evldh", VX(4, 773), VX_MASK, PPCSPE, { RS, EVUIMM_8, RA } },
2184 { "evldhx", VX(4, 772), VX_MASK, PPCSPE, { RS, RA, RB } },
2185 { "evlwhe", VX(4, 785), VX_MASK, PPCSPE, { RS, EVUIMM_4, RA } },
2186 { "evlwhex", VX(4, 784), VX_MASK, PPCSPE, { RS, RA, RB } },
2187 { "evlwhou", VX(4, 789), VX_MASK, PPCSPE, { RS, EVUIMM_4, RA } },
2188 { "evlwhoux", VX(4, 788), VX_MASK, PPCSPE, { RS, RA, RB } },
2189 { "evlwhos", VX(4, 791), VX_MASK, PPCSPE, { RS, EVUIMM_4, RA } },
2190 { "evlwhosx", VX(4, 790), VX_MASK, PPCSPE, { RS, RA, RB } },
2191 { "evlwwsplat",VX(4, 793), VX_MASK, PPCSPE, { RS, EVUIMM_4, RA } },
2192 { "evlwwsplatx",VX(4, 792), VX_MASK, PPCSPE, { RS, RA, RB } },
2193 { "evlwhsplat",VX(4, 797), VX_MASK, PPCSPE, { RS, EVUIMM_4, RA } },
2194 { "evlwhsplatx",VX(4, 796), VX_MASK, PPCSPE, { RS, RA, RB } },
2195 { "evlhhesplat",VX(4, 777), VX_MASK, PPCSPE, { RS, EVUIMM_2, RA } },
2196 { "evlhhesplatx",VX(4, 776), VX_MASK, PPCSPE, { RS, RA, RB } },
2197 { "evlhhousplat",VX(4, 781), VX_MASK, PPCSPE, { RS, EVUIMM_2, RA } },
2198 { "evlhhousplatx",VX(4, 780), VX_MASK, PPCSPE, { RS, RA, RB } },
2199 { "evlhhossplat",VX(4, 783), VX_MASK, PPCSPE, { RS, EVUIMM_2, RA } },
2200 { "evlhhossplatx",VX(4, 782), VX_MASK, PPCSPE, { RS, RA, RB } },
2202 { "evstdd", VX(4, 801), VX_MASK, PPCSPE, { RS, EVUIMM_8, RA } },
2203 { "evstddx", VX(4, 800), VX_MASK, PPCSPE, { RS, RA, RB } },
2204 { "evstdw", VX(4, 803), VX_MASK, PPCSPE, { RS, EVUIMM_8, RA } },
2205 { "evstdwx", VX(4, 802), VX_MASK, PPCSPE, { RS, RA, RB } },
2206 { "evstdh", VX(4, 805), VX_MASK, PPCSPE, { RS, EVUIMM_8, RA } },
2207 { "evstdhx", VX(4, 804), VX_MASK, PPCSPE, { RS, RA, RB } },
2208 { "evstwwe", VX(4, 825), VX_MASK, PPCSPE, { RS, EVUIMM_4, RA } },
2209 { "evstwwex", VX(4, 824), VX_MASK, PPCSPE, { RS, RA, RB } },
2210 { "evstwwo", VX(4, 829), VX_MASK, PPCSPE, { RS, EVUIMM_4, RA } },
2211 { "evstwwox", VX(4, 828), VX_MASK, PPCSPE, { RS, RA, RB } },
2212 { "evstwhe", VX(4, 817), VX_MASK, PPCSPE, { RS, EVUIMM_4, RA } },
2213 { "evstwhex", VX(4, 816), VX_MASK, PPCSPE, { RS, RA, RB } },
2214 { "evstwho", VX(4, 821), VX_MASK, PPCSPE, { RS, EVUIMM_4, RA } },
2215 { "evstwhox", VX(4, 820), VX_MASK, PPCSPE, { RS, RA, RB } },
2217 { "evfsabs", VX(4, 644), VX_MASK, PPCSPE, { RS, RA } },
2218 { "evfsnabs", VX(4, 645), VX_MASK, PPCSPE, { RS, RA } },
2219 { "evfsneg", VX(4, 646), VX_MASK, PPCSPE, { RS, RA } },
2220 { "evfsadd", VX(4, 640), VX_MASK, PPCSPE, { RS, RA, RB } },
2221 { "evfssub", VX(4, 641), VX_MASK, PPCSPE, { RS, RA, RB } },
2222 { "evfsmul", VX(4, 648), VX_MASK, PPCSPE, { RS, RA, RB } },
2223 { "evfsdiv", VX(4, 649), VX_MASK, PPCSPE, { RS, RA, RB } },
2224 { "evfscmpgt", VX(4, 652), VX_MASK, PPCSPE, { CRFD, RA, RB } },
2225 { "evfscmplt", VX(4, 653), VX_MASK, PPCSPE, { CRFD, RA, RB } },
2226 { "evfscmpeq", VX(4, 654), VX_MASK, PPCSPE, { CRFD, RA, RB } },
2227 { "evfststgt", VX(4, 668), VX_MASK, PPCSPE, { CRFD, RA, RB } },
2228 { "evfststlt", VX(4, 669), VX_MASK, PPCSPE, { CRFD, RA, RB } },
2229 { "evfststeq", VX(4, 670), VX_MASK, PPCSPE, { CRFD, RA, RB } },
2230 { "evfscfui", VX(4, 656), VX_MASK, PPCSPE, { RS, RB } },
2231 { "evfsctuiz", VX(4, 664), VX_MASK, PPCSPE, { RS, RB } },
2232 { "evfscfsi", VX(4, 657), VX_MASK, PPCSPE, { RS, RB } },
2233 { "evfscfuf", VX(4, 658), VX_MASK, PPCSPE, { RS, RB } },
2234 { "evfscfsf", VX(4, 659), VX_MASK, PPCSPE, { RS, RB } },
2235 { "evfsctui", VX(4, 660), VX_MASK, PPCSPE, { RS, RB } },
2236 { "evfsctsi", VX(4, 661), VX_MASK, PPCSPE, { RS, RB } },
2237 { "evfsctsiz", VX(4, 666), VX_MASK, PPCSPE, { RS, RB } },
2238 { "evfsctuf", VX(4, 662), VX_MASK, PPCSPE, { RS, RB } },
2239 { "evfsctsf", VX(4, 663), VX_MASK, PPCSPE, { RS, RB } },
2241 { "efsabs", VX(4, 708), VX_MASK, PPCEFS, { RS, RA } },
2242 { "efsnabs", VX(4, 709), VX_MASK, PPCEFS, { RS, RA } },
2243 { "efsneg", VX(4, 710), VX_MASK, PPCEFS, { RS, RA } },
2244 { "efsadd", VX(4, 704), VX_MASK, PPCEFS, { RS, RA, RB } },
2245 { "efssub", VX(4, 705), VX_MASK, PPCEFS, { RS, RA, RB } },
2246 { "efsmul", VX(4, 712), VX_MASK, PPCEFS, { RS, RA, RB } },
2247 { "efsdiv", VX(4, 713), VX_MASK, PPCEFS, { RS, RA, RB } },
2248 { "efscmpgt", VX(4, 716), VX_MASK, PPCEFS, { CRFD, RA, RB } },
2249 { "efscmplt", VX(4, 717), VX_MASK, PPCEFS, { CRFD, RA, RB } },
2250 { "efscmpeq", VX(4, 718), VX_MASK, PPCEFS, { CRFD, RA, RB } },
2251 { "efststgt", VX(4, 732), VX_MASK, PPCEFS, { CRFD, RA, RB } },
2252 { "efststlt", VX(4, 733), VX_MASK, PPCEFS, { CRFD, RA, RB } },
2253 { "efststeq", VX(4, 734), VX_MASK, PPCEFS, { CRFD, RA, RB } },
2254 { "efscfui", VX(4, 720), VX_MASK, PPCEFS, { RS, RB } },
2255 { "efsctuiz", VX(4, 728), VX_MASK, PPCEFS, { RS, RB } },
2256 { "efscfsi", VX(4, 721), VX_MASK, PPCEFS, { RS, RB } },
2257 { "efscfuf", VX(4, 722), VX_MASK, PPCEFS, { RS, RB } },
2258 { "efscfsf", VX(4, 723), VX_MASK, PPCEFS, { RS, RB } },
2259 { "efsctui", VX(4, 724), VX_MASK, PPCEFS, { RS, RB } },
2260 { "efsctsi", VX(4, 725), VX_MASK, PPCEFS, { RS, RB } },
2261 { "efsctsiz", VX(4, 730), VX_MASK, PPCEFS, { RS, RB } },
2262 { "efsctuf", VX(4, 726), VX_MASK, PPCEFS, { RS, RB } },
2263 { "efsctsf", VX(4, 727), VX_MASK, PPCEFS, { RS, RB } },
2265 { "evmhossf", VX(4, 1031), VX_MASK, PPCSPE, { RS, RA, RB } },
2266 { "evmhossfa", VX(4, 1063), VX_MASK, PPCSPE, { RS, RA, RB } },
2267 { "evmhosmf", VX(4, 1039), VX_MASK, PPCSPE, { RS, RA, RB } },
2268 { "evmhosmfa", VX(4, 1071), VX_MASK, PPCSPE, { RS, RA, RB } },
2269 { "evmhosmi", VX(4, 1037), VX_MASK, PPCSPE, { RS, RA, RB } },
2270 { "evmhosmia", VX(4, 1069), VX_MASK, PPCSPE, { RS, RA, RB } },
2271 { "evmhoumi", VX(4, 1036), VX_MASK, PPCSPE, { RS, RA, RB } },
2272 { "evmhoumia", VX(4, 1068), VX_MASK, PPCSPE, { RS, RA, RB } },
2273 { "evmhessf", VX(4, 1027), VX_MASK, PPCSPE, { RS, RA, RB } },
2274 { "evmhessfa", VX(4, 1059), VX_MASK, PPCSPE, { RS, RA, RB } },
2275 { "evmhesmf", VX(4, 1035), VX_MASK, PPCSPE, { RS, RA, RB } },
2276 { "evmhesmfa", VX(4, 1067), VX_MASK, PPCSPE, { RS, RA, RB } },
2277 { "evmhesmi", VX(4, 1033), VX_MASK, PPCSPE, { RS, RA, RB } },
2278 { "evmhesmia", VX(4, 1065), VX_MASK, PPCSPE, { RS, RA, RB } },
2279 { "evmheumi", VX(4, 1032), VX_MASK, PPCSPE, { RS, RA, RB } },
2280 { "evmheumia", VX(4, 1064), VX_MASK, PPCSPE, { RS, RA, RB } },
2282 { "evmhossfaaw",VX(4, 1287), VX_MASK, PPCSPE, { RS, RA, RB } },
2283 { "evmhossiaaw",VX(4, 1285), VX_MASK, PPCSPE, { RS, RA, RB } },
2284 { "evmhosmfaaw",VX(4, 1295), VX_MASK, PPCSPE, { RS, RA, RB } },
2285 { "evmhosmiaaw",VX(4, 1293), VX_MASK, PPCSPE, { RS, RA, RB } },
2286 { "evmhousiaaw",VX(4, 1284), VX_MASK, PPCSPE, { RS, RA, RB } },
2287 { "evmhoumiaaw",VX(4, 1292), VX_MASK, PPCSPE, { RS, RA, RB } },
2288 { "evmhessfaaw",VX(4, 1283), VX_MASK, PPCSPE, { RS, RA, RB } },
2289 { "evmhessiaaw",VX(4, 1281), VX_MASK, PPCSPE, { RS, RA, RB } },
2290 { "evmhesmfaaw",VX(4, 1291), VX_MASK, PPCSPE, { RS, RA, RB } },
2291 { "evmhesmiaaw",VX(4, 1289), VX_MASK, PPCSPE, { RS, RA, RB } },
2292 { "evmheusiaaw",VX(4, 1280), VX_MASK, PPCSPE, { RS, RA, RB } },
2293 { "evmheumiaaw",VX(4, 1288), VX_MASK, PPCSPE, { RS, RA, RB } },
2295 { "evmhossfanw",VX(4, 1415), VX_MASK, PPCSPE, { RS, RA, RB } },
2296 { "evmhossianw",VX(4, 1413), VX_MASK, PPCSPE, { RS, RA, RB } },
2297 { "evmhosmfanw",VX(4, 1423), VX_MASK, PPCSPE, { RS, RA, RB } },
2298 { "evmhosmianw",VX(4, 1421), VX_MASK, PPCSPE, { RS, RA, RB } },
2299 { "evmhousianw",VX(4, 1412), VX_MASK, PPCSPE, { RS, RA, RB } },
2300 { "evmhoumianw",VX(4, 1420), VX_MASK, PPCSPE, { RS, RA, RB } },
2301 { "evmhessfanw",VX(4, 1411), VX_MASK, PPCSPE, { RS, RA, RB } },
2302 { "evmhessianw",VX(4, 1409), VX_MASK, PPCSPE, { RS, RA, RB } },
2303 { "evmhesmfanw",VX(4, 1419), VX_MASK, PPCSPE, { RS, RA, RB } },
2304 { "evmhesmianw",VX(4, 1417), VX_MASK, PPCSPE, { RS, RA, RB } },
2305 { "evmheusianw",VX(4, 1408), VX_MASK, PPCSPE, { RS, RA, RB } },
2306 { "evmheumianw",VX(4, 1416), VX_MASK, PPCSPE, { RS, RA, RB } },
2308 { "evmhogsmfaa",VX(4, 1327), VX_MASK, PPCSPE, { RS, RA, RB } },
2309 { "evmhogsmiaa",VX(4, 1325), VX_MASK, PPCSPE, { RS, RA, RB } },
2310 { "evmhogumiaa",VX(4, 1324), VX_MASK, PPCSPE, { RS, RA, RB } },
2311 { "evmhegsmfaa",VX(4, 1323), VX_MASK, PPCSPE, { RS, RA, RB } },
2312 { "evmhegsmiaa",VX(4, 1321), VX_MASK, PPCSPE, { RS, RA, RB } },
2313 { "evmhegumiaa",VX(4, 1320), VX_MASK, PPCSPE, { RS, RA, RB } },
2315 { "evmhogsmfan",VX(4, 1455), VX_MASK, PPCSPE, { RS, RA, RB } },
2316 { "evmhogsmian",VX(4, 1453), VX_MASK, PPCSPE, { RS, RA, RB } },
2317 { "evmhogumian",VX(4, 1452), VX_MASK, PPCSPE, { RS, RA, RB } },
2318 { "evmhegsmfan",VX(4, 1451), VX_MASK, PPCSPE, { RS, RA, RB } },
2319 { "evmhegsmian",VX(4, 1449), VX_MASK, PPCSPE, { RS, RA, RB } },
2320 { "evmhegumian",VX(4, 1448), VX_MASK, PPCSPE, { RS, RA, RB } },
2322 { "evmwhssf", VX(4, 1095), VX_MASK, PPCSPE, { RS, RA, RB } },
2323 { "evmwhssfa", VX(4, 1127), VX_MASK, PPCSPE, { RS, RA, RB } },
2324 { "evmwhsmf", VX(4, 1103), VX_MASK, PPCSPE, { RS, RA, RB } },
2325 { "evmwhsmfa", VX(4, 1135), VX_MASK, PPCSPE, { RS, RA, RB } },
2326 { "evmwhsmi", VX(4, 1101), VX_MASK, PPCSPE, { RS, RA, RB } },
2327 { "evmwhsmia", VX(4, 1133), VX_MASK, PPCSPE, { RS, RA, RB } },
2328 { "evmwhumi", VX(4, 1100), VX_MASK, PPCSPE, { RS, RA, RB } },
2329 { "evmwhumia", VX(4, 1132), VX_MASK, PPCSPE, { RS, RA, RB } },
2331 { "evmwlumi", VX(4, 1096), VX_MASK, PPCSPE, { RS, RA, RB } },
2332 { "evmwlumia", VX(4, 1128), VX_MASK, PPCSPE, { RS, RA, RB } },
2334 { "evmwlssiaaw",VX(4, 1345), VX_MASK, PPCSPE, { RS, RA, RB } },
2335 { "evmwlsmiaaw",VX(4, 1353), VX_MASK, PPCSPE, { RS, RA, RB } },
2336 { "evmwlusiaaw",VX(4, 1344), VX_MASK, PPCSPE, { RS, RA, RB } },
2337 { "evmwlumiaaw",VX(4, 1352), VX_MASK, PPCSPE, { RS, RA, RB } },
2339 { "evmwlssianw",VX(4, 1473), VX_MASK, PPCSPE, { RS, RA, RB } },
2340 { "evmwlsmianw",VX(4, 1481), VX_MASK, PPCSPE, { RS, RA, RB } },
2341 { "evmwlusianw",VX(4, 1472), VX_MASK, PPCSPE, { RS, RA, RB } },
2342 { "evmwlumianw",VX(4, 1480), VX_MASK, PPCSPE, { RS, RA, RB } },
2344 { "evmwssf", VX(4, 1107), VX_MASK, PPCSPE, { RS, RA, RB } },
2345 { "evmwssfa", VX(4, 1139), VX_MASK, PPCSPE, { RS, RA, RB } },
2346 { "evmwsmf", VX(4, 1115), VX_MASK, PPCSPE, { RS, RA, RB } },
2347 { "evmwsmfa", VX(4, 1147), VX_MASK, PPCSPE, { RS, RA, RB } },
2348 { "evmwsmi", VX(4, 1113), VX_MASK, PPCSPE, { RS, RA, RB } },
2349 { "evmwsmia", VX(4, 1145), VX_MASK, PPCSPE, { RS, RA, RB } },
2350 { "evmwumi", VX(4, 1112), VX_MASK, PPCSPE, { RS, RA, RB } },
2351 { "evmwumia", VX(4, 1144), VX_MASK, PPCSPE, { RS, RA, RB } },
2353 { "evmwssfaa", VX(4, 1363), VX_MASK, PPCSPE, { RS, RA, RB } },
2354 { "evmwsmfaa", VX(4, 1371), VX_MASK, PPCSPE, { RS, RA, RB } },
2355 { "evmwsmiaa", VX(4, 1369), VX_MASK, PPCSPE, { RS, RA, RB } },
2356 { "evmwumiaa", VX(4, 1368), VX_MASK, PPCSPE, { RS, RA, RB } },
2358 { "evmwssfan", VX(4, 1491), VX_MASK, PPCSPE, { RS, RA, RB } },
2359 { "evmwsmfan", VX(4, 1499), VX_MASK, PPCSPE, { RS, RA, RB } },
2360 { "evmwsmian", VX(4, 1497), VX_MASK, PPCSPE, { RS, RA, RB } },
2361 { "evmwumian", VX(4, 1496), VX_MASK, PPCSPE, { RS, RA, RB } },
2363 { "evaddssiaaw",VX(4, 1217), VX_MASK, PPCSPE, { RS, RA } },
2364 { "evaddsmiaaw",VX(4, 1225), VX_MASK, PPCSPE, { RS, RA } },
2365 { "evaddusiaaw",VX(4, 1216), VX_MASK, PPCSPE, { RS, RA } },
2366 { "evaddumiaaw",VX(4, 1224), VX_MASK, PPCSPE, { RS, RA } },
2368 { "evsubfssiaaw",VX(4, 1219), VX_MASK, PPCSPE, { RS, RA } },
2369 { "evsubfsmiaaw",VX(4, 1227), VX_MASK, PPCSPE, { RS, RA } },
2370 { "evsubfusiaaw",VX(4, 1218), VX_MASK, PPCSPE, { RS, RA } },
2371 { "evsubfumiaaw",VX(4, 1226), VX_MASK, PPCSPE, { RS, RA } },
2373 { "evmra", VX(4, 1220), VX_MASK, PPCSPE, { RS, RA } },
2375 { "evdivws", VX(4, 1222), VX_MASK, PPCSPE, { RS, RA, RB } },
2376 { "evdivwu", VX(4, 1223), VX_MASK, PPCSPE, { RS, RA, RB } },
2378 { "mulli", OP(7), OP_MASK, PPCCOM, { RT, RA, SI } },
2379 { "muli", OP(7), OP_MASK, PWRCOM, { RT, RA, SI } },
2381 { "subfic", OP(8), OP_MASK, PPCCOM, { RT, RA, SI } },
2382 { "sfi", OP(8), OP_MASK, PWRCOM, { RT, RA, SI } },
2384 { "dozi", OP(9), OP_MASK, M601, { RT, RA, SI } },
2386 { "bce", B(9,0,0), B_MASK, BOOKE64, { BO, BI, BD } },
2387 { "bcel", B(9,0,1), B_MASK, BOOKE64, { BO, BI, BD } },
2388 { "bcea", B(9,1,0), B_MASK, BOOKE64, { BO, BI, BDA } },
2389 { "bcela", B(9,1,1), B_MASK, BOOKE64, { BO, BI, BDA } },
2391 { "cmplwi", OPL(10,0), OPL_MASK, PPCCOM, { OBF, RA, UI } },
2392 { "cmpldi", OPL(10,1), OPL_MASK, PPC64, { OBF, RA, UI } },
2393 { "cmpli", OP(10), OP_MASK, PPCONLY, { BF, L, RA, UI } },
2394 { "cmpli", OP(10), OP_MASK, PWRCOM, { BF, RA, UI } },
2396 { "cmpwi", OPL(11,0), OPL_MASK, PPCCOM, { OBF, RA, SI } },
2397 { "cmpdi", OPL(11,1), OPL_MASK, PPC64, { OBF, RA, SI } },
2398 { "cmpi", OP(11), OP_MASK, PPCONLY, { BF, L, RA, SI } },
2399 { "cmpi", OP(11), OP_MASK, PWRCOM, { BF, RA, SI } },
2401 { "addic", OP(12), OP_MASK, PPCCOM, { RT, RA, SI } },
2402 { "ai", OP(12), OP_MASK, PWRCOM, { RT, RA, SI } },
2403 { "subic", OP(12), OP_MASK, PPCCOM, { RT, RA, NSI } },
2405 { "addic.", OP(13), OP_MASK, PPCCOM, { RT, RA, SI } },
2406 { "ai.", OP(13), OP_MASK, PWRCOM, { RT, RA, SI } },
2407 { "subic.", OP(13), OP_MASK, PPCCOM, { RT, RA, NSI } },
2409 { "li", OP(14), DRA_MASK, PPCCOM, { RT, SI } },
2410 { "lil", OP(14), DRA_MASK, PWRCOM, { RT, SI } },
2411 { "addi", OP(14), OP_MASK, PPCCOM, { RT, RA, SI } },
2412 { "cal", OP(14), OP_MASK, PWRCOM, { RT, D, RA } },
2413 { "subi", OP(14), OP_MASK, PPCCOM, { RT, RA, NSI } },
2414 { "la", OP(14), OP_MASK, PPCCOM, { RT, D, RA } },
2416 { "lis", OP(15), DRA_MASK, PPCCOM, { RT, SISIGNOPT } },
2417 { "liu", OP(15), DRA_MASK, PWRCOM, { RT, SISIGNOPT } },
2418 { "addis", OP(15), OP_MASK, PPCCOM, { RT,RA,SISIGNOPT } },
2419 { "cau", OP(15), OP_MASK, PWRCOM, { RT,RA,SISIGNOPT } },
2420 { "subis", OP(15), OP_MASK, PPCCOM, { RT, RA, NSI } },
2422 { "bdnz-", BBO(16,BODNZ,0,0), BBOATBI_MASK, PPCCOM, { BDM } },
2423 { "bdnz+", BBO(16,BODNZ,0,0), BBOATBI_MASK, PPCCOM, { BDP } },
2424 { "bdnz", BBO(16,BODNZ,0,0), BBOATBI_MASK, PPCCOM, { BD } },
2425 { "bdn", BBO(16,BODNZ,0,0), BBOATBI_MASK, PWRCOM, { BD } },
2426 { "bdnzl-", BBO(16,BODNZ,0,1), BBOATBI_MASK, PPCCOM, { BDM } },
2427 { "bdnzl+", BBO(16,BODNZ,0,1), BBOATBI_MASK, PPCCOM, { BDP } },
2428 { "bdnzl", BBO(16,BODNZ,0,1), BBOATBI_MASK, PPCCOM, { BD } },
2429 { "bdnl", BBO(16,BODNZ,0,1), BBOATBI_MASK, PWRCOM, { BD } },
2430 { "bdnza-", BBO(16,BODNZ,1,0), BBOATBI_MASK, PPCCOM, { BDMA } },
2431 { "bdnza+", BBO(16,BODNZ,1,0), BBOATBI_MASK, PPCCOM, { BDPA } },
2432 { "bdnza", BBO(16,BODNZ,1,0), BBOATBI_MASK, PPCCOM, { BDA } },
2433 { "bdna", BBO(16,BODNZ,1,0), BBOATBI_MASK, PWRCOM, { BDA } },
2434 { "bdnzla-", BBO(16,BODNZ,1,1), BBOATBI_MASK, PPCCOM, { BDMA } },
2435 { "bdnzla+", BBO(16,BODNZ,1,1), BBOATBI_MASK, PPCCOM, { BDPA } },
2436 { "bdnzla", BBO(16,BODNZ,1,1), BBOATBI_MASK, PPCCOM, { BDA } },
2437 { "bdnla", BBO(16,BODNZ,1,1), BBOATBI_MASK, PWRCOM, { BDA } },
2438 { "bdz-", BBO(16,BODZ,0,0), BBOATBI_MASK, PPCCOM, { BDM } },
2439 { "bdz+", BBO(16,BODZ,0,0), BBOATBI_MASK, PPCCOM, { BDP } },
2440 { "bdz", BBO(16,BODZ,0,0), BBOATBI_MASK, COM, { BD } },
2441 { "bdzl-", BBO(16,BODZ,0,1), BBOATBI_MASK, PPCCOM, { BDM } },
2442 { "bdzl+", BBO(16,BODZ,0,1), BBOATBI_MASK, PPCCOM, { BDP } },
2443 { "bdzl", BBO(16,BODZ,0,1), BBOATBI_MASK, COM, { BD } },
2444 { "bdza-", BBO(16,BODZ,1,0), BBOATBI_MASK, PPCCOM, { BDMA } },
2445 { "bdza+", BBO(16,BODZ,1,0), BBOATBI_MASK, PPCCOM, { BDPA } },
2446 { "bdza", BBO(16,BODZ,1,0), BBOATBI_MASK, COM, { BDA } },
2447 { "bdzla-", BBO(16,BODZ,1,1), BBOATBI_MASK, PPCCOM, { BDMA } },
2448 { "bdzla+", BBO(16,BODZ,1,1), BBOATBI_MASK, PPCCOM, { BDPA } },
2449 { "bdzla", BBO(16,BODZ,1,1), BBOATBI_MASK, COM, { BDA } },
2450 { "blt-", BBOCB(16,BOT,CBLT,0,0), BBOATCB_MASK, PPCCOM, { CR, BDM } },
2451 { "blt+", BBOCB(16,BOT,CBLT,0,0), BBOATCB_MASK, PPCCOM, { CR, BDP } },
2452 { "blt", BBOCB(16,BOT,CBLT,0,0), BBOATCB_MASK, COM, { CR, BD } },
2453 { "bltl-", BBOCB(16,BOT,CBLT,0,1), BBOATCB_MASK, PPCCOM, { CR, BDM } },
2454 { "bltl+", BBOCB(16,BOT,CBLT,0,1), BBOATCB_MASK, PPCCOM, { CR, BDP } },
2455 { "bltl", BBOCB(16,BOT,CBLT,0,1), BBOATCB_MASK, COM, { CR, BD } },
2456 { "blta-", BBOCB(16,BOT,CBLT,1,0), BBOATCB_MASK, PPCCOM, { CR, BDMA } },
2457 { "blta+", BBOCB(16,BOT,CBLT,1,0), BBOATCB_MASK, PPCCOM, { CR, BDPA } },
2458 { "blta", BBOCB(16,BOT,CBLT,1,0), BBOATCB_MASK, COM, { CR, BDA } },
2459 { "bltla-", BBOCB(16,BOT,CBLT,1,1), BBOATCB_MASK, PPCCOM, { CR, BDMA } },
2460 { "bltla+", BBOCB(16,BOT,CBLT,1,1), BBOATCB_MASK, PPCCOM, { CR, BDPA } },
2461 { "bltla", BBOCB(16,BOT,CBLT,1,1), BBOATCB_MASK, COM, { CR, BDA } },
2462 { "bgt-", BBOCB(16,BOT,CBGT,0,0), BBOATCB_MASK, PPCCOM, { CR, BDM } },
2463 { "bgt+", BBOCB(16,BOT,CBGT,0,0), BBOATCB_MASK, PPCCOM, { CR, BDP } },
2464 { "bgt", BBOCB(16,BOT,CBGT,0,0), BBOATCB_MASK, COM, { CR, BD } },
2465 { "bgtl-", BBOCB(16,BOT,CBGT,0,1), BBOATCB_MASK, PPCCOM, { CR, BDM } },
2466 { "bgtl+", BBOCB(16,BOT,CBGT,0,1), BBOATCB_MASK, PPCCOM, { CR, BDP } },
2467 { "bgtl", BBOCB(16,BOT,CBGT,0,1), BBOATCB_MASK, COM, { CR, BD } },
2468 { "bgta-", BBOCB(16,BOT,CBGT,1,0), BBOATCB_MASK, PPCCOM, { CR, BDMA } },
2469 { "bgta+", BBOCB(16,BOT,CBGT,1,0), BBOATCB_MASK, PPCCOM, { CR, BDPA } },
2470 { "bgta", BBOCB(16,BOT,CBGT,1,0), BBOATCB_MASK, COM, { CR, BDA } },
2471 { "bgtla-", BBOCB(16,BOT,CBGT,1,1), BBOATCB_MASK, PPCCOM, { CR, BDMA } },
2472 { "bgtla+", BBOCB(16,BOT,CBGT,1,1), BBOATCB_MASK, PPCCOM, { CR, BDPA } },
2473 { "bgtla", BBOCB(16,BOT,CBGT,1,1), BBOATCB_MASK, COM, { CR, BDA } },
2474 { "beq-", BBOCB(16,BOT,CBEQ,0,0), BBOATCB_MASK, PPCCOM, { CR, BDM } },
2475 { "beq+", BBOCB(16,BOT,CBEQ,0,0), BBOATCB_MASK, PPCCOM, { CR, BDP } },
2476 { "beq", BBOCB(16,BOT,CBEQ,0,0), BBOATCB_MASK, COM, { CR, BD } },
2477 { "beql-", BBOCB(16,BOT,CBEQ,0,1), BBOATCB_MASK, PPCCOM, { CR, BDM } },
2478 { "beql+", BBOCB(16,BOT,CBEQ,0,1), BBOATCB_MASK, PPCCOM, { CR, BDP } },
2479 { "beql", BBOCB(16,BOT,CBEQ,0,1), BBOATCB_MASK, COM, { CR, BD } },
2480 { "beqa-", BBOCB(16,BOT,CBEQ,1,0), BBOATCB_MASK, PPCCOM, { CR, BDMA } },
2481 { "beqa+", BBOCB(16,BOT,CBEQ,1,0), BBOATCB_MASK, PPCCOM, { CR, BDPA } },
2482 { "beqa", BBOCB(16,BOT,CBEQ,1,0), BBOATCB_MASK, COM, { CR, BDA } },
2483 { "beqla-", BBOCB(16,BOT,CBEQ,1,1), BBOATCB_MASK, PPCCOM, { CR, BDMA } },
2484 { "beqla+", BBOCB(16,BOT,CBEQ,1,1), BBOATCB_MASK, PPCCOM, { CR, BDPA } },
2485 { "beqla", BBOCB(16,BOT,CBEQ,1,1), BBOATCB_MASK, COM, { CR, BDA } },
2486 { "bso-", BBOCB(16,BOT,CBSO,0,0), BBOATCB_MASK, PPCCOM, { CR, BDM } },
2487 { "bso+", BBOCB(16,BOT,CBSO,0,0), BBOATCB_MASK, PPCCOM, { CR, BDP } },
2488 { "bso", BBOCB(16,BOT,CBSO,0,0), BBOATCB_MASK, COM, { CR, BD } },
2489 { "bsol-", BBOCB(16,BOT,CBSO,0,1), BBOATCB_MASK, PPCCOM, { CR, BDM } },
2490 { "bsol+", BBOCB(16,BOT,CBSO,0,1), BBOATCB_MASK, PPCCOM, { CR, BDP } },
2491 { "bsol", BBOCB(16,BOT,CBSO,0,1), BBOATCB_MASK, COM, { CR, BD } },
2492 { "bsoa-", BBOCB(16,BOT,CBSO,1,0), BBOATCB_MASK, PPCCOM, { CR, BDMA } },
2493 { "bsoa+", BBOCB(16,BOT,CBSO,1,0), BBOATCB_MASK, PPCCOM, { CR, BDPA } },
2494 { "bsoa", BBOCB(16,BOT,CBSO,1,0), BBOATCB_MASK, COM, { CR, BDA } },
2495 { "bsola-", BBOCB(16,BOT,CBSO,1,1), BBOATCB_MASK, PPCCOM, { CR, BDMA } },
2496 { "bsola+", BBOCB(16,BOT,CBSO,1,1), BBOATCB_MASK, PPCCOM, { CR, BDPA } },
2497 { "bsola", BBOCB(16,BOT,CBSO,1,1), BBOATCB_MASK, COM, { CR, BDA } },
2498 { "bun-", BBOCB(16,BOT,CBSO,0,0), BBOATCB_MASK, PPCCOM, { CR, BDM } },
2499 { "bun+", BBOCB(16,BOT,CBSO,0,0), BBOATCB_MASK, PPCCOM, { CR, BDP } },
2500 { "bun", BBOCB(16,BOT,CBSO,0,0), BBOATCB_MASK, PPCCOM, { CR, BD } },
2501 { "bunl-", BBOCB(16,BOT,CBSO,0,1), BBOATCB_MASK, PPCCOM, { CR, BDM } },
2502 { "bunl+", BBOCB(16,BOT,CBSO,0,1), BBOATCB_MASK, PPCCOM, { CR, BDP } },
2503 { "bunl", BBOCB(16,BOT,CBSO,0,1), BBOATCB_MASK, PPCCOM, { CR, BD } },
2504 { "buna-", BBOCB(16,BOT,CBSO,1,0), BBOATCB_MASK, PPCCOM, { CR, BDMA } },
2505 { "buna+", BBOCB(16,BOT,CBSO,1,0), BBOATCB_MASK, PPCCOM, { CR, BDPA } },
2506 { "buna", BBOCB(16,BOT,CBSO,1,0), BBOATCB_MASK, PPCCOM, { CR, BDA } },
2507 { "bunla-", BBOCB(16,BOT,CBSO,1,1), BBOATCB_MASK, PPCCOM, { CR, BDMA } },
2508 { "bunla+", BBOCB(16,BOT,CBSO,1,1), BBOATCB_MASK, PPCCOM, { CR, BDPA } },
2509 { "bunla", BBOCB(16,BOT,CBSO,1,1), BBOATCB_MASK, PPCCOM, { CR, BDA } },
2510 { "bge-", BBOCB(16,BOF,CBLT,0,0), BBOATCB_MASK, PPCCOM, { CR, BDM } },
2511 { "bge+", BBOCB(16,BOF,CBLT,0,0), BBOATCB_MASK, PPCCOM, { CR, BDP } },
2512 { "bge", BBOCB(16,BOF,CBLT,0,0), BBOATCB_MASK, COM, { CR, BD } },
2513 { "bgel-", BBOCB(16,BOF,CBLT,0,1), BBOATCB_MASK, PPCCOM, { CR, BDM } },
2514 { "bgel+", BBOCB(16,BOF,CBLT,0,1), BBOATCB_MASK, PPCCOM, { CR, BDP } },
2515 { "bgel", BBOCB(16,BOF,CBLT,0,1), BBOATCB_MASK, COM, { CR, BD } },
2516 { "bgea-", BBOCB(16,BOF,CBLT,1,0), BBOATCB_MASK, PPCCOM, { CR, BDMA } },
2517 { "bgea+", BBOCB(16,BOF,CBLT,1,0), BBOATCB_MASK, PPCCOM, { CR, BDPA } },
2518 { "bgea", BBOCB(16,BOF,CBLT,1,0), BBOATCB_MASK, COM, { CR, BDA } },
2519 { "bgela-", BBOCB(16,BOF,CBLT,1,1), BBOATCB_MASK, PPCCOM, { CR, BDMA } },
2520 { "bgela+", BBOCB(16,BOF,CBLT,1,1), BBOATCB_MASK, PPCCOM, { CR, BDPA } },
2521 { "bgela", BBOCB(16,BOF,CBLT,1,1), BBOATCB_MASK, COM, { CR, BDA } },
2522 { "bnl-", BBOCB(16,BOF,CBLT,0,0), BBOATCB_MASK, PPCCOM, { CR, BDM } },
2523 { "bnl+", BBOCB(16,BOF,CBLT,0,0), BBOATCB_MASK, PPCCOM, { CR, BDP } },
2524 { "bnl", BBOCB(16,BOF,CBLT,0,0), BBOATCB_MASK, COM, { CR, BD } },
2525 { "bnll-", BBOCB(16,BOF,CBLT,0,1), BBOATCB_MASK, PPCCOM, { CR, BDM } },
2526 { "bnll+", BBOCB(16,BOF,CBLT,0,1), BBOATCB_MASK, PPCCOM, { CR, BDP } },
2527 { "bnll", BBOCB(16,BOF,CBLT,0,1), BBOATCB_MASK, COM, { CR, BD } },
2528 { "bnla-", BBOCB(16,BOF,CBLT,1,0), BBOATCB_MASK, PPCCOM, { CR, BDMA } },
2529 { "bnla+", BBOCB(16,BOF,CBLT,1,0), BBOATCB_MASK, PPCCOM, { CR, BDPA } },
2530 { "bnla", BBOCB(16,BOF,CBLT,1,0), BBOATCB_MASK, COM, { CR, BDA } },
2531 { "bnlla-", BBOCB(16,BOF,CBLT,1,1), BBOATCB_MASK, PPCCOM, { CR, BDMA } },
2532 { "bnlla+", BBOCB(16,BOF,CBLT,1,1), BBOATCB_MASK, PPCCOM, { CR, BDPA } },
2533 { "bnlla", BBOCB(16,BOF,CBLT,1,1), BBOATCB_MASK, COM, { CR, BDA } },
2534 { "ble-", BBOCB(16,BOF,CBGT,0,0), BBOATCB_MASK, PPCCOM, { CR, BDM } },
2535 { "ble+", BBOCB(16,BOF,CBGT,0,0), BBOATCB_MASK, PPCCOM, { CR, BDP } },
2536 { "ble", BBOCB(16,BOF,CBGT,0,0), BBOATCB_MASK, COM, { CR, BD } },
2537 { "blel-", BBOCB(16,BOF,CBGT,0,1), BBOATCB_MASK, PPCCOM, { CR, BDM } },
2538 { "blel+", BBOCB(16,BOF,CBGT,0,1), BBOATCB_MASK, PPCCOM, { CR, BDP } },
2539 { "blel", BBOCB(16,BOF,CBGT,0,1), BBOATCB_MASK, COM, { CR, BD } },
2540 { "blea-", BBOCB(16,BOF,CBGT,1,0), BBOATCB_MASK, PPCCOM, { CR, BDMA } },
2541 { "blea+", BBOCB(16,BOF,CBGT,1,0), BBOATCB_MASK, PPCCOM, { CR, BDPA } },
2542 { "blea", BBOCB(16,BOF,CBGT,1,0), BBOATCB_MASK, COM, { CR, BDA } },
2543 { "blela-", BBOCB(16,BOF,CBGT,1,1), BBOATCB_MASK, PPCCOM, { CR, BDMA } },
2544 { "blela+", BBOCB(16,BOF,CBGT,1,1), BBOATCB_MASK, PPCCOM, { CR, BDPA } },
2545 { "blela", BBOCB(16,BOF,CBGT,1,1), BBOATCB_MASK, COM, { CR, BDA } },
2546 { "bng-", BBOCB(16,BOF,CBGT,0,0), BBOATCB_MASK, PPCCOM, { CR, BDM } },
2547 { "bng+", BBOCB(16,BOF,CBGT,0,0), BBOATCB_MASK, PPCCOM, { CR, BDP } },
2548 { "bng", BBOCB(16,BOF,CBGT,0,0), BBOATCB_MASK, COM, { CR, BD } },
2549 { "bngl-", BBOCB(16,BOF,CBGT,0,1), BBOATCB_MASK, PPCCOM, { CR, BDM } },
2550 { "bngl+", BBOCB(16,BOF,CBGT,0,1), BBOATCB_MASK, PPCCOM, { CR, BDP } },
2551 { "bngl", BBOCB(16,BOF,CBGT,0,1), BBOATCB_MASK, COM, { CR, BD } },
2552 { "bnga-", BBOCB(16,BOF,CBGT,1,0), BBOATCB_MASK, PPCCOM, { CR, BDMA } },
2553 { "bnga+", BBOCB(16,BOF,CBGT,1,0), BBOATCB_MASK, PPCCOM, { CR, BDPA } },
2554 { "bnga", BBOCB(16,BOF,CBGT,1,0), BBOATCB_MASK, COM, { CR, BDA } },
2555 { "bngla-", BBOCB(16,BOF,CBGT,1,1), BBOATCB_MASK, PPCCOM, { CR, BDMA } },
2556 { "bngla+", BBOCB(16,BOF,CBGT,1,1), BBOATCB_MASK, PPCCOM, { CR, BDPA } },
2557 { "bngla", BBOCB(16,BOF,CBGT,1,1), BBOATCB_MASK, COM, { CR, BDA } },
2558 { "bne-", BBOCB(16,BOF,CBEQ,0,0), BBOATCB_MASK, PPCCOM, { CR, BDM } },
2559 { "bne+", BBOCB(16,BOF,CBEQ,0,0), BBOATCB_MASK, PPCCOM, { CR, BDP } },
2560 { "bne", BBOCB(16,BOF,CBEQ,0,0), BBOATCB_MASK, COM, { CR, BD } },
2561 { "bnel-", BBOCB(16,BOF,CBEQ,0,1), BBOATCB_MASK, PPCCOM, { CR, BDM } },
2562 { "bnel+", BBOCB(16,BOF,CBEQ,0,1), BBOATCB_MASK, PPCCOM, { CR, BDP } },
2563 { "bnel", BBOCB(16,BOF,CBEQ,0,1), BBOATCB_MASK, COM, { CR, BD } },
2564 { "bnea-", BBOCB(16,BOF,CBEQ,1,0), BBOATCB_MASK, PPCCOM, { CR, BDMA } },
2565 { "bnea+", BBOCB(16,BOF,CBEQ,1,0), BBOATCB_MASK, PPCCOM, { CR, BDPA } },
2566 { "bnea", BBOCB(16,BOF,CBEQ,1,0), BBOATCB_MASK, COM, { CR, BDA } },
2567 { "bnela-", BBOCB(16,BOF,CBEQ,1,1), BBOATCB_MASK, PPCCOM, { CR, BDMA } },
2568 { "bnela+", BBOCB(16,BOF,CBEQ,1,1), BBOATCB_MASK, PPCCOM, { CR, BDPA } },
2569 { "bnela", BBOCB(16,BOF,CBEQ,1,1), BBOATCB_MASK, COM, { CR, BDA } },
2570 { "bns-", BBOCB(16,BOF,CBSO,0,0), BBOATCB_MASK, PPCCOM, { CR, BDM } },
2571 { "bns+", BBOCB(16,BOF,CBSO,0,0), BBOATCB_MASK, PPCCOM, { CR, BDP } },
2572 { "bns", BBOCB(16,BOF,CBSO,0,0), BBOATCB_MASK, COM, { CR, BD } },
2573 { "bnsl-", BBOCB(16,BOF,CBSO,0,1), BBOATCB_MASK, PPCCOM, { CR, BDM } },
2574 { "bnsl+", BBOCB(16,BOF,CBSO,0,1), BBOATCB_MASK, PPCCOM, { CR, BDP } },
2575 { "bnsl", BBOCB(16,BOF,CBSO,0,1), BBOATCB_MASK, COM, { CR, BD } },
2576 { "bnsa-", BBOCB(16,BOF,CBSO,1,0), BBOATCB_MASK, PPCCOM, { CR, BDMA } },
2577 { "bnsa+", BBOCB(16,BOF,CBSO,1,0), BBOATCB_MASK, PPCCOM, { CR, BDPA } },
2578 { "bnsa", BBOCB(16,BOF,CBSO,1,0), BBOATCB_MASK, COM, { CR, BDA } },
2579 { "bnsla-", BBOCB(16,BOF,CBSO,1,1), BBOATCB_MASK, PPCCOM, { CR, BDMA } },
2580 { "bnsla+", BBOCB(16,BOF,CBSO,1,1), BBOATCB_MASK, PPCCOM, { CR, BDPA } },
2581 { "bnsla", BBOCB(16,BOF,CBSO,1,1), BBOATCB_MASK, COM, { CR, BDA } },
2582 { "bnu-", BBOCB(16,BOF,CBSO,0,0), BBOATCB_MASK, PPCCOM, { CR, BDM } },
2583 { "bnu+", BBOCB(16,BOF,CBSO,0,0), BBOATCB_MASK, PPCCOM, { CR, BDP } },
2584 { "bnu", BBOCB(16,BOF,CBSO,0,0), BBOATCB_MASK, PPCCOM, { CR, BD } },
2585 { "bnul-", BBOCB(16,BOF,CBSO,0,1), BBOATCB_MASK, PPCCOM, { CR, BDM } },
2586 { "bnul+", BBOCB(16,BOF,CBSO,0,1), BBOATCB_MASK, PPCCOM, { CR, BDP } },
2587 { "bnul", BBOCB(16,BOF,CBSO,0,1), BBOATCB_MASK, PPCCOM, { CR, BD } },
2588 { "bnua-", BBOCB(16,BOF,CBSO,1,0), BBOATCB_MASK, PPCCOM, { CR, BDMA } },
2589 { "bnua+", BBOCB(16,BOF,CBSO,1,0), BBOATCB_MASK, PPCCOM, { CR, BDPA } },
2590 { "bnua", BBOCB(16,BOF,CBSO,1,0), BBOATCB_MASK, PPCCOM, { CR, BDA } },
2591 { "bnula-", BBOCB(16,BOF,CBSO,1,1), BBOATCB_MASK, PPCCOM, { CR, BDMA } },
2592 { "bnula+", BBOCB(16,BOF,CBSO,1,1), BBOATCB_MASK, PPCCOM, { CR, BDPA } },
2593 { "bnula", BBOCB(16,BOF,CBSO,1,1), BBOATCB_MASK, PPCCOM, { CR, BDA } },
2594 { "bdnzt-", BBO(16,BODNZT,0,0), BBOY_MASK, NOPOWER4, { BI, BDM } },
2595 { "bdnzt+", BBO(16,BODNZT,0,0), BBOY_MASK, NOPOWER4, { BI, BDP } },
2596 { "bdnzt", BBO(16,BODNZT,0,0), BBOY_MASK, PPCCOM, { BI, BD } },
2597 { "bdnztl-", BBO(16,BODNZT,0,1), BBOY_MASK, NOPOWER4, { BI, BDM } },
2598 { "bdnztl+", BBO(16,BODNZT,0,1), BBOY_MASK, NOPOWER4, { BI, BDP } },
2599 { "bdnztl", BBO(16,BODNZT,0,1), BBOY_MASK, PPCCOM, { BI, BD } },
2600 { "bdnzta-", BBO(16,BODNZT,1,0), BBOY_MASK, NOPOWER4, { BI, BDMA } },
2601 { "bdnzta+", BBO(16,BODNZT,1,0), BBOY_MASK, NOPOWER4, { BI, BDPA } },
2602 { "bdnzta", BBO(16,BODNZT,1,0), BBOY_MASK, PPCCOM, { BI, BDA } },
2603 { "bdnztla-",BBO(16,BODNZT,1,1), BBOY_MASK, NOPOWER4, { BI, BDMA } },
2604 { "bdnztla+",BBO(16,BODNZT,1,1), BBOY_MASK, NOPOWER4, { BI, BDPA } },
2605 { "bdnztla", BBO(16,BODNZT,1,1), BBOY_MASK, PPCCOM, { BI, BDA } },
2606 { "bdnzf-", BBO(16,BODNZF,0,0), BBOY_MASK, NOPOWER4, { BI, BDM } },
2607 { "bdnzf+", BBO(16,BODNZF,0,0), BBOY_MASK, NOPOWER4, { BI, BDP } },
2608 { "bdnzf", BBO(16,BODNZF,0,0), BBOY_MASK, PPCCOM, { BI, BD } },
2609 { "bdnzfl-", BBO(16,BODNZF,0,1), BBOY_MASK, NOPOWER4, { BI, BDM } },
2610 { "bdnzfl+", BBO(16,BODNZF,0,1), BBOY_MASK, NOPOWER4, { BI, BDP } },
2611 { "bdnzfl", BBO(16,BODNZF,0,1), BBOY_MASK, PPCCOM, { BI, BD } },
2612 { "bdnzfa-", BBO(16,BODNZF,1,0), BBOY_MASK, NOPOWER4, { BI, BDMA } },
2613 { "bdnzfa+", BBO(16,BODNZF,1,0), BBOY_MASK, NOPOWER4, { BI, BDPA } },
2614 { "bdnzfa", BBO(16,BODNZF,1,0), BBOY_MASK, PPCCOM, { BI, BDA } },
2615 { "bdnzfla-",BBO(16,BODNZF,1,1), BBOY_MASK, NOPOWER4, { BI, BDMA } },
2616 { "bdnzfla+",BBO(16,BODNZF,1,1), BBOY_MASK, NOPOWER4, { BI, BDPA } },
2617 { "bdnzfla", BBO(16,BODNZF,1,1), BBOY_MASK, PPCCOM, { BI, BDA } },
2618 { "bt-", BBO(16,BOT,0,0), BBOAT_MASK, PPCCOM, { BI, BDM } },
2619 { "bt+", BBO(16,BOT,0,0), BBOAT_MASK, PPCCOM, { BI, BDP } },
2620 { "bt", BBO(16,BOT,0,0), BBOAT_MASK, PPCCOM, { BI, BD } },
2621 { "bbt", BBO(16,BOT,0,0), BBOAT_MASK, PWRCOM, { BI, BD } },
2622 { "btl-", BBO(16,BOT,0,1), BBOAT_MASK, PPCCOM, { BI, BDM } },
2623 { "btl+", BBO(16,BOT,0,1), BBOAT_MASK, PPCCOM, { BI, BDP } },
2624 { "btl", BBO(16,BOT,0,1), BBOAT_MASK, PPCCOM, { BI, BD } },
2625 { "bbtl", BBO(16,BOT,0,1), BBOAT_MASK, PWRCOM, { BI, BD } },
2626 { "bta-", BBO(16,BOT,1,0), BBOAT_MASK, PPCCOM, { BI, BDMA } },
2627 { "bta+", BBO(16,BOT,1,0), BBOAT_MASK, PPCCOM, { BI, BDPA } },
2628 { "bta", BBO(16,BOT,1,0), BBOAT_MASK, PPCCOM, { BI, BDA } },
2629 { "bbta", BBO(16,BOT,1,0), BBOAT_MASK, PWRCOM, { BI, BDA } },
2630 { "btla-", BBO(16,BOT,1,1), BBOAT_MASK, PPCCOM, { BI, BDMA } },
2631 { "btla+", BBO(16,BOT,1,1), BBOAT_MASK, PPCCOM, { BI, BDPA } },
2632 { "btla", BBO(16,BOT,1,1), BBOAT_MASK, PPCCOM, { BI, BDA } },
2633 { "bbtla", BBO(16,BOT,1,1), BBOAT_MASK, PWRCOM, { BI, BDA } },
2634 { "bf-", BBO(16,BOF,0,0), BBOAT_MASK, PPCCOM, { BI, BDM } },
2635 { "bf+", BBO(16,BOF,0,0), BBOAT_MASK, PPCCOM, { BI, BDP } },
2636 { "bf", BBO(16,BOF,0,0), BBOAT_MASK, PPCCOM, { BI, BD } },
2637 { "bbf", BBO(16,BOF,0,0), BBOAT_MASK, PWRCOM, { BI, BD } },
2638 { "bfl-", BBO(16,BOF,0,1), BBOAT_MASK, PPCCOM, { BI, BDM } },
2639 { "bfl+", BBO(16,BOF,0,1), BBOAT_MASK, PPCCOM, { BI, BDP } },
2640 { "bfl", BBO(16,BOF,0,1), BBOAT_MASK, PPCCOM, { BI, BD } },
2641 { "bbfl", BBO(16,BOF,0,1), BBOAT_MASK, PWRCOM, { BI, BD } },
2642 { "bfa-", BBO(16,BOF,1,0), BBOAT_MASK, PPCCOM, { BI, BDMA } },
2643 { "bfa+", BBO(16,BOF,1,0), BBOAT_MASK, PPCCOM, { BI, BDPA } },
2644 { "bfa", BBO(16,BOF,1,0), BBOAT_MASK, PPCCOM, { BI, BDA } },
2645 { "bbfa", BBO(16,BOF,1,0), BBOAT_MASK, PWRCOM, { BI, BDA } },
2646 { "bfla-", BBO(16,BOF,1,1), BBOAT_MASK, PPCCOM, { BI, BDMA } },
2647 { "bfla+", BBO(16,BOF,1,1), BBOAT_MASK, PPCCOM, { BI, BDPA } },
2648 { "bfla", BBO(16,BOF,1,1), BBOAT_MASK, PPCCOM, { BI, BDA } },
2649 { "bbfla", BBO(16,BOF,1,1), BBOAT_MASK, PWRCOM, { BI, BDA } },
2650 { "bdzt-", BBO(16,BODZT,0,0), BBOY_MASK, NOPOWER4, { BI, BDM } },
2651 { "bdzt+", BBO(16,BODZT,0,0), BBOY_MASK, NOPOWER4, { BI, BDP } },
2652 { "bdzt", BBO(16,BODZT,0,0), BBOY_MASK, PPCCOM, { BI, BD } },
2653 { "bdztl-", BBO(16,BODZT,0,1), BBOY_MASK, NOPOWER4, { BI, BDM } },
2654 { "bdztl+", BBO(16,BODZT,0,1), BBOY_MASK, NOPOWER4, { BI, BDP } },
2655 { "bdztl", BBO(16,BODZT,0,1), BBOY_MASK, PPCCOM, { BI, BD } },
2656 { "bdzta-", BBO(16,BODZT,1,0), BBOY_MASK, NOPOWER4, { BI, BDMA } },
2657 { "bdzta+", BBO(16,BODZT,1,0), BBOY_MASK, NOPOWER4, { BI, BDPA } },
2658 { "bdzta", BBO(16,BODZT,1,0), BBOY_MASK, PPCCOM, { BI, BDA } },
2659 { "bdztla-", BBO(16,BODZT,1,1), BBOY_MASK, NOPOWER4, { BI, BDMA } },
2660 { "bdztla+", BBO(16,BODZT,1,1), BBOY_MASK, NOPOWER4, { BI, BDPA } },
2661 { "bdztla", BBO(16,BODZT,1,1), BBOY_MASK, PPCCOM, { BI, BDA } },
2662 { "bdzf-", BBO(16,BODZF,0,0), BBOY_MASK, NOPOWER4, { BI, BDM } },
2663 { "bdzf+", BBO(16,BODZF,0,0), BBOY_MASK, NOPOWER4, { BI, BDP } },
2664 { "bdzf", BBO(16,BODZF,0,0), BBOY_MASK, PPCCOM, { BI, BD } },
2665 { "bdzfl-", BBO(16,BODZF,0,1), BBOY_MASK, NOPOWER4, { BI, BDM } },
2666 { "bdzfl+", BBO(16,BODZF,0,1), BBOY_MASK, NOPOWER4, { BI, BDP } },
2667 { "bdzfl", BBO(16,BODZF,0,1), BBOY_MASK, PPCCOM, { BI, BD } },
2668 { "bdzfa-", BBO(16,BODZF,1,0), BBOY_MASK, NOPOWER4, { BI, BDMA } },
2669 { "bdzfa+", BBO(16,BODZF,1,0), BBOY_MASK, NOPOWER4, { BI, BDPA } },
2670 { "bdzfa", BBO(16,BODZF,1,0), BBOY_MASK, PPCCOM, { BI, BDA } },
2671 { "bdzfla-", BBO(16,BODZF,1,1), BBOY_MASK, NOPOWER4, { BI, BDMA } },
2672 { "bdzfla+", BBO(16,BODZF,1,1), BBOY_MASK, NOPOWER4, { BI, BDPA } },
2673 { "bdzfla", BBO(16,BODZF,1,1), BBOY_MASK, PPCCOM, { BI, BDA } },
2674 { "bc-", B(16,0,0), B_MASK, PPCCOM, { BOE, BI, BDM } },
2675 { "bc+", B(16,0,0), B_MASK, PPCCOM, { BOE, BI, BDP } },
2676 { "bc", B(16,0,0), B_MASK, COM, { BO, BI, BD } },
2677 { "bcl-", B(16,0,1), B_MASK, PPCCOM, { BOE, BI, BDM } },
2678 { "bcl+", B(16,0,1), B_MASK, PPCCOM, { BOE, BI, BDP } },
2679 { "bcl", B(16,0,1), B_MASK, COM, { BO, BI, BD } },
2680 { "bca-", B(16,1,0), B_MASK, PPCCOM, { BOE, BI, BDMA } },
2681 { "bca+", B(16,1,0), B_MASK, PPCCOM, { BOE, BI, BDPA } },
2682 { "bca", B(16,1,0), B_MASK, COM, { BO, BI, BDA } },
2683 { "bcla-", B(16,1,1), B_MASK, PPCCOM, { BOE, BI, BDMA } },
2684 { "bcla+", B(16,1,1), B_MASK, PPCCOM, { BOE, BI, BDPA } },
2685 { "bcla", B(16,1,1), B_MASK, COM, { BO, BI, BDA } },
2687 { "sc", SC(17,1,0), 0xffffffff, PPC, { 0 } },
2688 { "svc", SC(17,0,0), SC_MASK, POWER, { LEV, FL1, FL2 } },
2689 { "svcl", SC(17,0,1), SC_MASK, POWER, { LEV, FL1, FL2 } },
2690 { "svca", SC(17,1,0), SC_MASK, PWRCOM, { SV } },
2691 { "svcla", SC(17,1,1), SC_MASK, POWER, { SV } },
2693 { "b", B(18,0,0), B_MASK, COM, { LI } },
2694 { "bl", B(18,0,1), B_MASK, COM, { LI } },
2695 { "ba", B(18,1,0), B_MASK, COM, { LIA } },
2696 { "bla", B(18,1,1), B_MASK, COM, { LIA } },
2698 { "mcrf", XL(19,0), XLBB_MASK|(3 << 21)|(3 << 16), COM, { BF, BFA } },
2700 { "blr", XLO(19,BOU,16,0), XLBOBIBB_MASK, PPCCOM, { 0 } },
2701 { "br", XLO(19,BOU,16,0), XLBOBIBB_MASK, PWRCOM, { 0 } },
2702 { "blrl", XLO(19,BOU,16,1), XLBOBIBB_MASK, PPCCOM, { 0 } },
2703 { "brl", XLO(19,BOU,16,1), XLBOBIBB_MASK, PWRCOM, { 0 } },
2704 { "bdnzlr", XLO(19,BODNZ,16,0), XLBOBIBB_MASK, PPCCOM, { 0 } },
2705 { "bdnzlr-", XLO(19,BODNZ,16,0), XLBOBIBB_MASK, NOPOWER4, { 0 } },
2706 { "bdnzlr+", XLO(19,BODNZP,16,0), XLBOBIBB_MASK, NOPOWER4, { 0 } },
2707 { "bdnzlr-", XLO(19,BODNZM4,16,0), XLBOBIBB_MASK, POWER4, { 0 } },
2708 { "bdnzlr+", XLO(19,BODNZP4,16,0), XLBOBIBB_MASK, POWER4, { 0 } },
2709 { "bdnzlrl", XLO(19,BODNZ,16,1), XLBOBIBB_MASK, PPCCOM, { 0 } },
2710 { "bdnzlrl-",XLO(19,BODNZ,16,1), XLBOBIBB_MASK, NOPOWER4, { 0 } },
2711 { "bdnzlrl+",XLO(19,BODNZP,16,1), XLBOBIBB_MASK, NOPOWER4, { 0 } },
2712 { "bdnzlrl-",XLO(19,BODNZM4,16,1), XLBOBIBB_MASK, POWER4, { 0 } },
2713 { "bdnzlrl+",XLO(19,BODNZP4,16,1), XLBOBIBB_MASK, POWER4, { 0 } },
2714 { "bdzlr", XLO(19,BODZ,16,0), XLBOBIBB_MASK, PPCCOM, { 0 } },
2715 { "bdzlr-", XLO(19,BODZ,16,0), XLBOBIBB_MASK, NOPOWER4, { 0 } },
2716 { "bdzlr+", XLO(19,BODZP,16,0), XLBOBIBB_MASK, NOPOWER4, { 0 } },
2717 { "bdzlr-", XLO(19,BODZM4,16,0), XLBOBIBB_MASK, POWER4, { 0 } },
2718 { "bdzlr+", XLO(19,BODZP4,16,0), XLBOBIBB_MASK, POWER4, { 0 } },
2719 { "bdzlrl", XLO(19,BODZ,16,1), XLBOBIBB_MASK, PPCCOM, { 0 } },
2720 { "bdzlrl-", XLO(19,BODZ,16,1), XLBOBIBB_MASK, NOPOWER4, { 0 } },
2721 { "bdzlrl+", XLO(19,BODZP,16,1), XLBOBIBB_MASK, NOPOWER4, { 0 } },
2722 { "bdzlrl-", XLO(19,BODZM4,16,1), XLBOBIBB_MASK, POWER4, { 0 } },
2723 { "bdzlrl+", XLO(19,BODZP4,16,1), XLBOBIBB_MASK, POWER4, { 0 } },
2724 { "bltlr", XLOCB(19,BOT,CBLT,16,0), XLBOCBBB_MASK, PPCCOM, { CR } },
2725 { "bltlr-", XLOCB(19,BOT,CBLT,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2726 { "bltlr+", XLOCB(19,BOTP,CBLT,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2727 { "bltlr-", XLOCB(19,BOTM4,CBLT,16,0), XLBOCBBB_MASK, POWER4, { CR } },
2728 { "bltlr+", XLOCB(19,BOTP4,CBLT,16,0), XLBOCBBB_MASK, POWER4, { CR } },
2729 { "bltr", XLOCB(19,BOT,CBLT,16,0), XLBOCBBB_MASK, PWRCOM, { CR } },
2730 { "bltlrl", XLOCB(19,BOT,CBLT,16,1), XLBOCBBB_MASK, PPCCOM, { CR } },
2731 { "bltlrl-", XLOCB(19,BOT,CBLT,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2732 { "bltlrl+", XLOCB(19,BOTP,CBLT,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2733 { "bltlrl-", XLOCB(19,BOTM4,CBLT,16,1), XLBOCBBB_MASK, POWER4, { CR } },
2734 { "bltlrl+", XLOCB(19,BOTP4,CBLT,16,1), XLBOCBBB_MASK, POWER4, { CR } },
2735 { "bltrl", XLOCB(19,BOT,CBLT,16,1), XLBOCBBB_MASK, PWRCOM, { CR } },
2736 { "bgtlr", XLOCB(19,BOT,CBGT,16,0), XLBOCBBB_MASK, PPCCOM, { CR } },
2737 { "bgtlr-", XLOCB(19,BOT,CBGT,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2738 { "bgtlr+", XLOCB(19,BOTP,CBGT,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2739 { "bgtlr-", XLOCB(19,BOTM4,CBGT,16,0), XLBOCBBB_MASK, POWER4, { CR } },
2740 { "bgtlr+", XLOCB(19,BOTP4,CBGT,16,0), XLBOCBBB_MASK, POWER4, { CR } },
2741 { "bgtr", XLOCB(19,BOT,CBGT,16,0), XLBOCBBB_MASK, PWRCOM, { CR } },
2742 { "bgtlrl", XLOCB(19,BOT,CBGT,16,1), XLBOCBBB_MASK, PPCCOM, { CR } },
2743 { "bgtlrl-", XLOCB(19,BOT,CBGT,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2744 { "bgtlrl+", XLOCB(19,BOTP,CBGT,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2745 { "bgtlrl-", XLOCB(19,BOTM4,CBGT,16,1), XLBOCBBB_MASK, POWER4, { CR } },
2746 { "bgtlrl+", XLOCB(19,BOTP4,CBGT,16,1), XLBOCBBB_MASK, POWER4, { CR } },
2747 { "bgtrl", XLOCB(19,BOT,CBGT,16,1), XLBOCBBB_MASK, PWRCOM, { CR } },
2748 { "beqlr", XLOCB(19,BOT,CBEQ,16,0), XLBOCBBB_MASK, PPCCOM, { CR } },
2749 { "beqlr-", XLOCB(19,BOT,CBEQ,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2750 { "beqlr+", XLOCB(19,BOTP,CBEQ,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2751 { "beqlr-", XLOCB(19,BOTM4,CBEQ,16,0), XLBOCBBB_MASK, POWER4, { CR } },
2752 { "beqlr+", XLOCB(19,BOTP4,CBEQ,16,0), XLBOCBBB_MASK, POWER4, { CR } },
2753 { "beqr", XLOCB(19,BOT,CBEQ,16,0), XLBOCBBB_MASK, PWRCOM, { CR } },
2754 { "beqlrl", XLOCB(19,BOT,CBEQ,16,1), XLBOCBBB_MASK, PPCCOM, { CR } },
2755 { "beqlrl-", XLOCB(19,BOT,CBEQ,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2756 { "beqlrl+", XLOCB(19,BOTP,CBEQ,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2757 { "beqlrl-", XLOCB(19,BOTM4,CBEQ,16,1), XLBOCBBB_MASK, POWER4, { CR } },
2758 { "beqlrl+", XLOCB(19,BOTP4,CBEQ,16,1), XLBOCBBB_MASK, POWER4, { CR } },
2759 { "beqrl", XLOCB(19,BOT,CBEQ,16,1), XLBOCBBB_MASK, PWRCOM, { CR } },
2760 { "bsolr", XLOCB(19,BOT,CBSO,16,0), XLBOCBBB_MASK, PPCCOM, { CR } },
2761 { "bsolr-", XLOCB(19,BOT,CBSO,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2762 { "bsolr+", XLOCB(19,BOTP,CBSO,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2763 { "bsolr-", XLOCB(19,BOTM4,CBSO,16,0), XLBOCBBB_MASK, POWER4, { CR } },
2764 { "bsolr+", XLOCB(19,BOTP4,CBSO,16,0), XLBOCBBB_MASK, POWER4, { CR } },
2765 { "bsor", XLOCB(19,BOT,CBSO,16,0), XLBOCBBB_MASK, PWRCOM, { CR } },
2766 { "bsolrl", XLOCB(19,BOT,CBSO,16,1), XLBOCBBB_MASK, PPCCOM, { CR } },
2767 { "bsolrl-", XLOCB(19,BOT,CBSO,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2768 { "bsolrl+", XLOCB(19,BOTP,CBSO,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2769 { "bsolrl-", XLOCB(19,BOTM4,CBSO,16,1), XLBOCBBB_MASK, POWER4, { CR } },
2770 { "bsolrl+", XLOCB(19,BOTP4,CBSO,16,1), XLBOCBBB_MASK, POWER4, { CR } },
2771 { "bsorl", XLOCB(19,BOT,CBSO,16,1), XLBOCBBB_MASK, PWRCOM, { CR } },
2772 { "bunlr", XLOCB(19,BOT,CBSO,16,0), XLBOCBBB_MASK, PPCCOM, { CR } },
2773 { "bunlr-", XLOCB(19,BOT,CBSO,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2774 { "bunlr+", XLOCB(19,BOTP,CBSO,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2775 { "bunlr-", XLOCB(19,BOTM4,CBSO,16,0), XLBOCBBB_MASK, POWER4, { CR } },
2776 { "bunlr+", XLOCB(19,BOTP4,CBSO,16,0), XLBOCBBB_MASK, POWER4, { CR } },
2777 { "bunlrl", XLOCB(19,BOT,CBSO,16,1), XLBOCBBB_MASK, PPCCOM, { CR } },
2778 { "bunlrl-", XLOCB(19,BOT,CBSO,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2779 { "bunlrl+", XLOCB(19,BOTP,CBSO,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2780 { "bunlrl-", XLOCB(19,BOTM4,CBSO,16,1), XLBOCBBB_MASK, POWER4, { CR } },
2781 { "bunlrl+", XLOCB(19,BOTP4,CBSO,16,1), XLBOCBBB_MASK, POWER4, { CR } },
2782 { "bgelr", XLOCB(19,BOF,CBLT,16,0), XLBOCBBB_MASK, PPCCOM, { CR } },
2783 { "bgelr-", XLOCB(19,BOF,CBLT,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2784 { "bgelr+", XLOCB(19,BOFP,CBLT,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2785 { "bgelr-", XLOCB(19,BOFM4,CBLT,16,0), XLBOCBBB_MASK, POWER4, { CR } },
2786 { "bgelr+", XLOCB(19,BOFP4,CBLT,16,0), XLBOCBBB_MASK, POWER4, { CR } },
2787 { "bger", XLOCB(19,BOF,CBLT,16,0), XLBOCBBB_MASK, PWRCOM, { CR } },
2788 { "bgelrl", XLOCB(19,BOF,CBLT,16,1), XLBOCBBB_MASK, PPCCOM, { CR } },
2789 { "bgelrl-", XLOCB(19,BOF,CBLT,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2790 { "bgelrl+", XLOCB(19,BOFP,CBLT,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2791 { "bgelrl-", XLOCB(19,BOFM4,CBLT,16,1), XLBOCBBB_MASK, POWER4, { CR } },
2792 { "bgelrl+", XLOCB(19,BOFP4,CBLT,16,1), XLBOCBBB_MASK, POWER4, { CR } },
2793 { "bgerl", XLOCB(19,BOF,CBLT,16,1), XLBOCBBB_MASK, PWRCOM, { CR } },
2794 { "bnllr", XLOCB(19,BOF,CBLT,16,0), XLBOCBBB_MASK, PPCCOM, { CR } },
2795 { "bnllr-", XLOCB(19,BOF,CBLT,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2796 { "bnllr+", XLOCB(19,BOFP,CBLT,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2797 { "bnllr-", XLOCB(19,BOFM4,CBLT,16,0), XLBOCBBB_MASK, POWER4, { CR } },
2798 { "bnllr+", XLOCB(19,BOFP4,CBLT,16,0), XLBOCBBB_MASK, POWER4, { CR } },
2799 { "bnlr", XLOCB(19,BOF,CBLT,16,0), XLBOCBBB_MASK, PWRCOM, { CR } },
2800 { "bnllrl", XLOCB(19,BOF,CBLT,16,1), XLBOCBBB_MASK, PPCCOM, { CR } },
2801 { "bnllrl-", XLOCB(19,BOF,CBLT,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2802 { "bnllrl+", XLOCB(19,BOFP,CBLT,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2803 { "bnllrl-", XLOCB(19,BOFM4,CBLT,16,1), XLBOCBBB_MASK, POWER4, { CR } },
2804 { "bnllrl+", XLOCB(19,BOFP4,CBLT,16,1), XLBOCBBB_MASK, POWER4, { CR } },
2805 { "bnlrl", XLOCB(19,BOF,CBLT,16,1), XLBOCBBB_MASK, PWRCOM, { CR } },
2806 { "blelr", XLOCB(19,BOF,CBGT,16,0), XLBOCBBB_MASK, PPCCOM, { CR } },
2807 { "blelr-", XLOCB(19,BOF,CBGT,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2808 { "blelr+", XLOCB(19,BOFP,CBGT,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2809 { "blelr-", XLOCB(19,BOFM4,CBGT,16,0), XLBOCBBB_MASK, POWER4, { CR } },
2810 { "blelr+", XLOCB(19,BOFP4,CBGT,16,0), XLBOCBBB_MASK, POWER4, { CR } },
2811 { "bler", XLOCB(19,BOF,CBGT,16,0), XLBOCBBB_MASK, PWRCOM, { CR } },
2812 { "blelrl", XLOCB(19,BOF,CBGT,16,1), XLBOCBBB_MASK, PPCCOM, { CR } },
2813 { "blelrl-", XLOCB(19,BOF,CBGT,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2814 { "blelrl+", XLOCB(19,BOFP,CBGT,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2815 { "blelrl-", XLOCB(19,BOFM4,CBGT,16,1), XLBOCBBB_MASK, POWER4, { CR } },
2816 { "blelrl+", XLOCB(19,BOFP4,CBGT,16,1), XLBOCBBB_MASK, POWER4, { CR } },
2817 { "blerl", XLOCB(19,BOF,CBGT,16,1), XLBOCBBB_MASK, PWRCOM, { CR } },
2818 { "bnglr", XLOCB(19,BOF,CBGT,16,0), XLBOCBBB_MASK, PPCCOM, { CR } },
2819 { "bnglr-", XLOCB(19,BOF,CBGT,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2820 { "bnglr+", XLOCB(19,BOFP,CBGT,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2821 { "bnglr-", XLOCB(19,BOFM4,CBGT,16,0), XLBOCBBB_MASK, POWER4, { CR } },
2822 { "bnglr+", XLOCB(19,BOFP4,CBGT,16,0), XLBOCBBB_MASK, POWER4, { CR } },
2823 { "bngr", XLOCB(19,BOF,CBGT,16,0), XLBOCBBB_MASK, PWRCOM, { CR } },
2824 { "bnglrl", XLOCB(19,BOF,CBGT,16,1), XLBOCBBB_MASK, PPCCOM, { CR } },
2825 { "bnglrl-", XLOCB(19,BOF,CBGT,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2826 { "bnglrl+", XLOCB(19,BOFP,CBGT,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2827 { "bnglrl-", XLOCB(19,BOFM4,CBGT,16,1), XLBOCBBB_MASK, POWER4, { CR } },
2828 { "bnglrl+", XLOCB(19,BOFP4,CBGT,16,1), XLBOCBBB_MASK, POWER4, { CR } },
2829 { "bngrl", XLOCB(19,BOF,CBGT,16,1), XLBOCBBB_MASK, PWRCOM, { CR } },
2830 { "bnelr", XLOCB(19,BOF,CBEQ,16,0), XLBOCBBB_MASK, PPCCOM, { CR } },
2831 { "bnelr-", XLOCB(19,BOF,CBEQ,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2832 { "bnelr+", XLOCB(19,BOFP,CBEQ,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2833 { "bnelr-", XLOCB(19,BOFM4,CBEQ,16,0), XLBOCBBB_MASK, POWER4, { CR } },
2834 { "bnelr+", XLOCB(19,BOFP4,CBEQ,16,0), XLBOCBBB_MASK, POWER4, { CR } },
2835 { "bner", XLOCB(19,BOF,CBEQ,16,0), XLBOCBBB_MASK, PWRCOM, { CR } },
2836 { "bnelrl", XLOCB(19,BOF,CBEQ,16,1), XLBOCBBB_MASK, PPCCOM, { CR } },
2837 { "bnelrl-", XLOCB(19,BOF,CBEQ,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2838 { "bnelrl+", XLOCB(19,BOFP,CBEQ,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2839 { "bnelrl-", XLOCB(19,BOFM4,CBEQ,16,1), XLBOCBBB_MASK, POWER4, { CR } },
2840 { "bnelrl+", XLOCB(19,BOFP4,CBEQ,16,1), XLBOCBBB_MASK, POWER4, { CR } },
2841 { "bnerl", XLOCB(19,BOF,CBEQ,16,1), XLBOCBBB_MASK, PWRCOM, { CR } },
2842 { "bnslr", XLOCB(19,BOF,CBSO,16,0), XLBOCBBB_MASK, PPCCOM, { CR } },
2843 { "bnslr-", XLOCB(19,BOF,CBSO,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2844 { "bnslr+", XLOCB(19,BOFP,CBSO,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2845 { "bnslr-", XLOCB(19,BOFM4,CBSO,16,0), XLBOCBBB_MASK, POWER4, { CR } },
2846 { "bnslr+", XLOCB(19,BOFP4,CBSO,16,0), XLBOCBBB_MASK, POWER4, { CR } },
2847 { "bnsr", XLOCB(19,BOF,CBSO,16,0), XLBOCBBB_MASK, PWRCOM, { CR } },
2848 { "bnslrl", XLOCB(19,BOF,CBSO,16,1), XLBOCBBB_MASK, PPCCOM, { CR } },
2849 { "bnslrl-", XLOCB(19,BOF,CBSO,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2850 { "bnslrl+", XLOCB(19,BOFP,CBSO,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2851 { "bnslrl-", XLOCB(19,BOFM4,CBSO,16,1), XLBOCBBB_MASK, POWER4, { CR } },
2852 { "bnslrl+", XLOCB(19,BOFP4,CBSO,16,1), XLBOCBBB_MASK, POWER4, { CR } },
2853 { "bnsrl", XLOCB(19,BOF,CBSO,16,1), XLBOCBBB_MASK, PWRCOM, { CR } },
2854 { "bnulr", XLOCB(19,BOF,CBSO,16,0), XLBOCBBB_MASK, PPCCOM, { CR } },
2855 { "bnulr-", XLOCB(19,BOF,CBSO,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2856 { "bnulr+", XLOCB(19,BOFP,CBSO,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2857 { "bnulr-", XLOCB(19,BOFM4,CBSO,16,0), XLBOCBBB_MASK, POWER4, { CR } },
2858 { "bnulr+", XLOCB(19,BOFP4,CBSO,16,0), XLBOCBBB_MASK, POWER4, { CR } },
2859 { "bnulrl", XLOCB(19,BOF,CBSO,16,1), XLBOCBBB_MASK, PPCCOM, { CR } },
2860 { "bnulrl-", XLOCB(19,BOF,CBSO,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2861 { "bnulrl+", XLOCB(19,BOFP,CBSO,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2862 { "bnulrl-", XLOCB(19,BOFM4,CBSO,16,1), XLBOCBBB_MASK, POWER4, { CR } },
2863 { "bnulrl+", XLOCB(19,BOFP4,CBSO,16,1), XLBOCBBB_MASK, POWER4, { CR } },
2864 { "btlr", XLO(19,BOT,16,0), XLBOBB_MASK, PPCCOM, { BI } },
2865 { "btlr-", XLO(19,BOT,16,0), XLBOBB_MASK, NOPOWER4, { BI } },
2866 { "btlr+", XLO(19,BOTP,16,0), XLBOBB_MASK, NOPOWER4, { BI } },
2867 { "btlr-", XLO(19,BOTM4,16,0), XLBOBB_MASK, POWER4, { BI } },
2868 { "btlr+", XLO(19,BOTP4,16,0), XLBOBB_MASK, POWER4, { BI } },
2869 { "bbtr", XLO(19,BOT,16,0), XLBOBB_MASK, PWRCOM, { BI } },
2870 { "btlrl", XLO(19,BOT,16,1), XLBOBB_MASK, PPCCOM, { BI } },
2871 { "btlrl-", XLO(19,BOT,16,1), XLBOBB_MASK, NOPOWER4, { BI } },
2872 { "btlrl+", XLO(19,BOTP,16,1), XLBOBB_MASK, NOPOWER4, { BI } },
2873 { "btlrl-", XLO(19,BOTM4,16,1), XLBOBB_MASK, POWER4, { BI } },
2874 { "btlrl+", XLO(19,BOTP4,16,1), XLBOBB_MASK, POWER4, { BI } },
2875 { "bbtrl", XLO(19,BOT,16,1), XLBOBB_MASK, PWRCOM, { BI } },
2876 { "bflr", XLO(19,BOF,16,0), XLBOBB_MASK, PPCCOM, { BI } },
2877 { "bflr-", XLO(19,BOF,16,0), XLBOBB_MASK, NOPOWER4, { BI } },
2878 { "bflr+", XLO(19,BOFP,16,0), XLBOBB_MASK, NOPOWER4, { BI } },
2879 { "bflr-", XLO(19,BOFM4,16,0), XLBOBB_MASK, POWER4, { BI } },
2880 { "bflr+", XLO(19,BOFP4,16,0), XLBOBB_MASK, POWER4, { BI } },
2881 { "bbfr", XLO(19,BOF,16,0), XLBOBB_MASK, PWRCOM, { BI } },
2882 { "bflrl", XLO(19,BOF,16,1), XLBOBB_MASK, PPCCOM, { BI } },
2883 { "bflrl-", XLO(19,BOF,16,1), XLBOBB_MASK, NOPOWER4, { BI } },
2884 { "bflrl+", XLO(19,BOFP,16,1), XLBOBB_MASK, NOPOWER4, { BI } },
2885 { "bflrl-", XLO(19,BOFM4,16,1), XLBOBB_MASK, POWER4, { BI } },
2886 { "bflrl+", XLO(19,BOFP4,16,1), XLBOBB_MASK, POWER4, { BI } },
2887 { "bbfrl", XLO(19,BOF,16,1), XLBOBB_MASK, PWRCOM, { BI } },
2888 { "bdnztlr", XLO(19,BODNZT,16,0), XLBOBB_MASK, PPCCOM, { BI } },
2889 { "bdnztlr-",XLO(19,BODNZT,16,0), XLBOBB_MASK, NOPOWER4, { BI } },
2890 { "bdnztlr+",XLO(19,BODNZTP,16,0), XLBOBB_MASK, NOPOWER4, { BI } },
2891 { "bdnztlrl",XLO(19,BODNZT,16,1), XLBOBB_MASK, PPCCOM, { BI } },
2892 { "bdnztlrl-",XLO(19,BODNZT,16,1), XLBOBB_MASK, NOPOWER4, { BI } },
2893 { "bdnztlrl+",XLO(19,BODNZTP,16,1), XLBOBB_MASK, NOPOWER4, { BI } },
2894 { "bdnzflr", XLO(19,BODNZF,16,0), XLBOBB_MASK, PPCCOM, { BI } },
2895 { "bdnzflr-",XLO(19,BODNZF,16,0), XLBOBB_MASK, NOPOWER4, { BI } },
2896 { "bdnzflr+",XLO(19,BODNZFP,16,0), XLBOBB_MASK, NOPOWER4, { BI } },
2897 { "bdnzflrl",XLO(19,BODNZF,16,1), XLBOBB_MASK, PPCCOM, { BI } },
2898 { "bdnzflrl-",XLO(19,BODNZF,16,1), XLBOBB_MASK, NOPOWER4, { BI } },
2899 { "bdnzflrl+",XLO(19,BODNZFP,16,1), XLBOBB_MASK, NOPOWER4, { BI } },
2900 { "bdztlr", XLO(19,BODZT,16,0), XLBOBB_MASK, PPCCOM, { BI } },
2901 { "bdztlr-", XLO(19,BODZT,16,0), XLBOBB_MASK, NOPOWER4, { BI } },
2902 { "bdztlr+", XLO(19,BODZTP,16,0), XLBOBB_MASK, NOPOWER4, { BI } },
2903 { "bdztlrl", XLO(19,BODZT,16,1), XLBOBB_MASK, PPCCOM, { BI } },
2904 { "bdztlrl-",XLO(19,BODZT,16,1), XLBOBB_MASK, NOPOWER4, { BI } },
2905 { "bdztlrl+",XLO(19,BODZTP,16,1), XLBOBB_MASK, NOPOWER4, { BI } },
2906 { "bdzflr", XLO(19,BODZF,16,0), XLBOBB_MASK, PPCCOM, { BI } },
2907 { "bdzflr-", XLO(19,BODZF,16,0), XLBOBB_MASK, NOPOWER4, { BI } },
2908 { "bdzflr+", XLO(19,BODZFP,16,0), XLBOBB_MASK, NOPOWER4, { BI } },
2909 { "bdzflrl", XLO(19,BODZF,16,1), XLBOBB_MASK, PPCCOM, { BI } },
2910 { "bdzflrl-",XLO(19,BODZF,16,1), XLBOBB_MASK, NOPOWER4, { BI } },
2911 { "bdzflrl+",XLO(19,BODZFP,16,1), XLBOBB_MASK, NOPOWER4, { BI } },
2912 { "bclr", XLLK(19,16,0), XLYBB_MASK, PPCCOM, { BO, BI } },
2913 { "bclrl", XLLK(19,16,1), XLYBB_MASK, PPCCOM, { BO, BI } },
2914 { "bclr+", XLYLK(19,16,1,0), XLYBB_MASK, PPCCOM, { BOE, BI } },
2915 { "bclrl+", XLYLK(19,16,1,1), XLYBB_MASK, PPCCOM, { BOE, BI } },
2916 { "bclr-", XLYLK(19,16,0,0), XLYBB_MASK, PPCCOM, { BOE, BI } },
2917 { "bclrl-", XLYLK(19,16,0,1), XLYBB_MASK, PPCCOM, { BOE, BI } },
2918 { "bcr", XLLK(19,16,0), XLBB_MASK, PWRCOM, { BO, BI } },
2919 { "bcrl", XLLK(19,16,1), XLBB_MASK, PWRCOM, { BO, BI } },
2920 { "bclre", XLLK(19,17,0), XLBB_MASK, BOOKE64, { BO, BI } },
2921 { "bclrel", XLLK(19,17,1), XLBB_MASK, BOOKE64, { BO, BI } },
2923 { "rfid", XL(19,18), 0xffffffff, PPC64, { 0 } },
2925 { "crnot", XL(19,33), XL_MASK, PPCCOM, { BT, BA, BBA } },
2926 { "crnor", XL(19,33), XL_MASK, COM, { BT, BA, BB } },
2927 { "rfmci", X(19,38), 0xffffffff, PPCRFMCI, { 0 } },
2929 { "rfi", XL(19,50), 0xffffffff, COM, { 0 } },
2930 { "rfci", XL(19,51), 0xffffffff, PPC403, { 0 } },
2931 { "rfci", XL(19,51), 0xffffffff, BOOKE, { 0 } },
2933 { "rfsvc", XL(19,82), 0xffffffff, POWER, { 0 } },
2935 { "crandc", XL(19,129), XL_MASK, COM, { BT, BA, BB } },
2937 { "isync", XL(19,150), 0xffffffff, PPCCOM, { 0 } },
2938 { "ics", XL(19,150), 0xffffffff, PWRCOM, { 0 } },
2940 { "crclr", XL(19,193), XL_MASK, PPCCOM, { BT, BAT, BBA } },
2941 { "crxor", XL(19,193), XL_MASK, COM, { BT, BA, BB } },
2943 { "crnand", XL(19,225), XL_MASK, COM, { BT, BA, BB } },
2945 { "crand", XL(19,257), XL_MASK, COM, { BT, BA, BB } },
2947 { "crset", XL(19,289), XL_MASK, PPCCOM, { BT, BAT, BBA } },
2948 { "creqv", XL(19,289), XL_MASK, COM, { BT, BA, BB } },
2950 { "crorc", XL(19,417), XL_MASK, COM, { BT, BA, BB } },
2952 { "crmove", XL(19,449), XL_MASK, PPCCOM, { BT, BA, BBA } },
2953 { "cror", XL(19,449), XL_MASK, COM, { BT, BA, BB } },
2955 { "bctr", XLO(19,BOU,528,0), XLBOBIBB_MASK, COM, { 0 } },
2956 { "bctrl", XLO(19,BOU,528,1), XLBOBIBB_MASK, COM, { 0 } },
2957 { "bltctr", XLOCB(19,BOT,CBLT,528,0), XLBOCBBB_MASK, PPCCOM, { CR } },
2958 { "bltctr-", XLOCB(19,BOT,CBLT,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2959 { "bltctr+", XLOCB(19,BOTP,CBLT,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2960 { "bltctr-", XLOCB(19,BOTM4,CBLT,528,0), XLBOCBBB_MASK, POWER4, { CR } },
2961 { "bltctr+", XLOCB(19,BOTP4,CBLT,528,0), XLBOCBBB_MASK, POWER4, { CR } },
2962 { "bltctrl", XLOCB(19,BOT,CBLT,528,1), XLBOCBBB_MASK, PPCCOM, { CR } },
2963 { "bltctrl-",XLOCB(19,BOT,CBLT,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2964 { "bltctrl+",XLOCB(19,BOTP,CBLT,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2965 { "bltctrl-",XLOCB(19,BOTM4,CBLT,528,1), XLBOCBBB_MASK, POWER4, { CR } },
2966 { "bltctrl+",XLOCB(19,BOTP4,CBLT,528,1), XLBOCBBB_MASK, POWER4, { CR } },
2967 { "bgtctr", XLOCB(19,BOT,CBGT,528,0), XLBOCBBB_MASK, PPCCOM, { CR } },
2968 { "bgtctr-", XLOCB(19,BOT,CBGT,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2969 { "bgtctr+", XLOCB(19,BOTP,CBGT,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2970 { "bgtctr-", XLOCB(19,BOTM4,CBGT,528,0), XLBOCBBB_MASK, POWER4, { CR } },
2971 { "bgtctr+", XLOCB(19,BOTP4,CBGT,528,0), XLBOCBBB_MASK, POWER4, { CR } },
2972 { "bgtctrl", XLOCB(19,BOT,CBGT,528,1), XLBOCBBB_MASK, PPCCOM, { CR } },
2973 { "bgtctrl-",XLOCB(19,BOT,CBGT,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2974 { "bgtctrl+",XLOCB(19,BOTP,CBGT,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2975 { "bgtctrl-",XLOCB(19,BOTM4,CBGT,528,1), XLBOCBBB_MASK, POWER4, { CR } },
2976 { "bgtctrl+",XLOCB(19,BOTP4,CBGT,528,1), XLBOCBBB_MASK, POWER4, { CR } },
2977 { "beqctr", XLOCB(19,BOT,CBEQ,528,0), XLBOCBBB_MASK, PPCCOM, { CR } },
2978 { "beqctr-", XLOCB(19,BOT,CBEQ,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2979 { "beqctr+", XLOCB(19,BOTP,CBEQ,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2980 { "beqctr-", XLOCB(19,BOTM4,CBEQ,528,0), XLBOCBBB_MASK, POWER4, { CR } },
2981 { "beqctr+", XLOCB(19,BOTP4,CBEQ,528,0), XLBOCBBB_MASK, POWER4, { CR } },
2982 { "beqctrl", XLOCB(19,BOT,CBEQ,528,1), XLBOCBBB_MASK, PPCCOM, { CR } },
2983 { "beqctrl-",XLOCB(19,BOT,CBEQ,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2984 { "beqctrl+",XLOCB(19,BOTP,CBEQ,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2985 { "beqctrl-",XLOCB(19,BOTM4,CBEQ,528,1), XLBOCBBB_MASK, POWER4, { CR } },
2986 { "beqctrl+",XLOCB(19,BOTP4,CBEQ,528,1), XLBOCBBB_MASK, POWER4, { CR } },
2987 { "bsoctr", XLOCB(19,BOT,CBSO,528,0), XLBOCBBB_MASK, PPCCOM, { CR } },
2988 { "bsoctr-", XLOCB(19,BOT,CBSO,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2989 { "bsoctr+", XLOCB(19,BOTP,CBSO,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2990 { "bsoctr-", XLOCB(19,BOTM4,CBSO,528,0), XLBOCBBB_MASK, POWER4, { CR } },
2991 { "bsoctr+", XLOCB(19,BOTP4,CBSO,528,0), XLBOCBBB_MASK, POWER4, { CR } },
2992 { "bsoctrl", XLOCB(19,BOT,CBSO,528,1), XLBOCBBB_MASK, PPCCOM, { CR } },
2993 { "bsoctrl-",XLOCB(19,BOT,CBSO,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2994 { "bsoctrl+",XLOCB(19,BOTP,CBSO,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2995 { "bsoctrl-",XLOCB(19,BOTM4,CBSO,528,1), XLBOCBBB_MASK, POWER4, { CR } },
2996 { "bsoctrl+",XLOCB(19,BOTP4,CBSO,528,1), XLBOCBBB_MASK, POWER4, { CR } },
2997 { "bunctr", XLOCB(19,BOT,CBSO,528,0), XLBOCBBB_MASK, PPCCOM, { CR } },
2998 { "bunctr-", XLOCB(19,BOT,CBSO,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2999 { "bunctr+", XLOCB(19,BOTP,CBSO,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
3000 { "bunctr-", XLOCB(19,BOTM4,CBSO,528,0), XLBOCBBB_MASK, POWER4, { CR } },
3001 { "bunctr+", XLOCB(19,BOTP4,CBSO,528,0), XLBOCBBB_MASK, POWER4, { CR } },
3002 { "bunctrl", XLOCB(19,BOT,CBSO,528,1), XLBOCBBB_MASK, PPCCOM, { CR } },
3003 { "bunctrl-",XLOCB(19,BOT,CBSO,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
3004 { "bunctrl+",XLOCB(19,BOTP,CBSO,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
3005 { "bunctrl-",XLOCB(19,BOTM4,CBSO,528,1), XLBOCBBB_MASK, POWER4, { CR } },
3006 { "bunctrl+",XLOCB(19,BOTP4,CBSO,528,1), XLBOCBBB_MASK, POWER4, { CR } },
3007 { "bgectr", XLOCB(19,BOF,CBLT,528,0), XLBOCBBB_MASK, PPCCOM, { CR } },
3008 { "bgectr-", XLOCB(19,BOF,CBLT,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
3009 { "bgectr+", XLOCB(19,BOFP,CBLT,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
3010 { "bgectr-", XLOCB(19,BOFM4,CBLT,528,0), XLBOCBBB_MASK, POWER4, { CR } },
3011 { "bgectr+", XLOCB(19,BOFP4,CBLT,528,0), XLBOCBBB_MASK, POWER4, { CR } },
3012 { "bgectrl", XLOCB(19,BOF,CBLT,528,1), XLBOCBBB_MASK, PPCCOM, { CR } },
3013 { "bgectrl-",XLOCB(19,BOF,CBLT,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
3014 { "bgectrl+",XLOCB(19,BOFP,CBLT,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
3015 { "bgectrl-",XLOCB(19,BOFM4,CBLT,528,1), XLBOCBBB_MASK, POWER4, { CR } },
3016 { "bgectrl+",XLOCB(19,BOFP4,CBLT,528,1), XLBOCBBB_MASK, POWER4, { CR } },
3017 { "bnlctr", XLOCB(19,BOF,CBLT,528,0), XLBOCBBB_MASK, PPCCOM, { CR } },
3018 { "bnlctr-", XLOCB(19,BOF,CBLT,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
3019 { "bnlctr+", XLOCB(19,BOFP,CBLT,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
3020 { "bnlctr-", XLOCB(19,BOFM4,CBLT,528,0), XLBOCBBB_MASK, POWER4, { CR } },
3021 { "bnlctr+", XLOCB(19,BOFP4,CBLT,528,0), XLBOCBBB_MASK, POWER4, { CR } },
3022 { "bnlctrl", XLOCB(19,BOF,CBLT,528,1), XLBOCBBB_MASK, PPCCOM, { CR } },
3023 { "bnlctrl-",XLOCB(19,BOF,CBLT,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
3024 { "bnlctrl+",XLOCB(19,BOFP,CBLT,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
3025 { "bnlctrl-",XLOCB(19,BOFM4,CBLT,528,1), XLBOCBBB_MASK, POWER4, { CR } },
3026 { "bnlctrl+",XLOCB(19,BOFP4,CBLT,528,1), XLBOCBBB_MASK, POWER4, { CR } },
3027 { "blectr", XLOCB(19,BOF,CBGT,528,0), XLBOCBBB_MASK, PPCCOM, { CR } },
3028 { "blectr-", XLOCB(19,BOF,CBGT,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
3029 { "blectr+", XLOCB(19,BOFP,CBGT,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
3030 { "blectr-", XLOCB(19,BOFM4,CBGT,528,0), XLBOCBBB_MASK, POWER4, { CR } },
3031 { "blectr+", XLOCB(19,BOFP4,CBGT,528,0), XLBOCBBB_MASK, POWER4, { CR } },
3032 { "blectrl", XLOCB(19,BOF,CBGT,528,1), XLBOCBBB_MASK, PPCCOM, { CR } },
3033 { "blectrl-",XLOCB(19,BOF,CBGT,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
3034 { "blectrl+",XLOCB(19,BOFP,CBGT,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
3035 { "blectrl-",XLOCB(19,BOFM4,CBGT,528,1), XLBOCBBB_MASK, POWER4, { CR } },
3036 { "blectrl+",XLOCB(19,BOFP4,CBGT,528,1), XLBOCBBB_MASK, POWER4, { CR } },
3037 { "bngctr", XLOCB(19,BOF,CBGT,528,0), XLBOCBBB_MASK, PPCCOM, { CR } },
3038 { "bngctr-", XLOCB(19,BOF,CBGT,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
3039 { "bngctr+", XLOCB(19,BOFP,CBGT,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
3040 { "bngctr-", XLOCB(19,BOFM4,CBGT,528,0), XLBOCBBB_MASK, POWER4, { CR } },
3041 { "bngctr+", XLOCB(19,BOFP4,CBGT,528,0), XLBOCBBB_MASK, POWER4, { CR } },
3042 { "bngctrl", XLOCB(19,BOF,CBGT,528,1), XLBOCBBB_MASK, PPCCOM, { CR } },
3043 { "bngctrl-",XLOCB(19,BOF,CBGT,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
3044 { "bngctrl+",XLOCB(19,BOFP,CBGT,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
3045 { "bngctrl-",XLOCB(19,BOFM4,CBGT,528,1), XLBOCBBB_MASK, POWER4, { CR } },
3046 { "bngctrl+",XLOCB(19,BOFP4,CBGT,528,1), XLBOCBBB_MASK, POWER4, { CR } },
3047 { "bnectr", XLOCB(19,BOF,CBEQ,528,0), XLBOCBBB_MASK, PPCCOM, { CR } },
3048 { "bnectr-", XLOCB(19,BOF,CBEQ,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
3049 { "bnectr+", XLOCB(19,BOFP,CBEQ,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
3050 { "bnectr-", XLOCB(19,BOFM4,CBEQ,528,0), XLBOCBBB_MASK, POWER4, { CR } },
3051 { "bnectr+", XLOCB(19,BOFP4,CBEQ,528,0), XLBOCBBB_MASK, POWER4, { CR } },
3052 { "bnectrl", XLOCB(19,BOF,CBEQ,528,1), XLBOCBBB_MASK, PPCCOM, { CR } },
3053 { "bnectrl-",XLOCB(19,BOF,CBEQ,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
3054 { "bnectrl+",XLOCB(19,BOFP,CBEQ,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
3055 { "bnectrl-",XLOCB(19,BOFM4,CBEQ,528,1), XLBOCBBB_MASK, POWER4, { CR } },
3056 { "bnectrl+",XLOCB(19,BOFP4,CBEQ,528,1), XLBOCBBB_MASK, POWER4, { CR } },
3057 { "bnsctr", XLOCB(19,BOF,CBSO,528,0), XLBOCBBB_MASK, PPCCOM, { CR } },
3058 { "bnsctr-", XLOCB(19,BOF,CBSO,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
3059 { "bnsctr+", XLOCB(19,BOFP,CBSO,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
3060 { "bnsctr-", XLOCB(19,BOFM4,CBSO,528,0), XLBOCBBB_MASK, POWER4, { CR } },
3061 { "bnsctr+", XLOCB(19,BOFP4,CBSO,528,0), XLBOCBBB_MASK, POWER4, { CR } },
3062 { "bnsctrl", XLOCB(19,BOF,CBSO,528,1), XLBOCBBB_MASK, PPCCOM, { CR } },
3063 { "bnsctrl-",XLOCB(19,BOF,CBSO,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
3064 { "bnsctrl+",XLOCB(19,BOFP,CBSO,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
3065 { "bnsctrl-",XLOCB(19,BOFM4,CBSO,528,1), XLBOCBBB_MASK, POWER4, { CR } },
3066 { "bnsctrl+",XLOCB(19,BOFP4,CBSO,528,1), XLBOCBBB_MASK, POWER4, { CR } },
3067 { "bnuctr", XLOCB(19,BOF,CBSO,528,0), XLBOCBBB_MASK, PPCCOM, { CR } },
3068 { "bnuctr-", XLOCB(19,BOF,CBSO,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
3069 { "bnuctr+", XLOCB(19,BOFP,CBSO,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
3070 { "bnuctr-", XLOCB(19,BOFM4,CBSO,528,0), XLBOCBBB_MASK, POWER4, { CR } },
3071 { "bnuctr+", XLOCB(19,BOFP4,CBSO,528,0), XLBOCBBB_MASK, POWER4, { CR } },
3072 { "bnuctrl", XLOCB(19,BOF,CBSO,528,1), XLBOCBBB_MASK, PPCCOM, { CR } },
3073 { "bnuctrl-",XLOCB(19,BOF,CBSO,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
3074 { "bnuctrl+",XLOCB(19,BOFP,CBSO,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
3075 { "bnuctrl-",XLOCB(19,BOFM4,CBSO,528,1), XLBOCBBB_MASK, POWER4, { CR } },
3076 { "bnuctrl+",XLOCB(19,BOFP4,CBSO,528,1), XLBOCBBB_MASK, POWER4, { CR } },
3077 { "btctr", XLO(19,BOT,528,0), XLBOBB_MASK, PPCCOM, { BI } },
3078 { "btctr-", XLO(19,BOT,528,0), XLBOBB_MASK, NOPOWER4, { BI } },
3079 { "btctr+", XLO(19,BOTP,528,0), XLBOBB_MASK, NOPOWER4, { BI } },
3080 { "btctr-", XLO(19,BOTM4,528,0), XLBOBB_MASK, POWER4, { BI } },
3081 { "btctr+", XLO(19,BOTP4,528,0), XLBOBB_MASK, POWER4, { BI } },
3082 { "btctrl", XLO(19,BOT,528,1), XLBOBB_MASK, PPCCOM, { BI } },
3083 { "btctrl-", XLO(19,BOT,528,1), XLBOBB_MASK, NOPOWER4, { BI } },
3084 { "btctrl+", XLO(19,BOTP,528,1), XLBOBB_MASK, NOPOWER4, { BI } },
3085 { "btctrl-", XLO(19,BOTM4,528,1), XLBOBB_MASK, POWER4, { BI } },
3086 { "btctrl+", XLO(19,BOTP4,528,1), XLBOBB_MASK, POWER4, { BI } },
3087 { "bfctr", XLO(19,BOF,528,0), XLBOBB_MASK, PPCCOM, { BI } },
3088 { "bfctr-", XLO(19,BOF,528,0), XLBOBB_MASK, NOPOWER4, { BI } },
3089 { "bfctr+", XLO(19,BOFP,528,0), XLBOBB_MASK, NOPOWER4, { BI } },
3090 { "bfctr-", XLO(19,BOFM4,528,0), XLBOBB_MASK, POWER4, { BI } },
3091 { "bfctr+", XLO(19,BOFP4,528,0), XLBOBB_MASK, POWER4, { BI } },
3092 { "bfctrl", XLO(19,BOF,528,1), XLBOBB_MASK, PPCCOM, { BI } },
3093 { "bfctrl-", XLO(19,BOF,528,1), XLBOBB_MASK, NOPOWER4, { BI } },
3094 { "bfctrl+", XLO(19,BOFP,528,1), XLBOBB_MASK, NOPOWER4, { BI } },
3095 { "bfctrl-", XLO(19,BOFM4,528,1), XLBOBB_MASK, POWER4, { BI } },
3096 { "bfctrl+", XLO(19,BOFP4,528,1), XLBOBB_MASK, POWER4, { BI } },
3097 { "bcctr", XLLK(19,528,0), XLYBB_MASK, PPCCOM, { BO, BI } },
3098 { "bcctr-", XLYLK(19,528,0,0), XLYBB_MASK, PPCCOM, { BOE, BI } },
3099 { "bcctr+", XLYLK(19,528,1,0), XLYBB_MASK, PPCCOM, { BOE, BI } },
3100 { "bcctrl", XLLK(19,528,1), XLYBB_MASK, PPCCOM, { BO, BI } },
3101 { "bcctrl-", XLYLK(19,528,0,1), XLYBB_MASK, PPCCOM, { BOE, BI } },
3102 { "bcctrl+", XLYLK(19,528,1,1), XLYBB_MASK, PPCCOM, { BOE, BI } },
3103 { "bcc", XLLK(19,528,0), XLBB_MASK, PWRCOM, { BO, BI } },
3104 { "bccl", XLLK(19,528,1), XLBB_MASK, PWRCOM, { BO, BI } },
3105 { "bcctre", XLLK(19,529,0), XLYBB_MASK, BOOKE64, { BO, BI } },
3106 { "bcctrel", XLLK(19,529,1), XLYBB_MASK, BOOKE64, { BO, BI } },
3108 { "rlwimi", M(20,0), M_MASK, PPCCOM, { RA,RS,SH,MBE,ME } },
3109 { "rlimi", M(20,0), M_MASK, PWRCOM, { RA,RS,SH,MBE,ME } },
3111 { "rlwimi.", M(20,1), M_MASK, PPCCOM, { RA,RS,SH,MBE,ME } },
3112 { "rlimi.", M(20,1), M_MASK, PWRCOM, { RA,RS,SH,MBE,ME } },
3114 { "rotlwi", MME(21,31,0), MMBME_MASK, PPCCOM, { RA, RS, SH } },
3115 { "clrlwi", MME(21,31,0), MSHME_MASK, PPCCOM, { RA, RS, MB } },
3116 { "rlwinm", M(21,0), M_MASK, PPCCOM, { RA,RS,SH,MBE,ME } },
3117 { "rlinm", M(21,0), M_MASK, PWRCOM, { RA,RS,SH,MBE,ME } },
3118 { "rotlwi.", MME(21,31,1), MMBME_MASK, PPCCOM, { RA,RS,SH } },
3119 { "clrlwi.", MME(21,31,1), MSHME_MASK, PPCCOM, { RA, RS, MB } },
3120 { "rlwinm.", M(21,1), M_MASK, PPCCOM, { RA,RS,SH,MBE,ME } },
3121 { "rlinm.", M(21,1), M_MASK, PWRCOM, { RA,RS,SH,MBE,ME } },
3123 { "rlmi", M(22,0), M_MASK, M601, { RA,RS,RB,MBE,ME } },
3124 { "rlmi.", M(22,1), M_MASK, M601, { RA,RS,RB,MBE,ME } },
3126 { "be", B(22,0,0), B_MASK, BOOKE64, { LI } },
3127 { "bel", B(22,0,1), B_MASK, BOOKE64, { LI } },
3128 { "bea", B(22,1,0), B_MASK, BOOKE64, { LIA } },
3129 { "bela", B(22,1,1), B_MASK, BOOKE64, { LIA } },
3131 { "rotlw", MME(23,31,0), MMBME_MASK, PPCCOM, { RA, RS, RB } },
3132 { "rlwnm", M(23,0), M_MASK, PPCCOM, { RA,RS,RB,MBE,ME } },
3133 { "rlnm", M(23,0), M_MASK, PWRCOM, { RA,RS,RB,MBE,ME } },
3134 { "rotlw.", MME(23,31,1), MMBME_MASK, PPCCOM, { RA, RS, RB } },
3135 { "rlwnm.", M(23,1), M_MASK, PPCCOM, { RA,RS,RB,MBE,ME } },
3136 { "rlnm.", M(23,1), M_MASK, PWRCOM, { RA,RS,RB,MBE,ME } },
3138 { "nop", OP(24), 0xffffffff, PPCCOM, { 0 } },
3139 { "ori", OP(24), OP_MASK, PPCCOM, { RA, RS, UI } },
3140 { "oril", OP(24), OP_MASK, PWRCOM, { RA, RS, UI } },
3142 { "oris", OP(25), OP_MASK, PPCCOM, { RA, RS, UI } },
3143 { "oriu", OP(25), OP_MASK, PWRCOM, { RA, RS, UI } },
3145 { "xori", OP(26), OP_MASK, PPCCOM, { RA, RS, UI } },
3146 { "xoril", OP(26), OP_MASK, PWRCOM, { RA, RS, UI } },
3148 { "xoris", OP(27), OP_MASK, PPCCOM, { RA, RS, UI } },
3149 { "xoriu", OP(27), OP_MASK, PWRCOM, { RA, RS, UI } },
3151 { "andi.", OP(28), OP_MASK, PPCCOM, { RA, RS, UI } },
3152 { "andil.", OP(28), OP_MASK, PWRCOM, { RA, RS, UI } },
3154 { "andis.", OP(29), OP_MASK, PPCCOM, { RA, RS, UI } },
3155 { "andiu.", OP(29), OP_MASK, PWRCOM, { RA, RS, UI } },
3157 { "rotldi", MD(30,0,0), MDMB_MASK, PPC64, { RA, RS, SH6 } },
3158 { "clrldi", MD(30,0,0), MDSH_MASK, PPC64, { RA, RS, MB6 } },
3159 { "rldicl", MD(30,0,0), MD_MASK, PPC64, { RA, RS, SH6, MB6 } },
3160 { "rotldi.", MD(30,0,1), MDMB_MASK, PPC64, { RA, RS, SH6 } },
3161 { "clrldi.", MD(30,0,1), MDSH_MASK, PPC64, { RA, RS, MB6 } },
3162 { "rldicl.", MD(30,0,1), MD_MASK, PPC64, { RA, RS, SH6, MB6 } },
3164 { "rldicr", MD(30,1,0), MD_MASK, PPC64, { RA, RS, SH6, ME6 } },
3165 { "rldicr.", MD(30,1,1), MD_MASK, PPC64, { RA, RS, SH6, ME6 } },
3167 { "rldic", MD(30,2,0), MD_MASK, PPC64, { RA, RS, SH6, MB6 } },
3168 { "rldic.", MD(30,2,1), MD_MASK, PPC64, { RA, RS, SH6, MB6 } },
3170 { "rldimi", MD(30,3,0), MD_MASK, PPC64, { RA, RS, SH6, MB6 } },
3171 { "rldimi.", MD(30,3,1), MD_MASK, PPC64, { RA, RS, SH6, MB6 } },
3173 { "rotld", MDS(30,8,0), MDSMB_MASK, PPC64, { RA, RS, RB } },
3174 { "rldcl", MDS(30,8,0), MDS_MASK, PPC64, { RA, RS, RB, MB6 } },
3175 { "rotld.", MDS(30,8,1), MDSMB_MASK, PPC64, { RA, RS, RB } },
3176 { "rldcl.", MDS(30,8,1), MDS_MASK, PPC64, { RA, RS, RB, MB6 } },
3178 { "rldcr", MDS(30,9,0), MDS_MASK, PPC64, { RA, RS, RB, ME6 } },
3179 { "rldcr.", MDS(30,9,1), MDS_MASK, PPC64, { RA, RS, RB, ME6 } },
3181 { "cmpw", XCMPL(31,0,0), XCMPL_MASK, PPCCOM, { OBF, RA, RB } },
3182 { "cmpd", XCMPL(31,0,1), XCMPL_MASK, PPC64, { OBF, RA, RB } },
3183 { "cmp", X(31,0), XCMP_MASK, PPCONLY, { BF, L, RA, RB } },
3184 { "cmp", X(31,0), XCMPL_MASK, PWRCOM, { BF, RA, RB } },
3186 { "twlgt", XTO(31,4,TOLGT), XTO_MASK, PPCCOM, { RA, RB } },
3187 { "tlgt", XTO(31,4,TOLGT), XTO_MASK, PWRCOM, { RA, RB } },
3188 { "twllt", XTO(31,4,TOLLT), XTO_MASK, PPCCOM, { RA, RB } },
3189 { "tllt", XTO(31,4,TOLLT), XTO_MASK, PWRCOM, { RA, RB } },
3190 { "tweq", XTO(31,4,TOEQ), XTO_MASK, PPCCOM, { RA, RB } },
3191 { "teq", XTO(31,4,TOEQ), XTO_MASK, PWRCOM, { RA, RB } },
3192 { "twlge", XTO(31,4,TOLGE), XTO_MASK, PPCCOM, { RA, RB } },
3193 { "tlge", XTO(31,4,TOLGE), XTO_MASK, PWRCOM, { RA, RB } },
3194 { "twlnl", XTO(31,4,TOLNL), XTO_MASK, PPCCOM, { RA, RB } },
3195 { "tlnl", XTO(31,4,TOLNL), XTO_MASK, PWRCOM, { RA, RB } },
3196 { "twlle", XTO(31,4,TOLLE), XTO_MASK, PPCCOM, { RA, RB } },
3197 { "tlle", XTO(31,4,TOLLE), XTO_MASK, PWRCOM, { RA, RB } },
3198 { "twlng", XTO(31,4,TOLNG), XTO_MASK, PPCCOM, { RA, RB } },
3199 { "tlng", XTO(31,4,TOLNG), XTO_MASK, PWRCOM, { RA, RB } },
3200 { "twgt", XTO(31,4,TOGT), XTO_MASK, PPCCOM, { RA, RB } },
3201 { "tgt", XTO(31,4,TOGT), XTO_MASK, PWRCOM, { RA, RB } },
3202 { "twge", XTO(31,4,TOGE), XTO_MASK, PPCCOM, { RA, RB } },
3203 { "tge", XTO(31,4,TOGE), XTO_MASK, PWRCOM, { RA, RB } },
3204 { "twnl", XTO(31,4,TONL), XTO_MASK, PPCCOM, { RA, RB } },
3205 { "tnl", XTO(31,4,TONL), XTO_MASK, PWRCOM, { RA, RB } },
3206 { "twlt", XTO(31,4,TOLT), XTO_MASK, PPCCOM, { RA, RB } },
3207 { "tlt", XTO(31,4,TOLT), XTO_MASK, PWRCOM, { RA, RB } },
3208 { "twle", XTO(31,4,TOLE), XTO_MASK, PPCCOM, { RA, RB } },
3209 { "tle", XTO(31,4,TOLE), XTO_MASK, PWRCOM, { RA, RB } },
3210 { "twng", XTO(31,4,TONG), XTO_MASK, PPCCOM, { RA, RB } },
3211 { "tng", XTO(31,4,TONG), XTO_MASK, PWRCOM, { RA, RB } },
3212 { "twne", XTO(31,4,TONE), XTO_MASK, PPCCOM, { RA, RB } },
3213 { "tne", XTO(31,4,TONE), XTO_MASK, PWRCOM, { RA, RB } },
3214 { "trap", XTO(31,4,TOU), 0xffffffff, PPCCOM, { 0 } },
3215 { "tw", X(31,4), X_MASK, PPCCOM, { TO, RA, RB } },
3216 { "t", X(31,4), X_MASK, PWRCOM, { TO, RA, RB } },
3218 { "subfc", XO(31,8,0,0), XO_MASK, PPCCOM, { RT, RA, RB } },
3219 { "sf", XO(31,8,0,0), XO_MASK, PWRCOM, { RT, RA, RB } },
3220 { "subc", XO(31,8,0,0), XO_MASK, PPC, { RT, RB, RA } },
3221 { "subfc.", XO(31,8,0,1), XO_MASK, PPCCOM, { RT, RA, RB } },
3222 { "sf.", XO(31,8,0,1), XO_MASK, PWRCOM, { RT, RA, RB } },
3223 { "subc.", XO(31,8,0,1), XO_MASK, PPCCOM, { RT, RB, RA } },
3224 { "subfco", XO(31,8,1,0), XO_MASK, PPCCOM, { RT, RA, RB } },
3225 { "sfo", XO(31,8,1,0), XO_MASK, PWRCOM, { RT, RA, RB } },
3226 { "subco", XO(31,8,1,0), XO_MASK, PPC, { RT, RB, RA } },
3227 { "subfco.", XO(31,8,1,1), XO_MASK, PPCCOM, { RT, RA, RB } },
3228 { "sfo.", XO(31,8,1,1), XO_MASK, PWRCOM, { RT, RA, RB } },
3229 { "subco.", XO(31,8,1,1), XO_MASK, PPC, { RT, RB, RA } },
3231 { "mulhdu", XO(31,9,0,0), XO_MASK, PPC64, { RT, RA, RB } },
3232 { "mulhdu.", XO(31,9,0,1), XO_MASK, PPC64, { RT, RA, RB } },
3234 { "addc", XO(31,10,0,0), XO_MASK, PPCCOM, { RT, RA, RB } },
3235 { "a", XO(31,10,0,0), XO_MASK, PWRCOM, { RT, RA, RB } },
3236 { "addc.", XO(31,10,0,1), XO_MASK, PPCCOM, { RT, RA, RB } },
3237 { "a.", XO(31,10,0,1), XO_MASK, PWRCOM, { RT, RA, RB } },
3238 { "addco", XO(31,10,1,0), XO_MASK, PPCCOM, { RT, RA, RB } },
3239 { "ao", XO(31,10,1,0), XO_MASK, PWRCOM, { RT, RA, RB } },
3240 { "addco.", XO(31,10,1,1), XO_MASK, PPCCOM, { RT, RA, RB } },
3241 { "ao.", XO(31,10,1,1), XO_MASK, PWRCOM, { RT, RA, RB } },
3243 { "mulhwu", XO(31,11,0,0), XO_MASK, PPC, { RT, RA, RB } },
3244 { "mulhwu.", XO(31,11,0,1), XO_MASK, PPC, { RT, RA, RB } },
3246 { "isellt", X(31,15), X_MASK, PPCISEL, { RT, RA, RB } },
3247 { "iselgt", X(31,47), X_MASK, PPCISEL, { RT, RA, RB } },
3248 { "iseleq", X(31,79), X_MASK, PPCISEL, { RT, RA, RB } },
3249 { "isel", XISEL(31,15), XISEL_MASK, PPCISEL, { RT, RA, RB, CRB } },
3251 { "mfcr", X(31,19), XRARB_MASK, NOPOWER4, { RT } },
3252 { "mfcr", X(31,19), XFXFXM_MASK, POWER4, { RT, FXM4 } },
3254 { "lwarx", X(31,20), X_MASK, PPC, { RT, RA, RB } },
3256 { "ldx", X(31,21), X_MASK, PPC64, { RT, RA, RB } },
3258 { "icbt", X(31,22), X_MASK, BOOKE, { CT, RA, RB } },
3260 { "lwzx", X(31,23), X_MASK, PPCCOM, { RT, RA, RB } },
3261 { "lx", X(31,23), X_MASK, PWRCOM, { RT, RA, RB } },
3263 { "slw", XRC(31,24,0), X_MASK, PPCCOM, { RA, RS, RB } },
3264 { "sl", XRC(31,24,0), X_MASK, PWRCOM, { RA, RS, RB } },
3265 { "slw.", XRC(31,24,1), X_MASK, PPCCOM, { RA, RS, RB } },
3266 { "sl.", XRC(31,24,1), X_MASK, PWRCOM, { RA, RS, RB } },
3268 { "cntlzw", XRC(31,26,0), XRB_MASK, PPCCOM, { RA, RS } },
3269 { "cntlz", XRC(31,26,0), XRB_MASK, PWRCOM, { RA, RS } },
3270 { "cntlzw.", XRC(31,26,1), XRB_MASK, PPCCOM, { RA, RS } },
3271 { "cntlz.", XRC(31,26,1), XRB_MASK, PWRCOM, { RA, RS } },
3273 { "sld", XRC(31,27,0), X_MASK, PPC64, { RA, RS, RB } },
3274 { "sld.", XRC(31,27,1), X_MASK, PPC64, { RA, RS, RB } },
3276 { "and", XRC(31,28,0), X_MASK, COM, { RA, RS, RB } },
3277 { "and.", XRC(31,28,1), X_MASK, COM, { RA, RS, RB } },
3279 { "maskg", XRC(31,29,0), X_MASK, M601, { RA, RS, RB } },
3280 { "maskg.", XRC(31,29,1), X_MASK, M601, { RA, RS, RB } },
3282 { "icbte", X(31,30), X_MASK, BOOKE64, { CT, RA, RB } },
3284 { "lwzxe", X(31,31), X_MASK, BOOKE64, { RT, RA, RB } },
3286 { "cmplw", XCMPL(31,32,0), XCMPL_MASK, PPCCOM, { OBF, RA, RB } },
3287 { "cmpld", XCMPL(31,32,1), XCMPL_MASK, PPC64, { OBF, RA, RB } },
3288 { "cmpl", X(31,32), XCMP_MASK, PPCONLY, { BF, L, RA, RB } },
3289 { "cmpl", X(31,32), XCMPL_MASK, PWRCOM, { BF, RA, RB } },
3291 { "subf", XO(31,40,0,0), XO_MASK, PPC, { RT, RA, RB } },
3292 { "sub", XO(31,40,0,0), XO_MASK, PPC, { RT, RB, RA } },
3293 { "subf.", XO(31,40,0,1), XO_MASK, PPC, { RT, RA, RB } },
3294 { "sub.", XO(31,40,0,1), XO_MASK, PPC, { RT, RB, RA } },
3295 { "subfo", XO(31,40,1,0), XO_MASK, PPC, { RT, RA, RB } },
3296 { "subo", XO(31,40,1,0), XO_MASK, PPC, { RT, RB, RA } },
3297 { "subfo.", XO(31,40,1,1), XO_MASK, PPC, { RT, RA, RB } },
3298 { "subo.", XO(31,40,1,1), XO_MASK, PPC, { RT, RB, RA } },
3300 { "ldux", X(31,53), X_MASK, PPC64, { RT, RAL, RB } },
3302 { "dcbst", X(31,54), XRT_MASK, PPC, { RA, RB } },
3304 { "lwzux", X(31,55), X_MASK, PPCCOM, { RT, RAL, RB } },
3305 { "lux", X(31,55), X_MASK, PWRCOM, { RT, RA, RB } },
3307 { "dcbste", X(31,62), XRT_MASK, BOOKE64, { RA, RB } },
3309 { "lwzuxe", X(31,63), X_MASK, BOOKE64, { RT, RAL, RB } },
3311 { "cntlzd", XRC(31,58,0), XRB_MASK, PPC64, { RA, RS } },
3312 { "cntlzd.", XRC(31,58,1), XRB_MASK, PPC64, { RA, RS } },
3314 { "andc", XRC(31,60,0), X_MASK, COM, { RA, RS, RB } },
3315 { "andc.", XRC(31,60,1), X_MASK, COM, { RA, RS, RB } },
3317 { "tdlgt", XTO(31,68,TOLGT), XTO_MASK, PPC64, { RA, RB } },
3318 { "tdllt", XTO(31,68,TOLLT), XTO_MASK, PPC64, { RA, RB } },
3319 { "tdeq", XTO(31,68,TOEQ), XTO_MASK, PPC64, { RA, RB } },
3320 { "tdlge", XTO(31,68,TOLGE), XTO_MASK, PPC64, { RA, RB } },
3321 { "tdlnl", XTO(31,68,TOLNL), XTO_MASK, PPC64, { RA, RB } },
3322 { "tdlle", XTO(31,68,TOLLE), XTO_MASK, PPC64, { RA, RB } },
3323 { "tdlng", XTO(31,68,TOLNG), XTO_MASK, PPC64, { RA, RB } },
3324 { "tdgt", XTO(31,68,TOGT), XTO_MASK, PPC64, { RA, RB } },
3325 { "tdge", XTO(31,68,TOGE), XTO_MASK, PPC64, { RA, RB } },
3326 { "tdnl", XTO(31,68,TONL), XTO_MASK, PPC64, { RA, RB } },
3327 { "tdlt", XTO(31,68,TOLT), XTO_MASK, PPC64, { RA, RB } },
3328 { "tdle", XTO(31,68,TOLE), XTO_MASK, PPC64, { RA, RB } },
3329 { "tdng", XTO(31,68,TONG), XTO_MASK, PPC64, { RA, RB } },
3330 { "tdne", XTO(31,68,TONE), XTO_MASK, PPC64, { RA, RB } },
3331 { "td", X(31,68), X_MASK, PPC64, { TO, RA, RB } },
3333 { "mulhd", XO(31,73,0,0), XO_MASK, PPC64, { RT, RA, RB } },
3334 { "mulhd.", XO(31,73,0,1), XO_MASK, PPC64, { RT, RA, RB } },
3336 { "mulhw", XO(31,75,0,0), XO_MASK, PPC, { RT, RA, RB } },
3337 { "mulhw.", XO(31,75,0,1), XO_MASK, PPC, { RT, RA, RB } },
3339 { "mtsrd", X(31,82), XRB_MASK|(1<<20), PPC64, { SR, RS } },
3341 { "mfmsr", X(31,83), XRARB_MASK, COM, { RT } },
3343 { "ldarx", X(31,84), X_MASK, PPC64, { RT, RA, RB } },
3345 { "dcbf", X(31,86), XRT_MASK, PPC, { RA, RB } },
3347 { "lbzx", X(31,87), X_MASK, COM, { RT, RA, RB } },
3349 { "dcbfe", X(31,94), XRT_MASK, BOOKE64, { RA, RB } },
3351 { "lbzxe", X(31,95), X_MASK, BOOKE64, { RT, RA, RB } },
3353 { "neg", XO(31,104,0,0), XORB_MASK, COM, { RT, RA } },
3354 { "neg.", XO(31,104,0,1), XORB_MASK, COM, { RT, RA } },
3355 { "nego", XO(31,104,1,0), XORB_MASK, COM, { RT, RA } },
3356 { "nego.", XO(31,104,1,1), XORB_MASK, COM, { RT, RA } },
3358 { "mul", XO(31,107,0,0), XO_MASK, M601, { RT, RA, RB } },
3359 { "mul.", XO(31,107,0,1), XO_MASK, M601, { RT, RA, RB } },
3360 { "mulo", XO(31,107,1,0), XO_MASK, M601, { RT, RA, RB } },
3361 { "mulo.", XO(31,107,1,1), XO_MASK, M601, { RT, RA, RB } },
3363 { "mtsrdin", X(31,114), XRA_MASK, PPC64, { RS, RB } },
3365 { "clf", X(31,118), XTO_MASK, POWER, { RA, RB } },
3367 { "lbzux", X(31,119), X_MASK, COM, { RT, RAL, RB } },
3369 { "not", XRC(31,124,0), X_MASK, COM, { RA, RS, RBS } },
3370 { "nor", XRC(31,124,0), X_MASK, COM, { RA, RS, RB } },
3371 { "not.", XRC(31,124,1), X_MASK, COM, { RA, RS, RBS } },
3372 { "nor.", XRC(31,124,1), X_MASK, COM, { RA, RS, RB } },
3374 { "lwarxe", X(31,126), X_MASK, BOOKE64, { RT, RA, RB } },
3376 { "lbzuxe", X(31,127), X_MASK, BOOKE64, { RT, RAL, RB } },
3378 { "wrtee", X(31,131), XRARB_MASK, PPC403, { RS } },
3379 { "wrtee", X(31,131), XRARB_MASK, BOOKE, { RS } },
3381 { "dcbtstls",X(31,134), X_MASK, PPCCHLK, { CT, RA, RB }},
3383 { "subfe", XO(31,136,0,0), XO_MASK, PPCCOM, { RT, RA, RB } },
3384 { "sfe", XO(31,136,0,0), XO_MASK, PWRCOM, { RT, RA, RB } },
3385 { "subfe.", XO(31,136,0,1), XO_MASK, PPCCOM, { RT, RA, RB } },
3386 { "sfe.", XO(31,136,0,1), XO_MASK, PWRCOM, { RT, RA, RB } },
3387 { "subfeo", XO(31,136,1,0), XO_MASK, PPCCOM, { RT, RA, RB } },
3388 { "sfeo", XO(31,136,1,0), XO_MASK, PWRCOM, { RT, RA, RB } },
3389 { "subfeo.", XO(31,136,1,1), XO_MASK, PPCCOM, { RT, RA, RB } },
3390 { "sfeo.", XO(31,136,1,1), XO_MASK, PWRCOM, { RT, RA, RB } },
3392 { "adde", XO(31,138,0,0), XO_MASK, PPCCOM, { RT, RA, RB } },
3393 { "ae", XO(31,138,0,0), XO_MASK, PWRCOM, { RT, RA, RB } },
3394 { "adde.", XO(31,138,0,1), XO_MASK, PPCCOM, { RT, RA, RB } },
3395 { "ae.", XO(31,138,0,1), XO_MASK, PWRCOM, { RT, RA, RB } },
3396 { "addeo", XO(31,138,1,0), XO_MASK, PPCCOM, { RT, RA, RB } },
3397 { "aeo", XO(31,138,1,0), XO_MASK, PWRCOM, { RT, RA, RB } },
3398 { "addeo.", XO(31,138,1,1), XO_MASK, PPCCOM, { RT, RA, RB } },
3399 { "aeo.", XO(31,138,1,1), XO_MASK, PWRCOM, { RT, RA, RB } },
3401 { "dcbtstlse",X(31,142),X_MASK, PPCCHLK64, { CT, RA, RB }},
3403 { "mtcr", XFXM(31,144,0xff), XRARB_MASK, COM, { RS }},
3404 { "mtcrf", X(31,144), XFXFXM_MASK, COM, { FXM, RS } },
3406 { "mtmsr", X(31,146), XRARB_MASK, COM, { RS } },
3408 { "stdx", X(31,149), X_MASK, PPC64, { RS, RA, RB } },
3410 { "stwcx.", XRC(31,150,1), X_MASK, PPC, { RS, RA, RB } },
3412 { "stwx", X(31,151), X_MASK, PPCCOM, { RS, RA, RB } },
3413 { "stx", X(31,151), X_MASK, PWRCOM, { RS, RA, RB } },
3415 { "stwcxe.", XRC(31,158,1), X_MASK, BOOKE64, { RS, RA, RB } },
3417 { "stwxe", X(31,159), X_MASK, BOOKE64, { RS, RA, RB } },
3419 { "slq", XRC(31,152,0), X_MASK, M601, { RA, RS, RB } },
3420 { "slq.", XRC(31,152,1), X_MASK, M601, { RA, RS, RB } },
3422 { "sle", XRC(31,153,0), X_MASK, M601, { RA, RS, RB } },
3423 { "sle.", XRC(31,153,1), X_MASK, M601, { RA, RS, RB } },
3425 { "wrteei", X(31,163), XE_MASK, PPC403, { E } },
3426 { "wrteei", X(31,163), XE_MASK, BOOKE, { E } },
3428 { "dcbtls", X(31,166), X_MASK, PPCCHLK, { CT, RA, RB }},
3429 { "dcbtlse", X(31,174), X_MASK, PPCCHLK64, { CT, RA, RB }},
3431 { "mtmsrd", X(31,178), XRLARB_MASK, PPC64, { RS, MTMSRD_L } },
3433 { "stdux", X(31,181), X_MASK, PPC64, { RS, RAS, RB } },
3435 { "stwux", X(31,183), X_MASK, PPCCOM, { RS, RAS, RB } },
3436 { "stux", X(31,183), X_MASK, PWRCOM, { RS, RA, RB } },
3438 { "sliq", XRC(31,184,0), X_MASK, M601, { RA, RS, SH } },
3439 { "sliq.", XRC(31,184,1), X_MASK, M601, { RA, RS, SH } },
3441 { "stwuxe", X(31,191), X_MASK, BOOKE64, { RS, RAS, RB } },
3443 { "subfze", XO(31,200,0,0), XORB_MASK, PPCCOM, { RT, RA } },
3444 { "sfze", XO(31,200,0,0), XORB_MASK, PWRCOM, { RT, RA } },
3445 { "subfze.", XO(31,200,0,1), XORB_MASK, PPCCOM, { RT, RA } },
3446 { "sfze.", XO(31,200,0,1), XORB_MASK, PWRCOM, { RT, RA } },
3447 { "subfzeo", XO(31,200,1,0), XORB_MASK, PPCCOM, { RT, RA } },
3448 { "sfzeo", XO(31,200,1,0), XORB_MASK, PWRCOM, { RT, RA } },
3449 { "subfzeo.",XO(31,200,1,1), XORB_MASK, PPCCOM, { RT, RA } },
3450 { "sfzeo.", XO(31,200,1,1), XORB_MASK, PWRCOM, { RT, RA } },
3452 { "addze", XO(31,202,0,0), XORB_MASK, PPCCOM, { RT, RA } },
3453 { "aze", XO(31,202,0,0), XORB_MASK, PWRCOM, { RT, RA } },
3454 { "addze.", XO(31,202,0,1), XORB_MASK, PPCCOM, { RT, RA } },
3455 { "aze.", XO(31,202,0,1), XORB_MASK, PWRCOM, { RT, RA } },
3456 { "addzeo", XO(31,202,1,0), XORB_MASK, PPCCOM, { RT, RA } },
3457 { "azeo", XO(31,202,1,0), XORB_MASK, PWRCOM, { RT, RA } },
3458 { "addzeo.", XO(31,202,1,1), XORB_MASK, PPCCOM, { RT, RA } },
3459 { "azeo.", XO(31,202,1,1), XORB_MASK, PWRCOM, { RT, RA } },
3461 { "mtsr", X(31,210), XRB_MASK|(1<<20), COM32, { SR, RS } },
3463 { "stdcx.", XRC(31,214,1), X_MASK, PPC64, { RS, RA, RB } },
3465 { "stbx", X(31,215), X_MASK, COM, { RS, RA, RB } },
3467 { "sllq", XRC(31,216,0), X_MASK, M601, { RA, RS, RB } },
3468 { "sllq.", XRC(31,216,1), X_MASK, M601, { RA, RS, RB } },
3470 { "sleq", XRC(31,217,0), X_MASK, M601, { RA, RS, RB } },
3471 { "sleq.", XRC(31,217,1), X_MASK, M601, { RA, RS, RB } },
3473 { "stbxe", X(31,223), X_MASK, BOOKE64, { RS, RA, RB } },
3475 { "icblc", X(31,230), X_MASK, PPCCHLK, { CT, RA, RB }},
3477 { "subfme", XO(31,232,0,0), XORB_MASK, PPCCOM, { RT, RA } },
3478 { "sfme", XO(31,232,0,0), XORB_MASK, PWRCOM, { RT, RA } },
3479 { "subfme.", XO(31,232,0,1), XORB_MASK, PPCCOM, { RT, RA } },
3480 { "sfme.", XO(31,232,0,1), XORB_MASK, PWRCOM, { RT, RA } },
3481 { "subfmeo", XO(31,232,1,0), XORB_MASK, PPCCOM, { RT, RA } },
3482 { "sfmeo", XO(31,232,1,0), XORB_MASK, PWRCOM, { RT, RA } },
3483 { "subfmeo.",XO(31,232,1,1), XORB_MASK, PPCCOM, { RT, RA } },
3484 { "sfmeo.", XO(31,232,1,1), XORB_MASK, PWRCOM, { RT, RA } },
3486 { "mulld", XO(31,233,0,0), XO_MASK, PPC64, { RT, RA, RB } },
3487 { "mulld.", XO(31,233,0,1), XO_MASK, PPC64, { RT, RA, RB } },
3488 { "mulldo", XO(31,233,1,0), XO_MASK, PPC64, { RT, RA, RB } },
3489 { "mulldo.", XO(31,233,1,1), XO_MASK, PPC64, { RT, RA, RB } },
3491 { "addme", XO(31,234,0,0), XORB_MASK, PPCCOM, { RT, RA } },
3492 { "ame", XO(31,234,0,0), XORB_MASK, PWRCOM, { RT, RA } },
3493 { "addme.", XO(31,234,0,1), XORB_MASK, PPCCOM, { RT, RA } },
3494 { "ame.", XO(31,234,0,1), XORB_MASK, PWRCOM, { RT, RA } },
3495 { "addmeo", XO(31,234,1,0), XORB_MASK, PPCCOM, { RT, RA } },
3496 { "ameo", XO(31,234,1,0), XORB_MASK, PWRCOM, { RT, RA } },
3497 { "addmeo.", XO(31,234,1,1), XORB_MASK, PPCCOM, { RT, RA } },
3498 { "ameo.", XO(31,234,1,1), XORB_MASK, PWRCOM, { RT, RA } },
3500 { "mullw", XO(31,235,0,0), XO_MASK, PPCCOM, { RT, RA, RB } },
3501 { "muls", XO(31,235,0,0), XO_MASK, PWRCOM, { RT, RA, RB } },
3502 { "mullw.", XO(31,235,0,1), XO_MASK, PPCCOM, { RT, RA, RB } },
3503 { "muls.", XO(31,235,0,1), XO_MASK, PWRCOM, { RT, RA, RB } },
3504 { "mullwo", XO(31,235,1,0), XO_MASK, PPCCOM, { RT, RA, RB } },
3505 { "mulso", XO(31,235,1,0), XO_MASK, PWRCOM, { RT, RA, RB } },
3506 { "mullwo.", XO(31,235,1,1), XO_MASK, PPCCOM, { RT, RA, RB } },
3507 { "mulso.", XO(31,235,1,1), XO_MASK, PWRCOM, { RT, RA, RB } },
3509 { "icblce", X(31,238), X_MASK, PPCCHLK64, { CT, RA, RB }},
3510 { "mtsrin", X(31,242), XRA_MASK, PPC32, { RS, RB } },
3511 { "mtsri", X(31,242), XRA_MASK, POWER32, { RS, RB } },
3513 { "dcbtst", X(31,246), XRT_MASK, PPC, { CT, RA, RB } },
3515 { "stbux", X(31,247), X_MASK, COM, { RS, RAS, RB } },
3517 { "slliq", XRC(31,248,0), X_MASK, M601, { RA, RS, SH } },
3518 { "slliq.", XRC(31,248,1), X_MASK, M601, { RA, RS, SH } },
3520 { "dcbtste", X(31,253), X_MASK, BOOKE64, { CT, RA, RB } },
3522 { "stbuxe", X(31,255), X_MASK, BOOKE64, { RS, RAS, RB } },
3524 { "mfdcrx", X(31,259), X_MASK, BOOKE, { RS, RA } },
3526 { "icbt", X(31,262), XRT_MASK, PPC403, { RA, RB } },
3528 { "doz", XO(31,264,0,0), XO_MASK, M601, { RT, RA, RB } },
3529 { "doz.", XO(31,264,0,1), XO_MASK, M601, { RT, RA, RB } },
3530 { "dozo", XO(31,264,1,0), XO_MASK, M601, { RT, RA, RB } },
3531 { "dozo.", XO(31,264,1,1), XO_MASK, M601, { RT, RA, RB } },
3533 { "add", XO(31,266,0,0), XO_MASK, PPCCOM, { RT, RA, RB } },
3534 { "cax", XO(31,266,0,0), XO_MASK, PWRCOM, { RT, RA, RB } },
3535 { "add.", XO(31,266,0,1), XO_MASK, PPCCOM, { RT, RA, RB } },
3536 { "cax.", XO(31,266,0,1), XO_MASK, PWRCOM, { RT, RA, RB } },
3537 { "addo", XO(31,266,1,0), XO_MASK, PPCCOM, { RT, RA, RB } },
3538 { "caxo", XO(31,266,1,0), XO_MASK, PWRCOM, { RT, RA, RB } },
3539 { "addo.", XO(31,266,1,1), XO_MASK, PPCCOM, { RT, RA, RB } },
3540 { "caxo.", XO(31,266,1,1), XO_MASK, PWRCOM, { RT, RA, RB } },
3542 { "tlbiel", X(31,274), XRTRA_MASK, POWER4, { RB } },
3544 { "mfapidi", X(31,275), X_MASK, BOOKE, { RT, RA } },
3546 { "lscbx", XRC(31,277,0), X_MASK, M601, { RT, RA, RB } },
3547 { "lscbx.", XRC(31,277,1), X_MASK, M601, { RT, RA, RB } },
3549 { "dcbt", X(31,278), XRT_MASK, PPC, { CT, RA, RB } },
3551 { "lhzx", X(31,279), X_MASK, COM, { RT, RA, RB } },
3553 { "eqv", XRC(31,284,0), X_MASK, COM, { RA, RS, RB } },
3554 { "eqv.", XRC(31,284,1), X_MASK, COM, { RA, RS, RB } },
3556 { "dcbte", X(31,286), X_MASK, BOOKE64, { CT, RA, RB } },
3558 { "lhzxe", X(31,287), X_MASK, BOOKE64, { RT, RA, RB } },
3560 { "tlbie", X(31,306), XRTLRA_MASK, PPC, { RB, L } },
3561 { "tlbi", X(31,306), XRT_MASK, POWER, { RA, RB } },
3563 { "eciwx", X(31,310), X_MASK, PPC, { RT, RA, RB } },
3565 { "lhzux", X(31,311), X_MASK, COM, { RT, RAL, RB } },
3567 { "xor", XRC(31,316,0), X_MASK, COM, { RA, RS, RB } },
3568 { "xor.", XRC(31,316,1), X_MASK, COM, { RA, RS, RB } },
3570 { "lhzuxe", X(31,319), X_MASK, BOOKE64, { RT, RAL, RB } },
3572 { "mfexisr", XSPR(31,323,64), XSPR_MASK, PPC403, { RT } },
3573 { "mfexier", XSPR(31,323,66), XSPR_MASK, PPC403, { RT } },
3574 { "mfbr0", XSPR(31,323,128), XSPR_MASK, PPC403, { RT } },
3575 { "mfbr1", XSPR(31,323,129), XSPR_MASK, PPC403, { RT } },
3576 { "mfbr2", XSPR(31,323,130), XSPR_MASK, PPC403, { RT } },
3577 { "mfbr3", XSPR(31,323,131), XSPR_MASK, PPC403, { RT } },
3578 { "mfbr4", XSPR(31,323,132), XSPR_MASK, PPC403, { RT } },
3579 { "mfbr5", XSPR(31,323,133), XSPR_MASK, PPC403, { RT } },
3580 { "mfbr6", XSPR(31,323,134), XSPR_MASK, PPC403, { RT } },
3581 { "mfbr7", XSPR(31,323,135), XSPR_MASK, PPC403, { RT } },
3582 { "mfbear", XSPR(31,323,144), XSPR_MASK, PPC403, { RT } },
3583 { "mfbesr", XSPR(31,323,145), XSPR_MASK, PPC403, { RT } },
3584 { "mfiocr", XSPR(31,323,160), XSPR_MASK, PPC403, { RT } },
3585 { "mfdmacr0", XSPR(31,323,192), XSPR_MASK, PPC403, { RT } },
3586 { "mfdmact0", XSPR(31,323,193), XSPR_MASK, PPC403, { RT } },
3587 { "mfdmada0", XSPR(31,323,194), XSPR_MASK, PPC403, { RT } },
3588 { "mfdmasa0", XSPR(31,323,195), XSPR_MASK, PPC403, { RT } },
3589 { "mfdmacc0", XSPR(31,323,196), XSPR_MASK, PPC403, { RT } },
3590 { "mfdmacr1", XSPR(31,323,200), XSPR_MASK, PPC403, { RT } },
3591 { "mfdmact1", XSPR(31,323,201), XSPR_MASK, PPC403, { RT } },
3592 { "mfdmada1", XSPR(31,323,202), XSPR_MASK, PPC403, { RT } },
3593 { "mfdmasa1", XSPR(31,323,203), XSPR_MASK, PPC403, { RT } },
3594 { "mfdmacc1", XSPR(31,323,204), XSPR_MASK, PPC403, { RT } },
3595 { "mfdmacr2", XSPR(31,323,208), XSPR_MASK, PPC403, { RT } },
3596 { "mfdmact2", XSPR(31,323,209), XSPR_MASK, PPC403, { RT } },
3597 { "mfdmada2", XSPR(31,323,210), XSPR_MASK, PPC403, { RT } },
3598 { "mfdmasa2", XSPR(31,323,211), XSPR_MASK, PPC403, { RT } },
3599 { "mfdmacc2", XSPR(31,323,212), XSPR_MASK, PPC403, { RT } },
3600 { "mfdmacr3", XSPR(31,323,216), XSPR_MASK, PPC403, { RT } },
3601 { "mfdmact3", XSPR(31,323,217), XSPR_MASK, PPC403, { RT } },
3602 { "mfdmada3", XSPR(31,323,218), XSPR_MASK, PPC403, { RT } },
3603 { "mfdmasa3", XSPR(31,323,219), XSPR_MASK, PPC403, { RT } },
3604 { "mfdmacc3", XSPR(31,323,220), XSPR_MASK, PPC403, { RT } },
3605 { "mfdmasr", XSPR(31,323,224), XSPR_MASK, PPC403, { RT } },
3606 { "mfdcr", X(31,323), X_MASK, PPC403, { RT, SPR } },
3607 { "mfdcr", X(31,323), X_MASK, BOOKE, { RT, SPR } },
3609 { "div", XO(31,331,0,0), XO_MASK, M601, { RT, RA, RB } },
3610 { "div.", XO(31,331,0,1), XO_MASK, M601, { RT, RA, RB } },
3611 { "divo", XO(31,331,1,0), XO_MASK, M601, { RT, RA, RB } },
3612 { "divo.", XO(31,331,1,1), XO_MASK, M601, { RT, RA, RB } },
3614 { "mfpmr", X(31,334), X_MASK, PPCPMR, { RT, PMR }},
3616 { "mfmq", XSPR(31,339,0), XSPR_MASK, M601, { RT } },
3617 { "mfxer", XSPR(31,339,1), XSPR_MASK, COM, { RT } },
3618 { "mfrtcu", XSPR(31,339,4), XSPR_MASK, COM, { RT } },
3619 { "mfrtcl", XSPR(31,339,5), XSPR_MASK, COM, { RT } },
3620 { "mfdec", XSPR(31,339,6), XSPR_MASK, MFDEC1, { RT } },
3621 { "mflr", XSPR(31,339,8), XSPR_MASK, COM, { RT } },
3622 { "mfctr", XSPR(31,339,9), XSPR_MASK, COM, { RT } },
3623 { "mftid", XSPR(31,339,17), XSPR_MASK, POWER, { RT } },
3624 { "mfdsisr", XSPR(31,339,18), XSPR_MASK, COM, { RT } },
3625 { "mfdar", XSPR(31,339,19), XSPR_MASK, COM, { RT } },
3626 { "mfdec", XSPR(31,339,22), XSPR_MASK, MFDEC2, { RT } },
3627 { "mfsdr0", XSPR(31,339,24), XSPR_MASK, POWER, { RT } },
3628 { "mfsdr1", XSPR(31,339,25), XSPR_MASK, COM, { RT } },
3629 { "mfsrr0", XSPR(31,339,26), XSPR_MASK, COM, { RT } },
3630 { "mfsrr1", XSPR(31,339,27), XSPR_MASK, COM, { RT } },
3631 { "mfpid", XSPR(31,339,48), XSPR_MASK, BOOKE, { RT } },
3632 { "mfcsrr0", XSPR(31,339,58), XSPR_MASK, BOOKE, { RT } },
3633 { "mfcsrr1", XSPR(31,339,59), XSPR_MASK, BOOKE, { RT } },
3634 { "mfdear", XSPR(31,339,61), XSPR_MASK, BOOKE, { RT } },
3635 { "mfesr", XSPR(31,339,62), XSPR_MASK, BOOKE, { RT } },
3636 { "mfivpr", XSPR(31,339,63), XSPR_MASK, BOOKE, { RT } },
3637 { "mfcmpa", XSPR(31,339,144), XSPR_MASK, PPC860, { RT } },
3638 { "mfcmpb", XSPR(31,339,145), XSPR_MASK, PPC860, { RT } },
3639 { "mfcmpc", XSPR(31,339,146), XSPR_MASK, PPC860, { RT } },
3640 { "mfcmpd", XSPR(31,339,147), XSPR_MASK, PPC860, { RT } },
3641 { "mficr", XSPR(31,339,148), XSPR_MASK, PPC860, { RT } },
3642 { "mfder", XSPR(31,339,149), XSPR_MASK, PPC860, { RT } },
3643 { "mfcounta", XSPR(31,339,150), XSPR_MASK, PPC860, { RT } },
3644 { "mfcountb", XSPR(31,339,151), XSPR_MASK, PPC860, { RT } },
3645 { "mfcmpe", XSPR(31,339,152), XSPR_MASK, PPC860, { RT } },
3646 { "mfcmpf", XSPR(31,339,153), XSPR_MASK, PPC860, { RT } },
3647 { "mfcmpg", XSPR(31,339,154), XSPR_MASK, PPC860, { RT } },
3648 { "mfcmph", XSPR(31,339,155), XSPR_MASK, PPC860, { RT } },
3649 { "mflctrl1", XSPR(31,339,156), XSPR_MASK, PPC860, { RT } },
3650 { "mflctrl2", XSPR(31,339,157), XSPR_MASK, PPC860, { RT } },
3651 { "mfictrl", XSPR(31,339,158), XSPR_MASK, PPC860, { RT } },
3652 { "mfbar", XSPR(31,339,159), XSPR_MASK, PPC860, { RT } },
3653 { "mfvrsave", XSPR(31,339,256), XSPR_MASK, PPCVEC, { RT } },
3654 { "mfusprg0", XSPR(31,339,256), XSPR_MASK, BOOKE, { RT } },
3655 { "mfsprg4", XSPR(31,339,260), XSPR_MASK, PPC405, { RT } },
3656 { "mfsprg5", XSPR(31,339,261), XSPR_MASK, PPC405, { RT } },
3657 { "mfsprg6", XSPR(31,339,262), XSPR_MASK, PPC405, { RT } },
3658 { "mfsprg7", XSPR(31,339,263), XSPR_MASK, PPC405, { RT } },
3659 { "mftb", XSPR(31,339,268), XSPR_MASK, BOOKE, { RT } },
3660 { "mftbl", XSPR(31,339,268), XSPR_MASK, BOOKE, { RT } },
3661 { "mftbu", XSPR(31,339,269), XSPR_MASK, BOOKE, { RT } },
3662 { "mfsprg", XSPR(31,339,272), XSPRG_MASK, PPC, { RT, SPRG } },
3663 { "mfsprg0", XSPR(31,339,272), XSPR_MASK, PPC, { RT } },
3664 { "mfsprg1", XSPR(31,339,273), XSPR_MASK, PPC, { RT } },
3665 { "mfsprg2", XSPR(31,339,274), XSPR_MASK, PPC, { RT } },
3666 { "mfsprg3", XSPR(31,339,275), XSPR_MASK, PPC, { RT } },
3667 { "mfasr", XSPR(31,339,280), XSPR_MASK, PPC64, { RT } },
3668 { "mfear", XSPR(31,339,282), XSPR_MASK, PPC, { RT } },
3669 { "mfpir", XSPR(31,339,286), XSPR_MASK, BOOKE, { RT } },
3670 { "mfpvr", XSPR(31,339,287), XSPR_MASK, PPC, { RT } },
3671 { "mfdbsr", XSPR(31,339,304), XSPR_MASK, BOOKE, { RT } },
3672 { "mfdbcr0", XSPR(31,339,308), XSPR_MASK, BOOKE, { RT } },
3673 { "mfdbcr1", XSPR(31,339,309), XSPR_MASK, BOOKE, { RT } },
3674 { "mfdbcr2", XSPR(31,339,310), XSPR_MASK, BOOKE, { RT } },
3675 { "mfiac1", XSPR(31,339,312), XSPR_MASK, BOOKE, { RT } },
3676 { "mfiac2", XSPR(31,339,313), XSPR_MASK, BOOKE, { RT } },
3677 { "mfiac3", XSPR(31,339,314), XSPR_MASK, BOOKE, { RT } },
3678 { "mfiac4", XSPR(31,339,315), XSPR_MASK, BOOKE, { RT } },
3679 { "mfdac1", XSPR(31,339,316), XSPR_MASK, BOOKE, { RT } },
3680 { "mfdac2", XSPR(31,339,317), XSPR_MASK, BOOKE, { RT } },
3681 { "mfdvc1", XSPR(31,339,318), XSPR_MASK, BOOKE, { RT } },
3682 { "mfdvc2", XSPR(31,339,319), XSPR_MASK, BOOKE, { RT } },
3683 { "mftsr", XSPR(31,339,336), XSPR_MASK, BOOKE, { RT } },
3684 { "mftcr", XSPR(31,339,340), XSPR_MASK, BOOKE, { RT } },
3685 { "mfivor0", XSPR(31,339,400), XSPR_MASK, BOOKE, { RT } },
3686 { "mfivor1", XSPR(31,339,401), XSPR_MASK, BOOKE, { RT } },
3687 { "mfivor2", XSPR(31,339,402), XSPR_MASK, BOOKE, { RT } },
3688 { "mfivor3", XSPR(31,339,403), XSPR_MASK, BOOKE, { RT } },
3689 { "mfivor4", XSPR(31,339,404), XSPR_MASK, BOOKE, { RT } },
3690 { "mfivor5", XSPR(31,339,405), XSPR_MASK, BOOKE, { RT } },
3691 { "mfivor6", XSPR(31,339,406), XSPR_MASK, BOOKE, { RT } },
3692 { "mfivor7", XSPR(31,339,407), XSPR_MASK, BOOKE, { RT } },
3693 { "mfivor8", XSPR(31,339,408), XSPR_MASK, BOOKE, { RT } },
3694 { "mfivor9", XSPR(31,339,409), XSPR_MASK, BOOKE, { RT } },
3695 { "mfivor10", XSPR(31,339,410), XSPR_MASK, BOOKE, { RT } },
3696 { "mfivor11", XSPR(31,339,411), XSPR_MASK, BOOKE, { RT } },
3697 { "mfivor12", XSPR(31,339,412), XSPR_MASK, BOOKE, { RT } },
3698 { "mfivor13", XSPR(31,339,413), XSPR_MASK, BOOKE, { RT } },
3699 { "mfivor14", XSPR(31,339,414), XSPR_MASK, BOOKE, { RT } },
3700 { "mfivor15", XSPR(31,339,415), XSPR_MASK, BOOKE, { RT } },
3701 { "mfspefscr", XSPR(31,339,512), XSPR_MASK, PPCSPE, { RT } },
3702 { "mfbbear", XSPR(31,339,513), XSPR_MASK, PPCBRLK, { RT } },
3703 { "mfbbtar", XSPR(31,339,514), XSPR_MASK, PPCBRLK, { RT } },
3704 { "mfibatu", XSPR(31,339,528), XSPRBAT_MASK, PPC, { RT, SPRBAT } },
3705 { "mfibatl", XSPR(31,339,529), XSPRBAT_MASK, PPC, { RT, SPRBAT } },
3706 { "mfdbatu", XSPR(31,339,536), XSPRBAT_MASK, PPC, { RT, SPRBAT } },
3707 { "mfdbatl", XSPR(31,339,537), XSPRBAT_MASK, PPC, { RT, SPRBAT } },
3708 { "mfic_cst", XSPR(31,339,560), XSPR_MASK, PPC860, { RT } },
3709 { "mfic_adr", XSPR(31,339,561), XSPR_MASK, PPC860, { RT } },
3710 { "mfic_dat", XSPR(31,339,562), XSPR_MASK, PPC860, { RT } },
3711 { "mfdc_cst", XSPR(31,339,568), XSPR_MASK, PPC860, { RT } },
3712 { "mfdc_adr", XSPR(31,339,569), XSPR_MASK, PPC860, { RT } },
3713 { "mfdc_dat", XSPR(31,339,570), XSPR_MASK, PPC860, { RT } },
3714 { "mfmcsrr0", XSPR(31,339,570), XSPR_MASK, PPCRFMCI, { RT } },
3715 { "mfmcsrr1", XSPR(31,339,571), XSPR_MASK, PPCRFMCI, { RT } },
3716 { "mfmcsr", XSPR(31,339,572), XSPR_MASK, PPCRFMCI, { RT } },
3717 { "mfdpdr", XSPR(31,339,630), XSPR_MASK, PPC860, { RT } },
3718 { "mfdpir", XSPR(31,339,631), XSPR_MASK, PPC860, { RT } },
3719 { "mfimmr", XSPR(31,339,638), XSPR_MASK, PPC860, { RT } },
3720 { "mfmi_ctr", XSPR(31,339,784), XSPR_MASK, PPC860, { RT } },
3721 { "mfmi_ap", XSPR(31,339,786), XSPR_MASK, PPC860, { RT } },
3722 { "mfmi_epn", XSPR(31,339,787), XSPR_MASK, PPC860, { RT } },
3723 { "mfmi_twc", XSPR(31,339,789), XSPR_MASK, PPC860, { RT } },
3724 { "mfmi_rpn", XSPR(31,339,790), XSPR_MASK, PPC860, { RT } },
3725 { "mfmd_ctr", XSPR(31,339,792), XSPR_MASK, PPC860, { RT } },
3726 { "mfm_casid", XSPR(31,339,793), XSPR_MASK, PPC860, { RT } },
3727 { "mfmd_ap", XSPR(31,339,794), XSPR_MASK, PPC860, { RT } },
3728 { "mfmd_epn", XSPR(31,339,795), XSPR_MASK, PPC860, { RT } },
3729 { "mfmd_twb", XSPR(31,339,796), XSPR_MASK, PPC860, { RT } },
3730 { "mfmd_twc", XSPR(31,339,797), XSPR_MASK, PPC860, { RT } },
3731 { "mfmd_rpn", XSPR(31,339,798), XSPR_MASK, PPC860, { RT } },
3732 { "mfm_tw", XSPR(31,339,799), XSPR_MASK, PPC860, { RT } },
3733 { "mfmi_dbcam", XSPR(31,339,816), XSPR_MASK, PPC860, { RT } },
3734 { "mfmi_dbram0",XSPR(31,339,817), XSPR_MASK, PPC860, { RT } },
3735 { "mfmi_dbram1",XSPR(31,339,818), XSPR_MASK, PPC860, { RT } },
3736 { "mfmd_dbcam", XSPR(31,339,824), XSPR_MASK, PPC860, { RT } },
3737 { "mfmd_dbram0",XSPR(31,339,825), XSPR_MASK, PPC860, { RT } },
3738 { "mfmd_dbram1",XSPR(31,339,826), XSPR_MASK, PPC860, { RT } },
3739 { "mfummcr0", XSPR(31,339,936), XSPR_MASK, PPC750, { RT } },
3740 { "mfupmc1", XSPR(31,339,937), XSPR_MASK, PPC750, { RT } },
3741 { "mfupmc2", XSPR(31,339,938), XSPR_MASK, PPC750, { RT } },
3742 { "mfusia", XSPR(31,339,939), XSPR_MASK, PPC750, { RT } },
3743 { "mfummcr1", XSPR(31,339,940), XSPR_MASK, PPC750, { RT } },
3744 { "mfupmc3", XSPR(31,339,941), XSPR_MASK, PPC750, { RT } },
3745 { "mfupmc4", XSPR(31,339,942), XSPR_MASK, PPC750, { RT } },
3746 { "mfzpr", XSPR(31,339,944), XSPR_MASK, PPC403, { RT } },
3747 { "mfpid", XSPR(31,339,945), XSPR_MASK, PPC403, { RT } },
3748 { "mfccr0", XSPR(31,339,947), XSPR_MASK, PPC405, { RT } },
3749 { "mfiac3", XSPR(31,339,948), XSPR_MASK, PPC405, { RT } },
3750 { "mfiac4", XSPR(31,339,949), XSPR_MASK, PPC405, { RT } },
3751 { "mfdvc1", XSPR(31,339,950), XSPR_MASK, PPC405, { RT } },
3752 { "mfdvc2", XSPR(31,339,951), XSPR_MASK, PPC405, { RT } },
3753 { "mfmmcr0", XSPR(31,339,952), XSPR_MASK, PPC750, { RT } },
3754 { "mfpmc1", XSPR(31,339,953), XSPR_MASK, PPC750, { RT } },
3755 { "mfsgr", XSPR(31,339,953), XSPR_MASK, PPC403, { RT } },
3756 { "mfpmc2", XSPR(31,339,954), XSPR_MASK, PPC750, { RT } },
3757 { "mfdcwr", XSPR(31,339,954), XSPR_MASK, PPC403, { RT } },
3758 { "mfsia", XSPR(31,339,955), XSPR_MASK, PPC750, { RT } },
3759 { "mfsler", XSPR(31,339,955), XSPR_MASK, PPC405, { RT } },
3760 { "mfmmcr1", XSPR(31,339,956), XSPR_MASK, PPC750, { RT } },
3761 { "mfsu0r", XSPR(31,339,956), XSPR_MASK, PPC405, { RT } },
3762 { "mfpmc3", XSPR(31,339,957), XSPR_MASK, PPC750, { RT } },
3763 { "mfdbcr1", XSPR(31,339,957), XSPR_MASK, PPC405, { RT } },
3764 { "mfpmc4", XSPR(31,339,958), XSPR_MASK, PPC750, { RT } },
3765 { "mficdbdr", XSPR(31,339,979), XSPR_MASK, PPC403, { RT } },
3766 { "mfesr", XSPR(31,339,980), XSPR_MASK, PPC403, { RT } },
3767 { "mfdear", XSPR(31,339,981), XSPR_MASK, PPC403, { RT } },
3768 { "mfevpr", XSPR(31,339,982), XSPR_MASK, PPC403, { RT } },
3769 { "mfcdbcr", XSPR(31,339,983), XSPR_MASK, PPC403, { RT } },
3770 { "mftsr", XSPR(31,339,984), XSPR_MASK, PPC403, { RT } },
3771 { "mftcr", XSPR(31,339,986), XSPR_MASK, PPC403, { RT } },
3772 { "mfpit", XSPR(31,339,987), XSPR_MASK, PPC403, { RT } },
3773 { "mftbhi", XSPR(31,339,988), XSPR_MASK, PPC403, { RT } },
3774 { "mftblo", XSPR(31,339,989), XSPR_MASK, PPC403, { RT } },
3775 { "mfsrr2", XSPR(31,339,990), XSPR_MASK, PPC403, { RT } },
3776 { "mfsrr3", XSPR(31,339,991), XSPR_MASK, PPC403, { RT } },
3777 { "mfdbsr", XSPR(31,339,1008), XSPR_MASK, PPC403, { RT } },
3778 { "mfdbcr0", XSPR(31,339,1010), XSPR_MASK, PPC405, { RT } },
3779 { "mfiac1", XSPR(31,339,1012), XSPR_MASK, PPC403, { RT } },
3780 { "mfiac2", XSPR(31,339,1013), XSPR_MASK, PPC403, { RT } },
3781 { "mfdac1", XSPR(31,339,1014), XSPR_MASK, PPC403, { RT } },
3782 { "mfdac2", XSPR(31,339,1015), XSPR_MASK, PPC403, { RT } },
3783 { "mfl2cr", XSPR(31,339,1017), XSPR_MASK, PPC750, { RT } },
3784 { "mfdccr", XSPR(31,339,1018), XSPR_MASK, PPC403, { RT } },
3785 { "mficcr", XSPR(31,339,1019), XSPR_MASK, PPC403, { RT } },
3786 { "mfictc", XSPR(31,339,1019), XSPR_MASK, PPC750, { RT } },
3787 { "mfpbl1", XSPR(31,339,1020), XSPR_MASK, PPC403, { RT } },
3788 { "mfthrm1", XSPR(31,339,1020), XSPR_MASK, PPC750, { RT } },
3789 { "mfpbu1", XSPR(31,339,1021), XSPR_MASK, PPC403, { RT } },
3790 { "mfthrm2", XSPR(31,339,1021), XSPR_MASK, PPC750, { RT } },
3791 { "mfpbl2", XSPR(31,339,1022), XSPR_MASK, PPC403, { RT } },
3792 { "mfthrm3", XSPR(31,339,1022), XSPR_MASK, PPC750, { RT } },
3793 { "mfpbu2", XSPR(31,339,1023), XSPR_MASK, PPC403, { RT } },
3794 { "mfspr", X(31,339), X_MASK, COM, { RT, SPR } },
3796 { "lwax", X(31,341), X_MASK, PPC64, { RT, RA, RB } },
3798 { "dst", XDSS(31,342,0), XDSS_MASK, PPCVEC, { RA, RB, STRM } },
3799 { "dstt", XDSS(31,342,1), XDSS_MASK, PPCVEC, { RA, RB, STRM } },
3801 { "lhax", X(31,343), X_MASK, COM, { RT, RA, RB } },
3803 { "lhaxe", X(31,351), X_MASK, BOOKE64, { RT, RA, RB } },
3805 { "dstst", XDSS(31,374,0), XDSS_MASK, PPCVEC, { RA, RB, STRM } },
3806 { "dststt", XDSS(31,374,1), XDSS_MASK, PPCVEC, { RA, RB, STRM } },
3808 { "dccci", X(31,454), XRT_MASK, PPC403, { RA, RB } },
3810 { "abs", XO(31,360,0,0), XORB_MASK, M601, { RT, RA } },
3811 { "abs.", XO(31,360,0,1), XORB_MASK, M601, { RT, RA } },
3812 { "abso", XO(31,360,1,0), XORB_MASK, M601, { RT, RA } },
3813 { "abso.", XO(31,360,1,1), XORB_MASK, M601, { RT, RA } },
3815 { "divs", XO(31,363,0,0), XO_MASK, M601, { RT, RA, RB } },
3816 { "divs.", XO(31,363,0,1), XO_MASK, M601, { RT, RA, RB } },
3817 { "divso", XO(31,363,1,0), XO_MASK, M601, { RT, RA, RB } },
3818 { "divso.", XO(31,363,1,1), XO_MASK, M601, { RT, RA, RB } },
3820 { "tlbia", X(31,370), 0xffffffff, PPC, { 0 } },
3822 { "mftbl", XSPR(31,371,268), XSPR_MASK, CLASSIC, { RT } },
3823 { "mftbu", XSPR(31,371,269), XSPR_MASK, CLASSIC, { RT } },
3824 { "mftb", X(31,371), X_MASK, CLASSIC, { RT, TBR } },
3826 { "lwaux", X(31,373), X_MASK, PPC64, { RT, RAL, RB } },
3828 { "lhaux", X(31,375), X_MASK, COM, { RT, RAL, RB } },
3830 { "lhauxe", X(31,383), X_MASK, BOOKE64, { RT, RAL, RB } },
3832 { "mtdcrx", X(31,387), X_MASK, BOOKE, { RA, RS } },
3834 { "dcblc", X(31,390), X_MASK, PPCCHLK, { CT, RA, RB }},
3836 { "subfe64", XO(31,392,0,0), XO_MASK, BOOKE64, { RT, RA, RB } },
3837 { "subfe64o",XO(31,392,1,0), XO_MASK, BOOKE64, { RT, RA, RB } },
3839 { "adde64", XO(31,394,0,0), XO_MASK, BOOKE64, { RT, RA, RB } },
3840 { "adde64o", XO(31,394,1,0), XO_MASK, BOOKE64, { RT, RA, RB } },
3842 { "dcblce", X(31,398), X_MASK, PPCCHLK64, { CT, RA, RB }},
3844 { "slbmte", X(31,402), XRA_MASK, PPC64, { RS, RB } },
3846 { "sthx", X(31,407), X_MASK, COM, { RS, RA, RB } },
3848 { "lfqx", X(31,791), X_MASK, POWER2, { FRT, RA, RB } },
3850 { "lfqux", X(31,823), X_MASK, POWER2, { FRT, RA, RB } },
3852 { "stfqx", X(31,919), X_MASK, POWER2, { FRS, RA, RB } },
3854 { "stfqux", X(31,951), X_MASK, POWER2, { FRS, RA, RB } },
3856 { "orc", XRC(31,412,0), X_MASK, COM, { RA, RS, RB } },
3857 { "orc.", XRC(31,412,1), X_MASK, COM, { RA, RS, RB } },
3859 { "sradi", XS(31,413,0), XS_MASK, PPC64, { RA, RS, SH6 } },
3860 { "sradi.", XS(31,413,1), XS_MASK, PPC64, { RA, RS, SH6 } },
3862 { "sthxe", X(31,415), X_MASK, BOOKE64, { RS, RA, RB } },
3864 { "slbie", X(31,434), XRTRA_MASK, PPC64, { RB } },
3866 { "ecowx", X(31,438), X_MASK, PPC, { RT, RA, RB } },
3868 { "sthux", X(31,439), X_MASK, COM, { RS, RAS, RB } },
3870 { "sthuxe", X(31,447), X_MASK, BOOKE64, { RS, RAS, RB } },
3872 { "mr", XRC(31,444,0), X_MASK, COM, { RA, RS, RBS } },
3873 { "or", XRC(31,444,0), X_MASK, COM, { RA, RS, RB } },
3874 { "mr.", XRC(31,444,1), X_MASK, COM, { RA, RS, RBS } },
3875 { "or.", XRC(31,444,1), X_MASK, COM, { RA, RS, RB } },
3877 { "mtexisr", XSPR(31,451,64), XSPR_MASK, PPC403, { RT } },
3878 { "mtexier", XSPR(31,451,66), XSPR_MASK, PPC403, { RT } },
3879 { "mtbr0", XSPR(31,451,128), XSPR_MASK, PPC403, { RT } },
3880 { "mtbr1", XSPR(31,451,129), XSPR_MASK, PPC403, { RT } },
3881 { "mtbr2", XSPR(31,451,130), XSPR_MASK, PPC403, { RT } },
3882 { "mtbr3", XSPR(31,451,131), XSPR_MASK, PPC403, { RT } },
3883 { "mtbr4", XSPR(31,451,132), XSPR_MASK, PPC403, { RT } },
3884 { "mtbr5", XSPR(31,451,133), XSPR_MASK, PPC403, { RT } },
3885 { "mtbr6", XSPR(31,451,134), XSPR_MASK, PPC403, { RT } },
3886 { "mtbr7", XSPR(31,451,135), XSPR_MASK, PPC403, { RT } },
3887 { "mtbear", XSPR(31,451,144), XSPR_MASK, PPC403, { RT } },
3888 { "mtbesr", XSPR(31,451,145), XSPR_MASK, PPC403, { RT } },
3889 { "mtiocr", XSPR(31,451,160), XSPR_MASK, PPC403, { RT } },
3890 { "mtdmacr0", XSPR(31,451,192), XSPR_MASK, PPC403, { RT } },
3891 { "mtdmact0", XSPR(31,451,193), XSPR_MASK, PPC403, { RT } },
3892 { "mtdmada0", XSPR(31,451,194), XSPR_MASK, PPC403, { RT } },
3893 { "mtdmasa0", XSPR(31,451,195), XSPR_MASK, PPC403, { RT } },
3894 { "mtdmacc0", XSPR(31,451,196), XSPR_MASK, PPC403, { RT } },
3895 { "mtdmacr1", XSPR(31,451,200), XSPR_MASK, PPC403, { RT } },
3896 { "mtdmact1", XSPR(31,451,201), XSPR_MASK, PPC403, { RT } },
3897 { "mtdmada1", XSPR(31,451,202), XSPR_MASK, PPC403, { RT } },
3898 { "mtdmasa1", XSPR(31,451,203), XSPR_MASK, PPC403, { RT } },
3899 { "mtdmacc1", XSPR(31,451,204), XSPR_MASK, PPC403, { RT } },
3900 { "mtdmacr2", XSPR(31,451,208), XSPR_MASK, PPC403, { RT } },
3901 { "mtdmact2", XSPR(31,451,209), XSPR_MASK, PPC403, { RT } },
3902 { "mtdmada2", XSPR(31,451,210), XSPR_MASK, PPC403, { RT } },
3903 { "mtdmasa2", XSPR(31,451,211), XSPR_MASK, PPC403, { RT } },
3904 { "mtdmacc2", XSPR(31,451,212), XSPR_MASK, PPC403, { RT } },
3905 { "mtdmacr3", XSPR(31,451,216), XSPR_MASK, PPC403, { RT } },
3906 { "mtdmact3", XSPR(31,451,217), XSPR_MASK, PPC403, { RT } },
3907 { "mtdmada3", XSPR(31,451,218), XSPR_MASK, PPC403, { RT } },
3908 { "mtdmasa3", XSPR(31,451,219), XSPR_MASK, PPC403, { RT } },
3909 { "mtdmacc3", XSPR(31,451,220), XSPR_MASK, PPC403, { RT } },
3910 { "mtdmasr", XSPR(31,451,224), XSPR_MASK, PPC403, { RT } },
3911 { "mtdcr", X(31,451), X_MASK, PPC403, { SPR, RS } },
3912 { "mtdcr", X(31,451), X_MASK, BOOKE, { SPR, RS } },
3914 { "subfze64",XO(31,456,0,0), XORB_MASK, BOOKE64, { RT, RA } },
3915 { "subfze64o",XO(31,456,1,0), XORB_MASK, BOOKE64, { RT, RA } },
3917 { "divdu", XO(31,457,0,0), XO_MASK, PPC64, { RT, RA, RB } },
3918 { "divdu.", XO(31,457,0,1), XO_MASK, PPC64, { RT, RA, RB } },
3919 { "divduo", XO(31,457,1,0), XO_MASK, PPC64, { RT, RA, RB } },
3920 { "divduo.", XO(31,457,1,1), XO_MASK, PPC64, { RT, RA, RB } },
3922 { "addze64", XO(31,458,0,0), XORB_MASK, BOOKE64, { RT, RA } },
3923 { "addze64o",XO(31,458,1,0), XORB_MASK, BOOKE64, { RT, RA } },
3925 { "divwu", XO(31,459,0,0), XO_MASK, PPC, { RT, RA, RB } },
3926 { "divwu.", XO(31,459,0,1), XO_MASK, PPC, { RT, RA, RB } },
3927 { "divwuo", XO(31,459,1,0), XO_MASK, PPC, { RT, RA, RB } },
3928 { "divwuo.", XO(31,459,1,1), XO_MASK, PPC, { RT, RA, RB } },
3930 { "mtmq", XSPR(31,467,0), XSPR_MASK, M601, { RS } },
3931 { "mtxer", XSPR(31,467,1), XSPR_MASK, COM, { RS } },
3932 { "mtlr", XSPR(31,467,8), XSPR_MASK, COM, { RS } },
3933 { "mtctr", XSPR(31,467,9), XSPR_MASK, COM, { RS } },
3934 { "mttid", XSPR(31,467,17), XSPR_MASK, POWER, { RS } },
3935 { "mtdsisr", XSPR(31,467,18), XSPR_MASK, COM, { RS } },
3936 { "mtdar", XSPR(31,467,19), XSPR_MASK, COM, { RS } },
3937 { "mtrtcu", XSPR(31,467,20), XSPR_MASK, COM, { RS } },
3938 { "mtrtcl", XSPR(31,467,21), XSPR_MASK, COM, { RS } },
3939 { "mtdec", XSPR(31,467,22), XSPR_MASK, COM, { RS } },
3940 { "mtsdr0", XSPR(31,467,24), XSPR_MASK, POWER, { RS } },
3941 { "mtsdr1", XSPR(31,467,25), XSPR_MASK, COM, { RS } },
3942 { "mtsrr0", XSPR(31,467,26), XSPR_MASK, COM, { RS } },
3943 { "mtsrr1", XSPR(31,467,27), XSPR_MASK, COM, { RS } },
3944 { "mtpid", XSPR(31,467,48), XSPR_MASK, BOOKE, { RS } },
3945 { "mtdecar", XSPR(31,467,54), XSPR_MASK, BOOKE, { RS } },
3946 { "mtcsrr0", XSPR(31,467,58), XSPR_MASK, BOOKE, { RS } },
3947 { "mtcsrr1", XSPR(31,467,59), XSPR_MASK, BOOKE, { RS } },
3948 { "mtdear", XSPR(31,467,61), XSPR_MASK, BOOKE, { RS } },
3949 { "mtesr", XSPR(31,467,62), XSPR_MASK, BOOKE, { RS } },
3950 { "mtivpr", XSPR(31,467,63), XSPR_MASK, BOOKE, { RS } },
3951 { "mtcmpa", XSPR(31,467,144), XSPR_MASK, PPC860, { RT } },
3952 { "mtcmpb", XSPR(31,467,145), XSPR_MASK, PPC860, { RT } },
3953 { "mtcmpc", XSPR(31,467,146), XSPR_MASK, PPC860, { RT } },
3954 { "mtcmpd", XSPR(31,467,147), XSPR_MASK, PPC860, { RT } },
3955 { "mticr", XSPR(31,467,148), XSPR_MASK, PPC860, { RT } },
3956 { "mtder", XSPR(31,467,149), XSPR_MASK, PPC860, { RT } },
3957 { "mtcounta", XSPR(31,467,150), XSPR_MASK, PPC860, { RT } },
3958 { "mtcountb", XSPR(31,467,151), XSPR_MASK, PPC860, { RT } },
3959 { "mtcmpe", XSPR(31,467,152), XSPR_MASK, PPC860, { RT } },
3960 { "mtcmpf", XSPR(31,467,153), XSPR_MASK, PPC860, { RT } },
3961 { "mtcmpg", XSPR(31,467,154), XSPR_MASK, PPC860, { RT } },
3962 { "mtcmph", XSPR(31,467,155), XSPR_MASK, PPC860, { RT } },
3963 { "mtlctrl1", XSPR(31,467,156), XSPR_MASK, PPC860, { RT } },
3964 { "mtlctrl2", XSPR(31,467,157), XSPR_MASK, PPC860, { RT } },
3965 { "mtictrl", XSPR(31,467,158), XSPR_MASK, PPC860, { RT } },
3966 { "mtbar", XSPR(31,467,159), XSPR_MASK, PPC860, { RT } },
3967 { "mtvrsave", XSPR(31,467,256), XSPR_MASK, PPCVEC, { RT } },
3968 { "mtusprg0", XSPR(31,467,256), XSPR_MASK, BOOKE, { RS } },
3969 { "mtsprg", XSPR(31,467,272), XSPRG_MASK,PPC, { SPRG, RS } },
3970 { "mtsprg0", XSPR(31,467,272), XSPR_MASK, PPC, { RT } },
3971 { "mtsprg1", XSPR(31,467,273), XSPR_MASK, PPC, { RT } },
3972 { "mtsprg2", XSPR(31,467,274), XSPR_MASK, PPC, { RT } },
3973 { "mtsprg3", XSPR(31,467,275), XSPR_MASK, PPC, { RT } },
3974 { "mtsprg4", XSPR(31,467,276), XSPR_MASK, PPC405, { RT } },
3975 { "mtsprg4", XSPR(31,467,276), XSPR_MASK, BOOKE, { RS } },
3976 { "mtsprg5", XSPR(31,467,277), XSPR_MASK, PPC405, { RT } },
3977 { "mtsprg5", XSPR(31,467,277), XSPR_MASK, BOOKE, { RS } },
3978 { "mtsprg6", XSPR(31,467,278), XSPR_MASK, PPC405, { RT } },
3979 { "mtsprg6", XSPR(31,467,278), XSPR_MASK, BOOKE, { RS } },
3980 { "mtsprg7", XSPR(31,467,279), XSPR_MASK, PPC405, { RT } },
3981 { "mtsprg7", XSPR(31,467,279), XSPR_MASK, BOOKE, { RS } },
3982 { "mtasr", XSPR(31,467,280), XSPR_MASK, PPC64, { RS } },
3983 { "mtear", XSPR(31,467,282), XSPR_MASK, PPC, { RS } },
3984 { "mttbl", XSPR(31,467,284), XSPR_MASK, PPC, { RS } },
3985 { "mttbu", XSPR(31,467,285), XSPR_MASK, PPC, { RS } },
3986 { "mtdbsr", XSPR(31,467,304), XSPR_MASK, BOOKE, { RS } },
3987 { "mtdbcr0", XSPR(31,467,308), XSPR_MASK, BOOKE, { RS } },
3988 { "mtdbcr1", XSPR(31,467,309), XSPR_MASK, BOOKE, { RS } },
3989 { "mtdbcr2", XSPR(31,467,310), XSPR_MASK, BOOKE, { RS } },
3990 { "mtiac1", XSPR(31,467,312), XSPR_MASK, BOOKE, { RS } },
3991 { "mtiac2", XSPR(31,467,313), XSPR_MASK, BOOKE, { RS } },
3992 { "mtiac3", XSPR(31,467,314), XSPR_MASK, BOOKE, { RS } },
3993 { "mtiac4", XSPR(31,467,315), XSPR_MASK, BOOKE, { RS } },
3994 { "mtdac1", XSPR(31,467,316), XSPR_MASK, BOOKE, { RS } },
3995 { "mtdac2", XSPR(31,467,317), XSPR_MASK, BOOKE, { RS } },
3996 { "mtdvc1", XSPR(31,467,318), XSPR_MASK, BOOKE, { RS } },
3997 { "mtdvc2", XSPR(31,467,319), XSPR_MASK, BOOKE, { RS } },
3998 { "mttsr", XSPR(31,467,336), XSPR_MASK, BOOKE, { RS } },
3999 { "mttcr", XSPR(31,467,340), XSPR_MASK, BOOKE, { RS } },
4000 { "mtivor0", XSPR(31,467,400), XSPR_MASK, BOOKE, { RS } },
4001 { "mtivor1", XSPR(31,467,401), XSPR_MASK, BOOKE, { RS } },
4002 { "mtivor2", XSPR(31,467,402), XSPR_MASK, BOOKE, { RS } },
4003 { "mtivor3", XSPR(31,467,403), XSPR_MASK, BOOKE, { RS } },
4004 { "mtivor4", XSPR(31,467,404), XSPR_MASK, BOOKE, { RS } },
4005 { "mtivor5", XSPR(31,467,405), XSPR_MASK, BOOKE, { RS } },
4006 { "mtivor6", XSPR(31,467,406), XSPR_MASK, BOOKE, { RS } },
4007 { "mtivor7", XSPR(31,467,407), XSPR_MASK, BOOKE, { RS } },
4008 { "mtivor8", XSPR(31,467,408), XSPR_MASK, BOOKE, { RS } },
4009 { "mtivor9", XSPR(31,467,409), XSPR_MASK, BOOKE, { RS } },
4010 { "mtivor10", XSPR(31,467,410), XSPR_MASK, BOOKE, { RS } },
4011 { "mtivor11", XSPR(31,467,411), XSPR_MASK, BOOKE, { RS } },
4012 { "mtivor12", XSPR(31,467,412), XSPR_MASK, BOOKE, { RS } },
4013 { "mtivor13", XSPR(31,467,413), XSPR_MASK, BOOKE, { RS } },
4014 { "mtivor14", XSPR(31,467,414), XSPR_MASK, BOOKE, { RS } },
4015 { "mtivor15", XSPR(31,467,415), XSPR_MASK, BOOKE, { RS } },
4016 { "mtspefscr", XSPR(31,467,512), XSPR_MASK, PPCSPE, { RS } },
4017 { "mtbbear", XSPR(31,467,513), XSPR_MASK, PPCBRLK, { RS } },
4018 { "mtbbtar", XSPR(31,467,514), XSPR_MASK, PPCBRLK, { RS } },
4019 { "mtibatu", XSPR(31,467,528), XSPRBAT_MASK, PPC, { SPRBAT, RS } },
4020 { "mtibatl", XSPR(31,467,529), XSPRBAT_MASK, PPC, { SPRBAT, RS } },
4021 { "mtdbatu", XSPR(31,467,536), XSPRBAT_MASK, PPC, { SPRBAT, RS } },
4022 { "mtdbatl", XSPR(31,467,537), XSPRBAT_MASK, PPC, { SPRBAT, RS } },
4023 { "mtmcsrr0", XSPR(31,467,570), XSPR_MASK, PPCRFMCI, { RS } },
4024 { "mtmcsrr1", XSPR(31,467,571), XSPR_MASK, PPCRFMCI, { RS } },
4025 { "mtmcsr", XSPR(31,467,572), XSPR_MASK, PPCRFMCI, { RS } },
4026 { "mtummcr0", XSPR(31,467,936), XSPR_MASK, PPC750, { RT } },
4027 { "mtupmc1", XSPR(31,467,937), XSPR_MASK, PPC750, { RT } },
4028 { "mtupmc2", XSPR(31,467,938), XSPR_MASK, PPC750, { RT } },
4029 { "mtusia", XSPR(31,467,939), XSPR_MASK, PPC750, { RT } },
4030 { "mtummcr1", XSPR(31,467,940), XSPR_MASK, PPC750, { RT } },
4031 { "mtupmc3", XSPR(31,467,941), XSPR_MASK, PPC750, { RT } },
4032 { "mtupmc4", XSPR(31,467,942), XSPR_MASK, PPC750, { RT } },
4033 { "mtzpr", XSPR(31,467,944), XSPR_MASK, PPC403, { RT } },
4034 { "mtpid", XSPR(31,467,945), XSPR_MASK, PPC403, { RT } },
4035 { "mtccr0", XSPR(31,467,947), XSPR_MASK, PPC405, { RT } },
4036 { "mtiac3", XSPR(31,467,948), XSPR_MASK, PPC405, { RT } },
4037 { "mtiac4", XSPR(31,467,949), XSPR_MASK, PPC405, { RT } },
4038 { "mtdvc1", XSPR(31,467,950), XSPR_MASK, PPC405, { RT } },
4039 { "mtdvc2", XSPR(31,467,951), XSPR_MASK, PPC405, { RT } },
4040 { "mtmmcr0", XSPR(31,467,952), XSPR_MASK, PPC750, { RT } },
4041 { "mtsgr", XSPR(31,467,953), XSPR_MASK, PPC403, { RT } },
4042 { "mtpmc1", XSPR(31,467,953), XSPR_MASK, PPC750, { RT } },
4043 { "mtdcwr", XSPR(31,467,954), XSPR_MASK, PPC403, { RT } },
4044 { "mtpmc2", XSPR(31,467,954), XSPR_MASK, PPC750, { RT } },
4045 { "mtsler", XSPR(31,467,955), XSPR_MASK, PPC405, { RT } },
4046 { "mtsia", XSPR(31,467,955), XSPR_MASK, PPC750, { RT } },
4047 { "mtsu0r", XSPR(31,467,956), XSPR_MASK, PPC405, { RT } },
4048 { "mtmmcr1", XSPR(31,467,956), XSPR_MASK, PPC750, { RT } },
4049 { "mtdbcr1", XSPR(31,467,957), XSPR_MASK, PPC405, { RT } },
4050 { "mtpmc3", XSPR(31,467,957), XSPR_MASK, PPC750, { RT } },
4051 { "mtpmc4", XSPR(31,467,958), XSPR_MASK, PPC750, { RT } },
4052 { "mticdbdr", XSPR(31,467,979), XSPR_MASK, PPC403, { RT } },
4053 { "mtesr", XSPR(31,467,980), XSPR_MASK, PPC403, { RT } },
4054 { "mtdear", XSPR(31,467,981), XSPR_MASK, PPC403, { RT } },
4055 { "mtevpr", XSPR(31,467,982), XSPR_MASK, PPC403, { RT } },
4056 { "mtcdbcr", XSPR(31,467,983), XSPR_MASK, PPC403, { RT } },
4057 { "mttsr", XSPR(31,467,984), XSPR_MASK, PPC403, { RT } },
4058 { "mttcr", XSPR(31,467,986), XSPR_MASK, PPC403, { RT } },
4059 { "mtpit", XSPR(31,467,987), XSPR_MASK, PPC403, { RT } },
4060 { "mttbhi", XSPR(31,467,988), XSPR_MASK, PPC403, { RT } },
4061 { "mttblo", XSPR(31,467,989), XSPR_MASK, PPC403, { RT } },
4062 { "mtsrr2", XSPR(31,467,990), XSPR_MASK, PPC403, { RT } },
4063 { "mtsrr3", XSPR(31,467,991), XSPR_MASK, PPC403, { RT } },
4064 { "mtdbsr", XSPR(31,467,1008), XSPR_MASK, PPC403, { RT } },
4065 { "mtdbcr0", XSPR(31,467,1010), XSPR_MASK, PPC405, { RT } },
4066 { "mtiac1", XSPR(31,467,1012), XSPR_MASK, PPC403, { RT } },
4067 { "mtiac2", XSPR(31,467,1013), XSPR_MASK, PPC403, { RT } },
4068 { "mtdac1", XSPR(31,467,1014), XSPR_MASK, PPC403, { RT } },
4069 { "mtdac2", XSPR(31,467,1015), XSPR_MASK, PPC403, { RT } },
4070 { "mtl2cr", XSPR(31,467,1017), XSPR_MASK, PPC750, { RT } },
4071 { "mtdccr", XSPR(31,467,1018), XSPR_MASK, PPC403, { RT } },
4072 { "mticcr", XSPR(31,467,1019), XSPR_MASK, PPC403, { RT } },
4073 { "mtictc", XSPR(31,467,1019), XSPR_MASK, PPC750, { RT } },
4074 { "mtpbl1", XSPR(31,467,1020), XSPR_MASK, PPC403, { RT } },
4075 { "mtthrm1", XSPR(31,467,1020), XSPR_MASK, PPC750, { RT } },
4076 { "mtpbu1", XSPR(31,467,1021), XSPR_MASK, PPC403, { RT } },
4077 { "mtthrm2", XSPR(31,467,1021), XSPR_MASK, PPC750, { RT } },
4078 { "mtpbl2", XSPR(31,467,1022), XSPR_MASK, PPC403, { RT } },
4079 { "mtthrm3", XSPR(31,467,1022), XSPR_MASK, PPC750, { RT } },
4080 { "mtpbu2", XSPR(31,467,1023), XSPR_MASK, PPC403, { RT } },
4081 { "mtspr", X(31,467), X_MASK, COM, { SPR, RS } },
4083 { "dcbi", X(31,470), XRT_MASK, PPC, { RA, RB } },
4085 { "nand", XRC(31,476,0), X_MASK, COM, { RA, RS, RB } },
4086 { "nand.", XRC(31,476,1), X_MASK, COM, { RA, RS, RB } },
4088 { "dcbie", X(31,478), XRT_MASK, BOOKE64, { RA, RB } },
4090 { "dcread", X(31,486), X_MASK, PPC403, { RT, RA, RB }},
4092 { "mtpmr", X(31,462), X_MASK, PPCPMR, { PMR, RS }},
4094 { "icbtls", X(31,486), X_MASK, PPCCHLK, { CT, RA, RB }},
4096 { "nabs", XO(31,488,0,0), XORB_MASK, M601, { RT, RA } },
4097 { "subfme64",XO(31,488,0,0), XORB_MASK, BOOKE64, { RT, RA } },
4098 { "nabs.", XO(31,488,0,1), XORB_MASK, M601, { RT, RA } },
4099 { "nabso", XO(31,488,1,0), XORB_MASK, M601, { RT, RA } },
4100 { "subfme64o",XO(31,488,1,0), XORB_MASK, BOOKE64, { RT, RA } },
4101 { "nabso.", XO(31,488,1,1), XORB_MASK, M601, { RT, RA } },
4103 { "divd", XO(31,489,0,0), XO_MASK, PPC64, { RT, RA, RB } },
4104 { "divd.", XO(31,489,0,1), XO_MASK, PPC64, { RT, RA, RB } },
4105 { "divdo", XO(31,489,1,0), XO_MASK, PPC64, { RT, RA, RB } },
4106 { "divdo.", XO(31,489,1,1), XO_MASK, PPC64, { RT, RA, RB } },
4108 { "addme64", XO(31,490,0,0), XORB_MASK, BOOKE64, { RT, RA } },
4109 { "addme64o",XO(31,490,1,0), XORB_MASK, BOOKE64, { RT, RA } },
4111 { "divw", XO(31,491,0,0), XO_MASK, PPC, { RT, RA, RB } },
4112 { "divw.", XO(31,491,0,1), XO_MASK, PPC, { RT, RA, RB } },
4113 { "divwo", XO(31,491,1,0), XO_MASK, PPC, { RT, RA, RB } },
4114 { "divwo.", XO(31,491,1,1), XO_MASK, PPC, { RT, RA, RB } },
4116 { "icbtlse", X(31,494), X_MASK, PPCCHLK64, { CT, RA, RB }},
4118 { "slbia", X(31,498), 0xffffffff, PPC64, { 0 } },
4120 { "cli", X(31,502), XRB_MASK, POWER, { RT, RA } },
4122 { "stdcxe.", XRC(31,511,1), X_MASK, BOOKE64, { RS, RA, RB } },
4124 { "mcrxr", X(31,512), XRARB_MASK|(3<<21), COM, { BF } },
4126 { "bblels", X(31,518), X_MASK, PPCBRLK, { 0 }},
4127 { "mcrxr64", X(31,544), XRARB_MASK|(3<<21), BOOKE64, { BF } },
4129 { "clcs", X(31,531), XRB_MASK, M601, { RT, RA } },
4131 { "lswx", X(31,533), X_MASK, PPCCOM, { RT, RA, RB } },
4132 { "lsx", X(31,533), X_MASK, PWRCOM, { RT, RA, RB } },
4134 { "lwbrx", X(31,534), X_MASK, PPCCOM, { RT, RA, RB } },
4135 { "lbrx", X(31,534), X_MASK, PWRCOM, { RT, RA, RB } },
4137 { "lfsx", X(31,535), X_MASK, COM, { FRT, RA, RB } },
4139 { "srw", XRC(31,536,0), X_MASK, PPCCOM, { RA, RS, RB } },
4140 { "sr", XRC(31,536,0), X_MASK, PWRCOM, { RA, RS, RB } },
4141 { "srw.", XRC(31,536,1), X_MASK, PPCCOM, { RA, RS, RB } },
4142 { "sr.", XRC(31,536,1), X_MASK, PWRCOM, { RA, RS, RB } },
4144 { "rrib", XRC(31,537,0), X_MASK, M601, { RA, RS, RB } },
4145 { "rrib.", XRC(31,537,1), X_MASK, M601, { RA, RS, RB } },
4147 { "srd", XRC(31,539,0), X_MASK, PPC64, { RA, RS, RB } },
4148 { "srd.", XRC(31,539,1), X_MASK, PPC64, { RA, RS, RB } },
4150 { "maskir", XRC(31,541,0), X_MASK, M601, { RA, RS, RB } },
4151 { "maskir.", XRC(31,541,1), X_MASK, M601, { RA, RS, RB } },
4153 { "lwbrxe", X(31,542), X_MASK, BOOKE64, { RT, RA, RB } },
4155 { "lfsxe", X(31,543), X_MASK, BOOKE64, { FRT, RA, RB } },
4157 { "bbelr", X(31,550), X_MASK, PPCBRLK, { 0 }},
4158 { "tlbsync", X(31,566), 0xffffffff, PPC, { 0 } },
4160 { "lfsux", X(31,567), X_MASK, COM, { FRT, RAS, RB } },
4162 { "lfsuxe", X(31,575), X_MASK, BOOKE64, { FRT, RAS, RB } },
4164 { "mfsr", X(31,595), XRB_MASK|(1<<20), COM32, { RT, SR } },
4166 { "lswi", X(31,597), X_MASK, PPCCOM, { RT, RA, NB } },
4167 { "lsi", X(31,597), X_MASK, PWRCOM, { RT, RA, NB } },
4169 { "lwsync", XSYNC(31,598,1), 0xffffffff, PPCONLY, { 0 } },
4170 { "ptesync", XSYNC(31,598,2), 0xffffffff, PPC64, { 0 } },
4171 { "msync", X(31,598), 0xffffffff, BOOKE, { 0 } },
4172 { "sync", X(31,598), XSYNC_MASK, PPCCOM, { LS } },
4173 { "dcs", X(31,598), 0xffffffff, PWRCOM, { 0 } },
4175 { "lfdx", X(31,599), X_MASK, COM, { FRT, RA, RB } },
4177 { "lfdxe", X(31,607), X_MASK, BOOKE64, { FRT, RA, RB } },
4179 { "mfsri", X(31,627), X_MASK, PWRCOM, { RT, RA, RB } },
4181 { "dclst", X(31,630), XRB_MASK, PWRCOM, { RS, RA } },
4183 { "lfdux", X(31,631), X_MASK, COM, { FRT, RAS, RB } },
4185 { "lfduxe", X(31,639), X_MASK, BOOKE64, { FRT, RAS, RB } },
4187 { "mfsrin", X(31,659), XRA_MASK, PPC32, { RT, RB } },
4189 { "stswx", X(31,661), X_MASK, PPCCOM, { RS, RA, RB } },
4190 { "stsx", X(31,661), X_MASK, PWRCOM, { RS, RA, RB } },
4192 { "stwbrx", X(31,662), X_MASK, PPCCOM, { RS, RA, RB } },
4193 { "stbrx", X(31,662), X_MASK, PWRCOM, { RS, RA, RB } },
4195 { "stfsx", X(31,663), X_MASK, COM, { FRS, RA, RB } },
4197 { "srq", XRC(31,664,0), X_MASK, M601, { RA, RS, RB } },
4198 { "srq.", XRC(31,664,1), X_MASK, M601, { RA, RS, RB } },
4200 { "sre", XRC(31,665,0), X_MASK, M601, { RA, RS, RB } },
4201 { "sre.", XRC(31,665,1), X_MASK, M601, { RA, RS, RB } },
4203 { "stwbrxe", X(31,670), X_MASK, BOOKE64, { RS, RA, RB } },
4205 { "stfsxe", X(31,671), X_MASK, BOOKE64, { FRS, RA, RB } },
4207 { "stfsux", X(31,695), X_MASK, COM, { FRS, RAS, RB } },
4209 { "sriq", XRC(31,696,0), X_MASK, M601, { RA, RS, SH } },
4210 { "sriq.", XRC(31,696,1), X_MASK, M601, { RA, RS, SH } },
4212 { "stfsuxe", X(31,703), X_MASK, BOOKE64, { FRS, RAS, RB } },
4214 { "stswi", X(31,725), X_MASK, PPCCOM, { RS, RA, NB } },
4215 { "stsi", X(31,725), X_MASK, PWRCOM, { RS, RA, NB } },
4217 { "stfdx", X(31,727), X_MASK, COM, { FRS, RA, RB } },
4219 { "srlq", XRC(31,728,0), X_MASK, M601, { RA, RS, RB } },
4220 { "srlq.", XRC(31,728,1), X_MASK, M601, { RA, RS, RB } },
4222 { "sreq", XRC(31,729,0), X_MASK, M601, { RA, RS, RB } },
4223 { "sreq.", XRC(31,729,1), X_MASK, M601, { RA, RS, RB } },
4225 { "stfdxe", X(31,735), X_MASK, BOOKE64, { FRS, RA, RB } },
4227 { "dcba", X(31,758), XRT_MASK, PPC405, { RA, RB } },
4228 { "dcba", X(31,758), XRT_MASK, BOOKE, { RA, RB } },
4230 { "stfdux", X(31,759), X_MASK, COM, { FRS, RAS, RB } },
4232 { "srliq", XRC(31,760,0), X_MASK, M601, { RA, RS, SH } },
4233 { "srliq.", XRC(31,760,1), X_MASK, M601, { RA, RS, SH } },
4235 { "dcbae", X(31,766), XRT_MASK, BOOKE64, { RA, RB } },
4237 { "stfduxe", X(31,767), X_MASK, BOOKE64, { FRS, RAS, RB } },
4239 { "tlbivax", X(31,786), XRT_MASK, BOOKE, { RA, RB } },
4240 { "tlbivaxe",X(31,787), XRT_MASK, BOOKE64, { RA, RB } },
4242 { "lhbrx", X(31,790), X_MASK, COM, { RT, RA, RB } },
4244 { "sraw", XRC(31,792,0), X_MASK, PPCCOM, { RA, RS, RB } },
4245 { "sra", XRC(31,792,0), X_MASK, PWRCOM, { RA, RS, RB } },
4246 { "sraw.", XRC(31,792,1), X_MASK, PPCCOM, { RA, RS, RB } },
4247 { "sra.", XRC(31,792,1), X_MASK, PWRCOM, { RA, RS, RB } },
4249 { "srad", XRC(31,794,0), X_MASK, PPC64, { RA, RS, RB } },
4250 { "srad.", XRC(31,794,1), X_MASK, PPC64, { RA, RS, RB } },
4252 { "lhbrxe", X(31,798), X_MASK, BOOKE64, { RT, RA, RB } },
4254 { "ldxe", X(31,799), X_MASK, BOOKE64, { RT, RA, RB } },
4255 { "lduxe", X(31,831), X_MASK, BOOKE64, { RT, RA, RB } },
4257 { "rac", X(31,818), X_MASK, PWRCOM, { RT, RA, RB } },
4259 { "dss", XDSS(31,822,0), XDSS_MASK, PPCVEC, { STRM } },
4260 { "dssall", XDSS(31,822,1), XDSS_MASK, PPCVEC, { 0 } },
4262 { "srawi", XRC(31,824,0), X_MASK, PPCCOM, { RA, RS, SH } },
4263 { "srai", XRC(31,824,0), X_MASK, PWRCOM, { RA, RS, SH } },
4264 { "srawi.", XRC(31,824,1), X_MASK, PPCCOM, { RA, RS, SH } },
4265 { "srai.", XRC(31,824,1), X_MASK, PWRCOM, { RA, RS, SH } },
4267 { "slbmfev", X(31,851), XRA_MASK, PPC64, { RT, RB } },
4269 { "mbar", X(31,854), X_MASK, BOOKE, { MO } },
4270 { "eieio", X(31,854), 0xffffffff, PPC, { 0 } },
4272 { "tlbsx", XRC(31,914,0), X_MASK, PPC403, { RT, RA, RB } },
4273 { "tlbsx.", XRC(31,914,1), X_MASK, PPC403, { RT, RA, RB } },
4275 { "tlbsx", XRC(31,914,0), X_MASK, BOOKE, { RA, RB } },
4276 { "tlbsx.", XRC(31,914,1), X_MASK, BOOKE, { RA, RB } },
4277 { "tlbsxe", XRC(31,915,0), X_MASK, BOOKE64, { RA, RB } },
4278 { "tlbsxe.", XRC(31,915,1), X_MASK, BOOKE64, { RA, RB } },
4280 { "slbmfee", X(31,915), XRA_MASK, PPC64, { RT, RB } },
4282 { "sthbrx", X(31,918), X_MASK, COM, { RS, RA, RB } },
4284 { "sraq", XRC(31,920,0), X_MASK, M601, { RA, RS, RB } },
4285 { "sraq.", XRC(31,920,1), X_MASK, M601, { RA, RS, RB } },
4287 { "srea", XRC(31,921,0), X_MASK, M601, { RA, RS, RB } },
4288 { "srea.", XRC(31,921,1), X_MASK, M601, { RA, RS, RB } },
4290 { "extsh", XRC(31,922,0), XRB_MASK, PPCCOM, { RA, RS } },
4291 { "exts", XRC(31,922,0), XRB_MASK, PWRCOM, { RA, RS } },
4292 { "extsh.", XRC(31,922,1), XRB_MASK, PPCCOM, { RA, RS } },
4293 { "exts.", XRC(31,922,1), XRB_MASK, PWRCOM, { RA, RS } },
4295 { "sthbrxe", X(31,926), X_MASK, BOOKE64, { RS, RA, RB } },
4297 { "stdxe", X(31,927), X_MASK, BOOKE64, { RS, RA, RB } },
4299 { "tlbre", X(31,946), X_MASK, BOOKE, { 0 } },
4301 { "tlbrehi", XTLB(31,946,0), XTLB_MASK, PPC403, { RT, RA } },
4302 { "tlbrelo", XTLB(31,946,1), XTLB_MASK, PPC403, { RT, RA } },
4303 { "tlbre", X(31,946), X_MASK, PPC403, { RS, RA, SH } },
4305 { "sraiq", XRC(31,952,0), X_MASK, M601, { RA, RS, SH } },
4306 { "sraiq.", XRC(31,952,1), X_MASK, M601, { RA, RS, SH } },
4308 { "extsb", XRC(31,954,0), XRB_MASK, PPC, { RA, RS} },
4309 { "extsb.", XRC(31,954,1), XRB_MASK, PPC, { RA, RS} },
4311 { "stduxe", X(31,959), X_MASK, BOOKE64, { RS, RAS, RB } },
4313 { "iccci", X(31,966), XRT_MASK, PPC403, { RA, RB } },
4315 { "tlbwe", X(31,978), X_MASK, BOOKE, { 0 } },
4317 { "tlbld", X(31,978), XRTRA_MASK, PPC, { RB } },
4319 { "tlbwehi", XTLB(31,978,0), XTLB_MASK, PPC403, { RT, RA } },
4320 { "tlbwelo", XTLB(31,978,1), XTLB_MASK, PPC403, { RT, RA } },
4321 { "tlbwe", X(31,978), X_MASK, PPC403, { RS, RA, SH } },
4323 { "icbi", X(31,982), XRT_MASK, PPC, { RA, RB } },
4325 { "stfiwx", X(31,983), X_MASK, PPC, { FRS, RA, RB } },
4327 { "extsw", XRC(31,986,0), XRB_MASK, PPC64 | BOOKE64,{ RA, RS } },
4328 { "extsw.", XRC(31,986,1), XRB_MASK, PPC64, { RA, RS } },
4330 { "icread", X(31,998), XRT_MASK, PPC403, { RA, RB } },
4332 { "icbie", X(31,990), XRT_MASK, BOOKE64, { RA, RB } },
4333 { "stfiwxe", X(31,991), X_MASK, BOOKE64, { FRS, RA, RB } },
4335 { "tlbli", X(31,1010), XRTRA_MASK, PPC, { RB } },
4337 { "dcbz", X(31,1014), XRT_MASK, PPC, { RA, RB } },
4338 { "dclz", X(31,1014), XRT_MASK, PPC, { RA, RB } },
4340 { "dcbze", X(31,1022), XRT_MASK, BOOKE64, { RA, RB } },
4342 { "lvebx", X(31, 7), X_MASK, PPCVEC, { VD, RA, RB } },
4343 { "lvehx", X(31, 39), X_MASK, PPCVEC, { VD, RA, RB } },
4344 { "lvewx", X(31, 71), X_MASK, PPCVEC, { VD, RA, RB } },
4345 { "lvsl", X(31, 6), X_MASK, PPCVEC, { VD, RA, RB } },
4346 { "lvsr", X(31, 38), X_MASK, PPCVEC, { VD, RA, RB } },
4347 { "lvx", X(31, 103), X_MASK, PPCVEC, { VD, RA, RB } },
4348 { "lvxl", X(31, 359), X_MASK, PPCVEC, { VD, RA, RB } },
4349 { "stvebx", X(31, 135), X_MASK, PPCVEC, { VS, RA, RB } },
4350 { "stvehx", X(31, 167), X_MASK, PPCVEC, { VS, RA, RB } },
4351 { "stvewx", X(31, 199), X_MASK, PPCVEC, { VS, RA, RB } },
4352 { "stvx", X(31, 231), X_MASK, PPCVEC, { VS, RA, RB } },
4353 { "stvxl", X(31, 487), X_MASK, PPCVEC, { VS, RA, RB } },
4355 { "lwz", OP(32), OP_MASK, PPCCOM, { RT, D, RA } },
4356 { "l", OP(32), OP_MASK, PWRCOM, { RT, D, RA } },
4358 { "lwzu", OP(33), OP_MASK, PPCCOM, { RT, D, RAL } },
4359 { "lu", OP(33), OP_MASK, PWRCOM, { RT, D, RA } },
4361 { "lbz", OP(34), OP_MASK, COM, { RT, D, RA } },
4363 { "lbzu", OP(35), OP_MASK, COM, { RT, D, RAL } },
4365 { "stw", OP(36), OP_MASK, PPCCOM, { RS, D, RA } },
4366 { "st", OP(36), OP_MASK, PWRCOM, { RS, D, RA } },
4368 { "stwu", OP(37), OP_MASK, PPCCOM, { RS, D, RAS } },
4369 { "stu", OP(37), OP_MASK, PWRCOM, { RS, D, RA } },
4371 { "stb", OP(38), OP_MASK, COM, { RS, D, RA } },
4373 { "stbu", OP(39), OP_MASK, COM, { RS, D, RAS } },
4375 { "lhz", OP(40), OP_MASK, COM, { RT, D, RA } },
4377 { "lhzu", OP(41), OP_MASK, COM, { RT, D, RAL } },
4379 { "lha", OP(42), OP_MASK, COM, { RT, D, RA } },
4381 { "lhau", OP(43), OP_MASK, COM, { RT, D, RAL } },
4383 { "sth", OP(44), OP_MASK, COM, { RS, D, RA } },
4385 { "sthu", OP(45), OP_MASK, COM, { RS, D, RAS } },
4387 { "lmw", OP(46), OP_MASK, PPCCOM, { RT, D, RAM } },
4388 { "lm", OP(46), OP_MASK, PWRCOM, { RT, D, RA } },
4390 { "stmw", OP(47), OP_MASK, PPCCOM, { RS, D, RA } },
4391 { "stm", OP(47), OP_MASK, PWRCOM, { RS, D, RA } },
4393 { "lfs", OP(48), OP_MASK, COM, { FRT, D, RA } },
4395 { "lfsu", OP(49), OP_MASK, COM, { FRT, D, RAS } },
4397 { "lfd", OP(50), OP_MASK, COM, { FRT, D, RA } },
4399 { "lfdu", OP(51), OP_MASK, COM, { FRT, D, RAS } },
4401 { "stfs", OP(52), OP_MASK, COM, { FRS, D, RA } },
4403 { "stfsu", OP(53), OP_MASK, COM, { FRS, D, RAS } },
4405 { "stfd", OP(54), OP_MASK, COM, { FRS, D, RA } },
4407 { "stfdu", OP(55), OP_MASK, COM, { FRS, D, RAS } },
4409 { "lq", OP(56), OP_MASK, POWER4, { RTQ, DQ, RAQ } },
4411 { "lfq", OP(56), OP_MASK, POWER2, { FRT, D, RA } },
4413 { "lfqu", OP(57), OP_MASK, POWER2, { FRT, D, RA } },
4415 { "lbze", DEO(58,0), DE_MASK, BOOKE64, { RT, DE, RA } },
4416 { "lbzue", DEO(58,1), DE_MASK, BOOKE64, { RT, DE, RAL } },
4417 { "lhze", DEO(58,2), DE_MASK, BOOKE64, { RT, DE, RA } },
4418 { "lhzue", DEO(58,3), DE_MASK, BOOKE64, { RT, DE, RAL } },
4419 { "lhae", DEO(58,4), DE_MASK, BOOKE64, { RT, DE, RA } },
4420 { "lhaue", DEO(58,5), DE_MASK, BOOKE64, { RT, DE, RAL } },
4421 { "lwze", DEO(58,6), DE_MASK, BOOKE64, { RT, DE, RA } },
4422 { "lwzue", DEO(58,7), DE_MASK, BOOKE64, { RT, DE, RAL } },
4423 { "stbe", DEO(58,8), DE_MASK, BOOKE64, { RS, DE, RA } },
4424 { "stbue", DEO(58,9), DE_MASK, BOOKE64, { RS, DE, RAS } },
4425 { "sthe", DEO(58,10), DE_MASK, BOOKE64, { RS, DE, RA } },
4426 { "sthue", DEO(58,11), DE_MASK, BOOKE64, { RS, DE, RAS } },
4427 { "stwe", DEO(58,14), DE_MASK, BOOKE64, { RS, DE, RA } },
4428 { "stwue", DEO(58,15), DE_MASK, BOOKE64, { RS, DE, RAS } },
4430 { "ld", DSO(58,0), DS_MASK, PPC64, { RT, DS, RA } },
4432 { "ldu", DSO(58,1), DS_MASK, PPC64, { RT, DS, RAL } },
4434 { "lwa", DSO(58,2), DS_MASK, PPC64, { RT, DS, RA } },
4436 { "fdivs", A(59,18,0), AFRC_MASK, PPC, { FRT, FRA, FRB } },
4437 { "fdivs.", A(59,18,1), AFRC_MASK, PPC, { FRT, FRA, FRB } },
4439 { "fsubs", A(59,20,0), AFRC_MASK, PPC, { FRT, FRA, FRB } },
4440 { "fsubs.", A(59,20,1), AFRC_MASK, PPC, { FRT, FRA, FRB } },
4442 { "fadds", A(59,21,0), AFRC_MASK, PPC, { FRT, FRA, FRB } },
4443 { "fadds.", A(59,21,1), AFRC_MASK, PPC, { FRT, FRA, FRB } },
4445 { "fsqrts", A(59,22,0), AFRAFRC_MASK, PPC, { FRT, FRB } },
4446 { "fsqrts.", A(59,22,1), AFRAFRC_MASK, PPC, { FRT, FRB } },
4448 { "fres", A(59,24,0), AFRAFRC_MASK, PPC, { FRT, FRB } },
4449 { "fres.", A(59,24,1), AFRAFRC_MASK, PPC, { FRT, FRB } },
4451 { "fmuls", A(59,25,0), AFRB_MASK, PPC, { FRT, FRA, FRC } },
4452 { "fmuls.", A(59,25,1), AFRB_MASK, PPC, { FRT, FRA, FRC } },
4454 { "fmsubs", A(59,28,0), A_MASK, PPC, { FRT,FRA,FRC,FRB } },
4455 { "fmsubs.", A(59,28,1), A_MASK, PPC, { FRT,FRA,FRC,FRB } },
4457 { "fmadds", A(59,29,0), A_MASK, PPC, { FRT,FRA,FRC,FRB } },
4458 { "fmadds.", A(59,29,1), A_MASK, PPC, { FRT,FRA,FRC,FRB } },
4460 { "fnmsubs", A(59,30,0), A_MASK, PPC, { FRT,FRA,FRC,FRB } },
4461 { "fnmsubs.",A(59,30,1), A_MASK, PPC, { FRT,FRA,FRC,FRB } },
4463 { "fnmadds", A(59,31,0), A_MASK, PPC, { FRT,FRA,FRC,FRB } },
4464 { "fnmadds.",A(59,31,1), A_MASK, PPC, { FRT,FRA,FRC,FRB } },
4466 { "stfq", OP(60), OP_MASK, POWER2, { FRS, D, RA } },
4468 { "stfqu", OP(61), OP_MASK, POWER2, { FRS, D, RA } },
4470 { "lde", DEO(62,0), DE_MASK, BOOKE64, { RT, DES, RA } },
4471 { "ldue", DEO(62,1), DE_MASK, BOOKE64, { RT, DES, RA } },
4472 { "lfse", DEO(62,4), DE_MASK, BOOKE64, { FRT, DES, RA } },
4473 { "lfsue", DEO(62,5), DE_MASK, BOOKE64, { FRT, DES, RAS } },
4474 { "lfde", DEO(62,6), DE_MASK, BOOKE64, { FRT, DES, RA } },
4475 { "lfdue", DEO(62,7), DE_MASK, BOOKE64, { FRT, DES, RAS } },
4476 { "stde", DEO(62,8), DE_MASK, BOOKE64, { RS, DES, RA } },
4477 { "stdue", DEO(62,9), DE_MASK, BOOKE64, { RS, DES, RAS } },
4478 { "stfse", DEO(62,12), DE_MASK, BOOKE64, { FRS, DES, RA } },
4479 { "stfsue", DEO(62,13), DE_MASK, BOOKE64, { FRS, DES, RAS } },
4480 { "stfde", DEO(62,14), DE_MASK, BOOKE64, { FRS, DES, RA } },
4481 { "stfdue", DEO(62,15), DE_MASK, BOOKE64, { FRS, DES, RAS } },
4483 { "std", DSO(62,0), DS_MASK, PPC64, { RS, DS, RA } },
4485 { "stdu", DSO(62,1), DS_MASK, PPC64, { RS, DS, RAS } },
4487 { "stq", DSO(62,2), DS_MASK, POWER4, { RSQ, DS, RA } },
4489 { "fcmpu", X(63,0), X_MASK|(3<<21), COM, { BF, FRA, FRB } },
4491 { "frsp", XRC(63,12,0), XRA_MASK, COM, { FRT, FRB } },
4492 { "frsp.", XRC(63,12,1), XRA_MASK, COM, { FRT, FRB } },
4494 { "fctiw", XRC(63,14,0), XRA_MASK, PPCCOM, { FRT, FRB } },
4495 { "fcir", XRC(63,14,0), XRA_MASK, POWER2, { FRT, FRB } },
4496 { "fctiw.", XRC(63,14,1), XRA_MASK, PPCCOM, { FRT, FRB } },
4497 { "fcir.", XRC(63,14,1), XRA_MASK, POWER2, { FRT, FRB } },
4499 { "fctiwz", XRC(63,15,0), XRA_MASK, PPCCOM, { FRT, FRB } },
4500 { "fcirz", XRC(63,15,0), XRA_MASK, POWER2, { FRT, FRB } },
4501 { "fctiwz.", XRC(63,15,1), XRA_MASK, PPCCOM, { FRT, FRB } },
4502 { "fcirz.", XRC(63,15,1), XRA_MASK, POWER2, { FRT, FRB } },
4504 { "fdiv", A(63,18,0), AFRC_MASK, PPCCOM, { FRT, FRA, FRB } },
4505 { "fd", A(63,18,0), AFRC_MASK, PWRCOM, { FRT, FRA, FRB } },
4506 { "fdiv.", A(63,18,1), AFRC_MASK, PPCCOM, { FRT, FRA, FRB } },
4507 { "fd.", A(63,18,1), AFRC_MASK, PWRCOM, { FRT, FRA, FRB } },
4509 { "fsub", A(63,20,0), AFRC_MASK, PPCCOM, { FRT, FRA, FRB } },
4510 { "fs", A(63,20,0), AFRC_MASK, PWRCOM, { FRT, FRA, FRB } },
4511 { "fsub.", A(63,20,1), AFRC_MASK, PPCCOM, { FRT, FRA, FRB } },
4512 { "fs.", A(63,20,1), AFRC_MASK, PWRCOM, { FRT, FRA, FRB } },
4514 { "fadd", A(63,21,0), AFRC_MASK, PPCCOM, { FRT, FRA, FRB } },
4515 { "fa", A(63,21,0), AFRC_MASK, PWRCOM, { FRT, FRA, FRB } },
4516 { "fadd.", A(63,21,1), AFRC_MASK, PPCCOM, { FRT, FRA, FRB } },
4517 { "fa.", A(63,21,1), AFRC_MASK, PWRCOM, { FRT, FRA, FRB } },
4519 { "fsqrt", A(63,22,0), AFRAFRC_MASK, PPCPWR2, { FRT, FRB } },
4520 { "fsqrt.", A(63,22,1), AFRAFRC_MASK, PPCPWR2, { FRT, FRB } },
4522 { "fsel", A(63,23,0), A_MASK, PPC, { FRT,FRA,FRC,FRB } },
4523 { "fsel.", A(63,23,1), A_MASK, PPC, { FRT,FRA,FRC,FRB } },
4525 { "fmul", A(63,25,0), AFRB_MASK, PPCCOM, { FRT, FRA, FRC } },
4526 { "fm", A(63,25,0), AFRB_MASK, PWRCOM, { FRT, FRA, FRC } },
4527 { "fmul.", A(63,25,1), AFRB_MASK, PPCCOM, { FRT, FRA, FRC } },
4528 { "fm.", A(63,25,1), AFRB_MASK, PWRCOM, { FRT, FRA, FRC } },
4530 { "frsqrte", A(63,26,0), AFRAFRC_MASK, PPC, { FRT, FRB } },
4531 { "frsqrte.",A(63,26,1), AFRAFRC_MASK, PPC, { FRT, FRB } },
4533 { "fmsub", A(63,28,0), A_MASK, PPCCOM, { FRT,FRA,FRC,FRB } },
4534 { "fms", A(63,28,0), A_MASK, PWRCOM, { FRT,FRA,FRC,FRB } },
4535 { "fmsub.", A(63,28,1), A_MASK, PPCCOM, { FRT,FRA,FRC,FRB } },
4536 { "fms.", A(63,28,1), A_MASK, PWRCOM, { FRT,FRA,FRC,FRB } },
4538 { "fmadd", A(63,29,0), A_MASK, PPCCOM, { FRT,FRA,FRC,FRB } },
4539 { "fma", A(63,29,0), A_MASK, PWRCOM, { FRT,FRA,FRC,FRB } },
4540 { "fmadd.", A(63,29,1), A_MASK, PPCCOM, { FRT,FRA,FRC,FRB } },
4541 { "fma.", A(63,29,1), A_MASK, PWRCOM, { FRT,FRA,FRC,FRB } },
4543 { "fnmsub", A(63,30,0), A_MASK, PPCCOM, { FRT,FRA,FRC,FRB } },
4544 { "fnms", A(63,30,0), A_MASK, PWRCOM, { FRT,FRA,FRC,FRB } },
4545 { "fnmsub.", A(63,30,1), A_MASK, PPCCOM, { FRT,FRA,FRC,FRB } },
4546 { "fnms.", A(63,30,1), A_MASK, PWRCOM, { FRT,FRA,FRC,FRB } },
4548 { "fnmadd", A(63,31,0), A_MASK, PPCCOM, { FRT,FRA,FRC,FRB } },
4549 { "fnma", A(63,31,0), A_MASK, PWRCOM, { FRT,FRA,FRC,FRB } },
4550 { "fnmadd.", A(63,31,1), A_MASK, PPCCOM, { FRT,FRA,FRC,FRB } },
4551 { "fnma.", A(63,31,1), A_MASK, PWRCOM, { FRT,FRA,FRC,FRB } },
4553 { "fcmpo", X(63,32), X_MASK|(3<<21), COM, { BF, FRA, FRB } },
4555 { "mtfsb1", XRC(63,38,0), XRARB_MASK, COM, { BT } },
4556 { "mtfsb1.", XRC(63,38,1), XRARB_MASK, COM, { BT } },
4558 { "fneg", XRC(63,40,0), XRA_MASK, COM, { FRT, FRB } },
4559 { "fneg.", XRC(63,40,1), XRA_MASK, COM, { FRT, FRB } },
4561 { "mcrfs", X(63,64), XRB_MASK|(3<<21)|(3<<16), COM, { BF, BFA } },
4563 { "mtfsb0", XRC(63,70,0), XRARB_MASK, COM, { BT } },
4564 { "mtfsb0.", XRC(63,70,1), XRARB_MASK, COM, { BT } },
4566 { "fmr", XRC(63,72,0), XRA_MASK, COM, { FRT, FRB } },
4567 { "fmr.", XRC(63,72,1), XRA_MASK, COM, { FRT, FRB } },
4569 { "mtfsfi", XRC(63,134,0), XRA_MASK|(3<<21)|(1<<11), COM, { BF, U } },
4570 { "mtfsfi.", XRC(63,134,1), XRA_MASK|(3<<21)|(1<<11), COM, { BF, U } },
4572 { "fnabs", XRC(63,136,0), XRA_MASK, COM, { FRT, FRB } },
4573 { "fnabs.", XRC(63,136,1), XRA_MASK, COM, { FRT, FRB } },
4575 { "fabs", XRC(63,264,0), XRA_MASK, COM, { FRT, FRB } },
4576 { "fabs.", XRC(63,264,1), XRA_MASK, COM, { FRT, FRB } },
4578 { "mffs", XRC(63,583,0), XRARB_MASK, COM, { FRT } },
4579 { "mffs.", XRC(63,583,1), XRARB_MASK, COM, { FRT } },
4581 { "mtfsf", XFL(63,711,0), XFL_MASK, COM, { FLM, FRB } },
4582 { "mtfsf.", XFL(63,711,1), XFL_MASK, COM, { FLM, FRB } },
4584 { "fctid", XRC(63,814,0), XRA_MASK, PPC64, { FRT, FRB } },
4585 { "fctid.", XRC(63,814,1), XRA_MASK, PPC64, { FRT, FRB } },
4587 { "fctidz", XRC(63,815,0), XRA_MASK, PPC64, { FRT, FRB } },
4588 { "fctidz.", XRC(63,815,1), XRA_MASK, PPC64, { FRT, FRB } },
4590 { "fcfid", XRC(63,846,0), XRA_MASK, PPC64, { FRT, FRB } },
4591 { "fcfid.", XRC(63,846,1), XRA_MASK, PPC64, { FRT, FRB } },
4595 const int powerpc_num_opcodes =
4596 sizeof (powerpc_opcodes) / sizeof (powerpc_opcodes[0]);
4598 /* The macro table. This is only used by the assembler. */
4600 /* The expressions of the form (-x ! 31) & (x | 31) have the value 0
4601 when x=0; 32-x when x is between 1 and 31; are negative if x is
4602 negative; and are 32 or more otherwise. This is what you want
4603 when, for instance, you are emulating a right shift by a
4604 rotate-left-and-mask, because the underlying instructions support
4605 shifts of size 0 but not shifts of size 32. By comparison, when
4606 extracting x bits from some word you want to use just 32-x, because
4607 the underlying instructions don't support extracting 0 bits but do
4608 support extracting the whole word (32 bits in this case). */
4610 const struct powerpc_macro powerpc_macros[] = {
4611 { "extldi", 4, PPC64, "rldicr %0,%1,%3,(%2)-1" },
4612 { "extldi.", 4, PPC64, "rldicr. %0,%1,%3,(%2)-1" },
4613 { "extrdi", 4, PPC64, "rldicl %0,%1,(%2)+(%3),64-(%2)" },
4614 { "extrdi.", 4, PPC64, "rldicl. %0,%1,(%2)+(%3),64-(%2)" },
4615 { "insrdi", 4, PPC64, "rldimi %0,%1,64-((%2)+(%3)),%3" },
4616 { "insrdi.", 4, PPC64, "rldimi. %0,%1,64-((%2)+(%3)),%3" },
4617 { "rotrdi", 3, PPC64, "rldicl %0,%1,(-(%2)!63)&((%2)|63),0" },
4618 { "rotrdi.", 3, PPC64, "rldicl. %0,%1,(-(%2)!63)&((%2)|63),0" },
4619 { "sldi", 3, PPC64, "rldicr %0,%1,%2,63-(%2)" },
4620 { "sldi.", 3, PPC64, "rldicr. %0,%1,%2,63-(%2)" },
4621 { "srdi", 3, PPC64, "rldicl %0,%1,(-(%2)!63)&((%2)|63),%2" },
4622 { "srdi.", 3, PPC64, "rldicl. %0,%1,(-(%2)!63)&((%2)|63),%2" },
4623 { "clrrdi", 3, PPC64, "rldicr %0,%1,0,63-(%2)" },
4624 { "clrrdi.", 3, PPC64, "rldicr. %0,%1,0,63-(%2)" },
4625 { "clrlsldi",4, PPC64, "rldic %0,%1,%3,(%2)-(%3)" },
4626 { "clrlsldi.",4, PPC64, "rldic. %0,%1,%3,(%2)-(%3)" },
4628 { "extlwi", 4, PPCCOM, "rlwinm %0,%1,%3,0,(%2)-1" },
4629 { "extlwi.", 4, PPCCOM, "rlwinm. %0,%1,%3,0,(%2)-1" },
4630 { "extrwi", 4, PPCCOM, "rlwinm %0,%1,((%2)+(%3))&((%2)+(%3)<>32),32-(%2),31" },
4631 { "extrwi.", 4, PPCCOM, "rlwinm. %0,%1,((%2)+(%3))&((%2)+(%3)<>32),32-(%2),31" },
4632 { "inslwi", 4, PPCCOM, "rlwimi %0,%1,(-(%3)!31)&((%3)|31),%3,(%2)+(%3)-1" },
4633 { "inslwi.", 4, PPCCOM, "rlwimi. %0,%1,(-(%3)!31)&((%3)|31),%3,(%2)+(%3)-1"},
4634 { "insrwi", 4, PPCCOM, "rlwimi %0,%1,32-((%2)+(%3)),%3,(%2)+(%3)-1" },
4635 { "insrwi.", 4, PPCCOM, "rlwimi. %0,%1,32-((%2)+(%3)),%3,(%2)+(%3)-1"},
4636 { "rotrwi", 3, PPCCOM, "rlwinm %0,%1,(-(%2)!31)&((%2)|31),0,31" },
4637 { "rotrwi.", 3, PPCCOM, "rlwinm. %0,%1,(-(%2)!31)&((%2)|31),0,31" },
4638 { "slwi", 3, PPCCOM, "rlwinm %0,%1,%2,0,31-(%2)" },
4639 { "sli", 3, PWRCOM, "rlinm %0,%1,%2,0,31-(%2)" },
4640 { "slwi.", 3, PPCCOM, "rlwinm. %0,%1,%2,0,31-(%2)" },
4641 { "sli.", 3, PWRCOM, "rlinm. %0,%1,%2,0,31-(%2)" },
4642 { "srwi", 3, PPCCOM, "rlwinm %0,%1,(-(%2)!31)&((%2)|31),%2,31" },
4643 { "sri", 3, PWRCOM, "rlinm %0,%1,(-(%2)!31)&((%2)|31),%2,31" },
4644 { "srwi.", 3, PPCCOM, "rlwinm. %0,%1,(-(%2)!31)&((%2)|31),%2,31" },
4645 { "sri.", 3, PWRCOM, "rlinm. %0,%1,(-(%2)!31)&((%2)|31),%2,31" },
4646 { "clrrwi", 3, PPCCOM, "rlwinm %0,%1,0,0,31-(%2)" },
4647 { "clrrwi.", 3, PPCCOM, "rlwinm. %0,%1,0,0,31-(%2)" },
4648 { "clrlslwi",4, PPCCOM, "rlwinm %0,%1,%3,(%2)-(%3),31-(%3)" },
4649 { "clrlslwi.",4, PPCCOM, "rlwinm. %0,%1,%3,(%2)-(%3),31-(%3)" },
4652 const int powerpc_num_macros =
4653 sizeof (powerpc_macros) / sizeof (powerpc_macros[0]);