1 /* ppc-opc.c -- PowerPC opcode list
2 Copyright (C) 1994-2016 Free Software Foundation, Inc.
3 Written by Ian Lance Taylor, Cygnus Support
5 This file is part of the GNU opcodes library.
7 This library is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 3, or (at your option)
12 It is distributed in the hope that it will be useful, but WITHOUT
13 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
14 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
15 License for more details.
17 You should have received a copy of the GNU General Public License
18 along with this file; see the file COPYING. If not, write to the
19 Free Software Foundation, 51 Franklin Street - Fifth Floor, Boston,
20 MA 02110-1301, USA. */
24 #include "opcode/ppc.h"
27 /* This file holds the PowerPC opcode table. The opcode table
28 includes almost all of the extended instruction mnemonics. This
29 permits the disassembler to use them, and simplifies the assembler
30 logic, at the cost of increasing the table size. The table is
31 strictly constant data, so the compiler should be able to put it in
34 This file also holds the operand table. All knowledge about
35 inserting operands into instructions and vice-versa is kept in this
38 /* Local insertion and extraction functions. */
40 static unsigned long insert_arx (unsigned long, long, ppc_cpu_t, const char **);
41 static long extract_arx (unsigned long, ppc_cpu_t, int *);
42 static unsigned long insert_ary (unsigned long, long, ppc_cpu_t, const char **);
43 static long extract_ary (unsigned long, ppc_cpu_t, int *);
44 static unsigned long insert_bat (unsigned long, long, ppc_cpu_t, const char **);
45 static long extract_bat (unsigned long, ppc_cpu_t, int *);
46 static unsigned long insert_bba (unsigned long, long, ppc_cpu_t, const char **);
47 static long extract_bba (unsigned long, ppc_cpu_t, int *);
48 static unsigned long insert_bdm (unsigned long, long, ppc_cpu_t, const char **);
49 static long extract_bdm (unsigned long, ppc_cpu_t, int *);
50 static unsigned long insert_bdp (unsigned long, long, ppc_cpu_t, const char **);
51 static long extract_bdp (unsigned long, ppc_cpu_t, int *);
52 static unsigned long insert_bo (unsigned long, long, ppc_cpu_t, const char **);
53 static long extract_bo (unsigned long, ppc_cpu_t, int *);
54 static unsigned long insert_boe (unsigned long, long, ppc_cpu_t, const char **);
55 static long extract_boe (unsigned long, ppc_cpu_t, int *);
56 static unsigned long insert_esync (unsigned long, long, ppc_cpu_t, const char **);
57 static unsigned long insert_dcmxs (unsigned long, long, ppc_cpu_t, const char **);
58 static long extract_dcmxs (unsigned long, ppc_cpu_t, int *);
59 static unsigned long insert_dxd (unsigned long, long, ppc_cpu_t, const char **);
60 static long extract_dxd (unsigned long, ppc_cpu_t, int *);
61 static unsigned long insert_dxdn (unsigned long, long, ppc_cpu_t, const char **);
62 static long extract_dxdn (unsigned long, ppc_cpu_t, int *);
63 static unsigned long insert_fxm (unsigned long, long, ppc_cpu_t, const char **);
64 static long extract_fxm (unsigned long, ppc_cpu_t, int *);
65 static unsigned long insert_l0 (unsigned long, long, ppc_cpu_t, const char **);
66 static long extract_l0 (unsigned long, ppc_cpu_t, int *);
67 static unsigned long insert_l1 (unsigned long, long, ppc_cpu_t, const char **);
68 static long extract_l1 (unsigned long, ppc_cpu_t, int *);
69 static unsigned long insert_li20 (unsigned long, long, ppc_cpu_t, const char **);
70 static long extract_li20 (unsigned long, ppc_cpu_t, int *);
71 static unsigned long insert_ls (unsigned long, long, ppc_cpu_t, const char **);
72 static unsigned long insert_mbe (unsigned long, long, ppc_cpu_t, const char **);
73 static long extract_mbe (unsigned long, ppc_cpu_t, int *);
74 static unsigned long insert_mb6 (unsigned long, long, ppc_cpu_t, const char **);
75 static long extract_mb6 (unsigned long, ppc_cpu_t, int *);
76 static long extract_nb (unsigned long, ppc_cpu_t, int *);
77 static unsigned long insert_nbi (unsigned long, long, ppc_cpu_t, const char **);
78 static unsigned long insert_nsi (unsigned long, long, ppc_cpu_t, const char **);
79 static long extract_nsi (unsigned long, ppc_cpu_t, int *);
80 static unsigned long insert_oimm (unsigned long, long, ppc_cpu_t, const char **);
81 static long extract_oimm (unsigned long, ppc_cpu_t, int *);
82 static unsigned long insert_ral (unsigned long, long, ppc_cpu_t, const char **);
83 static unsigned long insert_ram (unsigned long, long, ppc_cpu_t, const char **);
84 static unsigned long insert_raq (unsigned long, long, ppc_cpu_t, const char **);
85 static unsigned long insert_ras (unsigned long, long, ppc_cpu_t, const char **);
86 static unsigned long insert_rbs (unsigned long, long, ppc_cpu_t, const char **);
87 static long extract_rbs (unsigned long, ppc_cpu_t, int *);
88 static unsigned long insert_rbx (unsigned long, long, ppc_cpu_t, const char **);
89 static unsigned long insert_rx (unsigned long, long, ppc_cpu_t, const char **);
90 static long extract_rx (unsigned long, ppc_cpu_t, int *);
91 static unsigned long insert_ry (unsigned long, long, ppc_cpu_t, const char **);
92 static long extract_ry (unsigned long, ppc_cpu_t, int *);
93 static unsigned long insert_sh6 (unsigned long, long, ppc_cpu_t, const char **);
94 static long extract_sh6 (unsigned long, ppc_cpu_t, int *);
95 static unsigned long insert_sci8 (unsigned long, long, ppc_cpu_t, const char **);
96 static long extract_sci8 (unsigned long, ppc_cpu_t, int *);
97 static unsigned long insert_sci8n (unsigned long, long, ppc_cpu_t, const char **);
98 static long extract_sci8n (unsigned long, ppc_cpu_t, int *);
99 static unsigned long insert_sd4h (unsigned long, long, ppc_cpu_t, const char **);
100 static long extract_sd4h (unsigned long, ppc_cpu_t, int *);
101 static unsigned long insert_sd4w (unsigned long, long, ppc_cpu_t, const char **);
102 static long extract_sd4w (unsigned long, ppc_cpu_t, int *);
103 static unsigned long insert_spr (unsigned long, long, ppc_cpu_t, const char **);
104 static long extract_spr (unsigned long, ppc_cpu_t, int *);
105 static unsigned long insert_sprg (unsigned long, long, ppc_cpu_t, const char **);
106 static long extract_sprg (unsigned long, ppc_cpu_t, int *);
107 static unsigned long insert_tbr (unsigned long, long, ppc_cpu_t, const char **);
108 static long extract_tbr (unsigned long, ppc_cpu_t, int *);
109 static unsigned long insert_xt6 (unsigned long, long, ppc_cpu_t, const char **);
110 static long extract_xt6 (unsigned long, ppc_cpu_t, int *);
111 static unsigned long insert_xtq6 (unsigned long, long, ppc_cpu_t, const char **);
112 static long extract_xtq6 (unsigned long, ppc_cpu_t, int *);
113 static unsigned long insert_xa6 (unsigned long, long, ppc_cpu_t, const char **);
114 static long extract_xa6 (unsigned long, ppc_cpu_t, int *);
115 static unsigned long insert_xb6 (unsigned long, long, ppc_cpu_t, const char **);
116 static long extract_xb6 (unsigned long, ppc_cpu_t, int *);
117 static unsigned long insert_xb6s (unsigned long, long, ppc_cpu_t, const char **);
118 static long extract_xb6s (unsigned long, ppc_cpu_t, int *);
119 static unsigned long insert_xc6 (unsigned long, long, ppc_cpu_t, const char **);
120 static long extract_xc6 (unsigned long, ppc_cpu_t, int *);
121 static unsigned long insert_dm (unsigned long, long, ppc_cpu_t, const char **);
122 static long extract_dm (unsigned long, ppc_cpu_t, int *);
123 static unsigned long insert_vlesi (unsigned long, long, ppc_cpu_t, const char **);
124 static long extract_vlesi (unsigned long, ppc_cpu_t, int *);
125 static unsigned long insert_vlensi (unsigned long, long, ppc_cpu_t, const char **);
126 static long extract_vlensi (unsigned long, ppc_cpu_t, int *);
127 static unsigned long insert_vleui (unsigned long, long, ppc_cpu_t, const char **);
128 static long extract_vleui (unsigned long, ppc_cpu_t, int *);
129 static unsigned long insert_vleil (unsigned long, long, ppc_cpu_t, const char **);
130 static long extract_vleil (unsigned long, ppc_cpu_t, int *);
132 /* The operands table.
134 The fields are bitm, shift, insert, extract, flags.
136 We used to put parens around the various additions, like the one
137 for BA just below. However, that caused trouble with feeble
138 compilers with a limit on depth of a parenthesized expression, like
139 (reportedly) the compiler in Microsoft Developer Studio 5. So we
140 omit the parens, since the macros are never used in a context where
141 the addition will be ambiguous. */
143 const struct powerpc_operand powerpc_operands[] =
145 /* The zero index is used to indicate the end of the list of
148 { 0, 0, NULL, NULL, 0 },
150 /* The BA field in an XL form instruction. */
151 #define BA UNUSED + 1
152 /* The BI field in a B form or XL form instruction. */
154 #define BI_MASK (0x1f << 16)
155 { 0x1f, 16, NULL, NULL, PPC_OPERAND_CR_BIT },
157 /* The BA field in an XL form instruction when it must be the same
158 as the BT field in the same instruction. */
160 { 0x1f, 16, insert_bat, extract_bat, PPC_OPERAND_FAKE },
162 /* The BB field in an XL form instruction. */
164 #define BB_MASK (0x1f << 11)
165 { 0x1f, 11, NULL, NULL, PPC_OPERAND_CR_BIT },
167 /* The BB field in an XL form instruction when it must be the same
168 as the BA field in the same instruction. */
170 /* The VB field in a VX form instruction when it must be the same
171 as the VA field in the same instruction. */
173 { 0x1f, 11, insert_bba, extract_bba, PPC_OPERAND_FAKE },
175 /* The BD field in a B form instruction. The lower two bits are
178 { 0xfffc, 0, NULL, NULL, PPC_OPERAND_RELATIVE | PPC_OPERAND_SIGNED },
180 /* The BD field in a B form instruction when absolute addressing is
183 { 0xfffc, 0, NULL, NULL, PPC_OPERAND_ABSOLUTE | PPC_OPERAND_SIGNED },
185 /* The BD field in a B form instruction when the - modifier is used.
186 This sets the y bit of the BO field appropriately. */
188 { 0xfffc, 0, insert_bdm, extract_bdm,
189 PPC_OPERAND_RELATIVE | PPC_OPERAND_SIGNED },
191 /* The BD field in a B form instruction when the - modifier is used
192 and absolute address is used. */
194 { 0xfffc, 0, insert_bdm, extract_bdm,
195 PPC_OPERAND_ABSOLUTE | PPC_OPERAND_SIGNED },
197 /* The BD field in a B form instruction when the + modifier is used.
198 This sets the y bit of the BO field appropriately. */
200 { 0xfffc, 0, insert_bdp, extract_bdp,
201 PPC_OPERAND_RELATIVE | PPC_OPERAND_SIGNED },
203 /* The BD field in a B form instruction when the + modifier is used
204 and absolute addressing is used. */
206 { 0xfffc, 0, insert_bdp, extract_bdp,
207 PPC_OPERAND_ABSOLUTE | PPC_OPERAND_SIGNED },
209 /* The BF field in an X or XL form instruction. */
211 /* The CRFD field in an X form instruction. */
213 /* The CRD field in an XL form instruction. */
215 { 0x7, 23, NULL, NULL, PPC_OPERAND_CR_REG },
217 /* The BF field in an X or XL form instruction. */
219 { 0x7, 23, NULL, NULL, 0 },
221 /* An optional BF field. This is used for comparison instructions,
222 in which an omitted BF field is taken as zero. */
224 { 0x7, 23, NULL, NULL, PPC_OPERAND_CR_REG | PPC_OPERAND_OPTIONAL },
226 /* The BFA field in an X or XL form instruction. */
228 { 0x7, 18, NULL, NULL, PPC_OPERAND_CR_REG },
230 /* The BO field in a B form instruction. Certain values are
233 #define BO_MASK (0x1f << 21)
234 { 0x1f, 21, insert_bo, extract_bo, 0 },
236 /* The BO field in a B form instruction when the + or - modifier is
237 used. This is like the BO field, but it must be even. */
239 { 0x1e, 21, insert_boe, extract_boe, 0 },
242 { 0x3, 11, NULL, NULL, PPC_OPERAND_OPTIONAL },
244 /* The BT field in an X or XL form instruction. */
246 { 0x1f, 21, NULL, NULL, PPC_OPERAND_CR_BIT },
248 /* The BI16 field in a BD8 form instruction. */
250 { 0x3, 8, NULL, NULL, PPC_OPERAND_CR_BIT },
252 /* The BI32 field in a BD15 form instruction. */
253 #define BI32 BI16 + 1
254 { 0xf, 16, NULL, NULL, PPC_OPERAND_CR_BIT },
256 /* The BO32 field in a BD15 form instruction. */
257 #define BO32 BI32 + 1
258 { 0x3, 20, NULL, NULL, 0 },
260 /* The B8 field in a BD8 form instruction. */
262 { 0x1fe, -1, NULL, NULL, PPC_OPERAND_RELATIVE | PPC_OPERAND_SIGNED },
264 /* The B15 field in a BD15 form instruction. The lowest bit is
267 { 0xfffe, 0, NULL, NULL, PPC_OPERAND_RELATIVE | PPC_OPERAND_SIGNED },
269 /* The B24 field in a BD24 form instruction. The lowest bit is
272 { 0x1fffffe, 0, NULL, NULL, PPC_OPERAND_RELATIVE | PPC_OPERAND_SIGNED },
274 /* The condition register number portion of the BI field in a B form
275 or XL form instruction. This is used for the extended
276 conditional branch mnemonics, which set the lower two bits of the
277 BI field. This field is optional. */
279 { 0x7, 18, NULL, NULL, PPC_OPERAND_CR_REG | PPC_OPERAND_OPTIONAL },
281 /* The CRB field in an X form instruction. */
283 /* The MB field in an M form instruction. */
285 #define MB_MASK (0x1f << 6)
286 { 0x1f, 6, NULL, NULL, 0 },
288 /* The CRD32 field in an XL form instruction. */
289 #define CRD32 CRB + 1
290 { 0x3, 21, NULL, NULL, PPC_OPERAND_CR_REG },
292 /* The CRFS field in an X form instruction. */
293 #define CRFS CRD32 + 1
294 { 0x7, 0, NULL, NULL, PPC_OPERAND_CR_REG },
297 { 0x3, 18, NULL, NULL, PPC_OPERAND_CR_REG | PPC_OPERAND_OPTIONAL },
299 /* The CT field in an X form instruction. */
301 /* The MO field in an mbar instruction. */
303 { 0x1f, 21, NULL, NULL, PPC_OPERAND_OPTIONAL },
305 /* The D field in a D form instruction. This is a displacement off
306 a register, and implies that the next operand is a register in
309 { 0xffff, 0, NULL, NULL, PPC_OPERAND_PARENS | PPC_OPERAND_SIGNED },
311 /* The D8 field in a D form instruction. This is a displacement off
312 a register, and implies that the next operand is a register in
315 { 0xff, 0, NULL, NULL, PPC_OPERAND_PARENS | PPC_OPERAND_SIGNED },
317 /* The DCMX field in an X form instruction. */
319 { 0x7f, 16, NULL, NULL, 0 },
321 /* The split DCMX field in an X form instruction. */
322 #define DCMXS DCMX + 1
323 { 0x7f, PPC_OPSHIFT_INV, insert_dcmxs, extract_dcmxs, 0 },
325 /* The DQ field in a DQ form instruction. This is like D, but the
326 lower four bits are forced to zero. */
328 { 0xfff0, 0, NULL, NULL,
329 PPC_OPERAND_PARENS | PPC_OPERAND_SIGNED | PPC_OPERAND_DQ },
331 /* The DS field in a DS form instruction. This is like D, but the
332 lower two bits are forced to zero. */
334 { 0xfffc, 0, NULL, NULL,
335 PPC_OPERAND_PARENS | PPC_OPERAND_SIGNED | PPC_OPERAND_DS },
337 /* The DUIS or BHRBE fields in a XFX form instruction, 10 bits
341 { 0x3ff, 11, NULL, NULL, 0 },
343 /* The split D field in a DX form instruction. */
345 { 0xffff, PPC_OPSHIFT_INV, insert_dxd, extract_dxd,
346 PPC_OPERAND_SIGNED | PPC_OPERAND_SIGNOPT},
348 /* The split ND field in a DX form instruction.
349 This is the same as the DX field, only negated. */
351 { 0xffff, PPC_OPSHIFT_INV, insert_dxdn, extract_dxdn,
352 PPC_OPERAND_NEGATIVE | PPC_OPERAND_SIGNED | PPC_OPERAND_SIGNOPT},
354 /* The E field in a wrteei instruction. */
355 /* And the W bit in the pair singles instructions. */
356 /* And the ST field in a VX form instruction. */
360 { 0x1, 15, NULL, NULL, 0 },
362 /* The FL1 field in a POWER SC form instruction. */
364 /* The U field in an X form instruction. */
366 { 0xf, 12, NULL, NULL, 0 },
368 /* The FL2 field in a POWER SC form instruction. */
370 { 0x7, 2, NULL, NULL, 0 },
372 /* The FLM field in an XFL form instruction. */
374 { 0xff, 17, NULL, NULL, 0 },
376 /* The FRA field in an X or A form instruction. */
378 #define FRA_MASK (0x1f << 16)
379 { 0x1f, 16, NULL, NULL, PPC_OPERAND_FPR },
381 /* The FRAp field of DFP instructions. */
383 { 0x1e, 16, NULL, NULL, PPC_OPERAND_FPR },
385 /* The FRB field in an X or A form instruction. */
387 #define FRB_MASK (0x1f << 11)
388 { 0x1f, 11, NULL, NULL, PPC_OPERAND_FPR },
390 /* The FRBp field of DFP instructions. */
392 { 0x1e, 11, NULL, NULL, PPC_OPERAND_FPR },
394 /* The FRC field in an A form instruction. */
396 #define FRC_MASK (0x1f << 6)
397 { 0x1f, 6, NULL, NULL, PPC_OPERAND_FPR },
399 /* The FRS field in an X form instruction or the FRT field in a D, X
400 or A form instruction. */
403 { 0x1f, 21, NULL, NULL, PPC_OPERAND_FPR },
405 /* The FRSp field of stfdp or the FRTp field of lfdp and DFP
409 { 0x1e, 21, NULL, NULL, PPC_OPERAND_FPR },
411 /* The FXM field in an XFX instruction. */
413 { 0xff, 12, insert_fxm, extract_fxm, 0 },
415 /* Power4 version for mfcr. */
417 { 0xff, 12, insert_fxm, extract_fxm,
418 PPC_OPERAND_OPTIONAL | PPC_OPERAND_OPTIONAL_VALUE},
419 /* If the FXM4 operand is ommitted, use the sentinel value -1. */
420 { -1, -1, NULL, NULL, 0},
422 /* The IMM20 field in an LI instruction. */
423 #define IMM20 FXM4 + 2
424 { 0xfffff, PPC_OPSHIFT_INV, insert_li20, extract_li20, PPC_OPERAND_SIGNED},
426 /* The L field in a D or X form instruction. */
428 /* The R field in a HTM X form instruction. */
430 { 0x1, 21, NULL, NULL, PPC_OPERAND_OPTIONAL },
432 /* The L field in an X form instruction which must be zero. */
434 { 0x1, 21, insert_l0, extract_l0, PPC_OPERAND_OPTIONAL },
436 /* The L field in an X form instruction which must be one. */
438 { 0x1, 21, insert_l1, extract_l1, 0 },
440 /* The LEV field in a POWER SVC form instruction. */
441 #define SVC_LEV L1 + 1
442 { 0x7f, 5, NULL, NULL, 0 },
444 /* The LEV field in an SC form instruction. */
445 #define LEV SVC_LEV + 1
446 { 0x7f, 5, NULL, NULL, PPC_OPERAND_OPTIONAL },
448 /* The LI field in an I form instruction. The lower two bits are
451 { 0x3fffffc, 0, NULL, NULL, PPC_OPERAND_RELATIVE | PPC_OPERAND_SIGNED },
453 /* The LI field in an I form instruction when used as an absolute
456 { 0x3fffffc, 0, NULL, NULL, PPC_OPERAND_ABSOLUTE | PPC_OPERAND_SIGNED },
458 /* The LS or WC field in an X (sync or wait) form instruction. */
461 { 0x3, 21, insert_ls, NULL, PPC_OPERAND_OPTIONAL },
463 /* The ME field in an M form instruction. */
465 #define ME_MASK (0x1f << 1)
466 { 0x1f, 1, NULL, NULL, 0 },
468 /* The MB and ME fields in an M form instruction expressed a single
469 operand which is a bitmask indicating which bits to select. This
470 is a two operand form using PPC_OPERAND_NEXT. See the
471 description in opcode/ppc.h for what this means. */
473 { 0x1f, 6, NULL, NULL, PPC_OPERAND_OPTIONAL | PPC_OPERAND_NEXT },
474 { -1, 0, insert_mbe, extract_mbe, 0 },
476 /* The MB or ME field in an MD or MDS form instruction. The high
477 bit is wrapped to the low end. */
480 #define MB6_MASK (0x3f << 5)
481 { 0x3f, 5, insert_mb6, extract_mb6, 0 },
483 /* The NB field in an X form instruction. The value 32 is stored as
486 { 0x1f, 11, NULL, extract_nb, PPC_OPERAND_PLUS1 },
488 /* The NBI field in an lswi instruction, which has special value
489 restrictions. The value 32 is stored as 0. */
491 { 0x1f, 11, insert_nbi, extract_nb, PPC_OPERAND_PLUS1 },
493 /* The NSI field in a D form instruction. This is the same as the
494 SI field, only negated. */
496 { 0xffff, 0, insert_nsi, extract_nsi,
497 PPC_OPERAND_NEGATIVE | PPC_OPERAND_SIGNED },
499 /* The NSI field in a D form instruction when we accept a wide range
500 of positive values. */
501 #define NSISIGNOPT NSI + 1
502 { 0xffff, 0, insert_nsi, extract_nsi,
503 PPC_OPERAND_NEGATIVE | PPC_OPERAND_SIGNED | PPC_OPERAND_SIGNOPT },
505 /* The RA field in an D, DS, DQ, X, XO, M, or MDS form instruction. */
506 #define RA NSISIGNOPT + 1
507 #define RA_MASK (0x1f << 16)
508 { 0x1f, 16, NULL, NULL, PPC_OPERAND_GPR },
510 /* As above, but 0 in the RA field means zero, not r0. */
512 { 0x1f, 16, NULL, NULL, PPC_OPERAND_GPR_0 },
514 /* The RA field in the DQ form lq or an lswx instruction, which have special
515 value restrictions. */
518 { 0x1f, 16, insert_raq, NULL, PPC_OPERAND_GPR_0 },
520 /* The RA field in a D or X form instruction which is an updating
521 load, which means that the RA field may not be zero and may not
522 equal the RT field. */
524 { 0x1f, 16, insert_ral, NULL, PPC_OPERAND_GPR_0 },
526 /* The RA field in an lmw instruction, which has special value
529 { 0x1f, 16, insert_ram, NULL, PPC_OPERAND_GPR_0 },
531 /* The RA field in a D or X form instruction which is an updating
532 store or an updating floating point load, which means that the RA
533 field may not be zero. */
535 { 0x1f, 16, insert_ras, NULL, PPC_OPERAND_GPR_0 },
537 /* The RA field of the tlbwe, dccci and iccci instructions,
538 which are optional. */
539 #define RAOPT RAS + 1
540 { 0x1f, 16, NULL, NULL, PPC_OPERAND_GPR | PPC_OPERAND_OPTIONAL },
542 /* The RB field in an X, XO, M, or MDS form instruction. */
544 #define RB_MASK (0x1f << 11)
545 { 0x1f, 11, NULL, NULL, PPC_OPERAND_GPR },
547 /* The RB field in an X form instruction when it must be the same as
548 the RS field in the instruction. This is used for extended
549 mnemonics like mr. */
551 { 0x1f, 11, insert_rbs, extract_rbs, PPC_OPERAND_FAKE },
553 /* The RB field in an lswx instruction, which has special value
556 { 0x1f, 11, insert_rbx, NULL, PPC_OPERAND_GPR },
558 /* The RB field of the dccci and iccci instructions, which are optional. */
559 #define RBOPT RBX + 1
560 { 0x1f, 11, NULL, NULL, PPC_OPERAND_GPR | PPC_OPERAND_OPTIONAL },
562 /* The RC register field in an maddld, maddhd or maddhdu instruction. */
564 { 0x1f, 6, NULL, NULL, PPC_OPERAND_GPR },
566 /* The RS field in a D, DS, X, XFX, XS, M, MD or MDS form
567 instruction or the RT field in a D, DS, X, XFX or XO form
571 #define RT_MASK (0x1f << 21)
573 { 0x1f, 21, NULL, NULL, PPC_OPERAND_GPR },
575 /* The RS and RT fields of the DS form stq and DQ form lq instructions,
576 which have special value restrictions. */
579 { 0x1e, 21, NULL, NULL, PPC_OPERAND_GPR },
581 /* The RS field of the tlbwe instruction, which is optional. */
584 { 0x1f, 21, NULL, NULL, PPC_OPERAND_GPR | PPC_OPERAND_OPTIONAL },
586 /* The RX field of the SE_RR form instruction. */
588 { 0x1f, PPC_OPSHIFT_INV, insert_rx, extract_rx, PPC_OPERAND_GPR },
590 /* The ARX field of the SE_RR form instruction. */
592 { 0x1f, PPC_OPSHIFT_INV, insert_arx, extract_arx, PPC_OPERAND_GPR },
594 /* The RY field of the SE_RR form instruction. */
597 { 0x1f, PPC_OPSHIFT_INV, insert_ry, extract_ry, PPC_OPERAND_GPR },
599 /* The ARY field of the SE_RR form instruction. */
601 { 0x1f, PPC_OPSHIFT_INV, insert_ary, extract_ary, PPC_OPERAND_GPR },
603 /* The SCLSCI8 field in a D form instruction. */
604 #define SCLSCI8 ARY + 1
605 { 0xffffffff, PPC_OPSHIFT_INV, insert_sci8, extract_sci8, 0 },
607 /* The SCLSCI8N field in a D form instruction. This is the same as the
608 SCLSCI8 field, only negated. */
609 #define SCLSCI8N SCLSCI8 + 1
610 { 0xffffffff, PPC_OPSHIFT_INV, insert_sci8n, extract_sci8n,
611 PPC_OPERAND_NEGATIVE | PPC_OPERAND_SIGNED },
613 /* The SD field of the SD4 form instruction. */
614 #define SE_SD SCLSCI8N + 1
615 { 0xf, 8, NULL, NULL, PPC_OPERAND_PARENS },
617 /* The SD field of the SD4 form instruction, for halfword. */
618 #define SE_SDH SE_SD + 1
619 { 0x1e, PPC_OPSHIFT_INV, insert_sd4h, extract_sd4h, PPC_OPERAND_PARENS },
621 /* The SD field of the SD4 form instruction, for word. */
622 #define SE_SDW SE_SDH + 1
623 { 0x3c, PPC_OPSHIFT_INV, insert_sd4w, extract_sd4w, PPC_OPERAND_PARENS },
625 /* The SH field in an X or M form instruction. */
626 #define SH SE_SDW + 1
627 #define SH_MASK (0x1f << 11)
628 /* The other UIMM field in a EVX form instruction. */
630 /* The FC field in an atomic X form instruction. */
632 { 0x1f, 11, NULL, NULL, 0 },
634 /* The SI field in a HTM X form instruction. */
635 #define HTM_SI SH + 1
636 { 0x1f, 11, NULL, NULL, PPC_OPERAND_SIGNED },
638 /* The SH field in an MD form instruction. This is split. */
639 #define SH6 HTM_SI + 1
640 #define SH6_MASK ((0x1f << 11) | (1 << 1))
641 { 0x3f, PPC_OPSHIFT_INV, insert_sh6, extract_sh6, 0 },
643 /* The SH field of the tlbwe instruction, which is optional. */
645 { 0x1f, 11, NULL, NULL, PPC_OPERAND_OPTIONAL },
647 /* The SI field in a D form instruction. */
649 { 0xffff, 0, NULL, NULL, PPC_OPERAND_SIGNED },
651 /* The SI field in a D form instruction when we accept a wide range
652 of positive values. */
653 #define SISIGNOPT SI + 1
654 { 0xffff, 0, NULL, NULL, PPC_OPERAND_SIGNED | PPC_OPERAND_SIGNOPT },
656 /* The SI8 field in a D form instruction. */
657 #define SI8 SISIGNOPT + 1
658 { 0xff, 0, NULL, NULL, PPC_OPERAND_SIGNED },
660 /* The SPR field in an XFX form instruction. This is flipped--the
661 lower 5 bits are stored in the upper 5 and vice- versa. */
665 #define SPR_MASK (0x3ff << 11)
666 { 0x3ff, 11, insert_spr, extract_spr, 0 },
668 /* The BAT index number in an XFX form m[ft]ibat[lu] instruction. */
669 #define SPRBAT SPR + 1
670 #define SPRBAT_MASK (0x3 << 17)
671 { 0x3, 17, NULL, NULL, 0 },
673 /* The SPRG register number in an XFX form m[ft]sprg instruction. */
674 #define SPRG SPRBAT + 1
675 { 0x1f, 16, insert_sprg, extract_sprg, 0 },
677 /* The SR field in an X form instruction. */
679 /* The 4-bit UIMM field in a VX form instruction. */
681 { 0xf, 16, NULL, NULL, 0 },
683 /* The STRM field in an X AltiVec form instruction. */
685 /* The T field in a tlbilx form instruction. */
687 { 0x3, 21, NULL, NULL, 0 },
689 /* The ESYNC field in an X (sync) form instruction. */
690 #define ESYNC STRM + 1
691 { 0xf, 16, insert_esync, NULL, PPC_OPERAND_OPTIONAL },
693 /* The SV field in a POWER SC form instruction. */
695 { 0x3fff, 2, NULL, NULL, 0 },
697 /* The TBR field in an XFX form instruction. This is like the SPR
698 field, but it is optional. */
700 { 0x3ff, 11, insert_tbr, extract_tbr,
701 PPC_OPERAND_OPTIONAL | PPC_OPERAND_OPTIONAL_VALUE},
702 /* If the TBR operand is ommitted, use the value 268. */
703 { -1, 268, NULL, NULL, 0},
705 /* The TO field in a D or X form instruction. */
708 #define TO_MASK (0x1f << 21)
709 { 0x1f, 21, NULL, NULL, 0 },
711 /* The UI field in a D form instruction. */
713 { 0xffff, 0, NULL, NULL, 0 },
715 #define UISIGNOPT UI + 1
716 { 0xffff, 0, NULL, NULL, PPC_OPERAND_SIGNOPT },
718 /* The IMM field in an SE_IM5 instruction. */
719 #define UI5 UISIGNOPT + 1
720 { 0x1f, 4, NULL, NULL, 0 },
722 /* The OIMM field in an SE_OIM5 instruction. */
723 #define OIMM5 UI5 + 1
724 { 0x1f, PPC_OPSHIFT_INV, insert_oimm, extract_oimm, PPC_OPERAND_PLUS1 },
726 /* The UI7 field in an SE_LI instruction. */
727 #define UI7 OIMM5 + 1
728 { 0x7f, 4, NULL, NULL, 0 },
730 /* The VA field in a VA, VX or VXR form instruction. */
732 { 0x1f, 16, NULL, NULL, PPC_OPERAND_VR },
734 /* The VB field in a VA, VX or VXR form instruction. */
736 { 0x1f, 11, NULL, NULL, PPC_OPERAND_VR },
738 /* The VC field in a VA form instruction. */
740 { 0x1f, 6, NULL, NULL, PPC_OPERAND_VR },
742 /* The VD or VS field in a VA, VX, VXR or X form instruction. */
745 { 0x1f, 21, NULL, NULL, PPC_OPERAND_VR },
747 /* The SIMM field in a VX form instruction, and TE in Z form. */
750 { 0x1f, 16, NULL, NULL, PPC_OPERAND_SIGNED},
752 /* The UIMM field in a VX form instruction. */
753 #define UIMM SIMM + 1
755 { 0x1f, 16, NULL, NULL, 0 },
757 /* The 3-bit UIMM field in a VX form instruction. */
758 #define UIMM3 UIMM + 1
759 { 0x7, 16, NULL, NULL, 0 },
761 /* The 6-bit UIM field in a X form instruction. */
762 #define UIM6 UIMM3 + 1
763 { 0x3f, 16, NULL, NULL, 0 },
765 /* The SIX field in a VX form instruction. */
767 { 0xf, 11, NULL, NULL, 0 },
769 /* The PS field in a VX form instruction. */
771 { 0x1, 9, NULL, NULL, 0 },
773 /* The SHB field in a VA form instruction. */
775 { 0xf, 6, NULL, NULL, 0 },
777 /* The other UIMM field in a half word EVX form instruction. */
778 #define EVUIMM_2 SHB + 1
779 { 0x3e, 10, NULL, NULL, PPC_OPERAND_PARENS },
781 /* The other UIMM field in a word EVX form instruction. */
782 #define EVUIMM_4 EVUIMM_2 + 1
783 { 0x7c, 9, NULL, NULL, PPC_OPERAND_PARENS },
785 /* The other UIMM field in a double EVX form instruction. */
786 #define EVUIMM_8 EVUIMM_4 + 1
787 { 0xf8, 8, NULL, NULL, PPC_OPERAND_PARENS },
790 #define WS EVUIMM_8 + 1
791 { 0x7, 11, NULL, NULL, 0 },
793 /* PowerPC paired singles extensions. */
794 /* W bit in the pair singles instructions for x type instructions. */
796 /* The BO16 field in a BD8 form instruction. */
798 { 0x1, 10, 0, 0, 0 },
800 /* IDX bits for quantization in the pair singles instructions. */
802 { 0x7, 12, 0, 0, 0 },
804 /* IDX bits for quantization in the pair singles x-type instructions. */
808 /* Smaller D field for quantization in the pair singles instructions. */
810 { 0xfff, 0, 0, 0, PPC_OPERAND_PARENS | PPC_OPERAND_SIGNED },
812 /* The L field in an mtmsrd or A form instruction or R or W in an X form. */
816 { 0x1, 16, NULL, NULL, PPC_OPERAND_OPTIONAL },
818 /* The RMC or CY field in a Z23 form instruction. */
821 { 0x3, 9, NULL, NULL, 0 },
824 { 0x1, 16, NULL, NULL, 0 },
827 { 0x3, 18, NULL, NULL, PPC_OPERAND_OPTIONAL },
830 { 0x1, 17, NULL, NULL, PPC_OPERAND_OPTIONAL },
833 { 0x3, 19, NULL, NULL, 0 },
836 { 0x1, 20, NULL, NULL, 0 },
838 /* The S field in a XL form instruction. */
840 { 0x1, 11, NULL, NULL, PPC_OPERAND_OPTIONAL | PPC_OPERAND_OPTIONAL_VALUE},
841 /* If the SXL operand is ommitted, use the value 1. */
842 { -1, 1, NULL, NULL, 0},
844 /* SH field starting at bit position 16. */
846 /* The DCM and DGM fields in a Z form instruction. */
849 { 0x3f, 10, NULL, NULL, 0 },
851 /* The EH field in larx instruction. */
853 { 0x1, 0, NULL, NULL, PPC_OPERAND_OPTIONAL },
855 /* The L field in an mtfsf or XFL form instruction. */
856 /* The A field in a HTM X form instruction. */
859 { 0x1, 25, NULL, NULL, PPC_OPERAND_OPTIONAL},
861 /* Xilinx APU related masks and macros */
862 #define FCRT XFL_L + 1
863 #define FCRT_MASK (0x1f << 21)
864 { 0x1f, 21, 0, 0, PPC_OPERAND_FCR },
866 /* Xilinx FSL related masks and macros */
868 #define FSL_MASK (0x1f << 11)
869 { 0x1f, 11, 0, 0, PPC_OPERAND_FSL },
871 /* Xilinx UDI related masks and macros */
873 { 0x1f, 21, 0, 0, PPC_OPERAND_UDI },
876 { 0x1f, 16, 0, 0, PPC_OPERAND_UDI },
879 { 0x1f, 11, 0, 0, PPC_OPERAND_UDI },
882 { 0x1f, 6, 0, 0, PPC_OPERAND_UDI },
884 /* The VLESIMM field in a D form instruction. */
885 #define VLESIMM URC + 1
886 { 0xffff, PPC_OPSHIFT_INV, insert_vlesi, extract_vlesi,
887 PPC_OPERAND_SIGNED | PPC_OPERAND_SIGNOPT },
889 /* The VLENSIMM field in a D form instruction. */
890 #define VLENSIMM VLESIMM + 1
891 { 0xffff, PPC_OPSHIFT_INV, insert_vlensi, extract_vlensi,
892 PPC_OPERAND_NEGATIVE | PPC_OPERAND_SIGNED | PPC_OPERAND_SIGNOPT },
894 /* The VLEUIMM field in a D form instruction. */
895 #define VLEUIMM VLENSIMM + 1
896 { 0xffff, PPC_OPSHIFT_INV, insert_vleui, extract_vleui, 0 },
898 /* The VLEUIMML field in a D form instruction. */
899 #define VLEUIMML VLEUIMM + 1
900 { 0xffff, PPC_OPSHIFT_INV, insert_vleil, extract_vleil, 0 },
902 /* The XT and XS fields in an XX1 or XX3 form instruction. This is split. */
903 #define XS6 VLEUIMML + 1
905 { 0x3f, PPC_OPSHIFT_INV, insert_xt6, extract_xt6, PPC_OPERAND_VSR },
907 /* The XT and XS fields in an DQ form VSX instruction. This is split. */
910 { 0x3f, PPC_OPSHIFT_INV, insert_xtq6, extract_xtq6, PPC_OPERAND_VSR },
912 /* The XA field in an XX3 form instruction. This is split. */
914 { 0x3f, PPC_OPSHIFT_INV, insert_xa6, extract_xa6, PPC_OPERAND_VSR },
916 /* The XB field in an XX2 or XX3 form instruction. This is split. */
918 { 0x3f, PPC_OPSHIFT_INV, insert_xb6, extract_xb6, PPC_OPERAND_VSR },
920 /* The XB field in an XX3 form instruction when it must be the same as
921 the XA field in the instruction. This is used in extended mnemonics
922 like xvmovdp. This is split. */
924 { 0x3f, PPC_OPSHIFT_INV, insert_xb6s, extract_xb6s, PPC_OPERAND_FAKE },
926 /* The XC field in an XX4 form instruction. This is split. */
928 { 0x3f, PPC_OPSHIFT_INV, insert_xc6, extract_xc6, PPC_OPERAND_VSR },
930 /* The DM or SHW field in an XX3 form instruction. */
933 { 0x3, 8, NULL, NULL, 0 },
935 /* The DM field in an extended mnemonic XX3 form instruction. */
937 { 0x3, 8, insert_dm, extract_dm, 0 },
939 /* The UIM field in an XX2 form instruction. */
941 /* The 2-bit UIMM field in a VX form instruction. */
943 /* The 2-bit L field in a darn instruction. */
945 { 0x3, 16, NULL, NULL, 0 },
947 #define ERAT_T UIM + 1
948 { 0x7, 21, NULL, NULL, 0 },
950 #define IH ERAT_T + 1
951 { 0x7, 21, NULL, NULL, PPC_OPERAND_OPTIONAL },
953 /* The 8-bit IMM8 field in a XX1 form instruction. */
955 { 0xff, 11, NULL, NULL, PPC_OPERAND_SIGNOPT },
958 const unsigned int num_powerpc_operands = (sizeof (powerpc_operands)
959 / sizeof (powerpc_operands[0]));
961 /* The functions used to insert and extract complicated operands. */
963 /* The ARX, ARY, RX and RY operands are alternate encodings of GPRs. */
966 insert_arx (unsigned long insn,
968 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
969 const char **errmsg ATTRIBUTE_UNUSED)
971 if (value >= 8 && value < 24)
972 return insn | ((value - 8) & 0xf);
975 *errmsg = _("invalid register");
981 extract_arx (unsigned long insn,
982 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
983 int *invalid ATTRIBUTE_UNUSED)
985 return (insn & 0xf) + 8;
989 insert_ary (unsigned long insn,
991 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
992 const char **errmsg ATTRIBUTE_UNUSED)
994 if (value >= 8 && value < 24)
995 return insn | (((value - 8) & 0xf) << 4);
998 *errmsg = _("invalid register");
1004 extract_ary (unsigned long insn,
1005 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
1006 int *invalid ATTRIBUTE_UNUSED)
1008 return ((insn >> 4) & 0xf) + 8;
1011 static unsigned long
1012 insert_rx (unsigned long insn,
1014 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
1015 const char **errmsg)
1017 if (value >= 0 && value < 8)
1018 return insn | value;
1019 else if (value >= 24 && value <= 31)
1020 return insn | (value - 16);
1023 *errmsg = _("invalid register");
1029 extract_rx (unsigned long insn,
1030 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
1031 int *invalid ATTRIBUTE_UNUSED)
1033 int value = insn & 0xf;
1034 if (value >= 0 && value < 8)
1040 static unsigned long
1041 insert_ry (unsigned long insn,
1043 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
1044 const char **errmsg)
1046 if (value >= 0 && value < 8)
1047 return insn | (value << 4);
1048 else if (value >= 24 && value <= 31)
1049 return insn | ((value - 16) << 4);
1052 *errmsg = _("invalid register");
1058 extract_ry (unsigned long insn,
1059 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
1060 int *invalid ATTRIBUTE_UNUSED)
1062 int value = (insn >> 4) & 0xf;
1063 if (value >= 0 && value < 8)
1069 /* The BA field in an XL form instruction when it must be the same as
1070 the BT field in the same instruction. This operand is marked FAKE.
1071 The insertion function just copies the BT field into the BA field,
1072 and the extraction function just checks that the fields are the
1075 static unsigned long
1076 insert_bat (unsigned long insn,
1077 long value ATTRIBUTE_UNUSED,
1078 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
1079 const char **errmsg ATTRIBUTE_UNUSED)
1081 return insn | (((insn >> 21) & 0x1f) << 16);
1085 extract_bat (unsigned long insn,
1086 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
1089 if (((insn >> 21) & 0x1f) != ((insn >> 16) & 0x1f))
1094 /* The BB field in an XL form instruction when it must be the same as
1095 the BA field in the same instruction. This operand is marked FAKE.
1096 The insertion function just copies the BA field into the BB field,
1097 and the extraction function just checks that the fields are the
1100 static unsigned long
1101 insert_bba (unsigned long insn,
1102 long value ATTRIBUTE_UNUSED,
1103 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
1104 const char **errmsg ATTRIBUTE_UNUSED)
1106 return insn | (((insn >> 16) & 0x1f) << 11);
1110 extract_bba (unsigned long insn,
1111 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
1114 if (((insn >> 16) & 0x1f) != ((insn >> 11) & 0x1f))
1119 /* The BD field in a B form instruction when the - modifier is used.
1120 This modifier means that the branch is not expected to be taken.
1121 For chips built to versions of the architecture prior to version 2
1122 (ie. not Power4 compatible), we set the y bit of the BO field to 1
1123 if the offset is negative. When extracting, we require that the y
1124 bit be 1 and that the offset be positive, since if the y bit is 0
1125 we just want to print the normal form of the instruction.
1126 Power4 compatible targets use two bits, "a", and "t", instead of
1127 the "y" bit. "at" == 00 => no hint, "at" == 01 => unpredictable,
1128 "at" == 10 => not taken, "at" == 11 => taken. The "t" bit is 00001
1129 in BO field, the "a" bit is 00010 for branch on CR(BI) and 01000
1130 for branch on CTR. We only handle the taken/not-taken hint here.
1131 Note that we don't relax the conditions tested here when
1132 disassembling with -Many because insns using extract_bdm and
1133 extract_bdp always occur in pairs. One or the other will always
1136 #define ISA_V2 (PPC_OPCODE_POWER4 | PPC_OPCODE_E500MC | PPC_OPCODE_TITAN)
1138 static unsigned long
1139 insert_bdm (unsigned long insn,
1142 const char **errmsg ATTRIBUTE_UNUSED)
1144 if ((dialect & ISA_V2) == 0)
1146 if ((value & 0x8000) != 0)
1151 if ((insn & (0x14 << 21)) == (0x04 << 21))
1153 else if ((insn & (0x14 << 21)) == (0x10 << 21))
1156 return insn | (value & 0xfffc);
1160 extract_bdm (unsigned long insn,
1164 if ((dialect & ISA_V2) == 0)
1166 if (((insn & (1 << 21)) == 0) != ((insn & (1 << 15)) == 0))
1171 if ((insn & (0x17 << 21)) != (0x06 << 21)
1172 && (insn & (0x1d << 21)) != (0x18 << 21))
1176 return ((insn & 0xfffc) ^ 0x8000) - 0x8000;
1179 /* The BD field in a B form instruction when the + modifier is used.
1180 This is like BDM, above, except that the branch is expected to be
1183 static unsigned long
1184 insert_bdp (unsigned long insn,
1187 const char **errmsg ATTRIBUTE_UNUSED)
1189 if ((dialect & ISA_V2) == 0)
1191 if ((value & 0x8000) == 0)
1196 if ((insn & (0x14 << 21)) == (0x04 << 21))
1198 else if ((insn & (0x14 << 21)) == (0x10 << 21))
1201 return insn | (value & 0xfffc);
1205 extract_bdp (unsigned long insn,
1209 if ((dialect & ISA_V2) == 0)
1211 if (((insn & (1 << 21)) == 0) == ((insn & (1 << 15)) == 0))
1216 if ((insn & (0x17 << 21)) != (0x07 << 21)
1217 && (insn & (0x1d << 21)) != (0x19 << 21))
1221 return ((insn & 0xfffc) ^ 0x8000) - 0x8000;
1225 valid_bo_pre_v2 (long value)
1227 /* Certain encodings have bits that are required to be zero.
1228 These are (z must be zero, y may be anything):
1239 if ((value & 0x14) == 0)
1241 else if ((value & 0x14) == 0x4)
1242 return (value & 0x2) == 0;
1243 else if ((value & 0x14) == 0x10)
1244 return (value & 0x8) == 0;
1246 return value == 0x14;
1250 valid_bo_post_v2 (long value)
1252 /* Certain encodings have bits that are required to be zero.
1253 These are (z must be zero, a & t may be anything):
1264 if ((value & 0x14) == 0)
1265 return (value & 0x1) == 0;
1266 else if ((value & 0x14) == 0x14)
1267 return value == 0x14;
1272 /* Check for legal values of a BO field. */
1275 valid_bo (long value, ppc_cpu_t dialect, int extract)
1277 int valid_y = valid_bo_pre_v2 (value);
1278 int valid_at = valid_bo_post_v2 (value);
1280 /* When disassembling with -Many, accept either encoding on the
1281 second pass through opcodes. */
1282 if (extract && dialect == ~(ppc_cpu_t) PPC_OPCODE_ANY)
1283 return valid_y || valid_at;
1284 if ((dialect & ISA_V2) == 0)
1290 /* The BO field in a B form instruction. Warn about attempts to set
1291 the field to an illegal value. */
1293 static unsigned long
1294 insert_bo (unsigned long insn,
1297 const char **errmsg)
1299 if (!valid_bo (value, dialect, 0))
1300 *errmsg = _("invalid conditional option");
1301 else if (PPC_OP (insn) == 19 && (insn & 0x400) && ! (value & 4))
1302 *errmsg = _("invalid counter access");
1303 return insn | ((value & 0x1f) << 21);
1307 extract_bo (unsigned long insn,
1313 value = (insn >> 21) & 0x1f;
1314 if (!valid_bo (value, dialect, 1))
1319 /* The BO field in a B form instruction when the + or - modifier is
1320 used. This is like the BO field, but it must be even. When
1321 extracting it, we force it to be even. */
1323 static unsigned long
1324 insert_boe (unsigned long insn,
1327 const char **errmsg)
1329 if (!valid_bo (value, dialect, 0))
1330 *errmsg = _("invalid conditional option");
1331 else if (PPC_OP (insn) == 19 && (insn & 0x400) && ! (value & 4))
1332 *errmsg = _("invalid counter access");
1333 else if ((value & 1) != 0)
1334 *errmsg = _("attempt to set y bit when using + or - modifier");
1336 return insn | ((value & 0x1f) << 21);
1340 extract_boe (unsigned long insn,
1346 value = (insn >> 21) & 0x1f;
1347 if (!valid_bo (value, dialect, 1))
1349 return value & 0x1e;
1352 /* The DCMX field in a X form instruction when the field is split
1353 into separate DC, DM and DX fields. */
1355 static unsigned long
1356 insert_dcmxs (unsigned long insn,
1358 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
1359 const char **errmsg ATTRIBUTE_UNUSED)
1361 return insn | ((value & 0x1f) << 16) | ((value & 0x20) >> 3) | (value & 0x40);
1365 extract_dcmxs (unsigned long insn,
1366 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
1367 int *invalid ATTRIBUTE_UNUSED)
1369 return (insn & 0x40) | ((insn << 3) & 0x20) | ((insn >> 16) & 0x1f);
1372 /* The D field in a DX form instruction when the field is split
1373 into separate D0, D1 and D2 fields. */
1375 static unsigned long
1376 insert_dxd (unsigned long insn,
1378 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
1379 const char **errmsg ATTRIBUTE_UNUSED)
1381 return insn | (value & 0xffc1) | ((value & 0x3e) << 15);
1385 extract_dxd (unsigned long insn,
1386 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
1387 int *invalid ATTRIBUTE_UNUSED)
1389 unsigned long dxd = (insn & 0xffc1) | ((insn >> 15) & 0x3e);
1390 return (dxd ^ 0x8000) - 0x8000;
1393 static unsigned long
1394 insert_dxdn (unsigned long insn,
1396 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
1397 const char **errmsg ATTRIBUTE_UNUSED)
1399 return insert_dxd (insn, -value, dialect, errmsg);
1403 extract_dxdn (unsigned long insn,
1404 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
1405 int *invalid ATTRIBUTE_UNUSED)
1407 return -extract_dxd (insn, dialect, invalid);
1410 /* FXM mask in mfcr and mtcrf instructions. */
1412 static unsigned long
1413 insert_fxm (unsigned long insn,
1416 const char **errmsg)
1418 /* If we're handling the mfocrf and mtocrf insns ensure that exactly
1419 one bit of the mask field is set. */
1420 if ((insn & (1 << 20)) != 0)
1422 if (value == 0 || (value & -value) != value)
1424 *errmsg = _("invalid mask field");
1429 /* If only one bit of the FXM field is set, we can use the new form
1430 of the instruction, which is faster. Unlike the Power4 branch hint
1431 encoding, this is not backward compatible. Do not generate the
1432 new form unless -mpower4 has been given, or -many and the two
1433 operand form of mfcr was used. */
1435 && (value & -value) == value
1436 && ((dialect & PPC_OPCODE_POWER4) != 0
1437 || ((dialect & PPC_OPCODE_ANY) != 0
1438 && (insn & (0x3ff << 1)) == 19 << 1)))
1441 /* Any other value on mfcr is an error. */
1442 else if ((insn & (0x3ff << 1)) == 19 << 1)
1444 /* A value of -1 means we used the one operand form of
1445 mfcr which is valid. */
1447 *errmsg = _("invalid mfcr mask");
1451 return insn | ((value & 0xff) << 12);
1455 extract_fxm (unsigned long insn,
1456 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
1459 long mask = (insn >> 12) & 0xff;
1461 /* Is this a Power4 insn? */
1462 if ((insn & (1 << 20)) != 0)
1464 /* Exactly one bit of MASK should be set. */
1465 if (mask == 0 || (mask & -mask) != mask)
1469 /* Check that non-power4 form of mfcr has a zero MASK. */
1470 else if ((insn & (0x3ff << 1)) == 19 << 1)
1481 /* The L field in an X form instruction which must have the value zero. */
1483 static unsigned long
1484 insert_l0 (unsigned long insn,
1486 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
1487 const char **errmsg)
1490 *errmsg = _("invalid operand constant");
1491 return insn & ~(0x1 << 21);
1495 extract_l0 (unsigned long insn,
1496 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
1501 value = (insn >> 21) & 0x1;
1507 /* The L field in an X form instruction which must have the value one. */
1509 static unsigned long
1510 insert_l1 (unsigned long insn,
1512 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
1513 const char **errmsg)
1516 *errmsg = _("invalid operand constant");
1517 return insn | (0x1 << 21);
1521 extract_l1 (unsigned long insn,
1522 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
1527 value = (insn >> 21) & 0x1;
1533 static unsigned long
1534 insert_li20 (unsigned long insn,
1536 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
1537 const char **errmsg ATTRIBUTE_UNUSED)
1539 return insn | ((value & 0xf0000) >> 5) | ((value & 0x0f800) << 5) | (value & 0x7ff);
1543 extract_li20 (unsigned long insn,
1544 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
1545 int *invalid ATTRIBUTE_UNUSED)
1547 long ext = ((insn & 0x4000) == 0x4000) ? 0xfff00000 : 0x00000000;
1550 | (((insn >> 11) & 0xf) << 16)
1551 | (((insn >> 17) & 0xf) << 12)
1552 | (((insn >> 16) & 0x1) << 11)
1556 /* The 2-bit L field in a SYNC or WC field in a WAIT instruction.
1557 For SYNC, some L values are reserved:
1558 * Value 3 is reserved on newer server cpus.
1559 * Values 2 and 3 are reserved on all other cpus. */
1561 static unsigned long
1562 insert_ls (unsigned long insn,
1565 const char **errmsg)
1567 /* For SYNC, some L values are illegal. */
1568 if (((insn >> 1) & 0x3ff) == 598)
1570 long max_lvalue = (dialect & PPC_OPCODE_POWER4) ? 2 : 1;
1571 if (value > max_lvalue)
1573 *errmsg = _("illegal L operand value");
1578 return insn | ((value & 0x3) << 21);
1581 /* The 4-bit E field in a sync instruction that accepts 2 operands.
1582 If ESYNC is non-zero, then the L field must be either 0 or 1 and
1583 the complement of ESYNC-bit2. */
1585 static unsigned long
1586 insert_esync (unsigned long insn,
1589 const char **errmsg)
1591 unsigned long ls = (insn >> 21) & 0x03;
1595 if (((dialect & PPC_OPCODE_E6500) != 0 && ls > 1)
1596 || ((dialect & PPC_OPCODE_POWER9) != 0 && ls > 2))
1597 *errmsg = _("illegal L operand value");
1602 || (((value >> 1) & 0x1) ^ ls) == 0)
1603 *errmsg = _("incompatible L operand value");
1605 return insn | ((value & 0xf) << 16);
1608 /* The MB and ME fields in an M form instruction expressed as a single
1609 operand which is itself a bitmask. The extraction function always
1610 marks it as invalid, since we never want to recognize an
1611 instruction which uses a field of this type. */
1613 static unsigned long
1614 insert_mbe (unsigned long insn,
1616 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
1617 const char **errmsg)
1619 unsigned long uval, mask;
1620 int mb, me, mx, count, last;
1626 *errmsg = _("illegal bitmask");
1632 if ((uval & 1) != 0)
1638 /* mb: location of last 0->1 transition */
1639 /* me: location of last 1->0 transition */
1640 /* count: # transitions */
1642 for (mx = 0, mask = 1L << 31; mx < 32; ++mx, mask >>= 1)
1644 if ((uval & mask) && !last)
1650 else if (!(uval & mask) && last)
1660 if (count != 2 && (count != 0 || ! last))
1661 *errmsg = _("illegal bitmask");
1663 return insn | (mb << 6) | ((me - 1) << 1);
1667 extract_mbe (unsigned long insn,
1668 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
1677 mb = (insn >> 6) & 0x1f;
1678 me = (insn >> 1) & 0x1f;
1682 for (i = mb; i <= me; i++)
1683 ret |= 1L << (31 - i);
1685 else if (mb == me + 1)
1687 else /* (mb > me + 1) */
1690 for (i = me + 1; i < mb; i++)
1691 ret &= ~(1L << (31 - i));
1696 /* The MB or ME field in an MD or MDS form instruction. The high bit
1697 is wrapped to the low end. */
1699 static unsigned long
1700 insert_mb6 (unsigned long insn,
1702 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
1703 const char **errmsg ATTRIBUTE_UNUSED)
1705 return insn | ((value & 0x1f) << 6) | (value & 0x20);
1709 extract_mb6 (unsigned long insn,
1710 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
1711 int *invalid ATTRIBUTE_UNUSED)
1713 return ((insn >> 6) & 0x1f) | (insn & 0x20);
1716 /* The NB field in an X form instruction. The value 32 is stored as
1720 extract_nb (unsigned long insn,
1721 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
1722 int *invalid ATTRIBUTE_UNUSED)
1726 ret = (insn >> 11) & 0x1f;
1732 /* The NB field in an lswi instruction, which has special value
1733 restrictions. The value 32 is stored as 0. */
1735 static unsigned long
1736 insert_nbi (unsigned long insn,
1738 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
1739 const char **errmsg ATTRIBUTE_UNUSED)
1741 long rtvalue = (insn & RT_MASK) >> 21;
1742 long ravalue = (insn & RA_MASK) >> 16;
1746 if (rtvalue + (value + 3) / 4 > (rtvalue > ravalue ? ravalue + 32
1748 *errmsg = _("address register in load range");
1749 return insn | ((value & 0x1f) << 11);
1752 /* The NSI field in a D form instruction. This is the same as the SI
1753 field, only negated. The extraction function always marks it as
1754 invalid, since we never want to recognize an instruction which uses
1755 a field of this type. */
1757 static unsigned long
1758 insert_nsi (unsigned long insn,
1760 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
1761 const char **errmsg ATTRIBUTE_UNUSED)
1763 return insn | (-value & 0xffff);
1767 extract_nsi (unsigned long insn,
1768 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
1772 return -(((insn & 0xffff) ^ 0x8000) - 0x8000);
1775 /* The RA field in a D or X form instruction which is an updating
1776 load, which means that the RA field may not be zero and may not
1777 equal the RT field. */
1779 static unsigned long
1780 insert_ral (unsigned long insn,
1782 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
1783 const char **errmsg)
1786 || (unsigned long) value == ((insn >> 21) & 0x1f))
1787 *errmsg = "invalid register operand when updating";
1788 return insn | ((value & 0x1f) << 16);
1791 /* The RA field in an lmw instruction, which has special value
1794 static unsigned long
1795 insert_ram (unsigned long insn,
1797 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
1798 const char **errmsg)
1800 if ((unsigned long) value >= ((insn >> 21) & 0x1f))
1801 *errmsg = _("index register in load range");
1802 return insn | ((value & 0x1f) << 16);
1805 /* The RA field in the DQ form lq or an lswx instruction, which have special
1806 value restrictions. */
1808 static unsigned long
1809 insert_raq (unsigned long insn,
1811 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
1812 const char **errmsg)
1814 long rtvalue = (insn & RT_MASK) >> 21;
1816 if (value == rtvalue)
1817 *errmsg = _("source and target register operands must be different");
1818 return insn | ((value & 0x1f) << 16);
1821 /* The RA field in a D or X form instruction which is an updating
1822 store or an updating floating point load, which means that the RA
1823 field may not be zero. */
1825 static unsigned long
1826 insert_ras (unsigned long insn,
1828 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
1829 const char **errmsg)
1832 *errmsg = _("invalid register operand when updating");
1833 return insn | ((value & 0x1f) << 16);
1836 /* The RB field in an X form instruction when it must be the same as
1837 the RS field in the instruction. This is used for extended
1838 mnemonics like mr. This operand is marked FAKE. The insertion
1839 function just copies the BT field into the BA field, and the
1840 extraction function just checks that the fields are the same. */
1842 static unsigned long
1843 insert_rbs (unsigned long insn,
1844 long value ATTRIBUTE_UNUSED,
1845 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
1846 const char **errmsg ATTRIBUTE_UNUSED)
1848 return insn | (((insn >> 21) & 0x1f) << 11);
1852 extract_rbs (unsigned long insn,
1853 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
1856 if (((insn >> 21) & 0x1f) != ((insn >> 11) & 0x1f))
1861 /* The RB field in an lswx instruction, which has special value
1864 static unsigned long
1865 insert_rbx (unsigned long insn,
1867 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
1868 const char **errmsg)
1870 long rtvalue = (insn & RT_MASK) >> 21;
1872 if (value == rtvalue)
1873 *errmsg = _("source and target register operands must be different");
1874 return insn | ((value & 0x1f) << 11);
1877 /* The SCI8 field is made up of SCL and {U,N}I8 fields. */
1878 static unsigned long
1879 insert_sci8 (unsigned long insn,
1881 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
1882 const char **errmsg)
1884 unsigned int fill_scale = 0;
1885 unsigned long ui8 = value;
1887 if ((ui8 & 0xffffff00) == 0)
1889 else if ((ui8 & 0xffffff00) == 0xffffff00)
1891 else if ((ui8 & 0xffff00ff) == 0)
1893 fill_scale = 1 << 8;
1896 else if ((ui8 & 0xffff00ff) == 0xffff00ff)
1898 fill_scale = 0x400 | (1 << 8);
1901 else if ((ui8 & 0xff00ffff) == 0)
1903 fill_scale = 2 << 8;
1906 else if ((ui8 & 0xff00ffff) == 0xff00ffff)
1908 fill_scale = 0x400 | (2 << 8);
1911 else if ((ui8 & 0x00ffffff) == 0)
1913 fill_scale = 3 << 8;
1916 else if ((ui8 & 0x00ffffff) == 0x00ffffff)
1918 fill_scale = 0x400 | (3 << 8);
1923 *errmsg = _("illegal immediate value");
1927 return insn | fill_scale | (ui8 & 0xff);
1931 extract_sci8 (unsigned long insn,
1932 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
1933 int *invalid ATTRIBUTE_UNUSED)
1935 int fill = insn & 0x400;
1936 int scale_factor = (insn & 0x300) >> 5;
1937 long value = (insn & 0xff) << scale_factor;
1940 value |= ~((long) 0xff << scale_factor);
1944 static unsigned long
1945 insert_sci8n (unsigned long insn,
1948 const char **errmsg)
1950 return insert_sci8 (insn, -value, dialect, errmsg);
1954 extract_sci8n (unsigned long insn,
1958 return -extract_sci8 (insn, dialect, invalid);
1961 static unsigned long
1962 insert_sd4h (unsigned long insn,
1964 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
1965 const char **errmsg ATTRIBUTE_UNUSED)
1967 return insn | ((value & 0x1e) << 7);
1971 extract_sd4h (unsigned long insn,
1972 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
1973 int *invalid ATTRIBUTE_UNUSED)
1975 return ((insn >> 8) & 0xf) << 1;
1978 static unsigned long
1979 insert_sd4w (unsigned long insn,
1981 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
1982 const char **errmsg ATTRIBUTE_UNUSED)
1984 return insn | ((value & 0x3c) << 6);
1988 extract_sd4w (unsigned long insn,
1989 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
1990 int *invalid ATTRIBUTE_UNUSED)
1992 return ((insn >> 8) & 0xf) << 2;
1995 static unsigned long
1996 insert_oimm (unsigned long insn,
1998 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
1999 const char **errmsg ATTRIBUTE_UNUSED)
2001 return insn | (((value - 1) & 0x1f) << 4);
2005 extract_oimm (unsigned long insn,
2006 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
2007 int *invalid ATTRIBUTE_UNUSED)
2009 return ((insn >> 4) & 0x1f) + 1;
2012 /* The SH field in an MD form instruction. This is split. */
2014 static unsigned long
2015 insert_sh6 (unsigned long insn,
2017 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
2018 const char **errmsg ATTRIBUTE_UNUSED)
2020 return insn | ((value & 0x1f) << 11) | ((value & 0x20) >> 4);
2024 extract_sh6 (unsigned long insn,
2025 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
2026 int *invalid ATTRIBUTE_UNUSED)
2028 return ((insn >> 11) & 0x1f) | ((insn << 4) & 0x20);
2031 /* The SPR field in an XFX form instruction. This is flipped--the
2032 lower 5 bits are stored in the upper 5 and vice- versa. */
2034 static unsigned long
2035 insert_spr (unsigned long insn,
2037 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
2038 const char **errmsg ATTRIBUTE_UNUSED)
2040 return insn | ((value & 0x1f) << 16) | ((value & 0x3e0) << 6);
2044 extract_spr (unsigned long insn,
2045 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
2046 int *invalid ATTRIBUTE_UNUSED)
2048 return ((insn >> 16) & 0x1f) | ((insn >> 6) & 0x3e0);
2051 /* Some dialects have 8 SPRG registers instead of the standard 4. */
2052 #define ALLOW8_SPRG (PPC_OPCODE_BOOKE | PPC_OPCODE_405)
2054 static unsigned long
2055 insert_sprg (unsigned long insn,
2058 const char **errmsg)
2061 || (value > 3 && (dialect & ALLOW8_SPRG) == 0))
2062 *errmsg = _("invalid sprg number");
2064 /* If this is mfsprg4..7 then use spr 260..263 which can be read in
2065 user mode. Anything else must use spr 272..279. */
2066 if (value <= 3 || (insn & 0x100) != 0)
2069 return insn | ((value & 0x17) << 16);
2073 extract_sprg (unsigned long insn,
2077 unsigned long val = (insn >> 16) & 0x1f;
2079 /* mfsprg can use 260..263 and 272..279. mtsprg only uses spr 272..279
2080 If not BOOKE, 405 or VLE, then both use only 272..275. */
2081 if ((val - 0x10 > 3 && (dialect & ALLOW8_SPRG) == 0)
2082 || (val - 0x10 > 7 && (insn & 0x100) != 0)
2089 /* The TBR field in an XFX instruction. This is just like SPR, but it
2092 static unsigned long
2093 insert_tbr (unsigned long insn,
2095 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
2096 const char **errmsg)
2098 if (value != 268 && value != 269)
2099 *errmsg = _("invalid tbr number");
2100 return insn | ((value & 0x1f) << 16) | ((value & 0x3e0) << 6);
2104 extract_tbr (unsigned long insn,
2105 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
2110 ret = ((insn >> 16) & 0x1f) | ((insn >> 6) & 0x3e0);
2111 if (ret != 268 && ret != 269)
2116 /* The XT and XS fields in an XX1 or XX3 form instruction. This is split. */
2118 static unsigned long
2119 insert_xt6 (unsigned long insn,
2121 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
2122 const char **errmsg ATTRIBUTE_UNUSED)
2124 return insn | ((value & 0x1f) << 21) | ((value & 0x20) >> 5);
2128 extract_xt6 (unsigned long insn,
2129 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
2130 int *invalid ATTRIBUTE_UNUSED)
2132 return ((insn << 5) & 0x20) | ((insn >> 21) & 0x1f);
2135 /* The XT and XS fields in an DQ form VSX instruction. This is split. */
2136 static unsigned long
2137 insert_xtq6 (unsigned long insn,
2139 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
2140 const char **errmsg ATTRIBUTE_UNUSED)
2142 return insn | ((value & 0x1f) << 21) | ((value & 0x20) >> 2);
2146 extract_xtq6 (unsigned long insn,
2147 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
2148 int *invalid ATTRIBUTE_UNUSED)
2150 return ((insn << 2) & 0x20) | ((insn >> 21) & 0x1f);
2153 /* The XA field in an XX3 form instruction. This is split. */
2155 static unsigned long
2156 insert_xa6 (unsigned long insn,
2158 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
2159 const char **errmsg ATTRIBUTE_UNUSED)
2161 return insn | ((value & 0x1f) << 16) | ((value & 0x20) >> 3);
2165 extract_xa6 (unsigned long insn,
2166 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
2167 int *invalid ATTRIBUTE_UNUSED)
2169 return ((insn << 3) & 0x20) | ((insn >> 16) & 0x1f);
2172 /* The XB field in an XX3 form instruction. This is split. */
2174 static unsigned long
2175 insert_xb6 (unsigned long insn,
2177 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
2178 const char **errmsg ATTRIBUTE_UNUSED)
2180 return insn | ((value & 0x1f) << 11) | ((value & 0x20) >> 4);
2184 extract_xb6 (unsigned long insn,
2185 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
2186 int *invalid ATTRIBUTE_UNUSED)
2188 return ((insn << 4) & 0x20) | ((insn >> 11) & 0x1f);
2191 /* The XB field in an XX3 form instruction when it must be the same as
2192 the XA field in the instruction. This is used for extended
2193 mnemonics like xvmovdp. This operand is marked FAKE. The insertion
2194 function just copies the XA field into the XB field, and the
2195 extraction function just checks that the fields are the same. */
2197 static unsigned long
2198 insert_xb6s (unsigned long insn,
2199 long value ATTRIBUTE_UNUSED,
2200 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
2201 const char **errmsg ATTRIBUTE_UNUSED)
2203 return insn | (((insn >> 16) & 0x1f) << 11) | (((insn >> 2) & 0x1) << 1);
2207 extract_xb6s (unsigned long insn,
2208 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
2211 if ((((insn >> 16) & 0x1f) != ((insn >> 11) & 0x1f))
2212 || (((insn >> 2) & 0x1) != ((insn >> 1) & 0x1)))
2217 /* The XC field in an XX4 form instruction. This is split. */
2219 static unsigned long
2220 insert_xc6 (unsigned long insn,
2222 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
2223 const char **errmsg ATTRIBUTE_UNUSED)
2225 return insn | ((value & 0x1f) << 6) | ((value & 0x20) >> 2);
2229 extract_xc6 (unsigned long insn,
2230 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
2231 int *invalid ATTRIBUTE_UNUSED)
2233 return ((insn << 2) & 0x20) | ((insn >> 6) & 0x1f);
2236 static unsigned long
2237 insert_dm (unsigned long insn,
2239 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
2240 const char **errmsg)
2242 if (value != 0 && value != 1)
2243 *errmsg = _("invalid constant");
2244 return insn | (((value) ? 3 : 0) << 8);
2248 extract_dm (unsigned long insn,
2249 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
2254 value = (insn >> 8) & 3;
2255 if (value != 0 && value != 3)
2257 return (value) ? 1 : 0;
2260 /* The VLESIMM field in an I16A form instruction. This is split. */
2262 static unsigned long
2263 insert_vlesi (unsigned long insn,
2265 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
2266 const char **errmsg ATTRIBUTE_UNUSED)
2268 return insn | ((value & 0xf800) << 10) | (value & 0x7ff);
2272 extract_vlesi (unsigned long insn,
2273 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
2274 int *invalid ATTRIBUTE_UNUSED)
2276 long value = ((insn >> 10) & 0xf800) | (insn & 0x7ff);
2277 value = (value ^ 0x8000) - 0x8000;
2281 static unsigned long
2282 insert_vlensi (unsigned long insn,
2284 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
2285 const char **errmsg ATTRIBUTE_UNUSED)
2288 return insn | ((value & 0xf800) << 10) | (value & 0x7ff);
2291 extract_vlensi (unsigned long insn,
2292 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
2293 int *invalid ATTRIBUTE_UNUSED)
2295 long value = ((insn >> 10) & 0xf800) | (insn & 0x7ff);
2296 value = (value ^ 0x8000) - 0x8000;
2297 /* Don't use for disassembly. */
2302 /* The VLEUIMM field in an I16A form instruction. This is split. */
2304 static unsigned long
2305 insert_vleui (unsigned long insn,
2307 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
2308 const char **errmsg ATTRIBUTE_UNUSED)
2310 return insn | ((value & 0xf800) << 10) | (value & 0x7ff);
2314 extract_vleui (unsigned long insn,
2315 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
2316 int *invalid ATTRIBUTE_UNUSED)
2318 return ((insn >> 10) & 0xf800) | (insn & 0x7ff);
2321 /* The VLEUIMML field in an I16L form instruction. This is split. */
2323 static unsigned long
2324 insert_vleil (unsigned long insn,
2326 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
2327 const char **errmsg ATTRIBUTE_UNUSED)
2329 return insn | ((value & 0xf800) << 5) | (value & 0x7ff);
2333 extract_vleil (unsigned long insn,
2334 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
2335 int *invalid ATTRIBUTE_UNUSED)
2337 return ((insn >> 5) & 0xf800) | (insn & 0x7ff);
2341 /* Macros used to form opcodes. */
2343 /* The main opcode. */
2344 #define OP(x) ((((unsigned long)(x)) & 0x3f) << 26)
2345 #define OP_MASK OP (0x3f)
2347 /* The main opcode combined with a trap code in the TO field of a D
2348 form instruction. Used for extended mnemonics for the trap
2350 #define OPTO(x,to) (OP (x) | ((((unsigned long)(to)) & 0x1f) << 21))
2351 #define OPTO_MASK (OP_MASK | TO_MASK)
2353 /* The main opcode combined with a comparison size bit in the L field
2354 of a D form or X form instruction. Used for extended mnemonics for
2355 the comparison instructions. */
2356 #define OPL(x,l) (OP (x) | ((((unsigned long)(l)) & 1) << 21))
2357 #define OPL_MASK OPL (0x3f,1)
2359 /* The main opcode combined with an update code in D form instruction.
2360 Used for extended mnemonics for VLE memory instructions. */
2361 #define OPVUP(x,vup) (OP (x) | ((((unsigned long)(vup)) & 0xff) << 8))
2362 #define OPVUP_MASK OPVUP (0x3f, 0xff)
2364 /* An A form instruction. */
2365 #define A(op, xop, rc) (OP (op) | ((((unsigned long)(xop)) & 0x1f) << 1) | (((unsigned long)(rc)) & 1))
2366 #define A_MASK A (0x3f, 0x1f, 1)
2368 /* An A_MASK with the FRB field fixed. */
2369 #define AFRB_MASK (A_MASK | FRB_MASK)
2371 /* An A_MASK with the FRC field fixed. */
2372 #define AFRC_MASK (A_MASK | FRC_MASK)
2374 /* An A_MASK with the FRA and FRC fields fixed. */
2375 #define AFRAFRC_MASK (A_MASK | FRA_MASK | FRC_MASK)
2377 /* An AFRAFRC_MASK, but with L bit clear. */
2378 #define AFRALFRC_MASK (AFRAFRC_MASK & ~((unsigned long) 1 << 16))
2380 /* A B form instruction. */
2381 #define B(op, aa, lk) (OP (op) | ((((unsigned long)(aa)) & 1) << 1) | ((lk) & 1))
2382 #define B_MASK B (0x3f, 1, 1)
2384 /* A BD8 form instruction. This is a 16-bit instruction. */
2385 #define BD8(op, aa, lk) (((((unsigned long)(op)) & 0x3f) << 10) | (((aa) & 1) << 9) | (((lk) & 1) << 8))
2386 #define BD8_MASK BD8 (0x3f, 1, 1)
2388 /* Another BD8 form instruction. This is a 16-bit instruction. */
2389 #define BD8IO(op) ((((unsigned long)(op)) & 0x1f) << 11)
2390 #define BD8IO_MASK BD8IO (0x1f)
2392 /* A BD8 form instruction for simplified mnemonics. */
2393 #define EBD8IO(op, bo, bi) (BD8IO ((op)) | ((bo) << 10) | ((bi) << 8))
2394 /* A mask that excludes BO32 and BI32. */
2395 #define EBD8IO1_MASK 0xf800
2396 /* A mask that includes BO32 and excludes BI32. */
2397 #define EBD8IO2_MASK 0xfc00
2398 /* A mask that include BO32 AND BI32. */
2399 #define EBD8IO3_MASK 0xff00
2401 /* A BD15 form instruction. */
2402 #define BD15(op, aa, lk) (OP (op) | ((((unsigned long)(aa)) & 0xf) << 22) | ((lk) & 1))
2403 #define BD15_MASK BD15 (0x3f, 0xf, 1)
2405 /* A BD15 form instruction for extended conditional branch mnemonics. */
2406 #define EBD15(op, aa, bo, lk) (((op) & 0x3f) << 26) | (((aa) & 0xf) << 22) | (((bo) & 0x3) << 20) | ((lk) & 1)
2407 #define EBD15_MASK 0xfff00001
2409 /* A BD15 form instruction for extended conditional branch mnemonics with BI. */
2410 #define EBD15BI(op, aa, bo, bi, lk) (((op) & 0x3f) << 26) \
2411 | (((aa) & 0xf) << 22) \
2412 | (((bo) & 0x3) << 20) \
2413 | (((bi) & 0x3) << 16) \
2415 #define EBD15BI_MASK 0xfff30001
2417 /* A BD24 form instruction. */
2418 #define BD24(op, aa, lk) (OP (op) | ((((unsigned long)(aa)) & 1) << 25) | ((lk) & 1))
2419 #define BD24_MASK BD24 (0x3f, 1, 1)
2421 /* A B form instruction setting the BO field. */
2422 #define BBO(op, bo, aa, lk) (B ((op), (aa), (lk)) | ((((unsigned long)(bo)) & 0x1f) << 21))
2423 #define BBO_MASK BBO (0x3f, 0x1f, 1, 1)
2425 /* A BBO_MASK with the y bit of the BO field removed. This permits
2426 matching a conditional branch regardless of the setting of the y
2427 bit. Similarly for the 'at' bits used for power4 branch hints. */
2428 #define Y_MASK (((unsigned long) 1) << 21)
2429 #define AT1_MASK (((unsigned long) 3) << 21)
2430 #define AT2_MASK (((unsigned long) 9) << 21)
2431 #define BBOY_MASK (BBO_MASK &~ Y_MASK)
2432 #define BBOAT_MASK (BBO_MASK &~ AT1_MASK)
2434 /* A B form instruction setting the BO field and the condition bits of
2436 #define BBOCB(op, bo, cb, aa, lk) \
2437 (BBO ((op), (bo), (aa), (lk)) | ((((unsigned long)(cb)) & 0x3) << 16))
2438 #define BBOCB_MASK BBOCB (0x3f, 0x1f, 0x3, 1, 1)
2440 /* A BBOCB_MASK with the y bit of the BO field removed. */
2441 #define BBOYCB_MASK (BBOCB_MASK &~ Y_MASK)
2442 #define BBOATCB_MASK (BBOCB_MASK &~ AT1_MASK)
2443 #define BBOAT2CB_MASK (BBOCB_MASK &~ AT2_MASK)
2445 /* A BBOYCB_MASK in which the BI field is fixed. */
2446 #define BBOYBI_MASK (BBOYCB_MASK | BI_MASK)
2447 #define BBOATBI_MASK (BBOAT2CB_MASK | BI_MASK)
2449 /* A VLE C form instruction. */
2450 #define C_LK(x, lk) (((((unsigned long)(x)) & 0x7fff) << 1) | ((lk) & 1))
2451 #define C_LK_MASK C_LK(0x7fff, 1)
2452 #define C(x) ((((unsigned long)(x)) & 0xffff))
2453 #define C_MASK C(0xffff)
2455 /* An Context form instruction. */
2456 #define CTX(op, xop) (OP (op) | (((unsigned long)(xop)) & 0x7))
2457 #define CTX_MASK CTX(0x3f, 0x7)
2459 /* An User Context form instruction. */
2460 #define UCTX(op, xop) (OP (op) | (((unsigned long)(xop)) & 0x1f))
2461 #define UCTX_MASK UCTX(0x3f, 0x1f)
2463 /* The main opcode mask with the RA field clear. */
2464 #define DRA_MASK (OP_MASK | RA_MASK)
2466 /* A DQ form VSX instruction. */
2467 #define DQX(op, xop) (OP (op) | ((xop) & 0x7))
2468 #define DQX_MASK DQX (0x3f, 7)
2470 /* A DS form instruction. */
2471 #define DSO(op, xop) (OP (op) | ((xop) & 0x3))
2472 #define DS_MASK DSO (0x3f, 3)
2474 /* An DX form instruction. */
2475 #define DX(op, xop) (OP (op) | ((((unsigned long)(xop)) & 0x1f) << 1))
2476 #define DX_MASK DX (0x3f, 0x1f)
2478 /* An EVSEL form instruction. */
2479 #define EVSEL(op, xop) (OP (op) | (((unsigned long)(xop)) & 0xff) << 3)
2480 #define EVSEL_MASK EVSEL(0x3f, 0xff)
2482 /* An IA16 form instruction. */
2483 #define IA16(op, xop) (OP (op) | (((unsigned long)(xop)) & 0x1f) << 11)
2484 #define IA16_MASK IA16(0x3f, 0x1f)
2486 /* An I16A form instruction. */
2487 #define I16A(op, xop) (OP (op) | (((unsigned long)(xop)) & 0x1f) << 11)
2488 #define I16A_MASK I16A(0x3f, 0x1f)
2490 /* An I16L form instruction. */
2491 #define I16L(op, xop) (OP (op) | (((unsigned long)(xop)) & 0x1f) << 11)
2492 #define I16L_MASK I16L(0x3f, 0x1f)
2494 /* An IM7 form instruction. */
2495 #define IM7(op) ((((unsigned long)(op)) & 0x1f) << 11)
2496 #define IM7_MASK IM7(0x1f)
2498 /* An M form instruction. */
2499 #define M(op, rc) (OP (op) | ((rc) & 1))
2500 #define M_MASK M (0x3f, 1)
2502 /* An LI20 form instruction. */
2503 #define LI20(op, xop) (OP (op) | (((unsigned long)(xop)) & 0x1) << 15)
2504 #define LI20_MASK LI20(0x3f, 0x1)
2506 /* An M form instruction with the ME field specified. */
2507 #define MME(op, me, rc) (M ((op), (rc)) | ((((unsigned long)(me)) & 0x1f) << 1))
2509 /* An M_MASK with the MB and ME fields fixed. */
2510 #define MMBME_MASK (M_MASK | MB_MASK | ME_MASK)
2512 /* An M_MASK with the SH and ME fields fixed. */
2513 #define MSHME_MASK (M_MASK | SH_MASK | ME_MASK)
2515 /* An MD form instruction. */
2516 #define MD(op, xop, rc) (OP (op) | ((((unsigned long)(xop)) & 0x7) << 2) | ((rc) & 1))
2517 #define MD_MASK MD (0x3f, 0x7, 1)
2519 /* An MD_MASK with the MB field fixed. */
2520 #define MDMB_MASK (MD_MASK | MB6_MASK)
2522 /* An MD_MASK with the SH field fixed. */
2523 #define MDSH_MASK (MD_MASK | SH6_MASK)
2525 /* An MDS form instruction. */
2526 #define MDS(op, xop, rc) (OP (op) | ((((unsigned long)(xop)) & 0xf) << 1) | ((rc) & 1))
2527 #define MDS_MASK MDS (0x3f, 0xf, 1)
2529 /* An MDS_MASK with the MB field fixed. */
2530 #define MDSMB_MASK (MDS_MASK | MB6_MASK)
2532 /* An SC form instruction. */
2533 #define SC(op, sa, lk) (OP (op) | ((((unsigned long)(sa)) & 1) << 1) | ((lk) & 1))
2534 #define SC_MASK (OP_MASK | (((unsigned long)0x3ff) << 16) | (((unsigned long)1) << 1) | 1)
2536 /* An SCI8 form instruction. */
2537 #define SCI8(op, xop) (OP (op) | ((((unsigned long)(xop)) & 0x1f) << 11))
2538 #define SCI8_MASK SCI8(0x3f, 0x1f)
2540 /* An SCI8 form instruction. */
2541 #define SCI8BF(op, fop, xop) (OP (op) | ((((unsigned long)(xop)) & 0x1f) << 11) | (((fop) & 7) << 23))
2542 #define SCI8BF_MASK SCI8BF(0x3f, 7, 0x1f)
2544 /* An SD4 form instruction. This is a 16-bit instruction. */
2545 #define SD4(op) ((((unsigned long)(op)) & 0xf) << 12)
2546 #define SD4_MASK SD4(0xf)
2548 /* An SE_IM5 form instruction. This is a 16-bit instruction. */
2549 #define SE_IM5(op, xop) (((((unsigned long)(op)) & 0x3f) << 10) | (((xop) & 0x1) << 9))
2550 #define SE_IM5_MASK SE_IM5(0x3f, 1)
2552 /* An SE_R form instruction. This is a 16-bit instruction. */
2553 #define SE_R(op, xop) (((((unsigned long)(op)) & 0x3f) << 10) | (((xop) & 0x3f) << 4))
2554 #define SE_R_MASK SE_R(0x3f, 0x3f)
2556 /* An SE_RR form instruction. This is a 16-bit instruction. */
2557 #define SE_RR(op, xop) (((((unsigned long)(op)) & 0x3f) << 10) | (((xop) & 0x3) << 8))
2558 #define SE_RR_MASK SE_RR(0x3f, 3)
2560 /* A VX form instruction. */
2561 #define VX(op, xop) (OP (op) | (((unsigned long)(xop)) & 0x7ff))
2563 /* The mask for an VX form instruction. */
2564 #define VX_MASK VX(0x3f, 0x7ff)
2566 /* A VX_MASK with the VA field fixed. */
2567 #define VXVA_MASK (VX_MASK | (0x1f << 16))
2569 /* A VX_MASK with the VB field fixed. */
2570 #define VXVB_MASK (VX_MASK | (0x1f << 11))
2572 /* A VX_MASK with the VA and VB fields fixed. */
2573 #define VXVAVB_MASK (VX_MASK | (0x1f << 16) | (0x1f << 11))
2575 /* A VX_MASK with the VD and VA fields fixed. */
2576 #define VXVDVA_MASK (VX_MASK | (0x1f << 21) | (0x1f << 16))
2578 /* A VX_MASK with a UIMM4 field. */
2579 #define VXUIMM4_MASK (VX_MASK | (0x1 << 20))
2581 /* A VX_MASK with a UIMM3 field. */
2582 #define VXUIMM3_MASK (VX_MASK | (0x3 << 19))
2584 /* A VX_MASK with a UIMM2 field. */
2585 #define VXUIMM2_MASK (VX_MASK | (0x7 << 18))
2587 /* A VX_MASK with a PS field. */
2588 #define VXPS_MASK (VX_MASK & ~(0x1 << 9))
2590 /* A VX_MASK with the VA field fixed with a PS field. */
2591 #define VXVAPS_MASK ((VX_MASK | (0x1f << 16)) & ~(0x1 << 9))
2593 /* A VA form instruction. */
2594 #define VXA(op, xop) (OP (op) | (((unsigned long)(xop)) & 0x03f))
2596 /* The mask for an VA form instruction. */
2597 #define VXA_MASK VXA(0x3f, 0x3f)
2599 /* A VXA_MASK with a SHB field. */
2600 #define VXASHB_MASK (VXA_MASK | (1 << 10))
2602 /* A VXR form instruction. */
2603 #define VXR(op, xop, rc) (OP (op) | (((rc) & 1) << 10) | (((unsigned long)(xop)) & 0x3ff))
2605 /* The mask for a VXR form instruction. */
2606 #define VXR_MASK VXR(0x3f, 0x3ff, 1)
2608 /* A VX form instruction with a VA tertiary opcode. */
2609 #define VXVA(op, xop, vaop) (VX(op,xop) | (((vaop) & 0x1f) << 16))
2611 /* An X form instruction. */
2612 #define X(op, xop) (OP (op) | ((((unsigned long)(xop)) & 0x3ff) << 1))
2614 /* A X form instruction for Quad-Precision FP Instructions. */
2615 #define XVA(op, xop, vaop) (X(op,xop) | (((vaop) & 0x1f) << 16))
2617 /* An EX form instruction. */
2618 #define EX(op, xop) (OP (op) | (((unsigned long)(xop)) & 0x7ff))
2620 /* The mask for an EX form instruction. */
2621 #define EX_MASK EX (0x3f, 0x7ff)
2623 /* An XX2 form instruction. */
2624 #define XX2(op, xop) (OP (op) | ((((unsigned long)(xop)) & 0x1ff) << 2))
2626 /* A XX2 form instruction with the VA bits specified. */
2627 #define XX2VA(op, xop, vaop) (XX2(op,xop) | (((vaop) & 0x1f) << 16))
2629 /* An XX3 form instruction. */
2630 #define XX3(op, xop) (OP (op) | ((((unsigned long)(xop)) & 0xff) << 3))
2632 /* An XX3 form instruction with the RC bit specified. */
2633 #define XX3RC(op, xop, rc) (OP (op) | (((rc) & 1) << 10) | ((((unsigned long)(xop)) & 0x7f) << 3))
2635 /* An XX4 form instruction. */
2636 #define XX4(op, xop) (OP (op) | ((((unsigned long)(xop)) & 0x3) << 4))
2638 /* A Z form instruction. */
2639 #define Z(op, xop) (OP (op) | ((((unsigned long)(xop)) & 0x1ff) << 1))
2641 /* An X form instruction with the RC bit specified. */
2642 #define XRC(op, xop, rc) (X ((op), (xop)) | ((rc) & 1))
2644 /* A X form instruction for Quad-Precision FP Instructions with RC bit. */
2645 #define XVARC(op, xop, vaop, rc) (XVA ((op), (xop), (vaop)) | ((rc) & 1))
2647 /* A Z form instruction with the RC bit specified. */
2648 #define ZRC(op, xop, rc) (Z ((op), (xop)) | ((rc) & 1))
2650 /* The mask for an X form instruction. */
2651 #define X_MASK XRC (0x3f, 0x3ff, 1)
2653 /* The mask for an X form instruction with the BF bits specified. */
2654 #define XBF_MASK (X_MASK | (3 << 21))
2656 /* An X form wait instruction with everything filled in except the WC field. */
2657 #define XWC_MASK (XRC (0x3f, 0x3ff, 1) | (7 << 23) | RA_MASK | RB_MASK)
2659 /* The mask for an XX1 form instruction. */
2660 #define XX1_MASK X (0x3f, 0x3ff)
2662 /* An XX1_MASK with the RB field fixed. */
2663 #define XX1RB_MASK (XX1_MASK | RB_MASK)
2665 /* The mask for an XX2 form instruction. */
2666 #define XX2_MASK (XX2 (0x3f, 0x1ff) | (0x1f << 16))
2668 /* The mask for an XX2 form instruction with the UIM bits specified. */
2669 #define XX2UIM_MASK (XX2 (0x3f, 0x1ff) | (7 << 18))
2671 /* The mask for an XX2 form instruction with the 4 UIM bits specified. */
2672 #define XX2UIM4_MASK (XX2 (0x3f, 0x1ff) | (1 << 20))
2674 /* The mask for an XX2 form instruction with the BF bits specified. */
2675 #define XX2BF_MASK (XX2_MASK | (3 << 21) | (1))
2677 /* The mask for an XX2 form instruction with the BF and DCMX bits specified. */
2678 #define XX2BFD_MASK (XX2 (0x3f, 0x1ff) | 1)
2680 /* The mask for an XX2 form instruction with a split DCMX bits specified. */
2681 #define XX2DCMXS_MASK XX2 (0x3f, 0x1ee)
2683 /* The mask for an XX3 form instruction. */
2684 #define XX3_MASK XX3 (0x3f, 0xff)
2686 /* The mask for an XX3 form instruction with the BF bits specified. */
2687 #define XX3BF_MASK (XX3 (0x3f, 0xff) | (3 << 21) | (1))
2689 /* The mask for an XX3 form instruction with the DM or SHW bits specified. */
2690 #define XX3DM_MASK (XX3 (0x3f, 0x1f) | (1 << 10))
2691 #define XX3SHW_MASK XX3DM_MASK
2693 /* The mask for an XX4 form instruction. */
2694 #define XX4_MASK XX4 (0x3f, 0x3)
2696 /* An X form wait instruction with everything filled in except the WC field. */
2697 #define XWC_MASK (XRC (0x3f, 0x3ff, 1) | (7 << 23) | RA_MASK | RB_MASK)
2699 /* The mask for a Z form instruction. */
2700 #define Z_MASK ZRC (0x3f, 0x1ff, 1)
2701 #define Z2_MASK ZRC (0x3f, 0xff, 1)
2703 /* An X_MASK with the RA/VA field fixed. */
2704 #define XRA_MASK (X_MASK | RA_MASK)
2705 #define XVA_MASK XRA_MASK
2707 /* An XRA_MASK with the A_L/W field clear. */
2708 #define XWRA_MASK (XRA_MASK & ~((unsigned long) 1 << 16))
2709 #define XRLA_MASK XWRA_MASK
2711 /* An X_MASK with the RB field fixed. */
2712 #define XRB_MASK (X_MASK | RB_MASK)
2714 /* An X_MASK with the RT field fixed. */
2715 #define XRT_MASK (X_MASK | RT_MASK)
2717 /* An XRT_MASK mask with the L bits clear. */
2718 #define XLRT_MASK (XRT_MASK & ~((unsigned long) 0x3 << 21))
2720 /* An X_MASK with the RA and RB fields fixed. */
2721 #define XRARB_MASK (X_MASK | RA_MASK | RB_MASK)
2723 /* An XBF_MASK with the RA and RB fields fixed. */
2724 #define XBFRARB_MASK (XBF_MASK | RA_MASK | RB_MASK)
2726 /* An XRARB_MASK, but with the L bit clear. */
2727 #define XRLARB_MASK (XRARB_MASK & ~((unsigned long) 1 << 16))
2729 /* An XRARB_MASK, but with the L bits in a darn instruction clear. */
2730 #define XLRAND_MASK (XRARB_MASK & ~((unsigned long) 3 << 16))
2732 /* An X_MASK with the RT and RA fields fixed. */
2733 #define XRTRA_MASK (X_MASK | RT_MASK | RA_MASK)
2735 /* An X_MASK with the RT and RB fields fixed. */
2736 #define XRTRB_MASK (X_MASK | RT_MASK | RB_MASK)
2738 /* An XRTRA_MASK, but with L bit clear. */
2739 #define XRTLRA_MASK (XRTRA_MASK & ~((unsigned long) 1 << 21))
2741 /* An X_MASK with the RT, RA and RB fields fixed. */
2742 #define XRTRARB_MASK (X_MASK | RT_MASK | RA_MASK | RB_MASK)
2744 /* An XRTRARB_MASK, but with L bit clear. */
2745 #define XRTLRARB_MASK (XRTRARB_MASK & ~((unsigned long) 1 << 21))
2747 /* An XRTRARB_MASK, but with A bit clear. */
2748 #define XRTARARB_MASK (XRTRARB_MASK & ~((unsigned long) 1 << 25))
2750 /* An XRTRARB_MASK, but with BF bits clear. */
2751 #define XRTBFRARB_MASK (XRTRARB_MASK & ~((unsigned long) 7 << 23))
2753 /* An X form instruction with the L bit specified. */
2754 #define XOPL(op, xop, l) (X ((op), (xop)) | ((((unsigned long)(l)) & 1) << 21))
2756 /* An X form instruction with the L bits specified. */
2757 #define XOPL2(op, xop, l) (X ((op), (xop)) | ((((unsigned long)(l)) & 3) << 21))
2759 /* An X form instruction with the L bit and RC bit specified. */
2760 #define XRCL(op, xop, l, rc) (XRC ((op), (xop), (rc)) | ((((unsigned long)(l)) & 1) << 21))
2762 /* An X form instruction with RT fields specified */
2763 #define XRT(op, xop, rt) (X ((op), (xop)) \
2764 | ((((unsigned long)(rt)) & 0x1f) << 21))
2766 /* An X form instruction with RT and RA fields specified */
2767 #define XRTRA(op, xop, rt, ra) (X ((op), (xop)) \
2768 | ((((unsigned long)(rt)) & 0x1f) << 21) \
2769 | ((((unsigned long)(ra)) & 0x1f) << 16))
2771 /* The mask for an X form comparison instruction. */
2772 #define XCMP_MASK (X_MASK | (((unsigned long)1) << 22))
2774 /* The mask for an X form comparison instruction with the L field
2776 #define XCMPL_MASK (XCMP_MASK | (((unsigned long)1) << 21))
2778 /* An X form trap instruction with the TO field specified. */
2779 #define XTO(op, xop, to) (X ((op), (xop)) | ((((unsigned long)(to)) & 0x1f) << 21))
2780 #define XTO_MASK (X_MASK | TO_MASK)
2782 /* An X form tlb instruction with the SH field specified. */
2783 #define XTLB(op, xop, sh) (X ((op), (xop)) | ((((unsigned long)(sh)) & 0x1f) << 11))
2784 #define XTLB_MASK (X_MASK | SH_MASK)
2786 /* An X form sync instruction. */
2787 #define XSYNC(op, xop, l) (X ((op), (xop)) | ((((unsigned long)(l)) & 3) << 21))
2789 /* An X form sync instruction with everything filled in except the LS field. */
2790 #define XSYNC_MASK (0xff9fffff)
2792 /* An X form sync instruction with everything filled in except the L and E fields. */
2793 #define XSYNCLE_MASK (0xff90ffff)
2795 /* An X_MASK, but with the EH bit clear. */
2796 #define XEH_MASK (X_MASK & ~((unsigned long )1))
2798 /* An X form AltiVec dss instruction. */
2799 #define XDSS(op, xop, a) (X ((op), (xop)) | ((((unsigned long)(a)) & 1) << 25))
2800 #define XDSS_MASK XDSS(0x3f, 0x3ff, 1)
2802 /* An XFL form instruction. */
2803 #define XFL(op, xop, rc) (OP (op) | ((((unsigned long)(xop)) & 0x3ff) << 1) | (((unsigned long)(rc)) & 1))
2804 #define XFL_MASK XFL (0x3f, 0x3ff, 1)
2806 /* An X form isel instruction. */
2807 #define XISEL(op, xop) (OP (op) | ((((unsigned long)(xop)) & 0x1f) << 1))
2808 #define XISEL_MASK XISEL(0x3f, 0x1f)
2810 /* An XL form instruction with the LK field set to 0. */
2811 #define XL(op, xop) (OP (op) | ((((unsigned long)(xop)) & 0x3ff) << 1))
2813 /* An XL form instruction which uses the LK field. */
2814 #define XLLK(op, xop, lk) (XL ((op), (xop)) | ((lk) & 1))
2816 /* The mask for an XL form instruction. */
2817 #define XL_MASK XLLK (0x3f, 0x3ff, 1)
2819 /* An XL_MASK with the RT, RA and RB fields fixed, but S bit clear. */
2820 #define XLS_MASK ((XL_MASK | RT_MASK | RA_MASK | RB_MASK) & ~(1 << 11))
2822 /* An XL form instruction which explicitly sets the BO field. */
2823 #define XLO(op, bo, xop, lk) \
2824 (XLLK ((op), (xop), (lk)) | ((((unsigned long)(bo)) & 0x1f) << 21))
2825 #define XLO_MASK (XL_MASK | BO_MASK)
2827 /* An XL form instruction which explicitly sets the y bit of the BO
2829 #define XLYLK(op, xop, y, lk) (XLLK ((op), (xop), (lk)) | ((((unsigned long)(y)) & 1) << 21))
2830 #define XLYLK_MASK (XL_MASK | Y_MASK)
2832 /* An XL form instruction which sets the BO field and the condition
2833 bits of the BI field. */
2834 #define XLOCB(op, bo, cb, xop, lk) \
2835 (XLO ((op), (bo), (xop), (lk)) | ((((unsigned long)(cb)) & 3) << 16))
2836 #define XLOCB_MASK XLOCB (0x3f, 0x1f, 0x3, 0x3ff, 1)
2838 /* An XL_MASK or XLYLK_MASK or XLOCB_MASK with the BB field fixed. */
2839 #define XLBB_MASK (XL_MASK | BB_MASK)
2840 #define XLYBB_MASK (XLYLK_MASK | BB_MASK)
2841 #define XLBOCBBB_MASK (XLOCB_MASK | BB_MASK)
2843 /* A mask for branch instructions using the BH field. */
2844 #define XLBH_MASK (XL_MASK | (0x1c << 11))
2846 /* An XL_MASK with the BO and BB fields fixed. */
2847 #define XLBOBB_MASK (XL_MASK | BO_MASK | BB_MASK)
2849 /* An XL_MASK with the BO, BI and BB fields fixed. */
2850 #define XLBOBIBB_MASK (XL_MASK | BO_MASK | BI_MASK | BB_MASK)
2852 /* An X form mbar instruction with MO field. */
2853 #define XMBAR(op, xop, mo) (X ((op), (xop)) | ((((unsigned long)(mo)) & 1) << 21))
2855 /* An XO form instruction. */
2856 #define XO(op, xop, oe, rc) \
2857 (OP (op) | ((((unsigned long)(xop)) & 0x1ff) << 1) | ((((unsigned long)(oe)) & 1) << 10) | (((unsigned long)(rc)) & 1))
2858 #define XO_MASK XO (0x3f, 0x1ff, 1, 1)
2860 /* An XO_MASK with the RB field fixed. */
2861 #define XORB_MASK (XO_MASK | RB_MASK)
2863 /* An XOPS form instruction for paired singles. */
2864 #define XOPS(op, xop, rc) \
2865 (OP (op) | ((((unsigned long)(xop)) & 0x3ff) << 1) | (((unsigned long)(rc)) & 1))
2866 #define XOPS_MASK XOPS (0x3f, 0x3ff, 1)
2869 /* An XS form instruction. */
2870 #define XS(op, xop, rc) (OP (op) | ((((unsigned long)(xop)) & 0x1ff) << 2) | (((unsigned long)(rc)) & 1))
2871 #define XS_MASK XS (0x3f, 0x1ff, 1)
2873 /* A mask for the FXM version of an XFX form instruction. */
2874 #define XFXFXM_MASK (X_MASK | (1 << 11) | (1 << 20))
2876 /* An XFX form instruction with the FXM field filled in. */
2877 #define XFXM(op, xop, fxm, p4) \
2878 (X ((op), (xop)) | ((((unsigned long)(fxm)) & 0xff) << 12) \
2879 | ((unsigned long)(p4) << 20))
2881 /* An XFX form instruction with the SPR field filled in. */
2882 #define XSPR(op, xop, spr) \
2883 (X ((op), (xop)) | ((((unsigned long)(spr)) & 0x1f) << 16) | ((((unsigned long)(spr)) & 0x3e0) << 6))
2884 #define XSPR_MASK (X_MASK | SPR_MASK)
2886 /* An XFX form instruction with the SPR field filled in except for the
2888 #define XSPRBAT_MASK (XSPR_MASK &~ SPRBAT_MASK)
2890 /* An XFX form instruction with the SPR field filled in except for the
2892 #define XSPRG_MASK (XSPR_MASK & ~(0x1f << 16))
2894 /* An X form instruction with everything filled in except the E field. */
2895 #define XE_MASK (0xffff7fff)
2897 /* An X form user context instruction. */
2898 #define XUC(op, xop) (OP (op) | (((unsigned long)(xop)) & 0x1f))
2899 #define XUC_MASK XUC(0x3f, 0x1f)
2901 /* An XW form instruction. */
2902 #define XW(op, xop, rc) (OP (op) | ((((unsigned long)(xop)) & 0x3f) << 1) | ((rc) & 1))
2903 /* The mask for a G form instruction. rc not supported at present. */
2904 #define XW_MASK XW (0x3f, 0x3f, 0)
2906 /* An APU form instruction. */
2907 #define APU(op, xop, rc) (OP (op) | (((unsigned long)(xop)) & 0x3ff) << 1 | ((rc) & 1))
2909 /* The mask for an APU form instruction. */
2910 #define APU_MASK APU (0x3f, 0x3ff, 1)
2911 #define APU_RT_MASK (APU_MASK | RT_MASK)
2912 #define APU_RA_MASK (APU_MASK | RA_MASK)
2914 /* The BO encodings used in extended conditional branch mnemonics. */
2915 #define BODNZF (0x0)
2916 #define BODNZFP (0x1)
2918 #define BODZFP (0x3)
2919 #define BODNZT (0x8)
2920 #define BODNZTP (0x9)
2922 #define BODZTP (0xb)
2933 #define BODNZ (0x10)
2934 #define BODNZP (0x11)
2936 #define BODZP (0x13)
2937 #define BODNZM4 (0x18)
2938 #define BODNZP4 (0x19)
2939 #define BODZM4 (0x1a)
2940 #define BODZP4 (0x1b)
2944 /* The BO16 encodings used in extended VLE conditional branch mnemonics. */
2948 /* The BO32 encodings used in extended VLE conditional branch mnemonics. */
2951 #define BO32DNZ (0x2)
2952 #define BO32DZ (0x3)
2954 /* The BI condition bit encodings used in extended conditional branch
2961 /* The TO encodings used in extended trap mnemonics. */
2978 /* Smaller names for the flags so each entry in the opcodes table will
2979 fit on a single line. */
2981 #define PPC PPC_OPCODE_PPC
2982 #define PPCCOM PPC_OPCODE_PPC | PPC_OPCODE_COMMON
2983 #define POWER4 PPC_OPCODE_POWER4
2984 #define POWER5 PPC_OPCODE_POWER5
2985 #define POWER6 PPC_OPCODE_POWER6
2986 #define POWER7 PPC_OPCODE_POWER7
2987 #define POWER8 PPC_OPCODE_POWER8
2988 #define POWER9 PPC_OPCODE_POWER9
2989 #define CELL PPC_OPCODE_CELL
2990 #define PPC64 PPC_OPCODE_64 | PPC_OPCODE_64_BRIDGE
2991 #define NON32 (PPC_OPCODE_64 | PPC_OPCODE_POWER4 \
2992 | PPC_OPCODE_EFS | PPC_OPCODE_E500MC | PPC_OPCODE_TITAN)
2993 #define PPC403 PPC_OPCODE_403
2994 #define PPC405 PPC_OPCODE_405
2995 #define PPC440 PPC_OPCODE_440
2996 #define PPC464 PPC440
2997 #define PPC476 PPC_OPCODE_476
2998 #define PPC750 PPC_OPCODE_750
2999 #define PPC7450 PPC_OPCODE_7450
3000 #define PPC860 PPC_OPCODE_860
3001 #define PPCPS PPC_OPCODE_PPCPS
3002 #define PPCVEC PPC_OPCODE_ALTIVEC
3003 #define PPCVEC2 PPC_OPCODE_ALTIVEC2
3004 #define PPCVEC3 PPC_OPCODE_ALTIVEC2
3005 #define PPCVSX PPC_OPCODE_VSX
3006 #define PPCVSX2 PPC_OPCODE_VSX
3007 #define PPCVSX3 PPC_OPCODE_VSX3
3008 #define POWER PPC_OPCODE_POWER
3009 #define POWER2 PPC_OPCODE_POWER | PPC_OPCODE_POWER2
3010 #define PWR2COM PPC_OPCODE_POWER | PPC_OPCODE_POWER2 | PPC_OPCODE_COMMON
3011 #define PPCPWR2 PPC_OPCODE_PPC | PPC_OPCODE_POWER | PPC_OPCODE_POWER2 | PPC_OPCODE_COMMON
3012 #define COM PPC_OPCODE_POWER | PPC_OPCODE_PPC | PPC_OPCODE_COMMON
3013 #define M601 PPC_OPCODE_POWER | PPC_OPCODE_601
3014 #define PWRCOM PPC_OPCODE_POWER | PPC_OPCODE_601 | PPC_OPCODE_COMMON
3015 #define MFDEC1 PPC_OPCODE_POWER
3016 #define MFDEC2 PPC_OPCODE_PPC | PPC_OPCODE_601 | PPC_OPCODE_BOOKE | PPC_OPCODE_TITAN
3017 #define BOOKE PPC_OPCODE_BOOKE
3018 #define NO371 PPC_OPCODE_BOOKE | PPC_OPCODE_PPCPS | PPC_OPCODE_EFS
3019 #define PPCE300 PPC_OPCODE_E300
3020 #define PPCSPE PPC_OPCODE_SPE
3021 #define PPCISEL PPC_OPCODE_ISEL
3022 #define PPCEFS PPC_OPCODE_EFS
3023 #define PPCBRLK PPC_OPCODE_BRLOCK
3024 #define PPCPMR PPC_OPCODE_PMR
3025 #define PPCTMR PPC_OPCODE_TMR
3026 #define PPCCHLK PPC_OPCODE_CACHELCK
3027 #define PPCRFMCI PPC_OPCODE_RFMCI
3028 #define E500MC PPC_OPCODE_E500MC
3029 #define PPCA2 PPC_OPCODE_A2
3030 #define TITAN PPC_OPCODE_TITAN
3031 #define MULHW PPC_OPCODE_405 | PPC_OPCODE_440 | TITAN
3032 #define E500 PPC_OPCODE_E500
3033 #define E6500 PPC_OPCODE_E6500
3034 #define PPCVLE PPC_OPCODE_VLE
3035 #define PPCHTM PPC_OPCODE_HTM
3036 /* The list of embedded processors that use the embedded operand ordering
3037 for the 3 operand dcbt and dcbtst instructions. */
3038 #define DCBT_EO (PPC_OPCODE_E500 | PPC_OPCODE_E500MC | PPC_OPCODE_476 \
3043 /* The opcode table.
3045 The format of the opcode table is:
3047 NAME OPCODE MASK FLAGS ANTI {OPERANDS}
3049 NAME is the name of the instruction.
3050 OPCODE is the instruction opcode.
3051 MASK is the opcode mask; this is used to tell the disassembler
3052 which bits in the actual opcode must match OPCODE.
3053 FLAGS are flags indicating which processors support the instruction.
3054 ANTI indicates which processors don't support the instruction.
3055 OPERANDS is the list of operands.
3057 The disassembler reads the table in order and prints the first
3058 instruction which matches, so this table is sorted to put more
3059 specific instructions before more general instructions.
3061 This table must be sorted by major opcode. Please try to keep it
3062 vaguely sorted within major opcode too, except of course where
3063 constrained otherwise by disassembler operation. */
3065 const struct powerpc_opcode powerpc_opcodes[] = {
3066 {"attn", X(0,256), X_MASK, POWER4|PPCA2, PPC476|PPCVLE, {0}},
3067 {"tdlgti", OPTO(2,TOLGT), OPTO_MASK, PPC64, PPCVLE, {RA, SI}},
3068 {"tdllti", OPTO(2,TOLLT), OPTO_MASK, PPC64, PPCVLE, {RA, SI}},
3069 {"tdeqi", OPTO(2,TOEQ), OPTO_MASK, PPC64, PPCVLE, {RA, SI}},
3070 {"tdlgei", OPTO(2,TOLGE), OPTO_MASK, PPC64, PPCVLE, {RA, SI}},
3071 {"tdlnli", OPTO(2,TOLNL), OPTO_MASK, PPC64, PPCVLE, {RA, SI}},
3072 {"tdllei", OPTO(2,TOLLE), OPTO_MASK, PPC64, PPCVLE, {RA, SI}},
3073 {"tdlngi", OPTO(2,TOLNG), OPTO_MASK, PPC64, PPCVLE, {RA, SI}},
3074 {"tdgti", OPTO(2,TOGT), OPTO_MASK, PPC64, PPCVLE, {RA, SI}},
3075 {"tdgei", OPTO(2,TOGE), OPTO_MASK, PPC64, PPCVLE, {RA, SI}},
3076 {"tdnli", OPTO(2,TONL), OPTO_MASK, PPC64, PPCVLE, {RA, SI}},
3077 {"tdlti", OPTO(2,TOLT), OPTO_MASK, PPC64, PPCVLE, {RA, SI}},
3078 {"tdlei", OPTO(2,TOLE), OPTO_MASK, PPC64, PPCVLE, {RA, SI}},
3079 {"tdngi", OPTO(2,TONG), OPTO_MASK, PPC64, PPCVLE, {RA, SI}},
3080 {"tdnei", OPTO(2,TONE), OPTO_MASK, PPC64, PPCVLE, {RA, SI}},
3081 {"tdui", OPTO(2,TOU), OPTO_MASK, PPC64, PPCVLE, {RA, SI}},
3082 {"tdi", OP(2), OP_MASK, PPC64, PPCVLE, {TO, RA, SI}},
3084 {"twlgti", OPTO(3,TOLGT), OPTO_MASK, PPCCOM, PPCVLE, {RA, SI}},
3085 {"tlgti", OPTO(3,TOLGT), OPTO_MASK, PWRCOM, PPCVLE, {RA, SI}},
3086 {"twllti", OPTO(3,TOLLT), OPTO_MASK, PPCCOM, PPCVLE, {RA, SI}},
3087 {"tllti", OPTO(3,TOLLT), OPTO_MASK, PWRCOM, PPCVLE, {RA, SI}},
3088 {"tweqi", OPTO(3,TOEQ), OPTO_MASK, PPCCOM, PPCVLE, {RA, SI}},
3089 {"teqi", OPTO(3,TOEQ), OPTO_MASK, PWRCOM, PPCVLE, {RA, SI}},
3090 {"twlgei", OPTO(3,TOLGE), OPTO_MASK, PPCCOM, PPCVLE, {RA, SI}},
3091 {"tlgei", OPTO(3,TOLGE), OPTO_MASK, PWRCOM, PPCVLE, {RA, SI}},
3092 {"twlnli", OPTO(3,TOLNL), OPTO_MASK, PPCCOM, PPCVLE, {RA, SI}},
3093 {"tlnli", OPTO(3,TOLNL), OPTO_MASK, PWRCOM, PPCVLE, {RA, SI}},
3094 {"twllei", OPTO(3,TOLLE), OPTO_MASK, PPCCOM, PPCVLE, {RA, SI}},
3095 {"tllei", OPTO(3,TOLLE), OPTO_MASK, PWRCOM, PPCVLE, {RA, SI}},
3096 {"twlngi", OPTO(3,TOLNG), OPTO_MASK, PPCCOM, PPCVLE, {RA, SI}},
3097 {"tlngi", OPTO(3,TOLNG), OPTO_MASK, PWRCOM, PPCVLE, {RA, SI}},
3098 {"twgti", OPTO(3,TOGT), OPTO_MASK, PPCCOM, PPCVLE, {RA, SI}},
3099 {"tgti", OPTO(3,TOGT), OPTO_MASK, PWRCOM, PPCVLE, {RA, SI}},
3100 {"twgei", OPTO(3,TOGE), OPTO_MASK, PPCCOM, PPCVLE, {RA, SI}},
3101 {"tgei", OPTO(3,TOGE), OPTO_MASK, PWRCOM, PPCVLE, {RA, SI}},
3102 {"twnli", OPTO(3,TONL), OPTO_MASK, PPCCOM, PPCVLE, {RA, SI}},
3103 {"tnli", OPTO(3,TONL), OPTO_MASK, PWRCOM, PPCVLE, {RA, SI}},
3104 {"twlti", OPTO(3,TOLT), OPTO_MASK, PPCCOM, PPCVLE, {RA, SI}},
3105 {"tlti", OPTO(3,TOLT), OPTO_MASK, PWRCOM, PPCVLE, {RA, SI}},
3106 {"twlei", OPTO(3,TOLE), OPTO_MASK, PPCCOM, PPCVLE, {RA, SI}},
3107 {"tlei", OPTO(3,TOLE), OPTO_MASK, PWRCOM, PPCVLE, {RA, SI}},
3108 {"twngi", OPTO(3,TONG), OPTO_MASK, PPCCOM, PPCVLE, {RA, SI}},
3109 {"tngi", OPTO(3,TONG), OPTO_MASK, PWRCOM, PPCVLE, {RA, SI}},
3110 {"twnei", OPTO(3,TONE), OPTO_MASK, PPCCOM, PPCVLE, {RA, SI}},
3111 {"tnei", OPTO(3,TONE), OPTO_MASK, PWRCOM, PPCVLE, {RA, SI}},
3112 {"twui", OPTO(3,TOU), OPTO_MASK, PPCCOM, PPCVLE, {RA, SI}},
3113 {"tui", OPTO(3,TOU), OPTO_MASK, PWRCOM, PPCVLE, {RA, SI}},
3114 {"twi", OP(3), OP_MASK, PPCCOM, PPCVLE, {TO, RA, SI}},
3115 {"ti", OP(3), OP_MASK, PWRCOM, PPCVLE, {TO, RA, SI}},
3117 {"ps_cmpu0", X (4, 0), XBF_MASK, PPCPS, 0, {BF, FRA, FRB}},
3118 {"vaddubm", VX (4, 0), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
3119 {"vmul10cuq", VX (4, 1), VXVB_MASK, PPCVEC3, 0, {VD, VA}},
3120 {"vmaxub", VX (4, 2), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
3121 {"vrlb", VX (4, 4), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
3122 {"vcmpequb", VXR(4, 6,0), VXR_MASK, PPCVEC, 0, {VD, VA, VB}},
3123 {"vcmpneb", VXR(4, 7,0), VXR_MASK, PPCVEC3, 0, {VD, VA, VB}},
3124 {"vmuloub", VX (4, 8), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
3125 {"vaddfp", VX (4, 10), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
3126 {"psq_lx", XW (4, 6,0), XW_MASK, PPCPS, 0, {FRT,RA,RB,PSWM,PSQM}},
3127 {"vmrghb", VX (4, 12), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
3128 {"psq_stx", XW (4, 7,0), XW_MASK, PPCPS, 0, {FRS,RA,RB,PSWM,PSQM}},
3129 {"vpkuhum", VX (4, 14), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
3130 {"mulhhwu", XRC(4, 8,0), X_MASK, MULHW, 0, {RT, RA, RB}},
3131 {"mulhhwu.", XRC(4, 8,1), X_MASK, MULHW, 0, {RT, RA, RB}},
3132 {"ps_sum0", A (4, 10,0), A_MASK, PPCPS, 0, {FRT, FRA, FRC, FRB}},
3133 {"ps_sum0.", A (4, 10,1), A_MASK, PPCPS, 0, {FRT, FRA, FRC, FRB}},
3134 {"ps_sum1", A (4, 11,0), A_MASK, PPCPS, 0, {FRT, FRA, FRC, FRB}},
3135 {"ps_sum1.", A (4, 11,1), A_MASK, PPCPS, 0, {FRT, FRA, FRC, FRB}},
3136 {"ps_muls0", A (4, 12,0), AFRB_MASK, PPCPS, 0, {FRT, FRA, FRC}},
3137 {"machhwu", XO (4, 12,0,0), XO_MASK, MULHW, 0, {RT, RA, RB}},
3138 {"ps_muls0.", A (4, 12,1), AFRB_MASK, PPCPS, 0, {FRT, FRA, FRC}},
3139 {"machhwu.", XO (4, 12,0,1), XO_MASK, MULHW, 0, {RT, RA, RB}},
3140 {"ps_muls1", A (4, 13,0), AFRB_MASK, PPCPS, 0, {FRT, FRA, FRC}},
3141 {"ps_muls1.", A (4, 13,1), AFRB_MASK, PPCPS, 0, {FRT, FRA, FRC}},
3142 {"ps_madds0", A (4, 14,0), A_MASK, PPCPS, 0, {FRT, FRA, FRC, FRB}},
3143 {"ps_madds0.", A (4, 14,1), A_MASK, PPCPS, 0, {FRT, FRA, FRC, FRB}},
3144 {"ps_madds1", A (4, 15,0), A_MASK, PPCPS, 0, {FRT, FRA, FRC, FRB}},
3145 {"ps_madds1.", A (4, 15,1), A_MASK, PPCPS, 0, {FRT, FRA, FRC, FRB}},
3146 {"vmhaddshs", VXA(4, 32), VXA_MASK, PPCVEC, 0, {VD, VA, VB, VC}},
3147 {"vmhraddshs", VXA(4, 33), VXA_MASK, PPCVEC, 0, {VD, VA, VB, VC}},
3148 {"vmladduhm", VXA(4, 34), VXA_MASK, PPCVEC, 0, {VD, VA, VB, VC}},
3149 {"vmsumudm", VXA(4, 35), VXA_MASK, PPCVEC3, 0, {VD, VA, VB, VC}},
3150 {"ps_div", A (4, 18,0), AFRC_MASK, PPCPS, 0, {FRT, FRA, FRB}},
3151 {"vmsumubm", VXA(4, 36), VXA_MASK, PPCVEC, 0, {VD, VA, VB, VC}},
3152 {"ps_div.", A (4, 18,1), AFRC_MASK, PPCPS, 0, {FRT, FRA, FRB}},
3153 {"vmsummbm", VXA(4, 37), VXA_MASK, PPCVEC, 0, {VD, VA, VB, VC}},
3154 {"vmsumuhm", VXA(4, 38), VXA_MASK, PPCVEC, 0, {VD, VA, VB, VC}},
3155 {"vmsumuhs", VXA(4, 39), VXA_MASK, PPCVEC, 0, {VD, VA, VB, VC}},
3156 {"ps_sub", A (4, 20,0), AFRC_MASK, PPCPS, 0, {FRT, FRA, FRB}},
3157 {"vmsumshm", VXA(4, 40), VXA_MASK, PPCVEC, 0, {VD, VA, VB, VC}},
3158 {"ps_sub.", A (4, 20,1), AFRC_MASK, PPCPS, 0, {FRT, FRA, FRB}},
3159 {"vmsumshs", VXA(4, 41), VXA_MASK, PPCVEC, 0, {VD, VA, VB, VC}},
3160 {"ps_add", A (4, 21,0), AFRC_MASK, PPCPS, 0, {FRT, FRA, FRB}},
3161 {"vsel", VXA(4, 42), VXA_MASK, PPCVEC, 0, {VD, VA, VB, VC}},
3162 {"ps_add.", A (4, 21,1), AFRC_MASK, PPCPS, 0, {FRT, FRA, FRB}},
3163 {"vperm", VXA(4, 43), VXA_MASK, PPCVEC, 0, {VD, VA, VB, VC}},
3164 {"vsldoi", VXA(4, 44), VXASHB_MASK, PPCVEC, 0, {VD, VA, VB, SHB}},
3165 {"vpermxor", VXA(4, 45), VXA_MASK, PPCVEC2, 0, {VD, VA, VB, VC}},
3166 {"ps_sel", A (4, 23,0), A_MASK, PPCPS, 0, {FRT, FRA, FRC, FRB}},
3167 {"vmaddfp", VXA(4, 46), VXA_MASK, PPCVEC, 0, {VD, VA, VC, VB}},
3168 {"ps_sel.", A (4, 23,1), A_MASK, PPCPS, 0, {FRT, FRA, FRC, FRB}},
3169 {"vnmsubfp", VXA(4, 47), VXA_MASK, PPCVEC, 0, {VD, VA, VC, VB}},
3170 {"ps_res", A (4, 24,0), AFRAFRC_MASK, PPCPS, 0, {FRT, FRB}},
3171 {"maddhd", VXA(4, 48), VXA_MASK, POWER9, 0, {RT, RA, RB, RC}},
3172 {"ps_res.", A (4, 24,1), AFRAFRC_MASK, PPCPS, 0, {FRT, FRB}},
3173 {"maddhdu", VXA(4, 49), VXA_MASK, POWER9, 0, {RT, RA, RB, RC}},
3174 {"ps_mul", A (4, 25,0), AFRB_MASK, PPCPS, 0, {FRT, FRA, FRC}},
3175 {"ps_mul.", A (4, 25,1), AFRB_MASK, PPCPS, 0, {FRT, FRA, FRC}},
3176 {"maddld", VXA(4, 51), VXA_MASK, POWER9, 0, {RT, RA, RB, RC}},
3177 {"ps_rsqrte", A (4, 26,0), AFRAFRC_MASK, PPCPS, 0, {FRT, FRB}},
3178 {"ps_rsqrte.", A (4, 26,1), AFRAFRC_MASK, PPCPS, 0, {FRT, FRB}},
3179 {"ps_msub", A (4, 28,0), A_MASK, PPCPS, 0, {FRT, FRA, FRC, FRB}},
3180 {"ps_msub.", A (4, 28,1), A_MASK, PPCPS, 0, {FRT, FRA, FRC, FRB}},
3181 {"ps_madd", A (4, 29,0), A_MASK, PPCPS, 0, {FRT, FRA, FRC, FRB}},
3182 {"ps_madd.", A (4, 29,1), A_MASK, PPCPS, 0, {FRT, FRA, FRC, FRB}},
3183 {"vpermr", VXA(4, 59), VXA_MASK, PPCVEC3, 0, {VD, VA, VB, VC}},
3184 {"ps_nmsub", A (4, 30,0), A_MASK, PPCPS, 0, {FRT, FRA, FRC, FRB}},
3185 {"vaddeuqm", VXA(4, 60), VXA_MASK, PPCVEC2, 0, {VD, VA, VB, VC}},
3186 {"ps_nmsub.", A (4, 30,1), A_MASK, PPCPS, 0, {FRT, FRA, FRC, FRB}},
3187 {"vaddecuq", VXA(4, 61), VXA_MASK, PPCVEC2, 0, {VD, VA, VB, VC}},
3188 {"ps_nmadd", A (4, 31,0), A_MASK, PPCPS, 0, {FRT, FRA, FRC, FRB}},
3189 {"vsubeuqm", VXA(4, 62), VXA_MASK, PPCVEC2, 0, {VD, VA, VB, VC}},
3190 {"ps_nmadd.", A (4, 31,1), A_MASK, PPCPS, 0, {FRT, FRA, FRC, FRB}},
3191 {"vsubecuq", VXA(4, 63), VXA_MASK, PPCVEC2, 0, {VD, VA, VB, VC}},
3192 {"ps_cmpo0", X (4, 32), XBF_MASK, PPCPS, 0, {BF, FRA, FRB}},
3193 {"vadduhm", VX (4, 64), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
3194 {"vmul10ecuq", VX (4, 65), VX_MASK, PPCVEC3, 0, {VD, VA, VB}},
3195 {"vmaxuh", VX (4, 66), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
3196 {"vrlh", VX (4, 68), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
3197 {"vcmpequh", VXR(4, 70,0), VXR_MASK, PPCVEC, 0, {VD, VA, VB}},
3198 {"vcmpneh", VXR(4, 71,0), VXR_MASK, PPCVEC3, 0, {VD, VA, VB}},
3199 {"vmulouh", VX (4, 72), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
3200 {"vsubfp", VX (4, 74), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
3201 {"psq_lux", XW (4, 38,0), XW_MASK, PPCPS, 0, {FRT,RA,RB,PSWM,PSQM}},
3202 {"vmrghh", VX (4, 76), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
3203 {"psq_stux", XW (4, 39,0), XW_MASK, PPCPS, 0, {FRS,RA,RB,PSWM,PSQM}},
3204 {"vpkuwum", VX (4, 78), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
3205 {"ps_neg", XRC(4, 40,0), XRA_MASK, PPCPS, 0, {FRT, FRB}},
3206 {"mulhhw", XRC(4, 40,0), X_MASK, MULHW, 0, {RT, RA, RB}},
3207 {"ps_neg.", XRC(4, 40,1), XRA_MASK, PPCPS, 0, {FRT, FRB}},
3208 {"mulhhw.", XRC(4, 40,1), X_MASK, MULHW, 0, {RT, RA, RB}},
3209 {"machhw", XO (4, 44,0,0), XO_MASK, MULHW, 0, {RT, RA, RB}},
3210 {"machhw.", XO (4, 44,0,1), XO_MASK, MULHW, 0, {RT, RA, RB}},
3211 {"nmachhw", XO (4, 46,0,0), XO_MASK, MULHW, 0, {RT, RA, RB}},
3212 {"nmachhw.", XO (4, 46,0,1), XO_MASK, MULHW, 0, {RT, RA, RB}},
3213 {"ps_cmpu1", X (4, 64), XBF_MASK, PPCPS, 0, {BF, FRA, FRB}},
3214 {"vadduwm", VX (4, 128), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
3215 {"vmaxuw", VX (4, 130), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
3216 {"vrlw", VX (4, 132), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
3217 {"vrlwmi", VX (4, 133), VX_MASK, PPCVEC3, 0, {VD, VA, VB}},
3218 {"vcmpequw", VXR(4, 134,0), VXR_MASK, PPCVEC, 0, {VD, VA, VB}},
3219 {"vcmpnew", VXR(4, 135,0), VXR_MASK, PPCVEC3, 0, {VD, VA, VB}},
3220 {"vmulouw", VX (4, 136), VX_MASK, PPCVEC2, 0, {VD, VA, VB}},
3221 {"vmuluwm", VX (4, 137), VX_MASK, PPCVEC2, 0, {VD, VA, VB}},
3222 {"vmrghw", VX (4, 140), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
3223 {"vpkuhus", VX (4, 142), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
3224 {"ps_mr", XRC(4, 72,0), XRA_MASK, PPCPS, 0, {FRT, FRB}},
3225 {"ps_mr.", XRC(4, 72,1), XRA_MASK, PPCPS, 0, {FRT, FRB}},
3226 {"machhwsu", XO (4, 76,0,0), XO_MASK, MULHW, 0, {RT, RA, RB}},
3227 {"machhwsu.", XO (4, 76,0,1), XO_MASK, MULHW, 0, {RT, RA, RB}},
3228 {"ps_cmpo1", X (4, 96), XBF_MASK, PPCPS, 0, {BF, FRA, FRB}},
3229 {"vaddudm", VX (4, 192), VX_MASK, PPCVEC2, 0, {VD, VA, VB}},
3230 {"vmaxud", VX (4, 194), VX_MASK, PPCVEC2, 0, {VD, VA, VB}},
3231 {"vrld", VX (4, 196), VX_MASK, PPCVEC2, 0, {VD, VA, VB}},
3232 {"vrldmi", VX (4, 197), VX_MASK, PPCVEC3, 0, {VD, VA, VB}},
3233 {"vcmpeqfp", VXR(4, 198,0), VXR_MASK, PPCVEC, 0, {VD, VA, VB}},
3234 {"vcmpequd", VXR(4, 199,0), VXR_MASK, PPCVEC2, 0, {VD, VA, VB}},
3235 {"vpkuwus", VX (4, 206), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
3236 {"machhws", XO (4, 108,0,0), XO_MASK, MULHW, 0, {RT, RA, RB}},
3237 {"machhws.", XO (4, 108,0,1), XO_MASK, MULHW, 0, {RT, RA, RB}},
3238 {"nmachhws", XO (4, 110,0,0), XO_MASK, MULHW, 0, {RT, RA, RB}},
3239 {"nmachhws.", XO (4, 110,0,1), XO_MASK, MULHW, 0, {RT, RA, RB}},
3240 {"vadduqm", VX (4, 256), VX_MASK, PPCVEC2, 0, {VD, VA, VB}},
3241 {"vmaxsb", VX (4, 258), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
3242 {"vslb", VX (4, 260), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
3243 {"vcmpnezb", VXR(4, 263,0), VXR_MASK, PPCVEC3, 0, {VD, VA, VB}},
3244 {"vmulosb", VX (4, 264), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
3245 {"vrefp", VX (4, 266), VXVA_MASK, PPCVEC, 0, {VD, VB}},
3246 {"vmrglb", VX (4, 268), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
3247 {"vpkshus", VX (4, 270), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
3248 {"ps_nabs", XRC(4, 136,0), XRA_MASK, PPCPS, 0, {FRT, FRB}},
3249 {"mulchwu", XRC(4, 136,0), X_MASK, MULHW, 0, {RT, RA, RB}},
3250 {"ps_nabs.", XRC(4, 136,1), XRA_MASK, PPCPS, 0, {FRT, FRB}},
3251 {"mulchwu.", XRC(4, 136,1), X_MASK, MULHW, 0, {RT, RA, RB}},
3252 {"macchwu", XO (4, 140,0,0), XO_MASK, MULHW, 0, {RT, RA, RB}},
3253 {"macchwu.", XO (4, 140,0,1), XO_MASK, MULHW, 0, {RT, RA, RB}},
3254 {"vaddcuq", VX (4, 320), VX_MASK, PPCVEC2, 0, {VD, VA, VB}},
3255 {"vmaxsh", VX (4, 322), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
3256 {"vslh", VX (4, 324), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
3257 {"vcmpnezh", VXR(4, 327,0), VXR_MASK, PPCVEC3, 0, {VD, VA, VB}},
3258 {"vmulosh", VX (4, 328), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
3259 {"vrsqrtefp", VX (4, 330), VXVA_MASK, PPCVEC, 0, {VD, VB}},
3260 {"vmrglh", VX (4, 332), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
3261 {"vpkswus", VX (4, 334), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
3262 {"mulchw", XRC(4, 168,0), X_MASK, MULHW, 0, {RT, RA, RB}},
3263 {"mulchw.", XRC(4, 168,1), X_MASK, MULHW, 0, {RT, RA, RB}},
3264 {"macchw", XO (4, 172,0,0), XO_MASK, MULHW, 0, {RT, RA, RB}},
3265 {"macchw.", XO (4, 172,0,1), XO_MASK, MULHW, 0, {RT, RA, RB}},
3266 {"nmacchw", XO (4, 174,0,0), XO_MASK, MULHW, 0, {RT, RA, RB}},
3267 {"nmacchw.", XO (4, 174,0,1), XO_MASK, MULHW, 0, {RT, RA, RB}},
3268 {"vaddcuw", VX (4, 384), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
3269 {"vmaxsw", VX (4, 386), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
3270 {"vslw", VX (4, 388), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
3271 {"vrlwnm", VX (4, 389), VX_MASK, PPCVEC3, 0, {VD, VA, VB}},
3272 {"vcmpnezw", VXR(4, 391,0), VXR_MASK, PPCVEC3, 0, {VD, VA, VB}},
3273 {"vmulosw", VX (4, 392), VX_MASK, PPCVEC2, 0, {VD, VA, VB}},
3274 {"vexptefp", VX (4, 394), VXVA_MASK, PPCVEC, 0, {VD, VB}},
3275 {"vmrglw", VX (4, 396), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
3276 {"vpkshss", VX (4, 398), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
3277 {"macchwsu", XO (4, 204,0,0), XO_MASK, MULHW, 0, {RT, RA, RB}},
3278 {"macchwsu.", XO (4, 204,0,1), XO_MASK, MULHW, 0, {RT, RA, RB}},
3279 {"vmaxsd", VX (4, 450), VX_MASK, PPCVEC2, 0, {VD, VA, VB}},
3280 {"vsl", VX (4, 452), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
3281 {"vrldnm", VX (4, 453), VX_MASK, PPCVEC3, 0, {VD, VA, VB}},
3282 {"vcmpgefp", VXR(4, 454,0), VXR_MASK, PPCVEC, 0, {VD, VA, VB}},
3283 {"vlogefp", VX (4, 458), VXVA_MASK, PPCVEC, 0, {VD, VB}},
3284 {"vpkswss", VX (4, 462), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
3285 {"macchws", XO (4, 236,0,0), XO_MASK, MULHW, 0, {RT, RA, RB}},
3286 {"macchws.", XO (4, 236,0,1), XO_MASK, MULHW, 0, {RT, RA, RB}},
3287 {"nmacchws", XO (4, 238,0,0), XO_MASK, MULHW, 0, {RT, RA, RB}},
3288 {"nmacchws.", XO (4, 238,0,1), XO_MASK, MULHW, 0, {RT, RA, RB}},
3289 {"evaddw", VX (4, 512), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3290 {"vaddubs", VX (4, 512), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
3291 {"vmul10uq", VX (4, 513), VXVB_MASK, PPCVEC3, 0, {VD, VA}},
3292 {"evaddiw", VX (4, 514), VX_MASK, PPCSPE, 0, {RS, RB, UIMM}},
3293 {"vminub", VX (4, 514), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
3294 {"evsubfw", VX (4, 516), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3295 {"evsubw", VX (4, 516), VX_MASK, PPCSPE, 0, {RS, RB, RA}},
3296 {"vsrb", VX (4, 516), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
3297 {"evsubifw", VX (4, 518), VX_MASK, PPCSPE, 0, {RS, UIMM, RB}},
3298 {"evsubiw", VX (4, 518), VX_MASK, PPCSPE, 0, {RS, RB, UIMM}},
3299 {"vcmpgtub", VXR(4, 518,0), VXR_MASK, PPCVEC, 0, {VD, VA, VB}},
3300 {"evabs", VX (4, 520), VX_MASK, PPCSPE, 0, {RS, RA}},
3301 {"vmuleub", VX (4, 520), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
3302 {"evneg", VX (4, 521), VX_MASK, PPCSPE, 0, {RS, RA}},
3303 {"evextsb", VX (4, 522), VX_MASK, PPCSPE, 0, {RS, RA}},
3304 {"vrfin", VX (4, 522), VXVA_MASK, PPCVEC, 0, {VD, VB}},
3305 {"evextsh", VX (4, 523), VX_MASK, PPCSPE, 0, {RS, RA}},
3306 {"evrndw", VX (4, 524), VX_MASK, PPCSPE, 0, {RS, RA}},
3307 {"vspltb", VX (4, 524), VXUIMM4_MASK, PPCVEC, 0, {VD, VB, UIMM4}},
3308 {"vextractub", VX (4, 525), VXUIMM4_MASK, PPCVEC3, 0, {VD, VB, UIMM4}},
3309 {"evcntlzw", VX (4, 525), VX_MASK, PPCSPE, 0, {RS, RA}},
3310 {"evcntlsw", VX (4, 526), VX_MASK, PPCSPE, 0, {RS, RA}},
3311 {"vupkhsb", VX (4, 526), VXVA_MASK, PPCVEC, 0, {VD, VB}},
3312 {"brinc", VX (4, 527), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3313 {"ps_abs", XRC(4, 264,0), XRA_MASK, PPCPS, 0, {FRT, FRB}},
3314 {"ps_abs.", XRC(4, 264,1), XRA_MASK, PPCPS, 0, {FRT, FRB}},
3315 {"evand", VX (4, 529), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3316 {"evandc", VX (4, 530), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3317 {"evxor", VX (4, 534), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3318 {"evmr", VX (4, 535), VX_MASK, PPCSPE, 0, {RS, RA, BBA}},
3319 {"evor", VX (4, 535), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3320 {"evnor", VX (4, 536), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3321 {"evnot", VX (4, 536), VX_MASK, PPCSPE, 0, {RS, RA, BBA}},
3322 {"get", APU(4, 268,0), APU_RA_MASK, PPC405, 0, {RT, FSL}},
3323 {"eveqv", VX (4, 537), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3324 {"evorc", VX (4, 539), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3325 {"evnand", VX (4, 542), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3326 {"evsrwu", VX (4, 544), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3327 {"evsrws", VX (4, 545), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3328 {"evsrwiu", VX (4, 546), VX_MASK, PPCSPE, 0, {RS, RA, EVUIMM}},
3329 {"evsrwis", VX (4, 547), VX_MASK, PPCSPE, 0, {RS, RA, EVUIMM}},
3330 {"evslw", VX (4, 548), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3331 {"evslwi", VX (4, 550), VX_MASK, PPCSPE, 0, {RS, RA, EVUIMM}},
3332 {"evrlw", VX (4, 552), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3333 {"evsplati", VX (4, 553), VX_MASK, PPCSPE, 0, {RS, SIMM}},
3334 {"evrlwi", VX (4, 554), VX_MASK, PPCSPE, 0, {RS, RA, EVUIMM}},
3335 {"evsplatfi", VX (4, 555), VX_MASK, PPCSPE, 0, {RS, SIMM}},
3336 {"evmergehi", VX (4, 556), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3337 {"evmergelo", VX (4, 557), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3338 {"evmergehilo", VX (4, 558), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3339 {"evmergelohi", VX (4, 559), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3340 {"evcmpgtu", VX (4, 560), VX_MASK, PPCSPE, 0, {CRFD, RA, RB}},
3341 {"evcmpgts", VX (4, 561), VX_MASK, PPCSPE, 0, {CRFD, RA, RB}},
3342 {"evcmpltu", VX (4, 562), VX_MASK, PPCSPE, 0, {CRFD, RA, RB}},
3343 {"evcmplts", VX (4, 563), VX_MASK, PPCSPE, 0, {CRFD, RA, RB}},
3344 {"evcmpeq", VX (4, 564), VX_MASK, PPCSPE, 0, {CRFD, RA, RB}},
3345 {"cget", APU(4, 284,0), APU_RA_MASK, PPC405, 0, {RT, FSL}},
3346 {"vadduhs", VX (4, 576), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
3347 {"vmul10euq", VX (4, 577), VX_MASK, PPCVEC3, 0, {VD, VA, VB}},
3348 {"vminuh", VX (4, 578), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
3349 {"vsrh", VX (4, 580), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
3350 {"vcmpgtuh", VXR(4, 582,0), VXR_MASK, PPCVEC, 0, {VD, VA, VB}},
3351 {"vmuleuh", VX (4, 584), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
3352 {"vrfiz", VX (4, 586), VXVA_MASK, PPCVEC, 0, {VD, VB}},
3353 {"vsplth", VX (4, 588), VXUIMM3_MASK, PPCVEC, 0, {VD, VB, UIMM3}},
3354 {"vextractuh", VX (4, 589), VXUIMM4_MASK, PPCVEC3, 0, {VD, VB, UIMM4}},
3355 {"vupkhsh", VX (4, 590), VXVA_MASK, PPCVEC, 0, {VD, VB}},
3356 {"nget", APU(4, 300,0), APU_RA_MASK, PPC405, 0, {RT, FSL}},
3357 {"evsel", EVSEL(4,79), EVSEL_MASK, PPCSPE, 0, {RS, RA, RB, CRFS}},
3358 {"ncget", APU(4, 316,0), APU_RA_MASK, PPC405, 0, {RT, FSL}},
3359 {"evfsadd", VX (4, 640), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3360 {"vadduws", VX (4, 640), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
3361 {"evfssub", VX (4, 641), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3362 {"vminuw", VX (4, 642), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
3363 {"evfsabs", VX (4, 644), VX_MASK, PPCSPE, 0, {RS, RA}},
3364 {"vsrw", VX (4, 644), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
3365 {"evfsnabs", VX (4, 645), VX_MASK, PPCSPE, 0, {RS, RA}},
3366 {"evfsneg", VX (4, 646), VX_MASK, PPCSPE, 0, {RS, RA}},
3367 {"vcmpgtuw", VXR(4, 646,0), VXR_MASK, PPCVEC, 0, {VD, VA, VB}},
3368 {"vmuleuw", VX (4, 648), VX_MASK, PPCVEC2, 0, {VD, VA, VB}},
3369 {"evfsmul", VX (4, 648), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3370 {"evfsdiv", VX (4, 649), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3371 {"vrfip", VX (4, 650), VXVA_MASK, PPCVEC, 0, {VD, VB}},
3372 {"evfscmpgt", VX (4, 652), VX_MASK, PPCSPE, 0, {CRFD, RA, RB}},
3373 {"vspltw", VX (4, 652), VXUIMM2_MASK, PPCVEC, 0, {VD, VB, UIMM2}},
3374 {"vextractuw", VX (4, 653), VXUIMM4_MASK, PPCVEC3, 0, {VD, VB, UIMM4}},
3375 {"evfscmplt", VX (4, 653), VX_MASK, PPCSPE, 0, {CRFD, RA, RB}},
3376 {"evfscmpeq", VX (4, 654), VX_MASK, PPCSPE, 0, {CRFD, RA, RB}},
3377 {"vupklsb", VX (4, 654), VXVA_MASK, PPCVEC, 0, {VD, VB}},
3378 {"evfscfui", VX (4, 656), VX_MASK, PPCSPE, 0, {RS, RB}},
3379 {"evfscfsi", VX (4, 657), VX_MASK, PPCSPE, 0, {RS, RB}},
3380 {"evfscfuf", VX (4, 658), VX_MASK, PPCSPE, 0, {RS, RB}},
3381 {"evfscfsf", VX (4, 659), VX_MASK, PPCSPE, 0, {RS, RB}},
3382 {"evfsctui", VX (4, 660), VX_MASK, PPCSPE, 0, {RS, RB}},
3383 {"evfsctsi", VX (4, 661), VX_MASK, PPCSPE, 0, {RS, RB}},
3384 {"evfsctuf", VX (4, 662), VX_MASK, PPCSPE, 0, {RS, RB}},
3385 {"evfsctsf", VX (4, 663), VX_MASK, PPCSPE, 0, {RS, RB}},
3386 {"evfsctuiz", VX (4, 664), VX_MASK, PPCSPE, 0, {RS, RB}},
3387 {"put", APU(4, 332,0), APU_RT_MASK, PPC405, 0, {RA, FSL}},
3388 {"evfsctsiz", VX (4, 666), VX_MASK, PPCSPE, 0, {RS, RB}},
3389 {"evfststgt", VX (4, 668), VX_MASK, PPCSPE, 0, {CRFD, RA, RB}},
3390 {"evfststlt", VX (4, 669), VX_MASK, PPCSPE, 0, {CRFD, RA, RB}},
3391 {"evfststeq", VX (4, 670), VX_MASK, PPCSPE, 0, {CRFD, RA, RB}},
3392 {"cput", APU(4, 348,0), APU_RT_MASK, PPC405, 0, {RA, FSL}},
3393 {"efsadd", VX (4, 704), VX_MASK, PPCEFS, 0, {RS, RA, RB}},
3394 {"efssub", VX (4, 705), VX_MASK, PPCEFS, 0, {RS, RA, RB}},
3395 {"vminud", VX (4, 706), VX_MASK, PPCVEC2, 0, {VD, VA, VB}},
3396 {"efsabs", VX (4, 708), VX_MASK, PPCEFS, 0, {RS, RA}},
3397 {"vsr", VX (4, 708), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
3398 {"efsnabs", VX (4, 709), VX_MASK, PPCEFS, 0, {RS, RA}},
3399 {"efsneg", VX (4, 710), VX_MASK, PPCEFS, 0, {RS, RA}},
3400 {"vcmpgtfp", VXR(4, 710,0), VXR_MASK, PPCVEC, 0, {VD, VA, VB}},
3401 {"vcmpgtud", VXR(4, 711,0), VXR_MASK, PPCVEC2, 0, {VD, VA, VB}},
3402 {"efsmul", VX (4, 712), VX_MASK, PPCEFS, 0, {RS, RA, RB}},
3403 {"efsdiv", VX (4, 713), VX_MASK, PPCEFS, 0, {RS, RA, RB}},
3404 {"vrfim", VX (4, 714), VXVA_MASK, PPCVEC, 0, {VD, VB}},
3405 {"efscmpgt", VX (4, 716), VX_MASK, PPCEFS, 0, {CRFD, RA, RB}},
3406 {"vextractd", VX (4, 717), VXUIMM4_MASK, PPCVEC3, 0, {VD, VB, UIMM4}},
3407 {"efscmplt", VX (4, 717), VX_MASK, PPCEFS, 0, {CRFD, RA, RB}},
3408 {"efscmpeq", VX (4, 718), VX_MASK, PPCEFS, 0, {CRFD, RA, RB}},
3409 {"vupklsh", VX (4, 718), VXVA_MASK, PPCVEC, 0, {VD, VB}},
3410 {"efscfd", VX (4, 719), VX_MASK, PPCEFS, 0, {RS, RB}},
3411 {"efscfui", VX (4, 720), VX_MASK, PPCEFS, 0, {RS, RB}},
3412 {"efscfsi", VX (4, 721), VX_MASK, PPCEFS, 0, {RS, RB}},
3413 {"efscfuf", VX (4, 722), VX_MASK, PPCEFS, 0, {RS, RB}},
3414 {"efscfsf", VX (4, 723), VX_MASK, PPCEFS, 0, {RS, RB}},
3415 {"efsctui", VX (4, 724), VX_MASK, PPCEFS, 0, {RS, RB}},
3416 {"efsctsi", VX (4, 725), VX_MASK, PPCEFS, 0, {RS, RB}},
3417 {"efsctuf", VX (4, 726), VX_MASK, PPCEFS, 0, {RS, RB}},
3418 {"efsctsf", VX (4, 727), VX_MASK, PPCEFS, 0, {RS, RB}},
3419 {"efsctuiz", VX (4, 728), VX_MASK, PPCEFS, 0, {RS, RB}},
3420 {"nput", APU(4, 364,0), APU_RT_MASK, PPC405, 0, {RA, FSL}},
3421 {"efsctsiz", VX (4, 730), VX_MASK, PPCEFS, 0, {RS, RB}},
3422 {"efststgt", VX (4, 732), VX_MASK, PPCEFS, 0, {CRFD, RA, RB}},
3423 {"efststlt", VX (4, 733), VX_MASK, PPCEFS, 0, {CRFD, RA, RB}},
3424 {"efststeq", VX (4, 734), VX_MASK, PPCEFS, 0, {CRFD, RA, RB}},
3425 {"efdadd", VX (4, 736), VX_MASK, PPCEFS, 0, {RS, RA, RB}},
3426 {"efdsub", VX (4, 737), VX_MASK, PPCEFS, 0, {RS, RA, RB}},
3427 {"efdcfuid", VX (4, 738), VX_MASK, PPCEFS, 0, {RS, RB}},
3428 {"efdcfsid", VX (4, 739), VX_MASK, PPCEFS, 0, {RS, RB}},
3429 {"efdabs", VX (4, 740), VX_MASK, PPCEFS, 0, {RS, RA}},
3430 {"efdnabs", VX (4, 741), VX_MASK, PPCEFS, 0, {RS, RA}},
3431 {"efdneg", VX (4, 742), VX_MASK, PPCEFS, 0, {RS, RA}},
3432 {"efdmul", VX (4, 744), VX_MASK, PPCEFS, 0, {RS, RA, RB}},
3433 {"efddiv", VX (4, 745), VX_MASK, PPCEFS, 0, {RS, RA, RB}},
3434 {"efdctuidz", VX (4, 746), VX_MASK, PPCEFS, 0, {RS, RB}},
3435 {"efdctsidz", VX (4, 747), VX_MASK, PPCEFS, 0, {RS, RB}},
3436 {"efdcmpgt", VX (4, 748), VX_MASK, PPCEFS, 0, {CRFD, RA, RB}},
3437 {"efdcmplt", VX (4, 749), VX_MASK, PPCEFS, 0, {CRFD, RA, RB}},
3438 {"efdcmpeq", VX (4, 750), VX_MASK, PPCEFS, 0, {CRFD, RA, RB}},
3439 {"efdcfs", VX (4, 751), VX_MASK, PPCEFS, 0, {RS, RB}},
3440 {"efdcfui", VX (4, 752), VX_MASK, PPCEFS, 0, {RS, RB}},
3441 {"efdcfsi", VX (4, 753), VX_MASK, PPCEFS, 0, {RS, RB}},
3442 {"efdcfuf", VX (4, 754), VX_MASK, PPCEFS, 0, {RS, RB}},
3443 {"efdcfsf", VX (4, 755), VX_MASK, PPCEFS, 0, {RS, RB}},
3444 {"efdctui", VX (4, 756), VX_MASK, PPCEFS, 0, {RS, RB}},
3445 {"efdctsi", VX (4, 757), VX_MASK, PPCEFS, 0, {RS, RB}},
3446 {"efdctuf", VX (4, 758), VX_MASK, PPCEFS, 0, {RS, RB}},
3447 {"efdctsf", VX (4, 759), VX_MASK, PPCEFS, 0, {RS, RB}},
3448 {"efdctuiz", VX (4, 760), VX_MASK, PPCEFS, 0, {RS, RB}},
3449 {"ncput", APU(4, 380,0), APU_RT_MASK, PPC405, 0, {RA, FSL}},
3450 {"efdctsiz", VX (4, 762), VX_MASK, PPCEFS, 0, {RS, RB}},
3451 {"efdtstgt", VX (4, 764), VX_MASK, PPCEFS, 0, {CRFD, RA, RB}},
3452 {"efdtstlt", VX (4, 765), VX_MASK, PPCEFS, 0, {CRFD, RA, RB}},
3453 {"efdtsteq", VX (4, 766), VX_MASK, PPCEFS, 0, {CRFD, RA, RB}},
3454 {"evlddx", VX (4, 768), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3455 {"vaddsbs", VX (4, 768), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
3456 {"evldd", VX (4, 769), VX_MASK, PPCSPE, 0, {RS, EVUIMM_8, RA}},
3457 {"evldwx", VX (4, 770), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3458 {"vminsb", VX (4, 770), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
3459 {"evldw", VX (4, 771), VX_MASK, PPCSPE, 0, {RS, EVUIMM_8, RA}},
3460 {"evldhx", VX (4, 772), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3461 {"vsrab", VX (4, 772), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
3462 {"evldh", VX (4, 773), VX_MASK, PPCSPE, 0, {RS, EVUIMM_8, RA}},
3463 {"vcmpgtsb", VXR(4, 774,0), VXR_MASK, PPCVEC, 0, {VD, VA, VB}},
3464 {"evlhhesplatx",VX (4, 776), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3465 {"vmulesb", VX (4, 776), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
3466 {"evlhhesplat", VX (4, 777), VX_MASK, PPCSPE, 0, {RS, EVUIMM_2, RA}},
3467 {"vcfux", VX (4, 778), VX_MASK, PPCVEC, 0, {VD, VB, UIMM}},
3468 {"vcuxwfp", VX (4, 778), VX_MASK, PPCVEC, 0, {VD, VB, UIMM}},
3469 {"evlhhousplatx",VX(4, 780), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3470 {"vspltisb", VX (4, 780), VXVB_MASK, PPCVEC, 0, {VD, SIMM}},
3471 {"vinsertb", VX (4, 781), VXUIMM4_MASK, PPCVEC3, 0, {VD, VB, UIMM4}},
3472 {"evlhhousplat",VX (4, 781), VX_MASK, PPCSPE, 0, {RS, EVUIMM_2, RA}},
3473 {"evlhhossplatx",VX(4, 782), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3474 {"vpkpx", VX (4, 782), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
3475 {"evlhhossplat",VX (4, 783), VX_MASK, PPCSPE, 0, {RS, EVUIMM_2, RA}},
3476 {"mullhwu", XRC(4, 392,0), X_MASK, MULHW, 0, {RT, RA, RB}},
3477 {"evlwhex", VX (4, 784), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3478 {"mullhwu.", XRC(4, 392,1), X_MASK, MULHW, 0, {RT, RA, RB}},
3479 {"evlwhe", VX (4, 785), VX_MASK, PPCSPE, 0, {RS, EVUIMM_4, RA}},
3480 {"evlwhoux", VX (4, 788), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3481 {"evlwhou", VX (4, 789), VX_MASK, PPCSPE, 0, {RS, EVUIMM_4, RA}},
3482 {"evlwhosx", VX (4, 790), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3483 {"evlwhos", VX (4, 791), VX_MASK, PPCSPE, 0, {RS, EVUIMM_4, RA}},
3484 {"maclhwu", XO (4, 396,0,0),XO_MASK, MULHW, 0, {RT, RA, RB}},
3485 {"evlwwsplatx", VX (4, 792), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3486 {"maclhwu.", XO (4, 396,0,1),XO_MASK, MULHW, 0, {RT, RA, RB}},
3487 {"evlwwsplat", VX (4, 793), VX_MASK, PPCSPE, 0, {RS, EVUIMM_4, RA}},
3488 {"evlwhsplatx", VX (4, 796), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3489 {"evlwhsplat", VX (4, 797), VX_MASK, PPCSPE, 0, {RS, EVUIMM_4, RA}},
3490 {"evstddx", VX (4, 800), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3491 {"evstdd", VX (4, 801), VX_MASK, PPCSPE, 0, {RS, EVUIMM_8, RA}},
3492 {"evstdwx", VX (4, 802), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3493 {"evstdw", VX (4, 803), VX_MASK, PPCSPE, 0, {RS, EVUIMM_8, RA}},
3494 {"evstdhx", VX (4, 804), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3495 {"evstdh", VX (4, 805), VX_MASK, PPCSPE, 0, {RS, EVUIMM_8, RA}},
3496 {"evstwhex", VX (4, 816), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3497 {"evstwhe", VX (4, 817), VX_MASK, PPCSPE, 0, {RS, EVUIMM_4, RA}},
3498 {"evstwhox", VX (4, 820), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3499 {"evstwho", VX (4, 821), VX_MASK, PPCSPE, 0, {RS, EVUIMM_4, RA}},
3500 {"evstwwex", VX (4, 824), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3501 {"evstwwe", VX (4, 825), VX_MASK, PPCSPE, 0, {RS, EVUIMM_4, RA}},
3502 {"evstwwox", VX (4, 828), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3503 {"evstwwo", VX (4, 829), VX_MASK, PPCSPE, 0, {RS, EVUIMM_4, RA}},
3504 {"vaddshs", VX (4, 832), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
3505 {"bcdcpsgn.", VX (4, 833), VX_MASK, PPCVEC3, 0, {VD, VA, VB}},
3506 {"vminsh", VX (4, 834), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
3507 {"vsrah", VX (4, 836), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
3508 {"vcmpgtsh", VXR(4, 838,0), VXR_MASK, PPCVEC, 0, {VD, VA, VB}},
3509 {"vmulesh", VX (4, 840), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
3510 {"vcfsx", VX (4, 842), VX_MASK, PPCVEC, 0, {VD, VB, UIMM}},
3511 {"vcsxwfp", VX (4, 842), VX_MASK, PPCVEC, 0, {VD, VB, UIMM}},
3512 {"vspltish", VX (4, 844), VXVB_MASK, PPCVEC, 0, {VD, SIMM}},
3513 {"vinserth", VX (4, 845), VXUIMM4_MASK, PPCVEC3, 0, {VD, VB, UIMM4}},
3514 {"vupkhpx", VX (4, 846), VXVA_MASK, PPCVEC, 0, {VD, VB}},
3515 {"mullhw", XRC(4, 424,0), X_MASK, MULHW, 0, {RT, RA, RB}},
3516 {"mullhw.", XRC(4, 424,1), X_MASK, MULHW, 0, {RT, RA, RB}},
3517 {"maclhw", XO (4, 428,0,0),XO_MASK, MULHW, 0, {RT, RA, RB}},
3518 {"maclhw.", XO (4, 428,0,1),XO_MASK, MULHW, 0, {RT, RA, RB}},
3519 {"nmaclhw", XO (4, 430,0,0),XO_MASK, MULHW, 0, {RT, RA, RB}},
3520 {"nmaclhw.", XO (4, 430,0,1),XO_MASK, MULHW, 0, {RT, RA, RB}},
3521 {"vaddsws", VX (4, 896), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
3522 {"vminsw", VX (4, 898), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
3523 {"vsraw", VX (4, 900), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
3524 {"vcmpgtsw", VXR(4, 902,0), VXR_MASK, PPCVEC, 0, {VD, VA, VB}},
3525 {"vmulesw", VX (4, 904), VX_MASK, PPCVEC2, 0, {VD, VA, VB}},
3526 {"vctuxs", VX (4, 906), VX_MASK, PPCVEC, 0, {VD, VB, UIMM}},
3527 {"vcfpuxws", VX (4, 906), VX_MASK, PPCVEC, 0, {VD, VB, UIMM}},
3528 {"vspltisw", VX (4, 908), VXVB_MASK, PPCVEC, 0, {VD, SIMM}},
3529 {"vinsertw", VX (4, 909), VXUIMM4_MASK, PPCVEC3, 0, {VD, VB, UIMM4}},
3530 {"maclhwsu", XO (4, 460,0,0), XO_MASK, MULHW, 0, {RT, RA, RB}},
3531 {"maclhwsu.", XO (4, 460,0,1), XO_MASK, MULHW, 0, {RT, RA, RB}},
3532 {"vminsd", VX (4, 962), VX_MASK, PPCVEC2, 0, {VD, VA, VB}},
3533 {"vsrad", VX (4, 964), VX_MASK, PPCVEC2, 0, {VD, VA, VB}},
3534 {"vcmpbfp", VXR(4, 966,0), VXR_MASK, PPCVEC, 0, {VD, VA, VB}},
3535 {"vcmpgtsd", VXR(4, 967,0), VXR_MASK, PPCVEC2, 0, {VD, VA, VB}},
3536 {"vctsxs", VX (4, 970), VX_MASK, PPCVEC, 0, {VD, VB, UIMM}},
3537 {"vcfpsxws", VX (4, 970), VX_MASK, PPCVEC, 0, {VD, VB, UIMM}},
3538 {"vinsertd", VX (4, 973), VXUIMM4_MASK, PPCVEC3, 0, {VD, VB, UIMM4}},
3539 {"vupklpx", VX (4, 974), VXVA_MASK, PPCVEC, 0, {VD, VB}},
3540 {"maclhws", XO (4, 492,0,0), XO_MASK, MULHW, 0, {RT, RA, RB}},
3541 {"maclhws.", XO (4, 492,0,1), XO_MASK, MULHW, 0, {RT, RA, RB}},
3542 {"nmaclhws", XO (4, 494,0,0), XO_MASK, MULHW, 0, {RT, RA, RB}},
3543 {"nmaclhws.", XO (4, 494,0,1), XO_MASK, MULHW, 0, {RT, RA, RB}},
3544 {"vsububm", VX (4,1024), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
3545 {"bcdadd.", VX (4,1025), VXPS_MASK, PPCVEC2, 0, {VD, VA, VB, PS}},
3546 {"vavgub", VX (4,1026), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
3547 {"vabsdub", VX (4,1027), VX_MASK, PPCVEC2, 0, {VD, VA, VB}},
3548 {"evmhessf", VX (4,1027), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3549 {"vand", VX (4,1028), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
3550 {"vcmpequb.", VXR(4, 6,1), VXR_MASK, PPCVEC, 0, {VD, VA, VB}},
3551 {"vcmpneb.", VXR(4, 7,1), VXR_MASK, PPCVEC3, 0, {VD, VA, VB}},
3552 {"udi0fcm.", APU(4, 515,0), APU_MASK, PPC405|PPC440, PPC476, {URT, URA, URB}},
3553 {"udi0fcm", APU(4, 515,1), APU_MASK, PPC405|PPC440, PPC476, {URT, URA, URB}},
3554 {"evmhossf", VX (4,1031), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3555 {"vpmsumb", VX (4,1032), VX_MASK, PPCVEC2, 0, {VD, VA, VB}},
3556 {"evmheumi", VX (4,1032), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3557 {"evmhesmi", VX (4,1033), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3558 {"vmaxfp", VX (4,1034), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
3559 {"evmhesmf", VX (4,1035), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3560 {"evmhoumi", VX (4,1036), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3561 {"vslo", VX (4,1036), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
3562 {"evmhosmi", VX (4,1037), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3563 {"evmhosmf", VX (4,1039), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3564 {"machhwuo", XO (4, 12,1,0), XO_MASK, MULHW, 0, {RT, RA, RB}},
3565 {"machhwuo.", XO (4, 12,1,1), XO_MASK, MULHW, 0, {RT, RA, RB}},
3566 {"ps_merge00", XOPS(4,528,0), XOPS_MASK, PPCPS, 0, {FRT, FRA, FRB}},
3567 {"ps_merge00.", XOPS(4,528,1), XOPS_MASK, PPCPS, 0, {FRT, FRA, FRB}},
3568 {"evmhessfa", VX (4,1059), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3569 {"evmhossfa", VX (4,1063), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3570 {"evmheumia", VX (4,1064), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3571 {"evmhesmia", VX (4,1065), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3572 {"evmhesmfa", VX (4,1067), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3573 {"evmhoumia", VX (4,1068), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3574 {"evmhosmia", VX (4,1069), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3575 {"evmhosmfa", VX (4,1071), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3576 {"vsubuhm", VX (4,1088), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
3577 {"bcdsub.", VX (4,1089), VXPS_MASK, PPCVEC2, 0, {VD, VA, VB, PS}},
3578 {"vavguh", VX (4,1090), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
3579 {"vabsduh", VX (4,1091), VX_MASK, PPCVEC2, 0, {VD, VA, VB}},
3580 {"vandc", VX (4,1092), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
3581 {"vcmpequh.", VXR(4, 70,1), VXR_MASK, PPCVEC, 0, {VD, VA, VB}},
3582 {"udi1fcm.", APU(4, 547,0), APU_MASK, PPC405|PPC440, PPC476, {URT, URA, URB}},
3583 {"udi1fcm", APU(4, 547,1), APU_MASK, PPC405|PPC440, PPC476, {URT, URA, URB}},
3584 {"vcmpneh.", VXR(4, 71,1), VXR_MASK, PPCVEC3, 0, {VD, VA, VB}},
3585 {"evmwhssf", VX (4,1095), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3586 {"vpmsumh", VX (4,1096), VX_MASK, PPCVEC2, 0, {VD, VA, VB}},
3587 {"evmwlumi", VX (4,1096), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3588 {"vminfp", VX (4,1098), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
3589 {"evmwhumi", VX (4,1100), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3590 {"vsro", VX (4,1100), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
3591 {"evmwhsmi", VX (4,1101), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3592 {"vpkudum", VX (4,1102), VX_MASK, PPCVEC2, 0, {VD, VA, VB}},
3593 {"evmwhsmf", VX (4,1103), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3594 {"evmwssf", VX (4,1107), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3595 {"machhwo", XO (4, 44,1,0), XO_MASK, MULHW, 0, {RT, RA, RB}},
3596 {"evmwumi", VX (4,1112), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3597 {"machhwo.", XO (4, 44,1,1), XO_MASK, MULHW, 0, {RT, RA, RB}},
3598 {"evmwsmi", VX (4,1113), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3599 {"evmwsmf", VX (4,1115), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3600 {"nmachhwo", XO (4, 46,1,0), XO_MASK, MULHW, 0, {RT, RA, RB}},
3601 {"nmachhwo.", XO (4, 46,1,1), XO_MASK, MULHW, 0, {RT, RA, RB}},
3602 {"ps_merge01", XOPS(4,560,0), XOPS_MASK, PPCPS, 0, {FRT, FRA, FRB}},
3603 {"ps_merge01.", XOPS(4,560,1), XOPS_MASK, PPCPS, 0, {FRT, FRA, FRB}},
3604 {"evmwhssfa", VX (4,1127), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3605 {"evmwlumia", VX (4,1128), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3606 {"evmwhumia", VX (4,1132), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3607 {"evmwhsmia", VX (4,1133), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3608 {"evmwhsmfa", VX (4,1135), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3609 {"evmwssfa", VX (4,1139), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3610 {"evmwumia", VX (4,1144), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3611 {"evmwsmia", VX (4,1145), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3612 {"evmwsmfa", VX (4,1147), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3613 {"vsubuwm", VX (4,1152), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
3614 {"bcdus.", VX (4,1153), VX_MASK, PPCVEC3, 0, {VD, VA, VB}},
3615 {"vavguw", VX (4,1154), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
3616 {"vabsduw", VX (4,1155), VX_MASK, PPCVEC2, 0, {VD, VA, VB}},
3617 {"vmr", VX (4,1156), VX_MASK, PPCVEC, 0, {VD, VA, VBA}},
3618 {"vor", VX (4,1156), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
3619 {"vcmpnew.", VXR(4, 135,1), VXR_MASK, PPCVEC3, 0, {VD, VA, VB}},
3620 {"vpmsumw", VX (4,1160), VX_MASK, PPCVEC2, 0, {VD, VA, VB}},
3621 {"vcmpequw.", VXR(4, 134,1), VXR_MASK, PPCVEC, 0, {VD, VA, VB}},
3622 {"udi2fcm.", APU(4, 579,0), APU_MASK, PPC405|PPC440, PPC476, {URT, URA, URB}},
3623 {"udi2fcm", APU(4, 579,1), APU_MASK, PPC405|PPC440, PPC476, {URT, URA, URB}},
3624 {"machhwsuo", XO (4, 76,1,0), XO_MASK, MULHW, 0, {RT, RA, RB}},
3625 {"machhwsuo.", XO (4, 76,1,1), XO_MASK, MULHW, 0, {RT, RA, RB}},
3626 {"ps_merge10", XOPS(4,592,0), XOPS_MASK, PPCPS, 0, {FRT, FRA, FRB}},
3627 {"ps_merge10.", XOPS(4,592,1), XOPS_MASK, PPCPS, 0, {FRT, FRA, FRB}},
3628 {"vsubudm", VX (4,1216), VX_MASK, PPCVEC2, 0, {VD, VA, VB}},
3629 {"evaddusiaaw", VX (4,1216), VX_MASK, PPCSPE, 0, {RS, RA}},
3630 {"bcds.", VX (4,1217), VXPS_MASK, PPCVEC3, 0, {VD, VA, VB, PS}},
3631 {"evaddssiaaw", VX (4,1217), VX_MASK, PPCSPE, 0, {RS, RA}},
3632 {"evsubfusiaaw",VX (4,1218), VX_MASK, PPCSPE, 0, {RS, RA}},
3633 {"evsubfssiaaw",VX (4,1219), VX_MASK, PPCSPE, 0, {RS, RA}},
3634 {"evmra", VX (4,1220), VX_MASK, PPCSPE, 0, {RS, RA}},
3635 {"vxor", VX (4,1220), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
3636 {"evdivws", VX (4,1222), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3637 {"vcmpeqfp.", VXR(4, 198,1), VXR_MASK, PPCVEC, 0, {VD, VA, VB}},
3638 {"udi3fcm.", APU(4, 611,0), APU_MASK, PPC405|PPC440, PPC476, {URT, URA, URB}},
3639 {"vcmpequd.", VXR(4, 199,1), VXR_MASK, PPCVEC2, 0, {VD, VA, VB}},
3640 {"udi3fcm", APU(4, 611,1), APU_MASK, PPC405|PPC440, PPC476, {URT, URA, URB}},
3641 {"evdivwu", VX (4,1223), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3642 {"vpmsumd", VX (4,1224), VX_MASK, PPCVEC2, 0, {VD, VA, VB}},
3643 {"evaddumiaaw", VX (4,1224), VX_MASK, PPCSPE, 0, {RS, RA}},
3644 {"evaddsmiaaw", VX (4,1225), VX_MASK, PPCSPE, 0, {RS, RA}},
3645 {"evsubfumiaaw",VX (4,1226), VX_MASK, PPCSPE, 0, {RS, RA}},
3646 {"evsubfsmiaaw",VX (4,1227), VX_MASK, PPCSPE, 0, {RS, RA}},
3647 {"vpkudus", VX (4,1230), VX_MASK, PPCVEC2, 0, {VD, VA, VB}},
3648 {"machhwso", XO (4, 108,1,0), XO_MASK, MULHW, 0, {RT, RA, RB}},
3649 {"machhwso.", XO (4, 108,1,1), XO_MASK, MULHW, 0, {RT, RA, RB}},
3650 {"nmachhwso", XO (4, 110,1,0), XO_MASK, MULHW, 0, {RT, RA, RB}},
3651 {"nmachhwso.", XO (4, 110,1,1), XO_MASK, MULHW, 0, {RT, RA, RB}},
3652 {"ps_merge11", XOPS(4,624,0), XOPS_MASK, PPCPS, 0, {FRT, FRA, FRB}},
3653 {"ps_merge11.", XOPS(4,624,1), XOPS_MASK, PPCPS, 0, {FRT, FRA, FRB}},
3654 {"vsubuqm", VX (4,1280), VX_MASK, PPCVEC2, 0, {VD, VA, VB}},
3655 {"evmheusiaaw", VX (4,1280), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3656 {"bcdtrunc.", VX (4,1281), VXPS_MASK, PPCVEC3, 0, {VD, VA, VB, PS}},
3657 {"evmhessiaaw", VX (4,1281), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3658 {"vavgsb", VX (4,1282), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
3659 {"evmhessfaaw", VX (4,1283), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3660 {"evmhousiaaw", VX (4,1284), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3661 {"vnot", VX (4,1284), VX_MASK, PPCVEC, 0, {VD, VA, VBA}},
3662 {"vnor", VX (4,1284), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
3663 {"evmhossiaaw", VX (4,1285), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3664 {"udi4fcm.", APU(4, 643,0), APU_MASK, PPC405|PPC440, PPC476, {URT, URA, URB}},
3665 {"udi4fcm", APU(4, 643,1), APU_MASK, PPC405|PPC440, PPC476, {URT, URA, URB}},
3666 {"vcmpnezb.", VXR(4, 263,1), VXR_MASK, PPCVEC3, 0, {VD, VA, VB}},
3667 {"evmhossfaaw", VX (4,1287), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3668 {"evmheumiaaw", VX (4,1288), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3669 {"vcipher", VX (4,1288), VX_MASK, PPCVEC2, 0, {VD, VA, VB}},
3670 {"vcipherlast", VX (4,1289), VX_MASK, PPCVEC2, 0, {VD, VA, VB}},
3671 {"evmhesmiaaw", VX (4,1289), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3672 {"evmhesmfaaw", VX (4,1291), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3673 {"vgbbd", VX (4,1292), VXVA_MASK, PPCVEC2, 0, {VD, VB}},
3674 {"evmhoumiaaw", VX (4,1292), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3675 {"evmhosmiaaw", VX (4,1293), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3676 {"evmhosmfaaw", VX (4,1295), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3677 {"macchwuo", XO (4, 140,1,0), XO_MASK, MULHW, 0, {RT, RA, RB}},
3678 {"macchwuo.", XO (4, 140,1,1), XO_MASK, MULHW, 0, {RT, RA, RB}},
3679 {"evmhegumiaa", VX (4,1320), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3680 {"evmhegsmiaa", VX (4,1321), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3681 {"evmhegsmfaa", VX (4,1323), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3682 {"evmhogumiaa", VX (4,1324), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3683 {"evmhogsmiaa", VX (4,1325), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3684 {"evmhogsmfaa", VX (4,1327), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3685 {"vsubcuq", VX (4,1344), VX_MASK, PPCVEC2, 0, {VD, VA, VB}},
3686 {"evmwlusiaaw", VX (4,1344), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3687 {"bcdutrunc.", VX (4,1345), VX_MASK, PPCVEC3, 0, {VD, VA, VB}},
3688 {"evmwlssiaaw", VX (4,1345), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3689 {"vavgsh", VX (4,1346), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
3690 {"vorc", VX (4,1348), VX_MASK, PPCVEC2, 0, {VD, VA, VB}},
3691 {"udi5fcm.", APU(4, 675,0), APU_MASK, PPC405|PPC440, PPC476, {URT, URA, URB}},
3692 {"udi5fcm", APU(4, 675,1), APU_MASK, PPC405|PPC440, PPC476, {URT, URA, URB}},
3693 {"vcmpnezh.", VXR(4, 327,1), VXR_MASK, PPCVEC3, 0, {VD, VA, VB}},
3694 {"vncipher", VX (4,1352), VX_MASK, PPCVEC2, 0, {VD, VA, VB}},
3695 {"evmwlumiaaw", VX (4,1352), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3696 {"vncipherlast",VX (4,1353), VX_MASK, PPCVEC2, 0, {VD, VA, VB}},
3697 {"evmwlsmiaaw", VX (4,1353), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3698 {"vbpermq", VX (4,1356), VX_MASK, PPCVEC2, 0, {VD, VA, VB}},
3699 {"vpksdus", VX (4,1358), VX_MASK, PPCVEC2, 0, {VD, VA, VB}},
3700 {"evmwssfaa", VX (4,1363), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3701 {"macchwo", XO (4, 172,1,0), XO_MASK, MULHW, 0, {RT, RA, RB}},
3702 {"evmwumiaa", VX (4,1368), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3703 {"macchwo.", XO (4, 172,1,1), XO_MASK, MULHW, 0, {RT, RA, RB}},
3704 {"evmwsmiaa", VX (4,1369), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3705 {"evmwsmfaa", VX (4,1371), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3706 {"nmacchwo", XO (4, 174,1,0), XO_MASK, MULHW, 0, {RT, RA, RB}},
3707 {"nmacchwo.", XO (4, 174,1,1), XO_MASK, MULHW, 0, {RT, RA, RB}},
3708 {"evmheusianw", VX (4,1408), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3709 {"vsubcuw", VX (4,1408), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
3710 {"evmhessianw", VX (4,1409), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3711 {"bcdctsq.", VXVA(4,1409,0), VXVA_MASK, PPCVEC3, 0, {VD, VB}},
3712 {"bcdcfsq.", VXVA(4,1409,2), VXVAPS_MASK, PPCVEC3, 0, {VD, VB, PS}},
3713 {"bcdctz.", VXVA(4,1409,4), VXVAPS_MASK, PPCVEC3, 0, {VD, VB, PS}},
3714 {"bcdctn.", VXVA(4,1409,5), VXVA_MASK, PPCVEC3, 0, {VD, VB}},
3715 {"bcdcfz.", VXVA(4,1409,6), VXVAPS_MASK, PPCVEC3, 0, {VD, VB, PS}},
3716 {"bcdcfn.", VXVA(4,1409,7), VXVAPS_MASK, PPCVEC3, 0, {VD, VB, PS}},
3717 {"bcdsetsgn.", VXVA(4,1409,31), VXVAPS_MASK, PPCVEC3, 0, {VD, VB, PS}},
3718 {"vavgsw", VX (4,1410), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
3719 {"evmhessfanw", VX (4,1411), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3720 {"vnand", VX (4,1412), VX_MASK, PPCVEC2, 0, {VD, VA, VB}},
3721 {"evmhousianw", VX (4,1412), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3722 {"evmhossianw", VX (4,1413), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3723 {"udi6fcm.", APU(4, 707,0), APU_MASK, PPC405|PPC440, PPC476, {URT, URA, URB}},
3724 {"udi6fcm", APU(4, 707,1), APU_MASK, PPC405|PPC440, PPC476, {URT, URA, URB}},
3725 {"vcmpnezw.", VXR(4, 391,1), VXR_MASK, PPCVEC3, 0, {VD, VA, VB}},
3726 {"evmhossfanw", VX (4,1415), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3727 {"evmheumianw", VX (4,1416), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3728 {"evmhesmianw", VX (4,1417), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3729 {"evmhesmfanw", VX (4,1419), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3730 {"evmhoumianw", VX (4,1420), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3731 {"evmhosmianw", VX (4,1421), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3732 {"evmhosmfanw", VX (4,1423), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3733 {"macchwsuo", XO (4, 204,1,0), XO_MASK, MULHW, 0, {RT, RA, RB}},
3734 {"macchwsuo.", XO (4, 204,1,1), XO_MASK, MULHW, 0, {RT, RA, RB}},
3735 {"evmhegumian", VX (4,1448), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3736 {"evmhegsmian", VX (4,1449), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3737 {"evmhegsmfan", VX (4,1451), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3738 {"evmhogumian", VX (4,1452), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3739 {"evmhogsmian", VX (4,1453), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3740 {"evmhogsmfan", VX (4,1455), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3741 {"evmwlusianw", VX (4,1472), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3742 {"bcdsr.", VX (4,1473), VXPS_MASK, PPCVEC3, 0, {VD, VA, VB, PS}},
3743 {"evmwlssianw", VX (4,1473), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3744 {"vsld", VX (4,1476), VX_MASK, PPCVEC2, 0, {VD, VA, VB}},
3745 {"vcmpgefp.", VXR(4, 454,1), VXR_MASK, PPCVEC, 0, {VD, VA, VB}},
3746 {"udi7fcm.", APU(4, 739,0), APU_MASK, PPC405|PPC440, PPC476, {URT, URA, URB}},
3747 {"udi7fcm", APU(4, 739,1), APU_MASK, PPC405|PPC440, PPC476, {URT, URA, URB}},
3748 {"vsbox", VX (4,1480), VXVB_MASK, PPCVEC2, 0, {VD, VA}},
3749 {"evmwlumianw", VX (4,1480), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3750 {"evmwlsmianw", VX (4,1481), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3751 {"vbpermd", VX (4,1484), VX_MASK, PPCVEC3, 0, {VD, VA, VB}},
3752 {"vpksdss", VX (4,1486), VX_MASK, PPCVEC2, 0, {VD, VA, VB}},
3753 {"evmwssfan", VX (4,1491), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3754 {"macchwso", XO (4, 236,1,0), XO_MASK, MULHW, 0, {RT, RA, RB}},
3755 {"evmwumian", VX (4,1496), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3756 {"macchwso.", XO (4, 236,1,1), XO_MASK, MULHW, 0, {RT, RA, RB}},
3757 {"evmwsmian", VX (4,1497), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3758 {"evmwsmfan", VX (4,1499), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3759 {"nmacchwso", XO (4, 238,1,0), XO_MASK, MULHW, 0, {RT, RA, RB}},
3760 {"nmacchwso.", XO (4, 238,1,1), XO_MASK, MULHW, 0, {RT, RA, RB}},
3761 {"vsububs", VX (4,1536), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
3762 {"vclzlsbb", VXVA(4,1538,0), VXVA_MASK, PPCVEC3, 0, {RT, VB}},
3763 {"vctzlsbb", VXVA(4,1538,1), VXVA_MASK, PPCVEC3, 0, {RT, VB}},
3764 {"vnegw", VXVA(4,1538,6), VXVA_MASK, PPCVEC3, 0, {VD, VB}},
3765 {"vnegd", VXVA(4,1538,7), VXVA_MASK, PPCVEC3, 0, {VD, VB}},
3766 {"vprtybw", VXVA(4,1538,8), VXVA_MASK, PPCVEC3, 0, {VD, VB}},
3767 {"vprtybd", VXVA(4,1538,9), VXVA_MASK, PPCVEC3, 0, {VD, VB}},
3768 {"vprtybq", VXVA(4,1538,10), VXVA_MASK, PPCVEC3, 0, {VD, VB}},
3769 {"vextsb2w", VXVA(4,1538,16), VXVA_MASK, PPCVEC3, 0, {VD, VB}},
3770 {"vextsh2w", VXVA(4,1538,17), VXVA_MASK, PPCVEC3, 0, {VD, VB}},
3771 {"vextsb2d", VXVA(4,1538,24), VXVA_MASK, PPCVEC3, 0, {VD, VB}},
3772 {"vextsh2d", VXVA(4,1538,25), VXVA_MASK, PPCVEC3, 0, {VD, VB}},
3773 {"vextsw2d", VXVA(4,1538,26), VXVA_MASK, PPCVEC3, 0, {VD, VB}},
3774 {"vctzb", VXVA(4,1538,28), VXVA_MASK, PPCVEC3, 0, {VD, VB}},
3775 {"vctzh", VXVA(4,1538,29), VXVA_MASK, PPCVEC3, 0, {VD, VB}},
3776 {"vctzw", VXVA(4,1538,30), VXVA_MASK, PPCVEC3, 0, {VD, VB}},
3777 {"vctzd", VXVA(4,1538,31), VXVA_MASK, PPCVEC3, 0, {VD, VB}},
3778 {"mfvscr", VX (4,1540), VXVAVB_MASK, PPCVEC, 0, {VD}},
3779 {"vcmpgtub.", VXR(4, 518,1), VXR_MASK, PPCVEC, 0, {VD, VA, VB}},
3780 {"udi8fcm.", APU(4, 771,0), APU_MASK, PPC440, PPC476, {URT, URA, URB}},
3781 {"udi8fcm", APU(4, 771,1), APU_MASK, PPC440, PPC476, {URT, URA, URB}},
3782 {"vsum4ubs", VX (4,1544), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
3783 {"vextublx", VX (4,1549), VX_MASK, PPCVEC3, 0, {RT, RA, VB}},
3784 {"vsubuhs", VX (4,1600), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
3785 {"mtvscr", VX (4,1604), VXVDVA_MASK, PPCVEC, 0, {VB}},
3786 {"vcmpgtuh.", VXR(4, 582,1), VXR_MASK, PPCVEC, 0, {VD, VA, VB}},
3787 {"vsum4shs", VX (4,1608), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
3788 {"udi9fcm.", APU(4, 804,0), APU_MASK, PPC440, PPC476, {URT, URA, URB}},
3789 {"udi9fcm", APU(4, 804,1), APU_MASK, PPC440, PPC476, {URT, URA, URB}},
3790 {"vextuhlx", VX (4,1613), VX_MASK, PPCVEC3, 0, {RT, RA, VB}},
3791 {"vupkhsw", VX (4,1614), VXVA_MASK, PPCVEC2, 0, {VD, VB}},
3792 {"vsubuws", VX (4,1664), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
3793 {"vshasigmaw", VX (4,1666), VX_MASK, PPCVEC2, 0, {VD, VA, ST, SIX}},
3794 {"veqv", VX (4,1668), VX_MASK, PPCVEC2, 0, {VD, VA, VB}},
3795 {"vcmpgtuw.", VXR(4, 646,1), VXR_MASK, PPCVEC, 0, {VD, VA, VB}},
3796 {"udi10fcm.", APU(4, 835,0), APU_MASK, PPC440, PPC476, {URT, URA, URB}},
3797 {"udi10fcm", APU(4, 835,1), APU_MASK, PPC440, PPC476, {URT, URA, URB}},
3798 {"vsum2sws", VX (4,1672), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
3799 {"vmrgow", VX (4,1676), VX_MASK, PPCVEC2, 0, {VD, VA, VB}},
3800 {"vextuwlx", VX (4,1677), VX_MASK, PPCVEC3, 0, {RT, RA, VB}},
3801 {"vshasigmad", VX (4,1730), VX_MASK, PPCVEC2, 0, {VD, VA, ST, SIX}},
3802 {"vsrd", VX (4,1732), VX_MASK, PPCVEC2, 0, {VD, VA, VB}},
3803 {"vcmpgtfp.", VXR(4, 710,1), VXR_MASK, PPCVEC, 0, {VD, VA, VB}},
3804 {"udi11fcm.", APU(4, 867,0), APU_MASK, PPC440, PPC476, {URT, URA, URB}},
3805 {"vcmpgtud.", VXR(4, 711,1), VXR_MASK, PPCVEC2, 0, {VD, VA, VB}},
3806 {"udi11fcm", APU(4, 867,1), APU_MASK, PPC440, PPC476, {URT, URA, URB}},
3807 {"vupklsw", VX (4,1742), VXVA_MASK, PPCVEC2, 0, {VD, VB}},
3808 {"vsubsbs", VX (4,1792), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
3809 {"vclzb", VX (4,1794), VXVA_MASK, PPCVEC2, 0, {VD, VB}},
3810 {"vpopcntb", VX (4,1795), VXVA_MASK, PPCVEC2, 0, {VD, VB}},
3811 {"vsrv", VX (4,1796), VX_MASK, PPCVEC3, 0, {VD, VA, VB}},
3812 {"vcmpgtsb.", VXR(4, 774,1), VXR_MASK, PPCVEC, 0, {VD, VA, VB}},
3813 {"udi12fcm.", APU(4, 899,0), APU_MASK, PPC440, PPC476, {URT, URA, URB}},
3814 {"udi12fcm", APU(4, 899,1), APU_MASK, PPC440, PPC476, {URT, URA, URB}},
3815 {"vsum4sbs", VX (4,1800), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
3816 {"vextubrx", VX (4,1805), VX_MASK, PPCVEC3, 0, {RT, RA, VB}},
3817 {"maclhwuo", XO (4, 396,1,0), XO_MASK, MULHW, 0, {RT, RA, RB}},
3818 {"maclhwuo.", XO (4, 396,1,1), XO_MASK, MULHW, 0, {RT, RA, RB}},
3819 {"vsubshs", VX (4,1856), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
3820 {"vclzh", VX (4,1858), VXVA_MASK, PPCVEC2, 0, {VD, VB}},
3821 {"vpopcnth", VX (4,1859), VXVA_MASK, PPCVEC2, 0, {VD, VB}},
3822 {"vslv", VX (4,1860), VX_MASK, PPCVEC3, 0, {VD, VA, VB}},
3823 {"vcmpgtsh.", VXR(4, 838,1), VXR_MASK, PPCVEC, 0, {VD, VA, VB}},
3824 {"vextuhrx", VX (4,1869), VX_MASK, PPCVEC3, 0, {RT, RA, VB}},
3825 {"udi13fcm.", APU(4, 931,0), APU_MASK, PPC440, PPC476, {URT, URA, URB}},
3826 {"udi13fcm", APU(4, 931,1), APU_MASK, PPC440, PPC476, {URT, URA, URB}},
3827 {"maclhwo", XO (4, 428,1,0), XO_MASK, MULHW, 0, {RT, RA, RB}},
3828 {"maclhwo.", XO (4, 428,1,1), XO_MASK, MULHW, 0, {RT, RA, RB}},
3829 {"nmaclhwo", XO (4, 430,1,0), XO_MASK, MULHW, 0, {RT, RA, RB}},
3830 {"nmaclhwo.", XO (4, 430,1,1), XO_MASK, MULHW, 0, {RT, RA, RB}},
3831 {"vsubsws", VX (4,1920), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
3832 {"vclzw", VX (4,1922), VXVA_MASK, PPCVEC2, 0, {VD, VB}},
3833 {"vpopcntw", VX (4,1923), VXVA_MASK, PPCVEC2, 0, {VD, VB}},
3834 {"vcmpgtsw.", VXR(4, 902,1), VXR_MASK, PPCVEC, 0, {VD, VA, VB}},
3835 {"udi14fcm.", APU(4, 963,0), APU_MASK, PPC440, PPC476, {URT, URA, URB}},
3836 {"udi14fcm", APU(4, 963,1), APU_MASK, PPC440, PPC476, {URT, URA, URB}},
3837 {"vsumsws", VX (4,1928), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
3838 {"vmrgew", VX (4,1932), VX_MASK, PPCVEC2, 0, {VD, VA, VB}},
3839 {"vextuwrx", VX (4,1933), VX_MASK, PPCVEC3, 0, {RT, RA, VB}},
3840 {"maclhwsuo", XO (4, 460,1,0), XO_MASK, MULHW, 0, {RT, RA, RB}},
3841 {"maclhwsuo.", XO (4, 460,1,1), XO_MASK, MULHW, 0, {RT, RA, RB}},
3842 {"vclzd", VX (4,1986), VXVA_MASK, PPCVEC2, 0, {VD, VB}},
3843 {"vpopcntd", VX (4,1987), VXVA_MASK, PPCVEC2, 0, {VD, VB}},
3844 {"vcmpbfp.", VXR(4, 966,1), VXR_MASK, PPCVEC, 0, {VD, VA, VB}},
3845 {"udi15fcm.", APU(4, 995,0), APU_MASK, PPC440, PPC476, {URT, URA, URB}},
3846 {"vcmpgtsd.", VXR(4, 967,1), VXR_MASK, PPCVEC2, 0, {VD, VA, VB}},
3847 {"udi15fcm", APU(4, 995,1), APU_MASK, PPC440, PPC476, {URT, URA, URB}},
3848 {"maclhwso", XO (4, 492,1,0), XO_MASK, MULHW, 0, {RT, RA, RB}},
3849 {"maclhwso.", XO (4, 492,1,1), XO_MASK, MULHW, 0, {RT, RA, RB}},
3850 {"nmaclhwso", XO (4, 494,1,0), XO_MASK, MULHW, 0, {RT, RA, RB}},
3851 {"nmaclhwso.", XO (4, 494,1,1), XO_MASK, MULHW, 0, {RT, RA, RB}},
3852 {"dcbz_l", X (4,1014), XRT_MASK, PPCPS, 0, {RA, RB}},
3854 {"mulli", OP(7), OP_MASK, PPCCOM, PPCVLE, {RT, RA, SI}},
3855 {"muli", OP(7), OP_MASK, PWRCOM, PPCVLE, {RT, RA, SI}},
3857 {"subfic", OP(8), OP_MASK, PPCCOM, PPCVLE, {RT, RA, SI}},
3858 {"sfi", OP(8), OP_MASK, PWRCOM, PPCVLE, {RT, RA, SI}},
3860 {"dozi", OP(9), OP_MASK, M601, PPCVLE, {RT, RA, SI}},
3862 {"cmplwi", OPL(10,0), OPL_MASK, PPCCOM, PPCVLE, {OBF, RA, UISIGNOPT}},
3863 {"cmpldi", OPL(10,1), OPL_MASK, PPC64, PPCVLE, {OBF, RA, UISIGNOPT}},
3864 {"cmpli", OP(10), OP_MASK, PPC, PPCVLE, {BF, L, RA, UISIGNOPT}},
3865 {"cmpli", OP(10), OP_MASK, PWRCOM, PPC|PPCVLE, {BF, RA, UISIGNOPT}},
3867 {"cmpwi", OPL(11,0), OPL_MASK, PPCCOM, PPCVLE, {OBF, RA, SI}},
3868 {"cmpdi", OPL(11,1), OPL_MASK, PPC64, PPCVLE, {OBF, RA, SI}},
3869 {"cmpi", OP(11), OP_MASK, PPC, PPCVLE, {BF, L, RA, SI}},
3870 {"cmpi", OP(11), OP_MASK, PWRCOM, PPC|PPCVLE, {BF, RA, SI}},
3872 {"addic", OP(12), OP_MASK, PPCCOM, PPCVLE, {RT, RA, SI}},
3873 {"ai", OP(12), OP_MASK, PWRCOM, PPCVLE, {RT, RA, SI}},
3874 {"subic", OP(12), OP_MASK, PPCCOM, PPCVLE, {RT, RA, NSI}},
3876 {"addic.", OP(13), OP_MASK, PPCCOM, PPCVLE, {RT, RA, SI}},
3877 {"ai.", OP(13), OP_MASK, PWRCOM, PPCVLE, {RT, RA, SI}},
3878 {"subic.", OP(13), OP_MASK, PPCCOM, PPCVLE, {RT, RA, NSI}},
3880 {"li", OP(14), DRA_MASK, PPCCOM, PPCVLE, {RT, SI}},
3881 {"lil", OP(14), DRA_MASK, PWRCOM, PPCVLE, {RT, SI}},
3882 {"addi", OP(14), OP_MASK, PPCCOM, PPCVLE, {RT, RA0, SI}},
3883 {"cal", OP(14), OP_MASK, PWRCOM, PPCVLE, {RT, D, RA0}},
3884 {"subi", OP(14), OP_MASK, PPCCOM, PPCVLE, {RT, RA0, NSI}},
3885 {"la", OP(14), OP_MASK, PPCCOM, PPCVLE, {RT, D, RA0}},
3887 {"lis", OP(15), DRA_MASK, PPCCOM, PPCVLE, {RT, SISIGNOPT}},
3888 {"liu", OP(15), DRA_MASK, PWRCOM, PPCVLE, {RT, SISIGNOPT}},
3889 {"addis", OP(15), OP_MASK, PPCCOM, PPCVLE, {RT, RA0, SISIGNOPT}},
3890 {"cau", OP(15), OP_MASK, PWRCOM, PPCVLE, {RT, RA0, SISIGNOPT}},
3891 {"subis", OP(15), OP_MASK, PPCCOM, PPCVLE, {RT, RA0, NSISIGNOPT}},
3893 {"bdnz-", BBO(16,BODNZ,0,0), BBOATBI_MASK, PPCCOM, PPCVLE, {BDM}},
3894 {"bdnz+", BBO(16,BODNZ,0,0), BBOATBI_MASK, PPCCOM, PPCVLE, {BDP}},
3895 {"bdnz", BBO(16,BODNZ,0,0), BBOATBI_MASK, PPCCOM, PPCVLE, {BD}},
3896 {"bdn", BBO(16,BODNZ,0,0), BBOATBI_MASK, PWRCOM, PPCVLE, {BD}},
3897 {"bdnzl-", BBO(16,BODNZ,0,1), BBOATBI_MASK, PPCCOM, PPCVLE, {BDM}},
3898 {"bdnzl+", BBO(16,BODNZ,0,1), BBOATBI_MASK, PPCCOM, PPCVLE, {BDP}},
3899 {"bdnzl", BBO(16,BODNZ,0,1), BBOATBI_MASK, PPCCOM, PPCVLE, {BD}},
3900 {"bdnl", BBO(16,BODNZ,0,1), BBOATBI_MASK, PWRCOM, PPCVLE, {BD}},
3901 {"bdnza-", BBO(16,BODNZ,1,0), BBOATBI_MASK, PPCCOM, PPCVLE, {BDMA}},
3902 {"bdnza+", BBO(16,BODNZ,1,0), BBOATBI_MASK, PPCCOM, PPCVLE, {BDPA}},
3903 {"bdnza", BBO(16,BODNZ,1,0), BBOATBI_MASK, PPCCOM, PPCVLE, {BDA}},
3904 {"bdna", BBO(16,BODNZ,1,0), BBOATBI_MASK, PWRCOM, PPCVLE, {BDA}},
3905 {"bdnzla-", BBO(16,BODNZ,1,1), BBOATBI_MASK, PPCCOM, PPCVLE, {BDMA}},
3906 {"bdnzla+", BBO(16,BODNZ,1,1), BBOATBI_MASK, PPCCOM, PPCVLE, {BDPA}},
3907 {"bdnzla", BBO(16,BODNZ,1,1), BBOATBI_MASK, PPCCOM, PPCVLE, {BDA}},
3908 {"bdnla", BBO(16,BODNZ,1,1), BBOATBI_MASK, PWRCOM, PPCVLE, {BDA}},
3909 {"bdz-", BBO(16,BODZ,0,0), BBOATBI_MASK, PPCCOM, PPCVLE, {BDM}},
3910 {"bdz+", BBO(16,BODZ,0,0), BBOATBI_MASK, PPCCOM, PPCVLE, {BDP}},
3911 {"bdz", BBO(16,BODZ,0,0), BBOATBI_MASK, COM, PPCVLE, {BD}},
3912 {"bdzl-", BBO(16,BODZ,0,1), BBOATBI_MASK, PPCCOM, PPCVLE, {BDM}},
3913 {"bdzl+", BBO(16,BODZ,0,1), BBOATBI_MASK, PPCCOM, PPCVLE, {BDP}},
3914 {"bdzl", BBO(16,BODZ,0,1), BBOATBI_MASK, COM, PPCVLE, {BD}},
3915 {"bdza-", BBO(16,BODZ,1,0), BBOATBI_MASK, PPCCOM, PPCVLE, {BDMA}},
3916 {"bdza+", BBO(16,BODZ,1,0), BBOATBI_MASK, PPCCOM, PPCVLE, {BDPA}},
3917 {"bdza", BBO(16,BODZ,1,0), BBOATBI_MASK, COM, PPCVLE, {BDA}},
3918 {"bdzla-", BBO(16,BODZ,1,1), BBOATBI_MASK, PPCCOM, PPCVLE, {BDMA}},
3919 {"bdzla+", BBO(16,BODZ,1,1), BBOATBI_MASK, PPCCOM, PPCVLE, {BDPA}},
3920 {"bdzla", BBO(16,BODZ,1,1), BBOATBI_MASK, COM, PPCVLE, {BDA}},
3922 {"bge-", BBOCB(16,BOF,CBLT,0,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDM}},
3923 {"bge+", BBOCB(16,BOF,CBLT,0,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDP}},
3924 {"bge", BBOCB(16,BOF,CBLT,0,0), BBOATCB_MASK, COM, PPCVLE, {CR, BD}},
3925 {"bnl-", BBOCB(16,BOF,CBLT,0,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDM}},
3926 {"bnl+", BBOCB(16,BOF,CBLT,0,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDP}},
3927 {"bnl", BBOCB(16,BOF,CBLT,0,0), BBOATCB_MASK, COM, PPCVLE, {CR, BD}},
3928 {"bgel-", BBOCB(16,BOF,CBLT,0,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDM}},
3929 {"bgel+", BBOCB(16,BOF,CBLT,0,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDP}},
3930 {"bgel", BBOCB(16,BOF,CBLT,0,1), BBOATCB_MASK, COM, PPCVLE, {CR, BD}},
3931 {"bnll-", BBOCB(16,BOF,CBLT,0,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDM}},
3932 {"bnll+", BBOCB(16,BOF,CBLT,0,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDP}},
3933 {"bnll", BBOCB(16,BOF,CBLT,0,1), BBOATCB_MASK, COM, PPCVLE, {CR, BD}},
3934 {"bgea-", BBOCB(16,BOF,CBLT,1,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDMA}},
3935 {"bgea+", BBOCB(16,BOF,CBLT,1,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDPA}},
3936 {"bgea", BBOCB(16,BOF,CBLT,1,0), BBOATCB_MASK, COM, PPCVLE, {CR, BDA}},
3937 {"bnla-", BBOCB(16,BOF,CBLT,1,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDMA}},
3938 {"bnla+", BBOCB(16,BOF,CBLT,1,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDPA}},
3939 {"bnla", BBOCB(16,BOF,CBLT,1,0), BBOATCB_MASK, COM, PPCVLE, {CR, BDA}},
3940 {"bgela-", BBOCB(16,BOF,CBLT,1,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDMA}},
3941 {"bgela+", BBOCB(16,BOF,CBLT,1,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDPA}},
3942 {"bgela", BBOCB(16,BOF,CBLT,1,1), BBOATCB_MASK, COM, PPCVLE, {CR, BDA}},
3943 {"bnlla-", BBOCB(16,BOF,CBLT,1,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDMA}},
3944 {"bnlla+", BBOCB(16,BOF,CBLT,1,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDPA}},
3945 {"bnlla", BBOCB(16,BOF,CBLT,1,1), BBOATCB_MASK, COM, PPCVLE, {CR, BDA}},
3946 {"ble-", BBOCB(16,BOF,CBGT,0,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDM}},
3947 {"ble+", BBOCB(16,BOF,CBGT,0,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDP}},
3948 {"ble", BBOCB(16,BOF,CBGT,0,0), BBOATCB_MASK, COM, PPCVLE, {CR, BD}},
3949 {"bng-", BBOCB(16,BOF,CBGT,0,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDM}},
3950 {"bng+", BBOCB(16,BOF,CBGT,0,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDP}},
3951 {"bng", BBOCB(16,BOF,CBGT,0,0), BBOATCB_MASK, COM, PPCVLE, {CR, BD}},
3952 {"blel-", BBOCB(16,BOF,CBGT,0,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDM}},
3953 {"blel+", BBOCB(16,BOF,CBGT,0,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDP}},
3954 {"blel", BBOCB(16,BOF,CBGT,0,1), BBOATCB_MASK, COM, PPCVLE, {CR, BD}},
3955 {"bngl-", BBOCB(16,BOF,CBGT,0,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDM}},
3956 {"bngl+", BBOCB(16,BOF,CBGT,0,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDP}},
3957 {"bngl", BBOCB(16,BOF,CBGT,0,1), BBOATCB_MASK, COM, PPCVLE, {CR, BD}},
3958 {"blea-", BBOCB(16,BOF,CBGT,1,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDMA}},
3959 {"blea+", BBOCB(16,BOF,CBGT,1,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDPA}},
3960 {"blea", BBOCB(16,BOF,CBGT,1,0), BBOATCB_MASK, COM, PPCVLE, {CR, BDA}},
3961 {"bnga-", BBOCB(16,BOF,CBGT,1,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDMA}},
3962 {"bnga+", BBOCB(16,BOF,CBGT,1,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDPA}},
3963 {"bnga", BBOCB(16,BOF,CBGT,1,0), BBOATCB_MASK, COM, PPCVLE, {CR, BDA}},
3964 {"blela-", BBOCB(16,BOF,CBGT,1,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDMA}},
3965 {"blela+", BBOCB(16,BOF,CBGT,1,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDPA}},
3966 {"blela", BBOCB(16,BOF,CBGT,1,1), BBOATCB_MASK, COM, PPCVLE, {CR, BDA}},
3967 {"bngla-", BBOCB(16,BOF,CBGT,1,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDMA}},
3968 {"bngla+", BBOCB(16,BOF,CBGT,1,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDPA}},
3969 {"bngla", BBOCB(16,BOF,CBGT,1,1), BBOATCB_MASK, COM, PPCVLE, {CR, BDA}},
3970 {"bne-", BBOCB(16,BOF,CBEQ,0,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDM}},
3971 {"bne+", BBOCB(16,BOF,CBEQ,0,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDP}},
3972 {"bne", BBOCB(16,BOF,CBEQ,0,0), BBOATCB_MASK, COM, PPCVLE, {CR, BD}},
3973 {"bnel-", BBOCB(16,BOF,CBEQ,0,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDM}},
3974 {"bnel+", BBOCB(16,BOF,CBEQ,0,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDP}},
3975 {"bnel", BBOCB(16,BOF,CBEQ,0,1), BBOATCB_MASK, COM, PPCVLE, {CR, BD}},
3976 {"bnea-", BBOCB(16,BOF,CBEQ,1,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDMA}},
3977 {"bnea+", BBOCB(16,BOF,CBEQ,1,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDPA}},
3978 {"bnea", BBOCB(16,BOF,CBEQ,1,0), BBOATCB_MASK, COM, PPCVLE, {CR, BDA}},
3979 {"bnela-", BBOCB(16,BOF,CBEQ,1,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDMA}},
3980 {"bnela+", BBOCB(16,BOF,CBEQ,1,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDPA}},
3981 {"bnela", BBOCB(16,BOF,CBEQ,1,1), BBOATCB_MASK, COM, PPCVLE, {CR, BDA}},
3982 {"bns-", BBOCB(16,BOF,CBSO,0,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDM}},
3983 {"bns+", BBOCB(16,BOF,CBSO,0,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDP}},
3984 {"bns", BBOCB(16,BOF,CBSO,0,0), BBOATCB_MASK, COM, PPCVLE, {CR, BD}},
3985 {"bnu-", BBOCB(16,BOF,CBSO,0,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDM}},
3986 {"bnu+", BBOCB(16,BOF,CBSO,0,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDP}},
3987 {"bnu", BBOCB(16,BOF,CBSO,0,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BD}},
3988 {"bnsl-", BBOCB(16,BOF,CBSO,0,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDM}},
3989 {"bnsl+", BBOCB(16,BOF,CBSO,0,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDP}},
3990 {"bnsl", BBOCB(16,BOF,CBSO,0,1), BBOATCB_MASK, COM, PPCVLE, {CR, BD}},
3991 {"bnul-", BBOCB(16,BOF,CBSO,0,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDM}},
3992 {"bnul+", BBOCB(16,BOF,CBSO,0,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDP}},
3993 {"bnul", BBOCB(16,BOF,CBSO,0,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BD}},
3994 {"bnsa-", BBOCB(16,BOF,CBSO,1,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDMA}},
3995 {"bnsa+", BBOCB(16,BOF,CBSO,1,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDPA}},
3996 {"bnsa", BBOCB(16,BOF,CBSO,1,0), BBOATCB_MASK, COM, PPCVLE, {CR, BDA}},
3997 {"bnua-", BBOCB(16,BOF,CBSO,1,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDMA}},
3998 {"bnua+", BBOCB(16,BOF,CBSO,1,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDPA}},
3999 {"bnua", BBOCB(16,BOF,CBSO,1,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDA}},
4000 {"bnsla-", BBOCB(16,BOF,CBSO,1,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDMA}},
4001 {"bnsla+", BBOCB(16,BOF,CBSO,1,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDPA}},
4002 {"bnsla", BBOCB(16,BOF,CBSO,1,1), BBOATCB_MASK, COM, PPCVLE, {CR, BDA}},
4003 {"bnula-", BBOCB(16,BOF,CBSO,1,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDMA}},
4004 {"bnula+", BBOCB(16,BOF,CBSO,1,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDPA}},
4005 {"bnula", BBOCB(16,BOF,CBSO,1,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDA}},
4007 {"blt-", BBOCB(16,BOT,CBLT,0,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDM}},
4008 {"blt+", BBOCB(16,BOT,CBLT,0,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDP}},
4009 {"blt", BBOCB(16,BOT,CBLT,0,0), BBOATCB_MASK, COM, PPCVLE, {CR, BD}},
4010 {"bltl-", BBOCB(16,BOT,CBLT,0,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDM}},
4011 {"bltl+", BBOCB(16,BOT,CBLT,0,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDP}},
4012 {"bltl", BBOCB(16,BOT,CBLT,0,1), BBOATCB_MASK, COM, PPCVLE, {CR, BD}},
4013 {"blta-", BBOCB(16,BOT,CBLT,1,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDMA}},
4014 {"blta+", BBOCB(16,BOT,CBLT,1,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDPA}},
4015 {"blta", BBOCB(16,BOT,CBLT,1,0), BBOATCB_MASK, COM, PPCVLE, {CR, BDA}},
4016 {"bltla-", BBOCB(16,BOT,CBLT,1,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDMA}},
4017 {"bltla+", BBOCB(16,BOT,CBLT,1,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDPA}},
4018 {"bltla", BBOCB(16,BOT,CBLT,1,1), BBOATCB_MASK, COM, PPCVLE, {CR, BDA}},
4019 {"bgt-", BBOCB(16,BOT,CBGT,0,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDM}},
4020 {"bgt+", BBOCB(16,BOT,CBGT,0,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDP}},
4021 {"bgt", BBOCB(16,BOT,CBGT,0,0), BBOATCB_MASK, COM, PPCVLE, {CR, BD}},
4022 {"bgtl-", BBOCB(16,BOT,CBGT,0,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDM}},
4023 {"bgtl+", BBOCB(16,BOT,CBGT,0,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDP}},
4024 {"bgtl", BBOCB(16,BOT,CBGT,0,1), BBOATCB_MASK, COM, PPCVLE, {CR, BD}},
4025 {"bgta-", BBOCB(16,BOT,CBGT,1,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDMA}},
4026 {"bgta+", BBOCB(16,BOT,CBGT,1,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDPA}},
4027 {"bgta", BBOCB(16,BOT,CBGT,1,0), BBOATCB_MASK, COM, PPCVLE, {CR, BDA}},
4028 {"bgtla-", BBOCB(16,BOT,CBGT,1,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDMA}},
4029 {"bgtla+", BBOCB(16,BOT,CBGT,1,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDPA}},
4030 {"bgtla", BBOCB(16,BOT,CBGT,1,1), BBOATCB_MASK, COM, PPCVLE, {CR, BDA}},
4031 {"beq-", BBOCB(16,BOT,CBEQ,0,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDM}},
4032 {"beq+", BBOCB(16,BOT,CBEQ,0,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDP}},
4033 {"beq", BBOCB(16,BOT,CBEQ,0,0), BBOATCB_MASK, COM, PPCVLE, {CR, BD}},
4034 {"beql-", BBOCB(16,BOT,CBEQ,0,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDM}},
4035 {"beql+", BBOCB(16,BOT,CBEQ,0,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDP}},
4036 {"beql", BBOCB(16,BOT,CBEQ,0,1), BBOATCB_MASK, COM, PPCVLE, {CR, BD}},
4037 {"beqa-", BBOCB(16,BOT,CBEQ,1,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDMA}},
4038 {"beqa+", BBOCB(16,BOT,CBEQ,1,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDPA}},
4039 {"beqa", BBOCB(16,BOT,CBEQ,1,0), BBOATCB_MASK, COM, PPCVLE, {CR, BDA}},
4040 {"beqla-", BBOCB(16,BOT,CBEQ,1,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDMA}},
4041 {"beqla+", BBOCB(16,BOT,CBEQ,1,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDPA}},
4042 {"beqla", BBOCB(16,BOT,CBEQ,1,1), BBOATCB_MASK, COM, PPCVLE, {CR, BDA}},
4043 {"bso-", BBOCB(16,BOT,CBSO,0,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDM}},
4044 {"bso+", BBOCB(16,BOT,CBSO,0,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDP}},
4045 {"bso", BBOCB(16,BOT,CBSO,0,0), BBOATCB_MASK, COM, PPCVLE, {CR, BD}},
4046 {"bun-", BBOCB(16,BOT,CBSO,0,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDM}},
4047 {"bun+", BBOCB(16,BOT,CBSO,0,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDP}},
4048 {"bun", BBOCB(16,BOT,CBSO,0,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BD}},
4049 {"bsol-", BBOCB(16,BOT,CBSO,0,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDM}},
4050 {"bsol+", BBOCB(16,BOT,CBSO,0,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDP}},
4051 {"bsol", BBOCB(16,BOT,CBSO,0,1), BBOATCB_MASK, COM, PPCVLE, {CR, BD}},
4052 {"bunl-", BBOCB(16,BOT,CBSO,0,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDM}},
4053 {"bunl+", BBOCB(16,BOT,CBSO,0,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDP}},
4054 {"bunl", BBOCB(16,BOT,CBSO,0,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BD}},
4055 {"bsoa-", BBOCB(16,BOT,CBSO,1,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDMA}},
4056 {"bsoa+", BBOCB(16,BOT,CBSO,1,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDPA}},
4057 {"bsoa", BBOCB(16,BOT,CBSO,1,0), BBOATCB_MASK, COM, PPCVLE, {CR, BDA}},
4058 {"buna-", BBOCB(16,BOT,CBSO,1,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDMA}},
4059 {"buna+", BBOCB(16,BOT,CBSO,1,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDPA}},
4060 {"buna", BBOCB(16,BOT,CBSO,1,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDA}},
4061 {"bsola-", BBOCB(16,BOT,CBSO,1,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDMA}},
4062 {"bsola+", BBOCB(16,BOT,CBSO,1,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDPA}},
4063 {"bsola", BBOCB(16,BOT,CBSO,1,1), BBOATCB_MASK, COM, PPCVLE, {CR, BDA}},
4064 {"bunla-", BBOCB(16,BOT,CBSO,1,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDMA}},
4065 {"bunla+", BBOCB(16,BOT,CBSO,1,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDPA}},
4066 {"bunla", BBOCB(16,BOT,CBSO,1,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDA}},
4068 {"bdnzf-", BBO(16,BODNZF,0,0), BBOY_MASK, PPCCOM, ISA_V2|PPCVLE, {BI, BDM}},
4069 {"bdnzf+", BBO(16,BODNZF,0,0), BBOY_MASK, PPCCOM, ISA_V2|PPCVLE, {BI, BDP}},
4070 {"bdnzf", BBO(16,BODNZF,0,0), BBOY_MASK, PPCCOM, PPCVLE, {BI, BD}},
4071 {"bdnzfl-", BBO(16,BODNZF,0,1), BBOY_MASK, PPCCOM, ISA_V2|PPCVLE, {BI, BDM}},
4072 {"bdnzfl+", BBO(16,BODNZF,0,1), BBOY_MASK, PPCCOM, ISA_V2|PPCVLE, {BI, BDP}},
4073 {"bdnzfl", BBO(16,BODNZF,0,1), BBOY_MASK, PPCCOM, PPCVLE, {BI, BD}},
4074 {"bdnzfa-", BBO(16,BODNZF,1,0), BBOY_MASK, PPCCOM, ISA_V2|PPCVLE, {BI, BDMA}},
4075 {"bdnzfa+", BBO(16,BODNZF,1,0), BBOY_MASK, PPCCOM, ISA_V2|PPCVLE, {BI, BDPA}},
4076 {"bdnzfa", BBO(16,BODNZF,1,0), BBOY_MASK, PPCCOM, PPCVLE, {BI, BDA}},
4077 {"bdnzfla-", BBO(16,BODNZF,1,1), BBOY_MASK, PPCCOM, ISA_V2|PPCVLE, {BI, BDMA}},
4078 {"bdnzfla+", BBO(16,BODNZF,1,1), BBOY_MASK, PPCCOM, ISA_V2|PPCVLE, {BI, BDPA}},
4079 {"bdnzfla", BBO(16,BODNZF,1,1), BBOY_MASK, PPCCOM, PPCVLE, {BI, BDA}},
4080 {"bdzf-", BBO(16,BODZF,0,0), BBOY_MASK, PPCCOM, ISA_V2|PPCVLE, {BI, BDM}},
4081 {"bdzf+", BBO(16,BODZF,0,0), BBOY_MASK, PPCCOM, ISA_V2|PPCVLE, {BI, BDP}},
4082 {"bdzf", BBO(16,BODZF,0,0), BBOY_MASK, PPCCOM, PPCVLE, {BI, BD}},
4083 {"bdzfl-", BBO(16,BODZF,0,1), BBOY_MASK, PPCCOM, ISA_V2|PPCVLE, {BI, BDM}},
4084 {"bdzfl+", BBO(16,BODZF,0,1), BBOY_MASK, PPCCOM, ISA_V2|PPCVLE, {BI, BDP}},
4085 {"bdzfl", BBO(16,BODZF,0,1), BBOY_MASK, PPCCOM, PPCVLE, {BI, BD}},
4086 {"bdzfa-", BBO(16,BODZF,1,0), BBOY_MASK, PPCCOM, ISA_V2|PPCVLE, {BI, BDMA}},
4087 {"bdzfa+", BBO(16,BODZF,1,0), BBOY_MASK, PPCCOM, ISA_V2|PPCVLE, {BI, BDPA}},
4088 {"bdzfa", BBO(16,BODZF,1,0), BBOY_MASK, PPCCOM, PPCVLE, {BI, BDA}},
4089 {"bdzfla-", BBO(16,BODZF,1,1), BBOY_MASK, PPCCOM, ISA_V2|PPCVLE, {BI, BDMA}},
4090 {"bdzfla+", BBO(16,BODZF,1,1), BBOY_MASK, PPCCOM, ISA_V2|PPCVLE, {BI, BDPA}},
4091 {"bdzfla", BBO(16,BODZF,1,1), BBOY_MASK, PPCCOM, PPCVLE, {BI, BDA}},
4093 {"bf-", BBO(16,BOF,0,0), BBOAT_MASK, PPCCOM, PPCVLE, {BI, BDM}},
4094 {"bf+", BBO(16,BOF,0,0), BBOAT_MASK, PPCCOM, PPCVLE, {BI, BDP}},
4095 {"bf", BBO(16,BOF,0,0), BBOAT_MASK, PPCCOM, PPCVLE, {BI, BD}},
4096 {"bbf", BBO(16,BOF,0,0), BBOAT_MASK, PWRCOM, PPCVLE, {BI, BD}},
4097 {"bfl-", BBO(16,BOF,0,1), BBOAT_MASK, PPCCOM, PPCVLE, {BI, BDM}},
4098 {"bfl+", BBO(16,BOF,0,1), BBOAT_MASK, PPCCOM, PPCVLE, {BI, BDP}},
4099 {"bfl", BBO(16,BOF,0,1), BBOAT_MASK, PPCCOM, PPCVLE, {BI, BD}},
4100 {"bbfl", BBO(16,BOF,0,1), BBOAT_MASK, PWRCOM, PPCVLE, {BI, BD}},
4101 {"bfa-", BBO(16,BOF,1,0), BBOAT_MASK, PPCCOM, PPCVLE, {BI, BDMA}},
4102 {"bfa+", BBO(16,BOF,1,0), BBOAT_MASK, PPCCOM, PPCVLE, {BI, BDPA}},
4103 {"bfa", BBO(16,BOF,1,0), BBOAT_MASK, PPCCOM, PPCVLE, {BI, BDA}},
4104 {"bbfa", BBO(16,BOF,1,0), BBOAT_MASK, PWRCOM, PPCVLE, {BI, BDA}},
4105 {"bfla-", BBO(16,BOF,1,1), BBOAT_MASK, PPCCOM, PPCVLE, {BI, BDMA}},
4106 {"bfla+", BBO(16,BOF,1,1), BBOAT_MASK, PPCCOM, PPCVLE, {BI, BDPA}},
4107 {"bfla", BBO(16,BOF,1,1), BBOAT_MASK, PPCCOM, PPCVLE, {BI, BDA}},
4108 {"bbfla", BBO(16,BOF,1,1), BBOAT_MASK, PWRCOM, PPCVLE, {BI, BDA}},
4110 {"bdnzt-", BBO(16,BODNZT,0,0), BBOY_MASK, PPCCOM, ISA_V2|PPCVLE, {BI, BDM}},
4111 {"bdnzt+", BBO(16,BODNZT,0,0), BBOY_MASK, PPCCOM, ISA_V2|PPCVLE, {BI, BDP}},
4112 {"bdnzt", BBO(16,BODNZT,0,0), BBOY_MASK, PPCCOM, PPCVLE, {BI, BD}},
4113 {"bdnztl-", BBO(16,BODNZT,0,1), BBOY_MASK, PPCCOM, ISA_V2|PPCVLE, {BI, BDM}},
4114 {"bdnztl+", BBO(16,BODNZT,0,1), BBOY_MASK, PPCCOM, ISA_V2|PPCVLE, {BI, BDP}},
4115 {"bdnztl", BBO(16,BODNZT,0,1), BBOY_MASK, PPCCOM, PPCVLE, {BI, BD}},
4116 {"bdnzta-", BBO(16,BODNZT,1,0), BBOY_MASK, PPCCOM, ISA_V2|PPCVLE, {BI, BDMA}},
4117 {"bdnzta+", BBO(16,BODNZT,1,0), BBOY_MASK, PPCCOM, ISA_V2|PPCVLE, {BI, BDPA}},
4118 {"bdnzta", BBO(16,BODNZT,1,0), BBOY_MASK, PPCCOM, PPCVLE, {BI, BDA}},
4119 {"bdnztla-", BBO(16,BODNZT,1,1), BBOY_MASK, PPCCOM, ISA_V2|PPCVLE, {BI, BDMA}},
4120 {"bdnztla+", BBO(16,BODNZT,1,1), BBOY_MASK, PPCCOM, ISA_V2|PPCVLE, {BI, BDPA}},
4121 {"bdnztla", BBO(16,BODNZT,1,1), BBOY_MASK, PPCCOM, PPCVLE, {BI, BDA}},
4122 {"bdzt-", BBO(16,BODZT,0,0), BBOY_MASK, PPCCOM, ISA_V2|PPCVLE, {BI, BDM}},
4123 {"bdzt+", BBO(16,BODZT,0,0), BBOY_MASK, PPCCOM, ISA_V2|PPCVLE, {BI, BDP}},
4124 {"bdzt", BBO(16,BODZT,0,0), BBOY_MASK, PPCCOM, PPCVLE, {BI, BD}},
4125 {"bdztl-", BBO(16,BODZT,0,1), BBOY_MASK, PPCCOM, ISA_V2|PPCVLE, {BI, BDM}},
4126 {"bdztl+", BBO(16,BODZT,0,1), BBOY_MASK, PPCCOM, ISA_V2|PPCVLE, {BI, BDP}},
4127 {"bdztl", BBO(16,BODZT,0,1), BBOY_MASK, PPCCOM, PPCVLE, {BI, BD}},
4128 {"bdzta-", BBO(16,BODZT,1,0), BBOY_MASK, PPCCOM, ISA_V2|PPCVLE, {BI, BDMA}},
4129 {"bdzta+", BBO(16,BODZT,1,0), BBOY_MASK, PPCCOM, ISA_V2|PPCVLE, {BI, BDPA}},
4130 {"bdzta", BBO(16,BODZT,1,0), BBOY_MASK, PPCCOM, PPCVLE, {BI, BDA}},
4131 {"bdztla-", BBO(16,BODZT,1,1), BBOY_MASK, PPCCOM, ISA_V2|PPCVLE, {BI, BDMA}},
4132 {"bdztla+", BBO(16,BODZT,1,1), BBOY_MASK, PPCCOM, ISA_V2|PPCVLE, {BI, BDPA}},
4133 {"bdztla", BBO(16,BODZT,1,1), BBOY_MASK, PPCCOM, PPCVLE, {BI, BDA}},
4135 {"bt-", BBO(16,BOT,0,0), BBOAT_MASK, PPCCOM, PPCVLE, {BI, BDM}},
4136 {"bt+", BBO(16,BOT,0,0), BBOAT_MASK, PPCCOM, PPCVLE, {BI, BDP}},
4137 {"bt", BBO(16,BOT,0,0), BBOAT_MASK, PPCCOM, PPCVLE, {BI, BD}},
4138 {"bbt", BBO(16,BOT,0,0), BBOAT_MASK, PWRCOM, PPCVLE, {BI, BD}},
4139 {"btl-", BBO(16,BOT,0,1), BBOAT_MASK, PPCCOM, PPCVLE, {BI, BDM}},
4140 {"btl+", BBO(16,BOT,0,1), BBOAT_MASK, PPCCOM, PPCVLE, {BI, BDP}},
4141 {"btl", BBO(16,BOT,0,1), BBOAT_MASK, PPCCOM, PPCVLE, {BI, BD}},
4142 {"bbtl", BBO(16,BOT,0,1), BBOAT_MASK, PWRCOM, PPCVLE, {BI, BD}},
4143 {"bta-", BBO(16,BOT,1,0), BBOAT_MASK, PPCCOM, PPCVLE, {BI, BDMA}},
4144 {"bta+", BBO(16,BOT,1,0), BBOAT_MASK, PPCCOM, PPCVLE, {BI, BDPA}},
4145 {"bta", BBO(16,BOT,1,0), BBOAT_MASK, PPCCOM, PPCVLE, {BI, BDA}},
4146 {"bbta", BBO(16,BOT,1,0), BBOAT_MASK, PWRCOM, PPCVLE, {BI, BDA}},
4147 {"btla-", BBO(16,BOT,1,1), BBOAT_MASK, PPCCOM, PPCVLE, {BI, BDMA}},
4148 {"btla+", BBO(16,BOT,1,1), BBOAT_MASK, PPCCOM, PPCVLE, {BI, BDPA}},
4149 {"btla", BBO(16,BOT,1,1), BBOAT_MASK, PPCCOM, PPCVLE, {BI, BDA}},
4150 {"bbtla", BBO(16,BOT,1,1), BBOAT_MASK, PWRCOM, PPCVLE, {BI, BDA}},
4152 {"bc-", B(16,0,0), B_MASK, PPCCOM, PPCVLE, {BOE, BI, BDM}},
4153 {"bc+", B(16,0,0), B_MASK, PPCCOM, PPCVLE, {BOE, BI, BDP}},
4154 {"bc", B(16,0,0), B_MASK, COM, PPCVLE, {BO, BI, BD}},
4155 {"bcl-", B(16,0,1), B_MASK, PPCCOM, PPCVLE, {BOE, BI, BDM}},
4156 {"bcl+", B(16,0,1), B_MASK, PPCCOM, PPCVLE, {BOE, BI, BDP}},
4157 {"bcl", B(16,0,1), B_MASK, COM, PPCVLE, {BO, BI, BD}},
4158 {"bca-", B(16,1,0), B_MASK, PPCCOM, PPCVLE, {BOE, BI, BDMA}},
4159 {"bca+", B(16,1,0), B_MASK, PPCCOM, PPCVLE, {BOE, BI, BDPA}},
4160 {"bca", B(16,1,0), B_MASK, COM, PPCVLE, {BO, BI, BDA}},
4161 {"bcla-", B(16,1,1), B_MASK, PPCCOM, PPCVLE, {BOE, BI, BDMA}},
4162 {"bcla+", B(16,1,1), B_MASK, PPCCOM, PPCVLE, {BOE, BI, BDPA}},
4163 {"bcla", B(16,1,1), B_MASK, COM, PPCVLE, {BO, BI, BDA}},
4165 {"svc", SC(17,0,0), SC_MASK, POWER, PPCVLE, {SVC_LEV, FL1, FL2}},
4166 {"svcl", SC(17,0,1), SC_MASK, POWER, PPCVLE, {SVC_LEV, FL1, FL2}},
4167 {"sc", SC(17,1,0), SC_MASK, PPC, PPCVLE, {LEV}},
4168 {"svca", SC(17,1,0), SC_MASK, PWRCOM, PPCVLE, {SV}},
4169 {"svcla", SC(17,1,1), SC_MASK, POWER, PPCVLE, {SV}},
4171 {"b", B(18,0,0), B_MASK, COM, PPCVLE, {LI}},
4172 {"bl", B(18,0,1), B_MASK, COM, PPCVLE, {LI}},
4173 {"ba", B(18,1,0), B_MASK, COM, PPCVLE, {LIA}},
4174 {"bla", B(18,1,1), B_MASK, COM, PPCVLE, {LIA}},
4176 {"mcrf", XL(19,0), XLBB_MASK|(3<<21)|(3<<16), COM, PPCVLE, {BF, BFA}},
4178 {"addpcis", DX(19,2), DX_MASK, POWER9, PPCVLE, {RT, DXD}},
4179 {"subpcis", DX(19,2), DX_MASK, POWER9, PPCVLE, {RT, NDXD}},
4181 {"bdnzlr", XLO(19,BODNZ,16,0), XLBOBIBB_MASK, PPCCOM, PPCVLE, {0}},
4182 {"bdnzlr-", XLO(19,BODNZ,16,0), XLBOBIBB_MASK, PPCCOM, ISA_V2|PPCVLE, {0}},
4183 {"bdnzlrl", XLO(19,BODNZ,16,1), XLBOBIBB_MASK, PPCCOM, PPCVLE, {0}},
4184 {"bdnzlrl-", XLO(19,BODNZ,16,1), XLBOBIBB_MASK, PPCCOM, ISA_V2|PPCVLE, {0}},
4185 {"bdnzlr+", XLO(19,BODNZP,16,0), XLBOBIBB_MASK, PPCCOM, ISA_V2|PPCVLE, {0}},
4186 {"bdnzlrl+", XLO(19,BODNZP,16,1), XLBOBIBB_MASK, PPCCOM, ISA_V2|PPCVLE, {0}},
4187 {"bdzlr", XLO(19,BODZ,16,0), XLBOBIBB_MASK, PPCCOM, PPCVLE, {0}},
4188 {"bdzlr-", XLO(19,BODZ,16,0), XLBOBIBB_MASK, PPCCOM, ISA_V2|PPCVLE, {0}},
4189 {"bdzlrl", XLO(19,BODZ,16,1), XLBOBIBB_MASK, PPCCOM, PPCVLE, {0}},
4190 {"bdzlrl-", XLO(19,BODZ,16,1), XLBOBIBB_MASK, PPCCOM, ISA_V2|PPCVLE, {0}},
4191 {"bdzlr+", XLO(19,BODZP,16,0), XLBOBIBB_MASK, PPCCOM, ISA_V2|PPCVLE, {0}},
4192 {"bdzlrl+", XLO(19,BODZP,16,1), XLBOBIBB_MASK, PPCCOM, ISA_V2|PPCVLE, {0}},
4193 {"blr", XLO(19,BOU,16,0), XLBOBIBB_MASK, PPCCOM, PPCVLE, {0}},
4194 {"br", XLO(19,BOU,16,0), XLBOBIBB_MASK, PWRCOM, PPCVLE, {0}},
4195 {"blrl", XLO(19,BOU,16,1), XLBOBIBB_MASK, PPCCOM, PPCVLE, {0}},
4196 {"brl", XLO(19,BOU,16,1), XLBOBIBB_MASK, PWRCOM, PPCVLE, {0}},
4197 {"bdnzlr-", XLO(19,BODNZM4,16,0), XLBOBIBB_MASK, ISA_V2, PPCVLE, {0}},
4198 {"bdnzlrl-", XLO(19,BODNZM4,16,1), XLBOBIBB_MASK, ISA_V2, PPCVLE, {0}},
4199 {"bdnzlr+", XLO(19,BODNZP4,16,0), XLBOBIBB_MASK, ISA_V2, PPCVLE, {0}},
4200 {"bdnzlrl+", XLO(19,BODNZP4,16,1), XLBOBIBB_MASK, ISA_V2, PPCVLE, {0}},
4201 {"bdzlr-", XLO(19,BODZM4,16,0), XLBOBIBB_MASK, ISA_V2, PPCVLE, {0}},
4202 {"bdzlrl-", XLO(19,BODZM4,16,1), XLBOBIBB_MASK, ISA_V2, PPCVLE, {0}},
4203 {"bdzlr+", XLO(19,BODZP4,16,0), XLBOBIBB_MASK, ISA_V2, PPCVLE, {0}},
4204 {"bdzlrl+", XLO(19,BODZP4,16,1), XLBOBIBB_MASK, ISA_V2, PPCVLE, {0}},
4206 {"bgelr", XLOCB(19,BOF,CBLT,16,0), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}},
4207 {"bgelr-", XLOCB(19,BOF,CBLT,16,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
4208 {"bger", XLOCB(19,BOF,CBLT,16,0), XLBOCBBB_MASK, PWRCOM, PPCVLE, {CR}},
4209 {"bnllr", XLOCB(19,BOF,CBLT,16,0), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}},
4210 {"bnllr-", XLOCB(19,BOF,CBLT,16,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
4211 {"bnlr", XLOCB(19,BOF,CBLT,16,0), XLBOCBBB_MASK, PWRCOM, PPCVLE, {CR}},
4212 {"bgelrl", XLOCB(19,BOF,CBLT,16,1), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}},
4213 {"bgelrl-", XLOCB(19,BOF,CBLT,16,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
4214 {"bgerl", XLOCB(19,BOF,CBLT,16,1), XLBOCBBB_MASK, PWRCOM, PPCVLE, {CR}},
4215 {"bnllrl", XLOCB(19,BOF,CBLT,16,1), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}},
4216 {"bnllrl-", XLOCB(19,BOF,CBLT,16,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
4217 {"bnlrl", XLOCB(19,BOF,CBLT,16,1), XLBOCBBB_MASK, PWRCOM, PPCVLE, {CR}},
4218 {"blelr", XLOCB(19,BOF,CBGT,16,0), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}},
4219 {"blelr-", XLOCB(19,BOF,CBGT,16,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
4220 {"bler", XLOCB(19,BOF,CBGT,16,0), XLBOCBBB_MASK, PWRCOM, PPCVLE, {CR}},
4221 {"bnglr", XLOCB(19,BOF,CBGT,16,0), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}},
4222 {"bnglr-", XLOCB(19,BOF,CBGT,16,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
4223 {"bngr", XLOCB(19,BOF,CBGT,16,0), XLBOCBBB_MASK, PWRCOM, PPCVLE, {CR}},
4224 {"blelrl", XLOCB(19,BOF,CBGT,16,1), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}},
4225 {"blelrl-", XLOCB(19,BOF,CBGT,16,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
4226 {"blerl", XLOCB(19,BOF,CBGT,16,1), XLBOCBBB_MASK, PWRCOM, PPCVLE, {CR}},
4227 {"bnglrl", XLOCB(19,BOF,CBGT,16,1), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}},
4228 {"bnglrl-", XLOCB(19,BOF,CBGT,16,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
4229 {"bngrl", XLOCB(19,BOF,CBGT,16,1), XLBOCBBB_MASK, PWRCOM, PPCVLE, {CR}},
4230 {"bnelr", XLOCB(19,BOF,CBEQ,16,0), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}},
4231 {"bnelr-", XLOCB(19,BOF,CBEQ,16,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
4232 {"bner", XLOCB(19,BOF,CBEQ,16,0), XLBOCBBB_MASK, PWRCOM, PPCVLE, {CR}},
4233 {"bnelrl", XLOCB(19,BOF,CBEQ,16,1), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}},
4234 {"bnelrl-", XLOCB(19,BOF,CBEQ,16,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
4235 {"bnerl", XLOCB(19,BOF,CBEQ,16,1), XLBOCBBB_MASK, PWRCOM, PPCVLE, {CR}},
4236 {"bnslr", XLOCB(19,BOF,CBSO,16,0), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}},
4237 {"bnslr-", XLOCB(19,BOF,CBSO,16,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
4238 {"bnsr", XLOCB(19,BOF,CBSO,16,0), XLBOCBBB_MASK, PWRCOM, PPCVLE, {CR}},
4239 {"bnulr", XLOCB(19,BOF,CBSO,16,0), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}},
4240 {"bnulr-", XLOCB(19,BOF,CBSO,16,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
4241 {"bnslrl", XLOCB(19,BOF,CBSO,16,1), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}},
4242 {"bnslrl-", XLOCB(19,BOF,CBSO,16,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
4243 {"bnsrl", XLOCB(19,BOF,CBSO,16,1), XLBOCBBB_MASK, PWRCOM, PPCVLE, {CR}},
4244 {"bnulrl", XLOCB(19,BOF,CBSO,16,1), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}},
4245 {"bnulrl-", XLOCB(19,BOF,CBSO,16,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
4246 {"bgelr+", XLOCB(19,BOFP,CBLT,16,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
4247 {"bnllr+", XLOCB(19,BOFP,CBLT,16,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
4248 {"bgelrl+", XLOCB(19,BOFP,CBLT,16,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
4249 {"bnllrl+", XLOCB(19,BOFP,CBLT,16,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
4250 {"blelr+", XLOCB(19,BOFP,CBGT,16,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
4251 {"bnglr+", XLOCB(19,BOFP,CBGT,16,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
4252 {"blelrl+", XLOCB(19,BOFP,CBGT,16,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
4253 {"bnglrl+", XLOCB(19,BOFP,CBGT,16,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
4254 {"bnelr+", XLOCB(19,BOFP,CBEQ,16,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
4255 {"bnelrl+", XLOCB(19,BOFP,CBEQ,16,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
4256 {"bnslr+", XLOCB(19,BOFP,CBSO,16,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
4257 {"bnulr+", XLOCB(19,BOFP,CBSO,16,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
4258 {"bnslrl+", XLOCB(19,BOFP,CBSO,16,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
4259 {"bnulrl+", XLOCB(19,BOFP,CBSO,16,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
4260 {"bgelr-", XLOCB(19,BOFM4,CBLT,16,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
4261 {"bnllr-", XLOCB(19,BOFM4,CBLT,16,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
4262 {"bgelrl-", XLOCB(19,BOFM4,CBLT,16,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
4263 {"bnllrl-", XLOCB(19,BOFM4,CBLT,16,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
4264 {"blelr-", XLOCB(19,BOFM4,CBGT,16,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
4265 {"bnglr-", XLOCB(19,BOFM4,CBGT,16,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
4266 {"blelrl-", XLOCB(19,BOFM4,CBGT,16,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
4267 {"bnglrl-", XLOCB(19,BOFM4,CBGT,16,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
4268 {"bnelr-", XLOCB(19,BOFM4,CBEQ,16,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
4269 {"bnelrl-", XLOCB(19,BOFM4,CBEQ,16,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
4270 {"bnslr-", XLOCB(19,BOFM4,CBSO,16,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
4271 {"bnulr-", XLOCB(19,BOFM4,CBSO,16,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
4272 {"bnslrl-", XLOCB(19,BOFM4,CBSO,16,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
4273 {"bnulrl-", XLOCB(19,BOFM4,CBSO,16,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
4274 {"bgelr+", XLOCB(19,BOFP4,CBLT,16,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
4275 {"bnllr+", XLOCB(19,BOFP4,CBLT,16,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
4276 {"bgelrl+", XLOCB(19,BOFP4,CBLT,16,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
4277 {"bnllrl+", XLOCB(19,BOFP4,CBLT,16,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
4278 {"blelr+", XLOCB(19,BOFP4,CBGT,16,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
4279 {"bnglr+", XLOCB(19,BOFP4,CBGT,16,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
4280 {"blelrl+", XLOCB(19,BOFP4,CBGT,16,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
4281 {"bnglrl+", XLOCB(19,BOFP4,CBGT,16,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
4282 {"bnelr+", XLOCB(19,BOFP4,CBEQ,16,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
4283 {"bnelrl+", XLOCB(19,BOFP4,CBEQ,16,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
4284 {"bnslr+", XLOCB(19,BOFP4,CBSO,16,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
4285 {"bnulr+", XLOCB(19,BOFP4,CBSO,16,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
4286 {"bnslrl+", XLOCB(19,BOFP4,CBSO,16,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
4287 {"bnulrl+", XLOCB(19,BOFP4,CBSO,16,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
4288 {"bltlr", XLOCB(19,BOT,CBLT,16,0), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}},
4289 {"bltlr-", XLOCB(19,BOT,CBLT,16,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
4290 {"bltr", XLOCB(19,BOT,CBLT,16,0), XLBOCBBB_MASK, PWRCOM, PPCVLE, {CR}},
4291 {"bltlrl", XLOCB(19,BOT,CBLT,16,1), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}},
4292 {"bltlrl-", XLOCB(19,BOT,CBLT,16,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
4293 {"bltrl", XLOCB(19,BOT,CBLT,16,1), XLBOCBBB_MASK, PWRCOM, PPCVLE, {CR}},
4294 {"bgtlr", XLOCB(19,BOT,CBGT,16,0), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}},
4295 {"bgtlr-", XLOCB(19,BOT,CBGT,16,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
4296 {"bgtr", XLOCB(19,BOT,CBGT,16,0), XLBOCBBB_MASK, PWRCOM, PPCVLE, {CR}},
4297 {"bgtlrl", XLOCB(19,BOT,CBGT,16,1), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}},
4298 {"bgtlrl-", XLOCB(19,BOT,CBGT,16,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
4299 {"bgtrl", XLOCB(19,BOT,CBGT,16,1), XLBOCBBB_MASK, PWRCOM, PPCVLE, {CR}},
4300 {"beqlr", XLOCB(19,BOT,CBEQ,16,0), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}},
4301 {"beqlr-", XLOCB(19,BOT,CBEQ,16,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
4302 {"beqr", XLOCB(19,BOT,CBEQ,16,0), XLBOCBBB_MASK, PWRCOM, PPCVLE, {CR}},
4303 {"beqlrl", XLOCB(19,BOT,CBEQ,16,1), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}},
4304 {"beqlrl-", XLOCB(19,BOT,CBEQ,16,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
4305 {"beqrl", XLOCB(19,BOT,CBEQ,16,1), XLBOCBBB_MASK, PWRCOM, PPCVLE, {CR}},
4306 {"bsolr", XLOCB(19,BOT,CBSO,16,0), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}},
4307 {"bsolr-", XLOCB(19,BOT,CBSO,16,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
4308 {"bsor", XLOCB(19,BOT,CBSO,16,0), XLBOCBBB_MASK, PWRCOM, PPCVLE, {CR}},
4309 {"bunlr", XLOCB(19,BOT,CBSO,16,0), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}},
4310 {"bunlr-", XLOCB(19,BOT,CBSO,16,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
4311 {"bsolrl", XLOCB(19,BOT,CBSO,16,1), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}},
4312 {"bsolrl-", XLOCB(19,BOT,CBSO,16,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
4313 {"bsorl", XLOCB(19,BOT,CBSO,16,1), XLBOCBBB_MASK, PWRCOM, PPCVLE, {CR}},
4314 {"bunlrl", XLOCB(19,BOT,CBSO,16,1), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}},
4315 {"bunlrl-", XLOCB(19,BOT,CBSO,16,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
4316 {"bltlr+", XLOCB(19,BOTP,CBLT,16,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
4317 {"bltlrl+", XLOCB(19,BOTP,CBLT,16,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
4318 {"bgtlr+", XLOCB(19,BOTP,CBGT,16,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
4319 {"bgtlrl+", XLOCB(19,BOTP,CBGT,16,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
4320 {"beqlr+", XLOCB(19,BOTP,CBEQ,16,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
4321 {"beqlrl+", XLOCB(19,BOTP,CBEQ,16,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
4322 {"bsolr+", XLOCB(19,BOTP,CBSO,16,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
4323 {"bunlr+", XLOCB(19,BOTP,CBSO,16,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
4324 {"bsolrl+", XLOCB(19,BOTP,CBSO,16,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
4325 {"bunlrl+", XLOCB(19,BOTP,CBSO,16,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
4326 {"bltlr-", XLOCB(19,BOTM4,CBLT,16,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
4327 {"bltlrl-", XLOCB(19,BOTM4,CBLT,16,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
4328 {"bgtlr-", XLOCB(19,BOTM4,CBGT,16,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
4329 {"bgtlrl-", XLOCB(19,BOTM4,CBGT,16,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
4330 {"beqlr-", XLOCB(19,BOTM4,CBEQ,16,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
4331 {"beqlrl-", XLOCB(19,BOTM4,CBEQ,16,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
4332 {"bsolr-", XLOCB(19,BOTM4,CBSO,16,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
4333 {"bunlr-", XLOCB(19,BOTM4,CBSO,16,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
4334 {"bsolrl-", XLOCB(19,BOTM4,CBSO,16,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
4335 {"bunlrl-", XLOCB(19,BOTM4,CBSO,16,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
4336 {"bltlr+", XLOCB(19,BOTP4,CBLT,16,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
4337 {"bltlrl+", XLOCB(19,BOTP4,CBLT,16,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
4338 {"bgtlr+", XLOCB(19,BOTP4,CBGT,16,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
4339 {"bgtlrl+", XLOCB(19,BOTP4,CBGT,16,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
4340 {"beqlr+", XLOCB(19,BOTP4,CBEQ,16,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
4341 {"beqlrl+", XLOCB(19,BOTP4,CBEQ,16,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
4342 {"bsolr+", XLOCB(19,BOTP4,CBSO,16,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
4343 {"bunlr+", XLOCB(19,BOTP4,CBSO,16,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
4344 {"bsolrl+", XLOCB(19,BOTP4,CBSO,16,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
4345 {"bunlrl+", XLOCB(19,BOTP4,CBSO,16,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
4347 {"bdnzflr", XLO(19,BODNZF,16,0), XLBOBB_MASK, PPCCOM, PPCVLE, {BI}},
4348 {"bdnzflr-", XLO(19,BODNZF,16,0), XLBOBB_MASK, PPCCOM, ISA_V2|PPCVLE, {BI}},
4349 {"bdnzflrl", XLO(19,BODNZF,16,1), XLBOBB_MASK, PPCCOM, PPCVLE, {BI}},
4350 {"bdnzflrl-",XLO(19,BODNZF,16,1), XLBOBB_MASK, PPCCOM, ISA_V2|PPCVLE, {BI}},
4351 {"bdnzflr+", XLO(19,BODNZFP,16,0), XLBOBB_MASK, PPCCOM, ISA_V2|PPCVLE, {BI}},
4352 {"bdnzflrl+",XLO(19,BODNZFP,16,1), XLBOBB_MASK, PPCCOM, ISA_V2|PPCVLE, {BI}},
4353 {"bdzflr", XLO(19,BODZF,16,0), XLBOBB_MASK, PPCCOM, PPCVLE, {BI}},
4354 {"bdzflr-", XLO(19,BODZF,16,0), XLBOBB_MASK, PPCCOM, ISA_V2|PPCVLE, {BI}},
4355 {"bdzflrl", XLO(19,BODZF,16,1), XLBOBB_MASK, PPCCOM, PPCVLE, {BI}},
4356 {"bdzflrl-", XLO(19,BODZF,16,1), XLBOBB_MASK, PPCCOM, ISA_V2|PPCVLE, {BI}},
4357 {"bdzflr+", XLO(19,BODZFP,16,0), XLBOBB_MASK, PPCCOM, ISA_V2|PPCVLE, {BI}},
4358 {"bdzflrl+", XLO(19,BODZFP,16,1), XLBOBB_MASK, PPCCOM, ISA_V2|PPCVLE, {BI}},
4359 {"bflr", XLO(19,BOF,16,0), XLBOBB_MASK, PPCCOM, PPCVLE, {BI}},
4360 {"bflr-", XLO(19,BOF,16,0), XLBOBB_MASK, PPCCOM, ISA_V2|PPCVLE, {BI}},
4361 {"bbfr", XLO(19,BOF,16,0), XLBOBB_MASK, PWRCOM, PPCVLE, {BI}},
4362 {"bflrl", XLO(19,BOF,16,1), XLBOBB_MASK, PPCCOM, PPCVLE, {BI}},
4363 {"bflrl-", XLO(19,BOF,16,1), XLBOBB_MASK, PPCCOM, ISA_V2|PPCVLE, {BI}},
4364 {"bbfrl", XLO(19,BOF,16,1), XLBOBB_MASK, PWRCOM, PPCVLE, {BI}},
4365 {"bflr+", XLO(19,BOFP,16,0), XLBOBB_MASK, PPCCOM, ISA_V2|PPCVLE, {BI}},
4366 {"bflrl+", XLO(19,BOFP,16,1), XLBOBB_MASK, PPCCOM, ISA_V2|PPCVLE, {BI}},
4367 {"bflr-", XLO(19,BOFM4,16,0), XLBOBB_MASK, ISA_V2, PPCVLE, {BI}},
4368 {"bflrl-", XLO(19,BOFM4,16,1), XLBOBB_MASK, ISA_V2, PPCVLE, {BI}},
4369 {"bflr+", XLO(19,BOFP4,16,0), XLBOBB_MASK, ISA_V2, PPCVLE, {BI}},
4370 {"bflrl+", XLO(19,BOFP4,16,1), XLBOBB_MASK, ISA_V2, PPCVLE, {BI}},
4371 {"bdnztlr", XLO(19,BODNZT,16,0), XLBOBB_MASK, PPCCOM, PPCVLE, {BI}},
4372 {"bdnztlr-", XLO(19,BODNZT,16,0), XLBOBB_MASK, PPCCOM, ISA_V2|PPCVLE, {BI}},
4373 {"bdnztlrl", XLO(19,BODNZT,16,1), XLBOBB_MASK, PPCCOM, PPCVLE, {BI}},
4374 {"bdnztlrl-", XLO(19,BODNZT,16,1), XLBOBB_MASK, PPCCOM, ISA_V2|PPCVLE, {BI}},
4375 {"bdnztlr+", XLO(19,BODNZTP,16,0), XLBOBB_MASK, PPCCOM, ISA_V2|PPCVLE, {BI}},
4376 {"bdnztlrl+", XLO(19,BODNZTP,16,1), XLBOBB_MASK, PPCCOM, ISA_V2|PPCVLE, {BI}},
4377 {"bdztlr", XLO(19,BODZT,16,0), XLBOBB_MASK, PPCCOM, PPCVLE, {BI}},
4378 {"bdztlr-", XLO(19,BODZT,16,0), XLBOBB_MASK, PPCCOM, ISA_V2|PPCVLE, {BI}},
4379 {"bdztlrl", XLO(19,BODZT,16,1), XLBOBB_MASK, PPCCOM, PPCVLE, {BI}},
4380 {"bdztlrl-", XLO(19,BODZT,16,1), XLBOBB_MASK, PPCCOM, ISA_V2|PPCVLE, {BI}},
4381 {"bdztlr+", XLO(19,BODZTP,16,0), XLBOBB_MASK, PPCCOM, ISA_V2|PPCVLE, {BI}},
4382 {"bdztlrl+", XLO(19,BODZTP,16,1), XLBOBB_MASK, PPCCOM, ISA_V2|PPCVLE, {BI}},
4383 {"btlr", XLO(19,BOT,16,0), XLBOBB_MASK, PPCCOM, PPCVLE, {BI}},
4384 {"btlr-", XLO(19,BOT,16,0), XLBOBB_MASK, PPCCOM, ISA_V2|PPCVLE, {BI}},
4385 {"bbtr", XLO(19,BOT,16,0), XLBOBB_MASK, PWRCOM, PPCVLE, {BI}},
4386 {"btlrl", XLO(19,BOT,16,1), XLBOBB_MASK, PPCCOM, PPCVLE, {BI}},
4387 {"btlrl-", XLO(19,BOT,16,1), XLBOBB_MASK, PPCCOM, ISA_V2|PPCVLE, {BI}},
4388 {"bbtrl", XLO(19,BOT,16,1), XLBOBB_MASK, PWRCOM, PPCVLE, {BI}},
4389 {"btlr+", XLO(19,BOTP,16,0), XLBOBB_MASK, PPCCOM, ISA_V2|PPCVLE, {BI}},
4390 {"btlrl+", XLO(19,BOTP,16,1), XLBOBB_MASK, PPCCOM, ISA_V2|PPCVLE, {BI}},
4391 {"btlr-", XLO(19,BOTM4,16,0), XLBOBB_MASK, ISA_V2, PPCVLE, {BI}},
4392 {"btlrl-", XLO(19,BOTM4,16,1), XLBOBB_MASK, ISA_V2, PPCVLE, {BI}},
4393 {"btlr+", XLO(19,BOTP4,16,0), XLBOBB_MASK, ISA_V2, PPCVLE, {BI}},
4394 {"btlrl+", XLO(19,BOTP4,16,1), XLBOBB_MASK, ISA_V2, PPCVLE, {BI}},
4396 {"bclr-", XLYLK(19,16,0,0), XLYBB_MASK, PPCCOM, PPCVLE, {BOE, BI}},
4397 {"bclrl-", XLYLK(19,16,0,1), XLYBB_MASK, PPCCOM, PPCVLE, {BOE, BI}},
4398 {"bclr+", XLYLK(19,16,1,0), XLYBB_MASK, PPCCOM, PPCVLE, {BOE, BI}},
4399 {"bclrl+", XLYLK(19,16,1,1), XLYBB_MASK, PPCCOM, PPCVLE, {BOE, BI}},
4400 {"bclr", XLLK(19,16,0), XLBH_MASK, PPCCOM, PPCVLE, {BO, BI, BH}},
4401 {"bcr", XLLK(19,16,0), XLBB_MASK, PWRCOM, PPCVLE, {BO, BI}},
4402 {"bclrl", XLLK(19,16,1), XLBH_MASK, PPCCOM, PPCVLE, {BO, BI, BH}},
4403 {"bcrl", XLLK(19,16,1), XLBB_MASK, PWRCOM, PPCVLE, {BO, BI}},
4405 {"rfid", XL(19,18), 0xffffffff, PPC64, PPCVLE, {0}},
4407 {"crnot", XL(19,33), XL_MASK, PPCCOM, PPCVLE, {BT, BA, BBA}},
4408 {"crnor", XL(19,33), XL_MASK, COM, PPCVLE, {BT, BA, BB}},
4409 {"rfmci", X(19,38), 0xffffffff, PPCRFMCI|PPCA2|PPC476, PPCVLE, {0}},
4411 {"rfdi", XL(19,39), 0xffffffff, E500MC, PPCVLE, {0}},
4412 {"rfi", XL(19,50), 0xffffffff, COM, PPCVLE, {0}},
4413 {"rfci", XL(19,51), 0xffffffff, PPC403|BOOKE|PPCE300|PPCA2|PPC476, PPCVLE, {0}},
4415 {"rfsvc", XL(19,82), 0xffffffff, POWER, PPCVLE, {0}},
4417 {"rfgi", XL(19,102), 0xffffffff, E500MC|PPCA2, PPCVLE, {0}},
4419 {"crandc", XL(19,129), XL_MASK, COM, PPCVLE, {BT, BA, BB}},
4421 {"rfebb", XL(19,146), XLS_MASK, POWER8, PPCVLE, {SXL}},
4423 {"isync", XL(19,150), 0xffffffff, PPCCOM, PPCVLE, {0}},
4424 {"ics", XL(19,150), 0xffffffff, PWRCOM, PPCVLE, {0}},
4426 {"crclr", XL(19,193), XL_MASK, PPCCOM, PPCVLE, {BT, BAT, BBA}},
4427 {"crxor", XL(19,193), XL_MASK, COM, PPCVLE, {BT, BA, BB}},
4429 {"dnh", X(19,198), X_MASK, E500MC, PPCVLE, {DUI, DUIS}},
4431 {"crnand", XL(19,225), XL_MASK, COM, PPCVLE, {BT, BA, BB}},
4433 {"crand", XL(19,257), XL_MASK, COM, PPCVLE, {BT, BA, BB}},
4435 {"hrfid", XL(19,274), 0xffffffff, POWER5|CELL, PPC476|PPCVLE, {0}},
4437 {"crset", XL(19,289), XL_MASK, PPCCOM, PPCVLE, {BT, BAT, BBA}},
4438 {"creqv", XL(19,289), XL_MASK, COM, PPCVLE, {BT, BA, BB}},
4440 {"urfid", XL(19,306), 0xffffffff, POWER9, PPCVLE, {0}},
4441 {"stop", XL(19,370), 0xffffffff, POWER9, PPCVLE, {0}},
4443 {"doze", XL(19,402), 0xffffffff, POWER6, POWER9|PPCVLE, {0}},
4445 {"crorc", XL(19,417), XL_MASK, COM, PPCVLE, {BT, BA, BB}},
4447 {"nap", XL(19,434), 0xffffffff, POWER6, POWER9|PPCVLE, {0}},
4449 {"crmove", XL(19,449), XL_MASK, PPCCOM, PPCVLE, {BT, BA, BBA}},
4450 {"cror", XL(19,449), XL_MASK, COM, PPCVLE, {BT, BA, BB}},
4452 {"sleep", XL(19,466), 0xffffffff, POWER6, POWER9|PPCVLE, {0}},
4453 {"rvwinkle", XL(19,498), 0xffffffff, POWER6, POWER9|PPCVLE, {0}},
4455 {"bctr", XLO(19,BOU,528,0), XLBOBIBB_MASK, COM, PPCVLE, {0}},
4456 {"bctrl", XLO(19,BOU,528,1), XLBOBIBB_MASK, COM, PPCVLE, {0}},
4458 {"bgectr", XLOCB(19,BOF,CBLT,528,0), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}},
4459 {"bgectr-", XLOCB(19,BOF,CBLT,528,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
4460 {"bnlctr", XLOCB(19,BOF,CBLT,528,0), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}},
4461 {"bnlctr-", XLOCB(19,BOF,CBLT,528,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
4462 {"bgectrl", XLOCB(19,BOF,CBLT,528,1), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}},
4463 {"bgectrl-",XLOCB(19,BOF,CBLT,528,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
4464 {"bnlctrl", XLOCB(19,BOF,CBLT,528,1), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}},
4465 {"bnlctrl-",XLOCB(19,BOF,CBLT,528,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
4466 {"blectr", XLOCB(19,BOF,CBGT,528,0), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}},
4467 {"blectr-", XLOCB(19,BOF,CBGT,528,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
4468 {"bngctr", XLOCB(19,BOF,CBGT,528,0), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}},
4469 {"bngctr-", XLOCB(19,BOF,CBGT,528,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
4470 {"blectrl", XLOCB(19,BOF,CBGT,528,1), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}},
4471 {"blectrl-",XLOCB(19,BOF,CBGT,528,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
4472 {"bngctrl", XLOCB(19,BOF,CBGT,528,1), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}},
4473 {"bngctrl-",XLOCB(19,BOF,CBGT,528,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
4474 {"bnectr", XLOCB(19,BOF,CBEQ,528,0), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}},
4475 {"bnectr-", XLOCB(19,BOF,CBEQ,528,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
4476 {"bnectrl", XLOCB(19,BOF,CBEQ,528,1), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}},
4477 {"bnectrl-",XLOCB(19,BOF,CBEQ,528,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
4478 {"bnsctr", XLOCB(19,BOF,CBSO,528,0), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}},
4479 {"bnsctr-", XLOCB(19,BOF,CBSO,528,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
4480 {"bnuctr", XLOCB(19,BOF,CBSO,528,0), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}},
4481 {"bnuctr-", XLOCB(19,BOF,CBSO,528,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
4482 {"bnsctrl", XLOCB(19,BOF,CBSO,528,1), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}},
4483 {"bnsctrl-",XLOCB(19,BOF,CBSO,528,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
4484 {"bnuctrl", XLOCB(19,BOF,CBSO,528,1), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}},
4485 {"bnuctrl-",XLOCB(19,BOF,CBSO,528,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
4486 {"bgectr+", XLOCB(19,BOFP,CBLT,528,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
4487 {"bnlctr+", XLOCB(19,BOFP,CBLT,528,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
4488 {"bgectrl+",XLOCB(19,BOFP,CBLT,528,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
4489 {"bnlctrl+",XLOCB(19,BOFP,CBLT,528,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
4490 {"blectr+", XLOCB(19,BOFP,CBGT,528,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
4491 {"bngctr+", XLOCB(19,BOFP,CBGT,528,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
4492 {"blectrl+",XLOCB(19,BOFP,CBGT,528,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
4493 {"bngctrl+",XLOCB(19,BOFP,CBGT,528,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
4494 {"bnectr+", XLOCB(19,BOFP,CBEQ,528,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
4495 {"bnectrl+",XLOCB(19,BOFP,CBEQ,528,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
4496 {"bnsctr+", XLOCB(19,BOFP,CBSO,528,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
4497 {"bnuctr+", XLOCB(19,BOFP,CBSO,528,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
4498 {"bnsctrl+",XLOCB(19,BOFP,CBSO,528,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
4499 {"bnuctrl+",XLOCB(19,BOFP,CBSO,528,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
4500 {"bgectr-", XLOCB(19,BOFM4,CBLT,528,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
4501 {"bnlctr-", XLOCB(19,BOFM4,CBLT,528,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
4502 {"bgectrl-",XLOCB(19,BOFM4,CBLT,528,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
4503 {"bnlctrl-",XLOCB(19,BOFM4,CBLT,528,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
4504 {"blectr-", XLOCB(19,BOFM4,CBGT,528,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
4505 {"bngctr-", XLOCB(19,BOFM4,CBGT,528,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
4506 {"blectrl-",XLOCB(19,BOFM4,CBGT,528,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
4507 {"bngctrl-",XLOCB(19,BOFM4,CBGT,528,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
4508 {"bnectr-", XLOCB(19,BOFM4,CBEQ,528,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
4509 {"bnectrl-",XLOCB(19,BOFM4,CBEQ,528,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
4510 {"bnsctr-", XLOCB(19,BOFM4,CBSO,528,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
4511 {"bnuctr-", XLOCB(19,BOFM4,CBSO,528,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
4512 {"bnsctrl-",XLOCB(19,BOFM4,CBSO,528,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
4513 {"bnuctrl-",XLOCB(19,BOFM4,CBSO,528,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
4514 {"bgectr+", XLOCB(19,BOFP4,CBLT,528,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
4515 {"bnlctr+", XLOCB(19,BOFP4,CBLT,528,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
4516 {"bgectrl+",XLOCB(19,BOFP4,CBLT,528,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
4517 {"bnlctrl+",XLOCB(19,BOFP4,CBLT,528,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
4518 {"blectr+", XLOCB(19,BOFP4,CBGT,528,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
4519 {"bngctr+", XLOCB(19,BOFP4,CBGT,528,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
4520 {"blectrl+",XLOCB(19,BOFP4,CBGT,528,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
4521 {"bngctrl+",XLOCB(19,BOFP4,CBGT,528,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
4522 {"bnectr+", XLOCB(19,BOFP4,CBEQ,528,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
4523 {"bnectrl+",XLOCB(19,BOFP4,CBEQ,528,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
4524 {"bnsctr+", XLOCB(19,BOFP4,CBSO,528,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
4525 {"bnuctr+", XLOCB(19,BOFP4,CBSO,528,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
4526 {"bnsctrl+",XLOCB(19,BOFP4,CBSO,528,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
4527 {"bnuctrl+",XLOCB(19,BOFP4,CBSO,528,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
4528 {"bltctr", XLOCB(19,BOT,CBLT,528,0), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}},
4529 {"bltctr-", XLOCB(19,BOT,CBLT,528,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
4530 {"bltctrl", XLOCB(19,BOT,CBLT,528,1), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}},
4531 {"bltctrl-",XLOCB(19,BOT,CBLT,528,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
4532 {"bgtctr", XLOCB(19,BOT,CBGT,528,0), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}},
4533 {"bgtctr-", XLOCB(19,BOT,CBGT,528,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
4534 {"bgtctrl", XLOCB(19,BOT,CBGT,528,1), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}},
4535 {"bgtctrl-",XLOCB(19,BOT,CBGT,528,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
4536 {"beqctr", XLOCB(19,BOT,CBEQ,528,0), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}},
4537 {"beqctr-", XLOCB(19,BOT,CBEQ,528,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
4538 {"beqctrl", XLOCB(19,BOT,CBEQ,528,1), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}},
4539 {"beqctrl-",XLOCB(19,BOT,CBEQ,528,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
4540 {"bsoctr", XLOCB(19,BOT,CBSO,528,0), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}},
4541 {"bsoctr-", XLOCB(19,BOT,CBSO,528,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
4542 {"bunctr", XLOCB(19,BOT,CBSO,528,0), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}},
4543 {"bunctr-", XLOCB(19,BOT,CBSO,528,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
4544 {"bsoctrl", XLOCB(19,BOT,CBSO,528,1), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}},
4545 {"bsoctrl-",XLOCB(19,BOT,CBSO,528,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
4546 {"bunctrl", XLOCB(19,BOT,CBSO,528,1), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}},
4547 {"bunctrl-",XLOCB(19,BOT,CBSO,528,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
4548 {"bltctr+", XLOCB(19,BOTP,CBLT,528,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
4549 {"bltctrl+",XLOCB(19,BOTP,CBLT,528,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
4550 {"bgtctr+", XLOCB(19,BOTP,CBGT,528,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
4551 {"bgtctrl+",XLOCB(19,BOTP,CBGT,528,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
4552 {"beqctr+", XLOCB(19,BOTP,CBEQ,528,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
4553 {"beqctrl+",XLOCB(19,BOTP,CBEQ,528,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
4554 {"bsoctr+", XLOCB(19,BOTP,CBSO,528,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
4555 {"bunctr+", XLOCB(19,BOTP,CBSO,528,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
4556 {"bsoctrl+",XLOCB(19,BOTP,CBSO,528,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
4557 {"bunctrl+",XLOCB(19,BOTP,CBSO,528,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
4558 {"bltctr-", XLOCB(19,BOTM4,CBLT,528,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
4559 {"bltctrl-",XLOCB(19,BOTM4,CBLT,528,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
4560 {"bgtctr-", XLOCB(19,BOTM4,CBGT,528,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
4561 {"bgtctrl-",XLOCB(19,BOTM4,CBGT,528,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
4562 {"beqctr-", XLOCB(19,BOTM4,CBEQ,528,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
4563 {"beqctrl-",XLOCB(19,BOTM4,CBEQ,528,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
4564 {"bsoctr-", XLOCB(19,BOTM4,CBSO,528,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
4565 {"bunctr-", XLOCB(19,BOTM4,CBSO,528,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
4566 {"bsoctrl-",XLOCB(19,BOTM4,CBSO,528,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
4567 {"bunctrl-",XLOCB(19,BOTM4,CBSO,528,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
4568 {"bltctr+", XLOCB(19,BOTP4,CBLT,528,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
4569 {"bltctrl+",XLOCB(19,BOTP4,CBLT,528,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
4570 {"bgtctr+", XLOCB(19,BOTP4,CBGT,528,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
4571 {"bgtctrl+",XLOCB(19,BOTP4,CBGT,528,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
4572 {"beqctr+", XLOCB(19,BOTP4,CBEQ,528,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
4573 {"beqctrl+",XLOCB(19,BOTP4,CBEQ,528,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
4574 {"bsoctr+", XLOCB(19,BOTP4,CBSO,528,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
4575 {"bunctr+", XLOCB(19,BOTP4,CBSO,528,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
4576 {"bsoctrl+",XLOCB(19,BOTP4,CBSO,528,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
4577 {"bunctrl+",XLOCB(19,BOTP4,CBSO,528,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
4579 {"bfctr", XLO(19,BOF,528,0), XLBOBB_MASK, PPCCOM, PPCVLE, {BI}},
4580 {"bfctr-", XLO(19,BOF,528,0), XLBOBB_MASK, PPCCOM, ISA_V2|PPCVLE, {BI}},
4581 {"bfctrl", XLO(19,BOF,528,1), XLBOBB_MASK, PPCCOM, PPCVLE, {BI}},
4582 {"bfctrl-", XLO(19,BOF,528,1), XLBOBB_MASK, PPCCOM, ISA_V2|PPCVLE, {BI}},
4583 {"bfctr+", XLO(19,BOFP,528,0), XLBOBB_MASK, PPCCOM, ISA_V2|PPCVLE, {BI}},
4584 {"bfctrl+", XLO(19,BOFP,528,1), XLBOBB_MASK, PPCCOM, ISA_V2|PPCVLE, {BI}},
4585 {"bfctr-", XLO(19,BOFM4,528,0), XLBOBB_MASK, ISA_V2, PPCVLE, {BI}},
4586 {"bfctrl-", XLO(19,BOFM4,528,1), XLBOBB_MASK, ISA_V2, PPCVLE, {BI}},
4587 {"bfctr+", XLO(19,BOFP4,528,0), XLBOBB_MASK, ISA_V2, PPCVLE, {BI}},
4588 {"bfctrl+", XLO(19,BOFP4,528,1), XLBOBB_MASK, ISA_V2, PPCVLE, {BI}},
4589 {"btctr", XLO(19,BOT,528,0), XLBOBB_MASK, PPCCOM, PPCVLE, {BI}},
4590 {"btctr-", XLO(19,BOT,528,0), XLBOBB_MASK, PPCCOM, ISA_V2|PPCVLE, {BI}},
4591 {"btctrl", XLO(19,BOT,528,1), XLBOBB_MASK, PPCCOM, PPCVLE, {BI}},
4592 {"btctrl-", XLO(19,BOT,528,1), XLBOBB_MASK, PPCCOM, ISA_V2|PPCVLE, {BI}},
4593 {"btctr+", XLO(19,BOTP,528,0), XLBOBB_MASK, PPCCOM, ISA_V2|PPCVLE, {BI}},
4594 {"btctrl+", XLO(19,BOTP,528,1), XLBOBB_MASK, PPCCOM, ISA_V2|PPCVLE, {BI}},
4595 {"btctr-", XLO(19,BOTM4,528,0), XLBOBB_MASK, ISA_V2, PPCVLE, {BI}},
4596 {"btctrl-", XLO(19,BOTM4,528,1), XLBOBB_MASK, ISA_V2, PPCVLE, {BI}},
4597 {"btctr+", XLO(19,BOTP4,528,0), XLBOBB_MASK, ISA_V2, PPCVLE, {BI}},
4598 {"btctrl+", XLO(19,BOTP4,528,1), XLBOBB_MASK, ISA_V2, PPCVLE, {BI}},
4600 {"bcctr-", XLYLK(19,528,0,0), XLYBB_MASK, PPCCOM, PPCVLE, {BOE, BI}},
4601 {"bcctrl-", XLYLK(19,528,0,1), XLYBB_MASK, PPCCOM, PPCVLE, {BOE, BI}},
4602 {"bcctr+", XLYLK(19,528,1,0), XLYBB_MASK, PPCCOM, PPCVLE, {BOE, BI}},
4603 {"bcctrl+", XLYLK(19,528,1,1), XLYBB_MASK, PPCCOM, PPCVLE, {BOE, BI}},
4604 {"bcctr", XLLK(19,528,0), XLBH_MASK, PPCCOM, PPCVLE, {BO, BI, BH}},
4605 {"bcc", XLLK(19,528,0), XLBB_MASK, PWRCOM, PPCVLE, {BO, BI}},
4606 {"bcctrl", XLLK(19,528,1), XLBH_MASK, PPCCOM, PPCVLE, {BO, BI, BH}},
4607 {"bccl", XLLK(19,528,1), XLBB_MASK, PWRCOM, PPCVLE, {BO, BI}},
4609 {"bctar-", XLYLK(19,560,0,0), XLYBB_MASK, POWER8, PPCVLE, {BOE, BI}},
4610 {"bctarl-", XLYLK(19,560,0,1), XLYBB_MASK, POWER8, PPCVLE, {BOE, BI}},
4611 {"bctar+", XLYLK(19,560,1,0), XLYBB_MASK, POWER8, PPCVLE, {BOE, BI}},
4612 {"bctarl+", XLYLK(19,560,1,1), XLYBB_MASK, POWER8, PPCVLE, {BOE, BI}},
4613 {"bctar", XLLK(19,560,0), XLBH_MASK, POWER8, PPCVLE, {BO, BI, BH}},
4614 {"bctarl", XLLK(19,560,1), XLBH_MASK, POWER8, PPCVLE, {BO, BI, BH}},
4616 {"rlwimi", M(20,0), M_MASK, PPCCOM, PPCVLE, {RA, RS, SH, MBE, ME}},
4617 {"rlimi", M(20,0), M_MASK, PWRCOM, PPCVLE, {RA, RS, SH, MBE, ME}},
4619 {"rlwimi.", M(20,1), M_MASK, PPCCOM, PPCVLE, {RA, RS, SH, MBE, ME}},
4620 {"rlimi.", M(20,1), M_MASK, PWRCOM, PPCVLE, {RA, RS, SH, MBE, ME}},
4622 {"rotlwi", MME(21,31,0), MMBME_MASK, PPCCOM, PPCVLE, {RA, RS, SH}},
4623 {"clrlwi", MME(21,31,0), MSHME_MASK, PPCCOM, PPCVLE, {RA, RS, MB}},
4624 {"rlwinm", M(21,0), M_MASK, PPCCOM, PPCVLE, {RA, RS, SH, MBE, ME}},
4625 {"rlinm", M(21,0), M_MASK, PWRCOM, PPCVLE, {RA, RS, SH, MBE, ME}},
4626 {"rotlwi.", MME(21,31,1), MMBME_MASK, PPCCOM, PPCVLE, {RA, RS, SH}},
4627 {"clrlwi.", MME(21,31,1), MSHME_MASK, PPCCOM, PPCVLE, {RA, RS, MB}},
4628 {"rlwinm.", M(21,1), M_MASK, PPCCOM, PPCVLE, {RA, RS, SH, MBE, ME}},
4629 {"rlinm.", M(21,1), M_MASK, PWRCOM, PPCVLE, {RA, RS, SH, MBE, ME}},
4631 {"rlmi", M(22,0), M_MASK, M601, PPCVLE, {RA, RS, RB, MBE, ME}},
4632 {"rlmi.", M(22,1), M_MASK, M601, PPCVLE, {RA, RS, RB, MBE, ME}},
4634 {"rotlw", MME(23,31,0), MMBME_MASK, PPCCOM, PPCVLE, {RA, RS, RB}},
4635 {"rlwnm", M(23,0), M_MASK, PPCCOM, PPCVLE, {RA, RS, RB, MBE, ME}},
4636 {"rlnm", M(23,0), M_MASK, PWRCOM, PPCVLE, {RA, RS, RB, MBE, ME}},
4637 {"rotlw.", MME(23,31,1), MMBME_MASK, PPCCOM, PPCVLE, {RA, RS, RB}},
4638 {"rlwnm.", M(23,1), M_MASK, PPCCOM, PPCVLE, {RA, RS, RB, MBE, ME}},
4639 {"rlnm.", M(23,1), M_MASK, PWRCOM, PPCVLE, {RA, RS, RB, MBE, ME}},
4641 {"nop", OP(24), 0xffffffff, PPCCOM, PPCVLE, {0}},
4642 {"ori", OP(24), OP_MASK, PPCCOM, PPCVLE, {RA, RS, UI}},
4643 {"oril", OP(24), OP_MASK, PWRCOM, PPCVLE, {RA, RS, UI}},
4645 {"oris", OP(25), OP_MASK, PPCCOM, PPCVLE, {RA, RS, UI}},
4646 {"oriu", OP(25), OP_MASK, PWRCOM, PPCVLE, {RA, RS, UI}},
4648 {"xnop", OP(26), 0xffffffff, PPCCOM, PPCVLE, {0}},
4649 {"xori", OP(26), OP_MASK, PPCCOM, PPCVLE, {RA, RS, UI}},
4650 {"xoril", OP(26), OP_MASK, PWRCOM, PPCVLE, {RA, RS, UI}},
4652 {"xoris", OP(27), OP_MASK, PPCCOM, PPCVLE, {RA, RS, UI}},
4653 {"xoriu", OP(27), OP_MASK, PWRCOM, PPCVLE, {RA, RS, UI}},
4655 {"andi.", OP(28), OP_MASK, PPCCOM, PPCVLE, {RA, RS, UI}},
4656 {"andil.", OP(28), OP_MASK, PWRCOM, PPCVLE, {RA, RS, UI}},
4658 {"andis.", OP(29), OP_MASK, PPCCOM, PPCVLE, {RA, RS, UI}},
4659 {"andiu.", OP(29), OP_MASK, PWRCOM, PPCVLE, {RA, RS, UI}},
4661 {"rotldi", MD(30,0,0), MDMB_MASK, PPC64, PPCVLE, {RA, RS, SH6}},
4662 {"clrldi", MD(30,0,0), MDSH_MASK, PPC64, PPCVLE, {RA, RS, MB6}},
4663 {"rldicl", MD(30,0,0), MD_MASK, PPC64, PPCVLE, {RA, RS, SH6, MB6}},
4664 {"rotldi.", MD(30,0,1), MDMB_MASK, PPC64, PPCVLE, {RA, RS, SH6}},
4665 {"clrldi.", MD(30,0,1), MDSH_MASK, PPC64, PPCVLE, {RA, RS, MB6}},
4666 {"rldicl.", MD(30,0,1), MD_MASK, PPC64, PPCVLE, {RA, RS, SH6, MB6}},
4668 {"rldicr", MD(30,1,0), MD_MASK, PPC64, PPCVLE, {RA, RS, SH6, ME6}},
4669 {"rldicr.", MD(30,1,1), MD_MASK, PPC64, PPCVLE, {RA, RS, SH6, ME6}},
4671 {"rldic", MD(30,2,0), MD_MASK, PPC64, PPCVLE, {RA, RS, SH6, MB6}},
4672 {"rldic.", MD(30,2,1), MD_MASK, PPC64, PPCVLE, {RA, RS, SH6, MB6}},
4674 {"rldimi", MD(30,3,0), MD_MASK, PPC64, PPCVLE, {RA, RS, SH6, MB6}},
4675 {"rldimi.", MD(30,3,1), MD_MASK, PPC64, PPCVLE, {RA, RS, SH6, MB6}},
4677 {"rotld", MDS(30,8,0), MDSMB_MASK, PPC64, PPCVLE, {RA, RS, RB}},
4678 {"rldcl", MDS(30,8,0), MDS_MASK, PPC64, PPCVLE, {RA, RS, RB, MB6}},
4679 {"rotld.", MDS(30,8,1), MDSMB_MASK, PPC64, PPCVLE, {RA, RS, RB}},
4680 {"rldcl.", MDS(30,8,1), MDS_MASK, PPC64, PPCVLE, {RA, RS, RB, MB6}},
4682 {"rldcr", MDS(30,9,0), MDS_MASK, PPC64, PPCVLE, {RA, RS, RB, ME6}},
4683 {"rldcr.", MDS(30,9,1), MDS_MASK, PPC64, PPCVLE, {RA, RS, RB, ME6}},
4685 {"cmpw", XOPL(31,0,0), XCMPL_MASK, PPCCOM, 0, {OBF, RA, RB}},
4686 {"cmpd", XOPL(31,0,1), XCMPL_MASK, PPC64, 0, {OBF, RA, RB}},
4687 {"cmp", X(31,0), XCMP_MASK, PPC, 0, {BF, L, RA, RB}},
4688 {"cmp", X(31,0), XCMPL_MASK, PWRCOM, PPC, {BF, RA, RB}},
4690 {"twlgt", XTO(31,4,TOLGT), XTO_MASK, PPCCOM, 0, {RA, RB}},
4691 {"tlgt", XTO(31,4,TOLGT), XTO_MASK, PWRCOM, 0, {RA, RB}},
4692 {"twllt", XTO(31,4,TOLLT), XTO_MASK, PPCCOM, 0, {RA, RB}},
4693 {"tllt", XTO(31,4,TOLLT), XTO_MASK, PWRCOM, 0, {RA, RB}},
4694 {"tweq", XTO(31,4,TOEQ), XTO_MASK, PPCCOM, 0, {RA, RB}},
4695 {"teq", XTO(31,4,TOEQ), XTO_MASK, PWRCOM, 0, {RA, RB}},
4696 {"twlge", XTO(31,4,TOLGE), XTO_MASK, PPCCOM, 0, {RA, RB}},
4697 {"tlge", XTO(31,4,TOLGE), XTO_MASK, PWRCOM, 0, {RA, RB}},
4698 {"twlnl", XTO(31,4,TOLNL), XTO_MASK, PPCCOM, 0, {RA, RB}},
4699 {"tlnl", XTO(31,4,TOLNL), XTO_MASK, PWRCOM, 0, {RA, RB}},
4700 {"twlle", XTO(31,4,TOLLE), XTO_MASK, PPCCOM, 0, {RA, RB}},
4701 {"tlle", XTO(31,4,TOLLE), XTO_MASK, PWRCOM, 0, {RA, RB}},
4702 {"twlng", XTO(31,4,TOLNG), XTO_MASK, PPCCOM, 0, {RA, RB}},
4703 {"tlng", XTO(31,4,TOLNG), XTO_MASK, PWRCOM, 0, {RA, RB}},
4704 {"twgt", XTO(31,4,TOGT), XTO_MASK, PPCCOM, 0, {RA, RB}},
4705 {"tgt", XTO(31,4,TOGT), XTO_MASK, PWRCOM, 0, {RA, RB}},
4706 {"twge", XTO(31,4,TOGE), XTO_MASK, PPCCOM, 0, {RA, RB}},
4707 {"tge", XTO(31,4,TOGE), XTO_MASK, PWRCOM, 0, {RA, RB}},
4708 {"twnl", XTO(31,4,TONL), XTO_MASK, PPCCOM, 0, {RA, RB}},
4709 {"tnl", XTO(31,4,TONL), XTO_MASK, PWRCOM, 0, {RA, RB}},
4710 {"twlt", XTO(31,4,TOLT), XTO_MASK, PPCCOM, 0, {RA, RB}},
4711 {"tlt", XTO(31,4,TOLT), XTO_MASK, PWRCOM, 0, {RA, RB}},
4712 {"twle", XTO(31,4,TOLE), XTO_MASK, PPCCOM, 0, {RA, RB}},
4713 {"tle", XTO(31,4,TOLE), XTO_MASK, PWRCOM, 0, {RA, RB}},
4714 {"twng", XTO(31,4,TONG), XTO_MASK, PPCCOM, 0, {RA, RB}},
4715 {"tng", XTO(31,4,TONG), XTO_MASK, PWRCOM, 0, {RA, RB}},
4716 {"twne", XTO(31,4,TONE), XTO_MASK, PPCCOM, 0, {RA, RB}},
4717 {"tne", XTO(31,4,TONE), XTO_MASK, PWRCOM, 0, {RA, RB}},
4718 {"trap", XTO(31,4,TOU), 0xffffffff, PPCCOM, 0, {0}},
4719 {"twu", XTO(31,4,TOU), XTO_MASK, PPCCOM, 0, {RA, RB}},
4720 {"tu", XTO(31,4,TOU), XTO_MASK, PWRCOM, 0, {RA, RB}},
4721 {"tw", X(31,4), X_MASK, PPCCOM, 0, {TO, RA, RB}},
4722 {"t", X(31,4), X_MASK, PWRCOM, 0, {TO, RA, RB}},
4724 {"lvsl", X(31,6), X_MASK, PPCVEC, 0, {VD, RA0, RB}},
4725 {"lvebx", X(31,7), X_MASK, PPCVEC, 0, {VD, RA0, RB}},
4726 {"lbfcmx", APU(31,7,0), APU_MASK, PPC405, 0, {FCRT, RA, RB}},
4728 {"subfc", XO(31,8,0,0), XO_MASK, PPCCOM, 0, {RT, RA, RB}},
4729 {"sf", XO(31,8,0,0), XO_MASK, PWRCOM, 0, {RT, RA, RB}},
4730 {"subc", XO(31,8,0,0), XO_MASK, PPCCOM, 0, {RT, RB, RA}},
4731 {"subfc.", XO(31,8,0,1), XO_MASK, PPCCOM, 0, {RT, RA, RB}},
4732 {"sf.", XO(31,8,0,1), XO_MASK, PWRCOM, 0, {RT, RA, RB}},
4733 {"subc.", XO(31,8,0,1), XO_MASK, PPCCOM, 0, {RT, RB, RA}},
4735 {"mulhdu", XO(31,9,0,0), XO_MASK, PPC64, 0, {RT, RA, RB}},
4736 {"mulhdu.", XO(31,9,0,1), XO_MASK, PPC64, 0, {RT, RA, RB}},
4738 {"addc", XO(31,10,0,0), XO_MASK, PPCCOM, 0, {RT, RA, RB}},
4739 {"a", XO(31,10,0,0), XO_MASK, PWRCOM, 0, {RT, RA, RB}},
4740 {"addc.", XO(31,10,0,1), XO_MASK, PPCCOM, 0, {RT, RA, RB}},
4741 {"a.", XO(31,10,0,1), XO_MASK, PWRCOM, 0, {RT, RA, RB}},
4743 {"mulhwu", XO(31,11,0,0), XO_MASK, PPC, 0, {RT, RA, RB}},
4744 {"mulhwu.", XO(31,11,0,1), XO_MASK, PPC, 0, {RT, RA, RB}},
4746 {"lxsiwzx", X(31,12), XX1_MASK, PPCVSX2, 0, {XT6, RA0, RB}},
4748 {"isellt", X(31,15), X_MASK, PPCISEL, 0, {RT, RA0, RB}},
4750 {"tlbilxlpid", XTO(31,18,0), XTO_MASK, E500MC|PPCA2, 0, {0}},
4751 {"tlbilxpid", XTO(31,18,1), XTO_MASK, E500MC|PPCA2, 0, {0}},
4752 {"tlbilxva", XTO(31,18,3), XTO_MASK, E500MC|PPCA2, 0, {RA0, RB}},
4753 {"tlbilx", X(31,18), X_MASK, E500MC|PPCA2, 0, {T, RA0, RB}},
4755 {"mfcr", XFXM(31,19,0,0), XFXFXM_MASK, COM, 0, {RT, FXM4}},
4756 {"mfocrf", XFXM(31,19,0,1), XFXFXM_MASK, COM, 0, {RT, FXM}},
4758 {"lwarx", X(31,20), XEH_MASK, PPC, 0, {RT, RA0, RB, EH}},
4760 {"ldx", X(31,21), X_MASK, PPC64, 0, {RT, RA0, RB}},
4762 {"icbt", X(31,22), X_MASK, BOOKE|PPCE300|PPCA2|PPC476, 0, {CT, RA0, RB}},
4764 {"lwzx", X(31,23), X_MASK, PPCCOM, 0, {RT, RA0, RB}},
4765 {"lx", X(31,23), X_MASK, PWRCOM, 0, {RT, RA, RB}},
4767 {"slw", XRC(31,24,0), X_MASK, PPCCOM, 0, {RA, RS, RB}},
4768 {"sl", XRC(31,24,0), X_MASK, PWRCOM, 0, {RA, RS, RB}},
4769 {"slw.", XRC(31,24,1), X_MASK, PPCCOM, 0, {RA, RS, RB}},
4770 {"sl.", XRC(31,24,1), X_MASK, PWRCOM, 0, {RA, RS, RB}},
4772 {"cntlzw", XRC(31,26,0), XRB_MASK, PPCCOM, 0, {RA, RS}},
4773 {"cntlz", XRC(31,26,0), XRB_MASK, PWRCOM, 0, {RA, RS}},
4774 {"cntlzw.", XRC(31,26,1), XRB_MASK, PPCCOM, 0, {RA, RS}},
4775 {"cntlz.", XRC(31,26,1), XRB_MASK, PWRCOM, 0, {RA, RS}},
4777 {"sld", XRC(31,27,0), X_MASK, PPC64, 0, {RA, RS, RB}},
4778 {"sld.", XRC(31,27,1), X_MASK, PPC64, 0, {RA, RS, RB}},
4780 {"and", XRC(31,28,0), X_MASK, COM, 0, {RA, RS, RB}},
4781 {"and.", XRC(31,28,1), X_MASK, COM, 0, {RA, RS, RB}},
4783 {"maskg", XRC(31,29,0), X_MASK, M601, PPCA2, {RA, RS, RB}},
4784 {"maskg.", XRC(31,29,1), X_MASK, M601, PPCA2, {RA, RS, RB}},
4786 {"ldepx", X(31,29), X_MASK, E500MC|PPCA2, 0, {RT, RA0, RB}},
4788 {"waitasec", X(31,30), XRTRARB_MASK, POWER8, POWER9, {0}},
4789 {"wait", X(31,30), XWC_MASK, POWER9, 0, {WC}},
4791 {"lwepx", X(31,31), X_MASK, E500MC|PPCA2, 0, {RT, RA0, RB}},
4793 {"cmplw", XOPL(31,32,0), XCMPL_MASK, PPCCOM, 0, {OBF, RA, RB}},
4794 {"cmpld", XOPL(31,32,1), XCMPL_MASK, PPC64, 0, {OBF, RA, RB}},
4795 {"cmpl", X(31,32), XCMP_MASK, PPC, 0, {BF, L, RA, RB}},
4796 {"cmpl", X(31,32), XCMPL_MASK, PWRCOM, PPC, {BF, RA, RB}},
4798 {"lvsr", X(31,38), X_MASK, PPCVEC, 0, {VD, RA0, RB}},
4799 {"lvehx", X(31,39), X_MASK, PPCVEC, 0, {VD, RA0, RB}},
4800 {"lhfcmx", APU(31,39,0), APU_MASK, PPC405, 0, {FCRT, RA, RB}},
4802 {"mviwsplt", X(31,46), X_MASK, PPCVEC2, 0, {VD, RA, RB}},
4804 {"iselgt", X(31,47), X_MASK, PPCISEL, 0, {RT, RA0, RB}},
4806 {"lvewx", X(31,71), X_MASK, PPCVEC, 0, {VD, RA0, RB}},
4808 {"addg6s", XO(31,74,0,0), XO_MASK, POWER6, 0, {RT, RA, RB}},
4810 {"lxsiwax", X(31,76), XX1_MASK, PPCVSX2, 0, {XT6, RA0, RB}},
4812 {"iseleq", X(31,79), X_MASK, PPCISEL, 0, {RT, RA0, RB}},
4814 {"isel", XISEL(31,15), XISEL_MASK, PPCISEL|TITAN, 0, {RT, RA0, RB, CRB}},
4816 {"subf", XO(31,40,0,0), XO_MASK, PPC, 0, {RT, RA, RB}},
4817 {"sub", XO(31,40,0,0), XO_MASK, PPC, 0, {RT, RB, RA}},
4818 {"subf.", XO(31,40,0,1), XO_MASK, PPC, 0, {RT, RA, RB}},
4819 {"sub.", XO(31,40,0,1), XO_MASK, PPC, 0, {RT, RB, RA}},
4821 {"mfvsrd", X(31,51), XX1RB_MASK, PPCVSX2, 0, {RA, XS6}},
4822 {"mffprd", X(31,51), XX1RB_MASK|1, PPCVSX2, 0, {RA, FRS}},
4823 {"mfvrd", X(31,51)|1, XX1RB_MASK|1, PPCVSX2, 0, {RA, VS}},
4824 {"eratilx", X(31,51), X_MASK, PPCA2, 0, {ERAT_T, RA, RB}},
4826 {"lbarx", X(31,52), XEH_MASK, POWER8|E6500, 0, {RT, RA0, RB, EH}},
4828 {"ldux", X(31,53), X_MASK, PPC64, 0, {RT, RAL, RB}},
4830 {"dcbst", X(31,54), XRT_MASK, PPC, 0, {RA0, RB}},
4832 {"lwzux", X(31,55), X_MASK, PPCCOM, 0, {RT, RAL, RB}},
4833 {"lux", X(31,55), X_MASK, PWRCOM, 0, {RT, RA, RB}},
4835 {"cntlzd", XRC(31,58,0), XRB_MASK, PPC64, 0, {RA, RS}},
4836 {"cntlzd.", XRC(31,58,1), XRB_MASK, PPC64, 0, {RA, RS}},
4838 {"andc", XRC(31,60,0), X_MASK, COM, 0, {RA, RS, RB}},
4839 {"andc.", XRC(31,60,1), X_MASK, COM, 0, {RA, RS, RB}},
4841 {"waitrsv", X(31,62)|(1<<21), 0xffffffff, E500MC|PPCA2, 0, {0}},
4842 {"waitimpl", X(31,62)|(2<<21), 0xffffffff, E500MC|PPCA2, 0, {0}},
4843 {"wait", X(31,62), XWC_MASK, E500MC|PPCA2, 0, {WC}},
4845 {"dcbstep", XRT(31,63,0), XRT_MASK, E500MC|PPCA2, 0, {RA0, RB}},
4847 {"tdlgt", XTO(31,68,TOLGT), XTO_MASK, PPC64, 0, {RA, RB}},
4848 {"tdllt", XTO(31,68,TOLLT), XTO_MASK, PPC64, 0, {RA, RB}},
4849 {"tdeq", XTO(31,68,TOEQ), XTO_MASK, PPC64, 0, {RA, RB}},
4850 {"tdlge", XTO(31,68,TOLGE), XTO_MASK, PPC64, 0, {RA, RB}},
4851 {"tdlnl", XTO(31,68,TOLNL), XTO_MASK, PPC64, 0, {RA, RB}},
4852 {"tdlle", XTO(31,68,TOLLE), XTO_MASK, PPC64, 0, {RA, RB}},
4853 {"tdlng", XTO(31,68,TOLNG), XTO_MASK, PPC64, 0, {RA, RB}},
4854 {"tdgt", XTO(31,68,TOGT), XTO_MASK, PPC64, 0, {RA, RB}},
4855 {"tdge", XTO(31,68,TOGE), XTO_MASK, PPC64, 0, {RA, RB}},
4856 {"tdnl", XTO(31,68,TONL), XTO_MASK, PPC64, 0, {RA, RB}},
4857 {"tdlt", XTO(31,68,TOLT), XTO_MASK, PPC64, 0, {RA, RB}},
4858 {"tdle", XTO(31,68,TOLE), XTO_MASK, PPC64, 0, {RA, RB}},
4859 {"tdng", XTO(31,68,TONG), XTO_MASK, PPC64, 0, {RA, RB}},
4860 {"tdne", XTO(31,68,TONE), XTO_MASK, PPC64, 0, {RA, RB}},
4861 {"tdu", XTO(31,68,TOU), XTO_MASK, PPC64, 0, {RA, RB}},
4862 {"td", X(31,68), X_MASK, PPC64, 0, {TO, RA, RB}},
4864 {"lwfcmx", APU(31,71,0), APU_MASK, PPC405, 0, {FCRT, RA, RB}},
4865 {"mulhd", XO(31,73,0,0), XO_MASK, PPC64, 0, {RT, RA, RB}},
4866 {"mulhd.", XO(31,73,0,1), XO_MASK, PPC64, 0, {RT, RA, RB}},
4868 {"mulhw", XO(31,75,0,0), XO_MASK, PPC, 0, {RT, RA, RB}},
4869 {"mulhw.", XO(31,75,0,1), XO_MASK, PPC, 0, {RT, RA, RB}},
4871 {"dlmzb", XRC(31,78,0), X_MASK, PPC403|PPC440|TITAN, 0, {RA, RS, RB}},
4872 {"dlmzb.", XRC(31,78,1), X_MASK, PPC403|PPC440|TITAN, 0, {RA, RS, RB}},
4874 {"mtsrd", X(31,82), XRB_MASK|(1<<20), PPC64, 0, {SR, RS}},
4876 {"mfmsr", X(31,83), XRARB_MASK, COM, 0, {RT}},
4878 {"ldarx", X(31,84), XEH_MASK, PPC64, 0, {RT, RA0, RB, EH}},
4880 {"dcbfl", XOPL(31,86,1), XRT_MASK, POWER5, PPC476, {RA0, RB}},
4881 {"dcbf", X(31,86), XLRT_MASK, PPC, 0, {RA0, RB, L}},
4883 {"lbzx", X(31,87), X_MASK, COM, 0, {RT, RA0, RB}},
4885 {"lbepx", X(31,95), X_MASK, E500MC|PPCA2, 0, {RT, RA0, RB}},
4887 {"dni", XRC(31,97,1), XRB_MASK, E6500, 0, {DUI, DCTL}},
4889 {"lvx", X(31,103), X_MASK, PPCVEC, 0, {VD, RA0, RB}},
4890 {"lqfcmx", APU(31,103,0), APU_MASK, PPC405, 0, {FCRT, RA, RB}},
4892 {"neg", XO(31,104,0,0), XORB_MASK, COM, 0, {RT, RA}},
4893 {"neg.", XO(31,104,0,1), XORB_MASK, COM, 0, {RT, RA}},
4895 {"mul", XO(31,107,0,0), XO_MASK, M601, 0, {RT, RA, RB}},
4896 {"mul.", XO(31,107,0,1), XO_MASK, M601, 0, {RT, RA, RB}},
4898 {"mvidsplt", X(31,110), X_MASK, PPCVEC2, 0, {VD, RA, RB}},
4900 {"mtsrdin", X(31,114), XRA_MASK, PPC64, 0, {RS, RB}},
4902 {"mffprwz", X(31,115), XX1RB_MASK|1, PPCVSX2, 0, {RA, FRS}},
4903 {"mfvrwz", X(31,115)|1, XX1RB_MASK|1, PPCVSX2, 0, {RA, VS}},
4904 {"mfvsrwz", X(31,115), XX1RB_MASK, PPCVSX2, 0, {RA, XS6}},
4906 {"lharx", X(31,116), XEH_MASK, POWER8|E6500, 0, {RT, RA0, RB, EH}},
4908 {"clf", X(31,118), XTO_MASK, POWER, 0, {RA, RB}},
4910 {"lbzux", X(31,119), X_MASK, COM, 0, {RT, RAL, RB}},
4912 {"popcntb", X(31,122), XRB_MASK, POWER5, 0, {RA, RS}},
4914 {"not", XRC(31,124,0), X_MASK, COM, 0, {RA, RS, RBS}},
4915 {"nor", XRC(31,124,0), X_MASK, COM, 0, {RA, RS, RB}},
4916 {"not.", XRC(31,124,1), X_MASK, COM, 0, {RA, RS, RBS}},
4917 {"nor.", XRC(31,124,1), X_MASK, COM, 0, {RA, RS, RB}},
4919 {"dcbfep", XRT(31,127,0), XRT_MASK, E500MC|PPCA2, 0, {RA0, RB}},
4921 {"setb", X(31,128), XRB_MASK|(3<<16), POWER9, 0, {RT, BFA}},
4923 {"wrtee", X(31,131), XRARB_MASK, PPC403|BOOKE|PPCA2|PPC476, 0, {RS}},
4925 {"dcbtstls", X(31,134), X_MASK, PPCCHLK|PPC476|TITAN, 0, {CT, RA0, RB}},
4927 {"stvebx", X(31,135), X_MASK, PPCVEC, 0, {VS, RA0, RB}},
4928 {"stbfcmx", APU(31,135,0), APU_MASK, PPC405, 0, {FCRT, RA, RB}},
4930 {"subfe", XO(31,136,0,0), XO_MASK, PPCCOM, 0, {RT, RA, RB}},
4931 {"sfe", XO(31,136,0,0), XO_MASK, PWRCOM, 0, {RT, RA, RB}},
4932 {"subfe.", XO(31,136,0,1), XO_MASK, PPCCOM, 0, {RT, RA, RB}},
4933 {"sfe.", XO(31,136,0,1), XO_MASK, PWRCOM, 0, {RT, RA, RB}},
4935 {"adde", XO(31,138,0,0), XO_MASK, PPCCOM, 0, {RT, RA, RB}},
4936 {"ae", XO(31,138,0,0), XO_MASK, PWRCOM, 0, {RT, RA, RB}},
4937 {"adde.", XO(31,138,0,1), XO_MASK, PPCCOM, 0, {RT, RA, RB}},
4938 {"ae.", XO(31,138,0,1), XO_MASK, PWRCOM, 0, {RT, RA, RB}},
4940 {"stxsiwx", X(31,140), XX1_MASK, PPCVSX2, 0, {XS6, RA0, RB}},
4942 {"msgsndp", XRTRA(31,142,0,0), XRTRA_MASK, POWER8, 0, {RB}},
4943 {"dcbtstlse", X(31,142), X_MASK, PPCCHLK, E500MC, {CT, RA0, RB}},
4945 {"mtcr", XFXM(31,144,0xff,0), XRARB_MASK, COM, 0, {RS}},
4946 {"mtcrf", XFXM(31,144,0,0), XFXFXM_MASK, COM, 0, {FXM, RS}},
4947 {"mtocrf", XFXM(31,144,0,1), XFXFXM_MASK, COM, 0, {FXM, RS}},
4949 {"mtmsr", X(31,146), XRLARB_MASK, COM, 0, {RS, A_L}},
4951 {"mtsle", X(31,147), XRTLRARB_MASK, POWER8, 0, {L}},
4953 {"eratsx", XRC(31,147,0), X_MASK, PPCA2, 0, {RT, RA0, RB}},
4954 {"eratsx.", XRC(31,147,1), X_MASK, PPCA2, 0, {RT, RA0, RB}},
4956 {"stdx", X(31,149), X_MASK, PPC64, 0, {RS, RA0, RB}},
4958 {"stwcx.", XRC(31,150,1), X_MASK, PPC, 0, {RS, RA0, RB}},
4960 {"stwx", X(31,151), X_MASK, PPCCOM, 0, {RS, RA0, RB}},
4961 {"stx", X(31,151), X_MASK, PWRCOM, 0, {RS, RA, RB}},
4963 {"slq", XRC(31,152,0), X_MASK, M601, 0, {RA, RS, RB}},
4964 {"slq.", XRC(31,152,1), X_MASK, M601, 0, {RA, RS, RB}},
4966 {"sle", XRC(31,153,0), X_MASK, M601, 0, {RA, RS, RB}},
4967 {"sle.", XRC(31,153,1), X_MASK, M601, 0, {RA, RS, RB}},
4969 {"prtyw", X(31,154), XRB_MASK, POWER6|PPCA2|PPC476, 0, {RA, RS}},
4971 {"stdepx", X(31,157), X_MASK, E500MC|PPCA2, 0, {RS, RA0, RB}},
4973 {"stwepx", X(31,159), X_MASK, E500MC|PPCA2, 0, {RS, RA0, RB}},
4975 {"wrteei", X(31,163), XE_MASK, PPC403|BOOKE|PPCA2|PPC476, 0, {E}},
4977 {"dcbtls", X(31,166), X_MASK, PPCCHLK|PPC476|TITAN, 0, {CT, RA0, RB}},
4979 {"stvehx", X(31,167), X_MASK, PPCVEC, 0, {VS, RA0, RB}},
4980 {"sthfcmx", APU(31,167,0), APU_MASK, PPC405, 0, {FCRT, RA, RB}},
4982 {"addex", ZRC(31,170,0), Z2_MASK, POWER9, 0, {RT, RA, RB, CY}},
4983 {"addex.", ZRC(31,170,1), Z2_MASK, POWER9, 0, {RT, RA, RB, CY}},
4985 {"msgclrp", XRTRA(31,174,0,0), XRTRA_MASK, POWER8, 0, {RB}},
4986 {"dcbtlse", X(31,174), X_MASK, PPCCHLK, E500MC, {CT, RA0, RB}},
4988 {"mtmsrd", X(31,178), XRLARB_MASK, PPC64, 0, {RS, A_L}},
4990 {"mtvsrd", X(31,179), XX1RB_MASK, PPCVSX2, 0, {XT6, RA}},
4991 {"mtfprd", X(31,179), XX1RB_MASK|1, PPCVSX2, 0, {FRT, RA}},
4992 {"mtvrd", X(31,179)|1, XX1RB_MASK|1, PPCVSX2, 0, {VD, RA}},
4993 {"eratre", X(31,179), X_MASK, PPCA2, 0, {RT, RA, WS}},
4995 {"stdux", X(31,181), X_MASK, PPC64, 0, {RS, RAS, RB}},
4997 {"stqcx.", XRC(31,182,1), X_MASK, POWER8, 0, {RSQ, RA0, RB}},
4998 {"wchkall", X(31,182), X_MASK, PPCA2, 0, {OBF}},
5000 {"stwux", X(31,183), X_MASK, PPCCOM, 0, {RS, RAS, RB}},
5001 {"stux", X(31,183), X_MASK, PWRCOM, 0, {RS, RA0, RB}},
5003 {"sliq", XRC(31,184,0), X_MASK, M601, 0, {RA, RS, SH}},
5004 {"sliq.", XRC(31,184,1), X_MASK, M601, 0, {RA, RS, SH}},
5006 {"prtyd", X(31,186), XRB_MASK, POWER6|PPCA2, 0, {RA, RS}},
5008 {"cmprb", X(31,192), XCMP_MASK, POWER9, 0, {BF, L, RA, RB}},
5010 {"icblq.", XRC(31,198,1), X_MASK, E6500, 0, {CT, RA0, RB}},
5012 {"stvewx", X(31,199), X_MASK, PPCVEC, 0, {VS, RA0, RB}},
5013 {"stwfcmx", APU(31,199,0), APU_MASK, PPC405, 0, {FCRT, RA, RB}},
5015 {"subfze", XO(31,200,0,0), XORB_MASK, PPCCOM, 0, {RT, RA}},
5016 {"sfze", XO(31,200,0,0), XORB_MASK, PWRCOM, 0, {RT, RA}},
5017 {"subfze.", XO(31,200,0,1), XORB_MASK, PPCCOM, 0, {RT, RA}},
5018 {"sfze.", XO(31,200,0,1), XORB_MASK, PWRCOM, 0, {RT, RA}},
5020 {"addze", XO(31,202,0,0), XORB_MASK, PPCCOM, 0, {RT, RA}},
5021 {"aze", XO(31,202,0,0), XORB_MASK, PWRCOM, 0, {RT, RA}},
5022 {"addze.", XO(31,202,0,1), XORB_MASK, PPCCOM, 0, {RT, RA}},
5023 {"aze.", XO(31,202,0,1), XORB_MASK, PWRCOM, 0, {RT, RA}},
5025 {"msgsnd", XRTRA(31,206,0,0), XRTRA_MASK, E500MC|PPCA2|POWER8, 0, {RB}},
5027 {"mtsr", X(31,210), XRB_MASK|(1<<20), COM, NON32, {SR, RS}},
5029 {"mtfprwa", X(31,211), XX1RB_MASK|1, PPCVSX2, 0, {FRT, RA}},
5030 {"mtvrwa", X(31,211)|1, XX1RB_MASK|1, PPCVSX2, 0, {VD, RA}},
5031 {"mtvsrwa", X(31,211), XX1RB_MASK, PPCVSX2, 0, {XT6, RA}},
5032 {"eratwe", X(31,211), X_MASK, PPCA2, 0, {RS, RA, WS}},
5034 {"ldawx.", XRC(31,212,1), X_MASK, PPCA2, 0, {RT, RA0, RB}},
5036 {"stdcx.", XRC(31,214,1), X_MASK, PPC64, 0, {RS, RA0, RB}},
5038 {"stbx", X(31,215), X_MASK, COM, 0, {RS, RA0, RB}},
5040 {"sllq", XRC(31,216,0), X_MASK, M601, 0, {RA, RS, RB}},
5041 {"sllq.", XRC(31,216,1), X_MASK, M601, 0, {RA, RS, RB}},
5043 {"sleq", XRC(31,217,0), X_MASK, M601, 0, {RA, RS, RB}},
5044 {"sleq.", XRC(31,217,1), X_MASK, M601, 0, {RA, RS, RB}},
5046 {"stbepx", X(31,223), X_MASK, E500MC|PPCA2, 0, {RS, RA0, RB}},
5048 {"cmpeqb", X(31,224), XCMPL_MASK, POWER9, 0, {BF, RA, RB}},
5050 {"icblc", X(31,230), X_MASK, PPCCHLK|PPC476|TITAN, 0, {CT, RA0, RB}},
5052 {"stvx", X(31,231), X_MASK, PPCVEC, 0, {VS, RA0, RB}},
5053 {"stqfcmx", APU(31,231,0), APU_MASK, PPC405, 0, {FCRT, RA, RB}},
5055 {"subfme", XO(31,232,0,0), XORB_MASK, PPCCOM, 0, {RT, RA}},
5056 {"sfme", XO(31,232,0,0), XORB_MASK, PWRCOM, 0, {RT, RA}},
5057 {"subfme.", XO(31,232,0,1), XORB_MASK, PPCCOM, 0, {RT, RA}},
5058 {"sfme.", XO(31,232,0,1), XORB_MASK, PWRCOM, 0, {RT, RA}},
5060 {"mulld", XO(31,233,0,0), XO_MASK, PPC64, 0, {RT, RA, RB}},
5061 {"mulld.", XO(31,233,0,1), XO_MASK, PPC64, 0, {RT, RA, RB}},
5063 {"addme", XO(31,234,0,0), XORB_MASK, PPCCOM, 0, {RT, RA}},
5064 {"ame", XO(31,234,0,0), XORB_MASK, PWRCOM, 0, {RT, RA}},
5065 {"addme.", XO(31,234,0,1), XORB_MASK, PPCCOM, 0, {RT, RA}},
5066 {"ame.", XO(31,234,0,1), XORB_MASK, PWRCOM, 0, {RT, RA}},
5068 {"mullw", XO(31,235,0,0), XO_MASK, PPCCOM, 0, {RT, RA, RB}},
5069 {"muls", XO(31,235,0,0), XO_MASK, PWRCOM, 0, {RT, RA, RB}},
5070 {"mullw.", XO(31,235,0,1), XO_MASK, PPCCOM, 0, {RT, RA, RB}},
5071 {"muls.", XO(31,235,0,1), XO_MASK, PWRCOM, 0, {RT, RA, RB}},
5073 {"icblce", X(31,238), X_MASK, PPCCHLK, E500MC|PPCA2, {CT, RA, RB}},
5074 {"msgclr", XRTRA(31,238,0,0), XRTRA_MASK, E500MC|PPCA2|POWER8, 0, {RB}},
5075 {"mtsrin", X(31,242), XRA_MASK, PPC, NON32, {RS, RB}},
5076 {"mtsri", X(31,242), XRA_MASK, POWER, NON32, {RS, RB}},
5078 {"mtfprwz", X(31,243), XX1RB_MASK|1, PPCVSX2, 0, {FRT, RA}},
5079 {"mtvrwz", X(31,243)|1, XX1RB_MASK|1, PPCVSX2, 0, {VD, RA}},
5080 {"mtvsrwz", X(31,243), XX1RB_MASK, PPCVSX2, 0, {XT6, RA}},
5082 {"dcbtstt", XRT(31,246,0x10), XRT_MASK, POWER7, 0, {RA0, RB}},
5083 {"dcbtst", X(31,246), X_MASK, POWER4, DCBT_EO, {RA0, RB, CT}},
5084 {"dcbtst", X(31,246), X_MASK, DCBT_EO, 0, {CT, RA0, RB}},
5085 {"dcbtst", X(31,246), X_MASK, PPC, POWER4|DCBT_EO, {RA0, RB}},
5087 {"stbux", X(31,247), X_MASK, COM, 0, {RS, RAS, RB}},
5089 {"slliq", XRC(31,248,0), X_MASK, M601, 0, {RA, RS, SH}},
5090 {"slliq.", XRC(31,248,1), X_MASK, M601, 0, {RA, RS, SH}},
5092 {"bpermd", X(31,252), X_MASK, POWER7|PPCA2, 0, {RA, RS, RB}},
5094 {"dcbtstep", XRT(31,255,0), X_MASK, E500MC|PPCA2, 0, {RT, RA0, RB}},
5096 {"mfdcrx", X(31,259), X_MASK, BOOKE|PPCA2|PPC476, TITAN, {RS, RA}},
5097 {"mfdcrx.", XRC(31,259,1), X_MASK, PPCA2, 0, {RS, RA}},
5099 {"lvexbx", X(31,261), X_MASK, PPCVEC2, 0, {VD, RA0, RB}},
5101 {"icbt", X(31,262), XRT_MASK, PPC403, 0, {RA, RB}},
5103 {"lvepxl", X(31,263), X_MASK, PPCVEC2, 0, {VD, RA0, RB}},
5105 {"ldfcmx", APU(31,263,0), APU_MASK, PPC405, 0, {FCRT, RA, RB}},
5106 {"doz", XO(31,264,0,0), XO_MASK, M601, 0, {RT, RA, RB}},
5107 {"doz.", XO(31,264,0,1), XO_MASK, M601, 0, {RT, RA, RB}},
5109 {"modud", X(31,265), X_MASK, POWER9, 0, {RT, RA, RB}},
5111 {"add", XO(31,266,0,0), XO_MASK, PPCCOM, 0, {RT, RA, RB}},
5112 {"cax", XO(31,266,0,0), XO_MASK, PWRCOM, 0, {RT, RA, RB}},
5113 {"add.", XO(31,266,0,1), XO_MASK, PPCCOM, 0, {RT, RA, RB}},
5114 {"cax.", XO(31,266,0,1), XO_MASK, PWRCOM, 0, {RT, RA, RB}},
5116 {"moduw", X(31,267), X_MASK, POWER9, 0, {RT, RA, RB}},
5118 {"lxvx", X(31,268), XX1_MASK|1<<6, PPCVSX3, 0, {XT6, RA0, RB}},
5119 {"lxvl", X(31,269), XX1_MASK, PPCVSX3, 0, {XT6, RA0, RB}},
5121 {"ehpriv", X(31,270), 0xffffffff, E500MC|PPCA2, 0, {0}},
5123 {"tlbiel", X(31,274), X_MASK|1<<20,POWER9, PPC476, {RB, RSO, RIC, PRS, X_R}},
5124 {"tlbiel", X(31,274), XRTLRA_MASK, POWER4, POWER9|PPC476, {RB, L}},
5126 {"mfapidi", X(31,275), X_MASK, BOOKE, E500|TITAN, {RT, RA}},
5128 {"lqarx", X(31,276), XEH_MASK, POWER8, 0, {RTQ, RAX, RBX, EH}},
5130 {"lscbx", XRC(31,277,0), X_MASK, M601, 0, {RT, RA, RB}},
5131 {"lscbx.", XRC(31,277,1), X_MASK, M601, 0, {RT, RA, RB}},
5133 {"dcbtt", XRT(31,278,0x10), XRT_MASK, POWER7, 0, {RA0, RB}},
5134 {"dcbt", X(31,278), X_MASK, POWER4, DCBT_EO, {RA0, RB, CT}},
5135 {"dcbt", X(31,278), X_MASK, DCBT_EO, 0, {CT, RA0, RB}},
5136 {"dcbt", X(31,278), X_MASK, PPC, POWER4|DCBT_EO, {RA0, RB}},
5138 {"lhzx", X(31,279), X_MASK, COM, 0, {RT, RA0, RB}},
5140 {"cdtbcd", X(31,282), XRB_MASK, POWER6, 0, {RA, RS}},
5142 {"eqv", XRC(31,284,0), X_MASK, COM, 0, {RA, RS, RB}},
5143 {"eqv.", XRC(31,284,1), X_MASK, COM, 0, {RA, RS, RB}},
5145 {"lhepx", X(31,287), X_MASK, E500MC|PPCA2, 0, {RT, RA0, RB}},
5147 {"mfdcrux", X(31,291), X_MASK, PPC464, 0, {RS, RA}},
5149 {"lvexhx", X(31,293), X_MASK, PPCVEC2, 0, {VD, RA0, RB}},
5150 {"lvepx", X(31,295), X_MASK, PPCVEC2, 0, {VD, RA0, RB}},
5152 {"lxvll", X(31,301), XX1_MASK, PPCVSX3, 0, {XT6, RA0, RB}},
5154 {"mfbhrbe", X(31,302), X_MASK, POWER8, 0, {RT, BHRBE}},
5156 {"tlbie", X(31,306), X_MASK|1<<20,POWER9, TITAN, {RB, RS, RIC, PRS, X_R}},
5157 {"tlbie", X(31,306), XRA_MASK, POWER7, POWER9|TITAN, {RB, RS}},
5158 {"tlbie", X(31,306), XRTLRA_MASK, PPC, E500|POWER7|TITAN, {RB, L}},
5159 {"tlbi", X(31,306), XRT_MASK, POWER, 0, {RA0, RB}},
5161 {"mfvsrld", X(31,307), XX1RB_MASK, PPCVSX3, 0, {RA, XS6}},
5163 {"ldmx", X(31,309), X_MASK, POWER9, 0, {RT, RA0, RB}},
5165 {"eciwx", X(31,310), X_MASK, PPC, E500|TITAN, {RT, RA0, RB}},
5167 {"lhzux", X(31,311), X_MASK, COM, 0, {RT, RAL, RB}},
5169 {"cbcdtd", X(31,314), XRB_MASK, POWER6, 0, {RA, RS}},
5171 {"xor", XRC(31,316,0), X_MASK, COM, 0, {RA, RS, RB}},
5172 {"xor.", XRC(31,316,1), X_MASK, COM, 0, {RA, RS, RB}},
5174 {"dcbtep", XRT(31,319,0), X_MASK, E500MC|PPCA2, 0, {RT, RA0, RB}},
5176 {"mfexisr", XSPR(31,323, 64), XSPR_MASK, PPC403, 0, {RT}},
5177 {"mfexier", XSPR(31,323, 66), XSPR_MASK, PPC403, 0, {RT}},
5178 {"mfbr0", XSPR(31,323,128), XSPR_MASK, PPC403, 0, {RT}},
5179 {"mfbr1", XSPR(31,323,129), XSPR_MASK, PPC403, 0, {RT}},
5180 {"mfbr2", XSPR(31,323,130), XSPR_MASK, PPC403, 0, {RT}},
5181 {"mfbr3", XSPR(31,323,131), XSPR_MASK, PPC403, 0, {RT}},
5182 {"mfbr4", XSPR(31,323,132), XSPR_MASK, PPC403, 0, {RT}},
5183 {"mfbr5", XSPR(31,323,133), XSPR_MASK, PPC403, 0, {RT}},
5184 {"mfbr6", XSPR(31,323,134), XSPR_MASK, PPC403, 0, {RT}},
5185 {"mfbr7", XSPR(31,323,135), XSPR_MASK, PPC403, 0, {RT}},
5186 {"mfbear", XSPR(31,323,144), XSPR_MASK, PPC403, 0, {RT}},
5187 {"mfbesr", XSPR(31,323,145), XSPR_MASK, PPC403, 0, {RT}},
5188 {"mfiocr", XSPR(31,323,160), XSPR_MASK, PPC403, 0, {RT}},
5189 {"mfdmacr0", XSPR(31,323,192), XSPR_MASK, PPC403, 0, {RT}},
5190 {"mfdmact0", XSPR(31,323,193), XSPR_MASK, PPC403, 0, {RT}},
5191 {"mfdmada0", XSPR(31,323,194), XSPR_MASK, PPC403, 0, {RT}},
5192 {"mfdmasa0", XSPR(31,323,195), XSPR_MASK, PPC403, 0, {RT}},
5193 {"mfdmacc0", XSPR(31,323,196), XSPR_MASK, PPC403, 0, {RT}},
5194 {"mfdmacr1", XSPR(31,323,200), XSPR_MASK, PPC403, 0, {RT}},
5195 {"mfdmact1", XSPR(31,323,201), XSPR_MASK, PPC403, 0, {RT}},
5196 {"mfdmada1", XSPR(31,323,202), XSPR_MASK, PPC403, 0, {RT}},
5197 {"mfdmasa1", XSPR(31,323,203), XSPR_MASK, PPC403, 0, {RT}},
5198 {"mfdmacc1", XSPR(31,323,204), XSPR_MASK, PPC403, 0, {RT}},
5199 {"mfdmacr2", XSPR(31,323,208), XSPR_MASK, PPC403, 0, {RT}},
5200 {"mfdmact2", XSPR(31,323,209), XSPR_MASK, PPC403, 0, {RT}},
5201 {"mfdmada2", XSPR(31,323,210), XSPR_MASK, PPC403, 0, {RT}},
5202 {"mfdmasa2", XSPR(31,323,211), XSPR_MASK, PPC403, 0, {RT}},
5203 {"mfdmacc2", XSPR(31,323,212), XSPR_MASK, PPC403, 0, {RT}},
5204 {"mfdmacr3", XSPR(31,323,216), XSPR_MASK, PPC403, 0, {RT}},
5205 {"mfdmact3", XSPR(31,323,217), XSPR_MASK, PPC403, 0, {RT}},
5206 {"mfdmada3", XSPR(31,323,218), XSPR_MASK, PPC403, 0, {RT}},
5207 {"mfdmasa3", XSPR(31,323,219), XSPR_MASK, PPC403, 0, {RT}},
5208 {"mfdmacc3", XSPR(31,323,220), XSPR_MASK, PPC403, 0, {RT}},
5209 {"mfdmasr", XSPR(31,323,224), XSPR_MASK, PPC403, 0, {RT}},
5210 {"mfdcr", X(31,323), X_MASK, PPC403|BOOKE|PPCA2|PPC476, E500|TITAN, {RT, SPR}},
5211 {"mfdcr.", XRC(31,323,1), X_MASK, PPCA2, 0, {RT, SPR}},
5213 {"lvexwx", X(31,325), X_MASK, PPCVEC2, 0, {VD, RA0, RB}},
5215 {"dcread", X(31,326), X_MASK, PPC476|TITAN, 0, {RT, RA0, RB}},
5217 {"div", XO(31,331,0,0), XO_MASK, M601, 0, {RT, RA, RB}},
5218 {"div.", XO(31,331,0,1), XO_MASK, M601, 0, {RT, RA, RB}},
5220 {"lxvdsx", X(31,332), XX1_MASK, PPCVSX, 0, {XT6, RA0, RB}},
5222 {"mfpmr", X(31,334), X_MASK, PPCPMR|PPCE300, 0, {RT, PMR}},
5223 {"mftmr", X(31,366), X_MASK, PPCTMR|E6500, 0, {RT, TMR}},
5225 {"slbsync", X(31,338), 0xffffffff, POWER9, 0, {0}},
5227 {"mfmq", XSPR(31,339, 0), XSPR_MASK, M601, 0, {RT}},
5228 {"mfxer", XSPR(31,339, 1), XSPR_MASK, COM, 0, {RT}},
5229 {"mfrtcu", XSPR(31,339, 4), XSPR_MASK, COM, TITAN, {RT}},
5230 {"mfrtcl", XSPR(31,339, 5), XSPR_MASK, COM, TITAN, {RT}},
5231 {"mfdec", XSPR(31,339, 6), XSPR_MASK, MFDEC1, 0, {RT}},
5232 {"mflr", XSPR(31,339, 8), XSPR_MASK, COM, 0, {RT}},
5233 {"mfctr", XSPR(31,339, 9), XSPR_MASK, COM, 0, {RT}},
5234 {"mfdscr", XSPR(31,339, 17), XSPR_MASK, POWER6, 0, {RT}},
5235 {"mftid", XSPR(31,339, 17), XSPR_MASK, POWER, 0, {RT}},
5236 {"mfdsisr", XSPR(31,339, 18), XSPR_MASK, COM, TITAN, {RT}},
5237 {"mfdar", XSPR(31,339, 19), XSPR_MASK, COM, TITAN, {RT}},
5238 {"mfdec", XSPR(31,339, 22), XSPR_MASK, MFDEC2, MFDEC1, {RT}},
5239 {"mfsdr0", XSPR(31,339, 24), XSPR_MASK, POWER, 0, {RT}},
5240 {"mfsdr1", XSPR(31,339, 25), XSPR_MASK, COM, TITAN, {RT}},
5241 {"mfsrr0", XSPR(31,339, 26), XSPR_MASK, COM, 0, {RT}},
5242 {"mfsrr1", XSPR(31,339, 27), XSPR_MASK, COM, 0, {RT}},
5243 {"mfcfar", XSPR(31,339, 28), XSPR_MASK, POWER6, 0, {RT}},
5244 {"mfpid", XSPR(31,339, 48), XSPR_MASK, BOOKE, 0, {RT}},
5245 {"mfcsrr0", XSPR(31,339, 58), XSPR_MASK, BOOKE, 0, {RT}},
5246 {"mfcsrr1", XSPR(31,339, 59), XSPR_MASK, BOOKE, 0, {RT}},
5247 {"mfdear", XSPR(31,339, 61), XSPR_MASK, BOOKE, 0, {RT}},
5248 {"mfesr", XSPR(31,339, 62), XSPR_MASK, BOOKE, 0, {RT}},
5249 {"mfivpr", XSPR(31,339, 63), XSPR_MASK, BOOKE, 0, {RT}},
5250 {"mfctrl", XSPR(31,339,136), XSPR_MASK, POWER4, 0, {RT}},
5251 {"mfcmpa", XSPR(31,339,144), XSPR_MASK, PPC860, 0, {RT}},
5252 {"mfcmpb", XSPR(31,339,145), XSPR_MASK, PPC860, 0, {RT}},
5253 {"mfcmpc", XSPR(31,339,146), XSPR_MASK, PPC860, 0, {RT}},
5254 {"mfcmpd", XSPR(31,339,147), XSPR_MASK, PPC860, 0, {RT}},
5255 {"mficr", XSPR(31,339,148), XSPR_MASK, PPC860, 0, {RT}},
5256 {"mfder", XSPR(31,339,149), XSPR_MASK, PPC860, 0, {RT}},
5257 {"mfcounta", XSPR(31,339,150), XSPR_MASK, PPC860, 0, {RT}},
5258 {"mfcountb", XSPR(31,339,151), XSPR_MASK, PPC860, 0, {RT}},
5259 {"mfcmpe", XSPR(31,339,152), XSPR_MASK, PPC860, 0, {RT}},
5260 {"mfcmpf", XSPR(31,339,153), XSPR_MASK, PPC860, 0, {RT}},
5261 {"mfcmpg", XSPR(31,339,154), XSPR_MASK, PPC860, 0, {RT}},
5262 {"mfcmph", XSPR(31,339,155), XSPR_MASK, PPC860, 0, {RT}},
5263 {"mflctrl1", XSPR(31,339,156), XSPR_MASK, PPC860, 0, {RT}},
5264 {"mflctrl2", XSPR(31,339,157), XSPR_MASK, PPC860, 0, {RT}},
5265 {"mfictrl", XSPR(31,339,158), XSPR_MASK, PPC860, 0, {RT}},
5266 {"mfbar", XSPR(31,339,159), XSPR_MASK, PPC860, 0, {RT}},
5267 {"mfvrsave", XSPR(31,339,256), XSPR_MASK, PPCVEC, 0, {RT}},
5268 {"mfusprg0", XSPR(31,339,256), XSPR_MASK, BOOKE, 0, {RT}},
5269 {"mfsprg", XSPR(31,339,256), XSPRG_MASK, PPC, 0, {RT, SPRG}},
5270 {"mfsprg4", XSPR(31,339,260), XSPR_MASK, PPC405|BOOKE, 0, {RT}},
5271 {"mfsprg5", XSPR(31,339,261), XSPR_MASK, PPC405|BOOKE, 0, {RT}},
5272 {"mfsprg6", XSPR(31,339,262), XSPR_MASK, PPC405|BOOKE, 0, {RT}},
5273 {"mfsprg7", XSPR(31,339,263), XSPR_MASK, PPC405|BOOKE, 0, {RT}},
5274 {"mftbu", XSPR(31,339,269), XSPR_MASK, POWER4|BOOKE, 0, {RT}},
5275 {"mftb", X(31,339), X_MASK, POWER4|BOOKE, 0, {RT, TBR}},
5276 {"mftbl", XSPR(31,339,268), XSPR_MASK, POWER4|BOOKE, 0, {RT}},
5277 {"mfsprg0", XSPR(31,339,272), XSPR_MASK, PPC, 0, {RT}},
5278 {"mfsprg1", XSPR(31,339,273), XSPR_MASK, PPC, 0, {RT}},
5279 {"mfsprg2", XSPR(31,339,274), XSPR_MASK, PPC, 0, {RT}},
5280 {"mfsprg3", XSPR(31,339,275), XSPR_MASK, PPC, 0, {RT}},
5281 {"mfasr", XSPR(31,339,280), XSPR_MASK, PPC64, 0, {RT}},
5282 {"mfear", XSPR(31,339,282), XSPR_MASK, PPC, TITAN, {RT}},
5283 {"mfpir", XSPR(31,339,286), XSPR_MASK, BOOKE, 0, {RT}},
5284 {"mfpvr", XSPR(31,339,287), XSPR_MASK, PPC, 0, {RT}},
5285 {"mfdbsr", XSPR(31,339,304), XSPR_MASK, BOOKE, 0, {RT}},
5286 {"mfdbcr0", XSPR(31,339,308), XSPR_MASK, BOOKE, 0, {RT}},
5287 {"mfdbcr1", XSPR(31,339,309), XSPR_MASK, BOOKE, 0, {RT}},
5288 {"mfdbcr2", XSPR(31,339,310), XSPR_MASK, BOOKE, 0, {RT}},
5289 {"mfiac1", XSPR(31,339,312), XSPR_MASK, BOOKE, 0, {RT}},
5290 {"mfiac2", XSPR(31,339,313), XSPR_MASK, BOOKE, 0, {RT}},
5291 {"mfiac3", XSPR(31,339,314), XSPR_MASK, BOOKE, 0, {RT}},
5292 {"mfiac4", XSPR(31,339,315), XSPR_MASK, BOOKE, 0, {RT}},
5293 {"mfdac1", XSPR(31,339,316), XSPR_MASK, BOOKE, 0, {RT}},
5294 {"mfdac2", XSPR(31,339,317), XSPR_MASK, BOOKE, 0, {RT}},
5295 {"mfdvc1", XSPR(31,339,318), XSPR_MASK, BOOKE, 0, {RT}},
5296 {"mfdvc2", XSPR(31,339,319), XSPR_MASK, BOOKE, 0, {RT}},
5297 {"mftsr", XSPR(31,339,336), XSPR_MASK, BOOKE, 0, {RT}},
5298 {"mftcr", XSPR(31,339,340), XSPR_MASK, BOOKE, 0, {RT}},
5299 {"mfivor0", XSPR(31,339,400), XSPR_MASK, BOOKE, 0, {RT}},
5300 {"mfivor1", XSPR(31,339,401), XSPR_MASK, BOOKE, 0, {RT}},
5301 {"mfivor2", XSPR(31,339,402), XSPR_MASK, BOOKE, 0, {RT}},
5302 {"mfivor3", XSPR(31,339,403), XSPR_MASK, BOOKE, 0, {RT}},
5303 {"mfivor4", XSPR(31,339,404), XSPR_MASK, BOOKE, 0, {RT}},
5304 {"mfivor5", XSPR(31,339,405), XSPR_MASK, BOOKE, 0, {RT}},
5305 {"mfivor6", XSPR(31,339,406), XSPR_MASK, BOOKE, 0, {RT}},
5306 {"mfivor7", XSPR(31,339,407), XSPR_MASK, BOOKE, 0, {RT}},
5307 {"mfivor8", XSPR(31,339,408), XSPR_MASK, BOOKE, 0, {RT}},
5308 {"mfivor9", XSPR(31,339,409), XSPR_MASK, BOOKE, 0, {RT}},
5309 {"mfivor10", XSPR(31,339,410), XSPR_MASK, BOOKE, 0, {RT}},
5310 {"mfivor11", XSPR(31,339,411), XSPR_MASK, BOOKE, 0, {RT}},
5311 {"mfivor12", XSPR(31,339,412), XSPR_MASK, BOOKE, 0, {RT}},
5312 {"mfivor13", XSPR(31,339,413), XSPR_MASK, BOOKE, 0, {RT}},
5313 {"mfivor14", XSPR(31,339,414), XSPR_MASK, BOOKE, 0, {RT}},
5314 {"mfivor15", XSPR(31,339,415), XSPR_MASK, BOOKE, 0, {RT}},
5315 {"mfspefscr", XSPR(31,339,512), XSPR_MASK, PPCSPE, 0, {RT}},
5316 {"mfbbear", XSPR(31,339,513), XSPR_MASK, PPCBRLK, 0, {RT}},
5317 {"mfbbtar", XSPR(31,339,514), XSPR_MASK, PPCBRLK, 0, {RT}},
5318 {"mfivor32", XSPR(31,339,528), XSPR_MASK, PPCSPE, 0, {RT}},
5319 {"mfibatu", XSPR(31,339,528), XSPRBAT_MASK, PPC, TITAN, {RT, SPRBAT}},
5320 {"mfivor33", XSPR(31,339,529), XSPR_MASK, PPCSPE, 0, {RT}},
5321 {"mfibatl", XSPR(31,339,529), XSPRBAT_MASK, PPC, TITAN, {RT, SPRBAT}},
5322 {"mfivor34", XSPR(31,339,530), XSPR_MASK, PPCSPE, 0, {RT}},
5323 {"mfivor35", XSPR(31,339,531), XSPR_MASK, PPCPMR, 0, {RT}},
5324 {"mfdbatu", XSPR(31,339,536), XSPRBAT_MASK, PPC, TITAN, {RT, SPRBAT}},
5325 {"mfdbatl", XSPR(31,339,537), XSPRBAT_MASK, PPC, TITAN, {RT, SPRBAT}},
5326 {"mfic_cst", XSPR(31,339,560), XSPR_MASK, PPC860, 0, {RT}},
5327 {"mfic_adr", XSPR(31,339,561), XSPR_MASK, PPC860, 0, {RT}},
5328 {"mfic_dat", XSPR(31,339,562), XSPR_MASK, PPC860, 0, {RT}},
5329 {"mfdc_cst", XSPR(31,339,568), XSPR_MASK, PPC860, 0, {RT}},
5330 {"mfdc_adr", XSPR(31,339,569), XSPR_MASK, PPC860, 0, {RT}},
5331 {"mfdc_dat", XSPR(31,339,570), XSPR_MASK, PPC860, 0, {RT}},
5332 {"mfmcsrr0", XSPR(31,339,570), XSPR_MASK, PPCRFMCI, 0, {RT}},
5333 {"mfmcsrr1", XSPR(31,339,571), XSPR_MASK, PPCRFMCI, 0, {RT}},
5334 {"mfmcsr", XSPR(31,339,572), XSPR_MASK, PPCRFMCI, 0, {RT}},
5335 {"mfmcar", XSPR(31,339,573), XSPR_MASK, PPCRFMCI, TITAN, {RT}},
5336 {"mfdpdr", XSPR(31,339,630), XSPR_MASK, PPC860, 0, {RT}},
5337 {"mfdpir", XSPR(31,339,631), XSPR_MASK, PPC860, 0, {RT}},
5338 {"mfimmr", XSPR(31,339,638), XSPR_MASK, PPC860, 0, {RT}},
5339 {"mfmi_ctr", XSPR(31,339,784), XSPR_MASK, PPC860, 0, {RT}},
5340 {"mfmi_ap", XSPR(31,339,786), XSPR_MASK, PPC860, 0, {RT}},
5341 {"mfmi_epn", XSPR(31,339,787), XSPR_MASK, PPC860, 0, {RT}},
5342 {"mfmi_twc", XSPR(31,339,789), XSPR_MASK, PPC860, 0, {RT}},
5343 {"mfmi_rpn", XSPR(31,339,790), XSPR_MASK, PPC860, 0, {RT}},
5344 {"mfmd_ctr", XSPR(31,339,792), XSPR_MASK, PPC860, 0, {RT}},
5345 {"mfm_casid", XSPR(31,339,793), XSPR_MASK, PPC860, 0, {RT}},
5346 {"mfmd_ap", XSPR(31,339,794), XSPR_MASK, PPC860, 0, {RT}},
5347 {"mfmd_epn", XSPR(31,339,795), XSPR_MASK, PPC860, 0, {RT}},
5348 {"mfmd_twb", XSPR(31,339,796), XSPR_MASK, PPC860, 0, {RT}},
5349 {"mfmd_twc", XSPR(31,339,797), XSPR_MASK, PPC860, 0, {RT}},
5350 {"mfmd_rpn", XSPR(31,339,798), XSPR_MASK, PPC860, 0, {RT}},
5351 {"mfm_tw", XSPR(31,339,799), XSPR_MASK, PPC860, 0, {RT}},
5352 {"mfmi_dbcam", XSPR(31,339,816), XSPR_MASK, PPC860, 0, {RT}},
5353 {"mfmi_dbram0", XSPR(31,339,817), XSPR_MASK, PPC860, 0, {RT}},
5354 {"mfmi_dbram1", XSPR(31,339,818), XSPR_MASK, PPC860, 0, {RT}},
5355 {"mfmd_dbcam", XSPR(31,339,824), XSPR_MASK, PPC860, 0, {RT}},
5356 {"mfmd_dbram0", XSPR(31,339,825), XSPR_MASK, PPC860, 0, {RT}},
5357 {"mfmd_dbram1", XSPR(31,339,826), XSPR_MASK, PPC860, 0, {RT}},
5358 {"mfivndx", XSPR(31,339,880), XSPR_MASK, TITAN, 0, {RT}},
5359 {"mfdvndx", XSPR(31,339,881), XSPR_MASK, TITAN, 0, {RT}},
5360 {"mfivlim", XSPR(31,339,882), XSPR_MASK, TITAN, 0, {RT}},
5361 {"mfdvlim", XSPR(31,339,883), XSPR_MASK, TITAN, 0, {RT}},
5362 {"mfclcsr", XSPR(31,339,884), XSPR_MASK, TITAN, 0, {RT}},
5363 {"mfccr1", XSPR(31,339,888), XSPR_MASK, TITAN, 0, {RT}},
5364 {"mfppr", XSPR(31,339,896), XSPR_MASK, POWER7, 0, {RT}},
5365 {"mfppr32", XSPR(31,339,898), XSPR_MASK, POWER7, 0, {RT}},
5366 {"mfrstcfg", XSPR(31,339,923), XSPR_MASK, TITAN, 0, {RT}},
5367 {"mfdcdbtrl", XSPR(31,339,924), XSPR_MASK, TITAN, 0, {RT}},
5368 {"mfdcdbtrh", XSPR(31,339,925), XSPR_MASK, TITAN, 0, {RT}},
5369 {"mficdbtr", XSPR(31,339,927), XSPR_MASK, TITAN, 0, {RT}},
5370 {"mfummcr0", XSPR(31,339,936), XSPR_MASK, PPC750, 0, {RT}},
5371 {"mfupmc1", XSPR(31,339,937), XSPR_MASK, PPC750, 0, {RT}},
5372 {"mfupmc2", XSPR(31,339,938), XSPR_MASK, PPC750, 0, {RT}},
5373 {"mfusia", XSPR(31,339,939), XSPR_MASK, PPC750, 0, {RT}},
5374 {"mfummcr1", XSPR(31,339,940), XSPR_MASK, PPC750, 0, {RT}},
5375 {"mfupmc3", XSPR(31,339,941), XSPR_MASK, PPC750, 0, {RT}},
5376 {"mfupmc4", XSPR(31,339,942), XSPR_MASK, PPC750, 0, {RT}},
5377 {"mfzpr", XSPR(31,339,944), XSPR_MASK, PPC403, 0, {RT}},
5378 {"mfpid", XSPR(31,339,945), XSPR_MASK, PPC403, 0, {RT}},
5379 {"mfmmucr", XSPR(31,339,946), XSPR_MASK, TITAN, 0, {RT}},
5380 {"mfccr0", XSPR(31,339,947), XSPR_MASK, PPC405|TITAN, 0, {RT}},
5381 {"mfiac3", XSPR(31,339,948), XSPR_MASK, PPC405, 0, {RT}},
5382 {"mfiac4", XSPR(31,339,949), XSPR_MASK, PPC405, 0, {RT}},
5383 {"mfdvc1", XSPR(31,339,950), XSPR_MASK, PPC405, 0, {RT}},
5384 {"mfdvc2", XSPR(31,339,951), XSPR_MASK, PPC405, 0, {RT}},
5385 {"mfmmcr0", XSPR(31,339,952), XSPR_MASK, PPC750, 0, {RT}},
5386 {"mfpmc1", XSPR(31,339,953), XSPR_MASK, PPC750, 0, {RT}},
5387 {"mfsgr", XSPR(31,339,953), XSPR_MASK, PPC403, 0, {RT}},
5388 {"mfdcwr", XSPR(31,339,954), XSPR_MASK, PPC403, 0, {RT}},
5389 {"mfpmc2", XSPR(31,339,954), XSPR_MASK, PPC750, 0, {RT}},
5390 {"mfsia", XSPR(31,339,955), XSPR_MASK, PPC750, 0, {RT}},
5391 {"mfsler", XSPR(31,339,955), XSPR_MASK, PPC405, 0, {RT}},
5392 {"mfmmcr1", XSPR(31,339,956), XSPR_MASK, PPC750, 0, {RT}},
5393 {"mfsu0r", XSPR(31,339,956), XSPR_MASK, PPC405, 0, {RT}},
5394 {"mfdbcr1", XSPR(31,339,957), XSPR_MASK, PPC405, 0, {RT}},
5395 {"mfpmc3", XSPR(31,339,957), XSPR_MASK, PPC750, 0, {RT}},
5396 {"mfpmc4", XSPR(31,339,958), XSPR_MASK, PPC750, 0, {RT}},
5397 {"mficdbdr", XSPR(31,339,979), XSPR_MASK, PPC403|TITAN, 0, {RT}},
5398 {"mfesr", XSPR(31,339,980), XSPR_MASK, PPC403, 0, {RT}},
5399 {"mfdear", XSPR(31,339,981), XSPR_MASK, PPC403, 0, {RT}},
5400 {"mfevpr", XSPR(31,339,982), XSPR_MASK, PPC403, 0, {RT}},
5401 {"mfcdbcr", XSPR(31,339,983), XSPR_MASK, PPC403, 0, {RT}},
5402 {"mftsr", XSPR(31,339,984), XSPR_MASK, PPC403, 0, {RT}},
5403 {"mftcr", XSPR(31,339,986), XSPR_MASK, PPC403, 0, {RT}},
5404 {"mfpit", XSPR(31,339,987), XSPR_MASK, PPC403, 0, {RT}},
5405 {"mftbhi", XSPR(31,339,988), XSPR_MASK, PPC403, 0, {RT}},
5406 {"mftblo", XSPR(31,339,989), XSPR_MASK, PPC403, 0, {RT}},
5407 {"mfsrr2", XSPR(31,339,990), XSPR_MASK, PPC403, 0, {RT}},
5408 {"mfsrr3", XSPR(31,339,991), XSPR_MASK, PPC403, 0, {RT}},
5409 {"mfdbsr", XSPR(31,339,1008), XSPR_MASK, PPC403, 0, {RT}},
5410 {"mfdbcr0", XSPR(31,339,1010), XSPR_MASK, PPC405, 0, {RT}},
5411 {"mfdbdr", XSPR(31,339,1011), XSPR_MASK, TITAN, 0, {RS}},
5412 {"mfiac1", XSPR(31,339,1012), XSPR_MASK, PPC403, 0, {RT}},
5413 {"mfiac2", XSPR(31,339,1013), XSPR_MASK, PPC403, 0, {RT}},
5414 {"mfdac1", XSPR(31,339,1014), XSPR_MASK, PPC403, 0, {RT}},
5415 {"mfdac2", XSPR(31,339,1015), XSPR_MASK, PPC403, 0, {RT}},
5416 {"mfl2cr", XSPR(31,339,1017), XSPR_MASK, PPC750, 0, {RT}},
5417 {"mfdccr", XSPR(31,339,1018), XSPR_MASK, PPC403, 0, {RT}},
5418 {"mficcr", XSPR(31,339,1019), XSPR_MASK, PPC403, 0, {RT}},
5419 {"mfictc", XSPR(31,339,1019), XSPR_MASK, PPC750, 0, {RT}},
5420 {"mfpbl1", XSPR(31,339,1020), XSPR_MASK, PPC403, 0, {RT}},
5421 {"mfthrm1", XSPR(31,339,1020), XSPR_MASK, PPC750, 0, {RT}},
5422 {"mfpbu1", XSPR(31,339,1021), XSPR_MASK, PPC403, 0, {RT}},
5423 {"mfthrm2", XSPR(31,339,1021), XSPR_MASK, PPC750, 0, {RT}},
5424 {"mfpbl2", XSPR(31,339,1022), XSPR_MASK, PPC403, 0, {RT}},
5425 {"mfthrm3", XSPR(31,339,1022), XSPR_MASK, PPC750, 0, {RT}},
5426 {"mfpbu2", XSPR(31,339,1023), XSPR_MASK, PPC403, 0, {RT}},
5427 {"mfspr", X(31,339), X_MASK, COM, 0, {RT, SPR}},
5429 {"lwax", X(31,341), X_MASK, PPC64, 0, {RT, RA0, RB}},
5431 {"dst", XDSS(31,342,0), XDSS_MASK, PPCVEC, 0, {RA, RB, STRM}},
5433 {"lhax", X(31,343), X_MASK, COM, 0, {RT, RA0, RB}},
5435 {"lvxl", X(31,359), X_MASK, PPCVEC, 0, {VD, RA0, RB}},
5437 {"abs", XO(31,360,0,0), XORB_MASK, M601, 0, {RT, RA}},
5438 {"abs.", XO(31,360,0,1), XORB_MASK, M601, 0, {RT, RA}},
5440 {"divs", XO(31,363,0,0), XO_MASK, M601, 0, {RT, RA, RB}},
5441 {"divs.", XO(31,363,0,1), XO_MASK, M601, 0, {RT, RA, RB}},
5443 {"lxvwsx", X(31,364), XX1_MASK, PPCVSX3, 0, {XT6, RA0, RB}},
5445 {"tlbia", X(31,370), 0xffffffff, PPC, E500|TITAN, {0}},
5447 {"mftbu", XSPR(31,371,269), XSPR_MASK, PPC, NO371|POWER4, {RT}},
5448 {"mftb", X(31,371), X_MASK, PPC, NO371|POWER4, {RT, TBR}},
5449 {"mftbl", XSPR(31,371,268), XSPR_MASK, PPC, NO371|POWER4, {RT}},
5451 {"lwaux", X(31,373), X_MASK, PPC64, 0, {RT, RAL, RB}},
5453 {"dstst", XDSS(31,374,0), XDSS_MASK, PPCVEC, 0, {RA, RB, STRM}},
5455 {"lhaux", X(31,375), X_MASK, COM, 0, {RT, RAL, RB}},
5457 {"popcntw", X(31,378), XRB_MASK, POWER7|PPCA2, 0, {RA, RS}},
5459 {"mtdcrx", X(31,387), X_MASK, BOOKE|PPCA2|PPC476, TITAN, {RA, RS}},
5460 {"mtdcrx.", XRC(31,387,1), X_MASK, PPCA2, 0, {RA, RS}},
5462 {"stvexbx", X(31,389), X_MASK, PPCVEC2, 0, {VS, RA0, RB}},
5464 {"dcblc", X(31,390), X_MASK, PPCCHLK|PPC476|TITAN, 0, {CT, RA0, RB}},
5465 {"stdfcmx", APU(31,391,0), APU_MASK, PPC405, 0, {FCRT, RA, RB}},
5467 {"divdeu", XO(31,393,0,0), XO_MASK, POWER7|PPCA2, 0, {RT, RA, RB}},
5468 {"divdeu.", XO(31,393,0,1), XO_MASK, POWER7|PPCA2, 0, {RT, RA, RB}},
5469 {"divweu", XO(31,395,0,0), XO_MASK, POWER7|PPCA2, 0, {RT, RA, RB}},
5470 {"divweu.", XO(31,395,0,1), XO_MASK, POWER7|PPCA2, 0, {RT, RA, RB}},
5472 {"stxvx", X(31,396), XX1_MASK, PPCVSX3, 0, {XS6, RA0, RB}},
5473 {"stxvl", X(31,397), XX1_MASK, PPCVSX3, 0, {XS6, RA0, RB}},
5475 {"dcblce", X(31,398), X_MASK, PPCCHLK, E500MC, {CT, RA, RB}},
5477 {"slbmte", X(31,402), XRA_MASK, PPC64, 0, {RS, RB}},
5479 {"mtvsrws", X(31,403), XX1RB_MASK, PPCVSX3, 0, {XT6, RA}},
5481 {"pbt.", XRC(31,404,1), X_MASK, POWER8, 0, {RS, RA0, RB}},
5483 {"icswx", XRC(31,406,0), X_MASK, POWER7|PPCA2, 0, {RS, RA, RB}},
5484 {"icswx.", XRC(31,406,1), X_MASK, POWER7|PPCA2, 0, {RS, RA, RB}},
5486 {"sthx", X(31,407), X_MASK, COM, 0, {RS, RA0, RB}},
5488 {"orc", XRC(31,412,0), X_MASK, COM, 0, {RA, RS, RB}},
5489 {"orc.", XRC(31,412,1), X_MASK, COM, 0, {RA, RS, RB}},
5491 {"sthepx", X(31,415), X_MASK, E500MC|PPCA2, 0, {RS, RA0, RB}},
5493 {"mtdcrux", X(31,419), X_MASK, PPC464, 0, {RA, RS}},
5495 {"stvexhx", X(31,421), X_MASK, PPCVEC2, 0, {VS, RA0, RB}},
5497 {"dcblq.", XRC(31,422,1), X_MASK, E6500, 0, {CT, RA0, RB}},
5499 {"divde", XO(31,425,0,0), XO_MASK, POWER7|PPCA2, 0, {RT, RA, RB}},
5500 {"divde.", XO(31,425,0,1), XO_MASK, POWER7|PPCA2, 0, {RT, RA, RB}},
5501 {"divwe", XO(31,427,0,0), XO_MASK, POWER7|PPCA2, 0, {RT, RA, RB}},
5502 {"divwe.", XO(31,427,0,1), XO_MASK, POWER7|PPCA2, 0, {RT, RA, RB}},
5504 {"stxvll", X(31,429), XX1_MASK, PPCVSX3, 0, {XS6, RA0, RB}},
5506 {"clrbhrb", X(31,430), 0xffffffff, POWER8, 0, {0}},
5508 {"slbie", X(31,434), XRTRA_MASK, PPC64, 0, {RB}},
5510 {"mtvsrdd", X(31,435), XX1_MASK, PPCVSX3, 0, {XT6, RA0, RB}},
5512 {"lwzmx", X(31,437), X_MASK, POWER9, 0, {RT, RA0, RB}},
5514 {"ecowx", X(31,438), X_MASK, PPC, E500|TITAN, {RT, RA0, RB}},
5516 {"sthux", X(31,439), X_MASK, COM, 0, {RS, RAS, RB}},
5518 {"mdors", 0x7f9ce378, 0xffffffff, E500MC, 0, {0}},
5520 {"miso", 0x7f5ad378, 0xffffffff, E6500, 0, {0}},
5522 /* The "yield", "mdoio" and "mdoom" instructions are extended mnemonics for
5523 "or rX,rX,rX", with rX being r27, r29 and r30 respectively. */
5524 {"yield", 0x7f7bdb78, 0xffffffff, POWER7, 0, {0}},
5525 {"mdoio", 0x7fbdeb78, 0xffffffff, POWER7, 0, {0}},
5526 {"mdoom", 0x7fdef378, 0xffffffff, POWER7, 0, {0}},
5527 {"mr", XRC(31,444,0), X_MASK, COM, 0, {RA, RS, RBS}},
5528 {"or", XRC(31,444,0), X_MASK, COM, 0, {RA, RS, RB}},
5529 {"mr.", XRC(31,444,1), X_MASK, COM, 0, {RA, RS, RBS}},
5530 {"or.", XRC(31,444,1), X_MASK, COM, 0, {RA, RS, RB}},
5532 {"mtexisr", XSPR(31,451, 64), XSPR_MASK, PPC403, 0, {RS}},
5533 {"mtexier", XSPR(31,451, 66), XSPR_MASK, PPC403, 0, {RS}},
5534 {"mtbr0", XSPR(31,451,128), XSPR_MASK, PPC403, 0, {RS}},
5535 {"mtbr1", XSPR(31,451,129), XSPR_MASK, PPC403, 0, {RS}},
5536 {"mtbr2", XSPR(31,451,130), XSPR_MASK, PPC403, 0, {RS}},
5537 {"mtbr3", XSPR(31,451,131), XSPR_MASK, PPC403, 0, {RS}},
5538 {"mtbr4", XSPR(31,451,132), XSPR_MASK, PPC403, 0, {RS}},
5539 {"mtbr5", XSPR(31,451,133), XSPR_MASK, PPC403, 0, {RS}},
5540 {"mtbr6", XSPR(31,451,134), XSPR_MASK, PPC403, 0, {RS}},
5541 {"mtbr7", XSPR(31,451,135), XSPR_MASK, PPC403, 0, {RS}},
5542 {"mtbear", XSPR(31,451,144), XSPR_MASK, PPC403, 0, {RS}},
5543 {"mtbesr", XSPR(31,451,145), XSPR_MASK, PPC403, 0, {RS}},
5544 {"mtiocr", XSPR(31,451,160), XSPR_MASK, PPC403, 0, {RS}},
5545 {"mtdmacr0", XSPR(31,451,192), XSPR_MASK, PPC403, 0, {RS}},
5546 {"mtdmact0", XSPR(31,451,193), XSPR_MASK, PPC403, 0, {RS}},
5547 {"mtdmada0", XSPR(31,451,194), XSPR_MASK, PPC403, 0, {RS}},
5548 {"mtdmasa0", XSPR(31,451,195), XSPR_MASK, PPC403, 0, {RS}},
5549 {"mtdmacc0", XSPR(31,451,196), XSPR_MASK, PPC403, 0, {RS}},
5550 {"mtdmacr1", XSPR(31,451,200), XSPR_MASK, PPC403, 0, {RS}},
5551 {"mtdmact1", XSPR(31,451,201), XSPR_MASK, PPC403, 0, {RS}},
5552 {"mtdmada1", XSPR(31,451,202), XSPR_MASK, PPC403, 0, {RS}},
5553 {"mtdmasa1", XSPR(31,451,203), XSPR_MASK, PPC403, 0, {RS}},
5554 {"mtdmacc1", XSPR(31,451,204), XSPR_MASK, PPC403, 0, {RS}},
5555 {"mtdmacr2", XSPR(31,451,208), XSPR_MASK, PPC403, 0, {RS}},
5556 {"mtdmact2", XSPR(31,451,209), XSPR_MASK, PPC403, 0, {RS}},
5557 {"mtdmada2", XSPR(31,451,210), XSPR_MASK, PPC403, 0, {RS}},
5558 {"mtdmasa2", XSPR(31,451,211), XSPR_MASK, PPC403, 0, {RS}},
5559 {"mtdmacc2", XSPR(31,451,212), XSPR_MASK, PPC403, 0, {RS}},
5560 {"mtdmacr3", XSPR(31,451,216), XSPR_MASK, PPC403, 0, {RS}},
5561 {"mtdmact3", XSPR(31,451,217), XSPR_MASK, PPC403, 0, {RS}},
5562 {"mtdmada3", XSPR(31,451,218), XSPR_MASK, PPC403, 0, {RS}},
5563 {"mtdmasa3", XSPR(31,451,219), XSPR_MASK, PPC403, 0, {RS}},
5564 {"mtdmacc3", XSPR(31,451,220), XSPR_MASK, PPC403, 0, {RS}},
5565 {"mtdmasr", XSPR(31,451,224), XSPR_MASK, PPC403, 0, {RS}},
5566 {"mtdcr", X(31,451), X_MASK, PPC403|BOOKE|PPCA2|PPC476, E500|TITAN, {SPR, RS}},
5567 {"mtdcr.", XRC(31,451,1), X_MASK, PPCA2, 0, {SPR, RS}},
5569 {"stvexwx", X(31,453), X_MASK, PPCVEC2, 0, {VS, RA0, RB}},
5571 {"dccci", X(31,454), XRT_MASK, PPC403|PPC440|TITAN|PPCA2, 0, {RAOPT, RBOPT}},
5572 {"dci", X(31,454), XRARB_MASK, PPCA2|PPC476, 0, {CT}},
5574 {"divdu", XO(31,457,0,0), XO_MASK, PPC64, 0, {RT, RA, RB}},
5575 {"divdu.", XO(31,457,0,1), XO_MASK, PPC64, 0, {RT, RA, RB}},
5577 {"divwu", XO(31,459,0,0), XO_MASK, PPC, 0, {RT, RA, RB}},
5578 {"divwu.", XO(31,459,0,1), XO_MASK, PPC, 0, {RT, RA, RB}},
5580 {"mtpmr", X(31,462), X_MASK, PPCPMR|PPCE300, 0, {PMR, RS}},
5581 {"mttmr", X(31,494), X_MASK, PPCTMR|E6500, 0, {TMR, RS}},
5583 {"slbieg", X(31,466), XRA_MASK, POWER9, 0, {RS, RB}},
5585 {"mtmq", XSPR(31,467, 0), XSPR_MASK, M601, 0, {RS}},
5586 {"mtxer", XSPR(31,467, 1), XSPR_MASK, COM, 0, {RS}},
5587 {"mtlr", XSPR(31,467, 8), XSPR_MASK, COM, 0, {RS}},
5588 {"mtctr", XSPR(31,467, 9), XSPR_MASK, COM, 0, {RS}},
5589 {"mtdscr", XSPR(31,467, 17), XSPR_MASK, POWER6, 0, {RS}},
5590 {"mttid", XSPR(31,467, 17), XSPR_MASK, POWER, 0, {RS}},
5591 {"mtdsisr", XSPR(31,467, 18), XSPR_MASK, COM, TITAN, {RS}},
5592 {"mtdar", XSPR(31,467, 19), XSPR_MASK, COM, TITAN, {RS}},
5593 {"mtrtcu", XSPR(31,467, 20), XSPR_MASK, COM, TITAN, {RS}},
5594 {"mtrtcl", XSPR(31,467, 21), XSPR_MASK, COM, TITAN, {RS}},
5595 {"mtdec", XSPR(31,467, 22), XSPR_MASK, COM, 0, {RS}},
5596 {"mtsdr0", XSPR(31,467, 24), XSPR_MASK, POWER, 0, {RS}},
5597 {"mtsdr1", XSPR(31,467, 25), XSPR_MASK, COM, TITAN, {RS}},
5598 {"mtsrr0", XSPR(31,467, 26), XSPR_MASK, COM, 0, {RS}},
5599 {"mtsrr1", XSPR(31,467, 27), XSPR_MASK, COM, 0, {RS}},
5600 {"mtcfar", XSPR(31,467, 28), XSPR_MASK, POWER6, 0, {RS}},
5601 {"mtpid", XSPR(31,467, 48), XSPR_MASK, BOOKE, 0, {RS}},
5602 {"mtdecar", XSPR(31,467, 54), XSPR_MASK, BOOKE, 0, {RS}},
5603 {"mtcsrr0", XSPR(31,467, 58), XSPR_MASK, BOOKE, 0, {RS}},
5604 {"mtcsrr1", XSPR(31,467, 59), XSPR_MASK, BOOKE, 0, {RS}},
5605 {"mtdear", XSPR(31,467, 61), XSPR_MASK, BOOKE, 0, {RS}},
5606 {"mtesr", XSPR(31,467, 62), XSPR_MASK, BOOKE, 0, {RS}},
5607 {"mtivpr", XSPR(31,467, 63), XSPR_MASK, BOOKE, 0, {RS}},
5608 {"mtcmpa", XSPR(31,467,144), XSPR_MASK, PPC860, 0, {RS}},
5609 {"mtcmpb", XSPR(31,467,145), XSPR_MASK, PPC860, 0, {RS}},
5610 {"mtcmpc", XSPR(31,467,146), XSPR_MASK, PPC860, 0, {RS}},
5611 {"mtcmpd", XSPR(31,467,147), XSPR_MASK, PPC860, 0, {RS}},
5612 {"mticr", XSPR(31,467,148), XSPR_MASK, PPC860, 0, {RS}},
5613 {"mtder", XSPR(31,467,149), XSPR_MASK, PPC860, 0, {RS}},
5614 {"mtcounta", XSPR(31,467,150), XSPR_MASK, PPC860, 0, {RS}},
5615 {"mtcountb", XSPR(31,467,151), XSPR_MASK, PPC860, 0, {RS}},
5616 {"mtctrl", XSPR(31,467,152), XSPR_MASK, POWER4, 0, {RS}},
5617 {"mtcmpe", XSPR(31,467,152), XSPR_MASK, PPC860, 0, {RS}},
5618 {"mtcmpf", XSPR(31,467,153), XSPR_MASK, PPC860, 0, {RS}},
5619 {"mtcmpg", XSPR(31,467,154), XSPR_MASK, PPC860, 0, {RS}},
5620 {"mtcmph", XSPR(31,467,155), XSPR_MASK, PPC860, 0, {RS}},
5621 {"mtlctrl1", XSPR(31,467,156), XSPR_MASK, PPC860, 0, {RS}},
5622 {"mtlctrl2", XSPR(31,467,157), XSPR_MASK, PPC860, 0, {RS}},
5623 {"mtictrl", XSPR(31,467,158), XSPR_MASK, PPC860, 0, {RS}},
5624 {"mtbar", XSPR(31,467,159), XSPR_MASK, PPC860, 0, {RS}},
5625 {"mtvrsave", XSPR(31,467,256), XSPR_MASK, PPCVEC, 0, {RS}},
5626 {"mtusprg0", XSPR(31,467,256), XSPR_MASK, BOOKE, 0, {RS}},
5627 {"mtsprg", XSPR(31,467,256), XSPRG_MASK, PPC, 0, {SPRG, RS}},
5628 {"mtsprg0", XSPR(31,467,272), XSPR_MASK, PPC, 0, {RS}},
5629 {"mtsprg1", XSPR(31,467,273), XSPR_MASK, PPC, 0, {RS}},
5630 {"mtsprg2", XSPR(31,467,274), XSPR_MASK, PPC, 0, {RS}},
5631 {"mtsprg3", XSPR(31,467,275), XSPR_MASK, PPC, 0, {RS}},
5632 {"mtsprg4", XSPR(31,467,276), XSPR_MASK, PPC405|BOOKE, 0, {RS}},
5633 {"mtsprg5", XSPR(31,467,277), XSPR_MASK, PPC405|BOOKE, 0, {RS}},
5634 {"mtsprg6", XSPR(31,467,278), XSPR_MASK, PPC405|BOOKE, 0, {RS}},
5635 {"mtsprg7", XSPR(31,467,279), XSPR_MASK, PPC405|BOOKE, 0, {RS}},
5636 {"mtasr", XSPR(31,467,280), XSPR_MASK, PPC64, 0, {RS}},
5637 {"mtear", XSPR(31,467,282), XSPR_MASK, PPC, TITAN, {RS}},
5638 {"mttbl", XSPR(31,467,284), XSPR_MASK, PPC, 0, {RS}},
5639 {"mttbu", XSPR(31,467,285), XSPR_MASK, PPC, 0, {RS}},
5640 {"mtdbsr", XSPR(31,467,304), XSPR_MASK, BOOKE, 0, {RS}},
5641 {"mtdbcr0", XSPR(31,467,308), XSPR_MASK, BOOKE, 0, {RS}},
5642 {"mtdbcr1", XSPR(31,467,309), XSPR_MASK, BOOKE, 0, {RS}},
5643 {"mtdbcr2", XSPR(31,467,310), XSPR_MASK, BOOKE, 0, {RS}},
5644 {"mtiac1", XSPR(31,467,312), XSPR_MASK, BOOKE, 0, {RS}},
5645 {"mtiac2", XSPR(31,467,313), XSPR_MASK, BOOKE, 0, {RS}},
5646 {"mtiac3", XSPR(31,467,314), XSPR_MASK, BOOKE, 0, {RS}},
5647 {"mtiac4", XSPR(31,467,315), XSPR_MASK, BOOKE, 0, {RS}},
5648 {"mtdac1", XSPR(31,467,316), XSPR_MASK, BOOKE, 0, {RS}},
5649 {"mtdac2", XSPR(31,467,317), XSPR_MASK, BOOKE, 0, {RS}},
5650 {"mtdvc1", XSPR(31,467,318), XSPR_MASK, BOOKE, 0, {RS}},
5651 {"mtdvc2", XSPR(31,467,319), XSPR_MASK, BOOKE, 0, {RS}},
5652 {"mttsr", XSPR(31,467,336), XSPR_MASK, BOOKE, 0, {RS}},
5653 {"mttcr", XSPR(31,467,340), XSPR_MASK, BOOKE, 0, {RS}},
5654 {"mtivor0", XSPR(31,467,400), XSPR_MASK, BOOKE, 0, {RS}},
5655 {"mtivor1", XSPR(31,467,401), XSPR_MASK, BOOKE, 0, {RS}},
5656 {"mtivor2", XSPR(31,467,402), XSPR_MASK, BOOKE, 0, {RS}},
5657 {"mtivor3", XSPR(31,467,403), XSPR_MASK, BOOKE, 0, {RS}},
5658 {"mtivor4", XSPR(31,467,404), XSPR_MASK, BOOKE, 0, {RS}},
5659 {"mtivor5", XSPR(31,467,405), XSPR_MASK, BOOKE, 0, {RS}},
5660 {"mtivor6", XSPR(31,467,406), XSPR_MASK, BOOKE, 0, {RS}},
5661 {"mtivor7", XSPR(31,467,407), XSPR_MASK, BOOKE, 0, {RS}},
5662 {"mtivor8", XSPR(31,467,408), XSPR_MASK, BOOKE, 0, {RS}},
5663 {"mtivor9", XSPR(31,467,409), XSPR_MASK, BOOKE, 0, {RS}},
5664 {"mtivor10", XSPR(31,467,410), XSPR_MASK, BOOKE, 0, {RS}},
5665 {"mtivor11", XSPR(31,467,411), XSPR_MASK, BOOKE, 0, {RS}},
5666 {"mtivor12", XSPR(31,467,412), XSPR_MASK, BOOKE, 0, {RS}},
5667 {"mtivor13", XSPR(31,467,413), XSPR_MASK, BOOKE, 0, {RS}},
5668 {"mtivor14", XSPR(31,467,414), XSPR_MASK, BOOKE, 0, {RS}},
5669 {"mtivor15", XSPR(31,467,415), XSPR_MASK, BOOKE, 0, {RS}},
5670 {"mtspefscr", XSPR(31,467,512), XSPR_MASK, PPCSPE, 0, {RS}},
5671 {"mtbbear", XSPR(31,467,513), XSPR_MASK, PPCBRLK, 0, {RS}},
5672 {"mtbbtar", XSPR(31,467,514), XSPR_MASK, PPCBRLK, 0, {RS}},
5673 {"mtivor32", XSPR(31,467,528), XSPR_MASK, PPCSPE, 0, {RS}},
5674 {"mtibatu", XSPR(31,467,528), XSPRBAT_MASK, PPC, TITAN, {SPRBAT, RS}},
5675 {"mtivor33", XSPR(31,467,529), XSPR_MASK, PPCSPE, 0, {RS}},
5676 {"mtibatl", XSPR(31,467,529), XSPRBAT_MASK, PPC, TITAN, {SPRBAT, RS}},
5677 {"mtivor34", XSPR(31,467,530), XSPR_MASK, PPCSPE, 0, {RS}},
5678 {"mtivor35", XSPR(31,467,531), XSPR_MASK, PPCPMR, 0, {RS}},
5679 {"mtdbatu", XSPR(31,467,536), XSPRBAT_MASK, PPC, TITAN, {SPRBAT, RS}},
5680 {"mtdbatl", XSPR(31,467,537), XSPRBAT_MASK, PPC, TITAN, {SPRBAT, RS}},
5681 {"mtmcsrr0", XSPR(31,467,570), XSPR_MASK, PPCRFMCI, 0, {RS}},
5682 {"mtmcsrr1", XSPR(31,467,571), XSPR_MASK, PPCRFMCI, 0, {RS}},
5683 {"mtmcsr", XSPR(31,467,572), XSPR_MASK, PPCRFMCI, 0, {RS}},
5684 {"mtivndx", XSPR(31,467,880), XSPR_MASK, TITAN, 0, {RS}},
5685 {"mtdvndx", XSPR(31,467,881), XSPR_MASK, TITAN, 0, {RS}},
5686 {"mtivlim", XSPR(31,467,882), XSPR_MASK, TITAN, 0, {RS}},
5687 {"mtdvlim", XSPR(31,467,883), XSPR_MASK, TITAN, 0, {RS}},
5688 {"mtclcsr", XSPR(31,467,884), XSPR_MASK, TITAN, 0, {RS}},
5689 {"mtccr1", XSPR(31,467,888), XSPR_MASK, TITAN, 0, {RS}},
5690 {"mtppr", XSPR(31,467,896), XSPR_MASK, POWER7, 0, {RS}},
5691 {"mtppr32", XSPR(31,467,898), XSPR_MASK, POWER7, 0, {RS}},
5692 {"mtummcr0", XSPR(31,467,936), XSPR_MASK, PPC750, 0, {RS}},
5693 {"mtupmc1", XSPR(31,467,937), XSPR_MASK, PPC750, 0, {RS}},
5694 {"mtupmc2", XSPR(31,467,938), XSPR_MASK, PPC750, 0, {RS}},
5695 {"mtusia", XSPR(31,467,939), XSPR_MASK, PPC750, 0, {RS}},
5696 {"mtummcr1", XSPR(31,467,940), XSPR_MASK, PPC750, 0, {RS}},
5697 {"mtupmc3", XSPR(31,467,941), XSPR_MASK, PPC750, 0, {RS}},
5698 {"mtupmc4", XSPR(31,467,942), XSPR_MASK, PPC750, 0, {RS}},
5699 {"mtzpr", XSPR(31,467,944), XSPR_MASK, PPC403, 0, {RS}},
5700 {"mtpid", XSPR(31,467,945), XSPR_MASK, PPC403, 0, {RS}},
5701 {"mtrmmucr", XSPR(31,467,946), XSPR_MASK, TITAN, 0, {RS}},
5702 {"mtccr0", XSPR(31,467,947), XSPR_MASK, PPC405|TITAN, 0, {RS}},
5703 {"mtiac3", XSPR(31,467,948), XSPR_MASK, PPC405, 0, {RS}},
5704 {"mtiac4", XSPR(31,467,949), XSPR_MASK, PPC405, 0, {RS}},
5705 {"mtdvc1", XSPR(31,467,950), XSPR_MASK, PPC405, 0, {RS}},
5706 {"mtdvc2", XSPR(31,467,951), XSPR_MASK, PPC405, 0, {RS}},
5707 {"mtmmcr0", XSPR(31,467,952), XSPR_MASK, PPC750, 0, {RS}},
5708 {"mtpmc1", XSPR(31,467,953), XSPR_MASK, PPC750, 0, {RS}},
5709 {"mtsgr", XSPR(31,467,953), XSPR_MASK, PPC403, 0, {RS}},
5710 {"mtdcwr", XSPR(31,467,954), XSPR_MASK, PPC403, 0, {RS}},
5711 {"mtpmc2", XSPR(31,467,954), XSPR_MASK, PPC750, 0, {RS}},
5712 {"mtsia", XSPR(31,467,955), XSPR_MASK, PPC750, 0, {RS}},
5713 {"mtsler", XSPR(31,467,955), XSPR_MASK, PPC405, 0, {RS}},
5714 {"mtmmcr1", XSPR(31,467,956), XSPR_MASK, PPC750, 0, {RS}},
5715 {"mtsu0r", XSPR(31,467,956), XSPR_MASK, PPC405, 0, {RS}},
5716 {"mtdbcr1", XSPR(31,467,957), XSPR_MASK, PPC405, 0, {RS}},
5717 {"mtpmc3", XSPR(31,467,957), XSPR_MASK, PPC750, 0, {RS}},
5718 {"mtpmc4", XSPR(31,467,958), XSPR_MASK, PPC750, 0, {RS}},
5719 {"mticdbdr", XSPR(31,467,979), XSPR_MASK, PPC403, 0, {RS}},
5720 {"mtesr", XSPR(31,467,980), XSPR_MASK, PPC403, 0, {RS}},
5721 {"mtdear", XSPR(31,467,981), XSPR_MASK, PPC403, 0, {RS}},
5722 {"mtevpr", XSPR(31,467,982), XSPR_MASK, PPC403, 0, {RS}},
5723 {"mtcdbcr", XSPR(31,467,983), XSPR_MASK, PPC403, 0, {RS}},
5724 {"mttsr", XSPR(31,467,984), XSPR_MASK, PPC403, 0, {RS}},
5725 {"mttcr", XSPR(31,467,986), XSPR_MASK, PPC403, 0, {RS}},
5726 {"mtpit", XSPR(31,467,987), XSPR_MASK, PPC403, 0, {RS}},
5727 {"mttbhi", XSPR(31,467,988), XSPR_MASK, PPC403, 0, {RS}},
5728 {"mttblo", XSPR(31,467,989), XSPR_MASK, PPC403, 0, {RS}},
5729 {"mtsrr2", XSPR(31,467,990), XSPR_MASK, PPC403, 0, {RS}},
5730 {"mtsrr3", XSPR(31,467,991), XSPR_MASK, PPC403, 0, {RS}},
5731 {"mtdbsr", XSPR(31,467,1008), XSPR_MASK, PPC403, 0, {RS}},
5732 {"mtdbdr", XSPR(31,467,1011), XSPR_MASK, TITAN, 0, {RS}},
5733 {"mtdbcr0", XSPR(31,467,1010), XSPR_MASK, PPC405, 0, {RS}},
5734 {"mtiac1", XSPR(31,467,1012), XSPR_MASK, PPC403, 0, {RS}},
5735 {"mtiac2", XSPR(31,467,1013), XSPR_MASK, PPC403, 0, {RS}},
5736 {"mtdac1", XSPR(31,467,1014), XSPR_MASK, PPC403, 0, {RS}},
5737 {"mtdac2", XSPR(31,467,1015), XSPR_MASK, PPC403, 0, {RS}},
5738 {"mtl2cr", XSPR(31,467,1017), XSPR_MASK, PPC750, 0, {RS}},
5739 {"mtdccr", XSPR(31,467,1018), XSPR_MASK, PPC403, 0, {RS}},
5740 {"mticcr", XSPR(31,467,1019), XSPR_MASK, PPC403, 0, {RS}},
5741 {"mtictc", XSPR(31,467,1019), XSPR_MASK, PPC750, 0, {RS}},
5742 {"mtpbl1", XSPR(31,467,1020), XSPR_MASK, PPC403, 0, {RS}},
5743 {"mtthrm1", XSPR(31,467,1020), XSPR_MASK, PPC750, 0, {RS}},
5744 {"mtpbu1", XSPR(31,467,1021), XSPR_MASK, PPC403, 0, {RS}},
5745 {"mtthrm2", XSPR(31,467,1021), XSPR_MASK, PPC750, 0, {RS}},
5746 {"mtpbl2", XSPR(31,467,1022), XSPR_MASK, PPC403, 0, {RS}},
5747 {"mtthrm3", XSPR(31,467,1022), XSPR_MASK, PPC750, 0, {RS}},
5748 {"mtpbu2", XSPR(31,467,1023), XSPR_MASK, PPC403, 0, {RS}},
5749 {"mtspr", X(31,467), X_MASK, COM, 0, {SPR, RS}},
5751 {"dcbi", X(31,470), XRT_MASK, PPC, 0, {RA0, RB}},
5753 {"nand", XRC(31,476,0), X_MASK, COM, 0, {RA, RS, RB}},
5754 {"nand.", XRC(31,476,1), X_MASK, COM, 0, {RA, RS, RB}},
5756 {"dsn", X(31,483), XRT_MASK, E500MC, 0, {RA, RB}},
5758 {"dcread", X(31,486), X_MASK, PPC403|PPC440, PPCA2|PPC476, {RT, RA0, RB}},
5760 {"icbtls", X(31,486), X_MASK, PPCCHLK|PPC476|TITAN, 0, {CT, RA0, RB}},
5762 {"stvxl", X(31,487), X_MASK, PPCVEC, 0, {VS, RA0, RB}},
5764 {"nabs", XO(31,488,0,0), XORB_MASK, M601, 0, {RT, RA}},
5765 {"nabs.", XO(31,488,0,1), XORB_MASK, M601, 0, {RT, RA}},
5767 {"divd", XO(31,489,0,0), XO_MASK, PPC64, 0, {RT, RA, RB}},
5768 {"divd.", XO(31,489,0,1), XO_MASK, PPC64, 0, {RT, RA, RB}},
5770 {"divw", XO(31,491,0,0), XO_MASK, PPC, 0, {RT, RA, RB}},
5771 {"divw.", XO(31,491,0,1), XO_MASK, PPC, 0, {RT, RA, RB}},
5773 {"icbtlse", X(31,494), X_MASK, PPCCHLK, E500MC, {CT, RA, RB}},
5775 {"slbia", X(31,498), 0xff1fffff, POWER6, 0, {IH}},
5776 {"slbia", X(31,498), 0xffffffff, PPC64, POWER6, {0}},
5778 {"cli", X(31,502), XRB_MASK, POWER, 0, {RT, RA}},
5780 {"popcntd", X(31,506), XRB_MASK, POWER7|PPCA2, 0, {RA, RS}},
5782 {"cmpb", X(31,508), X_MASK, POWER6|PPCA2|PPC476, 0, {RA, RS, RB}},
5784 {"mcrxr", X(31,512), XBFRARB_MASK, COM, POWER7, {BF}},
5786 {"lbdx", X(31,515), X_MASK, E500MC, 0, {RT, RA, RB}},
5788 {"bblels", X(31,518), X_MASK, PPCBRLK, 0, {0}},
5790 {"lvlx", X(31,519), X_MASK, CELL, 0, {VD, RA0, RB}},
5791 {"lbfcmux", APU(31,519,0), APU_MASK, PPC405, 0, {FCRT, RA, RB}},
5793 {"subfco", XO(31,8,1,0), XO_MASK, PPCCOM, 0, {RT, RA, RB}},
5794 {"sfo", XO(31,8,1,0), XO_MASK, PWRCOM, 0, {RT, RA, RB}},
5795 {"subco", XO(31,8,1,0), XO_MASK, PPCCOM, 0, {RT, RB, RA}},
5796 {"subfco.", XO(31,8,1,1), XO_MASK, PPCCOM, 0, {RT, RA, RB}},
5797 {"sfo.", XO(31,8,1,1), XO_MASK, PWRCOM, 0, {RT, RA, RB}},
5798 {"subco.", XO(31,8,1,1), XO_MASK, PPCCOM, 0, {RT, RB, RA}},
5800 {"addco", XO(31,10,1,0), XO_MASK, PPCCOM, 0, {RT, RA, RB}},
5801 {"ao", XO(31,10,1,0), XO_MASK, PWRCOM, 0, {RT, RA, RB}},
5802 {"addco.", XO(31,10,1,1), XO_MASK, PPCCOM, 0, {RT, RA, RB}},
5803 {"ao.", XO(31,10,1,1), XO_MASK, PWRCOM, 0, {RT, RA, RB}},
5805 {"lxsspx", X(31,524), XX1_MASK, PPCVSX2, 0, {XT6, RA0, RB}},
5807 {"clcs", X(31,531), XRB_MASK, M601, 0, {RT, RA}},
5809 {"ldbrx", X(31,532), X_MASK, CELL|POWER7|PPCA2, 0, {RT, RA0, RB}},
5811 {"lswx", X(31,533), X_MASK, PPCCOM, E500|E500MC, {RT, RAX, RBX}},
5812 {"lsx", X(31,533), X_MASK, PWRCOM, 0, {RT, RA, RB}},
5814 {"lwbrx", X(31,534), X_MASK, PPCCOM, 0, {RT, RA0, RB}},
5815 {"lbrx", X(31,534), X_MASK, PWRCOM, 0, {RT, RA, RB}},
5817 {"lfsx", X(31,535), X_MASK, COM, PPCEFS, {FRT, RA0, RB}},
5819 {"srw", XRC(31,536,0), X_MASK, PPCCOM, 0, {RA, RS, RB}},
5820 {"sr", XRC(31,536,0), X_MASK, PWRCOM, 0, {RA, RS, RB}},
5821 {"srw.", XRC(31,536,1), X_MASK, PPCCOM, 0, {RA, RS, RB}},
5822 {"sr.", XRC(31,536,1), X_MASK, PWRCOM, 0, {RA, RS, RB}},
5824 {"rrib", XRC(31,537,0), X_MASK, M601, 0, {RA, RS, RB}},
5825 {"rrib.", XRC(31,537,1), X_MASK, M601, 0, {RA, RS, RB}},
5827 {"cnttzw", XRC(31,538,0), XRB_MASK, POWER9, 0, {RA, RS}},
5828 {"cnttzw.", XRC(31,538,1), XRB_MASK, POWER9, 0, {RA, RS}},
5830 {"srd", XRC(31,539,0), X_MASK, PPC64, 0, {RA, RS, RB}},
5831 {"srd.", XRC(31,539,1), X_MASK, PPC64, 0, {RA, RS, RB}},
5833 {"maskir", XRC(31,541,0), X_MASK, M601, 0, {RA, RS, RB}},
5834 {"maskir.", XRC(31,541,1), X_MASK, M601, 0, {RA, RS, RB}},
5836 {"lhdx", X(31,547), X_MASK, E500MC, 0, {RT, RA, RB}},
5838 {"lvtrx", X(31,549), X_MASK, PPCVEC2, 0, {VD, RA0, RB}},
5840 {"bbelr", X(31,550), X_MASK, PPCBRLK, 0, {0}},
5842 {"lvrx", X(31,551), X_MASK, CELL, 0, {VD, RA0, RB}},
5843 {"lhfcmux", APU(31,551,0), APU_MASK, PPC405, 0, {FCRT, RA, RB}},
5845 {"subfo", XO(31,40,1,0), XO_MASK, PPC, 0, {RT, RA, RB}},
5846 {"subo", XO(31,40,1,0), XO_MASK, PPC, 0, {RT, RB, RA}},
5847 {"subfo.", XO(31,40,1,1), XO_MASK, PPC, 0, {RT, RA, RB}},
5848 {"subo.", XO(31,40,1,1), XO_MASK, PPC, 0, {RT, RB, RA}},
5850 {"tlbsync", X(31,566), 0xffffffff, PPC, 0, {0}},
5852 {"lfsux", X(31,567), X_MASK, COM, PPCEFS, {FRT, RAS, RB}},
5854 {"cnttzd", XRC(31,570,0), XRB_MASK, POWER9, 0, {RA, RS}},
5855 {"cnttzd.", XRC(31,570,1), XRB_MASK, POWER9, 0, {RA, RS}},
5857 {"mcrxrx", X(31,576), XBFRARB_MASK, POWER9, 0, {BF}},
5859 {"lwdx", X(31,579), X_MASK, E500MC, 0, {RT, RA, RB}},
5861 {"lvtlx", X(31,581), X_MASK, PPCVEC2, 0, {VD, RA0, RB}},
5863 {"lwat", X(31,582), X_MASK, POWER9, 0, {RT, RA0, FC}},
5865 {"lwfcmux", APU(31,583,0), APU_MASK, PPC405, 0, {FCRT, RA, RB}},
5867 {"lxsdx", X(31,588), XX1_MASK, PPCVSX, 0, {XT6, RA0, RB}},
5869 {"mfsr", X(31,595), XRB_MASK|(1<<20), COM, NON32, {RT, SR}},
5871 {"lswi", X(31,597), X_MASK, PPCCOM, E500|E500MC, {RT, RAX, NBI}},
5872 {"lsi", X(31,597), X_MASK, PWRCOM, 0, {RT, RA0, NB}},
5874 {"hwsync", XSYNC(31,598,0), 0xffffffff, POWER4, BOOKE|PPC476, {0}},
5875 {"lwsync", XSYNC(31,598,1), 0xffffffff, PPC, E500, {0}},
5876 {"ptesync", XSYNC(31,598,2), 0xffffffff, PPC64, 0, {0}},
5877 {"sync", X(31,598), XSYNCLE_MASK, POWER9|E6500, 0, {LS, ESYNC}},
5878 {"sync", X(31,598), XSYNC_MASK, PPCCOM, BOOKE|PPC476|POWER9, {LS}},
5879 {"msync", X(31,598), 0xffffffff, BOOKE|PPCA2|PPC476, 0, {0}},
5880 {"sync", X(31,598), 0xffffffff, BOOKE|PPC476, E6500, {0}},
5881 {"lwsync", X(31,598), 0xffffffff, E500, 0, {0}},
5882 {"dcs", X(31,598), 0xffffffff, PWRCOM, 0, {0}},
5884 {"lfdx", X(31,599), X_MASK, COM, PPCEFS, {FRT, RA0, RB}},
5886 {"mffgpr", XRC(31,607,0), XRA_MASK, POWER6, POWER7, {FRT, RB}},
5887 {"lfdepx", X(31,607), X_MASK, E500MC|PPCA2, 0, {FRT, RA0, RB}},
5889 {"lddx", X(31,611), X_MASK, E500MC, 0, {RT, RA, RB}},
5891 {"lvswx", X(31,613), X_MASK, PPCVEC2, 0, {VD, RA0, RB}},
5893 {"ldat", X(31,614), X_MASK, POWER9, 0, {RT, RA0, FC}},
5895 {"lqfcmux", APU(31,615,0), APU_MASK, PPC405, 0, {FCRT, RA, RB}},
5897 {"nego", XO(31,104,1,0), XORB_MASK, COM, 0, {RT, RA}},
5898 {"nego.", XO(31,104,1,1), XORB_MASK, COM, 0, {RT, RA}},
5900 {"mulo", XO(31,107,1,0), XO_MASK, M601, 0, {RT, RA, RB}},
5901 {"mulo.", XO(31,107,1,1), XO_MASK, M601, 0, {RT, RA, RB}},
5903 {"mfsri", X(31,627), X_MASK, M601, 0, {RT, RA, RB}},
5905 {"dclst", X(31,630), XRB_MASK, M601, 0, {RS, RA}},
5907 {"lfdux", X(31,631), X_MASK, COM, PPCEFS, {FRT, RAS, RB}},
5909 {"stbdx", X(31,643), X_MASK, E500MC, 0, {RS, RA, RB}},
5911 {"stvlx", X(31,647), X_MASK, CELL, 0, {VS, RA0, RB}},
5912 {"stbfcmux", APU(31,647,0), APU_MASK, PPC405, 0, {FCRT, RA, RB}},
5914 {"stxsspx", X(31,652), XX1_MASK, PPCVSX2, 0, {XS6, RA0, RB}},
5916 {"tbegin.", XRC(31,654,1), XRTLRARB_MASK, PPCHTM, 0, {HTM_R}},
5918 {"subfeo", XO(31,136,1,0), XO_MASK, PPCCOM, 0, {RT, RA, RB}},
5919 {"sfeo", XO(31,136,1,0), XO_MASK, PWRCOM, 0, {RT, RA, RB}},
5920 {"subfeo.", XO(31,136,1,1), XO_MASK, PPCCOM, 0, {RT, RA, RB}},
5921 {"sfeo.", XO(31,136,1,1), XO_MASK, PWRCOM, 0, {RT, RA, RB}},
5923 {"addeo", XO(31,138,1,0), XO_MASK, PPCCOM, 0, {RT, RA, RB}},
5924 {"aeo", XO(31,138,1,0), XO_MASK, PWRCOM, 0, {RT, RA, RB}},
5925 {"addeo.", XO(31,138,1,1), XO_MASK, PPCCOM, 0, {RT, RA, RB}},
5926 {"aeo.", XO(31,138,1,1), XO_MASK, PWRCOM, 0, {RT, RA, RB}},
5928 {"mfsrin", X(31,659), XRA_MASK, PPC, NON32, {RT, RB}},
5930 {"stdbrx", X(31,660), X_MASK, CELL|POWER7|PPCA2, 0, {RS, RA0, RB}},
5932 {"stswx", X(31,661), X_MASK, PPCCOM, E500|E500MC, {RS, RA0, RB}},
5933 {"stsx", X(31,661), X_MASK, PWRCOM, 0, {RS, RA0, RB}},
5935 {"stwbrx", X(31,662), X_MASK, PPCCOM, 0, {RS, RA0, RB}},
5936 {"stbrx", X(31,662), X_MASK, PWRCOM, 0, {RS, RA0, RB}},
5938 {"stfsx", X(31,663), X_MASK, COM, PPCEFS, {FRS, RA0, RB}},
5940 {"srq", XRC(31,664,0), X_MASK, M601, 0, {RA, RS, RB}},
5941 {"srq.", XRC(31,664,1), X_MASK, M601, 0, {RA, RS, RB}},
5943 {"sre", XRC(31,665,0), X_MASK, M601, 0, {RA, RS, RB}},
5944 {"sre.", XRC(31,665,1), X_MASK, M601, 0, {RA, RS, RB}},
5946 {"sthdx", X(31,675), X_MASK, E500MC, 0, {RS, RA, RB}},
5948 {"stvfrx", X(31,677), X_MASK, PPCVEC2, 0, {VS, RA0, RB}},
5950 {"stvrx", X(31,679), X_MASK, CELL, 0, {VS, RA0, RB}},
5951 {"sthfcmux", APU(31,679,0), APU_MASK, PPC405, 0, {FCRT, RA, RB}},
5953 {"tendall.", XRC(31,686,1)|(1<<25), XRTRARB_MASK, PPCHTM, 0, {0}},
5954 {"tend.", XRC(31,686,1), XRTARARB_MASK, PPCHTM, 0, {HTM_A}},
5956 {"stbcx.", XRC(31,694,1), X_MASK, POWER8|E6500, 0, {RS, RA0, RB}},
5958 {"stfsux", X(31,695), X_MASK, COM, PPCEFS, {FRS, RAS, RB}},
5960 {"sriq", XRC(31,696,0), X_MASK, M601, 0, {RA, RS, SH}},
5961 {"sriq.", XRC(31,696,1), X_MASK, M601, 0, {RA, RS, SH}},
5963 {"stwdx", X(31,707), X_MASK, E500MC, 0, {RS, RA, RB}},
5965 {"stvflx", X(31,709), X_MASK, PPCVEC2, 0, {VS, RA0, RB}},
5967 {"stwat", X(31,710), X_MASK, POWER9, 0, {RS, RA0, FC}},
5969 {"stwfcmux", APU(31,711,0), APU_MASK, PPC405, 0, {FCRT, RA, RB}},
5971 {"stxsdx", X(31,716), XX1_MASK, PPCVSX, 0, {XS6, RA0, RB}},
5973 {"tcheck", X(31,718), XRTBFRARB_MASK, PPCHTM, 0, {BF}},
5975 {"subfzeo", XO(31,200,1,0), XORB_MASK, PPCCOM, 0, {RT, RA}},
5976 {"sfzeo", XO(31,200,1,0), XORB_MASK, PWRCOM, 0, {RT, RA}},
5977 {"subfzeo.", XO(31,200,1,1), XORB_MASK, PPCCOM, 0, {RT, RA}},
5978 {"sfzeo.", XO(31,200,1,1), XORB_MASK, PWRCOM, 0, {RT, RA}},
5980 {"addzeo", XO(31,202,1,0), XORB_MASK, PPCCOM, 0, {RT, RA}},
5981 {"azeo", XO(31,202,1,0), XORB_MASK, PWRCOM, 0, {RT, RA}},
5982 {"addzeo.", XO(31,202,1,1), XORB_MASK, PPCCOM, 0, {RT, RA}},
5983 {"azeo.", XO(31,202,1,1), XORB_MASK, PWRCOM, 0, {RT, RA}},
5985 {"stswi", X(31,725), X_MASK, PPCCOM, E500|E500MC, {RS, RA0, NB}},
5986 {"stsi", X(31,725), X_MASK, PWRCOM, 0, {RS, RA0, NB}},
5988 {"sthcx.", XRC(31,726,1), X_MASK, POWER8|E6500, 0, {RS, RA0, RB}},
5990 {"stfdx", X(31,727), X_MASK, COM, PPCEFS, {FRS, RA0, RB}},
5992 {"srlq", XRC(31,728,0), X_MASK, M601, 0, {RA, RS, RB}},
5993 {"srlq.", XRC(31,728,1), X_MASK, M601, 0, {RA, RS, RB}},
5995 {"sreq", XRC(31,729,0), X_MASK, M601, 0, {RA, RS, RB}},
5996 {"sreq.", XRC(31,729,1), X_MASK, M601, 0, {RA, RS, RB}},
5998 {"mftgpr", XRC(31,735,0), XRA_MASK, POWER6, POWER7, {RT, FRB}},
5999 {"stfdepx", X(31,735), X_MASK, E500MC|PPCA2, 0, {FRS, RA0, RB}},
6001 {"stddx", X(31,739), X_MASK, E500MC, 0, {RS, RA, RB}},
6003 {"stvswx", X(31,741), X_MASK, PPCVEC2, 0, {VS, RA0, RB}},
6005 {"stdat", X(31,742), X_MASK, POWER9, 0, {RS, RA0, FC}},
6007 {"stqfcmux", APU(31,743,0), APU_MASK, PPC405, 0, {FCRT, RA, RB}},
6009 {"subfmeo", XO(31,232,1,0), XORB_MASK, PPCCOM, 0, {RT, RA}},
6010 {"sfmeo", XO(31,232,1,0), XORB_MASK, PWRCOM, 0, {RT, RA}},
6011 {"subfmeo.", XO(31,232,1,1), XORB_MASK, PPCCOM, 0, {RT, RA}},
6012 {"sfmeo.", XO(31,232,1,1), XORB_MASK, PWRCOM, 0, {RT, RA}},
6014 {"mulldo", XO(31,233,1,0), XO_MASK, PPC64, 0, {RT, RA, RB}},
6015 {"mulldo.", XO(31,233,1,1), XO_MASK, PPC64, 0, {RT, RA, RB}},
6017 {"addmeo", XO(31,234,1,0), XORB_MASK, PPCCOM, 0, {RT, RA}},
6018 {"ameo", XO(31,234,1,0), XORB_MASK, PWRCOM, 0, {RT, RA}},
6019 {"addmeo.", XO(31,234,1,1), XORB_MASK, PPCCOM, 0, {RT, RA}},
6020 {"ameo.", XO(31,234,1,1), XORB_MASK, PWRCOM, 0, {RT, RA}},
6022 {"mullwo", XO(31,235,1,0), XO_MASK, PPCCOM, 0, {RT, RA, RB}},
6023 {"mulso", XO(31,235,1,0), XO_MASK, PWRCOM, 0, {RT, RA, RB}},
6024 {"mullwo.", XO(31,235,1,1), XO_MASK, PPCCOM, 0, {RT, RA, RB}},
6025 {"mulso.", XO(31,235,1,1), XO_MASK, PWRCOM, 0, {RT, RA, RB}},
6027 {"tsuspend.", XRCL(31,750,0,1), XRTRARB_MASK,PPCHTM, 0, {0}},
6028 {"tresume.", XRCL(31,750,1,1), XRTRARB_MASK,PPCHTM, 0, {0}},
6029 {"tsr.", XRC(31,750,1), XRTLRARB_MASK,PPCHTM, 0, {L}},
6031 {"darn", X(31,755), XLRAND_MASK, POWER9, 0, {RT, LRAND}},
6033 {"dcba", X(31,758), XRT_MASK, PPC405|PPC7450|BOOKE|PPCA2|PPC476, 0, {RA0, RB}},
6034 {"dcbal", XOPL(31,758,1), XRT_MASK, E500MC, 0, {RA0, RB}},
6036 {"stfdux", X(31,759), X_MASK, COM, PPCEFS, {FRS, RAS, RB}},
6038 {"srliq", XRC(31,760,0), X_MASK, M601, 0, {RA, RS, SH}},
6039 {"srliq.", XRC(31,760,1), X_MASK, M601, 0, {RA, RS, SH}},
6041 {"lvsm", X(31,773), X_MASK, PPCVEC2, 0, {VD, RA0, RB}},
6043 {"copy_first", XOPL(31,774,1), XRT_MASK, POWER9, 0, {RA0, RB}},
6044 {"copy", X(31,774), XLRT_MASK, POWER9, 0, {RA0, RB, L}},
6046 {"stvepxl", X(31,775), X_MASK, PPCVEC2, 0, {VS, RA0, RB}},
6047 {"lvlxl", X(31,775), X_MASK, CELL, 0, {VD, RA0, RB}},
6048 {"ldfcmux", APU(31,775,0), APU_MASK, PPC405, 0, {FCRT, RA, RB}},
6050 {"dozo", XO(31,264,1,0), XO_MASK, M601, 0, {RT, RA, RB}},
6051 {"dozo.", XO(31,264,1,1), XO_MASK, M601, 0, {RT, RA, RB}},
6053 {"addo", XO(31,266,1,0), XO_MASK, PPCCOM, 0, {RT, RA, RB}},
6054 {"caxo", XO(31,266,1,0), XO_MASK, PWRCOM, 0, {RT, RA, RB}},
6055 {"addo.", XO(31,266,1,1), XO_MASK, PPCCOM, 0, {RT, RA, RB}},
6056 {"caxo.", XO(31,266,1,1), XO_MASK, PWRCOM, 0, {RT, RA, RB}},
6058 {"modsd", X(31,777), X_MASK, POWER9, 0, {RT, RA, RB}},
6059 {"modsw", X(31,779), X_MASK, POWER9, 0, {RT, RA, RB}},
6061 {"lxvw4x", X(31,780), XX1_MASK, PPCVSX, 0, {XT6, RA0, RB}},
6062 {"lxsibzx", X(31,781), XX1_MASK, PPCVSX3, 0, {XT6, RA0, RB}},
6064 {"tabortwc.", XRC(31,782,1), X_MASK, PPCHTM, 0, {TO, RA, RB}},
6066 {"tlbivax", X(31,786), XRT_MASK, BOOKE|PPCA2|PPC476, 0, {RA0, RB}},
6068 {"lwzcix", X(31,789), X_MASK, POWER6, 0, {RT, RA0, RB}},
6070 {"lhbrx", X(31,790), X_MASK, COM, 0, {RT, RA0, RB}},
6072 {"lfdpx", X(31,791), X_MASK, POWER6, POWER7, {FRTp, RA0, RB}},
6073 {"lfqx", X(31,791), X_MASK, POWER2, 0, {FRT, RA, RB}},
6075 {"sraw", XRC(31,792,0), X_MASK, PPCCOM, 0, {RA, RS, RB}},
6076 {"sra", XRC(31,792,0), X_MASK, PWRCOM, 0, {RA, RS, RB}},
6077 {"sraw.", XRC(31,792,1), X_MASK, PPCCOM, 0, {RA, RS, RB}},
6078 {"sra.", XRC(31,792,1), X_MASK, PWRCOM, 0, {RA, RS, RB}},
6080 {"srad", XRC(31,794,0), X_MASK, PPC64, 0, {RA, RS, RB}},
6081 {"srad.", XRC(31,794,1), X_MASK, PPC64, 0, {RA, RS, RB}},
6083 {"lfddx", X(31,803), X_MASK, E500MC, 0, {FRT, RA, RB}},
6085 {"lvtrxl", X(31,805), X_MASK, PPCVEC2, 0, {VD, RA0, RB}},
6086 {"stvepx", X(31,807), X_MASK, PPCVEC2, 0, {VS, RA0, RB}},
6087 {"lvrxl", X(31,807), X_MASK, CELL, 0, {VD, RA0, RB}},
6089 {"lxvh8x", X(31,812), XX1_MASK, PPCVSX3, 0, {XT6, RA0, RB}},
6090 {"lxsihzx", X(31,813), XX1_MASK, PPCVSX3, 0, {XT6, RA0, RB}},
6092 {"tabortdc.", XRC(31,814,1), X_MASK, PPCHTM, 0, {TO, RA, RB}},
6094 {"rac", X(31,818), X_MASK, M601, 0, {RT, RA, RB}},
6096 {"erativax", X(31,819), X_MASK, PPCA2, 0, {RS, RA0, RB}},
6098 {"lhzcix", X(31,821), X_MASK, POWER6, 0, {RT, RA0, RB}},
6100 {"dss", XDSS(31,822,0), XDSS_MASK, PPCVEC, 0, {STRM}},
6102 {"lfqux", X(31,823), X_MASK, POWER2, 0, {FRT, RA, RB}},
6104 {"srawi", XRC(31,824,0), X_MASK, PPCCOM, 0, {RA, RS, SH}},
6105 {"srai", XRC(31,824,0), X_MASK, PWRCOM, 0, {RA, RS, SH}},
6106 {"srawi.", XRC(31,824,1), X_MASK, PPCCOM, 0, {RA, RS, SH}},
6107 {"srai.", XRC(31,824,1), X_MASK, PWRCOM, 0, {RA, RS, SH}},
6109 {"sradi", XS(31,413,0), XS_MASK, PPC64, 0, {RA, RS, SH6}},
6110 {"sradi.", XS(31,413,1), XS_MASK, PPC64, 0, {RA, RS, SH6}},
6112 {"lvtlxl", X(31,837), X_MASK, PPCVEC2, 0, {VD, RA0, RB}},
6114 {"cp_abort", X(31,838), XRTRARB_MASK,POWER9, 0, {0}},
6116 {"divo", XO(31,331,1,0), XO_MASK, M601, 0, {RT, RA, RB}},
6117 {"divo.", XO(31,331,1,1), XO_MASK, M601, 0, {RT, RA, RB}},
6119 {"lxvd2x", X(31,844), XX1_MASK, PPCVSX, 0, {XT6, RA0, RB}},
6120 {"lxvx", X(31,844), XX1_MASK, POWER8, POWER9|PPCVSX3, {XT6, RA0, RB}},
6122 {"tabortwci.", XRC(31,846,1), X_MASK, PPCHTM, 0, {TO, RA, HTM_SI}},
6124 {"tlbsrx.", XRC(31,850,1), XRT_MASK, PPCA2, 0, {RA0, RB}},
6126 {"slbmfev", X(31,851), XRLA_MASK, POWER9, 0, {RT, RB, A_L}},
6127 {"slbmfev", X(31,851), XRA_MASK, PPC64, POWER9, {RT, RB}},
6129 {"lbzcix", X(31,853), X_MASK, POWER6, 0, {RT, RA0, RB}},
6131 {"eieio", X(31,854), 0xffffffff, PPC, BOOKE|PPCA2|PPC476, {0}},
6132 {"mbar", X(31,854), X_MASK, BOOKE|PPCA2|PPC476, 0, {MO}},
6133 {"eieio", XMBAR(31,854,1),0xffffffff, E500, 0, {0}},
6134 {"eieio", X(31,854), 0xffffffff, PPCA2|PPC476, 0, {0}},
6136 {"lfiwax", X(31,855), X_MASK, POWER6|PPCA2|PPC476, 0, {FRT, RA0, RB}},
6138 {"lvswxl", X(31,869), X_MASK, PPCVEC2, 0, {VD, RA0, RB}},
6140 {"abso", XO(31,360,1,0), XORB_MASK, M601, 0, {RT, RA}},
6141 {"abso.", XO(31,360,1,1), XORB_MASK, M601, 0, {RT, RA}},
6143 {"divso", XO(31,363,1,0), XO_MASK, M601, 0, {RT, RA, RB}},
6144 {"divso.", XO(31,363,1,1), XO_MASK, M601, 0, {RT, RA, RB}},
6146 {"lxvb16x", X(31,876), XX1_MASK, PPCVSX3, 0, {XT6, RA0, RB}},
6148 {"tabortdci.", XRC(31,878,1), X_MASK, PPCHTM, 0, {TO, RA, HTM_SI}},
6150 {"rmieg", X(31,882), XRTRA_MASK, POWER9, 0, {RB}},
6152 {"ldcix", X(31,885), X_MASK, POWER6, 0, {RT, RA0, RB}},
6154 {"msgsync", X(31,886), 0xffffffff, POWER9, 0, {0}},
6156 {"lfiwzx", X(31,887), X_MASK, POWER7|PPCA2, 0, {FRT, RA0, RB}},
6158 {"extswsli", XS(31,445,0), XS_MASK, POWER9, 0, {RA, RS, SH6}},
6159 {"extswsli.", XS(31,445,1), XS_MASK, POWER9, 0, {RA, RS, SH6}},
6161 {"paste", XRC(31,902,0), XLRT_MASK, POWER9, 0, {RA0, RB, L0}},
6162 {"paste_last", XRCL(31,902,1,1),XRT_MASK, POWER9, 0, {RA0, RB}},
6163 {"paste.", XRC(31,902,1), XLRT_MASK, POWER9, 0, {RA0, RB, L1}},
6165 {"stvlxl", X(31,903), X_MASK, CELL, 0, {VS, RA0, RB}},
6166 {"stdfcmux", APU(31,903,0), APU_MASK, PPC405, 0, {FCRT, RA, RB}},
6168 {"divdeuo", XO(31,393,1,0), XO_MASK, POWER7|PPCA2, 0, {RT, RA, RB}},
6169 {"divdeuo.", XO(31,393,1,1), XO_MASK, POWER7|PPCA2, 0, {RT, RA, RB}},
6170 {"divweuo", XO(31,395,1,0), XO_MASK, POWER7|PPCA2, 0, {RT, RA, RB}},
6171 {"divweuo.", XO(31,395,1,1), XO_MASK, POWER7|PPCA2, 0, {RT, RA, RB}},
6173 {"stxvw4x", X(31,908), XX1_MASK, PPCVSX, 0, {XS6, RA0, RB}},
6174 {"stxsibx", X(31,909), XX1_MASK, PPCVSX3, 0, {XS6, RA0, RB}},
6176 {"tabort.", XRC(31,910,1), XRTRB_MASK, PPCHTM, 0, {RA}},
6178 {"tlbsx", XRC(31,914,0), X_MASK, PPC403|BOOKE|PPCA2|PPC476, 0, {RTO, RA0, RB}},
6179 {"tlbsx.", XRC(31,914,1), X_MASK, PPC403|BOOKE|PPCA2|PPC476, 0, {RTO, RA0, RB}},
6181 {"slbmfee", X(31,915), XRLA_MASK, POWER9, 0, {RT, RB, A_L}},
6182 {"slbmfee", X(31,915), XRA_MASK, PPC64, POWER9, {RT, RB}},
6184 {"stwcix", X(31,917), X_MASK, POWER6, 0, {RS, RA0, RB}},
6186 {"sthbrx", X(31,918), X_MASK, COM, 0, {RS, RA0, RB}},
6188 {"stfdpx", X(31,919), X_MASK, POWER6, POWER7, {FRSp, RA0, RB}},
6189 {"stfqx", X(31,919), X_MASK, POWER2, 0, {FRS, RA0, RB}},
6191 {"sraq", XRC(31,920,0), X_MASK, M601, 0, {RA, RS, RB}},
6192 {"sraq.", XRC(31,920,1), X_MASK, M601, 0, {RA, RS, RB}},
6194 {"srea", XRC(31,921,0), X_MASK, M601, 0, {RA, RS, RB}},
6195 {"srea.", XRC(31,921,1), X_MASK, M601, 0, {RA, RS, RB}},
6197 {"extsh", XRC(31,922,0), XRB_MASK, PPCCOM, 0, {RA, RS}},
6198 {"exts", XRC(31,922,0), XRB_MASK, PWRCOM, 0, {RA, RS}},
6199 {"extsh.", XRC(31,922,1), XRB_MASK, PPCCOM, 0, {RA, RS}},
6200 {"exts.", XRC(31,922,1), XRB_MASK, PWRCOM, 0, {RA, RS}},
6202 {"stfddx", X(31,931), X_MASK, E500MC, 0, {FRS, RA, RB}},
6204 {"stvfrxl", X(31,933), X_MASK, PPCVEC2, 0, {VS, RA0, RB}},
6206 {"wclrone", XOPL2(31,934,2),XRT_MASK, PPCA2, 0, {RA0, RB}},
6207 {"wclrall", X(31,934), XRARB_MASK, PPCA2, 0, {L}},
6208 {"wclr", X(31,934), X_MASK, PPCA2, 0, {L, RA0, RB}},
6210 {"stvrxl", X(31,935), X_MASK, CELL, 0, {VS, RA0, RB}},
6212 {"divdeo", XO(31,425,1,0), XO_MASK, POWER7|PPCA2, 0, {RT, RA, RB}},
6213 {"divdeo.", XO(31,425,1,1), XO_MASK, POWER7|PPCA2, 0, {RT, RA, RB}},
6214 {"divweo", XO(31,427,1,0), XO_MASK, POWER7|PPCA2, 0, {RT, RA, RB}},
6215 {"divweo.", XO(31,427,1,1), XO_MASK, POWER7|PPCA2, 0, {RT, RA, RB}},
6217 {"stxvh8x", X(31,940), XX1_MASK, PPCVSX3, 0, {XS6, RA0, RB}},
6218 {"stxsihx", X(31,941), XX1_MASK, PPCVSX3, 0, {XS6, RA0, RB}},
6220 {"treclaim.", XRC(31,942,1), XRTRB_MASK, PPCHTM, 0, {RA}},
6222 {"tlbrehi", XTLB(31,946,0), XTLB_MASK, PPC403, PPCA2, {RT, RA}},
6223 {"tlbrelo", XTLB(31,946,1), XTLB_MASK, PPC403, PPCA2, {RT, RA}},
6224 {"tlbre", X(31,946), X_MASK, PPC403|BOOKE|PPCA2|PPC476, 0, {RSO, RAOPT, SHO}},
6226 {"sthcix", X(31,949), X_MASK, POWER6, 0, {RS, RA0, RB}},
6228 {"icswepx", XRC(31,950,0), X_MASK, PPCA2, 0, {RS, RA, RB}},
6229 {"icswepx.", XRC(31,950,1), X_MASK, PPCA2, 0, {RS, RA, RB}},
6231 {"stfqux", X(31,951), X_MASK, POWER2, 0, {FRS, RA, RB}},
6233 {"sraiq", XRC(31,952,0), X_MASK, M601, 0, {RA, RS, SH}},
6234 {"sraiq.", XRC(31,952,1), X_MASK, M601, 0, {RA, RS, SH}},
6236 {"extsb", XRC(31,954,0), XRB_MASK, PPC, 0, {RA, RS}},
6237 {"extsb.", XRC(31,954,1), XRB_MASK, PPC, 0, {RA, RS}},
6239 {"stvflxl", X(31,965), X_MASK, PPCVEC2, 0, {VS, RA0, RB}},
6241 {"iccci", X(31,966), XRT_MASK, PPC403|PPC440|TITAN|PPCA2, 0, {RAOPT, RBOPT}},
6242 {"ici", X(31,966), XRARB_MASK, PPCA2|PPC476, 0, {CT}},
6244 {"divduo", XO(31,457,1,0), XO_MASK, PPC64, 0, {RT, RA, RB}},
6245 {"divduo.", XO(31,457,1,1), XO_MASK, PPC64, 0, {RT, RA, RB}},
6247 {"divwuo", XO(31,459,1,0), XO_MASK, PPC, 0, {RT, RA, RB}},
6248 {"divwuo.", XO(31,459,1,1), XO_MASK, PPC, 0, {RT, RA, RB}},
6250 {"stxvd2x", X(31,972), XX1_MASK, PPCVSX, 0, {XS6, RA0, RB}},
6251 {"stxvx", X(31,972), XX1_MASK, POWER8, POWER9|PPCVSX3, {XS6, RA0, RB}},
6253 {"tlbld", X(31,978), XRTRA_MASK, PPC, PPC403|BOOKE|PPCA2|PPC476, {RB}},
6254 {"tlbwehi", XTLB(31,978,0), XTLB_MASK, PPC403, 0, {RT, RA}},
6255 {"tlbwelo", XTLB(31,978,1), XTLB_MASK, PPC403, 0, {RT, RA}},
6256 {"tlbwe", X(31,978), X_MASK, PPC403|BOOKE|PPCA2|PPC476, 0, {RSO, RAOPT, SHO}},
6258 {"slbfee.", XRC(31,979,1), XRA_MASK, POWER6, 0, {RT, RB}},
6260 {"stbcix", X(31,981), X_MASK, POWER6, 0, {RS, RA0, RB}},
6262 {"icbi", X(31,982), XRT_MASK, PPC, 0, {RA0, RB}},
6264 {"stfiwx", X(31,983), X_MASK, PPC, PPCEFS, {FRS, RA0, RB}},
6266 {"extsw", XRC(31,986,0), XRB_MASK, PPC64, 0, {RA, RS}},
6267 {"extsw.", XRC(31,986,1), XRB_MASK, PPC64, 0, {RA, RS}},
6269 {"icbiep", XRT(31,991,0), XRT_MASK, E500MC|PPCA2, 0, {RA0, RB}},
6271 {"stvswxl", X(31,997), X_MASK, PPCVEC2, 0, {VS, RA0, RB}},
6273 {"icread", X(31,998), XRT_MASK, PPC403|PPC440|PPC476|TITAN, 0, {RA0, RB}},
6275 {"nabso", XO(31,488,1,0), XORB_MASK, M601, 0, {RT, RA}},
6276 {"nabso.", XO(31,488,1,1), XORB_MASK, M601, 0, {RT, RA}},
6278 {"divdo", XO(31,489,1,0), XO_MASK, PPC64, 0, {RT, RA, RB}},
6279 {"divdo.", XO(31,489,1,1), XO_MASK, PPC64, 0, {RT, RA, RB}},
6281 {"divwo", XO(31,491,1,0), XO_MASK, PPC, 0, {RT, RA, RB}},
6282 {"divwo.", XO(31,491,1,1), XO_MASK, PPC, 0, {RT, RA, RB}},
6284 {"stxvb16x", X(31,1004), XX1_MASK, PPCVSX3, 0, {XS6, RA0, RB}},
6286 {"trechkpt.", XRC(31,1006,1), XRTRARB_MASK,PPCHTM, 0, {0}},
6288 {"tlbli", X(31,1010), XRTRA_MASK, PPC, TITAN, {RB}},
6290 {"stdcix", X(31,1013), X_MASK, POWER6, 0, {RS, RA0, RB}},
6292 {"dcbz", X(31,1014), XRT_MASK, PPC, 0, {RA0, RB}},
6293 {"dclz", X(31,1014), XRT_MASK, PPC, 0, {RA0, RB}},
6295 {"dcbzep", XRT(31,1023,0), XRT_MASK, E500MC|PPCA2, 0, {RA0, RB}},
6297 {"dcbzl", XOPL(31,1014,1), XRT_MASK, POWER4|E500MC, PPC476, {RA0, RB}},
6299 {"cctpl", 0x7c210b78, 0xffffffff, CELL, 0, {0}},
6300 {"cctpm", 0x7c421378, 0xffffffff, CELL, 0, {0}},
6301 {"cctph", 0x7c631b78, 0xffffffff, CELL, 0, {0}},
6303 {"dstt", XDSS(31,342,1), XDSS_MASK, PPCVEC, 0, {RA, RB, STRM}},
6304 {"dststt", XDSS(31,374,1), XDSS_MASK, PPCVEC, 0, {RA, RB, STRM}},
6305 {"dssall", XDSS(31,822,1), XDSS_MASK, PPCVEC, 0, {0}},
6307 {"db8cyc", 0x7f9ce378, 0xffffffff, CELL, 0, {0}},
6308 {"db10cyc", 0x7fbdeb78, 0xffffffff, CELL, 0, {0}},
6309 {"db12cyc", 0x7fdef378, 0xffffffff, CELL, 0, {0}},
6310 {"db16cyc", 0x7ffffb78, 0xffffffff, CELL, 0, {0}},
6312 {"lwz", OP(32), OP_MASK, PPCCOM, PPCVLE, {RT, D, RA0}},
6313 {"l", OP(32), OP_MASK, PWRCOM, PPCVLE, {RT, D, RA0}},
6315 {"lwzu", OP(33), OP_MASK, PPCCOM, PPCVLE, {RT, D, RAL}},
6316 {"lu", OP(33), OP_MASK, PWRCOM, PPCVLE, {RT, D, RA0}},
6318 {"lbz", OP(34), OP_MASK, COM, PPCVLE, {RT, D, RA0}},
6320 {"lbzu", OP(35), OP_MASK, COM, PPCVLE, {RT, D, RAL}},
6322 {"stw", OP(36), OP_MASK, PPCCOM, PPCVLE, {RS, D, RA0}},
6323 {"st", OP(36), OP_MASK, PWRCOM, PPCVLE, {RS, D, RA0}},
6325 {"stwu", OP(37), OP_MASK, PPCCOM, PPCVLE, {RS, D, RAS}},
6326 {"stu", OP(37), OP_MASK, PWRCOM, PPCVLE, {RS, D, RA0}},
6328 {"stb", OP(38), OP_MASK, COM, PPCVLE, {RS, D, RA0}},
6330 {"stbu", OP(39), OP_MASK, COM, PPCVLE, {RS, D, RAS}},
6332 {"lhz", OP(40), OP_MASK, COM, PPCVLE, {RT, D, RA0}},
6334 {"lhzu", OP(41), OP_MASK, COM, PPCVLE, {RT, D, RAL}},
6336 {"lha", OP(42), OP_MASK, COM, PPCVLE, {RT, D, RA0}},
6338 {"lhau", OP(43), OP_MASK, COM, PPCVLE, {RT, D, RAL}},
6340 {"sth", OP(44), OP_MASK, COM, PPCVLE, {RS, D, RA0}},
6342 {"sthu", OP(45), OP_MASK, COM, PPCVLE, {RS, D, RAS}},
6344 {"lmw", OP(46), OP_MASK, PPCCOM, PPCVLE, {RT, D, RAM}},
6345 {"lm", OP(46), OP_MASK, PWRCOM, PPCVLE, {RT, D, RA0}},
6347 {"stmw", OP(47), OP_MASK, PPCCOM, PPCVLE, {RS, D, RA0}},
6348 {"stm", OP(47), OP_MASK, PWRCOM, PPCVLE, {RS, D, RA0}},
6350 {"lfs", OP(48), OP_MASK, COM, PPCEFS|PPCVLE, {FRT, D, RA0}},
6352 {"lfsu", OP(49), OP_MASK, COM, PPCEFS|PPCVLE, {FRT, D, RAS}},
6354 {"lfd", OP(50), OP_MASK, COM, PPCEFS|PPCVLE, {FRT, D, RA0}},
6356 {"lfdu", OP(51), OP_MASK, COM, PPCEFS|PPCVLE, {FRT, D, RAS}},
6358 {"stfs", OP(52), OP_MASK, COM, PPCEFS|PPCVLE, {FRS, D, RA0}},
6360 {"stfsu", OP(53), OP_MASK, COM, PPCEFS|PPCVLE, {FRS, D, RAS}},
6362 {"stfd", OP(54), OP_MASK, COM, PPCEFS|PPCVLE, {FRS, D, RA0}},
6364 {"stfdu", OP(55), OP_MASK, COM, PPCEFS|PPCVLE, {FRS, D, RAS}},
6366 {"lq", OP(56), OP_MASK, POWER4, PPC476|PPCVLE, {RTQ, DQ, RAQ}},
6367 {"psq_l", OP(56), OP_MASK, PPCPS, PPCVLE, {FRT,PSD,RA,PSW,PSQ}},
6368 {"lfq", OP(56), OP_MASK, POWER2, PPCVLE, {FRT, D, RA0}},
6370 {"lxsd", DSO(57,2), DS_MASK, PPCVSX3, PPCVLE, {VD, DS, RA0}},
6371 {"lxssp", DSO(57,3), DS_MASK, PPCVSX3, PPCVLE, {VD, DS, RA0}},
6372 {"lfdp", OP(57), OP_MASK, POWER6, POWER7|PPCVLE, {FRTp, DS, RA0}},
6373 {"psq_lu", OP(57), OP_MASK, PPCPS, PPCVLE, {FRT,PSD,RA,PSW,PSQ}},
6374 {"lfqu", OP(57), OP_MASK, POWER2, PPCVLE, {FRT, D, RA0}},
6376 {"ld", DSO(58,0), DS_MASK, PPC64, PPCVLE, {RT, DS, RA0}},
6377 {"ldu", DSO(58,1), DS_MASK, PPC64, PPCVLE, {RT, DS, RAL}},
6378 {"lwa", DSO(58,2), DS_MASK, PPC64, PPCVLE, {RT, DS, RA0}},
6380 {"dadd", XRC(59,2,0), X_MASK, POWER6, PPCVLE, {FRT, FRA, FRB}},
6381 {"dadd.", XRC(59,2,1), X_MASK, POWER6, PPCVLE, {FRT, FRA, FRB}},
6383 {"dqua", ZRC(59,3,0), Z2_MASK, POWER6, PPCVLE, {FRT,FRA,FRB,RMC}},
6384 {"dqua.", ZRC(59,3,1), Z2_MASK, POWER6, PPCVLE, {FRT,FRA,FRB,RMC}},
6386 {"fdivs", A(59,18,0), AFRC_MASK, PPC, PPCEFS|PPCVLE, {FRT, FRA, FRB}},
6387 {"fdivs.", A(59,18,1), AFRC_MASK, PPC, PPCEFS|PPCVLE, {FRT, FRA, FRB}},
6389 {"fsubs", A(59,20,0), AFRC_MASK, PPC, PPCEFS|PPCVLE, {FRT, FRA, FRB}},
6390 {"fsubs.", A(59,20,1), AFRC_MASK, PPC, PPCEFS|PPCVLE, {FRT, FRA, FRB}},
6392 {"fadds", A(59,21,0), AFRC_MASK, PPC, PPCEFS|PPCVLE, {FRT, FRA, FRB}},
6393 {"fadds.", A(59,21,1), AFRC_MASK, PPC, PPCEFS|PPCVLE, {FRT, FRA, FRB}},
6395 {"fsqrts", A(59,22,0), AFRAFRC_MASK, PPC, TITAN|PPCVLE, {FRT, FRB}},
6396 {"fsqrts.", A(59,22,1), AFRAFRC_MASK, PPC, TITAN|PPCVLE, {FRT, FRB}},
6398 {"fres", A(59,24,0), AFRAFRC_MASK, POWER7, PPCVLE, {FRT, FRB}},
6399 {"fres", A(59,24,0), AFRALFRC_MASK, PPC, POWER7|PPCVLE, {FRT, FRB, A_L}},
6400 {"fres.", A(59,24,1), AFRAFRC_MASK, POWER7, PPCVLE, {FRT, FRB}},
6401 {"fres.", A(59,24,1), AFRALFRC_MASK, PPC, POWER7|PPCVLE, {FRT, FRB, A_L}},
6403 {"fmuls", A(59,25,0), AFRB_MASK, PPC, PPCEFS|PPCVLE, {FRT, FRA, FRC}},
6404 {"fmuls.", A(59,25,1), AFRB_MASK, PPC, PPCEFS|PPCVLE, {FRT, FRA, FRC}},
6406 {"frsqrtes", A(59,26,0), AFRAFRC_MASK, POWER7, PPCVLE, {FRT, FRB}},
6407 {"frsqrtes", A(59,26,0), AFRALFRC_MASK, POWER5, POWER7|PPCVLE, {FRT, FRB, A_L}},
6408 {"frsqrtes.", A(59,26,1), AFRAFRC_MASK, POWER7, PPCVLE, {FRT, FRB}},
6409 {"frsqrtes.", A(59,26,1), AFRALFRC_MASK, POWER5, POWER7|PPCVLE, {FRT, FRB, A_L}},
6411 {"fmsubs", A(59,28,0), A_MASK, PPC, PPCEFS|PPCVLE, {FRT, FRA, FRC, FRB}},
6412 {"fmsubs.", A(59,28,1), A_MASK, PPC, PPCEFS|PPCVLE, {FRT, FRA, FRC, FRB}},
6414 {"fmadds", A(59,29,0), A_MASK, PPC, PPCEFS|PPCVLE, {FRT, FRA, FRC, FRB}},
6415 {"fmadds.", A(59,29,1), A_MASK, PPC, PPCEFS|PPCVLE, {FRT, FRA, FRC, FRB}},
6417 {"fnmsubs", A(59,30,0), A_MASK, PPC, PPCEFS|PPCVLE, {FRT, FRA, FRC, FRB}},
6418 {"fnmsubs.", A(59,30,1), A_MASK, PPC, PPCEFS|PPCVLE, {FRT, FRA, FRC, FRB}},
6420 {"fnmadds", A(59,31,0), A_MASK, PPC, PPCEFS|PPCVLE, {FRT, FRA, FRC, FRB}},
6421 {"fnmadds.", A(59,31,1), A_MASK, PPC, PPCEFS|PPCVLE, {FRT, FRA, FRC, FRB}},
6423 {"dmul", XRC(59,34,0), X_MASK, POWER6, PPCVLE, {FRT, FRA, FRB}},
6424 {"dmul.", XRC(59,34,1), X_MASK, POWER6, PPCVLE, {FRT, FRA, FRB}},
6426 {"drrnd", ZRC(59,35,0), Z2_MASK, POWER6, PPCVLE, {FRT, FRA, FRB, RMC}},
6427 {"drrnd.", ZRC(59,35,1), Z2_MASK, POWER6, PPCVLE, {FRT, FRA, FRB, RMC}},
6429 {"dscli", ZRC(59,66,0), Z_MASK, POWER6, PPCVLE, {FRT, FRA, SH16}},
6430 {"dscli.", ZRC(59,66,1), Z_MASK, POWER6, PPCVLE, {FRT, FRA, SH16}},
6432 {"dquai", ZRC(59,67,0), Z2_MASK, POWER6, PPCVLE, {TE, FRT,FRB,RMC}},
6433 {"dquai.", ZRC(59,67,1), Z2_MASK, POWER6, PPCVLE, {TE, FRT,FRB,RMC}},
6435 {"dscri", ZRC(59,98,0), Z_MASK, POWER6, PPCVLE, {FRT, FRA, SH16}},
6436 {"dscri.", ZRC(59,98,1), Z_MASK, POWER6, PPCVLE, {FRT, FRA, SH16}},
6438 {"drintx", ZRC(59,99,0), Z2_MASK, POWER6, PPCVLE, {R, FRT, FRB, RMC}},
6439 {"drintx.", ZRC(59,99,1), Z2_MASK, POWER6, PPCVLE, {R, FRT, FRB, RMC}},
6441 {"dcmpo", X(59,130), X_MASK, POWER6, PPCVLE, {BF, FRA, FRB}},
6443 {"dtstex", X(59,162), X_MASK, POWER6, PPCVLE, {BF, FRA, FRB}},
6444 {"dtstdc", Z(59,194), Z_MASK, POWER6, PPCVLE, {BF, FRA, DCM}},
6445 {"dtstdg", Z(59,226), Z_MASK, POWER6, PPCVLE, {BF, FRA, DGM}},
6447 {"drintn", ZRC(59,227,0), Z2_MASK, POWER6, PPCVLE, {R, FRT, FRB, RMC}},
6448 {"drintn.", ZRC(59,227,1), Z2_MASK, POWER6, PPCVLE, {R, FRT, FRB, RMC}},
6450 {"dctdp", XRC(59,258,0), X_MASK, POWER6, PPCVLE, {FRT, FRB}},
6451 {"dctdp.", XRC(59,258,1), X_MASK, POWER6, PPCVLE, {FRT, FRB}},
6453 {"dctfix", XRC(59,290,0), X_MASK, POWER6, PPCVLE, {FRT, FRB}},
6454 {"dctfix.", XRC(59,290,1), X_MASK, POWER6, PPCVLE, {FRT, FRB}},
6456 {"ddedpd", XRC(59,322,0), X_MASK, POWER6, PPCVLE, {SP, FRT, FRB}},
6457 {"ddedpd.", XRC(59,322,1), X_MASK, POWER6, PPCVLE, {SP, FRT, FRB}},
6459 {"dxex", XRC(59,354,0), X_MASK, POWER6, PPCVLE, {FRT, FRB}},
6460 {"dxex.", XRC(59,354,1), X_MASK, POWER6, PPCVLE, {FRT, FRB}},
6462 {"dsub", XRC(59,514,0), X_MASK, POWER6, PPCVLE, {FRT, FRA, FRB}},
6463 {"dsub.", XRC(59,514,1), X_MASK, POWER6, PPCVLE, {FRT, FRA, FRB}},
6465 {"ddiv", XRC(59,546,0), X_MASK, POWER6, PPCVLE, {FRT, FRA, FRB}},
6466 {"ddiv.", XRC(59,546,1), X_MASK, POWER6, PPCVLE, {FRT, FRA, FRB}},
6468 {"dcmpu", X(59,642), X_MASK, POWER6, PPCVLE, {BF, FRA, FRB}},
6470 {"dtstsf", X(59,674), X_MASK, POWER6, PPCVLE, {BF, FRA, FRB}},
6471 {"dtstsfi", X(59,675), X_MASK|1<<22,POWER9, PPCVLE, {BF, UIM6, FRB}},
6473 {"drsp", XRC(59,770,0), X_MASK, POWER6, PPCVLE, {FRT, FRB}},
6474 {"drsp.", XRC(59,770,1), X_MASK, POWER6, PPCVLE, {FRT, FRB}},
6476 {"dcffix", XRC(59,802,0), X_MASK|FRA_MASK, POWER7, PPCVLE, {FRT, FRB}},
6477 {"dcffix.", XRC(59,802,1), X_MASK|FRA_MASK, POWER7, PPCVLE, {FRT, FRB}},
6479 {"denbcd", XRC(59,834,0), X_MASK, POWER6, PPCVLE, {S, FRT, FRB}},
6480 {"denbcd.", XRC(59,834,1), X_MASK, POWER6, PPCVLE, {S, FRT, FRB}},
6482 {"fcfids", XRC(59,846,0), XRA_MASK, POWER7|PPCA2, PPCVLE, {FRT, FRB}},
6483 {"fcfids.", XRC(59,846,1), XRA_MASK, POWER7|PPCA2, PPCVLE, {FRT, FRB}},
6485 {"diex", XRC(59,866,0), X_MASK, POWER6, PPCVLE, {FRT, FRA, FRB}},
6486 {"diex.", XRC(59,866,1), X_MASK, POWER6, PPCVLE, {FRT, FRA, FRB}},
6488 {"fcfidus", XRC(59,974,0), XRA_MASK, POWER7|PPCA2, PPCVLE, {FRT, FRB}},
6489 {"fcfidus.", XRC(59,974,1), XRA_MASK, POWER7|PPCA2, PPCVLE, {FRT, FRB}},
6491 {"xsaddsp", XX3(60,0), XX3_MASK, PPCVSX2, PPCVLE, {XT6, XA6, XB6}},
6492 {"xsmaddasp", XX3(60,1), XX3_MASK, PPCVSX2, PPCVLE, {XT6, XA6, XB6}},
6493 {"xxsldwi", XX3(60,2), XX3SHW_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6, SHW}},
6494 {"xscmpeqdp", XX3(60,3), XX3_MASK, PPCVSX3, PPCVLE, {XT6, XA6, XB6}},
6495 {"xsrsqrtesp", XX2(60,10), XX2_MASK, PPCVSX2, PPCVLE, {XT6, XB6}},
6496 {"xssqrtsp", XX2(60,11), XX2_MASK, PPCVSX2, PPCVLE, {XT6, XB6}},
6497 {"xxsel", XX4(60,3), XX4_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6, XC6}},
6498 {"xssubsp", XX3(60,8), XX3_MASK, PPCVSX2, PPCVLE, {XT6, XA6, XB6}},
6499 {"xsmaddmsp", XX3(60,9), XX3_MASK, PPCVSX2, PPCVLE, {XT6, XA6, XB6}},
6500 {"xxspltd", XX3(60,10), XX3DM_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6S, DMEX}},
6501 {"xxmrghd", XX3(60,10), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
6502 {"xxswapd", XX3(60,10)|(2<<8), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6S}},
6503 {"xxmrgld", XX3(60,10)|(3<<8), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
6504 {"xxpermdi", XX3(60,10), XX3DM_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6, DM}},
6505 {"xscmpgtdp", XX3(60,11), XX3_MASK, PPCVSX3, PPCVLE, {XT6, XA6, XB6}},
6506 {"xsresp", XX2(60,26), XX2_MASK, PPCVSX2, PPCVLE, {XT6, XB6}},
6507 {"xsmulsp", XX3(60,16), XX3_MASK, PPCVSX2, PPCVLE, {XT6, XA6, XB6}},
6508 {"xsmsubasp", XX3(60,17), XX3_MASK, PPCVSX2, PPCVLE, {XT6, XA6, XB6}},
6509 {"xxmrghw", XX3(60,18), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
6510 {"xscmpgedp", XX3(60,19), XX3_MASK, PPCVSX3, PPCVLE, {XT6, XA6, XB6}},
6511 {"xsdivsp", XX3(60,24), XX3_MASK, PPCVSX2, PPCVLE, {XT6, XA6, XB6}},
6512 {"xsmsubmsp", XX3(60,25), XX3_MASK, PPCVSX2, PPCVLE, {XT6, XA6, XB6}},
6513 {"xxperm", XX3(60,26), XX3_MASK, PPCVSX3, PPCVLE, {XT6, XA6, XB6}},
6514 {"xsadddp", XX3(60,32), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
6515 {"xsmaddadp", XX3(60,33), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
6516 {"xscmpudp", XX3(60,35), XX3BF_MASK, PPCVSX, PPCVLE, {BF, XA6, XB6}},
6517 {"xscvdpuxws", XX2(60,72), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}},
6518 {"xsrdpi", XX2(60,73), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}},
6519 {"xsrsqrtedp", XX2(60,74), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}},
6520 {"xssqrtdp", XX2(60,75), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}},
6521 {"xssubdp", XX3(60,40), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
6522 {"xsmaddmdp", XX3(60,41), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
6523 {"xscmpodp", XX3(60,43), XX3BF_MASK, PPCVSX, PPCVLE, {BF, XA6, XB6}},
6524 {"xscvdpsxws", XX2(60,88), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}},
6525 {"xsrdpiz", XX2(60,89), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}},
6526 {"xsredp", XX2(60,90), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}},
6527 {"xsmuldp", XX3(60,48), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
6528 {"xsmsubadp", XX3(60,49), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
6529 {"xxmrglw", XX3(60,50), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
6530 {"xsrdpip", XX2(60,105), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}},
6531 {"xstsqrtdp", XX2(60,106), XX2BF_MASK, PPCVSX, PPCVLE, {BF, XB6}},
6532 {"xsrdpic", XX2(60,107), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}},
6533 {"xsdivdp", XX3(60,56), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
6534 {"xsmsubmdp", XX3(60,57), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
6535 {"xxpermr", XX3(60,58), XX3_MASK, PPCVSX3, PPCVLE, {XT6, XA6, XB6}},
6536 {"xscmpexpdp", XX3(60,59), XX3BF_MASK, PPCVSX3, PPCVLE, {BF, XA6, XB6}},
6537 {"xsrdpim", XX2(60,121), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}},
6538 {"xstdivdp", XX3(60,61), XX3BF_MASK, PPCVSX, PPCVLE, {BF, XA6, XB6}},
6539 {"xvaddsp", XX3(60,64), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
6540 {"xvmaddasp", XX3(60,65), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
6541 {"xvcmpeqsp", XX3RC(60,67,0), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
6542 {"xvcmpeqsp.", XX3RC(60,67,1), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
6543 {"xvcvspuxws", XX2(60,136), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}},
6544 {"xvrspi", XX2(60,137), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}},
6545 {"xvrsqrtesp", XX2(60,138), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}},
6546 {"xvsqrtsp", XX2(60,139), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}},
6547 {"xvsubsp", XX3(60,72), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
6548 {"xvmaddmsp", XX3(60,73), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
6549 {"xvcmpgtsp", XX3RC(60,75,0), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
6550 {"xvcmpgtsp.", XX3RC(60,75,1), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
6551 {"xvcvspsxws", XX2(60,152), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}},
6552 {"xvrspiz", XX2(60,153), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}},
6553 {"xvresp", XX2(60,154), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}},
6554 {"xvmulsp", XX3(60,80), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
6555 {"xvmsubasp", XX3(60,81), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
6556 {"xxspltw", XX2(60,164), XX2UIM_MASK, PPCVSX, PPCVLE, {XT6, XB6, UIM}},
6557 {"xxextractuw", XX2(60,165), XX2UIM4_MASK, PPCVSX3, PPCVLE, {XT6, XB6, UIMM4}},
6558 {"xvcmpgesp", XX3RC(60,83,0), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
6559 {"xvcmpgesp.", XX3RC(60,83,1), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
6560 {"xvcvuxwsp", XX2(60,168), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}},
6561 {"xvrspip", XX2(60,169), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}},
6562 {"xvtsqrtsp", XX2(60,170), XX2BF_MASK, PPCVSX, PPCVLE, {BF, XB6}},
6563 {"xvrspic", XX2(60,171), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}},
6564 {"xvdivsp", XX3(60,88), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
6565 {"xvmsubmsp", XX3(60,89), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
6566 {"xxspltib", X(60,360), XX1_MASK|3<<19, PPCVSX3, PPCVLE, {XT6, IMM8}},
6567 {"xxinsertw", XX2(60,181), XX2UIM4_MASK, PPCVSX3, PPCVLE, {XT6, XB6, UIMM4}},
6568 {"xvcvsxwsp", XX2(60,184), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}},
6569 {"xvrspim", XX2(60,185), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}},
6570 {"xvtdivsp", XX3(60,93), XX3BF_MASK, PPCVSX, PPCVLE, {BF, XA6, XB6}},
6571 {"xvadddp", XX3(60,96), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
6572 {"xvmaddadp", XX3(60,97), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
6573 {"xvcmpeqdp", XX3RC(60,99,0), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
6574 {"xvcmpeqdp.", XX3RC(60,99,1), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
6575 {"xvcvdpuxws", XX2(60,200), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}},
6576 {"xvrdpi", XX2(60,201), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}},
6577 {"xvrsqrtedp", XX2(60,202), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}},
6578 {"xvsqrtdp", XX2(60,203), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}},
6579 {"xvsubdp", XX3(60,104), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
6580 {"xvmaddmdp", XX3(60,105), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
6581 {"xvcmpgtdp", XX3RC(60,107,0), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
6582 {"xvcmpgtdp.", XX3RC(60,107,1), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
6583 {"xvcvdpsxws", XX2(60,216), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}},
6584 {"xvrdpiz", XX2(60,217), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}},
6585 {"xvredp", XX2(60,218), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}},
6586 {"xvmuldp", XX3(60,112), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
6587 {"xvmsubadp", XX3(60,113), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
6588 {"xvcmpgedp", XX3RC(60,115,0), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
6589 {"xvcmpgedp.", XX3RC(60,115,1), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
6590 {"xvcvuxwdp", XX2(60,232), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}},
6591 {"xvrdpip", XX2(60,233), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}},
6592 {"xvtsqrtdp", XX2(60,234), XX2BF_MASK, PPCVSX, PPCVLE, {BF, XB6}},
6593 {"xvrdpic", XX2(60,235), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}},
6594 {"xvdivdp", XX3(60,120), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
6595 {"xvmsubmdp", XX3(60,121), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
6596 {"xvcvsxwdp", XX2(60,248), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}},
6597 {"xvrdpim", XX2(60,249), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}},
6598 {"xvtdivdp", XX3(60,125), XX3BF_MASK, PPCVSX, PPCVLE, {BF, XA6, XB6}},
6599 {"xsmaxcdp", XX3(60,128), XX3_MASK, PPCVSX3, PPCVLE, {XT6, XA6, XB6}},
6600 {"xsnmaddasp", XX3(60,129), XX3_MASK, PPCVSX2, PPCVLE, {XT6, XA6, XB6}},
6601 {"xxland", XX3(60,130), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
6602 {"xscvdpsp", XX2(60,265), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}},
6603 {"xscvdpspn", XX2(60,267), XX2_MASK, PPCVSX2, PPCVLE, {XT6, XB6}},
6604 {"xsmincdp", XX3(60,136), XX3_MASK, PPCVSX3, PPCVLE, {XT6, XA6, XB6}},
6605 {"xsnmaddmsp", XX3(60,137), XX3_MASK, PPCVSX2, PPCVLE, {XT6, XA6, XB6}},
6606 {"xxlandc", XX3(60,138), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
6607 {"xsrsp", XX2(60,281), XX2_MASK, PPCVSX2, PPCVLE, {XT6, XB6}},
6608 {"xsmaxjdp", XX3(60,144), XX3_MASK, PPCVSX3, PPCVLE, {XT6, XA6, XB6}},
6609 {"xsnmsubasp", XX3(60,145), XX3_MASK, PPCVSX2, PPCVLE, {XT6, XA6, XB6}},
6610 {"xxlor", XX3(60,146), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
6611 {"xscvuxdsp", XX2(60,296), XX2_MASK, PPCVSX2, PPCVLE, {XT6, XB6}},
6612 {"xststdcsp", XX2(60,298), XX2BFD_MASK, PPCVSX3, PPCVLE, {BF, XB6, DCMX}},
6613 {"xsminjdp", XX3(60,152), XX3_MASK, PPCVSX3, PPCVLE, {XT6, XA6, XB6}},
6614 {"xsnmsubmsp", XX3(60,153), XX3_MASK, PPCVSX2, PPCVLE, {XT6, XA6, XB6}},
6615 {"xxlxor", XX3(60,154), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
6616 {"xscvsxdsp", XX2(60,312), XX2_MASK, PPCVSX2, PPCVLE, {XT6, XB6}},
6617 {"xsmaxdp", XX3(60,160), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
6618 {"xsnmaddadp", XX3(60,161), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
6619 {"xxlnor", XX3(60,162), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
6620 {"xscvdpuxds", XX2(60,328), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}},
6621 {"xscvspdp", XX2(60,329), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}},
6622 {"xscvspdpn", XX2(60,331), XX2_MASK, PPCVSX2, PPCVLE, {XT6, XB6}},
6623 {"xsmindp", XX3(60,168), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
6624 {"xsnmaddmdp", XX3(60,169), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
6625 {"xxlorc", XX3(60,170), XX3_MASK, PPCVSX2, PPCVLE, {XT6, XA6, XB6}},
6626 {"xscvdpsxds", XX2(60,344), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}},
6627 {"xsabsdp", XX2(60,345), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}},
6628 {"xsxexpdp", XX2VA(60,347,0),XX2_MASK|1, PPCVSX3, PPCVLE, {RT, XB6}},
6629 {"xsxsigdp", XX2VA(60,347,1),XX2_MASK|1, PPCVSX3, PPCVLE, {RT, XB6}},
6630 {"xscvhpdp", XX2VA(60,347,16),XX2_MASK, PPCVSX3, PPCVLE, {XT6, XB6}},
6631 {"xscvdphp", XX2VA(60,347,17),XX2_MASK, PPCVSX3, PPCVLE, {XT6, XB6}},
6632 {"xscpsgndp", XX3(60,176), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
6633 {"xsnmsubadp", XX3(60,177), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
6634 {"xxlnand", XX3(60,178), XX3_MASK, PPCVSX2, PPCVLE, {XT6, XA6, XB6}},
6635 {"xscvuxddp", XX2(60,360), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}},
6636 {"xsnabsdp", XX2(60,361), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}},
6637 {"xststdcdp", XX2(60,362), XX2BFD_MASK, PPCVSX3, PPCVLE, {BF, XB6, DCMX}},
6638 {"xsnmsubmdp", XX3(60,185), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
6639 {"xxleqv", XX3(60,186), XX3_MASK, PPCVSX2, PPCVLE, {XT6, XA6, XB6}},
6640 {"xscvsxddp", XX2(60,376), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}},
6641 {"xsnegdp", XX2(60,377), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}},
6642 {"xvmaxsp", XX3(60,192), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
6643 {"xvnmaddasp", XX3(60,193), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
6644 {"xvcvspuxds", XX2(60,392), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}},
6645 {"xvcvdpsp", XX2(60,393), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}},
6646 {"xvminsp", XX3(60,200), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
6647 {"xvnmaddmsp", XX3(60,201), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
6648 {"xvcvspsxds", XX2(60,408), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}},
6649 {"xvabssp", XX2(60,409), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}},
6650 {"xvmovsp", XX3(60,208), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6S}},
6651 {"xvcpsgnsp", XX3(60,208), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
6652 {"xvnmsubasp", XX3(60,209), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
6653 {"xvcvuxdsp", XX2(60,424), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}},
6654 {"xvnabssp", XX2(60,425), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}},
6655 {"xvtstdcsp", XX2(60,426), XX2DCMXS_MASK, PPCVSX3, PPCVLE, {XT6, XB6, DCMXS}},
6656 {"xviexpsp", XX3(60,216), XX3_MASK, PPCVSX3, PPCVLE, {XT6, XA6, XB6}},
6657 {"xvnmsubmsp", XX3(60,217), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
6658 {"xvcvsxdsp", XX2(60,440), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}},
6659 {"xvnegsp", XX2(60,441), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}},
6660 {"xvmaxdp", XX3(60,224), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
6661 {"xvnmaddadp", XX3(60,225), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
6662 {"xvcvdpuxds", XX2(60,456), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}},
6663 {"xvcvspdp", XX2(60,457), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}},
6664 {"xsiexpdp", X(60,918), XX1_MASK, PPCVSX3, PPCVLE, {XT6, RA, RB}},
6665 {"xvmindp", XX3(60,232), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
6666 {"xvnmaddmdp", XX3(60,233), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
6667 {"xvcvdpsxds", XX2(60,472), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}},
6668 {"xvabsdp", XX2(60,473), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}},
6669 {"xvxexpdp", XX2VA(60,475,0),XX2_MASK, PPCVSX3, PPCVLE, {XT6, XB6}},
6670 {"xvxsigdp", XX2VA(60,475,1),XX2_MASK, PPCVSX3, PPCVLE, {XT6, XB6}},
6671 {"xxbrh", XX2VA(60,475,7),XX2_MASK, PPCVSX3, PPCVLE, {XT6, XB6}},
6672 {"xvxexpsp", XX2VA(60,475,8),XX2_MASK, PPCVSX3, PPCVLE, {XT6, XB6}},
6673 {"xvxsigsp", XX2VA(60,475,9),XX2_MASK, PPCVSX3, PPCVLE, {XT6, XB6}},
6674 {"xxbrw", XX2VA(60,475,15),XX2_MASK, PPCVSX3, PPCVLE, {XT6, XB6}},
6675 {"xxbrd", XX2VA(60,475,23),XX2_MASK, PPCVSX3, PPCVLE, {XT6, XB6}},
6676 {"xvcvhpsp", XX2VA(60,475,24),XX2_MASK, PPCVSX3, PPCVLE, {XT6, XB6}},
6677 {"xvcvsphp", XX2VA(60,475,25),XX2_MASK, PPCVSX3, PPCVLE, {XT6, XB6}},
6678 {"xxbrq", XX2VA(60,475,31),XX2_MASK, PPCVSX3, PPCVLE, {XT6, XB6}},
6679 {"xvmovdp", XX3(60,240), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6S}},
6680 {"xvcpsgndp", XX3(60,240), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
6681 {"xvnmsubadp", XX3(60,241), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
6682 {"xvcvuxddp", XX2(60,488), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}},
6683 {"xvnabsdp", XX2(60,489), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}},
6684 {"xvtstdcdp", XX2(60,490), XX2DCMXS_MASK, PPCVSX3, PPCVLE, {XT6, XB6, DCMXS}},
6685 {"xviexpdp", XX3(60,248), XX3_MASK, PPCVSX3, PPCVLE, {XT6, XA6, XB6}},
6686 {"xvnmsubmdp", XX3(60,249), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
6687 {"xvcvsxddp", XX2(60,504), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}},
6688 {"xvnegdp", XX2(60,505), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}},
6690 {"psq_st", OP(60), OP_MASK, PPCPS, PPCVLE, {FRS,PSD,RA,PSW,PSQ}},
6691 {"stfq", OP(60), OP_MASK, POWER2, PPCVLE, {FRS, D, RA}},
6693 {"lxv", DQX(61,1), DQX_MASK, PPCVSX3, PPCVLE, {XTQ6, DQ, RA0}},
6694 {"stxv", DQX(61,5), DQX_MASK, PPCVSX3, PPCVLE, {XSQ6, DQ, RA0}},
6695 {"stxsd", DSO(61,2), DS_MASK, PPCVSX3, PPCVLE, {VS, DS, RA0}},
6696 {"stxssp", DSO(61,3), DS_MASK, PPCVSX3, PPCVLE, {VS, DS, RA0}},
6697 {"stfdp", OP(61), OP_MASK, POWER6, POWER7|PPCVLE, {FRSp, DS, RA0}},
6698 {"psq_stu", OP(61), OP_MASK, PPCPS, PPCVLE, {FRS,PSD,RA,PSW,PSQ}},
6699 {"stfqu", OP(61), OP_MASK, POWER2, PPCVLE, {FRS, D, RA}},
6701 {"std", DSO(62,0), DS_MASK, PPC64, PPCVLE, {RS, DS, RA0}},
6702 {"stdu", DSO(62,1), DS_MASK, PPC64, PPCVLE, {RS, DS, RAS}},
6703 {"stq", DSO(62,2), DS_MASK, POWER4, PPC476|PPCVLE, {RSQ, DS, RA0}},
6705 {"fcmpu", X(63,0), XBF_MASK, COM, PPCEFS|PPCVLE, {BF, FRA, FRB}},
6707 {"daddq", XRC(63,2,0), X_MASK, POWER6, PPCVLE, {FRTp, FRAp, FRBp}},
6708 {"daddq.", XRC(63,2,1), X_MASK, POWER6, PPCVLE, {FRTp, FRAp, FRBp}},
6710 {"dquaq", ZRC(63,3,0), Z2_MASK, POWER6, PPCVLE, {FRTp, FRAp, FRBp, RMC}},
6711 {"dquaq.", ZRC(63,3,1), Z2_MASK, POWER6, PPCVLE, {FRTp, FRAp, FRBp, RMC}},
6713 {"xsaddqp", XRC(63,4,0), X_MASK, PPCVSX3, PPCVLE, {VD, VA, VB}},
6714 {"xsaddqpo", XRC(63,4,1), X_MASK, PPCVSX3, PPCVLE, {VD, VA, VB}},
6716 {"xsrqpi", ZRC(63,5,0), Z2_MASK, PPCVSX3, PPCVLE, {R, VD, VB, RMC}},
6717 {"xsrqpix", ZRC(63,5,1), Z2_MASK, PPCVSX3, PPCVLE, {R, VD, VB, RMC}},
6719 {"fcpsgn", XRC(63,8,0), X_MASK, POWER6|PPCA2|PPC476, PPCVLE, {FRT, FRA, FRB}},
6720 {"fcpsgn.", XRC(63,8,1), X_MASK, POWER6|PPCA2|PPC476, PPCVLE, {FRT, FRA, FRB}},
6722 {"frsp", XRC(63,12,0), XRA_MASK, COM, PPCEFS|PPCVLE, {FRT, FRB}},
6723 {"frsp.", XRC(63,12,1), XRA_MASK, COM, PPCEFS|PPCVLE, {FRT, FRB}},
6725 {"fctiw", XRC(63,14,0), XRA_MASK, PPCCOM, PPCEFS|PPCVLE, {FRT, FRB}},
6726 {"fcir", XRC(63,14,0), XRA_MASK, PWR2COM, PPCVLE, {FRT, FRB}},
6727 {"fctiw.", XRC(63,14,1), XRA_MASK, PPCCOM, PPCEFS|PPCVLE, {FRT, FRB}},
6728 {"fcir.", XRC(63,14,1), XRA_MASK, PWR2COM, PPCVLE, {FRT, FRB}},
6730 {"fctiwz", XRC(63,15,0), XRA_MASK, PPCCOM, PPCEFS|PPCVLE, {FRT, FRB}},
6731 {"fcirz", XRC(63,15,0), XRA_MASK, PWR2COM, PPCVLE, {FRT, FRB}},
6732 {"fctiwz.", XRC(63,15,1), XRA_MASK, PPCCOM, PPCEFS|PPCVLE, {FRT, FRB}},
6733 {"fcirz.", XRC(63,15,1), XRA_MASK, PWR2COM, PPCVLE, {FRT, FRB}},
6735 {"fdiv", A(63,18,0), AFRC_MASK, PPCCOM, PPCEFS|PPCVLE, {FRT, FRA, FRB}},
6736 {"fd", A(63,18,0), AFRC_MASK, PWRCOM, PPCVLE, {FRT, FRA, FRB}},
6737 {"fdiv.", A(63,18,1), AFRC_MASK, PPCCOM, PPCEFS|PPCVLE, {FRT, FRA, FRB}},
6738 {"fd.", A(63,18,1), AFRC_MASK, PWRCOM, PPCVLE, {FRT, FRA, FRB}},
6740 {"fsub", A(63,20,0), AFRC_MASK, PPCCOM, PPCEFS|PPCVLE, {FRT, FRA, FRB}},
6741 {"fs", A(63,20,0), AFRC_MASK, PWRCOM, PPCVLE, {FRT, FRA, FRB}},
6742 {"fsub.", A(63,20,1), AFRC_MASK, PPCCOM, PPCEFS|PPCVLE, {FRT, FRA, FRB}},
6743 {"fs.", A(63,20,1), AFRC_MASK, PWRCOM, PPCVLE, {FRT, FRA, FRB}},
6745 {"fadd", A(63,21,0), AFRC_MASK, PPCCOM, PPCEFS|PPCVLE, {FRT, FRA, FRB}},
6746 {"fa", A(63,21,0), AFRC_MASK, PWRCOM, PPCVLE, {FRT, FRA, FRB}},
6747 {"fadd.", A(63,21,1), AFRC_MASK, PPCCOM, PPCEFS|PPCVLE, {FRT, FRA, FRB}},
6748 {"fa.", A(63,21,1), AFRC_MASK, PWRCOM, PPCVLE, {FRT, FRA, FRB}},
6750 {"fsqrt", A(63,22,0), AFRAFRC_MASK, PPCPWR2, TITAN|PPCVLE, {FRT, FRB}},
6751 {"fsqrt.", A(63,22,1), AFRAFRC_MASK, PPCPWR2, TITAN|PPCVLE, {FRT, FRB}},
6753 {"fsel", A(63,23,0), A_MASK, PPC, PPCEFS|PPCVLE, {FRT, FRA, FRC, FRB}},
6754 {"fsel.", A(63,23,1), A_MASK, PPC, PPCEFS|PPCVLE, {FRT, FRA, FRC, FRB}},
6756 {"fre", A(63,24,0), AFRAFRC_MASK, POWER7, PPCVLE, {FRT, FRB}},
6757 {"fre", A(63,24,0), AFRALFRC_MASK, POWER5, POWER7|PPCVLE, {FRT, FRB, A_L}},
6758 {"fre.", A(63,24,1), AFRAFRC_MASK, POWER7, PPCVLE, {FRT, FRB}},
6759 {"fre.", A(63,24,1), AFRALFRC_MASK, POWER5, POWER7|PPCVLE, {FRT, FRB, A_L}},
6761 {"fmul", A(63,25,0), AFRB_MASK, PPCCOM, PPCEFS|PPCVLE, {FRT, FRA, FRC}},
6762 {"fm", A(63,25,0), AFRB_MASK, PWRCOM, PPCVLE|PPCVLE, {FRT, FRA, FRC}},
6763 {"fmul.", A(63,25,1), AFRB_MASK, PPCCOM, PPCEFS|PPCVLE, {FRT, FRA, FRC}},
6764 {"fm.", A(63,25,1), AFRB_MASK, PWRCOM, PPCVLE|PPCVLE, {FRT, FRA, FRC}},
6766 {"frsqrte", A(63,26,0), AFRAFRC_MASK, POWER7, PPCVLE, {FRT, FRB}},
6767 {"frsqrte", A(63,26,0), AFRALFRC_MASK, PPC, POWER7|PPCVLE, {FRT, FRB, A_L}},
6768 {"frsqrte.", A(63,26,1), AFRAFRC_MASK, POWER7, PPCVLE, {FRT, FRB}},
6769 {"frsqrte.", A(63,26,1), AFRALFRC_MASK, PPC, POWER7|PPCVLE, {FRT, FRB, A_L}},
6771 {"fmsub", A(63,28,0), A_MASK, PPCCOM, PPCEFS|PPCVLE, {FRT, FRA, FRC, FRB}},
6772 {"fms", A(63,28,0), A_MASK, PWRCOM, PPCVLE, {FRT, FRA, FRC, FRB}},
6773 {"fmsub.", A(63,28,1), A_MASK, PPCCOM, PPCEFS|PPCVLE, {FRT, FRA, FRC, FRB}},
6774 {"fms.", A(63,28,1), A_MASK, PWRCOM, PPCVLE, {FRT, FRA, FRC, FRB}},
6776 {"fmadd", A(63,29,0), A_MASK, PPCCOM, PPCEFS|PPCVLE, {FRT, FRA, FRC, FRB}},
6777 {"fma", A(63,29,0), A_MASK, PWRCOM, PPCVLE, {FRT, FRA, FRC, FRB}},
6778 {"fmadd.", A(63,29,1), A_MASK, PPCCOM, PPCEFS|PPCVLE, {FRT, FRA, FRC, FRB}},
6779 {"fma.", A(63,29,1), A_MASK, PWRCOM, PPCVLE, {FRT, FRA, FRC, FRB}},
6781 {"fnmsub", A(63,30,0), A_MASK, PPCCOM, PPCEFS|PPCVLE, {FRT, FRA, FRC, FRB}},
6782 {"fnms", A(63,30,0), A_MASK, PWRCOM, PPCVLE, {FRT, FRA, FRC, FRB}},
6783 {"fnmsub.", A(63,30,1), A_MASK, PPCCOM, PPCEFS|PPCVLE, {FRT, FRA, FRC, FRB}},
6784 {"fnms.", A(63,30,1), A_MASK, PWRCOM, PPCVLE, {FRT, FRA, FRC, FRB}},
6786 {"fnmadd", A(63,31,0), A_MASK, PPCCOM, PPCEFS|PPCVLE, {FRT, FRA, FRC, FRB}},
6787 {"fnma", A(63,31,0), A_MASK, PWRCOM, PPCVLE, {FRT, FRA, FRC, FRB}},
6788 {"fnmadd.", A(63,31,1), A_MASK, PPCCOM, PPCEFS|PPCVLE, {FRT, FRA, FRC, FRB}},
6789 {"fnma.", A(63,31,1), A_MASK, PWRCOM, PPCVLE, {FRT, FRA, FRC, FRB}},
6791 {"fcmpo", X(63,32), XBF_MASK, COM, PPCEFS|PPCVLE, {BF, FRA, FRB}},
6793 {"dmulq", XRC(63,34,0), X_MASK, POWER6, PPCVLE, {FRTp, FRAp, FRBp}},
6794 {"dmulq.", XRC(63,34,1), X_MASK, POWER6, PPCVLE, {FRTp, FRAp, FRBp}},
6796 {"drrndq", ZRC(63,35,0), Z2_MASK, POWER6, PPCVLE, {FRTp, FRA, FRBp, RMC}},
6797 {"drrndq.", ZRC(63,35,1), Z2_MASK, POWER6, PPCVLE, {FRTp, FRA, FRBp, RMC}},
6799 {"xsmulqp", XRC(63,36,0), X_MASK, PPCVSX3, PPCVLE, {VD, VA, VB}},
6800 {"xsmulqpo", XRC(63,36,1), X_MASK, PPCVSX3, PPCVLE, {VD, VA, VB}},
6802 {"xsrqpxp", Z(63,37), Z2_MASK, PPCVSX3, PPCVLE, {R, VD, VB, RMC}},
6804 {"mtfsb1", XRC(63,38,0), XRARB_MASK, COM, PPCVLE, {BT}},
6805 {"mtfsb1.", XRC(63,38,1), XRARB_MASK, COM, PPCVLE, {BT}},
6807 {"fneg", XRC(63,40,0), XRA_MASK, COM, PPCEFS|PPCVLE, {FRT, FRB}},
6808 {"fneg.", XRC(63,40,1), XRA_MASK, COM, PPCEFS|PPCVLE, {FRT, FRB}},
6810 {"mcrfs", X(63,64), XRB_MASK|(3<<21)|(3<<16), COM, PPCVLE, {BF, BFA}},
6812 {"dscliq", ZRC(63,66,0), Z_MASK, POWER6, PPCVLE, {FRTp, FRAp, SH16}},
6813 {"dscliq.", ZRC(63,66,1), Z_MASK, POWER6, PPCVLE, {FRTp, FRAp, SH16}},
6815 {"dquaiq", ZRC(63,67,0), Z2_MASK, POWER6, PPCVLE, {TE, FRTp, FRBp, RMC}},
6816 {"dquaiq.", ZRC(63,67,1), Z2_MASK, POWER6, PPCVLE, {TE, FRTp, FRBp, RMC}},
6818 {"mtfsb0", XRC(63,70,0), XRARB_MASK, COM, PPCVLE, {BT}},
6819 {"mtfsb0.", XRC(63,70,1), XRARB_MASK, COM, PPCVLE, {BT}},
6821 {"fmr", XRC(63,72,0), XRA_MASK, COM, PPCEFS|PPCVLE, {FRT, FRB}},
6822 {"fmr.", XRC(63,72,1), XRA_MASK, COM, PPCEFS|PPCVLE, {FRT, FRB}},
6824 {"dscriq", ZRC(63,98,0), Z_MASK, POWER6, PPCVLE, {FRTp, FRAp, SH16}},
6825 {"dscriq.", ZRC(63,98,1), Z_MASK, POWER6, PPCVLE, {FRTp, FRAp, SH16}},
6827 {"drintxq", ZRC(63,99,0), Z2_MASK, POWER6, PPCVLE, {R, FRTp, FRBp, RMC}},
6828 {"drintxq.", ZRC(63,99,1), Z2_MASK, POWER6, PPCVLE, {R, FRTp, FRBp, RMC}},
6830 {"xscpsgnqp", X(63,100), X_MASK, PPCVSX3, PPCVLE, {VD, VA, VB}},
6832 {"ftdiv", X(63,128), XBF_MASK, POWER7, PPCVLE, {BF, FRA, FRB}},
6834 {"dcmpoq", X(63,130), X_MASK, POWER6, PPCVLE, {BF, FRAp, FRBp}},
6836 {"xscmpoqp", X(63,132), XBF_MASK, PPCVSX3, PPCVLE, {BF, VA, VB}},
6838 {"mtfsfi", XRC(63,134,0), XWRA_MASK|(3<<21)|(1<<11), POWER6|PPCA2|PPC476, PPCVLE, {BFF, U, W}},
6839 {"mtfsfi", XRC(63,134,0), XRA_MASK|(3<<21)|(1<<11), COM, POWER6|PPCA2|PPC476|PPCVLE, {BFF, U}},
6840 {"mtfsfi.", XRC(63,134,1), XWRA_MASK|(3<<21)|(1<<11), POWER6|PPCA2|PPC476, PPCVLE, {BFF, U, W}},
6841 {"mtfsfi.", XRC(63,134,1), XRA_MASK|(3<<21)|(1<<11), COM, POWER6|PPCA2|PPC476|PPCVLE, {BFF, U}},
6843 {"fnabs", XRC(63,136,0), XRA_MASK, COM, PPCEFS|PPCVLE, {FRT, FRB}},
6844 {"fnabs.", XRC(63,136,1), XRA_MASK, COM, PPCEFS|PPCVLE, {FRT, FRB}},
6846 {"fctiwu", XRC(63,142,0), XRA_MASK, POWER7, PPCVLE, {FRT, FRB}},
6847 {"fctiwu.", XRC(63,142,1), XRA_MASK, POWER7, PPCVLE, {FRT, FRB}},
6848 {"fctiwuz", XRC(63,143,0), XRA_MASK, POWER7, PPCVLE, {FRT, FRB}},
6849 {"fctiwuz.", XRC(63,143,1), XRA_MASK, POWER7, PPCVLE, {FRT, FRB}},
6851 {"ftsqrt", X(63,160), XBF_MASK|FRA_MASK, POWER7, PPCVLE, {BF, FRB}},
6853 {"dtstexq", X(63,162), X_MASK, POWER6, PPCVLE, {BF, FRAp, FRBp}},
6855 {"xscmpexpqp", X(63,164), XBF_MASK, PPCVSX3, PPCVLE, {BF, VA, VB}},
6857 {"dtstdcq", Z(63,194), Z_MASK, POWER6, PPCVLE, {BF, FRAp, DCM}},
6858 {"dtstdgq", Z(63,226), Z_MASK, POWER6, PPCVLE, {BF, FRAp, DGM}},
6860 {"drintnq", ZRC(63,227,0), Z2_MASK, POWER6, PPCVLE, {R, FRTp, FRBp, RMC}},
6861 {"drintnq.", ZRC(63,227,1), Z2_MASK, POWER6, PPCVLE, {R, FRTp, FRBp, RMC}},
6863 {"dctqpq", XRC(63,258,0), X_MASK, POWER6, PPCVLE, {FRTp, FRB}},
6864 {"dctqpq.", XRC(63,258,1), X_MASK, POWER6, PPCVLE, {FRTp, FRB}},
6866 {"fabs", XRC(63,264,0), XRA_MASK, COM, PPCEFS|PPCVLE, {FRT, FRB}},
6867 {"fabs.", XRC(63,264,1), XRA_MASK, COM, PPCEFS|PPCVLE, {FRT, FRB}},
6869 {"dctfixq", XRC(63,290,0), X_MASK, POWER6, PPCVLE, {FRT, FRBp}},
6870 {"dctfixq.", XRC(63,290,1), X_MASK, POWER6, PPCVLE, {FRT, FRBp}},
6872 {"ddedpdq", XRC(63,322,0), X_MASK, POWER6, PPCVLE, {SP, FRTp, FRBp}},
6873 {"ddedpdq.", XRC(63,322,1), X_MASK, POWER6, PPCVLE, {SP, FRTp, FRBp}},
6875 {"dxexq", XRC(63,354,0), X_MASK, POWER6, PPCVLE, {FRT, FRBp}},
6876 {"dxexq.", XRC(63,354,1), X_MASK, POWER6, PPCVLE, {FRT, FRBp}},
6878 {"xsmaddqp", XRC(63,388,0), X_MASK, PPCVSX3, PPCVLE, {VD, VA, VB}},
6879 {"xsmaddqpo", XRC(63,388,1), X_MASK, PPCVSX3, PPCVLE, {VD, VA, VB}},
6881 {"frin", XRC(63,392,0), XRA_MASK, POWER5, PPCVLE, {FRT, FRB}},
6882 {"frin.", XRC(63,392,1), XRA_MASK, POWER5, PPCVLE, {FRT, FRB}},
6884 {"xsmsubqp", XRC(63,420,0), X_MASK, PPCVSX3, PPCVLE, {VD, VA, VB}},
6885 {"xsmsubqpo", XRC(63,420,1), X_MASK, PPCVSX3, PPCVLE, {VD, VA, VB}},
6887 {"friz", XRC(63,424,0), XRA_MASK, POWER5, PPCVLE, {FRT, FRB}},
6888 {"friz.", XRC(63,424,1), XRA_MASK, POWER5, PPCVLE, {FRT, FRB}},
6890 {"xsnmaddqp", XRC(63,452,0), X_MASK, PPCVSX3, PPCVLE, {VD, VA, VB}},
6891 {"xsnmaddqpo", XRC(63,452,1), X_MASK, PPCVSX3, PPCVLE, {VD, VA, VB}},
6893 {"frip", XRC(63,456,0), XRA_MASK, POWER5, PPCVLE, {FRT, FRB}},
6894 {"frip.", XRC(63,456,1), XRA_MASK, POWER5, PPCVLE, {FRT, FRB}},
6896 {"xsnmsubqp", XRC(63,484,0), X_MASK, PPCVSX3, PPCVLE, {VD, VA, VB}},
6897 {"xsnmsubqpo", XRC(63,484,1), X_MASK, PPCVSX3, PPCVLE, {VD, VA, VB}},
6899 {"frim", XRC(63,488,0), XRA_MASK, POWER5, PPCVLE, {FRT, FRB}},
6900 {"frim.", XRC(63,488,1), XRA_MASK, POWER5, PPCVLE, {FRT, FRB}},
6902 {"dsubq", XRC(63,514,0), X_MASK, POWER6, PPCVLE, {FRTp, FRAp, FRBp}},
6903 {"dsubq.", XRC(63,514,1), X_MASK, POWER6, PPCVLE, {FRTp, FRAp, FRBp}},
6905 {"xssubqp", XRC(63,516,0), X_MASK, PPCVSX3, PPCVLE, {VD, VA, VB}},
6906 {"xssubqpo", XRC(63,516,1), X_MASK, PPCVSX3, PPCVLE, {VD, VA, VB}},
6908 {"ddivq", XRC(63,546,0), X_MASK, POWER6, PPCVLE, {FRTp, FRAp, FRBp}},
6909 {"ddivq.", XRC(63,546,1), X_MASK, POWER6, PPCVLE, {FRTp, FRAp, FRBp}},
6911 {"xsdivqp", XRC(63,548,0), X_MASK, PPCVSX3, PPCVLE, {VD, VA, VB}},
6912 {"xsdivqpo", XRC(63,548,1), X_MASK, PPCVSX3, PPCVLE, {VD, VA, VB}},
6914 {"mffs", XRC(63,583,0), XRARB_MASK, COM, PPCEFS|PPCVLE, {FRT}},
6915 {"mffs.", XRC(63,583,1), XRARB_MASK, COM, PPCEFS|PPCVLE, {FRT}},
6917 {"dcmpuq", X(63,642), X_MASK, POWER6, PPCVLE, {BF, FRAp, FRBp}},
6919 {"xscmpuqp", X(63,644), XBF_MASK, PPCVSX3, PPCVLE, {BF, VA, VB}},
6921 {"dtstsfq", X(63,674), X_MASK, POWER6, PPCVLE, {BF, FRA, FRBp}},
6922 {"dtstsfiq", X(63,675), X_MASK|1<<22,POWER9, PPCVLE, {BF, UIM6, FRBp}},
6924 {"xststdcqp", X(63,708), X_MASK, PPCVSX3, PPCVLE, {BF, VB, DCMX}},
6926 {"mtfsf", XFL(63,711,0), XFL_MASK, POWER6|PPCA2|PPC476, PPCVLE, {FLM, FRB, XFL_L, W}},
6927 {"mtfsf", XFL(63,711,0), XFL_MASK, COM, POWER6|PPCA2|PPC476|PPCEFS|PPCVLE, {FLM, FRB}},
6928 {"mtfsf.", XFL(63,711,1), XFL_MASK, POWER6|PPCA2|PPC476, PPCVLE, {FLM, FRB, XFL_L, W}},
6929 {"mtfsf.", XFL(63,711,1), XFL_MASK, COM, POWER6|PPCA2|PPC476|PPCEFS|PPCVLE, {FLM, FRB}},
6931 {"drdpq", XRC(63,770,0), X_MASK, POWER6, PPCVLE, {FRTp, FRBp}},
6932 {"drdpq.", XRC(63,770,1), X_MASK, POWER6, PPCVLE, {FRTp, FRBp}},
6934 {"dcffixq", XRC(63,802,0), X_MASK, POWER6, PPCVLE, {FRTp, FRB}},
6935 {"dcffixq.", XRC(63,802,1), X_MASK, POWER6, PPCVLE, {FRTp, FRB}},
6937 {"xsabsqp", XVA(63,804,0), XVA_MASK, PPCVSX3, PPCVLE, {VD, VB}},
6938 {"xsxexpqp", XVA(63,804,2), XVA_MASK, PPCVSX3, PPCVLE, {VD, VB}},
6939 {"xsnabsqp", XVA(63,804,8), XVA_MASK, PPCVSX3, PPCVLE, {VD, VB}},
6940 {"xsnegqp", XVA(63,804,16), XVA_MASK, PPCVSX3, PPCVLE, {VD, VB}},
6941 {"xsxsigqp", XVA(63,804,18), XVA_MASK, PPCVSX3, PPCVLE, {VD, VB}},
6942 {"xssqrtqp", XVARC(63,804,27,0), XVA_MASK, PPCVSX3, PPCVLE, {VD, VB}},
6943 {"xssqrtqpo", XVARC(63,804,27,1), XVA_MASK, PPCVSX3, PPCVLE, {VD, VB}},
6945 {"fctid", XRC(63,814,0), XRA_MASK, PPC64, PPCVLE, {FRT, FRB}},
6946 {"fctid", XRC(63,814,0), XRA_MASK, PPC476, PPCVLE, {FRT, FRB}},
6947 {"fctid.", XRC(63,814,1), XRA_MASK, PPC64, PPCVLE, {FRT, FRB}},
6948 {"fctid.", XRC(63,814,1), XRA_MASK, PPC476, PPCVLE, {FRT, FRB}},
6950 {"fctidz", XRC(63,815,0), XRA_MASK, PPC64, PPCVLE, {FRT, FRB}},
6951 {"fctidz", XRC(63,815,0), XRA_MASK, PPC476, PPCVLE, {FRT, FRB}},
6952 {"fctidz.", XRC(63,815,1), XRA_MASK, PPC64, PPCVLE, {FRT, FRB}},
6953 {"fctidz.", XRC(63,815,1), XRA_MASK, PPC476, PPCVLE, {FRT, FRB}},
6955 {"denbcdq", XRC(63,834,0), X_MASK, POWER6, PPCVLE, {S, FRTp, FRBp}},
6956 {"denbcdq.", XRC(63,834,1), X_MASK, POWER6, PPCVLE, {S, FRTp, FRBp}},
6958 {"xscvqpuwz", XVA(63,836,1), XVA_MASK, PPCVSX3, PPCVLE, {VD, VB}},
6959 {"xscvudqp", XVA(63,836,2), XVA_MASK, PPCVSX3, PPCVLE, {VD, VB}},
6960 {"xscvqpswz", XVA(63,836,9), XVA_MASK, PPCVSX3, PPCVLE, {VD, VB}},
6961 {"xscvsdqp", XVA(63,836,10), XVA_MASK, PPCVSX3, PPCVLE, {VD, VB}},
6962 {"xscvqpudz", XVA(63,836,17), XVA_MASK, PPCVSX3, PPCVLE, {VD, VB}},
6963 {"xscvqpdp", XVARC(63,836,20,0), XVA_MASK, PPCVSX3, PPCVLE, {VD, VB}},
6964 {"xscvqpdpo", XVARC(63,836,20,1), XVA_MASK, PPCVSX3, PPCVLE, {VD, VB}},
6965 {"xscvdpqp", XVA(63,836,22), XVA_MASK, PPCVSX3, PPCVLE, {VD, VB}},
6966 {"xscvqpsdz", XVA(63,836,25), XVA_MASK, PPCVSX3, PPCVLE, {VD, VB}},
6968 {"fmrgow", X(63,838), X_MASK, PPCVSX2, PPCVLE, {FRT, FRA, FRB}},
6970 {"fcfid", XRC(63,846,0), XRA_MASK, PPC64, PPCVLE, {FRT, FRB}},
6971 {"fcfid", XRC(63,846,0), XRA_MASK, PPC476, PPCVLE, {FRT, FRB}},
6972 {"fcfid.", XRC(63,846,1), XRA_MASK, PPC64, PPCVLE, {FRT, FRB}},
6973 {"fcfid.", XRC(63,846,1), XRA_MASK, PPC476, PPCVLE, {FRT, FRB}},
6975 {"diexq", XRC(63,866,0), X_MASK, POWER6, PPCVLE, {FRTp, FRA, FRBp}},
6976 {"diexq.", XRC(63,866,1), X_MASK, POWER6, PPCVLE, {FRTp, FRA, FRBp}},
6978 {"xsiexpqp", X(63,868), X_MASK, PPCVSX3, PPCVLE, {VD, VA, VB}},
6980 {"fctidu", XRC(63,942,0), XRA_MASK, POWER7|PPCA2, PPCVLE, {FRT, FRB}},
6981 {"fctidu.", XRC(63,942,1), XRA_MASK, POWER7|PPCA2, PPCVLE, {FRT, FRB}},
6983 {"fctiduz", XRC(63,943,0), XRA_MASK, POWER7|PPCA2, PPCVLE, {FRT, FRB}},
6984 {"fctiduz.", XRC(63,943,1), XRA_MASK, POWER7|PPCA2, PPCVLE, {FRT, FRB}},
6986 {"fmrgew", X(63,966), X_MASK, PPCVSX2, PPCVLE, {FRT, FRA, FRB}},
6988 {"fcfidu", XRC(63,974,0), XRA_MASK, POWER7|PPCA2, PPCVLE, {FRT, FRB}},
6989 {"fcfidu.", XRC(63,974,1), XRA_MASK, POWER7|PPCA2, PPCVLE, {FRT, FRB}},
6992 const int powerpc_num_opcodes =
6993 sizeof (powerpc_opcodes) / sizeof (powerpc_opcodes[0]);
6995 /* The VLE opcode table.
6997 The format of this opcode table is the same as the main opcode table. */
6999 const struct powerpc_opcode vle_opcodes[] = {
7000 {"se_illegal", C(0), C_MASK, PPCVLE, 0, {}},
7001 {"se_isync", C(1), C_MASK, PPCVLE, 0, {}},
7002 {"se_sc", C(2), C_MASK, PPCVLE, 0, {}},
7003 {"se_blr", C_LK(2,0), C_LK_MASK, PPCVLE, 0, {}},
7004 {"se_blrl", C_LK(2,1), C_LK_MASK, PPCVLE, 0, {}},
7005 {"se_bctr", C_LK(3,0), C_LK_MASK, PPCVLE, 0, {}},
7006 {"se_bctrl", C_LK(3,1), C_LK_MASK, PPCVLE, 0, {}},
7007 {"se_rfi", C(8), C_MASK, PPCVLE, 0, {}},
7008 {"se_rfci", C(9), C_MASK, PPCVLE, 0, {}},
7009 {"se_rfdi", C(10), C_MASK, PPCVLE, 0, {}},
7010 {"se_rfmci", C(11), C_MASK, PPCRFMCI|PPCVLE, 0, {}},
7011 {"se_not", SE_R(0,2), SE_R_MASK, PPCVLE, 0, {RX}},
7012 {"se_neg", SE_R(0,3), SE_R_MASK, PPCVLE, 0, {RX}},
7013 {"se_mflr", SE_R(0,8), SE_R_MASK, PPCVLE, 0, {RX}},
7014 {"se_mtlr", SE_R(0,9), SE_R_MASK, PPCVLE, 0, {RX}},
7015 {"se_mfctr", SE_R(0,10), SE_R_MASK, PPCVLE, 0, {RX}},
7016 {"se_mtctr", SE_R(0,11), SE_R_MASK, PPCVLE, 0, {RX}},
7017 {"se_extzb", SE_R(0,12), SE_R_MASK, PPCVLE, 0, {RX}},
7018 {"se_extsb", SE_R(0,13), SE_R_MASK, PPCVLE, 0, {RX}},
7019 {"se_extzh", SE_R(0,14), SE_R_MASK, PPCVLE, 0, {RX}},
7020 {"se_extsh", SE_R(0,15), SE_R_MASK, PPCVLE, 0, {RX}},
7021 {"se_mr", SE_RR(0,1), SE_RR_MASK, PPCVLE, 0, {RX, RY}},
7022 {"se_mtar", SE_RR(0,2), SE_RR_MASK, PPCVLE, 0, {ARX, RY}},
7023 {"se_mfar", SE_RR(0,3), SE_RR_MASK, PPCVLE, 0, {RX, ARY}},
7024 {"se_add", SE_RR(1,0), SE_RR_MASK, PPCVLE, 0, {RX, RY}},
7025 {"se_mullw", SE_RR(1,1), SE_RR_MASK, PPCVLE, 0, {RX, RY}},
7026 {"se_sub", SE_RR(1,2), SE_RR_MASK, PPCVLE, 0, {RX, RY}},
7027 {"se_subf", SE_RR(1,3), SE_RR_MASK, PPCVLE, 0, {RX, RY}},
7028 {"se_cmp", SE_RR(3,0), SE_RR_MASK, PPCVLE, 0, {RX, RY}},
7029 {"se_cmpl", SE_RR(3,1), SE_RR_MASK, PPCVLE, 0, {RX, RY}},
7030 {"se_cmph", SE_RR(3,2), SE_RR_MASK, PPCVLE, 0, {RX, RY}},
7031 {"se_cmphl", SE_RR(3,3), SE_RR_MASK, PPCVLE, 0, {RX, RY}},
7033 {"e_cmpi", SCI8BF(6,0,21), SCI8BF_MASK, PPCVLE, 0, {CRD32, RA, SCLSCI8}},
7034 {"e_cmpli", SCI8BF(6,1,21), SCI8BF_MASK, PPCVLE, 0, {CRD32, RA, SCLSCI8}},
7035 {"e_addi", SCI8(6,16), SCI8_MASK, PPCVLE, 0, {RT, RA, SCLSCI8}},
7036 {"e_subi", SCI8(6,16), SCI8_MASK, PPCVLE, 0, {RT, RA, SCLSCI8N}},
7037 {"e_addi.", SCI8(6,17), SCI8_MASK, PPCVLE, 0, {RT, RA, SCLSCI8}},
7038 {"e_addic", SCI8(6,18), SCI8_MASK, PPCVLE, 0, {RT, RA, SCLSCI8}},
7039 {"e_subic", SCI8(6,18), SCI8_MASK, PPCVLE, 0, {RT, RA, SCLSCI8N}},
7040 {"e_addic.", SCI8(6,19), SCI8_MASK, PPCVLE, 0, {RT, RA, SCLSCI8}},
7041 {"e_subic.", SCI8(6,19), SCI8_MASK, PPCVLE, 0, {RT, RA, SCLSCI8N}},
7042 {"e_mulli", SCI8(6,20), SCI8_MASK, PPCVLE, 0, {RT, RA, SCLSCI8}},
7043 {"e_subfic", SCI8(6,22), SCI8_MASK, PPCVLE, 0, {RT, RA, SCLSCI8}},
7044 {"e_subfic.", SCI8(6,23), SCI8_MASK, PPCVLE, 0, {RT, RA, SCLSCI8}},
7045 {"e_andi", SCI8(6,24), SCI8_MASK, PPCVLE, 0, {RA, RS, SCLSCI8}},
7046 {"e_andi.", SCI8(6,25), SCI8_MASK, PPCVLE, 0, {RA, RS, SCLSCI8}},
7047 {"e_nop", SCI8(6,26), 0xffffffff, PPCVLE, 0, {0}},
7048 {"e_ori", SCI8(6,26), SCI8_MASK, PPCVLE, 0, {RA, RS, SCLSCI8}},
7049 {"e_ori.", SCI8(6,27), SCI8_MASK, PPCVLE, 0, {RA, RS, SCLSCI8}},
7050 {"e_xori", SCI8(6,28), SCI8_MASK, PPCVLE, 0, {RA, RS, SCLSCI8}},
7051 {"e_xori.", SCI8(6,29), SCI8_MASK, PPCVLE, 0, {RA, RS, SCLSCI8}},
7052 {"e_lbzu", OPVUP(6,0), OPVUP_MASK, PPCVLE, 0, {RT, D8, RA0}},
7053 {"e_lhau", OPVUP(6,3), OPVUP_MASK, PPCVLE, 0, {RT, D8, RA0}},
7054 {"e_lhzu", OPVUP(6,1), OPVUP_MASK, PPCVLE, 0, {RT, D8, RA0}},
7055 {"e_lmw", OPVUP(6,8), OPVUP_MASK, PPCVLE, 0, {RT, D8, RA0}},
7056 {"e_lwzu", OPVUP(6,2), OPVUP_MASK, PPCVLE, 0, {RT, D8, RA0}},
7057 {"e_stbu", OPVUP(6,4), OPVUP_MASK, PPCVLE, 0, {RT, D8, RA0}},
7058 {"e_sthu", OPVUP(6,5), OPVUP_MASK, PPCVLE, 0, {RT, D8, RA0}},
7059 {"e_stwu", OPVUP(6,6), OPVUP_MASK, PPCVLE, 0, {RT, D8, RA0}},
7060 {"e_stmw", OPVUP(6,9), OPVUP_MASK, PPCVLE, 0, {RT, D8, RA0}},
7061 {"e_add16i", OP(7), OP_MASK, PPCVLE, 0, {RT, RA, SI}},
7062 {"e_la", OP(7), OP_MASK, PPCVLE, 0, {RT, D, RA0}},
7063 {"e_sub16i", OP(7), OP_MASK, PPCVLE, 0, {RT, RA, NSI}},
7065 {"se_addi", SE_IM5(8,0), SE_IM5_MASK, PPCVLE, 0, {RX, OIMM5}},
7066 {"se_cmpli", SE_IM5(8,1), SE_IM5_MASK, PPCVLE, 0, {RX, OIMM5}},
7067 {"se_subi", SE_IM5(9,0), SE_IM5_MASK, PPCVLE, 0, {RX, OIMM5}},
7068 {"se_subi.", SE_IM5(9,1), SE_IM5_MASK, PPCVLE, 0, {RX, OIMM5}},
7069 {"se_cmpi", SE_IM5(10,1), SE_IM5_MASK, PPCVLE, 0, {RX, UI5}},
7070 {"se_bmaski", SE_IM5(11,0), SE_IM5_MASK, PPCVLE, 0, {RX, UI5}},
7071 {"se_andi", SE_IM5(11,1), SE_IM5_MASK, PPCVLE, 0, {RX, UI5}},
7073 {"e_lbz", OP(12), OP_MASK, PPCVLE, 0, {RT, D, RA0}},
7074 {"e_stb", OP(13), OP_MASK, PPCVLE, 0, {RT, D, RA0}},
7075 {"e_lha", OP(14), OP_MASK, PPCVLE, 0, {RT, D, RA0}},
7077 {"se_srw", SE_RR(16,0), SE_RR_MASK, PPCVLE, 0, {RX, RY}},
7078 {"se_sraw", SE_RR(16,1), SE_RR_MASK, PPCVLE, 0, {RX, RY}},
7079 {"se_slw", SE_RR(16,2), SE_RR_MASK, PPCVLE, 0, {RX, RY}},
7080 {"se_nop", SE_RR(17,0), 0xffff, PPCVLE, 0, {0}},
7081 {"se_or", SE_RR(17,0), SE_RR_MASK, PPCVLE, 0, {RX, RY}},
7082 {"se_andc", SE_RR(17,1), SE_RR_MASK, PPCVLE, 0, {RX, RY}},
7083 {"se_and", SE_RR(17,2), SE_RR_MASK, PPCVLE, 0, {RX, RY}},
7084 {"se_and.", SE_RR(17,3), SE_RR_MASK, PPCVLE, 0, {RX, RY}},
7085 {"se_li", IM7(9), IM7_MASK, PPCVLE, 0, {RX, UI7}},
7087 {"e_lwz", OP(20), OP_MASK, PPCVLE, 0, {RT, D, RA0}},
7088 {"e_stw", OP(21), OP_MASK, PPCVLE, 0, {RT, D, RA0}},
7089 {"e_lhz", OP(22), OP_MASK, PPCVLE, 0, {RT, D, RA0}},
7090 {"e_sth", OP(23), OP_MASK, PPCVLE, 0, {RT, D, RA0}},
7092 {"se_bclri", SE_IM5(24,0), SE_IM5_MASK, PPCVLE, 0, {RX, UI5}},
7093 {"se_bgeni", SE_IM5(24,1), SE_IM5_MASK, PPCVLE, 0, {RX, UI5}},
7094 {"se_bseti", SE_IM5(25,0), SE_IM5_MASK, PPCVLE, 0, {RX, UI5}},
7095 {"se_btsti", SE_IM5(25,1), SE_IM5_MASK, PPCVLE, 0, {RX, UI5}},
7096 {"se_srwi", SE_IM5(26,0), SE_IM5_MASK, PPCVLE, 0, {RX, UI5}},
7097 {"se_srawi", SE_IM5(26,1), SE_IM5_MASK, PPCVLE, 0, {RX, UI5}},
7098 {"se_slwi", SE_IM5(27,0), SE_IM5_MASK, PPCVLE, 0, {RX, UI5}},
7100 {"e_lis", I16L(28,28), I16L_MASK, PPCVLE, 0, {RD, VLEUIMML}},
7101 {"e_and2is.", I16L(28,29), I16L_MASK, PPCVLE, 0, {RD, VLEUIMML}},
7102 {"e_or2is", I16L(28,26), I16L_MASK, PPCVLE, 0, {RD, VLEUIMML}},
7103 {"e_and2i.", I16L(28,25), I16L_MASK, PPCVLE, 0, {RD, VLEUIMML}},
7104 {"e_or2i", I16L(28,24), I16L_MASK, PPCVLE, 0, {RD, VLEUIMML}},
7105 {"e_cmphl16i", IA16(28,23), IA16_MASK, PPCVLE, 0, {RA, VLEUIMM}},
7106 {"e_cmph16i", IA16(28,22), IA16_MASK, PPCVLE, 0, {RA, VLESIMM}},
7107 {"e_cmpl16i", I16A(28,21), I16A_MASK, PPCVLE, 0, {RA, VLEUIMM}},
7108 {"e_cmplwi", I16A(28,21), I16A_MASK, PPCVLE, 0, {RA, VLESIMM}},
7109 {"e_mull2i", I16A(28,20), I16A_MASK, PPCVLE, 0, {RA, VLESIMM}},
7110 {"e_cmp16i", IA16(28,19), IA16_MASK, PPCVLE, 0, {RA, VLESIMM}},
7111 {"e_cmpwi", IA16(28,19), IA16_MASK, PPCVLE, 0, {RA, VLESIMM}},
7112 {"e_sub2is", I16A(28,18), I16A_MASK, PPCVLE, 0, {RA, VLENSIMM}},
7113 {"e_add2is", I16A(28,18), I16A_MASK, PPCVLE, 0, {RA, VLESIMM}},
7114 {"e_sub2i.", I16A(28,17), I16A_MASK, PPCVLE, 0, {RA, VLENSIMM}},
7115 {"e_add2i.", I16A(28,17), I16A_MASK, PPCVLE, 0, {RA, VLESIMM}},
7116 {"e_li", LI20(28,0), LI20_MASK, PPCVLE, 0, {RT, IMM20}},
7117 {"e_rlwimi", M(29,0), M_MASK, PPCVLE, 0, {RA, RS, SH, MB, ME}},
7118 {"e_rlwinm", M(29,1), M_MASK, PPCVLE, 0, {RA, RT, SH, MBE, ME}},
7119 {"e_b", BD24(30,0,0), BD24_MASK, PPCVLE, 0, {B24}},
7120 {"e_bl", BD24(30,0,1), BD24_MASK, PPCVLE, 0, {B24}},
7121 {"e_bdnz", EBD15(30,8,BO32DNZ,0), EBD15_MASK, PPCVLE, 0, {B15}},
7122 {"e_bdnzl", EBD15(30,8,BO32DNZ,1), EBD15_MASK, PPCVLE, 0, {B15}},
7123 {"e_bdz", EBD15(30,8,BO32DZ,0), EBD15_MASK, PPCVLE, 0, {B15}},
7124 {"e_bdzl", EBD15(30,8,BO32DZ,1), EBD15_MASK, PPCVLE, 0, {B15}},
7125 {"e_bge", EBD15BI(30,8,BO32F,CBLT,0), EBD15BI_MASK, PPCVLE, 0, {CRS,B15}},
7126 {"e_bgel", EBD15BI(30,8,BO32F,CBLT,1), EBD15BI_MASK, PPCVLE, 0, {CRS,B15}},
7127 {"e_bnl", EBD15BI(30,8,BO32F,CBLT,0), EBD15BI_MASK, PPCVLE, 0, {CRS,B15}},
7128 {"e_bnll", EBD15BI(30,8,BO32F,CBLT,1), EBD15BI_MASK, PPCVLE, 0, {CRS,B15}},
7129 {"e_blt", EBD15BI(30,8,BO32T,CBLT,0), EBD15BI_MASK, PPCVLE, 0, {CRS,B15}},
7130 {"e_bltl", EBD15BI(30,8,BO32T,CBLT,1), EBD15BI_MASK, PPCVLE, 0, {CRS,B15}},
7131 {"e_bgt", EBD15BI(30,8,BO32T,CBGT,0), EBD15BI_MASK, PPCVLE, 0, {CRS,B15}},
7132 {"e_bgtl", EBD15BI(30,8,BO32T,CBGT,1), EBD15BI_MASK, PPCVLE, 0, {CRS,B15}},
7133 {"e_ble", EBD15BI(30,8,BO32F,CBGT,0), EBD15BI_MASK, PPCVLE, 0, {CRS,B15}},
7134 {"e_blel", EBD15BI(30,8,BO32F,CBGT,1), EBD15BI_MASK, PPCVLE, 0, {CRS,B15}},
7135 {"e_bng", EBD15BI(30,8,BO32F,CBGT,0), EBD15BI_MASK, PPCVLE, 0, {CRS,B15}},
7136 {"e_bngl", EBD15BI(30,8,BO32F,CBGT,1), EBD15BI_MASK, PPCVLE, 0, {CRS,B15}},
7137 {"e_bne", EBD15BI(30,8,BO32F,CBEQ,0), EBD15BI_MASK, PPCVLE, 0, {CRS,B15}},
7138 {"e_bnel", EBD15BI(30,8,BO32F,CBEQ,1), EBD15BI_MASK, PPCVLE, 0, {CRS,B15}},
7139 {"e_beq", EBD15BI(30,8,BO32T,CBEQ,0), EBD15BI_MASK, PPCVLE, 0, {CRS,B15}},
7140 {"e_beql", EBD15BI(30,8,BO32T,CBEQ,1), EBD15BI_MASK, PPCVLE, 0, {CRS,B15}},
7141 {"e_bso", EBD15BI(30,8,BO32T,CBSO,0), EBD15BI_MASK, PPCVLE, 0, {CRS,B15}},
7142 {"e_bsol", EBD15BI(30,8,BO32T,CBSO,1), EBD15BI_MASK, PPCVLE, 0, {CRS,B15}},
7143 {"e_bun", EBD15BI(30,8,BO32T,CBSO,0), EBD15BI_MASK, PPCVLE, 0, {CRS,B15}},
7144 {"e_bunl", EBD15BI(30,8,BO32T,CBSO,1), EBD15BI_MASK, PPCVLE, 0, {CRS,B15}},
7145 {"e_bns", EBD15BI(30,8,BO32F,CBSO,0), EBD15BI_MASK, PPCVLE, 0, {CRS,B15}},
7146 {"e_bnsl", EBD15BI(30,8,BO32F,CBSO,1), EBD15BI_MASK, PPCVLE, 0, {CRS,B15}},
7147 {"e_bnu", EBD15BI(30,8,BO32F,CBSO,0), EBD15BI_MASK, PPCVLE, 0, {CRS,B15}},
7148 {"e_bnul", EBD15BI(30,8,BO32F,CBSO,1), EBD15BI_MASK, PPCVLE, 0, {CRS,B15}},
7149 {"e_bc", BD15(30,8,0), BD15_MASK, PPCVLE, 0, {BO32, BI32, B15}},
7150 {"e_bcl", BD15(30,8,1), BD15_MASK, PPCVLE, 0, {BO32, BI32, B15}},
7152 {"e_bf", EBD15(30,8,BO32F,0), EBD15_MASK, PPCVLE, 0, {BI32,B15}},
7153 {"e_bfl", EBD15(30,8,BO32F,1), EBD15_MASK, PPCVLE, 0, {BI32,B15}},
7154 {"e_bt", EBD15(30,8,BO32T,0), EBD15_MASK, PPCVLE, 0, {BI32,B15}},
7155 {"e_btl", EBD15(30,8,BO32T,1), EBD15_MASK, PPCVLE, 0, {BI32,B15}},
7157 {"e_cmph", X(31,14), X_MASK, PPCVLE, 0, {CRD, RA, RB}},
7158 {"e_cmphl", X(31,46), X_MASK, PPCVLE, 0, {CRD, RA, RB}},
7159 {"e_crandc", XL(31,129), XL_MASK, PPCVLE, 0, {BT, BA, BB}},
7160 {"e_crnand", XL(31,225), XL_MASK, PPCVLE, 0, {BT, BA, BB}},
7161 {"e_crnot", XL(31,33), XL_MASK, PPCVLE, 0, {BT, BA, BBA}},
7162 {"e_crnor", XL(31,33), XL_MASK, PPCVLE, 0, {BT, BA, BB}},
7163 {"e_crclr", XL(31,193), XL_MASK, PPCVLE, 0, {BT, BAT, BBA}},
7164 {"e_crxor", XL(31,193), XL_MASK, PPCVLE, 0, {BT, BA, BB}},
7165 {"e_mcrf", XL(31,16), XL_MASK, PPCVLE, 0, {CRD, CR}},
7166 {"e_slwi", EX(31,112), EX_MASK, PPCVLE, 0, {RA, RS, SH}},
7167 {"e_slwi.", EX(31,113), EX_MASK, PPCVLE, 0, {RA, RS, SH}},
7169 {"e_crand", XL(31,257), XL_MASK, PPCVLE, 0, {BT, BA, BB}},
7171 {"e_rlw", EX(31,560), EX_MASK, PPCVLE, 0, {RA, RS, RB}},
7172 {"e_rlw.", EX(31,561), EX_MASK, PPCVLE, 0, {RA, RS, RB}},
7174 {"e_crset", XL(31,289), XL_MASK, PPCVLE, 0, {BT, BAT, BBA}},
7175 {"e_creqv", XL(31,289), XL_MASK, PPCVLE, 0, {BT, BA, BB}},
7177 {"e_rlwi", EX(31,624), EX_MASK, PPCVLE, 0, {RA, RS, SH}},
7178 {"e_rlwi.", EX(31,625), EX_MASK, PPCVLE, 0, {RA, RS, SH}},
7180 {"e_crorc", XL(31,417), XL_MASK, PPCVLE, 0, {BT, BA, BB}},
7182 {"e_crmove", XL(31,449), XL_MASK, PPCVLE, 0, {BT, BA, BBA}},
7183 {"e_cror", XL(31,449), XL_MASK, PPCVLE, 0, {BT, BA, BB}},
7185 {"mtmas1", XSPR(31,467,625), XSPR_MASK, PPCVLE, 0, {RS}},
7187 {"e_srwi", EX(31,1136), EX_MASK, PPCVLE, 0, {RA, RS, SH}},
7188 {"e_srwi.", EX(31,1137), EX_MASK, PPCVLE, 0, {RA, RS, SH}},
7190 {"se_lbz", SD4(8), SD4_MASK, PPCVLE, 0, {RZ, SE_SD, RX}},
7192 {"se_stb", SD4(9), SD4_MASK, PPCVLE, 0, {RZ, SE_SD, RX}},
7194 {"se_lhz", SD4(10), SD4_MASK, PPCVLE, 0, {RZ, SE_SDH, RX}},
7196 {"se_sth", SD4(11), SD4_MASK, PPCVLE, 0, {RZ, SE_SDH, RX}},
7198 {"se_lwz", SD4(12), SD4_MASK, PPCVLE, 0, {RZ, SE_SDW, RX}},
7200 {"se_stw", SD4(13), SD4_MASK, PPCVLE, 0, {RZ, SE_SDW, RX}},
7202 {"se_bge", EBD8IO(28,0,0), EBD8IO3_MASK, PPCVLE, 0, {B8}},
7203 {"se_bnl", EBD8IO(28,0,0), EBD8IO3_MASK, PPCVLE, 0, {B8}},
7204 {"se_ble", EBD8IO(28,0,1), EBD8IO3_MASK, PPCVLE, 0, {B8}},
7205 {"se_bng", EBD8IO(28,0,1), EBD8IO3_MASK, PPCVLE, 0, {B8}},
7206 {"se_bne", EBD8IO(28,0,2), EBD8IO3_MASK, PPCVLE, 0, {B8}},
7207 {"se_bns", EBD8IO(28,0,3), EBD8IO3_MASK, PPCVLE, 0, {B8}},
7208 {"se_bnu", EBD8IO(28,0,3), EBD8IO3_MASK, PPCVLE, 0, {B8}},
7209 {"se_bf", EBD8IO(28,0,0), EBD8IO2_MASK, PPCVLE, 0, {BI16, B8}},
7210 {"se_blt", EBD8IO(28,1,0), EBD8IO3_MASK, PPCVLE, 0, {B8}},
7211 {"se_bgt", EBD8IO(28,1,1), EBD8IO3_MASK, PPCVLE, 0, {B8}},
7212 {"se_beq", EBD8IO(28,1,2), EBD8IO3_MASK, PPCVLE, 0, {B8}},
7213 {"se_bso", EBD8IO(28,1,3), EBD8IO3_MASK, PPCVLE, 0, {B8}},
7214 {"se_bun", EBD8IO(28,1,3), EBD8IO3_MASK, PPCVLE, 0, {B8}},
7215 {"se_bt", EBD8IO(28,1,0), EBD8IO2_MASK, PPCVLE, 0, {BI16, B8}},
7216 {"se_bc", BD8IO(28), BD8IO_MASK, PPCVLE, 0, {BO16, BI16, B8}},
7217 {"se_b", BD8(58,0,0), BD8_MASK, PPCVLE, 0, {B8}},
7218 {"se_bl", BD8(58,0,1), BD8_MASK, PPCVLE, 0, {B8}},
7221 const int vle_num_opcodes =
7222 sizeof (vle_opcodes) / sizeof (vle_opcodes[0]);
7224 /* The macro table. This is only used by the assembler. */
7226 /* The expressions of the form (-x ! 31) & (x | 31) have the value 0
7227 when x=0; 32-x when x is between 1 and 31; are negative if x is
7228 negative; and are 32 or more otherwise. This is what you want
7229 when, for instance, you are emulating a right shift by a
7230 rotate-left-and-mask, because the underlying instructions support
7231 shifts of size 0 but not shifts of size 32. By comparison, when
7232 extracting x bits from some word you want to use just 32-x, because
7233 the underlying instructions don't support extracting 0 bits but do
7234 support extracting the whole word (32 bits in this case). */
7236 const struct powerpc_macro powerpc_macros[] = {
7237 {"extldi", 4, PPC64, "rldicr %0,%1,%3,(%2)-1"},
7238 {"extldi.", 4, PPC64, "rldicr. %0,%1,%3,(%2)-1"},
7239 {"extrdi", 4, PPC64, "rldicl %0,%1,((%2)+(%3))&((%2)+(%3)<>64),64-(%2)"},
7240 {"extrdi.", 4, PPC64, "rldicl. %0,%1,((%2)+(%3))&((%2)+(%3)<>64),64-(%2)"},
7241 {"insrdi", 4, PPC64, "rldimi %0,%1,64-((%2)+(%3)),%3"},
7242 {"insrdi.", 4, PPC64, "rldimi. %0,%1,64-((%2)+(%3)),%3"},
7243 {"rotrdi", 3, PPC64, "rldicl %0,%1,(-(%2)!63)&((%2)|63),0"},
7244 {"rotrdi.", 3, PPC64, "rldicl. %0,%1,(-(%2)!63)&((%2)|63),0"},
7245 {"sldi", 3, PPC64, "rldicr %0,%1,%2,63-(%2)"},
7246 {"sldi.", 3, PPC64, "rldicr. %0,%1,%2,63-(%2)"},
7247 {"srdi", 3, PPC64, "rldicl %0,%1,(-(%2)!63)&((%2)|63),%2"},
7248 {"srdi.", 3, PPC64, "rldicl. %0,%1,(-(%2)!63)&((%2)|63),%2"},
7249 {"clrrdi", 3, PPC64, "rldicr %0,%1,0,63-(%2)"},
7250 {"clrrdi.", 3, PPC64, "rldicr. %0,%1,0,63-(%2)"},
7251 {"clrlsldi", 4, PPC64, "rldic %0,%1,%3,(%2)-(%3)"},
7252 {"clrlsldi.",4, PPC64, "rldic. %0,%1,%3,(%2)-(%3)"},
7254 {"extlwi", 4, PPCCOM, "rlwinm %0,%1,%3,0,(%2)-1"},
7255 {"extlwi.", 4, PPCCOM, "rlwinm. %0,%1,%3,0,(%2)-1"},
7256 {"extrwi", 4, PPCCOM, "rlwinm %0,%1,((%2)+(%3))&((%2)+(%3)<>32),32-(%2),31"},
7257 {"extrwi.", 4, PPCCOM, "rlwinm. %0,%1,((%2)+(%3))&((%2)+(%3)<>32),32-(%2),31"},
7258 {"inslwi", 4, PPCCOM, "rlwimi %0,%1,(-(%3)!31)&((%3)|31),%3,(%2)+(%3)-1"},
7259 {"inslwi.", 4, PPCCOM, "rlwimi. %0,%1,(-(%3)!31)&((%3)|31),%3,(%2)+(%3)-1"},
7260 {"insrwi", 4, PPCCOM, "rlwimi %0,%1,32-((%2)+(%3)),%3,(%2)+(%3)-1"},
7261 {"insrwi.", 4, PPCCOM, "rlwimi. %0,%1,32-((%2)+(%3)),%3,(%2)+(%3)-1"},
7262 {"rotrwi", 3, PPCCOM, "rlwinm %0,%1,(-(%2)!31)&((%2)|31),0,31"},
7263 {"rotrwi.", 3, PPCCOM, "rlwinm. %0,%1,(-(%2)!31)&((%2)|31),0,31"},
7264 {"slwi", 3, PPCCOM, "rlwinm %0,%1,%2,0,31-(%2)"},
7265 {"sli", 3, PWRCOM, "rlinm %0,%1,%2,0,31-(%2)"},
7266 {"slwi.", 3, PPCCOM, "rlwinm. %0,%1,%2,0,31-(%2)"},
7267 {"sli.", 3, PWRCOM, "rlinm. %0,%1,%2,0,31-(%2)"},
7268 {"srwi", 3, PPCCOM, "rlwinm %0,%1,(-(%2)!31)&((%2)|31),%2,31"},
7269 {"sri", 3, PWRCOM, "rlinm %0,%1,(-(%2)!31)&((%2)|31),%2,31"},
7270 {"srwi.", 3, PPCCOM, "rlwinm. %0,%1,(-(%2)!31)&((%2)|31),%2,31"},
7271 {"sri.", 3, PWRCOM, "rlinm. %0,%1,(-(%2)!31)&((%2)|31),%2,31"},
7272 {"clrrwi", 3, PPCCOM, "rlwinm %0,%1,0,0,31-(%2)"},
7273 {"clrrwi.", 3, PPCCOM, "rlwinm. %0,%1,0,0,31-(%2)"},
7274 {"clrlslwi", 4, PPCCOM, "rlwinm %0,%1,%3,(%2)-(%3),31-(%3)"},
7275 {"clrlslwi.",4, PPCCOM, "rlwinm. %0,%1,%3,(%2)-(%3),31-(%3)"},
7277 {"e_extlwi", 4, PPCVLE, "e_rlwinm %0,%1,%3,0,(%2)-1"},
7278 {"e_extrwi", 4, PPCVLE, "e_rlwinm %0,%1,((%2)+(%3))&((%2)+(%3)<>32),32-(%2),31"},
7279 {"e_inslwi", 4, PPCVLE, "e_rlwimi %0,%1,(-(%3)!31)&((%3)|31),%3,(%2)+(%3)-1"},
7280 {"e_insrwi", 4, PPCVLE, "e_rlwimi %0,%1,32-((%2)+(%3)),%3,(%2)+(%3)-1"},
7281 {"e_rotlwi", 3, PPCVLE, "e_rlwinm %0,%1,%2,0,31"},
7282 {"e_rotrwi", 3, PPCVLE, "e_rlwinm %0,%1,(-(%2)!31)&((%2)|31),0,31"},
7283 {"e_slwi", 3, PPCVLE, "e_rlwinm %0,%1,%2,0,31-(%2)"},
7284 {"e_srwi", 3, PPCVLE, "e_rlwinm %0,%1,(-(%2)!31)&((%2)|31),%2,31"},
7285 {"e_clrlwi", 3, PPCVLE, "e_rlwinm %0,%1,0,%2,31"},
7286 {"e_clrrwi", 3, PPCVLE, "e_rlwinm %0,%1,0,0,31-(%2)"},
7287 {"e_clrlslwi",4, PPCVLE, "e_rlwinm %0,%1,%3,(%2)-(%3),31-(%3)"},
7290 const int powerpc_num_macros =
7291 sizeof (powerpc_macros) / sizeof (powerpc_macros[0]);