1 /* ppc-opc.c -- PowerPC opcode list
2 Copyright 1994, 1995, 1996, 1997, 1998, 2000, 2001, 2002, 2003, 2004
3 Free Software Foundation, Inc.
4 Written by Ian Lance Taylor, Cygnus Support
6 This file is part of GDB, GAS, and the GNU binutils.
8 GDB, GAS, and the GNU binutils are free software; you can redistribute
9 them and/or modify them under the terms of the GNU General Public
10 License as published by the Free Software Foundation; either version
11 2, or (at your option) any later version.
13 GDB, GAS, and the GNU binutils are distributed in the hope that they
14 will be useful, but WITHOUT ANY WARRANTY; without even the implied
15 warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See
16 the GNU General Public License for more details.
18 You should have received a copy of the GNU General Public License
19 along with this file; see the file COPYING. If not, write to the Free
20 Software Foundation, 59 Temple Place - Suite 330, Boston, MA
25 #include "opcode/ppc.h"
28 /* This file holds the PowerPC opcode table. The opcode table
29 includes almost all of the extended instruction mnemonics. This
30 permits the disassembler to use them, and simplifies the assembler
31 logic, at the cost of increasing the table size. The table is
32 strictly constant data, so the compiler should be able to put it in
35 This file also holds the operand table. All knowledge about
36 inserting operands into instructions and vice-versa is kept in this
39 /* Local insertion and extraction functions. */
41 static unsigned long insert_bat (unsigned long, long, int, const char **);
42 static long extract_bat (unsigned long, int, int *);
43 static unsigned long insert_bba (unsigned long, long, int, const char **);
44 static long extract_bba (unsigned long, int, int *);
45 static unsigned long insert_bd (unsigned long, long, int, const char **);
46 static long extract_bd (unsigned long, int, int *);
47 static unsigned long insert_bdm (unsigned long, long, int, const char **);
48 static long extract_bdm (unsigned long, int, int *);
49 static unsigned long insert_bdp (unsigned long, long, int, const char **);
50 static long extract_bdp (unsigned long, int, int *);
51 static unsigned long insert_bo (unsigned long, long, int, const char **);
52 static long extract_bo (unsigned long, int, int *);
53 static unsigned long insert_boe (unsigned long, long, int, const char **);
54 static long extract_boe (unsigned long, int, int *);
55 static unsigned long insert_dq (unsigned long, long, int, const char **);
56 static long extract_dq (unsigned long, int, int *);
57 static unsigned long insert_ds (unsigned long, long, int, const char **);
58 static long extract_ds (unsigned long, int, int *);
59 static unsigned long insert_de (unsigned long, long, int, const char **);
60 static long extract_de (unsigned long, int, int *);
61 static unsigned long insert_des (unsigned long, long, int, const char **);
62 static long extract_des (unsigned long, int, int *);
63 static unsigned long insert_fxm (unsigned long, long, int, const char **);
64 static long extract_fxm (unsigned long, int, int *);
65 static unsigned long insert_li (unsigned long, long, int, const char **);
66 static long extract_li (unsigned long, int, int *);
67 static unsigned long insert_mbe (unsigned long, long, int, const char **);
68 static long extract_mbe (unsigned long, int, int *);
69 static unsigned long insert_mb6 (unsigned long, long, int, const char **);
70 static long extract_mb6 (unsigned long, int, int *);
71 static unsigned long insert_nb (unsigned long, long, int, const char **);
72 static long extract_nb (unsigned long, int, int *);
73 static unsigned long insert_nsi (unsigned long, long, int, const char **);
74 static long extract_nsi (unsigned long, int, int *);
75 static unsigned long insert_ral (unsigned long, long, int, const char **);
76 static unsigned long insert_ram (unsigned long, long, int, const char **);
77 static unsigned long insert_raq (unsigned long, long, int, const char **);
78 static unsigned long insert_ras (unsigned long, long, int, const char **);
79 static unsigned long insert_rbs (unsigned long, long, int, const char **);
80 static long extract_rbs (unsigned long, int, int *);
81 static unsigned long insert_rsq (unsigned long, long, int, const char **);
82 static unsigned long insert_rtq (unsigned long, long, int, const char **);
83 static unsigned long insert_sh6 (unsigned long, long, int, const char **);
84 static long extract_sh6 (unsigned long, int, int *);
85 static unsigned long insert_spr (unsigned long, long, int, const char **);
86 static long extract_spr (unsigned long, int, int *);
87 static unsigned long insert_tbr (unsigned long, long, int, const char **);
88 static long extract_tbr (unsigned long, int, int *);
89 static unsigned long insert_ev2 (unsigned long, long, int, const char **);
90 static long extract_ev2 (unsigned long, int, int *);
91 static unsigned long insert_ev4 (unsigned long, long, int, const char **);
92 static long extract_ev4 (unsigned long, int, int *);
93 static unsigned long insert_ev8 (unsigned long, long, int, const char **);
94 static long extract_ev8 (unsigned long, int, int *);
96 /* The operands table.
98 The fields are bits, shift, insert, extract, flags.
100 We used to put parens around the various additions, like the one
101 for BA just below. However, that caused trouble with feeble
102 compilers with a limit on depth of a parenthesized expression, like
103 (reportedly) the compiler in Microsoft Developer Studio 5. So we
104 omit the parens, since the macros are never used in a context where
105 the addition will be ambiguous. */
107 const struct powerpc_operand powerpc_operands[] =
109 /* The zero index is used to indicate the end of the list of
114 /* The BA field in an XL form instruction. */
115 #define BA UNUSED + 1
116 #define BA_MASK (0x1f << 16)
117 { 5, 16, 0, 0, PPC_OPERAND_CR },
119 /* The BA field in an XL form instruction when it must be the same
120 as the BT field in the same instruction. */
122 { 5, 16, insert_bat, extract_bat, PPC_OPERAND_FAKE },
124 /* The BB field in an XL form instruction. */
126 #define BB_MASK (0x1f << 11)
127 { 5, 11, 0, 0, PPC_OPERAND_CR },
129 /* The BB field in an XL form instruction when it must be the same
130 as the BA field in the same instruction. */
132 { 5, 11, insert_bba, extract_bba, PPC_OPERAND_FAKE },
134 /* The BD field in a B form instruction. The lower two bits are
137 { 16, 0, insert_bd, extract_bd, PPC_OPERAND_RELATIVE | PPC_OPERAND_SIGNED },
139 /* The BD field in a B form instruction when absolute addressing is
142 { 16, 0, insert_bd, extract_bd, PPC_OPERAND_ABSOLUTE | PPC_OPERAND_SIGNED },
144 /* The BD field in a B form instruction when the - modifier is used.
145 This sets the y bit of the BO field appropriately. */
147 { 16, 0, insert_bdm, extract_bdm,
148 PPC_OPERAND_RELATIVE | PPC_OPERAND_SIGNED },
150 /* The BD field in a B form instruction when the - modifier is used
151 and absolute address is used. */
153 { 16, 0, insert_bdm, extract_bdm,
154 PPC_OPERAND_ABSOLUTE | PPC_OPERAND_SIGNED },
156 /* The BD field in a B form instruction when the + modifier is used.
157 This sets the y bit of the BO field appropriately. */
159 { 16, 0, insert_bdp, extract_bdp,
160 PPC_OPERAND_RELATIVE | PPC_OPERAND_SIGNED },
162 /* The BD field in a B form instruction when the + modifier is used
163 and absolute addressing is used. */
165 { 16, 0, insert_bdp, extract_bdp,
166 PPC_OPERAND_ABSOLUTE | PPC_OPERAND_SIGNED },
168 /* The BF field in an X or XL form instruction. */
170 { 3, 23, 0, 0, PPC_OPERAND_CR },
172 /* An optional BF field. This is used for comparison instructions,
173 in which an omitted BF field is taken as zero. */
175 { 3, 23, 0, 0, PPC_OPERAND_CR | PPC_OPERAND_OPTIONAL },
177 /* The BFA field in an X or XL form instruction. */
179 { 3, 18, 0, 0, PPC_OPERAND_CR },
181 /* The BI field in a B form or XL form instruction. */
183 #define BI_MASK (0x1f << 16)
184 { 5, 16, 0, 0, PPC_OPERAND_CR },
186 /* The BO field in a B form instruction. Certain values are
189 #define BO_MASK (0x1f << 21)
190 { 5, 21, insert_bo, extract_bo, 0 },
192 /* The BO field in a B form instruction when the + or - modifier is
193 used. This is like the BO field, but it must be even. */
195 { 5, 21, insert_boe, extract_boe, 0 },
197 /* The BT field in an X or XL form instruction. */
199 { 5, 21, 0, 0, PPC_OPERAND_CR },
201 /* The condition register number portion of the BI field in a B form
202 or XL form instruction. This is used for the extended
203 conditional branch mnemonics, which set the lower two bits of the
204 BI field. This field is optional. */
206 { 3, 18, 0, 0, PPC_OPERAND_CR | PPC_OPERAND_OPTIONAL },
208 /* The CRB field in an X form instruction. */
212 /* The CRFD field in an X form instruction. */
214 { 3, 23, 0, 0, PPC_OPERAND_CR },
216 /* The CRFS field in an X form instruction. */
217 #define CRFS CRFD + 1
218 { 3, 0, 0, 0, PPC_OPERAND_CR },
220 /* The CT field in an X form instruction. */
222 { 5, 21, 0, 0, PPC_OPERAND_OPTIONAL },
224 /* The D field in a D form instruction. This is a displacement off
225 a register, and implies that the next operand is a register in
228 { 16, 0, 0, 0, PPC_OPERAND_PARENS | PPC_OPERAND_SIGNED },
230 /* The DE field in a DE form instruction. This is like D, but is 12
233 { 14, 0, insert_de, extract_de, PPC_OPERAND_PARENS },
235 /* The DES field in a DES form instruction. This is like DS, but is 14
236 bits only (12 stored.) */
238 { 14, 0, insert_des, extract_des, PPC_OPERAND_PARENS | PPC_OPERAND_SIGNED },
240 /* The DQ field in a DQ form instruction. This is like D, but the
241 lower four bits are forced to zero. */
243 { 16, 0, insert_dq, extract_dq,
244 PPC_OPERAND_PARENS | PPC_OPERAND_SIGNED | PPC_OPERAND_DQ },
246 /* The DS field in a DS form instruction. This is like D, but the
247 lower two bits are forced to zero. */
249 { 16, 0, insert_ds, extract_ds,
250 PPC_OPERAND_PARENS | PPC_OPERAND_SIGNED | PPC_OPERAND_DS },
252 /* The E field in a wrteei instruction. */
256 /* The FL1 field in a POWER SC form instruction. */
260 /* The FL2 field in a POWER SC form instruction. */
264 /* The FLM field in an XFL form instruction. */
268 /* The FRA field in an X or A form instruction. */
270 #define FRA_MASK (0x1f << 16)
271 { 5, 16, 0, 0, PPC_OPERAND_FPR },
273 /* The FRB field in an X or A form instruction. */
275 #define FRB_MASK (0x1f << 11)
276 { 5, 11, 0, 0, PPC_OPERAND_FPR },
278 /* The FRC field in an A form instruction. */
280 #define FRC_MASK (0x1f << 6)
281 { 5, 6, 0, 0, PPC_OPERAND_FPR },
283 /* The FRS field in an X form instruction or the FRT field in a D, X
284 or A form instruction. */
287 { 5, 21, 0, 0, PPC_OPERAND_FPR },
289 /* The FXM field in an XFX instruction. */
291 #define FXM_MASK (0xff << 12)
292 { 8, 12, insert_fxm, extract_fxm, 0 },
294 /* Power4 version for mfcr. */
296 { 8, 12, insert_fxm, extract_fxm, PPC_OPERAND_OPTIONAL },
298 /* The L field in a D or X form instruction. */
300 { 1, 21, 0, 0, PPC_OPERAND_OPTIONAL },
302 /* The LEV field in a POWER SC form instruction. */
306 /* The LI field in an I form instruction. The lower two bits are
309 { 26, 0, insert_li, extract_li, PPC_OPERAND_RELATIVE | PPC_OPERAND_SIGNED },
311 /* The LI field in an I form instruction when used as an absolute
314 { 26, 0, insert_li, extract_li, PPC_OPERAND_ABSOLUTE | PPC_OPERAND_SIGNED },
316 /* The LS field in an X (sync) form instruction. */
318 { 2, 21, 0, 0, PPC_OPERAND_OPTIONAL },
320 /* The MB field in an M form instruction. */
322 #define MB_MASK (0x1f << 6)
325 /* The ME field in an M form instruction. */
327 #define ME_MASK (0x1f << 1)
330 /* The MB and ME fields in an M form instruction expressed a single
331 operand which is a bitmask indicating which bits to select. This
332 is a two operand form using PPC_OPERAND_NEXT. See the
333 description in opcode/ppc.h for what this means. */
335 { 5, 6, 0, 0, PPC_OPERAND_OPTIONAL | PPC_OPERAND_NEXT },
336 { 32, 0, insert_mbe, extract_mbe, 0 },
338 /* The MB or ME field in an MD or MDS form instruction. The high
339 bit is wrapped to the low end. */
342 #define MB6_MASK (0x3f << 5)
343 { 6, 5, insert_mb6, extract_mb6, 0 },
345 /* The MO field in an mbar instruction. */
347 { 5, 21, 0, 0, PPC_OPERAND_OPTIONAL },
349 /* The NB field in an X form instruction. The value 32 is stored as
352 { 6, 11, insert_nb, extract_nb, 0 },
354 /* The NSI field in a D form instruction. This is the same as the
355 SI field, only negated. */
357 { 16, 0, insert_nsi, extract_nsi,
358 PPC_OPERAND_NEGATIVE | PPC_OPERAND_SIGNED },
360 /* The RA field in an D, DS, DQ, X, XO, M, or MDS form instruction. */
362 #define RA_MASK (0x1f << 16)
363 { 5, 16, 0, 0, PPC_OPERAND_GPR },
365 /* As above, but 0 in the RA field means zero, not r0. */
367 { 5, 16, 0, 0, PPC_OPERAND_GPR_0 },
369 /* The RA field in the DQ form lq instruction, which has special
370 value restrictions. */
372 { 5, 16, insert_raq, 0, PPC_OPERAND_GPR_0 },
374 /* The RA field in a D or X form instruction which is an updating
375 load, which means that the RA field may not be zero and may not
376 equal the RT field. */
378 { 5, 16, insert_ral, 0, PPC_OPERAND_GPR_0 },
380 /* The RA field in an lmw instruction, which has special value
383 { 5, 16, insert_ram, 0, PPC_OPERAND_GPR_0 },
385 /* The RA field in a D or X form instruction which is an updating
386 store or an updating floating point load, which means that the RA
387 field may not be zero. */
389 { 5, 16, insert_ras, 0, PPC_OPERAND_GPR_0 },
391 /* The RA field of the tlbwe instruction, which is optional. */
392 #define RAOPT RAS + 1
393 { 5, 16, 0, 0, PPC_OPERAND_GPR | PPC_OPERAND_OPTIONAL },
395 /* The RB field in an X, XO, M, or MDS form instruction. */
397 #define RB_MASK (0x1f << 11)
398 { 5, 11, 0, 0, PPC_OPERAND_GPR },
400 /* The RB field in an X form instruction when it must be the same as
401 the RS field in the instruction. This is used for extended
402 mnemonics like mr. */
404 { 5, 1, insert_rbs, extract_rbs, PPC_OPERAND_FAKE },
406 /* The RS field in a D, DS, X, XFX, XS, M, MD or MDS form
407 instruction or the RT field in a D, DS, X, XFX or XO form
411 #define RT_MASK (0x1f << 21)
412 { 5, 21, 0, 0, PPC_OPERAND_GPR },
414 /* The RS field of the DS form stq instruction, which has special
415 value restrictions. */
417 { 5, 21, insert_rsq, 0, PPC_OPERAND_GPR_0 },
419 /* The RT field of the DQ form lq instruction, which has special
420 value restrictions. */
422 { 5, 21, insert_rtq, 0, PPC_OPERAND_GPR_0 },
424 /* The RS field of the tlbwe instruction, which is optional. */
426 { 5, 21, 0, 0, PPC_OPERAND_GPR | PPC_OPERAND_OPTIONAL },
428 /* The SH field in an X or M form instruction. */
430 #define SH_MASK (0x1f << 11)
433 /* The SH field in an MD form instruction. This is split. */
435 #define SH6_MASK ((0x1f << 11) | (1 << 1))
436 { 6, 1, insert_sh6, extract_sh6, 0 },
438 /* The SH field of the tlbwe instruction, which is optional. */
440 { 5, 11,0, 0, PPC_OPERAND_OPTIONAL },
442 /* The SI field in a D form instruction. */
444 { 16, 0, 0, 0, PPC_OPERAND_SIGNED },
446 /* The SI field in a D form instruction when we accept a wide range
447 of positive values. */
448 #define SISIGNOPT SI + 1
449 { 16, 0, 0, 0, PPC_OPERAND_SIGNED | PPC_OPERAND_SIGNOPT },
451 /* The SPR field in an XFX form instruction. This is flipped--the
452 lower 5 bits are stored in the upper 5 and vice- versa. */
453 #define SPR SISIGNOPT + 1
455 #define SPR_MASK (0x3ff << 11)
456 { 10, 11, insert_spr, extract_spr, 0 },
458 /* The BAT index number in an XFX form m[ft]ibat[lu] instruction. */
459 #define SPRBAT SPR + 1
460 #define SPRBAT_MASK (0x3 << 17)
463 /* The SPRG register number in an XFX form m[ft]sprg instruction. */
464 #define SPRG SPRBAT + 1
465 #define SPRG_MASK (0x3 << 16)
468 /* The SR field in an X form instruction. */
472 /* The STRM field in an X AltiVec form instruction. */
474 #define STRM_MASK (0x3 << 21)
477 /* The SV field in a POWER SC form instruction. */
481 /* The TBR field in an XFX form instruction. This is like the SPR
482 field, but it is optional. */
484 { 10, 11, insert_tbr, extract_tbr, PPC_OPERAND_OPTIONAL },
486 /* The TO field in a D or X form instruction. */
488 #define TO_MASK (0x1f << 21)
491 /* The U field in an X form instruction. */
495 /* The UI field in a D form instruction. */
499 /* The VA field in a VA, VX or VXR form instruction. */
501 #define VA_MASK (0x1f << 16)
502 { 5, 16, 0, 0, PPC_OPERAND_VR },
504 /* The VB field in a VA, VX or VXR form instruction. */
506 #define VB_MASK (0x1f << 11)
507 { 5, 11, 0, 0, PPC_OPERAND_VR },
509 /* The VC field in a VA form instruction. */
511 #define VC_MASK (0x1f << 6)
512 { 5, 6, 0, 0, PPC_OPERAND_VR },
514 /* The VD or VS field in a VA, VX, VXR or X form instruction. */
517 #define VD_MASK (0x1f << 21)
518 { 5, 21, 0, 0, PPC_OPERAND_VR },
520 /* The SIMM field in a VX form instruction. */
522 { 5, 16, 0, 0, PPC_OPERAND_SIGNED},
524 /* The UIMM field in a VX form instruction. */
525 #define UIMM SIMM + 1
528 /* The SHB field in a VA form instruction. */
532 /* The other UIMM field in a EVX form instruction. */
533 #define EVUIMM SHB + 1
536 /* The other UIMM field in a half word EVX form instruction. */
537 #define EVUIMM_2 EVUIMM + 1
538 { 32, 11, insert_ev2, extract_ev2, PPC_OPERAND_PARENS },
540 /* The other UIMM field in a word EVX form instruction. */
541 #define EVUIMM_4 EVUIMM_2 + 1
542 { 32, 11, insert_ev4, extract_ev4, PPC_OPERAND_PARENS },
544 /* The other UIMM field in a double EVX form instruction. */
545 #define EVUIMM_8 EVUIMM_4 + 1
546 { 32, 11, insert_ev8, extract_ev8, PPC_OPERAND_PARENS },
549 #define WS EVUIMM_8 + 1
550 #define WS_MASK (0x7 << 11)
553 /* The L field in an mtmsrd instruction */
554 #define MTMSRD_L WS + 1
555 { 1, 16, 0, 0, PPC_OPERAND_OPTIONAL },
559 /* The functions used to insert and extract complicated operands. */
561 /* The BA field in an XL form instruction when it must be the same as
562 the BT field in the same instruction. This operand is marked FAKE.
563 The insertion function just copies the BT field into the BA field,
564 and the extraction function just checks that the fields are the
568 insert_bat (unsigned long insn,
569 long value ATTRIBUTE_UNUSED,
570 int dialect ATTRIBUTE_UNUSED,
571 const char **errmsg ATTRIBUTE_UNUSED)
573 return insn | (((insn >> 21) & 0x1f) << 16);
577 extract_bat (unsigned long insn,
578 int dialect ATTRIBUTE_UNUSED,
581 if (((insn >> 21) & 0x1f) != ((insn >> 16) & 0x1f))
586 /* The BB field in an XL form instruction when it must be the same as
587 the BA field in the same instruction. This operand is marked FAKE.
588 The insertion function just copies the BA field into the BB field,
589 and the extraction function just checks that the fields are the
593 insert_bba (unsigned long insn,
594 long value ATTRIBUTE_UNUSED,
595 int dialect ATTRIBUTE_UNUSED,
596 const char **errmsg ATTRIBUTE_UNUSED)
598 return insn | (((insn >> 16) & 0x1f) << 11);
602 extract_bba (unsigned long insn,
603 int dialect ATTRIBUTE_UNUSED,
606 if (((insn >> 16) & 0x1f) != ((insn >> 11) & 0x1f))
611 /* The BD field in a B form instruction. The lower two bits are
615 insert_bd (unsigned long insn,
617 int dialect ATTRIBUTE_UNUSED,
618 const char **errmsg ATTRIBUTE_UNUSED)
620 return insn | (value & 0xfffc);
624 extract_bd (unsigned long insn,
625 int dialect ATTRIBUTE_UNUSED,
626 int *invalid ATTRIBUTE_UNUSED)
628 return ((insn & 0xfffc) ^ 0x8000) - 0x8000;
631 /* The BD field in a B form instruction when the - modifier is used.
632 This modifier means that the branch is not expected to be taken.
633 For chips built to versions of the architecture prior to version 2
634 (ie. not Power4 compatible), we set the y bit of the BO field to 1
635 if the offset is negative. When extracting, we require that the y
636 bit be 1 and that the offset be positive, since if the y bit is 0
637 we just want to print the normal form of the instruction.
638 Power4 compatible targets use two bits, "a", and "t", instead of
639 the "y" bit. "at" == 00 => no hint, "at" == 01 => unpredictable,
640 "at" == 10 => not taken, "at" == 11 => taken. The "t" bit is 00001
641 in BO field, the "a" bit is 00010 for branch on CR(BI) and 01000
642 for branch on CTR. We only handle the taken/not-taken hint here. */
645 insert_bdm (unsigned long insn,
648 const char **errmsg ATTRIBUTE_UNUSED)
650 if ((dialect & PPC_OPCODE_POWER4) == 0)
652 if ((value & 0x8000) != 0)
657 if ((insn & (0x14 << 21)) == (0x04 << 21))
659 else if ((insn & (0x14 << 21)) == (0x10 << 21))
662 return insn | (value & 0xfffc);
666 extract_bdm (unsigned long insn,
670 if ((dialect & PPC_OPCODE_POWER4) == 0)
672 if (((insn & (1 << 21)) == 0) != ((insn & (1 << 15)) == 0))
677 if ((insn & (0x17 << 21)) != (0x06 << 21)
678 && (insn & (0x1d << 21)) != (0x18 << 21))
682 return ((insn & 0xfffc) ^ 0x8000) - 0x8000;
685 /* The BD field in a B form instruction when the + modifier is used.
686 This is like BDM, above, except that the branch is expected to be
690 insert_bdp (unsigned long insn,
693 const char **errmsg ATTRIBUTE_UNUSED)
695 if ((dialect & PPC_OPCODE_POWER4) == 0)
697 if ((value & 0x8000) == 0)
702 if ((insn & (0x14 << 21)) == (0x04 << 21))
704 else if ((insn & (0x14 << 21)) == (0x10 << 21))
707 return insn | (value & 0xfffc);
711 extract_bdp (unsigned long insn,
715 if ((dialect & PPC_OPCODE_POWER4) == 0)
717 if (((insn & (1 << 21)) == 0) == ((insn & (1 << 15)) == 0))
722 if ((insn & (0x17 << 21)) != (0x07 << 21)
723 && (insn & (0x1d << 21)) != (0x19 << 21))
727 return ((insn & 0xfffc) ^ 0x8000) - 0x8000;
730 /* Check for legal values of a BO field. */
733 valid_bo (long value, int dialect)
735 if ((dialect & PPC_OPCODE_POWER4) == 0)
737 /* Certain encodings have bits that are required to be zero.
738 These are (z must be zero, y may be anything):
745 switch (value & 0x14)
751 return (value & 0x2) == 0;
753 return (value & 0x8) == 0;
755 return value == 0x14;
760 /* Certain encodings have bits that are required to be zero.
761 These are (z must be zero, a & t may be anything):
772 if ((value & 0x14) == 0)
773 return (value & 0x1) == 0;
774 else if ((value & 0x14) == 0x14)
775 return value == 0x14;
781 /* The BO field in a B form instruction. Warn about attempts to set
782 the field to an illegal value. */
785 insert_bo (unsigned long insn,
790 if (!valid_bo (value, dialect))
791 *errmsg = _("invalid conditional option");
792 return insn | ((value & 0x1f) << 21);
796 extract_bo (unsigned long insn,
802 value = (insn >> 21) & 0x1f;
803 if (!valid_bo (value, dialect))
808 /* The BO field in a B form instruction when the + or - modifier is
809 used. This is like the BO field, but it must be even. When
810 extracting it, we force it to be even. */
813 insert_boe (unsigned long insn,
818 if (!valid_bo (value, dialect))
819 *errmsg = _("invalid conditional option");
820 else if ((value & 1) != 0)
821 *errmsg = _("attempt to set y bit when using + or - modifier");
823 return insn | ((value & 0x1f) << 21);
827 extract_boe (unsigned long insn,
833 value = (insn >> 21) & 0x1f;
834 if (!valid_bo (value, dialect))
839 /* The DQ field in a DQ form instruction. This is like D, but the
840 lower four bits are forced to zero. */
843 insert_dq (unsigned long insn,
845 int dialect ATTRIBUTE_UNUSED,
848 if ((value & 0xf) != 0)
849 *errmsg = _("offset not a multiple of 16");
850 return insn | (value & 0xfff0);
854 extract_dq (unsigned long insn,
855 int dialect ATTRIBUTE_UNUSED,
856 int *invalid ATTRIBUTE_UNUSED)
858 return ((insn & 0xfff0) ^ 0x8000) - 0x8000;
862 insert_ev2 (unsigned long insn,
864 int dialect ATTRIBUTE_UNUSED,
867 if ((value & 1) != 0)
868 *errmsg = _("offset not a multiple of 2");
869 if ((value > 62) != 0)
870 *errmsg = _("offset greater than 62");
871 return insn | ((value & 0x3e) << 10);
875 extract_ev2 (unsigned long insn,
876 int dialect ATTRIBUTE_UNUSED,
877 int *invalid ATTRIBUTE_UNUSED)
879 return (insn >> 10) & 0x3e;
883 insert_ev4 (unsigned long insn,
885 int dialect ATTRIBUTE_UNUSED,
888 if ((value & 3) != 0)
889 *errmsg = _("offset not a multiple of 4");
890 if ((value > 124) != 0)
891 *errmsg = _("offset greater than 124");
892 return insn | ((value & 0x7c) << 9);
896 extract_ev4 (unsigned long insn,
897 int dialect ATTRIBUTE_UNUSED,
898 int *invalid ATTRIBUTE_UNUSED)
900 return (insn >> 9) & 0x7c;
904 insert_ev8 (unsigned long insn,
906 int dialect ATTRIBUTE_UNUSED,
909 if ((value & 7) != 0)
910 *errmsg = _("offset not a multiple of 8");
911 if ((value > 248) != 0)
912 *errmsg = _("offset greater than 248");
913 return insn | ((value & 0xf8) << 8);
917 extract_ev8 (unsigned long insn,
918 int dialect ATTRIBUTE_UNUSED,
919 int *invalid ATTRIBUTE_UNUSED)
921 return (insn >> 8) & 0xf8;
924 /* The DS field in a DS form instruction. This is like D, but the
925 lower two bits are forced to zero. */
928 insert_ds (unsigned long insn,
930 int dialect ATTRIBUTE_UNUSED,
933 if ((value & 3) != 0)
934 *errmsg = _("offset not a multiple of 4");
935 return insn | (value & 0xfffc);
939 extract_ds (unsigned long insn,
940 int dialect ATTRIBUTE_UNUSED,
941 int *invalid ATTRIBUTE_UNUSED)
943 return ((insn & 0xfffc) ^ 0x8000) - 0x8000;
946 /* The DE field in a DE form instruction. */
949 insert_de (unsigned long insn,
951 int dialect ATTRIBUTE_UNUSED,
954 if (value > 2047 || value < -2048)
955 *errmsg = _("offset not between -2048 and 2047");
956 return insn | ((value << 4) & 0xfff0);
960 extract_de (unsigned long insn,
961 int dialect ATTRIBUTE_UNUSED,
962 int *invalid ATTRIBUTE_UNUSED)
964 return (insn & 0xfff0) >> 4;
967 /* The DES field in a DES form instruction. */
970 insert_des (unsigned long insn,
972 int dialect ATTRIBUTE_UNUSED,
975 if (value > 8191 || value < -8192)
976 *errmsg = _("offset not between -8192 and 8191");
977 else if ((value & 3) != 0)
978 *errmsg = _("offset not a multiple of 4");
979 return insn | ((value << 2) & 0xfff0);
983 extract_des (unsigned long insn,
984 int dialect ATTRIBUTE_UNUSED,
985 int *invalid ATTRIBUTE_UNUSED)
987 return (((insn >> 2) & 0x3ffc) ^ 0x2000) - 0x2000;
990 /* FXM mask in mfcr and mtcrf instructions. */
993 insert_fxm (unsigned long insn,
998 /* If the optional field on mfcr is missing that means we want to use
999 the old form of the instruction that moves the whole cr. In that
1000 case we'll have VALUE zero. There doesn't seem to be a way to
1001 distinguish this from the case where someone writes mfcr %r3,0. */
1005 /* If only one bit of the FXM field is set, we can use the new form
1006 of the instruction, which is faster. Unlike the Power4 branch hint
1007 encoding, this is not backward compatible. */
1008 else if ((dialect & PPC_OPCODE_POWER4) != 0 && (value & -value) == value)
1011 /* Any other value on mfcr is an error. */
1012 else if ((insn & (0x3ff << 1)) == 19 << 1)
1014 *errmsg = _("ignoring invalid mfcr mask");
1018 return insn | ((value & 0xff) << 12);
1022 extract_fxm (unsigned long insn,
1026 long mask = (insn >> 12) & 0xff;
1028 /* Is this a Power4 insn? */
1029 if ((insn & (1 << 20)) != 0)
1031 if ((dialect & PPC_OPCODE_POWER4) == 0)
1035 /* Exactly one bit of MASK should be set. */
1036 if (mask == 0 || (mask & -mask) != mask)
1041 /* Check that non-power4 form of mfcr has a zero MASK. */
1042 else if ((insn & (0x3ff << 1)) == 19 << 1)
1051 /* The LI field in an I form instruction. The lower two bits are
1054 static unsigned long
1055 insert_li (unsigned long insn,
1057 int dialect ATTRIBUTE_UNUSED,
1058 const char **errmsg)
1060 if ((value & 3) != 0)
1061 *errmsg = _("ignoring least significant bits in branch offset");
1062 return insn | (value & 0x3fffffc);
1066 extract_li (unsigned long insn,
1067 int dialect ATTRIBUTE_UNUSED,
1068 int *invalid ATTRIBUTE_UNUSED)
1070 return ((insn & 0x3fffffc) ^ 0x2000000) - 0x2000000;
1073 /* The MB and ME fields in an M form instruction expressed as a single
1074 operand which is itself a bitmask. The extraction function always
1075 marks it as invalid, since we never want to recognize an
1076 instruction which uses a field of this type. */
1078 static unsigned long
1079 insert_mbe (unsigned long insn,
1081 int dialect ATTRIBUTE_UNUSED,
1082 const char **errmsg)
1084 unsigned long uval, mask;
1085 int mb, me, mx, count, last;
1091 *errmsg = _("illegal bitmask");
1097 if ((uval & 1) != 0)
1103 /* mb: location of last 0->1 transition */
1104 /* me: location of last 1->0 transition */
1105 /* count: # transitions */
1107 for (mx = 0, mask = 1L << 31; mx < 32; ++mx, mask >>= 1)
1109 if ((uval & mask) && !last)
1115 else if (!(uval & mask) && last)
1125 if (count != 2 && (count != 0 || ! last))
1126 *errmsg = _("illegal bitmask");
1128 return insn | (mb << 6) | ((me - 1) << 1);
1132 extract_mbe (unsigned long insn,
1133 int dialect ATTRIBUTE_UNUSED,
1142 mb = (insn >> 6) & 0x1f;
1143 me = (insn >> 1) & 0x1f;
1147 for (i = mb; i <= me; i++)
1148 ret |= 1L << (31 - i);
1150 else if (mb == me + 1)
1152 else /* (mb > me + 1) */
1155 for (i = me + 1; i < mb; i++)
1156 ret &= ~(1L << (31 - i));
1161 /* The MB or ME field in an MD or MDS form instruction. The high bit
1162 is wrapped to the low end. */
1164 static unsigned long
1165 insert_mb6 (unsigned long insn,
1167 int dialect ATTRIBUTE_UNUSED,
1168 const char **errmsg ATTRIBUTE_UNUSED)
1170 return insn | ((value & 0x1f) << 6) | (value & 0x20);
1174 extract_mb6 (unsigned long insn,
1175 int dialect ATTRIBUTE_UNUSED,
1176 int *invalid ATTRIBUTE_UNUSED)
1178 return ((insn >> 6) & 0x1f) | (insn & 0x20);
1181 /* The NB field in an X form instruction. The value 32 is stored as
1184 static unsigned long
1185 insert_nb (unsigned long insn,
1187 int dialect ATTRIBUTE_UNUSED,
1188 const char **errmsg)
1190 if (value < 0 || value > 32)
1191 *errmsg = _("value out of range");
1194 return insn | ((value & 0x1f) << 11);
1198 extract_nb (unsigned long insn,
1199 int dialect ATTRIBUTE_UNUSED,
1200 int *invalid ATTRIBUTE_UNUSED)
1204 ret = (insn >> 11) & 0x1f;
1210 /* The NSI field in a D form instruction. This is the same as the SI
1211 field, only negated. The extraction function always marks it as
1212 invalid, since we never want to recognize an instruction which uses
1213 a field of this type. */
1215 static unsigned long
1216 insert_nsi (unsigned long insn,
1218 int dialect ATTRIBUTE_UNUSED,
1219 const char **errmsg ATTRIBUTE_UNUSED)
1221 return insn | (-value & 0xffff);
1225 extract_nsi (unsigned long insn,
1226 int dialect ATTRIBUTE_UNUSED,
1230 return -(((insn & 0xffff) ^ 0x8000) - 0x8000);
1233 /* The RA field in a D or X form instruction which is an updating
1234 load, which means that the RA field may not be zero and may not
1235 equal the RT field. */
1237 static unsigned long
1238 insert_ral (unsigned long insn,
1240 int dialect ATTRIBUTE_UNUSED,
1241 const char **errmsg)
1244 || (unsigned long) value == ((insn >> 21) & 0x1f))
1245 *errmsg = "invalid register operand when updating";
1246 return insn | ((value & 0x1f) << 16);
1249 /* The RA field in an lmw instruction, which has special value
1252 static unsigned long
1253 insert_ram (unsigned long insn,
1255 int dialect ATTRIBUTE_UNUSED,
1256 const char **errmsg)
1258 if ((unsigned long) value >= ((insn >> 21) & 0x1f))
1259 *errmsg = _("index register in load range");
1260 return insn | ((value & 0x1f) << 16);
1263 /* The RA field in the DQ form lq instruction, which has special
1264 value restrictions. */
1266 static unsigned long
1267 insert_raq (unsigned long insn,
1269 int dialect ATTRIBUTE_UNUSED,
1270 const char **errmsg)
1272 long rtvalue = (insn & RT_MASK) >> 21;
1274 if (value == rtvalue)
1275 *errmsg = _("source and target register operands must be different");
1276 return insn | ((value & 0x1f) << 16);
1279 /* The RA field in a D or X form instruction which is an updating
1280 store or an updating floating point load, which means that the RA
1281 field may not be zero. */
1283 static unsigned long
1284 insert_ras (unsigned long insn,
1286 int dialect ATTRIBUTE_UNUSED,
1287 const char **errmsg)
1290 *errmsg = _("invalid register operand when updating");
1291 return insn | ((value & 0x1f) << 16);
1294 /* The RB field in an X form instruction when it must be the same as
1295 the RS field in the instruction. This is used for extended
1296 mnemonics like mr. This operand is marked FAKE. The insertion
1297 function just copies the BT field into the BA field, and the
1298 extraction function just checks that the fields are the same. */
1300 static unsigned long
1301 insert_rbs (unsigned long insn,
1302 long value ATTRIBUTE_UNUSED,
1303 int dialect ATTRIBUTE_UNUSED,
1304 const char **errmsg ATTRIBUTE_UNUSED)
1306 return insn | (((insn >> 21) & 0x1f) << 11);
1310 extract_rbs (unsigned long insn,
1311 int dialect ATTRIBUTE_UNUSED,
1314 if (((insn >> 21) & 0x1f) != ((insn >> 11) & 0x1f))
1319 /* The RT field of the DQ form lq instruction, which has special
1320 value restrictions. */
1322 static unsigned long
1323 insert_rtq (unsigned long insn,
1325 int dialect ATTRIBUTE_UNUSED,
1326 const char **errmsg)
1328 if ((value & 1) != 0)
1329 *errmsg = _("target register operand must be even");
1330 return insn | ((value & 0x1f) << 21);
1333 /* The RS field of the DS form stq instruction, which has special
1334 value restrictions. */
1336 static unsigned long
1337 insert_rsq (unsigned long insn,
1338 long value ATTRIBUTE_UNUSED,
1339 int dialect ATTRIBUTE_UNUSED,
1340 const char **errmsg)
1342 if ((value & 1) != 0)
1343 *errmsg = _("source register operand must be even");
1344 return insn | ((value & 0x1f) << 21);
1347 /* The SH field in an MD form instruction. This is split. */
1349 static unsigned long
1350 insert_sh6 (unsigned long insn,
1352 int dialect ATTRIBUTE_UNUSED,
1353 const char **errmsg ATTRIBUTE_UNUSED)
1355 return insn | ((value & 0x1f) << 11) | ((value & 0x20) >> 4);
1359 extract_sh6 (unsigned long insn,
1360 int dialect ATTRIBUTE_UNUSED,
1361 int *invalid ATTRIBUTE_UNUSED)
1363 return ((insn >> 11) & 0x1f) | ((insn << 4) & 0x20);
1366 /* The SPR field in an XFX form instruction. This is flipped--the
1367 lower 5 bits are stored in the upper 5 and vice- versa. */
1369 static unsigned long
1370 insert_spr (unsigned long insn,
1372 int dialect ATTRIBUTE_UNUSED,
1373 const char **errmsg ATTRIBUTE_UNUSED)
1375 return insn | ((value & 0x1f) << 16) | ((value & 0x3e0) << 6);
1379 extract_spr (unsigned long insn,
1380 int dialect ATTRIBUTE_UNUSED,
1381 int *invalid ATTRIBUTE_UNUSED)
1383 return ((insn >> 16) & 0x1f) | ((insn >> 6) & 0x3e0);
1386 /* The TBR field in an XFX instruction. This is just like SPR, but it
1387 is optional. When TBR is omitted, it must be inserted as 268 (the
1388 magic number of the TB register). These functions treat 0
1389 (indicating an omitted optional operand) as 268. This means that
1390 ``mftb 4,0'' is not handled correctly. This does not matter very
1391 much, since the architecture manual does not define mftb as
1392 accepting any values other than 268 or 269. */
1396 static unsigned long
1397 insert_tbr (unsigned long insn,
1399 int dialect ATTRIBUTE_UNUSED,
1400 const char **errmsg ATTRIBUTE_UNUSED)
1404 return insn | ((value & 0x1f) << 16) | ((value & 0x3e0) << 6);
1408 extract_tbr (unsigned long insn,
1409 int dialect ATTRIBUTE_UNUSED,
1410 int *invalid ATTRIBUTE_UNUSED)
1414 ret = ((insn >> 16) & 0x1f) | ((insn >> 6) & 0x3e0);
1420 /* Macros used to form opcodes. */
1422 /* The main opcode. */
1423 #define OP(x) ((((unsigned long)(x)) & 0x3f) << 26)
1424 #define OP_MASK OP (0x3f)
1426 /* The main opcode combined with a trap code in the TO field of a D
1427 form instruction. Used for extended mnemonics for the trap
1429 #define OPTO(x,to) (OP (x) | ((((unsigned long)(to)) & 0x1f) << 21))
1430 #define OPTO_MASK (OP_MASK | TO_MASK)
1432 /* The main opcode combined with a comparison size bit in the L field
1433 of a D form or X form instruction. Used for extended mnemonics for
1434 the comparison instructions. */
1435 #define OPL(x,l) (OP (x) | ((((unsigned long)(l)) & 1) << 21))
1436 #define OPL_MASK OPL (0x3f,1)
1438 /* An A form instruction. */
1439 #define A(op, xop, rc) (OP (op) | ((((unsigned long)(xop)) & 0x1f) << 1) | (((unsigned long)(rc)) & 1))
1440 #define A_MASK A (0x3f, 0x1f, 1)
1442 /* An A_MASK with the FRB field fixed. */
1443 #define AFRB_MASK (A_MASK | FRB_MASK)
1445 /* An A_MASK with the FRC field fixed. */
1446 #define AFRC_MASK (A_MASK | FRC_MASK)
1448 /* An A_MASK with the FRA and FRC fields fixed. */
1449 #define AFRAFRC_MASK (A_MASK | FRA_MASK | FRC_MASK)
1451 /* A B form instruction. */
1452 #define B(op, aa, lk) (OP (op) | ((((unsigned long)(aa)) & 1) << 1) | ((lk) & 1))
1453 #define B_MASK B (0x3f, 1, 1)
1455 /* A B form instruction setting the BO field. */
1456 #define BBO(op, bo, aa, lk) (B ((op), (aa), (lk)) | ((((unsigned long)(bo)) & 0x1f) << 21))
1457 #define BBO_MASK BBO (0x3f, 0x1f, 1, 1)
1459 /* A BBO_MASK with the y bit of the BO field removed. This permits
1460 matching a conditional branch regardless of the setting of the y
1461 bit. Similarly for the 'at' bits used for power4 branch hints. */
1462 #define Y_MASK (((unsigned long) 1) << 21)
1463 #define AT1_MASK (((unsigned long) 3) << 21)
1464 #define AT2_MASK (((unsigned long) 9) << 21)
1465 #define BBOY_MASK (BBO_MASK &~ Y_MASK)
1466 #define BBOAT_MASK (BBO_MASK &~ AT1_MASK)
1468 /* A B form instruction setting the BO field and the condition bits of
1470 #define BBOCB(op, bo, cb, aa, lk) \
1471 (BBO ((op), (bo), (aa), (lk)) | ((((unsigned long)(cb)) & 0x3) << 16))
1472 #define BBOCB_MASK BBOCB (0x3f, 0x1f, 0x3, 1, 1)
1474 /* A BBOCB_MASK with the y bit of the BO field removed. */
1475 #define BBOYCB_MASK (BBOCB_MASK &~ Y_MASK)
1476 #define BBOATCB_MASK (BBOCB_MASK &~ AT1_MASK)
1477 #define BBOAT2CB_MASK (BBOCB_MASK &~ AT2_MASK)
1479 /* A BBOYCB_MASK in which the BI field is fixed. */
1480 #define BBOYBI_MASK (BBOYCB_MASK | BI_MASK)
1481 #define BBOATBI_MASK (BBOAT2CB_MASK | BI_MASK)
1483 /* An Context form instruction. */
1484 #define CTX(op, xop) (OP (op) | (((unsigned long)(xop)) & 0x7))
1485 #define CTX_MASK CTX(0x3f, 0x7)
1487 /* An User Context form instruction. */
1488 #define UCTX(op, xop) (OP (op) | (((unsigned long)(xop)) & 0x1f))
1489 #define UCTX_MASK UCTX(0x3f, 0x1f)
1491 /* The main opcode mask with the RA field clear. */
1492 #define DRA_MASK (OP_MASK | RA_MASK)
1494 /* A DS form instruction. */
1495 #define DSO(op, xop) (OP (op) | ((xop) & 0x3))
1496 #define DS_MASK DSO (0x3f, 3)
1498 /* A DE form instruction. */
1499 #define DEO(op, xop) (OP (op) | ((xop) & 0xf))
1500 #define DE_MASK DEO (0x3e, 0xf)
1502 /* An EVSEL form instruction. */
1503 #define EVSEL(op, xop) (OP (op) | (((unsigned long)(xop)) & 0xff) << 3)
1504 #define EVSEL_MASK EVSEL(0x3f, 0xff)
1506 /* An M form instruction. */
1507 #define M(op, rc) (OP (op) | ((rc) & 1))
1508 #define M_MASK M (0x3f, 1)
1510 /* An M form instruction with the ME field specified. */
1511 #define MME(op, me, rc) (M ((op), (rc)) | ((((unsigned long)(me)) & 0x1f) << 1))
1513 /* An M_MASK with the MB and ME fields fixed. */
1514 #define MMBME_MASK (M_MASK | MB_MASK | ME_MASK)
1516 /* An M_MASK with the SH and ME fields fixed. */
1517 #define MSHME_MASK (M_MASK | SH_MASK | ME_MASK)
1519 /* An MD form instruction. */
1520 #define MD(op, xop, rc) (OP (op) | ((((unsigned long)(xop)) & 0x7) << 2) | ((rc) & 1))
1521 #define MD_MASK MD (0x3f, 0x7, 1)
1523 /* An MD_MASK with the MB field fixed. */
1524 #define MDMB_MASK (MD_MASK | MB6_MASK)
1526 /* An MD_MASK with the SH field fixed. */
1527 #define MDSH_MASK (MD_MASK | SH6_MASK)
1529 /* An MDS form instruction. */
1530 #define MDS(op, xop, rc) (OP (op) | ((((unsigned long)(xop)) & 0xf) << 1) | ((rc) & 1))
1531 #define MDS_MASK MDS (0x3f, 0xf, 1)
1533 /* An MDS_MASK with the MB field fixed. */
1534 #define MDSMB_MASK (MDS_MASK | MB6_MASK)
1536 /* An SC form instruction. */
1537 #define SC(op, sa, lk) (OP (op) | ((((unsigned long)(sa)) & 1) << 1) | ((lk) & 1))
1538 #define SC_MASK (OP_MASK | (((unsigned long)0x3ff) << 16) | (((unsigned long)1) << 1) | 1)
1540 /* An VX form instruction. */
1541 #define VX(op, xop) (OP (op) | (((unsigned long)(xop)) & 0x7ff))
1543 /* The mask for an VX form instruction. */
1544 #define VX_MASK VX(0x3f, 0x7ff)
1546 /* An VA form instruction. */
1547 #define VXA(op, xop) (OP (op) | (((unsigned long)(xop)) & 0x03f))
1549 /* The mask for an VA form instruction. */
1550 #define VXA_MASK VXA(0x3f, 0x3f)
1552 /* An VXR form instruction. */
1553 #define VXR(op, xop, rc) (OP (op) | (((rc) & 1) << 10) | (((unsigned long)(xop)) & 0x3ff))
1555 /* The mask for a VXR form instruction. */
1556 #define VXR_MASK VXR(0x3f, 0x3ff, 1)
1558 /* An X form instruction. */
1559 #define X(op, xop) (OP (op) | ((((unsigned long)(xop)) & 0x3ff) << 1))
1561 /* An X form instruction with the RC bit specified. */
1562 #define XRC(op, xop, rc) (X ((op), (xop)) | ((rc) & 1))
1564 /* The mask for an X form instruction. */
1565 #define X_MASK XRC (0x3f, 0x3ff, 1)
1567 /* An X_MASK with the RA field fixed. */
1568 #define XRA_MASK (X_MASK | RA_MASK)
1570 /* An X_MASK with the RB field fixed. */
1571 #define XRB_MASK (X_MASK | RB_MASK)
1573 /* An X_MASK with the RT field fixed. */
1574 #define XRT_MASK (X_MASK | RT_MASK)
1576 /* An X_MASK with the RA and RB fields fixed. */
1577 #define XRARB_MASK (X_MASK | RA_MASK | RB_MASK)
1579 /* An XRARB_MASK, but with the L bit clear. */
1580 #define XRLARB_MASK (XRARB_MASK & ~((unsigned long) 1 << 16))
1582 /* An X_MASK with the RT and RA fields fixed. */
1583 #define XRTRA_MASK (X_MASK | RT_MASK | RA_MASK)
1585 /* An XRTRA_MASK, but with L bit clear. */
1586 #define XRTLRA_MASK (XRTRA_MASK & ~((unsigned long) 1 << 21))
1588 /* An X form comparison instruction. */
1589 #define XCMPL(op, xop, l) (X ((op), (xop)) | ((((unsigned long)(l)) & 1) << 21))
1591 /* The mask for an X form comparison instruction. */
1592 #define XCMP_MASK (X_MASK | (((unsigned long)1) << 22))
1594 /* The mask for an X form comparison instruction with the L field
1596 #define XCMPL_MASK (XCMP_MASK | (((unsigned long)1) << 21))
1598 /* An X form trap instruction with the TO field specified. */
1599 #define XTO(op, xop, to) (X ((op), (xop)) | ((((unsigned long)(to)) & 0x1f) << 21))
1600 #define XTO_MASK (X_MASK | TO_MASK)
1602 /* An X form tlb instruction with the SH field specified. */
1603 #define XTLB(op, xop, sh) (X ((op), (xop)) | ((((unsigned long)(sh)) & 0x1f) << 11))
1604 #define XTLB_MASK (X_MASK | SH_MASK)
1606 /* An X form sync instruction. */
1607 #define XSYNC(op, xop, l) (X ((op), (xop)) | ((((unsigned long)(l)) & 3) << 21))
1609 /* An X form sync instruction with everything filled in except the LS field. */
1610 #define XSYNC_MASK (0xff9fffff)
1612 /* An X form AltiVec dss instruction. */
1613 #define XDSS(op, xop, a) (X ((op), (xop)) | ((((unsigned long)(a)) & 1) << 25))
1614 #define XDSS_MASK XDSS(0x3f, 0x3ff, 1)
1616 /* An XFL form instruction. */
1617 #define XFL(op, xop, rc) (OP (op) | ((((unsigned long)(xop)) & 0x3ff) << 1) | (((unsigned long)(rc)) & 1))
1618 #define XFL_MASK (XFL (0x3f, 0x3ff, 1) | (((unsigned long)1) << 25) | (((unsigned long)1) << 16))
1620 /* An X form isel instruction. */
1621 #define XISEL(op, xop) (OP (op) | ((((unsigned long)(xop)) & 0x1f) << 1))
1622 #define XISEL_MASK XISEL(0x3f, 0x1f)
1624 /* An XL form instruction with the LK field set to 0. */
1625 #define XL(op, xop) (OP (op) | ((((unsigned long)(xop)) & 0x3ff) << 1))
1627 /* An XL form instruction which uses the LK field. */
1628 #define XLLK(op, xop, lk) (XL ((op), (xop)) | ((lk) & 1))
1630 /* The mask for an XL form instruction. */
1631 #define XL_MASK XLLK (0x3f, 0x3ff, 1)
1633 /* An XL form instruction which explicitly sets the BO field. */
1634 #define XLO(op, bo, xop, lk) \
1635 (XLLK ((op), (xop), (lk)) | ((((unsigned long)(bo)) & 0x1f) << 21))
1636 #define XLO_MASK (XL_MASK | BO_MASK)
1638 /* An XL form instruction which explicitly sets the y bit of the BO
1640 #define XLYLK(op, xop, y, lk) (XLLK ((op), (xop), (lk)) | ((((unsigned long)(y)) & 1) << 21))
1641 #define XLYLK_MASK (XL_MASK | Y_MASK)
1643 /* An XL form instruction which sets the BO field and the condition
1644 bits of the BI field. */
1645 #define XLOCB(op, bo, cb, xop, lk) \
1646 (XLO ((op), (bo), (xop), (lk)) | ((((unsigned long)(cb)) & 3) << 16))
1647 #define XLOCB_MASK XLOCB (0x3f, 0x1f, 0x3, 0x3ff, 1)
1649 /* An XL_MASK or XLYLK_MASK or XLOCB_MASK with the BB field fixed. */
1650 #define XLBB_MASK (XL_MASK | BB_MASK)
1651 #define XLYBB_MASK (XLYLK_MASK | BB_MASK)
1652 #define XLBOCBBB_MASK (XLOCB_MASK | BB_MASK)
1654 /* An XL_MASK with the BO and BB fields fixed. */
1655 #define XLBOBB_MASK (XL_MASK | BO_MASK | BB_MASK)
1657 /* An XL_MASK with the BO, BI and BB fields fixed. */
1658 #define XLBOBIBB_MASK (XL_MASK | BO_MASK | BI_MASK | BB_MASK)
1660 /* An XO form instruction. */
1661 #define XO(op, xop, oe, rc) \
1662 (OP (op) | ((((unsigned long)(xop)) & 0x1ff) << 1) | ((((unsigned long)(oe)) & 1) << 10) | (((unsigned long)(rc)) & 1))
1663 #define XO_MASK XO (0x3f, 0x1ff, 1, 1)
1665 /* An XO_MASK with the RB field fixed. */
1666 #define XORB_MASK (XO_MASK | RB_MASK)
1668 /* An XS form instruction. */
1669 #define XS(op, xop, rc) (OP (op) | ((((unsigned long)(xop)) & 0x1ff) << 2) | (((unsigned long)(rc)) & 1))
1670 #define XS_MASK XS (0x3f, 0x1ff, 1)
1672 /* A mask for the FXM version of an XFX form instruction. */
1673 #define XFXFXM_MASK (X_MASK | (1 << 11))
1675 /* An XFX form instruction with the FXM field filled in. */
1676 #define XFXM(op, xop, fxm) \
1677 (X ((op), (xop)) | ((((unsigned long)(fxm)) & 0xff) << 12))
1679 /* An XFX form instruction with the SPR field filled in. */
1680 #define XSPR(op, xop, spr) \
1681 (X ((op), (xop)) | ((((unsigned long)(spr)) & 0x1f) << 16) | ((((unsigned long)(spr)) & 0x3e0) << 6))
1682 #define XSPR_MASK (X_MASK | SPR_MASK)
1684 /* An XFX form instruction with the SPR field filled in except for the
1686 #define XSPRBAT_MASK (XSPR_MASK &~ SPRBAT_MASK)
1688 /* An XFX form instruction with the SPR field filled in except for the
1690 #define XSPRG_MASK (XSPR_MASK &~ SPRG_MASK)
1692 /* An X form instruction with everything filled in except the E field. */
1693 #define XE_MASK (0xffff7fff)
1695 /* An X form user context instruction. */
1696 #define XUC(op, xop) (OP (op) | (((unsigned long)(xop)) & 0x1f))
1697 #define XUC_MASK XUC(0x3f, 0x1f)
1699 /* The BO encodings used in extended conditional branch mnemonics. */
1700 #define BODNZF (0x0)
1701 #define BODNZFP (0x1)
1703 #define BODZFP (0x3)
1704 #define BODNZT (0x8)
1705 #define BODNZTP (0x9)
1707 #define BODZTP (0xb)
1718 #define BODNZ (0x10)
1719 #define BODNZP (0x11)
1721 #define BODZP (0x13)
1722 #define BODNZM4 (0x18)
1723 #define BODNZP4 (0x19)
1724 #define BODZM4 (0x1a)
1725 #define BODZP4 (0x1b)
1729 /* The BI condition bit encodings used in extended conditional branch
1736 /* The TO encodings used in extended trap mnemonics. */
1753 /* Smaller names for the flags so each entry in the opcodes table will
1754 fit on a single line. */
1756 #define PPC PPC_OPCODE_PPC
1757 #define PPCCOM PPC_OPCODE_PPC | PPC_OPCODE_COMMON
1758 #define NOPOWER4 PPC_OPCODE_NOPOWER4 | PPCCOM
1759 #define POWER4 PPC_OPCODE_POWER4
1760 #define PPC32 PPC_OPCODE_32 | PPC_OPCODE_PPC
1761 #define PPC64 PPC_OPCODE_64 | PPC_OPCODE_PPC
1762 #define PPC403 PPC_OPCODE_403
1763 #define PPC405 PPC403
1764 #define PPC440 PPC_OPCODE_440
1767 #define PPCVEC PPC_OPCODE_ALTIVEC | PPC_OPCODE_PPC
1768 #define POWER PPC_OPCODE_POWER
1769 #define POWER2 PPC_OPCODE_POWER | PPC_OPCODE_POWER2
1770 #define PPCPWR2 PPC_OPCODE_PPC | PPC_OPCODE_POWER | PPC_OPCODE_POWER2
1771 #define POWER32 PPC_OPCODE_POWER | PPC_OPCODE_32
1772 #define COM PPC_OPCODE_POWER | PPC_OPCODE_PPC | PPC_OPCODE_COMMON
1773 #define COM32 PPC_OPCODE_POWER | PPC_OPCODE_PPC | PPC_OPCODE_COMMON | PPC_OPCODE_32
1774 #define M601 PPC_OPCODE_POWER | PPC_OPCODE_601
1775 #define PWRCOM PPC_OPCODE_POWER | PPC_OPCODE_601 | PPC_OPCODE_COMMON
1776 #define MFDEC1 PPC_OPCODE_POWER
1777 #define MFDEC2 PPC_OPCODE_PPC | PPC_OPCODE_601 | PPC_OPCODE_BOOKE
1778 #define BOOKE PPC_OPCODE_BOOKE
1779 #define BOOKE64 PPC_OPCODE_BOOKE64
1780 #define CLASSIC PPC_OPCODE_CLASSIC
1781 #define PPCSPE PPC_OPCODE_SPE
1782 #define PPCISEL PPC_OPCODE_ISEL
1783 #define PPCEFS PPC_OPCODE_EFS
1784 #define PPCBRLK PPC_OPCODE_BRLOCK
1785 #define PPCPMR PPC_OPCODE_PMR
1786 #define PPCCHLK PPC_OPCODE_CACHELCK
1787 #define PPCCHLK64 PPC_OPCODE_CACHELCK | PPC_OPCODE_BOOKE64
1788 #define PPCRFMCI PPC_OPCODE_RFMCI
1790 /* The opcode table.
1792 The format of the opcode table is:
1794 NAME OPCODE MASK FLAGS { OPERANDS }
1796 NAME is the name of the instruction.
1797 OPCODE is the instruction opcode.
1798 MASK is the opcode mask; this is used to tell the disassembler
1799 which bits in the actual opcode must match OPCODE.
1800 FLAGS are flags indicated what processors support the instruction.
1801 OPERANDS is the list of operands.
1803 The disassembler reads the table in order and prints the first
1804 instruction which matches, so this table is sorted to put more
1805 specific instructions before more general instructions. It is also
1806 sorted by major opcode. */
1808 const struct powerpc_opcode powerpc_opcodes[] = {
1809 { "attn", X(0,256), X_MASK, POWER4, { 0 } },
1810 { "tdlgti", OPTO(2,TOLGT), OPTO_MASK, PPC64, { RA, SI } },
1811 { "tdllti", OPTO(2,TOLLT), OPTO_MASK, PPC64, { RA, SI } },
1812 { "tdeqi", OPTO(2,TOEQ), OPTO_MASK, PPC64, { RA, SI } },
1813 { "tdlgei", OPTO(2,TOLGE), OPTO_MASK, PPC64, { RA, SI } },
1814 { "tdlnli", OPTO(2,TOLNL), OPTO_MASK, PPC64, { RA, SI } },
1815 { "tdllei", OPTO(2,TOLLE), OPTO_MASK, PPC64, { RA, SI } },
1816 { "tdlngi", OPTO(2,TOLNG), OPTO_MASK, PPC64, { RA, SI } },
1817 { "tdgti", OPTO(2,TOGT), OPTO_MASK, PPC64, { RA, SI } },
1818 { "tdgei", OPTO(2,TOGE), OPTO_MASK, PPC64, { RA, SI } },
1819 { "tdnli", OPTO(2,TONL), OPTO_MASK, PPC64, { RA, SI } },
1820 { "tdlti", OPTO(2,TOLT), OPTO_MASK, PPC64, { RA, SI } },
1821 { "tdlei", OPTO(2,TOLE), OPTO_MASK, PPC64, { RA, SI } },
1822 { "tdngi", OPTO(2,TONG), OPTO_MASK, PPC64, { RA, SI } },
1823 { "tdnei", OPTO(2,TONE), OPTO_MASK, PPC64, { RA, SI } },
1824 { "tdi", OP(2), OP_MASK, PPC64, { TO, RA, SI } },
1826 { "twlgti", OPTO(3,TOLGT), OPTO_MASK, PPCCOM, { RA, SI } },
1827 { "tlgti", OPTO(3,TOLGT), OPTO_MASK, PWRCOM, { RA, SI } },
1828 { "twllti", OPTO(3,TOLLT), OPTO_MASK, PPCCOM, { RA, SI } },
1829 { "tllti", OPTO(3,TOLLT), OPTO_MASK, PWRCOM, { RA, SI } },
1830 { "tweqi", OPTO(3,TOEQ), OPTO_MASK, PPCCOM, { RA, SI } },
1831 { "teqi", OPTO(3,TOEQ), OPTO_MASK, PWRCOM, { RA, SI } },
1832 { "twlgei", OPTO(3,TOLGE), OPTO_MASK, PPCCOM, { RA, SI } },
1833 { "tlgei", OPTO(3,TOLGE), OPTO_MASK, PWRCOM, { RA, SI } },
1834 { "twlnli", OPTO(3,TOLNL), OPTO_MASK, PPCCOM, { RA, SI } },
1835 { "tlnli", OPTO(3,TOLNL), OPTO_MASK, PWRCOM, { RA, SI } },
1836 { "twllei", OPTO(3,TOLLE), OPTO_MASK, PPCCOM, { RA, SI } },
1837 { "tllei", OPTO(3,TOLLE), OPTO_MASK, PWRCOM, { RA, SI } },
1838 { "twlngi", OPTO(3,TOLNG), OPTO_MASK, PPCCOM, { RA, SI } },
1839 { "tlngi", OPTO(3,TOLNG), OPTO_MASK, PWRCOM, { RA, SI } },
1840 { "twgti", OPTO(3,TOGT), OPTO_MASK, PPCCOM, { RA, SI } },
1841 { "tgti", OPTO(3,TOGT), OPTO_MASK, PWRCOM, { RA, SI } },
1842 { "twgei", OPTO(3,TOGE), OPTO_MASK, PPCCOM, { RA, SI } },
1843 { "tgei", OPTO(3,TOGE), OPTO_MASK, PWRCOM, { RA, SI } },
1844 { "twnli", OPTO(3,TONL), OPTO_MASK, PPCCOM, { RA, SI } },
1845 { "tnli", OPTO(3,TONL), OPTO_MASK, PWRCOM, { RA, SI } },
1846 { "twlti", OPTO(3,TOLT), OPTO_MASK, PPCCOM, { RA, SI } },
1847 { "tlti", OPTO(3,TOLT), OPTO_MASK, PWRCOM, { RA, SI } },
1848 { "twlei", OPTO(3,TOLE), OPTO_MASK, PPCCOM, { RA, SI } },
1849 { "tlei", OPTO(3,TOLE), OPTO_MASK, PWRCOM, { RA, SI } },
1850 { "twngi", OPTO(3,TONG), OPTO_MASK, PPCCOM, { RA, SI } },
1851 { "tngi", OPTO(3,TONG), OPTO_MASK, PWRCOM, { RA, SI } },
1852 { "twnei", OPTO(3,TONE), OPTO_MASK, PPCCOM, { RA, SI } },
1853 { "tnei", OPTO(3,TONE), OPTO_MASK, PWRCOM, { RA, SI } },
1854 { "twi", OP(3), OP_MASK, PPCCOM, { TO, RA, SI } },
1855 { "ti", OP(3), OP_MASK, PWRCOM, { TO, RA, SI } },
1857 { "macchw", XO(4,172,0,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1858 { "macchw.", XO(4,172,0,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1859 { "macchwo", XO(4,172,1,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1860 { "macchwo.", XO(4,172,1,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1861 { "macchws", XO(4,236,0,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1862 { "macchws.", XO(4,236,0,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1863 { "macchwso", XO(4,236,1,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1864 { "macchwso.", XO(4,236,1,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1865 { "macchwsu", XO(4,204,0,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1866 { "macchwsu.", XO(4,204,0,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1867 { "macchwsuo", XO(4,204,1,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1868 { "macchwsuo.", XO(4,204,1,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1869 { "macchwu", XO(4,140,0,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1870 { "macchwu.", XO(4,140,0,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1871 { "macchwuo", XO(4,140,1,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1872 { "macchwuo.", XO(4,140,1,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1873 { "machhw", XO(4,44,0,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1874 { "machhw.", XO(4,44,0,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1875 { "machhwo", XO(4,44,1,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1876 { "machhwo.", XO(4,44,1,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1877 { "machhws", XO(4,108,0,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1878 { "machhws.", XO(4,108,0,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1879 { "machhwso", XO(4,108,1,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1880 { "machhwso.", XO(4,108,1,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1881 { "machhwsu", XO(4,76,0,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1882 { "machhwsu.", XO(4,76,0,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1883 { "machhwsuo", XO(4,76,1,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1884 { "machhwsuo.", XO(4,76,1,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1885 { "machhwu", XO(4,12,0,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1886 { "machhwu.", XO(4,12,0,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1887 { "machhwuo", XO(4,12,1,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1888 { "machhwuo.", XO(4,12,1,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1889 { "maclhw", XO(4,428,0,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1890 { "maclhw.", XO(4,428,0,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1891 { "maclhwo", XO(4,428,1,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1892 { "maclhwo.", XO(4,428,1,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1893 { "maclhws", XO(4,492,0,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1894 { "maclhws.", XO(4,492,0,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1895 { "maclhwso", XO(4,492,1,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1896 { "maclhwso.", XO(4,492,1,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1897 { "maclhwsu", XO(4,460,0,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1898 { "maclhwsu.", XO(4,460,0,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1899 { "maclhwsuo", XO(4,460,1,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1900 { "maclhwsuo.", XO(4,460,1,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1901 { "maclhwu", XO(4,396,0,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1902 { "maclhwu.", XO(4,396,0,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1903 { "maclhwuo", XO(4,396,1,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1904 { "maclhwuo.", XO(4,396,1,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1905 { "mulchw", XRC(4,168,0), X_MASK, PPC405|PPC440, { RT, RA, RB } },
1906 { "mulchw.", XRC(4,168,1), X_MASK, PPC405|PPC440, { RT, RA, RB } },
1907 { "mulchwu", XRC(4,136,0), X_MASK, PPC405|PPC440, { RT, RA, RB } },
1908 { "mulchwu.", XRC(4,136,1), X_MASK, PPC405|PPC440, { RT, RA, RB } },
1909 { "mulhhw", XRC(4,40,0), X_MASK, PPC405|PPC440, { RT, RA, RB } },
1910 { "mulhhw.", XRC(4,40,1), X_MASK, PPC405|PPC440, { RT, RA, RB } },
1911 { "mulhhwu", XRC(4,8,0), X_MASK, PPC405|PPC440, { RT, RA, RB } },
1912 { "mulhhwu.", XRC(4,8,1), X_MASK, PPC405|PPC440, { RT, RA, RB } },
1913 { "mullhw", XRC(4,424,0), X_MASK, PPC405|PPC440, { RT, RA, RB } },
1914 { "mullhw.", XRC(4,424,1), X_MASK, PPC405|PPC440, { RT, RA, RB } },
1915 { "mullhwu", XRC(4,392,0), X_MASK, PPC405|PPC440, { RT, RA, RB } },
1916 { "mullhwu.", XRC(4,392,1), X_MASK, PPC405|PPC440, { RT, RA, RB } },
1917 { "nmacchw", XO(4,174,0,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1918 { "nmacchw.", XO(4,174,0,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1919 { "nmacchwo", XO(4,174,1,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1920 { "nmacchwo.", XO(4,174,1,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1921 { "nmacchws", XO(4,238,0,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1922 { "nmacchws.", XO(4,238,0,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1923 { "nmacchwso", XO(4,238,1,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1924 { "nmacchwso.", XO(4,238,1,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1925 { "nmachhw", XO(4,46,0,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1926 { "nmachhw.", XO(4,46,0,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1927 { "nmachhwo", XO(4,46,1,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1928 { "nmachhwo.", XO(4,46,1,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1929 { "nmachhws", XO(4,110,0,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1930 { "nmachhws.", XO(4,110,0,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1931 { "nmachhwso", XO(4,110,1,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1932 { "nmachhwso.", XO(4,110,1,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1933 { "nmaclhw", XO(4,430,0,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1934 { "nmaclhw.", XO(4,430,0,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1935 { "nmaclhwo", XO(4,430,1,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1936 { "nmaclhwo.", XO(4,430,1,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1937 { "nmaclhws", XO(4,494,0,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1938 { "nmaclhws.", XO(4,494,0,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1939 { "nmaclhwso", XO(4,494,1,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1940 { "nmaclhwso.", XO(4,494,1,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1941 { "mfvscr", VX(4, 1540), VX_MASK, PPCVEC, { VD } },
1942 { "mtvscr", VX(4, 1604), VX_MASK, PPCVEC, { VB } },
1943 { "vaddcuw", VX(4, 384), VX_MASK, PPCVEC, { VD, VA, VB } },
1944 { "vaddfp", VX(4, 10), VX_MASK, PPCVEC, { VD, VA, VB } },
1945 { "vaddsbs", VX(4, 768), VX_MASK, PPCVEC, { VD, VA, VB } },
1946 { "vaddshs", VX(4, 832), VX_MASK, PPCVEC, { VD, VA, VB } },
1947 { "vaddsws", VX(4, 896), VX_MASK, PPCVEC, { VD, VA, VB } },
1948 { "vaddubm", VX(4, 0), VX_MASK, PPCVEC, { VD, VA, VB } },
1949 { "vaddubs", VX(4, 512), VX_MASK, PPCVEC, { VD, VA, VB } },
1950 { "vadduhm", VX(4, 64), VX_MASK, PPCVEC, { VD, VA, VB } },
1951 { "vadduhs", VX(4, 576), VX_MASK, PPCVEC, { VD, VA, VB } },
1952 { "vadduwm", VX(4, 128), VX_MASK, PPCVEC, { VD, VA, VB } },
1953 { "vadduws", VX(4, 640), VX_MASK, PPCVEC, { VD, VA, VB } },
1954 { "vand", VX(4, 1028), VX_MASK, PPCVEC, { VD, VA, VB } },
1955 { "vandc", VX(4, 1092), VX_MASK, PPCVEC, { VD, VA, VB } },
1956 { "vavgsb", VX(4, 1282), VX_MASK, PPCVEC, { VD, VA, VB } },
1957 { "vavgsh", VX(4, 1346), VX_MASK, PPCVEC, { VD, VA, VB } },
1958 { "vavgsw", VX(4, 1410), VX_MASK, PPCVEC, { VD, VA, VB } },
1959 { "vavgub", VX(4, 1026), VX_MASK, PPCVEC, { VD, VA, VB } },
1960 { "vavguh", VX(4, 1090), VX_MASK, PPCVEC, { VD, VA, VB } },
1961 { "vavguw", VX(4, 1154), VX_MASK, PPCVEC, { VD, VA, VB } },
1962 { "vcfsx", VX(4, 842), VX_MASK, PPCVEC, { VD, VB, UIMM } },
1963 { "vcfux", VX(4, 778), VX_MASK, PPCVEC, { VD, VB, UIMM } },
1964 { "vcmpbfp", VXR(4, 966, 0), VXR_MASK, PPCVEC, { VD, VA, VB } },
1965 { "vcmpbfp.", VXR(4, 966, 1), VXR_MASK, PPCVEC, { VD, VA, VB } },
1966 { "vcmpeqfp", VXR(4, 198, 0), VXR_MASK, PPCVEC, { VD, VA, VB } },
1967 { "vcmpeqfp.", VXR(4, 198, 1), VXR_MASK, PPCVEC, { VD, VA, VB } },
1968 { "vcmpequb", VXR(4, 6, 0), VXR_MASK, PPCVEC, { VD, VA, VB } },
1969 { "vcmpequb.", VXR(4, 6, 1), VXR_MASK, PPCVEC, { VD, VA, VB } },
1970 { "vcmpequh", VXR(4, 70, 0), VXR_MASK, PPCVEC, { VD, VA, VB } },
1971 { "vcmpequh.", VXR(4, 70, 1), VXR_MASK, PPCVEC, { VD, VA, VB } },
1972 { "vcmpequw", VXR(4, 134, 0), VXR_MASK, PPCVEC, { VD, VA, VB } },
1973 { "vcmpequw.", VXR(4, 134, 1), VXR_MASK, PPCVEC, { VD, VA, VB } },
1974 { "vcmpgefp", VXR(4, 454, 0), VXR_MASK, PPCVEC, { VD, VA, VB } },
1975 { "vcmpgefp.", VXR(4, 454, 1), VXR_MASK, PPCVEC, { VD, VA, VB } },
1976 { "vcmpgtfp", VXR(4, 710, 0), VXR_MASK, PPCVEC, { VD, VA, VB } },
1977 { "vcmpgtfp.", VXR(4, 710, 1), VXR_MASK, PPCVEC, { VD, VA, VB } },
1978 { "vcmpgtsb", VXR(4, 774, 0), VXR_MASK, PPCVEC, { VD, VA, VB } },
1979 { "vcmpgtsb.", VXR(4, 774, 1), VXR_MASK, PPCVEC, { VD, VA, VB } },
1980 { "vcmpgtsh", VXR(4, 838, 0), VXR_MASK, PPCVEC, { VD, VA, VB } },
1981 { "vcmpgtsh.", VXR(4, 838, 1), VXR_MASK, PPCVEC, { VD, VA, VB } },
1982 { "vcmpgtsw", VXR(4, 902, 0), VXR_MASK, PPCVEC, { VD, VA, VB } },
1983 { "vcmpgtsw.", VXR(4, 902, 1), VXR_MASK, PPCVEC, { VD, VA, VB } },
1984 { "vcmpgtub", VXR(4, 518, 0), VXR_MASK, PPCVEC, { VD, VA, VB } },
1985 { "vcmpgtub.", VXR(4, 518, 1), VXR_MASK, PPCVEC, { VD, VA, VB } },
1986 { "vcmpgtuh", VXR(4, 582, 0), VXR_MASK, PPCVEC, { VD, VA, VB } },
1987 { "vcmpgtuh.", VXR(4, 582, 1), VXR_MASK, PPCVEC, { VD, VA, VB } },
1988 { "vcmpgtuw", VXR(4, 646, 0), VXR_MASK, PPCVEC, { VD, VA, VB } },
1989 { "vcmpgtuw.", VXR(4, 646, 1), VXR_MASK, PPCVEC, { VD, VA, VB } },
1990 { "vctsxs", VX(4, 970), VX_MASK, PPCVEC, { VD, VB, UIMM } },
1991 { "vctuxs", VX(4, 906), VX_MASK, PPCVEC, { VD, VB, UIMM } },
1992 { "vexptefp", VX(4, 394), VX_MASK, PPCVEC, { VD, VB } },
1993 { "vlogefp", VX(4, 458), VX_MASK, PPCVEC, { VD, VB } },
1994 { "vmaddfp", VXA(4, 46), VXA_MASK, PPCVEC, { VD, VA, VC, VB } },
1995 { "vmaxfp", VX(4, 1034), VX_MASK, PPCVEC, { VD, VA, VB } },
1996 { "vmaxsb", VX(4, 258), VX_MASK, PPCVEC, { VD, VA, VB } },
1997 { "vmaxsh", VX(4, 322), VX_MASK, PPCVEC, { VD, VA, VB } },
1998 { "vmaxsw", VX(4, 386), VX_MASK, PPCVEC, { VD, VA, VB } },
1999 { "vmaxub", VX(4, 2), VX_MASK, PPCVEC, { VD, VA, VB } },
2000 { "vmaxuh", VX(4, 66), VX_MASK, PPCVEC, { VD, VA, VB } },
2001 { "vmaxuw", VX(4, 130), VX_MASK, PPCVEC, { VD, VA, VB } },
2002 { "vmhaddshs", VXA(4, 32), VXA_MASK, PPCVEC, { VD, VA, VB, VC } },
2003 { "vmhraddshs", VXA(4, 33), VXA_MASK, PPCVEC, { VD, VA, VB, VC } },
2004 { "vminfp", VX(4, 1098), VX_MASK, PPCVEC, { VD, VA, VB } },
2005 { "vminsb", VX(4, 770), VX_MASK, PPCVEC, { VD, VA, VB } },
2006 { "vminsh", VX(4, 834), VX_MASK, PPCVEC, { VD, VA, VB } },
2007 { "vminsw", VX(4, 898), VX_MASK, PPCVEC, { VD, VA, VB } },
2008 { "vminub", VX(4, 514), VX_MASK, PPCVEC, { VD, VA, VB } },
2009 { "vminuh", VX(4, 578), VX_MASK, PPCVEC, { VD, VA, VB } },
2010 { "vminuw", VX(4, 642), VX_MASK, PPCVEC, { VD, VA, VB } },
2011 { "vmladduhm", VXA(4, 34), VXA_MASK, PPCVEC, { VD, VA, VB, VC } },
2012 { "vmrghb", VX(4, 12), VX_MASK, PPCVEC, { VD, VA, VB } },
2013 { "vmrghh", VX(4, 76), VX_MASK, PPCVEC, { VD, VA, VB } },
2014 { "vmrghw", VX(4, 140), VX_MASK, PPCVEC, { VD, VA, VB } },
2015 { "vmrglb", VX(4, 268), VX_MASK, PPCVEC, { VD, VA, VB } },
2016 { "vmrglh", VX(4, 332), VX_MASK, PPCVEC, { VD, VA, VB } },
2017 { "vmrglw", VX(4, 396), VX_MASK, PPCVEC, { VD, VA, VB } },
2018 { "vmsummbm", VXA(4, 37), VXA_MASK, PPCVEC, { VD, VA, VB, VC } },
2019 { "vmsumshm", VXA(4, 40), VXA_MASK, PPCVEC, { VD, VA, VB, VC } },
2020 { "vmsumshs", VXA(4, 41), VXA_MASK, PPCVEC, { VD, VA, VB, VC } },
2021 { "vmsumubm", VXA(4, 36), VXA_MASK, PPCVEC, { VD, VA, VB, VC } },
2022 { "vmsumuhm", VXA(4, 38), VXA_MASK, PPCVEC, { VD, VA, VB, VC } },
2023 { "vmsumuhs", VXA(4, 39), VXA_MASK, PPCVEC, { VD, VA, VB, VC } },
2024 { "vmulesb", VX(4, 776), VX_MASK, PPCVEC, { VD, VA, VB } },
2025 { "vmulesh", VX(4, 840), VX_MASK, PPCVEC, { VD, VA, VB } },
2026 { "vmuleub", VX(4, 520), VX_MASK, PPCVEC, { VD, VA, VB } },
2027 { "vmuleuh", VX(4, 584), VX_MASK, PPCVEC, { VD, VA, VB } },
2028 { "vmulosb", VX(4, 264), VX_MASK, PPCVEC, { VD, VA, VB } },
2029 { "vmulosh", VX(4, 328), VX_MASK, PPCVEC, { VD, VA, VB } },
2030 { "vmuloub", VX(4, 8), VX_MASK, PPCVEC, { VD, VA, VB } },
2031 { "vmulouh", VX(4, 72), VX_MASK, PPCVEC, { VD, VA, VB } },
2032 { "vnmsubfp", VXA(4, 47), VXA_MASK, PPCVEC, { VD, VA, VC, VB } },
2033 { "vnor", VX(4, 1284), VX_MASK, PPCVEC, { VD, VA, VB } },
2034 { "vor", VX(4, 1156), VX_MASK, PPCVEC, { VD, VA, VB } },
2035 { "vperm", VXA(4, 43), VXA_MASK, PPCVEC, { VD, VA, VB, VC } },
2036 { "vpkpx", VX(4, 782), VX_MASK, PPCVEC, { VD, VA, VB } },
2037 { "vpkshss", VX(4, 398), VX_MASK, PPCVEC, { VD, VA, VB } },
2038 { "vpkshus", VX(4, 270), VX_MASK, PPCVEC, { VD, VA, VB } },
2039 { "vpkswss", VX(4, 462), VX_MASK, PPCVEC, { VD, VA, VB } },
2040 { "vpkswus", VX(4, 334), VX_MASK, PPCVEC, { VD, VA, VB } },
2041 { "vpkuhum", VX(4, 14), VX_MASK, PPCVEC, { VD, VA, VB } },
2042 { "vpkuhus", VX(4, 142), VX_MASK, PPCVEC, { VD, VA, VB } },
2043 { "vpkuwum", VX(4, 78), VX_MASK, PPCVEC, { VD, VA, VB } },
2044 { "vpkuwus", VX(4, 206), VX_MASK, PPCVEC, { VD, VA, VB } },
2045 { "vrefp", VX(4, 266), VX_MASK, PPCVEC, { VD, VB } },
2046 { "vrfim", VX(4, 714), VX_MASK, PPCVEC, { VD, VB } },
2047 { "vrfin", VX(4, 522), VX_MASK, PPCVEC, { VD, VB } },
2048 { "vrfip", VX(4, 650), VX_MASK, PPCVEC, { VD, VB } },
2049 { "vrfiz", VX(4, 586), VX_MASK, PPCVEC, { VD, VB } },
2050 { "vrlb", VX(4, 4), VX_MASK, PPCVEC, { VD, VA, VB } },
2051 { "vrlh", VX(4, 68), VX_MASK, PPCVEC, { VD, VA, VB } },
2052 { "vrlw", VX(4, 132), VX_MASK, PPCVEC, { VD, VA, VB } },
2053 { "vrsqrtefp", VX(4, 330), VX_MASK, PPCVEC, { VD, VB } },
2054 { "vsel", VXA(4, 42), VXA_MASK, PPCVEC, { VD, VA, VB, VC } },
2055 { "vsl", VX(4, 452), VX_MASK, PPCVEC, { VD, VA, VB } },
2056 { "vslb", VX(4, 260), VX_MASK, PPCVEC, { VD, VA, VB } },
2057 { "vsldoi", VXA(4, 44), VXA_MASK, PPCVEC, { VD, VA, VB, SHB } },
2058 { "vslh", VX(4, 324), VX_MASK, PPCVEC, { VD, VA, VB } },
2059 { "vslo", VX(4, 1036), VX_MASK, PPCVEC, { VD, VA, VB } },
2060 { "vslw", VX(4, 388), VX_MASK, PPCVEC, { VD, VA, VB } },
2061 { "vspltb", VX(4, 524), VX_MASK, PPCVEC, { VD, VB, UIMM } },
2062 { "vsplth", VX(4, 588), VX_MASK, PPCVEC, { VD, VB, UIMM } },
2063 { "vspltisb", VX(4, 780), VX_MASK, PPCVEC, { VD, SIMM } },
2064 { "vspltish", VX(4, 844), VX_MASK, PPCVEC, { VD, SIMM } },
2065 { "vspltisw", VX(4, 908), VX_MASK, PPCVEC, { VD, SIMM } },
2066 { "vspltw", VX(4, 652), VX_MASK, PPCVEC, { VD, VB, UIMM } },
2067 { "vsr", VX(4, 708), VX_MASK, PPCVEC, { VD, VA, VB } },
2068 { "vsrab", VX(4, 772), VX_MASK, PPCVEC, { VD, VA, VB } },
2069 { "vsrah", VX(4, 836), VX_MASK, PPCVEC, { VD, VA, VB } },
2070 { "vsraw", VX(4, 900), VX_MASK, PPCVEC, { VD, VA, VB } },
2071 { "vsrb", VX(4, 516), VX_MASK, PPCVEC, { VD, VA, VB } },
2072 { "vsrh", VX(4, 580), VX_MASK, PPCVEC, { VD, VA, VB } },
2073 { "vsro", VX(4, 1100), VX_MASK, PPCVEC, { VD, VA, VB } },
2074 { "vsrw", VX(4, 644), VX_MASK, PPCVEC, { VD, VA, VB } },
2075 { "vsubcuw", VX(4, 1408), VX_MASK, PPCVEC, { VD, VA, VB } },
2076 { "vsubfp", VX(4, 74), VX_MASK, PPCVEC, { VD, VA, VB } },
2077 { "vsubsbs", VX(4, 1792), VX_MASK, PPCVEC, { VD, VA, VB } },
2078 { "vsubshs", VX(4, 1856), VX_MASK, PPCVEC, { VD, VA, VB } },
2079 { "vsubsws", VX(4, 1920), VX_MASK, PPCVEC, { VD, VA, VB } },
2080 { "vsububm", VX(4, 1024), VX_MASK, PPCVEC, { VD, VA, VB } },
2081 { "vsububs", VX(4, 1536), VX_MASK, PPCVEC, { VD, VA, VB } },
2082 { "vsubuhm", VX(4, 1088), VX_MASK, PPCVEC, { VD, VA, VB } },
2083 { "vsubuhs", VX(4, 1600), VX_MASK, PPCVEC, { VD, VA, VB } },
2084 { "vsubuwm", VX(4, 1152), VX_MASK, PPCVEC, { VD, VA, VB } },
2085 { "vsubuws", VX(4, 1664), VX_MASK, PPCVEC, { VD, VA, VB } },
2086 { "vsumsws", VX(4, 1928), VX_MASK, PPCVEC, { VD, VA, VB } },
2087 { "vsum2sws", VX(4, 1672), VX_MASK, PPCVEC, { VD, VA, VB } },
2088 { "vsum4sbs", VX(4, 1800), VX_MASK, PPCVEC, { VD, VA, VB } },
2089 { "vsum4shs", VX(4, 1608), VX_MASK, PPCVEC, { VD, VA, VB } },
2090 { "vsum4ubs", VX(4, 1544), VX_MASK, PPCVEC, { VD, VA, VB } },
2091 { "vupkhpx", VX(4, 846), VX_MASK, PPCVEC, { VD, VB } },
2092 { "vupkhsb", VX(4, 526), VX_MASK, PPCVEC, { VD, VB } },
2093 { "vupkhsh", VX(4, 590), VX_MASK, PPCVEC, { VD, VB } },
2094 { "vupklpx", VX(4, 974), VX_MASK, PPCVEC, { VD, VB } },
2095 { "vupklsb", VX(4, 654), VX_MASK, PPCVEC, { VD, VB } },
2096 { "vupklsh", VX(4, 718), VX_MASK, PPCVEC, { VD, VB } },
2097 { "vxor", VX(4, 1220), VX_MASK, PPCVEC, { VD, VA, VB } },
2099 { "evaddw", VX(4, 512), VX_MASK, PPCSPE, { RS, RA, RB } },
2100 { "evaddiw", VX(4, 514), VX_MASK, PPCSPE, { RS, RB, UIMM } },
2101 { "evsubfw", VX(4, 516), VX_MASK, PPCSPE, { RS, RA, RB } },
2102 { "evsubw", VX(4, 516), VX_MASK, PPCSPE, { RS, RB, RA } },
2103 { "evsubifw", VX(4, 518), VX_MASK, PPCSPE, { RS, UIMM, RB } },
2104 { "evsubiw", VX(4, 518), VX_MASK, PPCSPE, { RS, RB, UIMM } },
2105 { "evabs", VX(4, 520), VX_MASK, PPCSPE, { RS, RA } },
2106 { "evneg", VX(4, 521), VX_MASK, PPCSPE, { RS, RA } },
2107 { "evextsb", VX(4, 522), VX_MASK, PPCSPE, { RS, RA } },
2108 { "evextsh", VX(4, 523), VX_MASK, PPCSPE, { RS, RA } },
2109 { "evrndw", VX(4, 524), VX_MASK, PPCSPE, { RS, RA } },
2110 { "evcntlzw", VX(4, 525), VX_MASK, PPCSPE, { RS, RA } },
2111 { "evcntlsw", VX(4, 526), VX_MASK, PPCSPE, { RS, RA } },
2113 { "brinc", VX(4, 527), VX_MASK, PPCSPE, { RS, RA, RB } },
2115 { "evand", VX(4, 529), VX_MASK, PPCSPE, { RS, RA, RB } },
2116 { "evandc", VX(4, 530), VX_MASK, PPCSPE, { RS, RA, RB } },
2117 { "evmr", VX(4, 535), VX_MASK, PPCSPE, { RS, RA, BBA } },
2118 { "evor", VX(4, 535), VX_MASK, PPCSPE, { RS, RA, RB } },
2119 { "evorc", VX(4, 539), VX_MASK, PPCSPE, { RS, RA, RB } },
2120 { "evxor", VX(4, 534), VX_MASK, PPCSPE, { RS, RA, RB } },
2121 { "eveqv", VX(4, 537), VX_MASK, PPCSPE, { RS, RA, RB } },
2122 { "evnand", VX(4, 542), VX_MASK, PPCSPE, { RS, RA, RB } },
2123 { "evnot", VX(4, 536), VX_MASK, PPCSPE, { RS, RA, BBA } },
2124 { "evnor", VX(4, 536), VX_MASK, PPCSPE, { RS, RA, RB } },
2126 { "evrlw", VX(4, 552), VX_MASK, PPCSPE, { RS, RA, RB } },
2127 { "evrlwi", VX(4, 554), VX_MASK, PPCSPE, { RS, RA, EVUIMM } },
2128 { "evslw", VX(4, 548), VX_MASK, PPCSPE, { RS, RA, RB } },
2129 { "evslwi", VX(4, 550), VX_MASK, PPCSPE, { RS, RA, EVUIMM } },
2130 { "evsrws", VX(4, 545), VX_MASK, PPCSPE, { RS, RA, RB } },
2131 { "evsrwu", VX(4, 544), VX_MASK, PPCSPE, { RS, RA, RB } },
2132 { "evsrwis", VX(4, 547), VX_MASK, PPCSPE, { RS, RA, EVUIMM } },
2133 { "evsrwiu", VX(4, 546), VX_MASK, PPCSPE, { RS, RA, EVUIMM } },
2134 { "evsplati", VX(4, 553), VX_MASK, PPCSPE, { RS, SIMM } },
2135 { "evsplatfi", VX(4, 555), VX_MASK, PPCSPE, { RS, SIMM } },
2136 { "evmergehi", VX(4, 556), VX_MASK, PPCSPE, { RS, RA, RB } },
2137 { "evmergelo", VX(4, 557), VX_MASK, PPCSPE, { RS, RA, RB } },
2138 { "evmergehilo",VX(4,558), VX_MASK, PPCSPE, { RS, RA, RB } },
2139 { "evmergelohi",VX(4,559), VX_MASK, PPCSPE, { RS, RA, RB } },
2141 { "evcmpgts", VX(4, 561), VX_MASK, PPCSPE, { CRFD, RA, RB } },
2142 { "evcmpgtu", VX(4, 560), VX_MASK, PPCSPE, { CRFD, RA, RB } },
2143 { "evcmplts", VX(4, 563), VX_MASK, PPCSPE, { CRFD, RA, RB } },
2144 { "evcmpltu", VX(4, 562), VX_MASK, PPCSPE, { CRFD, RA, RB } },
2145 { "evcmpeq", VX(4, 564), VX_MASK, PPCSPE, { CRFD, RA, RB } },
2146 { "evsel", EVSEL(4,79),EVSEL_MASK, PPCSPE, { RS, RA, RB, CRFS } },
2148 { "evldd", VX(4, 769), VX_MASK, PPCSPE, { RS, EVUIMM_8, RA } },
2149 { "evlddx", VX(4, 768), VX_MASK, PPCSPE, { RS, RA, RB } },
2150 { "evldw", VX(4, 771), VX_MASK, PPCSPE, { RS, EVUIMM_8, RA } },
2151 { "evldwx", VX(4, 770), VX_MASK, PPCSPE, { RS, RA, RB } },
2152 { "evldh", VX(4, 773), VX_MASK, PPCSPE, { RS, EVUIMM_8, RA } },
2153 { "evldhx", VX(4, 772), VX_MASK, PPCSPE, { RS, RA, RB } },
2154 { "evlwhe", VX(4, 785), VX_MASK, PPCSPE, { RS, EVUIMM_4, RA } },
2155 { "evlwhex", VX(4, 784), VX_MASK, PPCSPE, { RS, RA, RB } },
2156 { "evlwhou", VX(4, 789), VX_MASK, PPCSPE, { RS, EVUIMM_4, RA } },
2157 { "evlwhoux", VX(4, 788), VX_MASK, PPCSPE, { RS, RA, RB } },
2158 { "evlwhos", VX(4, 791), VX_MASK, PPCSPE, { RS, EVUIMM_4, RA } },
2159 { "evlwhosx", VX(4, 790), VX_MASK, PPCSPE, { RS, RA, RB } },
2160 { "evlwwsplat",VX(4, 793), VX_MASK, PPCSPE, { RS, EVUIMM_4, RA } },
2161 { "evlwwsplatx",VX(4, 792), VX_MASK, PPCSPE, { RS, RA, RB } },
2162 { "evlwhsplat",VX(4, 797), VX_MASK, PPCSPE, { RS, EVUIMM_4, RA } },
2163 { "evlwhsplatx",VX(4, 796), VX_MASK, PPCSPE, { RS, RA, RB } },
2164 { "evlhhesplat",VX(4, 777), VX_MASK, PPCSPE, { RS, EVUIMM_2, RA } },
2165 { "evlhhesplatx",VX(4, 776), VX_MASK, PPCSPE, { RS, RA, RB } },
2166 { "evlhhousplat",VX(4, 781), VX_MASK, PPCSPE, { RS, EVUIMM_2, RA } },
2167 { "evlhhousplatx",VX(4, 780), VX_MASK, PPCSPE, { RS, RA, RB } },
2168 { "evlhhossplat",VX(4, 783), VX_MASK, PPCSPE, { RS, EVUIMM_2, RA } },
2169 { "evlhhossplatx",VX(4, 782), VX_MASK, PPCSPE, { RS, RA, RB } },
2171 { "evstdd", VX(4, 801), VX_MASK, PPCSPE, { RS, EVUIMM_8, RA } },
2172 { "evstddx", VX(4, 800), VX_MASK, PPCSPE, { RS, RA, RB } },
2173 { "evstdw", VX(4, 803), VX_MASK, PPCSPE, { RS, EVUIMM_8, RA } },
2174 { "evstdwx", VX(4, 802), VX_MASK, PPCSPE, { RS, RA, RB } },
2175 { "evstdh", VX(4, 805), VX_MASK, PPCSPE, { RS, EVUIMM_8, RA } },
2176 { "evstdhx", VX(4, 804), VX_MASK, PPCSPE, { RS, RA, RB } },
2177 { "evstwwe", VX(4, 825), VX_MASK, PPCSPE, { RS, EVUIMM_4, RA } },
2178 { "evstwwex", VX(4, 824), VX_MASK, PPCSPE, { RS, RA, RB } },
2179 { "evstwwo", VX(4, 829), VX_MASK, PPCSPE, { RS, EVUIMM_4, RA } },
2180 { "evstwwox", VX(4, 828), VX_MASK, PPCSPE, { RS, RA, RB } },
2181 { "evstwhe", VX(4, 817), VX_MASK, PPCSPE, { RS, EVUIMM_4, RA } },
2182 { "evstwhex", VX(4, 816), VX_MASK, PPCSPE, { RS, RA, RB } },
2183 { "evstwho", VX(4, 821), VX_MASK, PPCSPE, { RS, EVUIMM_4, RA } },
2184 { "evstwhox", VX(4, 820), VX_MASK, PPCSPE, { RS, RA, RB } },
2186 { "evfsabs", VX(4, 644), VX_MASK, PPCSPE, { RS, RA } },
2187 { "evfsnabs", VX(4, 645), VX_MASK, PPCSPE, { RS, RA } },
2188 { "evfsneg", VX(4, 646), VX_MASK, PPCSPE, { RS, RA } },
2189 { "evfsadd", VX(4, 640), VX_MASK, PPCSPE, { RS, RA, RB } },
2190 { "evfssub", VX(4, 641), VX_MASK, PPCSPE, { RS, RA, RB } },
2191 { "evfsmul", VX(4, 648), VX_MASK, PPCSPE, { RS, RA, RB } },
2192 { "evfsdiv", VX(4, 649), VX_MASK, PPCSPE, { RS, RA, RB } },
2193 { "evfscmpgt", VX(4, 652), VX_MASK, PPCSPE, { CRFD, RA, RB } },
2194 { "evfscmplt", VX(4, 653), VX_MASK, PPCSPE, { CRFD, RA, RB } },
2195 { "evfscmpeq", VX(4, 654), VX_MASK, PPCSPE, { CRFD, RA, RB } },
2196 { "evfststgt", VX(4, 668), VX_MASK, PPCSPE, { CRFD, RA, RB } },
2197 { "evfststlt", VX(4, 669), VX_MASK, PPCSPE, { CRFD, RA, RB } },
2198 { "evfststeq", VX(4, 670), VX_MASK, PPCSPE, { CRFD, RA, RB } },
2199 { "evfscfui", VX(4, 656), VX_MASK, PPCSPE, { RS, RB } },
2200 { "evfsctuiz", VX(4, 664), VX_MASK, PPCSPE, { RS, RB } },
2201 { "evfscfsi", VX(4, 657), VX_MASK, PPCSPE, { RS, RB } },
2202 { "evfscfuf", VX(4, 658), VX_MASK, PPCSPE, { RS, RB } },
2203 { "evfscfsf", VX(4, 659), VX_MASK, PPCSPE, { RS, RB } },
2204 { "evfsctui", VX(4, 660), VX_MASK, PPCSPE, { RS, RB } },
2205 { "evfsctsi", VX(4, 661), VX_MASK, PPCSPE, { RS, RB } },
2206 { "evfsctsiz", VX(4, 666), VX_MASK, PPCSPE, { RS, RB } },
2207 { "evfsctuf", VX(4, 662), VX_MASK, PPCSPE, { RS, RB } },
2208 { "evfsctsf", VX(4, 663), VX_MASK, PPCSPE, { RS, RB } },
2210 { "efsabs", VX(4, 708), VX_MASK, PPCEFS, { RS, RA } },
2211 { "efsnabs", VX(4, 709), VX_MASK, PPCEFS, { RS, RA } },
2212 { "efsneg", VX(4, 710), VX_MASK, PPCEFS, { RS, RA } },
2213 { "efsadd", VX(4, 704), VX_MASK, PPCEFS, { RS, RA, RB } },
2214 { "efssub", VX(4, 705), VX_MASK, PPCEFS, { RS, RA, RB } },
2215 { "efsmul", VX(4, 712), VX_MASK, PPCEFS, { RS, RA, RB } },
2216 { "efsdiv", VX(4, 713), VX_MASK, PPCEFS, { RS, RA, RB } },
2217 { "efscmpgt", VX(4, 716), VX_MASK, PPCEFS, { CRFD, RA, RB } },
2218 { "efscmplt", VX(4, 717), VX_MASK, PPCEFS, { CRFD, RA, RB } },
2219 { "efscmpeq", VX(4, 718), VX_MASK, PPCEFS, { CRFD, RA, RB } },
2220 { "efststgt", VX(4, 732), VX_MASK, PPCEFS, { CRFD, RA, RB } },
2221 { "efststlt", VX(4, 733), VX_MASK, PPCEFS, { CRFD, RA, RB } },
2222 { "efststeq", VX(4, 734), VX_MASK, PPCEFS, { CRFD, RA, RB } },
2223 { "efscfui", VX(4, 720), VX_MASK, PPCEFS, { RS, RB } },
2224 { "efsctuiz", VX(4, 728), VX_MASK, PPCEFS, { RS, RB } },
2225 { "efscfsi", VX(4, 721), VX_MASK, PPCEFS, { RS, RB } },
2226 { "efscfuf", VX(4, 722), VX_MASK, PPCEFS, { RS, RB } },
2227 { "efscfsf", VX(4, 723), VX_MASK, PPCEFS, { RS, RB } },
2228 { "efsctui", VX(4, 724), VX_MASK, PPCEFS, { RS, RB } },
2229 { "efsctsi", VX(4, 725), VX_MASK, PPCEFS, { RS, RB } },
2230 { "efsctsiz", VX(4, 730), VX_MASK, PPCEFS, { RS, RB } },
2231 { "efsctuf", VX(4, 726), VX_MASK, PPCEFS, { RS, RB } },
2232 { "efsctsf", VX(4, 727), VX_MASK, PPCEFS, { RS, RB } },
2234 { "evmhossf", VX(4, 1031), VX_MASK, PPCSPE, { RS, RA, RB } },
2235 { "evmhossfa", VX(4, 1063), VX_MASK, PPCSPE, { RS, RA, RB } },
2236 { "evmhosmf", VX(4, 1039), VX_MASK, PPCSPE, { RS, RA, RB } },
2237 { "evmhosmfa", VX(4, 1071), VX_MASK, PPCSPE, { RS, RA, RB } },
2238 { "evmhosmi", VX(4, 1037), VX_MASK, PPCSPE, { RS, RA, RB } },
2239 { "evmhosmia", VX(4, 1069), VX_MASK, PPCSPE, { RS, RA, RB } },
2240 { "evmhoumi", VX(4, 1036), VX_MASK, PPCSPE, { RS, RA, RB } },
2241 { "evmhoumia", VX(4, 1068), VX_MASK, PPCSPE, { RS, RA, RB } },
2242 { "evmhessf", VX(4, 1027), VX_MASK, PPCSPE, { RS, RA, RB } },
2243 { "evmhessfa", VX(4, 1059), VX_MASK, PPCSPE, { RS, RA, RB } },
2244 { "evmhesmf", VX(4, 1035), VX_MASK, PPCSPE, { RS, RA, RB } },
2245 { "evmhesmfa", VX(4, 1067), VX_MASK, PPCSPE, { RS, RA, RB } },
2246 { "evmhesmi", VX(4, 1033), VX_MASK, PPCSPE, { RS, RA, RB } },
2247 { "evmhesmia", VX(4, 1065), VX_MASK, PPCSPE, { RS, RA, RB } },
2248 { "evmheumi", VX(4, 1032), VX_MASK, PPCSPE, { RS, RA, RB } },
2249 { "evmheumia", VX(4, 1064), VX_MASK, PPCSPE, { RS, RA, RB } },
2251 { "evmhossfaaw",VX(4, 1287), VX_MASK, PPCSPE, { RS, RA, RB } },
2252 { "evmhossiaaw",VX(4, 1285), VX_MASK, PPCSPE, { RS, RA, RB } },
2253 { "evmhosmfaaw",VX(4, 1295), VX_MASK, PPCSPE, { RS, RA, RB } },
2254 { "evmhosmiaaw",VX(4, 1293), VX_MASK, PPCSPE, { RS, RA, RB } },
2255 { "evmhousiaaw",VX(4, 1284), VX_MASK, PPCSPE, { RS, RA, RB } },
2256 { "evmhoumiaaw",VX(4, 1292), VX_MASK, PPCSPE, { RS, RA, RB } },
2257 { "evmhessfaaw",VX(4, 1283), VX_MASK, PPCSPE, { RS, RA, RB } },
2258 { "evmhessiaaw",VX(4, 1281), VX_MASK, PPCSPE, { RS, RA, RB } },
2259 { "evmhesmfaaw",VX(4, 1291), VX_MASK, PPCSPE, { RS, RA, RB } },
2260 { "evmhesmiaaw",VX(4, 1289), VX_MASK, PPCSPE, { RS, RA, RB } },
2261 { "evmheusiaaw",VX(4, 1280), VX_MASK, PPCSPE, { RS, RA, RB } },
2262 { "evmheumiaaw",VX(4, 1288), VX_MASK, PPCSPE, { RS, RA, RB } },
2264 { "evmhossfanw",VX(4, 1415), VX_MASK, PPCSPE, { RS, RA, RB } },
2265 { "evmhossianw",VX(4, 1413), VX_MASK, PPCSPE, { RS, RA, RB } },
2266 { "evmhosmfanw",VX(4, 1423), VX_MASK, PPCSPE, { RS, RA, RB } },
2267 { "evmhosmianw",VX(4, 1421), VX_MASK, PPCSPE, { RS, RA, RB } },
2268 { "evmhousianw",VX(4, 1412), VX_MASK, PPCSPE, { RS, RA, RB } },
2269 { "evmhoumianw",VX(4, 1420), VX_MASK, PPCSPE, { RS, RA, RB } },
2270 { "evmhessfanw",VX(4, 1411), VX_MASK, PPCSPE, { RS, RA, RB } },
2271 { "evmhessianw",VX(4, 1409), VX_MASK, PPCSPE, { RS, RA, RB } },
2272 { "evmhesmfanw",VX(4, 1419), VX_MASK, PPCSPE, { RS, RA, RB } },
2273 { "evmhesmianw",VX(4, 1417), VX_MASK, PPCSPE, { RS, RA, RB } },
2274 { "evmheusianw",VX(4, 1408), VX_MASK, PPCSPE, { RS, RA, RB } },
2275 { "evmheumianw",VX(4, 1416), VX_MASK, PPCSPE, { RS, RA, RB } },
2277 { "evmhogsmfaa",VX(4, 1327), VX_MASK, PPCSPE, { RS, RA, RB } },
2278 { "evmhogsmiaa",VX(4, 1325), VX_MASK, PPCSPE, { RS, RA, RB } },
2279 { "evmhogumiaa",VX(4, 1324), VX_MASK, PPCSPE, { RS, RA, RB } },
2280 { "evmhegsmfaa",VX(4, 1323), VX_MASK, PPCSPE, { RS, RA, RB } },
2281 { "evmhegsmiaa",VX(4, 1321), VX_MASK, PPCSPE, { RS, RA, RB } },
2282 { "evmhegumiaa",VX(4, 1320), VX_MASK, PPCSPE, { RS, RA, RB } },
2284 { "evmhogsmfan",VX(4, 1455), VX_MASK, PPCSPE, { RS, RA, RB } },
2285 { "evmhogsmian",VX(4, 1453), VX_MASK, PPCSPE, { RS, RA, RB } },
2286 { "evmhogumian",VX(4, 1452), VX_MASK, PPCSPE, { RS, RA, RB } },
2287 { "evmhegsmfan",VX(4, 1451), VX_MASK, PPCSPE, { RS, RA, RB } },
2288 { "evmhegsmian",VX(4, 1449), VX_MASK, PPCSPE, { RS, RA, RB } },
2289 { "evmhegumian",VX(4, 1448), VX_MASK, PPCSPE, { RS, RA, RB } },
2291 { "evmwhssf", VX(4, 1095), VX_MASK, PPCSPE, { RS, RA, RB } },
2292 { "evmwhssfa", VX(4, 1127), VX_MASK, PPCSPE, { RS, RA, RB } },
2293 { "evmwhsmf", VX(4, 1103), VX_MASK, PPCSPE, { RS, RA, RB } },
2294 { "evmwhsmfa", VX(4, 1135), VX_MASK, PPCSPE, { RS, RA, RB } },
2295 { "evmwhsmi", VX(4, 1101), VX_MASK, PPCSPE, { RS, RA, RB } },
2296 { "evmwhsmia", VX(4, 1133), VX_MASK, PPCSPE, { RS, RA, RB } },
2297 { "evmwhumi", VX(4, 1100), VX_MASK, PPCSPE, { RS, RA, RB } },
2298 { "evmwhumia", VX(4, 1132), VX_MASK, PPCSPE, { RS, RA, RB } },
2300 { "evmwlumi", VX(4, 1096), VX_MASK, PPCSPE, { RS, RA, RB } },
2301 { "evmwlumia", VX(4, 1128), VX_MASK, PPCSPE, { RS, RA, RB } },
2303 { "evmwlssiaaw",VX(4, 1345), VX_MASK, PPCSPE, { RS, RA, RB } },
2304 { "evmwlsmiaaw",VX(4, 1353), VX_MASK, PPCSPE, { RS, RA, RB } },
2305 { "evmwlusiaaw",VX(4, 1344), VX_MASK, PPCSPE, { RS, RA, RB } },
2306 { "evmwlumiaaw",VX(4, 1352), VX_MASK, PPCSPE, { RS, RA, RB } },
2308 { "evmwlssianw",VX(4, 1473), VX_MASK, PPCSPE, { RS, RA, RB } },
2309 { "evmwlsmianw",VX(4, 1481), VX_MASK, PPCSPE, { RS, RA, RB } },
2310 { "evmwlusianw",VX(4, 1472), VX_MASK, PPCSPE, { RS, RA, RB } },
2311 { "evmwlumianw",VX(4, 1480), VX_MASK, PPCSPE, { RS, RA, RB } },
2313 { "evmwssf", VX(4, 1107), VX_MASK, PPCSPE, { RS, RA, RB } },
2314 { "evmwssfa", VX(4, 1139), VX_MASK, PPCSPE, { RS, RA, RB } },
2315 { "evmwsmf", VX(4, 1115), VX_MASK, PPCSPE, { RS, RA, RB } },
2316 { "evmwsmfa", VX(4, 1147), VX_MASK, PPCSPE, { RS, RA, RB } },
2317 { "evmwsmi", VX(4, 1113), VX_MASK, PPCSPE, { RS, RA, RB } },
2318 { "evmwsmia", VX(4, 1145), VX_MASK, PPCSPE, { RS, RA, RB } },
2319 { "evmwumi", VX(4, 1112), VX_MASK, PPCSPE, { RS, RA, RB } },
2320 { "evmwumia", VX(4, 1144), VX_MASK, PPCSPE, { RS, RA, RB } },
2322 { "evmwssfaa", VX(4, 1363), VX_MASK, PPCSPE, { RS, RA, RB } },
2323 { "evmwsmfaa", VX(4, 1371), VX_MASK, PPCSPE, { RS, RA, RB } },
2324 { "evmwsmiaa", VX(4, 1369), VX_MASK, PPCSPE, { RS, RA, RB } },
2325 { "evmwumiaa", VX(4, 1368), VX_MASK, PPCSPE, { RS, RA, RB } },
2327 { "evmwssfan", VX(4, 1491), VX_MASK, PPCSPE, { RS, RA, RB } },
2328 { "evmwsmfan", VX(4, 1499), VX_MASK, PPCSPE, { RS, RA, RB } },
2329 { "evmwsmian", VX(4, 1497), VX_MASK, PPCSPE, { RS, RA, RB } },
2330 { "evmwumian", VX(4, 1496), VX_MASK, PPCSPE, { RS, RA, RB } },
2332 { "evaddssiaaw",VX(4, 1217), VX_MASK, PPCSPE, { RS, RA } },
2333 { "evaddsmiaaw",VX(4, 1225), VX_MASK, PPCSPE, { RS, RA } },
2334 { "evaddusiaaw",VX(4, 1216), VX_MASK, PPCSPE, { RS, RA } },
2335 { "evaddumiaaw",VX(4, 1224), VX_MASK, PPCSPE, { RS, RA } },
2337 { "evsubfssiaaw",VX(4, 1219), VX_MASK, PPCSPE, { RS, RA } },
2338 { "evsubfsmiaaw",VX(4, 1227), VX_MASK, PPCSPE, { RS, RA } },
2339 { "evsubfusiaaw",VX(4, 1218), VX_MASK, PPCSPE, { RS, RA } },
2340 { "evsubfumiaaw",VX(4, 1226), VX_MASK, PPCSPE, { RS, RA } },
2342 { "evmra", VX(4, 1220), VX_MASK, PPCSPE, { RS, RA } },
2344 { "evdivws", VX(4, 1222), VX_MASK, PPCSPE, { RS, RA, RB } },
2345 { "evdivwu", VX(4, 1223), VX_MASK, PPCSPE, { RS, RA, RB } },
2347 { "mulli", OP(7), OP_MASK, PPCCOM, { RT, RA, SI } },
2348 { "muli", OP(7), OP_MASK, PWRCOM, { RT, RA, SI } },
2350 { "subfic", OP(8), OP_MASK, PPCCOM, { RT, RA, SI } },
2351 { "sfi", OP(8), OP_MASK, PWRCOM, { RT, RA, SI } },
2353 { "dozi", OP(9), OP_MASK, M601, { RT, RA, SI } },
2355 { "bce", B(9,0,0), B_MASK, BOOKE64, { BO, BI, BD } },
2356 { "bcel", B(9,0,1), B_MASK, BOOKE64, { BO, BI, BD } },
2357 { "bcea", B(9,1,0), B_MASK, BOOKE64, { BO, BI, BDA } },
2358 { "bcela", B(9,1,1), B_MASK, BOOKE64, { BO, BI, BDA } },
2360 { "cmplwi", OPL(10,0), OPL_MASK, PPCCOM, { OBF, RA, UI } },
2361 { "cmpldi", OPL(10,1), OPL_MASK, PPC64, { OBF, RA, UI } },
2362 { "cmpli", OP(10), OP_MASK, PPC, { BF, L, RA, UI } },
2363 { "cmpli", OP(10), OP_MASK, PWRCOM, { BF, RA, UI } },
2365 { "cmpwi", OPL(11,0), OPL_MASK, PPCCOM, { OBF, RA, SI } },
2366 { "cmpdi", OPL(11,1), OPL_MASK, PPC64, { OBF, RA, SI } },
2367 { "cmpi", OP(11), OP_MASK, PPC, { BF, L, RA, SI } },
2368 { "cmpi", OP(11), OP_MASK, PWRCOM, { BF, RA, SI } },
2370 { "addic", OP(12), OP_MASK, PPCCOM, { RT, RA, SI } },
2371 { "ai", OP(12), OP_MASK, PWRCOM, { RT, RA, SI } },
2372 { "subic", OP(12), OP_MASK, PPCCOM, { RT, RA, NSI } },
2374 { "addic.", OP(13), OP_MASK, PPCCOM, { RT, RA, SI } },
2375 { "ai.", OP(13), OP_MASK, PWRCOM, { RT, RA, SI } },
2376 { "subic.", OP(13), OP_MASK, PPCCOM, { RT, RA, NSI } },
2378 { "li", OP(14), DRA_MASK, PPCCOM, { RT, SI } },
2379 { "lil", OP(14), DRA_MASK, PWRCOM, { RT, SI } },
2380 { "addi", OP(14), OP_MASK, PPCCOM, { RT, RA0, SI } },
2381 { "cal", OP(14), OP_MASK, PWRCOM, { RT, D, RA0 } },
2382 { "subi", OP(14), OP_MASK, PPCCOM, { RT, RA0, NSI } },
2383 { "la", OP(14), OP_MASK, PPCCOM, { RT, D, RA0 } },
2385 { "lis", OP(15), DRA_MASK, PPCCOM, { RT, SISIGNOPT } },
2386 { "liu", OP(15), DRA_MASK, PWRCOM, { RT, SISIGNOPT } },
2387 { "addis", OP(15), OP_MASK, PPCCOM, { RT,RA0,SISIGNOPT } },
2388 { "cau", OP(15), OP_MASK, PWRCOM, { RT,RA0,SISIGNOPT } },
2389 { "subis", OP(15), OP_MASK, PPCCOM, { RT, RA0, NSI } },
2391 { "bdnz-", BBO(16,BODNZ,0,0), BBOATBI_MASK, PPCCOM, { BDM } },
2392 { "bdnz+", BBO(16,BODNZ,0,0), BBOATBI_MASK, PPCCOM, { BDP } },
2393 { "bdnz", BBO(16,BODNZ,0,0), BBOATBI_MASK, PPCCOM, { BD } },
2394 { "bdn", BBO(16,BODNZ,0,0), BBOATBI_MASK, PWRCOM, { BD } },
2395 { "bdnzl-", BBO(16,BODNZ,0,1), BBOATBI_MASK, PPCCOM, { BDM } },
2396 { "bdnzl+", BBO(16,BODNZ,0,1), BBOATBI_MASK, PPCCOM, { BDP } },
2397 { "bdnzl", BBO(16,BODNZ,0,1), BBOATBI_MASK, PPCCOM, { BD } },
2398 { "bdnl", BBO(16,BODNZ,0,1), BBOATBI_MASK, PWRCOM, { BD } },
2399 { "bdnza-", BBO(16,BODNZ,1,0), BBOATBI_MASK, PPCCOM, { BDMA } },
2400 { "bdnza+", BBO(16,BODNZ,1,0), BBOATBI_MASK, PPCCOM, { BDPA } },
2401 { "bdnza", BBO(16,BODNZ,1,0), BBOATBI_MASK, PPCCOM, { BDA } },
2402 { "bdna", BBO(16,BODNZ,1,0), BBOATBI_MASK, PWRCOM, { BDA } },
2403 { "bdnzla-", BBO(16,BODNZ,1,1), BBOATBI_MASK, PPCCOM, { BDMA } },
2404 { "bdnzla+", BBO(16,BODNZ,1,1), BBOATBI_MASK, PPCCOM, { BDPA } },
2405 { "bdnzla", BBO(16,BODNZ,1,1), BBOATBI_MASK, PPCCOM, { BDA } },
2406 { "bdnla", BBO(16,BODNZ,1,1), BBOATBI_MASK, PWRCOM, { BDA } },
2407 { "bdz-", BBO(16,BODZ,0,0), BBOATBI_MASK, PPCCOM, { BDM } },
2408 { "bdz+", BBO(16,BODZ,0,0), BBOATBI_MASK, PPCCOM, { BDP } },
2409 { "bdz", BBO(16,BODZ,0,0), BBOATBI_MASK, COM, { BD } },
2410 { "bdzl-", BBO(16,BODZ,0,1), BBOATBI_MASK, PPCCOM, { BDM } },
2411 { "bdzl+", BBO(16,BODZ,0,1), BBOATBI_MASK, PPCCOM, { BDP } },
2412 { "bdzl", BBO(16,BODZ,0,1), BBOATBI_MASK, COM, { BD } },
2413 { "bdza-", BBO(16,BODZ,1,0), BBOATBI_MASK, PPCCOM, { BDMA } },
2414 { "bdza+", BBO(16,BODZ,1,0), BBOATBI_MASK, PPCCOM, { BDPA } },
2415 { "bdza", BBO(16,BODZ,1,0), BBOATBI_MASK, COM, { BDA } },
2416 { "bdzla-", BBO(16,BODZ,1,1), BBOATBI_MASK, PPCCOM, { BDMA } },
2417 { "bdzla+", BBO(16,BODZ,1,1), BBOATBI_MASK, PPCCOM, { BDPA } },
2418 { "bdzla", BBO(16,BODZ,1,1), BBOATBI_MASK, COM, { BDA } },
2419 { "blt-", BBOCB(16,BOT,CBLT,0,0), BBOATCB_MASK, PPCCOM, { CR, BDM } },
2420 { "blt+", BBOCB(16,BOT,CBLT,0,0), BBOATCB_MASK, PPCCOM, { CR, BDP } },
2421 { "blt", BBOCB(16,BOT,CBLT,0,0), BBOATCB_MASK, COM, { CR, BD } },
2422 { "bltl-", BBOCB(16,BOT,CBLT,0,1), BBOATCB_MASK, PPCCOM, { CR, BDM } },
2423 { "bltl+", BBOCB(16,BOT,CBLT,0,1), BBOATCB_MASK, PPCCOM, { CR, BDP } },
2424 { "bltl", BBOCB(16,BOT,CBLT,0,1), BBOATCB_MASK, COM, { CR, BD } },
2425 { "blta-", BBOCB(16,BOT,CBLT,1,0), BBOATCB_MASK, PPCCOM, { CR, BDMA } },
2426 { "blta+", BBOCB(16,BOT,CBLT,1,0), BBOATCB_MASK, PPCCOM, { CR, BDPA } },
2427 { "blta", BBOCB(16,BOT,CBLT,1,0), BBOATCB_MASK, COM, { CR, BDA } },
2428 { "bltla-", BBOCB(16,BOT,CBLT,1,1), BBOATCB_MASK, PPCCOM, { CR, BDMA } },
2429 { "bltla+", BBOCB(16,BOT,CBLT,1,1), BBOATCB_MASK, PPCCOM, { CR, BDPA } },
2430 { "bltla", BBOCB(16,BOT,CBLT,1,1), BBOATCB_MASK, COM, { CR, BDA } },
2431 { "bgt-", BBOCB(16,BOT,CBGT,0,0), BBOATCB_MASK, PPCCOM, { CR, BDM } },
2432 { "bgt+", BBOCB(16,BOT,CBGT,0,0), BBOATCB_MASK, PPCCOM, { CR, BDP } },
2433 { "bgt", BBOCB(16,BOT,CBGT,0,0), BBOATCB_MASK, COM, { CR, BD } },
2434 { "bgtl-", BBOCB(16,BOT,CBGT,0,1), BBOATCB_MASK, PPCCOM, { CR, BDM } },
2435 { "bgtl+", BBOCB(16,BOT,CBGT,0,1), BBOATCB_MASK, PPCCOM, { CR, BDP } },
2436 { "bgtl", BBOCB(16,BOT,CBGT,0,1), BBOATCB_MASK, COM, { CR, BD } },
2437 { "bgta-", BBOCB(16,BOT,CBGT,1,0), BBOATCB_MASK, PPCCOM, { CR, BDMA } },
2438 { "bgta+", BBOCB(16,BOT,CBGT,1,0), BBOATCB_MASK, PPCCOM, { CR, BDPA } },
2439 { "bgta", BBOCB(16,BOT,CBGT,1,0), BBOATCB_MASK, COM, { CR, BDA } },
2440 { "bgtla-", BBOCB(16,BOT,CBGT,1,1), BBOATCB_MASK, PPCCOM, { CR, BDMA } },
2441 { "bgtla+", BBOCB(16,BOT,CBGT,1,1), BBOATCB_MASK, PPCCOM, { CR, BDPA } },
2442 { "bgtla", BBOCB(16,BOT,CBGT,1,1), BBOATCB_MASK, COM, { CR, BDA } },
2443 { "beq-", BBOCB(16,BOT,CBEQ,0,0), BBOATCB_MASK, PPCCOM, { CR, BDM } },
2444 { "beq+", BBOCB(16,BOT,CBEQ,0,0), BBOATCB_MASK, PPCCOM, { CR, BDP } },
2445 { "beq", BBOCB(16,BOT,CBEQ,0,0), BBOATCB_MASK, COM, { CR, BD } },
2446 { "beql-", BBOCB(16,BOT,CBEQ,0,1), BBOATCB_MASK, PPCCOM, { CR, BDM } },
2447 { "beql+", BBOCB(16,BOT,CBEQ,0,1), BBOATCB_MASK, PPCCOM, { CR, BDP } },
2448 { "beql", BBOCB(16,BOT,CBEQ,0,1), BBOATCB_MASK, COM, { CR, BD } },
2449 { "beqa-", BBOCB(16,BOT,CBEQ,1,0), BBOATCB_MASK, PPCCOM, { CR, BDMA } },
2450 { "beqa+", BBOCB(16,BOT,CBEQ,1,0), BBOATCB_MASK, PPCCOM, { CR, BDPA } },
2451 { "beqa", BBOCB(16,BOT,CBEQ,1,0), BBOATCB_MASK, COM, { CR, BDA } },
2452 { "beqla-", BBOCB(16,BOT,CBEQ,1,1), BBOATCB_MASK, PPCCOM, { CR, BDMA } },
2453 { "beqla+", BBOCB(16,BOT,CBEQ,1,1), BBOATCB_MASK, PPCCOM, { CR, BDPA } },
2454 { "beqla", BBOCB(16,BOT,CBEQ,1,1), BBOATCB_MASK, COM, { CR, BDA } },
2455 { "bso-", BBOCB(16,BOT,CBSO,0,0), BBOATCB_MASK, PPCCOM, { CR, BDM } },
2456 { "bso+", BBOCB(16,BOT,CBSO,0,0), BBOATCB_MASK, PPCCOM, { CR, BDP } },
2457 { "bso", BBOCB(16,BOT,CBSO,0,0), BBOATCB_MASK, COM, { CR, BD } },
2458 { "bsol-", BBOCB(16,BOT,CBSO,0,1), BBOATCB_MASK, PPCCOM, { CR, BDM } },
2459 { "bsol+", BBOCB(16,BOT,CBSO,0,1), BBOATCB_MASK, PPCCOM, { CR, BDP } },
2460 { "bsol", BBOCB(16,BOT,CBSO,0,1), BBOATCB_MASK, COM, { CR, BD } },
2461 { "bsoa-", BBOCB(16,BOT,CBSO,1,0), BBOATCB_MASK, PPCCOM, { CR, BDMA } },
2462 { "bsoa+", BBOCB(16,BOT,CBSO,1,0), BBOATCB_MASK, PPCCOM, { CR, BDPA } },
2463 { "bsoa", BBOCB(16,BOT,CBSO,1,0), BBOATCB_MASK, COM, { CR, BDA } },
2464 { "bsola-", BBOCB(16,BOT,CBSO,1,1), BBOATCB_MASK, PPCCOM, { CR, BDMA } },
2465 { "bsola+", BBOCB(16,BOT,CBSO,1,1), BBOATCB_MASK, PPCCOM, { CR, BDPA } },
2466 { "bsola", BBOCB(16,BOT,CBSO,1,1), BBOATCB_MASK, COM, { CR, BDA } },
2467 { "bun-", BBOCB(16,BOT,CBSO,0,0), BBOATCB_MASK, PPCCOM, { CR, BDM } },
2468 { "bun+", BBOCB(16,BOT,CBSO,0,0), BBOATCB_MASK, PPCCOM, { CR, BDP } },
2469 { "bun", BBOCB(16,BOT,CBSO,0,0), BBOATCB_MASK, PPCCOM, { CR, BD } },
2470 { "bunl-", BBOCB(16,BOT,CBSO,0,1), BBOATCB_MASK, PPCCOM, { CR, BDM } },
2471 { "bunl+", BBOCB(16,BOT,CBSO,0,1), BBOATCB_MASK, PPCCOM, { CR, BDP } },
2472 { "bunl", BBOCB(16,BOT,CBSO,0,1), BBOATCB_MASK, PPCCOM, { CR, BD } },
2473 { "buna-", BBOCB(16,BOT,CBSO,1,0), BBOATCB_MASK, PPCCOM, { CR, BDMA } },
2474 { "buna+", BBOCB(16,BOT,CBSO,1,0), BBOATCB_MASK, PPCCOM, { CR, BDPA } },
2475 { "buna", BBOCB(16,BOT,CBSO,1,0), BBOATCB_MASK, PPCCOM, { CR, BDA } },
2476 { "bunla-", BBOCB(16,BOT,CBSO,1,1), BBOATCB_MASK, PPCCOM, { CR, BDMA } },
2477 { "bunla+", BBOCB(16,BOT,CBSO,1,1), BBOATCB_MASK, PPCCOM, { CR, BDPA } },
2478 { "bunla", BBOCB(16,BOT,CBSO,1,1), BBOATCB_MASK, PPCCOM, { CR, BDA } },
2479 { "bge-", BBOCB(16,BOF,CBLT,0,0), BBOATCB_MASK, PPCCOM, { CR, BDM } },
2480 { "bge+", BBOCB(16,BOF,CBLT,0,0), BBOATCB_MASK, PPCCOM, { CR, BDP } },
2481 { "bge", BBOCB(16,BOF,CBLT,0,0), BBOATCB_MASK, COM, { CR, BD } },
2482 { "bgel-", BBOCB(16,BOF,CBLT,0,1), BBOATCB_MASK, PPCCOM, { CR, BDM } },
2483 { "bgel+", BBOCB(16,BOF,CBLT,0,1), BBOATCB_MASK, PPCCOM, { CR, BDP } },
2484 { "bgel", BBOCB(16,BOF,CBLT,0,1), BBOATCB_MASK, COM, { CR, BD } },
2485 { "bgea-", BBOCB(16,BOF,CBLT,1,0), BBOATCB_MASK, PPCCOM, { CR, BDMA } },
2486 { "bgea+", BBOCB(16,BOF,CBLT,1,0), BBOATCB_MASK, PPCCOM, { CR, BDPA } },
2487 { "bgea", BBOCB(16,BOF,CBLT,1,0), BBOATCB_MASK, COM, { CR, BDA } },
2488 { "bgela-", BBOCB(16,BOF,CBLT,1,1), BBOATCB_MASK, PPCCOM, { CR, BDMA } },
2489 { "bgela+", BBOCB(16,BOF,CBLT,1,1), BBOATCB_MASK, PPCCOM, { CR, BDPA } },
2490 { "bgela", BBOCB(16,BOF,CBLT,1,1), BBOATCB_MASK, COM, { CR, BDA } },
2491 { "bnl-", BBOCB(16,BOF,CBLT,0,0), BBOATCB_MASK, PPCCOM, { CR, BDM } },
2492 { "bnl+", BBOCB(16,BOF,CBLT,0,0), BBOATCB_MASK, PPCCOM, { CR, BDP } },
2493 { "bnl", BBOCB(16,BOF,CBLT,0,0), BBOATCB_MASK, COM, { CR, BD } },
2494 { "bnll-", BBOCB(16,BOF,CBLT,0,1), BBOATCB_MASK, PPCCOM, { CR, BDM } },
2495 { "bnll+", BBOCB(16,BOF,CBLT,0,1), BBOATCB_MASK, PPCCOM, { CR, BDP } },
2496 { "bnll", BBOCB(16,BOF,CBLT,0,1), BBOATCB_MASK, COM, { CR, BD } },
2497 { "bnla-", BBOCB(16,BOF,CBLT,1,0), BBOATCB_MASK, PPCCOM, { CR, BDMA } },
2498 { "bnla+", BBOCB(16,BOF,CBLT,1,0), BBOATCB_MASK, PPCCOM, { CR, BDPA } },
2499 { "bnla", BBOCB(16,BOF,CBLT,1,0), BBOATCB_MASK, COM, { CR, BDA } },
2500 { "bnlla-", BBOCB(16,BOF,CBLT,1,1), BBOATCB_MASK, PPCCOM, { CR, BDMA } },
2501 { "bnlla+", BBOCB(16,BOF,CBLT,1,1), BBOATCB_MASK, PPCCOM, { CR, BDPA } },
2502 { "bnlla", BBOCB(16,BOF,CBLT,1,1), BBOATCB_MASK, COM, { CR, BDA } },
2503 { "ble-", BBOCB(16,BOF,CBGT,0,0), BBOATCB_MASK, PPCCOM, { CR, BDM } },
2504 { "ble+", BBOCB(16,BOF,CBGT,0,0), BBOATCB_MASK, PPCCOM, { CR, BDP } },
2505 { "ble", BBOCB(16,BOF,CBGT,0,0), BBOATCB_MASK, COM, { CR, BD } },
2506 { "blel-", BBOCB(16,BOF,CBGT,0,1), BBOATCB_MASK, PPCCOM, { CR, BDM } },
2507 { "blel+", BBOCB(16,BOF,CBGT,0,1), BBOATCB_MASK, PPCCOM, { CR, BDP } },
2508 { "blel", BBOCB(16,BOF,CBGT,0,1), BBOATCB_MASK, COM, { CR, BD } },
2509 { "blea-", BBOCB(16,BOF,CBGT,1,0), BBOATCB_MASK, PPCCOM, { CR, BDMA } },
2510 { "blea+", BBOCB(16,BOF,CBGT,1,0), BBOATCB_MASK, PPCCOM, { CR, BDPA } },
2511 { "blea", BBOCB(16,BOF,CBGT,1,0), BBOATCB_MASK, COM, { CR, BDA } },
2512 { "blela-", BBOCB(16,BOF,CBGT,1,1), BBOATCB_MASK, PPCCOM, { CR, BDMA } },
2513 { "blela+", BBOCB(16,BOF,CBGT,1,1), BBOATCB_MASK, PPCCOM, { CR, BDPA } },
2514 { "blela", BBOCB(16,BOF,CBGT,1,1), BBOATCB_MASK, COM, { CR, BDA } },
2515 { "bng-", BBOCB(16,BOF,CBGT,0,0), BBOATCB_MASK, PPCCOM, { CR, BDM } },
2516 { "bng+", BBOCB(16,BOF,CBGT,0,0), BBOATCB_MASK, PPCCOM, { CR, BDP } },
2517 { "bng", BBOCB(16,BOF,CBGT,0,0), BBOATCB_MASK, COM, { CR, BD } },
2518 { "bngl-", BBOCB(16,BOF,CBGT,0,1), BBOATCB_MASK, PPCCOM, { CR, BDM } },
2519 { "bngl+", BBOCB(16,BOF,CBGT,0,1), BBOATCB_MASK, PPCCOM, { CR, BDP } },
2520 { "bngl", BBOCB(16,BOF,CBGT,0,1), BBOATCB_MASK, COM, { CR, BD } },
2521 { "bnga-", BBOCB(16,BOF,CBGT,1,0), BBOATCB_MASK, PPCCOM, { CR, BDMA } },
2522 { "bnga+", BBOCB(16,BOF,CBGT,1,0), BBOATCB_MASK, PPCCOM, { CR, BDPA } },
2523 { "bnga", BBOCB(16,BOF,CBGT,1,0), BBOATCB_MASK, COM, { CR, BDA } },
2524 { "bngla-", BBOCB(16,BOF,CBGT,1,1), BBOATCB_MASK, PPCCOM, { CR, BDMA } },
2525 { "bngla+", BBOCB(16,BOF,CBGT,1,1), BBOATCB_MASK, PPCCOM, { CR, BDPA } },
2526 { "bngla", BBOCB(16,BOF,CBGT,1,1), BBOATCB_MASK, COM, { CR, BDA } },
2527 { "bne-", BBOCB(16,BOF,CBEQ,0,0), BBOATCB_MASK, PPCCOM, { CR, BDM } },
2528 { "bne+", BBOCB(16,BOF,CBEQ,0,0), BBOATCB_MASK, PPCCOM, { CR, BDP } },
2529 { "bne", BBOCB(16,BOF,CBEQ,0,0), BBOATCB_MASK, COM, { CR, BD } },
2530 { "bnel-", BBOCB(16,BOF,CBEQ,0,1), BBOATCB_MASK, PPCCOM, { CR, BDM } },
2531 { "bnel+", BBOCB(16,BOF,CBEQ,0,1), BBOATCB_MASK, PPCCOM, { CR, BDP } },
2532 { "bnel", BBOCB(16,BOF,CBEQ,0,1), BBOATCB_MASK, COM, { CR, BD } },
2533 { "bnea-", BBOCB(16,BOF,CBEQ,1,0), BBOATCB_MASK, PPCCOM, { CR, BDMA } },
2534 { "bnea+", BBOCB(16,BOF,CBEQ,1,0), BBOATCB_MASK, PPCCOM, { CR, BDPA } },
2535 { "bnea", BBOCB(16,BOF,CBEQ,1,0), BBOATCB_MASK, COM, { CR, BDA } },
2536 { "bnela-", BBOCB(16,BOF,CBEQ,1,1), BBOATCB_MASK, PPCCOM, { CR, BDMA } },
2537 { "bnela+", BBOCB(16,BOF,CBEQ,1,1), BBOATCB_MASK, PPCCOM, { CR, BDPA } },
2538 { "bnela", BBOCB(16,BOF,CBEQ,1,1), BBOATCB_MASK, COM, { CR, BDA } },
2539 { "bns-", BBOCB(16,BOF,CBSO,0,0), BBOATCB_MASK, PPCCOM, { CR, BDM } },
2540 { "bns+", BBOCB(16,BOF,CBSO,0,0), BBOATCB_MASK, PPCCOM, { CR, BDP } },
2541 { "bns", BBOCB(16,BOF,CBSO,0,0), BBOATCB_MASK, COM, { CR, BD } },
2542 { "bnsl-", BBOCB(16,BOF,CBSO,0,1), BBOATCB_MASK, PPCCOM, { CR, BDM } },
2543 { "bnsl+", BBOCB(16,BOF,CBSO,0,1), BBOATCB_MASK, PPCCOM, { CR, BDP } },
2544 { "bnsl", BBOCB(16,BOF,CBSO,0,1), BBOATCB_MASK, COM, { CR, BD } },
2545 { "bnsa-", BBOCB(16,BOF,CBSO,1,0), BBOATCB_MASK, PPCCOM, { CR, BDMA } },
2546 { "bnsa+", BBOCB(16,BOF,CBSO,1,0), BBOATCB_MASK, PPCCOM, { CR, BDPA } },
2547 { "bnsa", BBOCB(16,BOF,CBSO,1,0), BBOATCB_MASK, COM, { CR, BDA } },
2548 { "bnsla-", BBOCB(16,BOF,CBSO,1,1), BBOATCB_MASK, PPCCOM, { CR, BDMA } },
2549 { "bnsla+", BBOCB(16,BOF,CBSO,1,1), BBOATCB_MASK, PPCCOM, { CR, BDPA } },
2550 { "bnsla", BBOCB(16,BOF,CBSO,1,1), BBOATCB_MASK, COM, { CR, BDA } },
2551 { "bnu-", BBOCB(16,BOF,CBSO,0,0), BBOATCB_MASK, PPCCOM, { CR, BDM } },
2552 { "bnu+", BBOCB(16,BOF,CBSO,0,0), BBOATCB_MASK, PPCCOM, { CR, BDP } },
2553 { "bnu", BBOCB(16,BOF,CBSO,0,0), BBOATCB_MASK, PPCCOM, { CR, BD } },
2554 { "bnul-", BBOCB(16,BOF,CBSO,0,1), BBOATCB_MASK, PPCCOM, { CR, BDM } },
2555 { "bnul+", BBOCB(16,BOF,CBSO,0,1), BBOATCB_MASK, PPCCOM, { CR, BDP } },
2556 { "bnul", BBOCB(16,BOF,CBSO,0,1), BBOATCB_MASK, PPCCOM, { CR, BD } },
2557 { "bnua-", BBOCB(16,BOF,CBSO,1,0), BBOATCB_MASK, PPCCOM, { CR, BDMA } },
2558 { "bnua+", BBOCB(16,BOF,CBSO,1,0), BBOATCB_MASK, PPCCOM, { CR, BDPA } },
2559 { "bnua", BBOCB(16,BOF,CBSO,1,0), BBOATCB_MASK, PPCCOM, { CR, BDA } },
2560 { "bnula-", BBOCB(16,BOF,CBSO,1,1), BBOATCB_MASK, PPCCOM, { CR, BDMA } },
2561 { "bnula+", BBOCB(16,BOF,CBSO,1,1), BBOATCB_MASK, PPCCOM, { CR, BDPA } },
2562 { "bnula", BBOCB(16,BOF,CBSO,1,1), BBOATCB_MASK, PPCCOM, { CR, BDA } },
2563 { "bdnzt-", BBO(16,BODNZT,0,0), BBOY_MASK, NOPOWER4, { BI, BDM } },
2564 { "bdnzt+", BBO(16,BODNZT,0,0), BBOY_MASK, NOPOWER4, { BI, BDP } },
2565 { "bdnzt", BBO(16,BODNZT,0,0), BBOY_MASK, PPCCOM, { BI, BD } },
2566 { "bdnztl-", BBO(16,BODNZT,0,1), BBOY_MASK, NOPOWER4, { BI, BDM } },
2567 { "bdnztl+", BBO(16,BODNZT,0,1), BBOY_MASK, NOPOWER4, { BI, BDP } },
2568 { "bdnztl", BBO(16,BODNZT,0,1), BBOY_MASK, PPCCOM, { BI, BD } },
2569 { "bdnzta-", BBO(16,BODNZT,1,0), BBOY_MASK, NOPOWER4, { BI, BDMA } },
2570 { "bdnzta+", BBO(16,BODNZT,1,0), BBOY_MASK, NOPOWER4, { BI, BDPA } },
2571 { "bdnzta", BBO(16,BODNZT,1,0), BBOY_MASK, PPCCOM, { BI, BDA } },
2572 { "bdnztla-",BBO(16,BODNZT,1,1), BBOY_MASK, NOPOWER4, { BI, BDMA } },
2573 { "bdnztla+",BBO(16,BODNZT,1,1), BBOY_MASK, NOPOWER4, { BI, BDPA } },
2574 { "bdnztla", BBO(16,BODNZT,1,1), BBOY_MASK, PPCCOM, { BI, BDA } },
2575 { "bdnzf-", BBO(16,BODNZF,0,0), BBOY_MASK, NOPOWER4, { BI, BDM } },
2576 { "bdnzf+", BBO(16,BODNZF,0,0), BBOY_MASK, NOPOWER4, { BI, BDP } },
2577 { "bdnzf", BBO(16,BODNZF,0,0), BBOY_MASK, PPCCOM, { BI, BD } },
2578 { "bdnzfl-", BBO(16,BODNZF,0,1), BBOY_MASK, NOPOWER4, { BI, BDM } },
2579 { "bdnzfl+", BBO(16,BODNZF,0,1), BBOY_MASK, NOPOWER4, { BI, BDP } },
2580 { "bdnzfl", BBO(16,BODNZF,0,1), BBOY_MASK, PPCCOM, { BI, BD } },
2581 { "bdnzfa-", BBO(16,BODNZF,1,0), BBOY_MASK, NOPOWER4, { BI, BDMA } },
2582 { "bdnzfa+", BBO(16,BODNZF,1,0), BBOY_MASK, NOPOWER4, { BI, BDPA } },
2583 { "bdnzfa", BBO(16,BODNZF,1,0), BBOY_MASK, PPCCOM, { BI, BDA } },
2584 { "bdnzfla-",BBO(16,BODNZF,1,1), BBOY_MASK, NOPOWER4, { BI, BDMA } },
2585 { "bdnzfla+",BBO(16,BODNZF,1,1), BBOY_MASK, NOPOWER4, { BI, BDPA } },
2586 { "bdnzfla", BBO(16,BODNZF,1,1), BBOY_MASK, PPCCOM, { BI, BDA } },
2587 { "bt-", BBO(16,BOT,0,0), BBOAT_MASK, PPCCOM, { BI, BDM } },
2588 { "bt+", BBO(16,BOT,0,0), BBOAT_MASK, PPCCOM, { BI, BDP } },
2589 { "bt", BBO(16,BOT,0,0), BBOAT_MASK, PPCCOM, { BI, BD } },
2590 { "bbt", BBO(16,BOT,0,0), BBOAT_MASK, PWRCOM, { BI, BD } },
2591 { "btl-", BBO(16,BOT,0,1), BBOAT_MASK, PPCCOM, { BI, BDM } },
2592 { "btl+", BBO(16,BOT,0,1), BBOAT_MASK, PPCCOM, { BI, BDP } },
2593 { "btl", BBO(16,BOT,0,1), BBOAT_MASK, PPCCOM, { BI, BD } },
2594 { "bbtl", BBO(16,BOT,0,1), BBOAT_MASK, PWRCOM, { BI, BD } },
2595 { "bta-", BBO(16,BOT,1,0), BBOAT_MASK, PPCCOM, { BI, BDMA } },
2596 { "bta+", BBO(16,BOT,1,0), BBOAT_MASK, PPCCOM, { BI, BDPA } },
2597 { "bta", BBO(16,BOT,1,0), BBOAT_MASK, PPCCOM, { BI, BDA } },
2598 { "bbta", BBO(16,BOT,1,0), BBOAT_MASK, PWRCOM, { BI, BDA } },
2599 { "btla-", BBO(16,BOT,1,1), BBOAT_MASK, PPCCOM, { BI, BDMA } },
2600 { "btla+", BBO(16,BOT,1,1), BBOAT_MASK, PPCCOM, { BI, BDPA } },
2601 { "btla", BBO(16,BOT,1,1), BBOAT_MASK, PPCCOM, { BI, BDA } },
2602 { "bbtla", BBO(16,BOT,1,1), BBOAT_MASK, PWRCOM, { BI, BDA } },
2603 { "bf-", BBO(16,BOF,0,0), BBOAT_MASK, PPCCOM, { BI, BDM } },
2604 { "bf+", BBO(16,BOF,0,0), BBOAT_MASK, PPCCOM, { BI, BDP } },
2605 { "bf", BBO(16,BOF,0,0), BBOAT_MASK, PPCCOM, { BI, BD } },
2606 { "bbf", BBO(16,BOF,0,0), BBOAT_MASK, PWRCOM, { BI, BD } },
2607 { "bfl-", BBO(16,BOF,0,1), BBOAT_MASK, PPCCOM, { BI, BDM } },
2608 { "bfl+", BBO(16,BOF,0,1), BBOAT_MASK, PPCCOM, { BI, BDP } },
2609 { "bfl", BBO(16,BOF,0,1), BBOAT_MASK, PPCCOM, { BI, BD } },
2610 { "bbfl", BBO(16,BOF,0,1), BBOAT_MASK, PWRCOM, { BI, BD } },
2611 { "bfa-", BBO(16,BOF,1,0), BBOAT_MASK, PPCCOM, { BI, BDMA } },
2612 { "bfa+", BBO(16,BOF,1,0), BBOAT_MASK, PPCCOM, { BI, BDPA } },
2613 { "bfa", BBO(16,BOF,1,0), BBOAT_MASK, PPCCOM, { BI, BDA } },
2614 { "bbfa", BBO(16,BOF,1,0), BBOAT_MASK, PWRCOM, { BI, BDA } },
2615 { "bfla-", BBO(16,BOF,1,1), BBOAT_MASK, PPCCOM, { BI, BDMA } },
2616 { "bfla+", BBO(16,BOF,1,1), BBOAT_MASK, PPCCOM, { BI, BDPA } },
2617 { "bfla", BBO(16,BOF,1,1), BBOAT_MASK, PPCCOM, { BI, BDA } },
2618 { "bbfla", BBO(16,BOF,1,1), BBOAT_MASK, PWRCOM, { BI, BDA } },
2619 { "bdzt-", BBO(16,BODZT,0,0), BBOY_MASK, NOPOWER4, { BI, BDM } },
2620 { "bdzt+", BBO(16,BODZT,0,0), BBOY_MASK, NOPOWER4, { BI, BDP } },
2621 { "bdzt", BBO(16,BODZT,0,0), BBOY_MASK, PPCCOM, { BI, BD } },
2622 { "bdztl-", BBO(16,BODZT,0,1), BBOY_MASK, NOPOWER4, { BI, BDM } },
2623 { "bdztl+", BBO(16,BODZT,0,1), BBOY_MASK, NOPOWER4, { BI, BDP } },
2624 { "bdztl", BBO(16,BODZT,0,1), BBOY_MASK, PPCCOM, { BI, BD } },
2625 { "bdzta-", BBO(16,BODZT,1,0), BBOY_MASK, NOPOWER4, { BI, BDMA } },
2626 { "bdzta+", BBO(16,BODZT,1,0), BBOY_MASK, NOPOWER4, { BI, BDPA } },
2627 { "bdzta", BBO(16,BODZT,1,0), BBOY_MASK, PPCCOM, { BI, BDA } },
2628 { "bdztla-", BBO(16,BODZT,1,1), BBOY_MASK, NOPOWER4, { BI, BDMA } },
2629 { "bdztla+", BBO(16,BODZT,1,1), BBOY_MASK, NOPOWER4, { BI, BDPA } },
2630 { "bdztla", BBO(16,BODZT,1,1), BBOY_MASK, PPCCOM, { BI, BDA } },
2631 { "bdzf-", BBO(16,BODZF,0,0), BBOY_MASK, NOPOWER4, { BI, BDM } },
2632 { "bdzf+", BBO(16,BODZF,0,0), BBOY_MASK, NOPOWER4, { BI, BDP } },
2633 { "bdzf", BBO(16,BODZF,0,0), BBOY_MASK, PPCCOM, { BI, BD } },
2634 { "bdzfl-", BBO(16,BODZF,0,1), BBOY_MASK, NOPOWER4, { BI, BDM } },
2635 { "bdzfl+", BBO(16,BODZF,0,1), BBOY_MASK, NOPOWER4, { BI, BDP } },
2636 { "bdzfl", BBO(16,BODZF,0,1), BBOY_MASK, PPCCOM, { BI, BD } },
2637 { "bdzfa-", BBO(16,BODZF,1,0), BBOY_MASK, NOPOWER4, { BI, BDMA } },
2638 { "bdzfa+", BBO(16,BODZF,1,0), BBOY_MASK, NOPOWER4, { BI, BDPA } },
2639 { "bdzfa", BBO(16,BODZF,1,0), BBOY_MASK, PPCCOM, { BI, BDA } },
2640 { "bdzfla-", BBO(16,BODZF,1,1), BBOY_MASK, NOPOWER4, { BI, BDMA } },
2641 { "bdzfla+", BBO(16,BODZF,1,1), BBOY_MASK, NOPOWER4, { BI, BDPA } },
2642 { "bdzfla", BBO(16,BODZF,1,1), BBOY_MASK, PPCCOM, { BI, BDA } },
2643 { "bc-", B(16,0,0), B_MASK, PPCCOM, { BOE, BI, BDM } },
2644 { "bc+", B(16,0,0), B_MASK, PPCCOM, { BOE, BI, BDP } },
2645 { "bc", B(16,0,0), B_MASK, COM, { BO, BI, BD } },
2646 { "bcl-", B(16,0,1), B_MASK, PPCCOM, { BOE, BI, BDM } },
2647 { "bcl+", B(16,0,1), B_MASK, PPCCOM, { BOE, BI, BDP } },
2648 { "bcl", B(16,0,1), B_MASK, COM, { BO, BI, BD } },
2649 { "bca-", B(16,1,0), B_MASK, PPCCOM, { BOE, BI, BDMA } },
2650 { "bca+", B(16,1,0), B_MASK, PPCCOM, { BOE, BI, BDPA } },
2651 { "bca", B(16,1,0), B_MASK, COM, { BO, BI, BDA } },
2652 { "bcla-", B(16,1,1), B_MASK, PPCCOM, { BOE, BI, BDMA } },
2653 { "bcla+", B(16,1,1), B_MASK, PPCCOM, { BOE, BI, BDPA } },
2654 { "bcla", B(16,1,1), B_MASK, COM, { BO, BI, BDA } },
2656 { "sc", SC(17,1,0), 0xffffffff, PPC, { 0 } },
2657 { "svc", SC(17,0,0), SC_MASK, POWER, { LEV, FL1, FL2 } },
2658 { "svcl", SC(17,0,1), SC_MASK, POWER, { LEV, FL1, FL2 } },
2659 { "svca", SC(17,1,0), SC_MASK, PWRCOM, { SV } },
2660 { "svcla", SC(17,1,1), SC_MASK, POWER, { SV } },
2662 { "b", B(18,0,0), B_MASK, COM, { LI } },
2663 { "bl", B(18,0,1), B_MASK, COM, { LI } },
2664 { "ba", B(18,1,0), B_MASK, COM, { LIA } },
2665 { "bla", B(18,1,1), B_MASK, COM, { LIA } },
2667 { "mcrf", XL(19,0), XLBB_MASK|(3 << 21)|(3 << 16), COM, { BF, BFA } },
2669 { "blr", XLO(19,BOU,16,0), XLBOBIBB_MASK, PPCCOM, { 0 } },
2670 { "br", XLO(19,BOU,16,0), XLBOBIBB_MASK, PWRCOM, { 0 } },
2671 { "blrl", XLO(19,BOU,16,1), XLBOBIBB_MASK, PPCCOM, { 0 } },
2672 { "brl", XLO(19,BOU,16,1), XLBOBIBB_MASK, PWRCOM, { 0 } },
2673 { "bdnzlr", XLO(19,BODNZ,16,0), XLBOBIBB_MASK, PPCCOM, { 0 } },
2674 { "bdnzlr-", XLO(19,BODNZ,16,0), XLBOBIBB_MASK, NOPOWER4, { 0 } },
2675 { "bdnzlr-", XLO(19,BODNZM4,16,0), XLBOBIBB_MASK, POWER4, { 0 } },
2676 { "bdnzlr+", XLO(19,BODNZP,16,0), XLBOBIBB_MASK, NOPOWER4, { 0 } },
2677 { "bdnzlr+", XLO(19,BODNZP4,16,0), XLBOBIBB_MASK, POWER4, { 0 } },
2678 { "bdnzlrl", XLO(19,BODNZ,16,1), XLBOBIBB_MASK, PPCCOM, { 0 } },
2679 { "bdnzlrl-",XLO(19,BODNZ,16,1), XLBOBIBB_MASK, NOPOWER4, { 0 } },
2680 { "bdnzlrl-",XLO(19,BODNZM4,16,1), XLBOBIBB_MASK, POWER4, { 0 } },
2681 { "bdnzlrl+",XLO(19,BODNZP,16,1), XLBOBIBB_MASK, NOPOWER4, { 0 } },
2682 { "bdnzlrl+",XLO(19,BODNZP4,16,1), XLBOBIBB_MASK, POWER4, { 0 } },
2683 { "bdzlr", XLO(19,BODZ,16,0), XLBOBIBB_MASK, PPCCOM, { 0 } },
2684 { "bdzlr-", XLO(19,BODZ,16,0), XLBOBIBB_MASK, NOPOWER4, { 0 } },
2685 { "bdzlr-", XLO(19,BODZM4,16,0), XLBOBIBB_MASK, POWER4, { 0 } },
2686 { "bdzlr+", XLO(19,BODZP,16,0), XLBOBIBB_MASK, NOPOWER4, { 0 } },
2687 { "bdzlr+", XLO(19,BODZP4,16,0), XLBOBIBB_MASK, POWER4, { 0 } },
2688 { "bdzlrl", XLO(19,BODZ,16,1), XLBOBIBB_MASK, PPCCOM, { 0 } },
2689 { "bdzlrl-", XLO(19,BODZ,16,1), XLBOBIBB_MASK, NOPOWER4, { 0 } },
2690 { "bdzlrl-", XLO(19,BODZM4,16,1), XLBOBIBB_MASK, POWER4, { 0 } },
2691 { "bdzlrl+", XLO(19,BODZP,16,1), XLBOBIBB_MASK, NOPOWER4, { 0 } },
2692 { "bdzlrl+", XLO(19,BODZP4,16,1), XLBOBIBB_MASK, POWER4, { 0 } },
2693 { "bltlr", XLOCB(19,BOT,CBLT,16,0), XLBOCBBB_MASK, PPCCOM, { CR } },
2694 { "bltlr-", XLOCB(19,BOT,CBLT,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2695 { "bltlr-", XLOCB(19,BOTM4,CBLT,16,0), XLBOCBBB_MASK, POWER4, { CR } },
2696 { "bltlr+", XLOCB(19,BOTP,CBLT,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2697 { "bltlr+", XLOCB(19,BOTP4,CBLT,16,0), XLBOCBBB_MASK, POWER4, { CR } },
2698 { "bltr", XLOCB(19,BOT,CBLT,16,0), XLBOCBBB_MASK, PWRCOM, { CR } },
2699 { "bltlrl", XLOCB(19,BOT,CBLT,16,1), XLBOCBBB_MASK, PPCCOM, { CR } },
2700 { "bltlrl-", XLOCB(19,BOT,CBLT,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2701 { "bltlrl-", XLOCB(19,BOTM4,CBLT,16,1), XLBOCBBB_MASK, POWER4, { CR } },
2702 { "bltlrl+", XLOCB(19,BOTP,CBLT,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2703 { "bltlrl+", XLOCB(19,BOTP4,CBLT,16,1), XLBOCBBB_MASK, POWER4, { CR } },
2704 { "bltrl", XLOCB(19,BOT,CBLT,16,1), XLBOCBBB_MASK, PWRCOM, { CR } },
2705 { "bgtlr", XLOCB(19,BOT,CBGT,16,0), XLBOCBBB_MASK, PPCCOM, { CR } },
2706 { "bgtlr-", XLOCB(19,BOT,CBGT,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2707 { "bgtlr-", XLOCB(19,BOTM4,CBGT,16,0), XLBOCBBB_MASK, POWER4, { CR } },
2708 { "bgtlr+", XLOCB(19,BOTP,CBGT,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2709 { "bgtlr+", XLOCB(19,BOTP4,CBGT,16,0), XLBOCBBB_MASK, POWER4, { CR } },
2710 { "bgtr", XLOCB(19,BOT,CBGT,16,0), XLBOCBBB_MASK, PWRCOM, { CR } },
2711 { "bgtlrl", XLOCB(19,BOT,CBGT,16,1), XLBOCBBB_MASK, PPCCOM, { CR } },
2712 { "bgtlrl-", XLOCB(19,BOT,CBGT,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2713 { "bgtlrl-", XLOCB(19,BOTM4,CBGT,16,1), XLBOCBBB_MASK, POWER4, { CR } },
2714 { "bgtlrl+", XLOCB(19,BOTP,CBGT,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2715 { "bgtlrl+", XLOCB(19,BOTP4,CBGT,16,1), XLBOCBBB_MASK, POWER4, { CR } },
2716 { "bgtrl", XLOCB(19,BOT,CBGT,16,1), XLBOCBBB_MASK, PWRCOM, { CR } },
2717 { "beqlr", XLOCB(19,BOT,CBEQ,16,0), XLBOCBBB_MASK, PPCCOM, { CR } },
2718 { "beqlr-", XLOCB(19,BOT,CBEQ,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2719 { "beqlr-", XLOCB(19,BOTM4,CBEQ,16,0), XLBOCBBB_MASK, POWER4, { CR } },
2720 { "beqlr+", XLOCB(19,BOTP,CBEQ,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2721 { "beqlr+", XLOCB(19,BOTP4,CBEQ,16,0), XLBOCBBB_MASK, POWER4, { CR } },
2722 { "beqr", XLOCB(19,BOT,CBEQ,16,0), XLBOCBBB_MASK, PWRCOM, { CR } },
2723 { "beqlrl", XLOCB(19,BOT,CBEQ,16,1), XLBOCBBB_MASK, PPCCOM, { CR } },
2724 { "beqlrl-", XLOCB(19,BOT,CBEQ,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2725 { "beqlrl-", XLOCB(19,BOTM4,CBEQ,16,1), XLBOCBBB_MASK, POWER4, { CR } },
2726 { "beqlrl+", XLOCB(19,BOTP,CBEQ,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2727 { "beqlrl+", XLOCB(19,BOTP4,CBEQ,16,1), XLBOCBBB_MASK, POWER4, { CR } },
2728 { "beqrl", XLOCB(19,BOT,CBEQ,16,1), XLBOCBBB_MASK, PWRCOM, { CR } },
2729 { "bsolr", XLOCB(19,BOT,CBSO,16,0), XLBOCBBB_MASK, PPCCOM, { CR } },
2730 { "bsolr-", XLOCB(19,BOT,CBSO,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2731 { "bsolr-", XLOCB(19,BOTM4,CBSO,16,0), XLBOCBBB_MASK, POWER4, { CR } },
2732 { "bsolr+", XLOCB(19,BOTP,CBSO,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2733 { "bsolr+", XLOCB(19,BOTP4,CBSO,16,0), XLBOCBBB_MASK, POWER4, { CR } },
2734 { "bsor", XLOCB(19,BOT,CBSO,16,0), XLBOCBBB_MASK, PWRCOM, { CR } },
2735 { "bsolrl", XLOCB(19,BOT,CBSO,16,1), XLBOCBBB_MASK, PPCCOM, { CR } },
2736 { "bsolrl-", XLOCB(19,BOT,CBSO,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2737 { "bsolrl-", XLOCB(19,BOTM4,CBSO,16,1), XLBOCBBB_MASK, POWER4, { CR } },
2738 { "bsolrl+", XLOCB(19,BOTP,CBSO,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2739 { "bsolrl+", XLOCB(19,BOTP4,CBSO,16,1), XLBOCBBB_MASK, POWER4, { CR } },
2740 { "bsorl", XLOCB(19,BOT,CBSO,16,1), XLBOCBBB_MASK, PWRCOM, { CR } },
2741 { "bunlr", XLOCB(19,BOT,CBSO,16,0), XLBOCBBB_MASK, PPCCOM, { CR } },
2742 { "bunlr-", XLOCB(19,BOT,CBSO,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2743 { "bunlr-", XLOCB(19,BOTM4,CBSO,16,0), XLBOCBBB_MASK, POWER4, { CR } },
2744 { "bunlr+", XLOCB(19,BOTP,CBSO,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2745 { "bunlr+", XLOCB(19,BOTP4,CBSO,16,0), XLBOCBBB_MASK, POWER4, { CR } },
2746 { "bunlrl", XLOCB(19,BOT,CBSO,16,1), XLBOCBBB_MASK, PPCCOM, { CR } },
2747 { "bunlrl-", XLOCB(19,BOT,CBSO,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2748 { "bunlrl-", XLOCB(19,BOTM4,CBSO,16,1), XLBOCBBB_MASK, POWER4, { CR } },
2749 { "bunlrl+", XLOCB(19,BOTP,CBSO,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2750 { "bunlrl+", XLOCB(19,BOTP4,CBSO,16,1), XLBOCBBB_MASK, POWER4, { CR } },
2751 { "bgelr", XLOCB(19,BOF,CBLT,16,0), XLBOCBBB_MASK, PPCCOM, { CR } },
2752 { "bgelr-", XLOCB(19,BOF,CBLT,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2753 { "bgelr-", XLOCB(19,BOFM4,CBLT,16,0), XLBOCBBB_MASK, POWER4, { CR } },
2754 { "bgelr+", XLOCB(19,BOFP,CBLT,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2755 { "bgelr+", XLOCB(19,BOFP4,CBLT,16,0), XLBOCBBB_MASK, POWER4, { CR } },
2756 { "bger", XLOCB(19,BOF,CBLT,16,0), XLBOCBBB_MASK, PWRCOM, { CR } },
2757 { "bgelrl", XLOCB(19,BOF,CBLT,16,1), XLBOCBBB_MASK, PPCCOM, { CR } },
2758 { "bgelrl-", XLOCB(19,BOF,CBLT,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2759 { "bgelrl-", XLOCB(19,BOFM4,CBLT,16,1), XLBOCBBB_MASK, POWER4, { CR } },
2760 { "bgelrl+", XLOCB(19,BOFP,CBLT,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2761 { "bgelrl+", XLOCB(19,BOFP4,CBLT,16,1), XLBOCBBB_MASK, POWER4, { CR } },
2762 { "bgerl", XLOCB(19,BOF,CBLT,16,1), XLBOCBBB_MASK, PWRCOM, { CR } },
2763 { "bnllr", XLOCB(19,BOF,CBLT,16,0), XLBOCBBB_MASK, PPCCOM, { CR } },
2764 { "bnllr-", XLOCB(19,BOF,CBLT,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2765 { "bnllr-", XLOCB(19,BOFM4,CBLT,16,0), XLBOCBBB_MASK, POWER4, { CR } },
2766 { "bnllr+", XLOCB(19,BOFP,CBLT,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2767 { "bnllr+", XLOCB(19,BOFP4,CBLT,16,0), XLBOCBBB_MASK, POWER4, { CR } },
2768 { "bnlr", XLOCB(19,BOF,CBLT,16,0), XLBOCBBB_MASK, PWRCOM, { CR } },
2769 { "bnllrl", XLOCB(19,BOF,CBLT,16,1), XLBOCBBB_MASK, PPCCOM, { CR } },
2770 { "bnllrl-", XLOCB(19,BOF,CBLT,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2771 { "bnllrl-", XLOCB(19,BOFM4,CBLT,16,1), XLBOCBBB_MASK, POWER4, { CR } },
2772 { "bnllrl+", XLOCB(19,BOFP,CBLT,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2773 { "bnllrl+", XLOCB(19,BOFP4,CBLT,16,1), XLBOCBBB_MASK, POWER4, { CR } },
2774 { "bnlrl", XLOCB(19,BOF,CBLT,16,1), XLBOCBBB_MASK, PWRCOM, { CR } },
2775 { "blelr", XLOCB(19,BOF,CBGT,16,0), XLBOCBBB_MASK, PPCCOM, { CR } },
2776 { "blelr-", XLOCB(19,BOF,CBGT,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2777 { "blelr-", XLOCB(19,BOFM4,CBGT,16,0), XLBOCBBB_MASK, POWER4, { CR } },
2778 { "blelr+", XLOCB(19,BOFP,CBGT,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2779 { "blelr+", XLOCB(19,BOFP4,CBGT,16,0), XLBOCBBB_MASK, POWER4, { CR } },
2780 { "bler", XLOCB(19,BOF,CBGT,16,0), XLBOCBBB_MASK, PWRCOM, { CR } },
2781 { "blelrl", XLOCB(19,BOF,CBGT,16,1), XLBOCBBB_MASK, PPCCOM, { CR } },
2782 { "blelrl-", XLOCB(19,BOF,CBGT,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2783 { "blelrl-", XLOCB(19,BOFM4,CBGT,16,1), XLBOCBBB_MASK, POWER4, { CR } },
2784 { "blelrl+", XLOCB(19,BOFP,CBGT,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2785 { "blelrl+", XLOCB(19,BOFP4,CBGT,16,1), XLBOCBBB_MASK, POWER4, { CR } },
2786 { "blerl", XLOCB(19,BOF,CBGT,16,1), XLBOCBBB_MASK, PWRCOM, { CR } },
2787 { "bnglr", XLOCB(19,BOF,CBGT,16,0), XLBOCBBB_MASK, PPCCOM, { CR } },
2788 { "bnglr-", XLOCB(19,BOF,CBGT,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2789 { "bnglr-", XLOCB(19,BOFM4,CBGT,16,0), XLBOCBBB_MASK, POWER4, { CR } },
2790 { "bnglr+", XLOCB(19,BOFP,CBGT,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2791 { "bnglr+", XLOCB(19,BOFP4,CBGT,16,0), XLBOCBBB_MASK, POWER4, { CR } },
2792 { "bngr", XLOCB(19,BOF,CBGT,16,0), XLBOCBBB_MASK, PWRCOM, { CR } },
2793 { "bnglrl", XLOCB(19,BOF,CBGT,16,1), XLBOCBBB_MASK, PPCCOM, { CR } },
2794 { "bnglrl-", XLOCB(19,BOF,CBGT,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2795 { "bnglrl-", XLOCB(19,BOFM4,CBGT,16,1), XLBOCBBB_MASK, POWER4, { CR } },
2796 { "bnglrl+", XLOCB(19,BOFP,CBGT,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2797 { "bnglrl+", XLOCB(19,BOFP4,CBGT,16,1), XLBOCBBB_MASK, POWER4, { CR } },
2798 { "bngrl", XLOCB(19,BOF,CBGT,16,1), XLBOCBBB_MASK, PWRCOM, { CR } },
2799 { "bnelr", XLOCB(19,BOF,CBEQ,16,0), XLBOCBBB_MASK, PPCCOM, { CR } },
2800 { "bnelr-", XLOCB(19,BOF,CBEQ,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2801 { "bnelr-", XLOCB(19,BOFM4,CBEQ,16,0), XLBOCBBB_MASK, POWER4, { CR } },
2802 { "bnelr+", XLOCB(19,BOFP,CBEQ,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2803 { "bnelr+", XLOCB(19,BOFP4,CBEQ,16,0), XLBOCBBB_MASK, POWER4, { CR } },
2804 { "bner", XLOCB(19,BOF,CBEQ,16,0), XLBOCBBB_MASK, PWRCOM, { CR } },
2805 { "bnelrl", XLOCB(19,BOF,CBEQ,16,1), XLBOCBBB_MASK, PPCCOM, { CR } },
2806 { "bnelrl-", XLOCB(19,BOF,CBEQ,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2807 { "bnelrl-", XLOCB(19,BOFM4,CBEQ,16,1), XLBOCBBB_MASK, POWER4, { CR } },
2808 { "bnelrl+", XLOCB(19,BOFP,CBEQ,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2809 { "bnelrl+", XLOCB(19,BOFP4,CBEQ,16,1), XLBOCBBB_MASK, POWER4, { CR } },
2810 { "bnerl", XLOCB(19,BOF,CBEQ,16,1), XLBOCBBB_MASK, PWRCOM, { CR } },
2811 { "bnslr", XLOCB(19,BOF,CBSO,16,0), XLBOCBBB_MASK, PPCCOM, { CR } },
2812 { "bnslr-", XLOCB(19,BOF,CBSO,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2813 { "bnslr-", XLOCB(19,BOFM4,CBSO,16,0), XLBOCBBB_MASK, POWER4, { CR } },
2814 { "bnslr+", XLOCB(19,BOFP,CBSO,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2815 { "bnslr+", XLOCB(19,BOFP4,CBSO,16,0), XLBOCBBB_MASK, POWER4, { CR } },
2816 { "bnsr", XLOCB(19,BOF,CBSO,16,0), XLBOCBBB_MASK, PWRCOM, { CR } },
2817 { "bnslrl", XLOCB(19,BOF,CBSO,16,1), XLBOCBBB_MASK, PPCCOM, { CR } },
2818 { "bnslrl-", XLOCB(19,BOF,CBSO,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2819 { "bnslrl-", XLOCB(19,BOFM4,CBSO,16,1), XLBOCBBB_MASK, POWER4, { CR } },
2820 { "bnslrl+", XLOCB(19,BOFP,CBSO,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2821 { "bnslrl+", XLOCB(19,BOFP4,CBSO,16,1), XLBOCBBB_MASK, POWER4, { CR } },
2822 { "bnsrl", XLOCB(19,BOF,CBSO,16,1), XLBOCBBB_MASK, PWRCOM, { CR } },
2823 { "bnulr", XLOCB(19,BOF,CBSO,16,0), XLBOCBBB_MASK, PPCCOM, { CR } },
2824 { "bnulr-", XLOCB(19,BOF,CBSO,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2825 { "bnulr-", XLOCB(19,BOFM4,CBSO,16,0), XLBOCBBB_MASK, POWER4, { CR } },
2826 { "bnulr+", XLOCB(19,BOFP,CBSO,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2827 { "bnulr+", XLOCB(19,BOFP4,CBSO,16,0), XLBOCBBB_MASK, POWER4, { CR } },
2828 { "bnulrl", XLOCB(19,BOF,CBSO,16,1), XLBOCBBB_MASK, PPCCOM, { CR } },
2829 { "bnulrl-", XLOCB(19,BOF,CBSO,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2830 { "bnulrl-", XLOCB(19,BOFM4,CBSO,16,1), XLBOCBBB_MASK, POWER4, { CR } },
2831 { "bnulrl+", XLOCB(19,BOFP,CBSO,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2832 { "bnulrl+", XLOCB(19,BOFP4,CBSO,16,1), XLBOCBBB_MASK, POWER4, { CR } },
2833 { "btlr", XLO(19,BOT,16,0), XLBOBB_MASK, PPCCOM, { BI } },
2834 { "btlr-", XLO(19,BOT,16,0), XLBOBB_MASK, NOPOWER4, { BI } },
2835 { "btlr-", XLO(19,BOTM4,16,0), XLBOBB_MASK, POWER4, { BI } },
2836 { "btlr+", XLO(19,BOTP,16,0), XLBOBB_MASK, NOPOWER4, { BI } },
2837 { "btlr+", XLO(19,BOTP4,16,0), XLBOBB_MASK, POWER4, { BI } },
2838 { "bbtr", XLO(19,BOT,16,0), XLBOBB_MASK, PWRCOM, { BI } },
2839 { "btlrl", XLO(19,BOT,16,1), XLBOBB_MASK, PPCCOM, { BI } },
2840 { "btlrl-", XLO(19,BOT,16,1), XLBOBB_MASK, NOPOWER4, { BI } },
2841 { "btlrl-", XLO(19,BOTM4,16,1), XLBOBB_MASK, POWER4, { BI } },
2842 { "btlrl+", XLO(19,BOTP,16,1), XLBOBB_MASK, NOPOWER4, { BI } },
2843 { "btlrl+", XLO(19,BOTP4,16,1), XLBOBB_MASK, POWER4, { BI } },
2844 { "bbtrl", XLO(19,BOT,16,1), XLBOBB_MASK, PWRCOM, { BI } },
2845 { "bflr", XLO(19,BOF,16,0), XLBOBB_MASK, PPCCOM, { BI } },
2846 { "bflr-", XLO(19,BOF,16,0), XLBOBB_MASK, NOPOWER4, { BI } },
2847 { "bflr-", XLO(19,BOFM4,16,0), XLBOBB_MASK, POWER4, { BI } },
2848 { "bflr+", XLO(19,BOFP,16,0), XLBOBB_MASK, NOPOWER4, { BI } },
2849 { "bflr+", XLO(19,BOFP4,16,0), XLBOBB_MASK, POWER4, { BI } },
2850 { "bbfr", XLO(19,BOF,16,0), XLBOBB_MASK, PWRCOM, { BI } },
2851 { "bflrl", XLO(19,BOF,16,1), XLBOBB_MASK, PPCCOM, { BI } },
2852 { "bflrl-", XLO(19,BOF,16,1), XLBOBB_MASK, NOPOWER4, { BI } },
2853 { "bflrl-", XLO(19,BOFM4,16,1), XLBOBB_MASK, POWER4, { BI } },
2854 { "bflrl+", XLO(19,BOFP,16,1), XLBOBB_MASK, NOPOWER4, { BI } },
2855 { "bflrl+", XLO(19,BOFP4,16,1), XLBOBB_MASK, POWER4, { BI } },
2856 { "bbfrl", XLO(19,BOF,16,1), XLBOBB_MASK, PWRCOM, { BI } },
2857 { "bdnztlr", XLO(19,BODNZT,16,0), XLBOBB_MASK, PPCCOM, { BI } },
2858 { "bdnztlr-",XLO(19,BODNZT,16,0), XLBOBB_MASK, NOPOWER4, { BI } },
2859 { "bdnztlr+",XLO(19,BODNZTP,16,0), XLBOBB_MASK, NOPOWER4, { BI } },
2860 { "bdnztlrl",XLO(19,BODNZT,16,1), XLBOBB_MASK, PPCCOM, { BI } },
2861 { "bdnztlrl-",XLO(19,BODNZT,16,1), XLBOBB_MASK, NOPOWER4, { BI } },
2862 { "bdnztlrl+",XLO(19,BODNZTP,16,1), XLBOBB_MASK, NOPOWER4, { BI } },
2863 { "bdnzflr", XLO(19,BODNZF,16,0), XLBOBB_MASK, PPCCOM, { BI } },
2864 { "bdnzflr-",XLO(19,BODNZF,16,0), XLBOBB_MASK, NOPOWER4, { BI } },
2865 { "bdnzflr+",XLO(19,BODNZFP,16,0), XLBOBB_MASK, NOPOWER4, { BI } },
2866 { "bdnzflrl",XLO(19,BODNZF,16,1), XLBOBB_MASK, PPCCOM, { BI } },
2867 { "bdnzflrl-",XLO(19,BODNZF,16,1), XLBOBB_MASK, NOPOWER4, { BI } },
2868 { "bdnzflrl+",XLO(19,BODNZFP,16,1), XLBOBB_MASK, NOPOWER4, { BI } },
2869 { "bdztlr", XLO(19,BODZT,16,0), XLBOBB_MASK, PPCCOM, { BI } },
2870 { "bdztlr-", XLO(19,BODZT,16,0), XLBOBB_MASK, NOPOWER4, { BI } },
2871 { "bdztlr+", XLO(19,BODZTP,16,0), XLBOBB_MASK, NOPOWER4, { BI } },
2872 { "bdztlrl", XLO(19,BODZT,16,1), XLBOBB_MASK, PPCCOM, { BI } },
2873 { "bdztlrl-",XLO(19,BODZT,16,1), XLBOBB_MASK, NOPOWER4, { BI } },
2874 { "bdztlrl+",XLO(19,BODZTP,16,1), XLBOBB_MASK, NOPOWER4, { BI } },
2875 { "bdzflr", XLO(19,BODZF,16,0), XLBOBB_MASK, PPCCOM, { BI } },
2876 { "bdzflr-", XLO(19,BODZF,16,0), XLBOBB_MASK, NOPOWER4, { BI } },
2877 { "bdzflr+", XLO(19,BODZFP,16,0), XLBOBB_MASK, NOPOWER4, { BI } },
2878 { "bdzflrl", XLO(19,BODZF,16,1), XLBOBB_MASK, PPCCOM, { BI } },
2879 { "bdzflrl-",XLO(19,BODZF,16,1), XLBOBB_MASK, NOPOWER4, { BI } },
2880 { "bdzflrl+",XLO(19,BODZFP,16,1), XLBOBB_MASK, NOPOWER4, { BI } },
2881 { "bclr", XLLK(19,16,0), XLYBB_MASK, PPCCOM, { BO, BI } },
2882 { "bclrl", XLLK(19,16,1), XLYBB_MASK, PPCCOM, { BO, BI } },
2883 { "bclr+", XLYLK(19,16,1,0), XLYBB_MASK, PPCCOM, { BOE, BI } },
2884 { "bclrl+", XLYLK(19,16,1,1), XLYBB_MASK, PPCCOM, { BOE, BI } },
2885 { "bclr-", XLYLK(19,16,0,0), XLYBB_MASK, PPCCOM, { BOE, BI } },
2886 { "bclrl-", XLYLK(19,16,0,1), XLYBB_MASK, PPCCOM, { BOE, BI } },
2887 { "bcr", XLLK(19,16,0), XLBB_MASK, PWRCOM, { BO, BI } },
2888 { "bcrl", XLLK(19,16,1), XLBB_MASK, PWRCOM, { BO, BI } },
2889 { "bclre", XLLK(19,17,0), XLBB_MASK, BOOKE64, { BO, BI } },
2890 { "bclrel", XLLK(19,17,1), XLBB_MASK, BOOKE64, { BO, BI } },
2892 { "rfid", XL(19,18), 0xffffffff, PPC64, { 0 } },
2894 { "crnot", XL(19,33), XL_MASK, PPCCOM, { BT, BA, BBA } },
2895 { "crnor", XL(19,33), XL_MASK, COM, { BT, BA, BB } },
2896 { "rfmci", X(19,38), 0xffffffff, PPCRFMCI, { 0 } },
2898 { "rfi", XL(19,50), 0xffffffff, COM, { 0 } },
2899 { "rfci", XL(19,51), 0xffffffff, PPC403 | BOOKE, { 0 } },
2901 { "rfsvc", XL(19,82), 0xffffffff, POWER, { 0 } },
2903 { "crandc", XL(19,129), XL_MASK, COM, { BT, BA, BB } },
2905 { "isync", XL(19,150), 0xffffffff, PPCCOM, { 0 } },
2906 { "ics", XL(19,150), 0xffffffff, PWRCOM, { 0 } },
2908 { "crclr", XL(19,193), XL_MASK, PPCCOM, { BT, BAT, BBA } },
2909 { "crxor", XL(19,193), XL_MASK, COM, { BT, BA, BB } },
2911 { "crnand", XL(19,225), XL_MASK, COM, { BT, BA, BB } },
2913 { "crand", XL(19,257), XL_MASK, COM, { BT, BA, BB } },
2915 { "crset", XL(19,289), XL_MASK, PPCCOM, { BT, BAT, BBA } },
2916 { "creqv", XL(19,289), XL_MASK, COM, { BT, BA, BB } },
2918 { "crorc", XL(19,417), XL_MASK, COM, { BT, BA, BB } },
2920 { "crmove", XL(19,449), XL_MASK, PPCCOM, { BT, BA, BBA } },
2921 { "cror", XL(19,449), XL_MASK, COM, { BT, BA, BB } },
2923 { "bctr", XLO(19,BOU,528,0), XLBOBIBB_MASK, COM, { 0 } },
2924 { "bctrl", XLO(19,BOU,528,1), XLBOBIBB_MASK, COM, { 0 } },
2925 { "bltctr", XLOCB(19,BOT,CBLT,528,0), XLBOCBBB_MASK, PPCCOM, { CR } },
2926 { "bltctr-", XLOCB(19,BOT,CBLT,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2927 { "bltctr-", XLOCB(19,BOTM4,CBLT,528,0), XLBOCBBB_MASK, POWER4, { CR } },
2928 { "bltctr+", XLOCB(19,BOTP,CBLT,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2929 { "bltctr+", XLOCB(19,BOTP4,CBLT,528,0), XLBOCBBB_MASK, POWER4, { CR } },
2930 { "bltctrl", XLOCB(19,BOT,CBLT,528,1), XLBOCBBB_MASK, PPCCOM, { CR } },
2931 { "bltctrl-",XLOCB(19,BOT,CBLT,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2932 { "bltctrl-",XLOCB(19,BOTM4,CBLT,528,1), XLBOCBBB_MASK, POWER4, { CR } },
2933 { "bltctrl+",XLOCB(19,BOTP,CBLT,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2934 { "bltctrl+",XLOCB(19,BOTP4,CBLT,528,1), XLBOCBBB_MASK, POWER4, { CR } },
2935 { "bgtctr", XLOCB(19,BOT,CBGT,528,0), XLBOCBBB_MASK, PPCCOM, { CR } },
2936 { "bgtctr-", XLOCB(19,BOT,CBGT,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2937 { "bgtctr-", XLOCB(19,BOTM4,CBGT,528,0), XLBOCBBB_MASK, POWER4, { CR } },
2938 { "bgtctr+", XLOCB(19,BOTP,CBGT,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2939 { "bgtctr+", XLOCB(19,BOTP4,CBGT,528,0), XLBOCBBB_MASK, POWER4, { CR } },
2940 { "bgtctrl", XLOCB(19,BOT,CBGT,528,1), XLBOCBBB_MASK, PPCCOM, { CR } },
2941 { "bgtctrl-",XLOCB(19,BOT,CBGT,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2942 { "bgtctrl-",XLOCB(19,BOTM4,CBGT,528,1), XLBOCBBB_MASK, POWER4, { CR } },
2943 { "bgtctrl+",XLOCB(19,BOTP,CBGT,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2944 { "bgtctrl+",XLOCB(19,BOTP4,CBGT,528,1), XLBOCBBB_MASK, POWER4, { CR } },
2945 { "beqctr", XLOCB(19,BOT,CBEQ,528,0), XLBOCBBB_MASK, PPCCOM, { CR } },
2946 { "beqctr-", XLOCB(19,BOT,CBEQ,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2947 { "beqctr-", XLOCB(19,BOTM4,CBEQ,528,0), XLBOCBBB_MASK, POWER4, { CR } },
2948 { "beqctr+", XLOCB(19,BOTP,CBEQ,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2949 { "beqctr+", XLOCB(19,BOTP4,CBEQ,528,0), XLBOCBBB_MASK, POWER4, { CR } },
2950 { "beqctrl", XLOCB(19,BOT,CBEQ,528,1), XLBOCBBB_MASK, PPCCOM, { CR } },
2951 { "beqctrl-",XLOCB(19,BOT,CBEQ,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2952 { "beqctrl-",XLOCB(19,BOTM4,CBEQ,528,1), XLBOCBBB_MASK, POWER4, { CR } },
2953 { "beqctrl+",XLOCB(19,BOTP,CBEQ,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2954 { "beqctrl+",XLOCB(19,BOTP4,CBEQ,528,1), XLBOCBBB_MASK, POWER4, { CR } },
2955 { "bsoctr", XLOCB(19,BOT,CBSO,528,0), XLBOCBBB_MASK, PPCCOM, { CR } },
2956 { "bsoctr-", XLOCB(19,BOT,CBSO,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2957 { "bsoctr-", XLOCB(19,BOTM4,CBSO,528,0), XLBOCBBB_MASK, POWER4, { CR } },
2958 { "bsoctr+", XLOCB(19,BOTP,CBSO,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2959 { "bsoctr+", XLOCB(19,BOTP4,CBSO,528,0), XLBOCBBB_MASK, POWER4, { CR } },
2960 { "bsoctrl", XLOCB(19,BOT,CBSO,528,1), XLBOCBBB_MASK, PPCCOM, { CR } },
2961 { "bsoctrl-",XLOCB(19,BOT,CBSO,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2962 { "bsoctrl-",XLOCB(19,BOTM4,CBSO,528,1), XLBOCBBB_MASK, POWER4, { CR } },
2963 { "bsoctrl+",XLOCB(19,BOTP,CBSO,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2964 { "bsoctrl+",XLOCB(19,BOTP4,CBSO,528,1), XLBOCBBB_MASK, POWER4, { CR } },
2965 { "bunctr", XLOCB(19,BOT,CBSO,528,0), XLBOCBBB_MASK, PPCCOM, { CR } },
2966 { "bunctr-", XLOCB(19,BOT,CBSO,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2967 { "bunctr-", XLOCB(19,BOTM4,CBSO,528,0), XLBOCBBB_MASK, POWER4, { CR } },
2968 { "bunctr+", XLOCB(19,BOTP,CBSO,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2969 { "bunctr+", XLOCB(19,BOTP4,CBSO,528,0), XLBOCBBB_MASK, POWER4, { CR } },
2970 { "bunctrl", XLOCB(19,BOT,CBSO,528,1), XLBOCBBB_MASK, PPCCOM, { CR } },
2971 { "bunctrl-",XLOCB(19,BOT,CBSO,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2972 { "bunctrl-",XLOCB(19,BOTM4,CBSO,528,1), XLBOCBBB_MASK, POWER4, { CR } },
2973 { "bunctrl+",XLOCB(19,BOTP,CBSO,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2974 { "bunctrl+",XLOCB(19,BOTP4,CBSO,528,1), XLBOCBBB_MASK, POWER4, { CR } },
2975 { "bgectr", XLOCB(19,BOF,CBLT,528,0), XLBOCBBB_MASK, PPCCOM, { CR } },
2976 { "bgectr-", XLOCB(19,BOF,CBLT,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2977 { "bgectr-", XLOCB(19,BOFM4,CBLT,528,0), XLBOCBBB_MASK, POWER4, { CR } },
2978 { "bgectr+", XLOCB(19,BOFP,CBLT,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2979 { "bgectr+", XLOCB(19,BOFP4,CBLT,528,0), XLBOCBBB_MASK, POWER4, { CR } },
2980 { "bgectrl", XLOCB(19,BOF,CBLT,528,1), XLBOCBBB_MASK, PPCCOM, { CR } },
2981 { "bgectrl-",XLOCB(19,BOF,CBLT,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2982 { "bgectrl-",XLOCB(19,BOFM4,CBLT,528,1), XLBOCBBB_MASK, POWER4, { CR } },
2983 { "bgectrl+",XLOCB(19,BOFP,CBLT,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2984 { "bgectrl+",XLOCB(19,BOFP4,CBLT,528,1), XLBOCBBB_MASK, POWER4, { CR } },
2985 { "bnlctr", XLOCB(19,BOF,CBLT,528,0), XLBOCBBB_MASK, PPCCOM, { CR } },
2986 { "bnlctr-", XLOCB(19,BOF,CBLT,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2987 { "bnlctr-", XLOCB(19,BOFM4,CBLT,528,0), XLBOCBBB_MASK, POWER4, { CR } },
2988 { "bnlctr+", XLOCB(19,BOFP,CBLT,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2989 { "bnlctr+", XLOCB(19,BOFP4,CBLT,528,0), XLBOCBBB_MASK, POWER4, { CR } },
2990 { "bnlctrl", XLOCB(19,BOF,CBLT,528,1), XLBOCBBB_MASK, PPCCOM, { CR } },
2991 { "bnlctrl-",XLOCB(19,BOF,CBLT,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2992 { "bnlctrl-",XLOCB(19,BOFM4,CBLT,528,1), XLBOCBBB_MASK, POWER4, { CR } },
2993 { "bnlctrl+",XLOCB(19,BOFP,CBLT,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2994 { "bnlctrl+",XLOCB(19,BOFP4,CBLT,528,1), XLBOCBBB_MASK, POWER4, { CR } },
2995 { "blectr", XLOCB(19,BOF,CBGT,528,0), XLBOCBBB_MASK, PPCCOM, { CR } },
2996 { "blectr-", XLOCB(19,BOF,CBGT,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2997 { "blectr-", XLOCB(19,BOFM4,CBGT,528,0), XLBOCBBB_MASK, POWER4, { CR } },
2998 { "blectr+", XLOCB(19,BOFP,CBGT,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2999 { "blectr+", XLOCB(19,BOFP4,CBGT,528,0), XLBOCBBB_MASK, POWER4, { CR } },
3000 { "blectrl", XLOCB(19,BOF,CBGT,528,1), XLBOCBBB_MASK, PPCCOM, { CR } },
3001 { "blectrl-",XLOCB(19,BOF,CBGT,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
3002 { "blectrl-",XLOCB(19,BOFM4,CBGT,528,1), XLBOCBBB_MASK, POWER4, { CR } },
3003 { "blectrl+",XLOCB(19,BOFP,CBGT,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
3004 { "blectrl+",XLOCB(19,BOFP4,CBGT,528,1), XLBOCBBB_MASK, POWER4, { CR } },
3005 { "bngctr", XLOCB(19,BOF,CBGT,528,0), XLBOCBBB_MASK, PPCCOM, { CR } },
3006 { "bngctr-", XLOCB(19,BOF,CBGT,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
3007 { "bngctr-", XLOCB(19,BOFM4,CBGT,528,0), XLBOCBBB_MASK, POWER4, { CR } },
3008 { "bngctr+", XLOCB(19,BOFP,CBGT,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
3009 { "bngctr+", XLOCB(19,BOFP4,CBGT,528,0), XLBOCBBB_MASK, POWER4, { CR } },
3010 { "bngctrl", XLOCB(19,BOF,CBGT,528,1), XLBOCBBB_MASK, PPCCOM, { CR } },
3011 { "bngctrl-",XLOCB(19,BOF,CBGT,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
3012 { "bngctrl-",XLOCB(19,BOFM4,CBGT,528,1), XLBOCBBB_MASK, POWER4, { CR } },
3013 { "bngctrl+",XLOCB(19,BOFP,CBGT,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
3014 { "bngctrl+",XLOCB(19,BOFP4,CBGT,528,1), XLBOCBBB_MASK, POWER4, { CR } },
3015 { "bnectr", XLOCB(19,BOF,CBEQ,528,0), XLBOCBBB_MASK, PPCCOM, { CR } },
3016 { "bnectr-", XLOCB(19,BOF,CBEQ,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
3017 { "bnectr-", XLOCB(19,BOFM4,CBEQ,528,0), XLBOCBBB_MASK, POWER4, { CR } },
3018 { "bnectr+", XLOCB(19,BOFP,CBEQ,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
3019 { "bnectr+", XLOCB(19,BOFP4,CBEQ,528,0), XLBOCBBB_MASK, POWER4, { CR } },
3020 { "bnectrl", XLOCB(19,BOF,CBEQ,528,1), XLBOCBBB_MASK, PPCCOM, { CR } },
3021 { "bnectrl-",XLOCB(19,BOF,CBEQ,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
3022 { "bnectrl-",XLOCB(19,BOFM4,CBEQ,528,1), XLBOCBBB_MASK, POWER4, { CR } },
3023 { "bnectrl+",XLOCB(19,BOFP,CBEQ,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
3024 { "bnectrl+",XLOCB(19,BOFP4,CBEQ,528,1), XLBOCBBB_MASK, POWER4, { CR } },
3025 { "bnsctr", XLOCB(19,BOF,CBSO,528,0), XLBOCBBB_MASK, PPCCOM, { CR } },
3026 { "bnsctr-", XLOCB(19,BOF,CBSO,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
3027 { "bnsctr-", XLOCB(19,BOFM4,CBSO,528,0), XLBOCBBB_MASK, POWER4, { CR } },
3028 { "bnsctr+", XLOCB(19,BOFP,CBSO,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
3029 { "bnsctr+", XLOCB(19,BOFP4,CBSO,528,0), XLBOCBBB_MASK, POWER4, { CR } },
3030 { "bnsctrl", XLOCB(19,BOF,CBSO,528,1), XLBOCBBB_MASK, PPCCOM, { CR } },
3031 { "bnsctrl-",XLOCB(19,BOF,CBSO,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
3032 { "bnsctrl-",XLOCB(19,BOFM4,CBSO,528,1), XLBOCBBB_MASK, POWER4, { CR } },
3033 { "bnsctrl+",XLOCB(19,BOFP,CBSO,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
3034 { "bnsctrl+",XLOCB(19,BOFP4,CBSO,528,1), XLBOCBBB_MASK, POWER4, { CR } },
3035 { "bnuctr", XLOCB(19,BOF,CBSO,528,0), XLBOCBBB_MASK, PPCCOM, { CR } },
3036 { "bnuctr-", XLOCB(19,BOF,CBSO,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
3037 { "bnuctr-", XLOCB(19,BOFM4,CBSO,528,0), XLBOCBBB_MASK, POWER4, { CR } },
3038 { "bnuctr+", XLOCB(19,BOFP,CBSO,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
3039 { "bnuctr+", XLOCB(19,BOFP4,CBSO,528,0), XLBOCBBB_MASK, POWER4, { CR } },
3040 { "bnuctrl", XLOCB(19,BOF,CBSO,528,1), XLBOCBBB_MASK, PPCCOM, { CR } },
3041 { "bnuctrl-",XLOCB(19,BOF,CBSO,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
3042 { "bnuctrl-",XLOCB(19,BOFM4,CBSO,528,1), XLBOCBBB_MASK, POWER4, { CR } },
3043 { "bnuctrl+",XLOCB(19,BOFP,CBSO,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
3044 { "bnuctrl+",XLOCB(19,BOFP4,CBSO,528,1), XLBOCBBB_MASK, POWER4, { CR } },
3045 { "btctr", XLO(19,BOT,528,0), XLBOBB_MASK, PPCCOM, { BI } },
3046 { "btctr-", XLO(19,BOT,528,0), XLBOBB_MASK, NOPOWER4, { BI } },
3047 { "btctr-", XLO(19,BOTM4,528,0), XLBOBB_MASK, POWER4, { BI } },
3048 { "btctr+", XLO(19,BOTP,528,0), XLBOBB_MASK, NOPOWER4, { BI } },
3049 { "btctr+", XLO(19,BOTP4,528,0), XLBOBB_MASK, POWER4, { BI } },
3050 { "btctrl", XLO(19,BOT,528,1), XLBOBB_MASK, PPCCOM, { BI } },
3051 { "btctrl-", XLO(19,BOT,528,1), XLBOBB_MASK, NOPOWER4, { BI } },
3052 { "btctrl-", XLO(19,BOTM4,528,1), XLBOBB_MASK, POWER4, { BI } },
3053 { "btctrl+", XLO(19,BOTP,528,1), XLBOBB_MASK, NOPOWER4, { BI } },
3054 { "btctrl+", XLO(19,BOTP4,528,1), XLBOBB_MASK, POWER4, { BI } },
3055 { "bfctr", XLO(19,BOF,528,0), XLBOBB_MASK, PPCCOM, { BI } },
3056 { "bfctr-", XLO(19,BOF,528,0), XLBOBB_MASK, NOPOWER4, { BI } },
3057 { "bfctr-", XLO(19,BOFM4,528,0), XLBOBB_MASK, POWER4, { BI } },
3058 { "bfctr+", XLO(19,BOFP,528,0), XLBOBB_MASK, NOPOWER4, { BI } },
3059 { "bfctr+", XLO(19,BOFP4,528,0), XLBOBB_MASK, POWER4, { BI } },
3060 { "bfctrl", XLO(19,BOF,528,1), XLBOBB_MASK, PPCCOM, { BI } },
3061 { "bfctrl-", XLO(19,BOF,528,1), XLBOBB_MASK, NOPOWER4, { BI } },
3062 { "bfctrl-", XLO(19,BOFM4,528,1), XLBOBB_MASK, POWER4, { BI } },
3063 { "bfctrl+", XLO(19,BOFP,528,1), XLBOBB_MASK, NOPOWER4, { BI } },
3064 { "bfctrl+", XLO(19,BOFP4,528,1), XLBOBB_MASK, POWER4, { BI } },
3065 { "bcctr", XLLK(19,528,0), XLYBB_MASK, PPCCOM, { BO, BI } },
3066 { "bcctr-", XLYLK(19,528,0,0), XLYBB_MASK, PPCCOM, { BOE, BI } },
3067 { "bcctr+", XLYLK(19,528,1,0), XLYBB_MASK, PPCCOM, { BOE, BI } },
3068 { "bcctrl", XLLK(19,528,1), XLYBB_MASK, PPCCOM, { BO, BI } },
3069 { "bcctrl-", XLYLK(19,528,0,1), XLYBB_MASK, PPCCOM, { BOE, BI } },
3070 { "bcctrl+", XLYLK(19,528,1,1), XLYBB_MASK, PPCCOM, { BOE, BI } },
3071 { "bcc", XLLK(19,528,0), XLBB_MASK, PWRCOM, { BO, BI } },
3072 { "bccl", XLLK(19,528,1), XLBB_MASK, PWRCOM, { BO, BI } },
3073 { "bcctre", XLLK(19,529,0), XLYBB_MASK, BOOKE64, { BO, BI } },
3074 { "bcctrel", XLLK(19,529,1), XLYBB_MASK, BOOKE64, { BO, BI } },
3076 { "rlwimi", M(20,0), M_MASK, PPCCOM, { RA,RS,SH,MBE,ME } },
3077 { "rlimi", M(20,0), M_MASK, PWRCOM, { RA,RS,SH,MBE,ME } },
3079 { "rlwimi.", M(20,1), M_MASK, PPCCOM, { RA,RS,SH,MBE,ME } },
3080 { "rlimi.", M(20,1), M_MASK, PWRCOM, { RA,RS,SH,MBE,ME } },
3082 { "rotlwi", MME(21,31,0), MMBME_MASK, PPCCOM, { RA, RS, SH } },
3083 { "clrlwi", MME(21,31,0), MSHME_MASK, PPCCOM, { RA, RS, MB } },
3084 { "rlwinm", M(21,0), M_MASK, PPCCOM, { RA,RS,SH,MBE,ME } },
3085 { "rlinm", M(21,0), M_MASK, PWRCOM, { RA,RS,SH,MBE,ME } },
3086 { "rotlwi.", MME(21,31,1), MMBME_MASK, PPCCOM, { RA,RS,SH } },
3087 { "clrlwi.", MME(21,31,1), MSHME_MASK, PPCCOM, { RA, RS, MB } },
3088 { "rlwinm.", M(21,1), M_MASK, PPCCOM, { RA,RS,SH,MBE,ME } },
3089 { "rlinm.", M(21,1), M_MASK, PWRCOM, { RA,RS,SH,MBE,ME } },
3091 { "rlmi", M(22,0), M_MASK, M601, { RA,RS,RB,MBE,ME } },
3092 { "rlmi.", M(22,1), M_MASK, M601, { RA,RS,RB,MBE,ME } },
3094 { "be", B(22,0,0), B_MASK, BOOKE64, { LI } },
3095 { "bel", B(22,0,1), B_MASK, BOOKE64, { LI } },
3096 { "bea", B(22,1,0), B_MASK, BOOKE64, { LIA } },
3097 { "bela", B(22,1,1), B_MASK, BOOKE64, { LIA } },
3099 { "rotlw", MME(23,31,0), MMBME_MASK, PPCCOM, { RA, RS, RB } },
3100 { "rlwnm", M(23,0), M_MASK, PPCCOM, { RA,RS,RB,MBE,ME } },
3101 { "rlnm", M(23,0), M_MASK, PWRCOM, { RA,RS,RB,MBE,ME } },
3102 { "rotlw.", MME(23,31,1), MMBME_MASK, PPCCOM, { RA, RS, RB } },
3103 { "rlwnm.", M(23,1), M_MASK, PPCCOM, { RA,RS,RB,MBE,ME } },
3104 { "rlnm.", M(23,1), M_MASK, PWRCOM, { RA,RS,RB,MBE,ME } },
3106 { "nop", OP(24), 0xffffffff, PPCCOM, { 0 } },
3107 { "ori", OP(24), OP_MASK, PPCCOM, { RA, RS, UI } },
3108 { "oril", OP(24), OP_MASK, PWRCOM, { RA, RS, UI } },
3110 { "oris", OP(25), OP_MASK, PPCCOM, { RA, RS, UI } },
3111 { "oriu", OP(25), OP_MASK, PWRCOM, { RA, RS, UI } },
3113 { "xori", OP(26), OP_MASK, PPCCOM, { RA, RS, UI } },
3114 { "xoril", OP(26), OP_MASK, PWRCOM, { RA, RS, UI } },
3116 { "xoris", OP(27), OP_MASK, PPCCOM, { RA, RS, UI } },
3117 { "xoriu", OP(27), OP_MASK, PWRCOM, { RA, RS, UI } },
3119 { "andi.", OP(28), OP_MASK, PPCCOM, { RA, RS, UI } },
3120 { "andil.", OP(28), OP_MASK, PWRCOM, { RA, RS, UI } },
3122 { "andis.", OP(29), OP_MASK, PPCCOM, { RA, RS, UI } },
3123 { "andiu.", OP(29), OP_MASK, PWRCOM, { RA, RS, UI } },
3125 { "rotldi", MD(30,0,0), MDMB_MASK, PPC64, { RA, RS, SH6 } },
3126 { "clrldi", MD(30,0,0), MDSH_MASK, PPC64, { RA, RS, MB6 } },
3127 { "rldicl", MD(30,0,0), MD_MASK, PPC64, { RA, RS, SH6, MB6 } },
3128 { "rotldi.", MD(30,0,1), MDMB_MASK, PPC64, { RA, RS, SH6 } },
3129 { "clrldi.", MD(30,0,1), MDSH_MASK, PPC64, { RA, RS, MB6 } },
3130 { "rldicl.", MD(30,0,1), MD_MASK, PPC64, { RA, RS, SH6, MB6 } },
3132 { "rldicr", MD(30,1,0), MD_MASK, PPC64, { RA, RS, SH6, ME6 } },
3133 { "rldicr.", MD(30,1,1), MD_MASK, PPC64, { RA, RS, SH6, ME6 } },
3135 { "rldic", MD(30,2,0), MD_MASK, PPC64, { RA, RS, SH6, MB6 } },
3136 { "rldic.", MD(30,2,1), MD_MASK, PPC64, { RA, RS, SH6, MB6 } },
3138 { "rldimi", MD(30,3,0), MD_MASK, PPC64, { RA, RS, SH6, MB6 } },
3139 { "rldimi.", MD(30,3,1), MD_MASK, PPC64, { RA, RS, SH6, MB6 } },
3141 { "rotld", MDS(30,8,0), MDSMB_MASK, PPC64, { RA, RS, RB } },
3142 { "rldcl", MDS(30,8,0), MDS_MASK, PPC64, { RA, RS, RB, MB6 } },
3143 { "rotld.", MDS(30,8,1), MDSMB_MASK, PPC64, { RA, RS, RB } },
3144 { "rldcl.", MDS(30,8,1), MDS_MASK, PPC64, { RA, RS, RB, MB6 } },
3146 { "rldcr", MDS(30,9,0), MDS_MASK, PPC64, { RA, RS, RB, ME6 } },
3147 { "rldcr.", MDS(30,9,1), MDS_MASK, PPC64, { RA, RS, RB, ME6 } },
3149 { "cmpw", XCMPL(31,0,0), XCMPL_MASK, PPCCOM, { OBF, RA, RB } },
3150 { "cmpd", XCMPL(31,0,1), XCMPL_MASK, PPC64, { OBF, RA, RB } },
3151 { "cmp", X(31,0), XCMP_MASK, PPC, { BF, L, RA, RB } },
3152 { "cmp", X(31,0), XCMPL_MASK, PWRCOM, { BF, RA, RB } },
3154 { "twlgt", XTO(31,4,TOLGT), XTO_MASK, PPCCOM, { RA, RB } },
3155 { "tlgt", XTO(31,4,TOLGT), XTO_MASK, PWRCOM, { RA, RB } },
3156 { "twllt", XTO(31,4,TOLLT), XTO_MASK, PPCCOM, { RA, RB } },
3157 { "tllt", XTO(31,4,TOLLT), XTO_MASK, PWRCOM, { RA, RB } },
3158 { "tweq", XTO(31,4,TOEQ), XTO_MASK, PPCCOM, { RA, RB } },
3159 { "teq", XTO(31,4,TOEQ), XTO_MASK, PWRCOM, { RA, RB } },
3160 { "twlge", XTO(31,4,TOLGE), XTO_MASK, PPCCOM, { RA, RB } },
3161 { "tlge", XTO(31,4,TOLGE), XTO_MASK, PWRCOM, { RA, RB } },
3162 { "twlnl", XTO(31,4,TOLNL), XTO_MASK, PPCCOM, { RA, RB } },
3163 { "tlnl", XTO(31,4,TOLNL), XTO_MASK, PWRCOM, { RA, RB } },
3164 { "twlle", XTO(31,4,TOLLE), XTO_MASK, PPCCOM, { RA, RB } },
3165 { "tlle", XTO(31,4,TOLLE), XTO_MASK, PWRCOM, { RA, RB } },
3166 { "twlng", XTO(31,4,TOLNG), XTO_MASK, PPCCOM, { RA, RB } },
3167 { "tlng", XTO(31,4,TOLNG), XTO_MASK, PWRCOM, { RA, RB } },
3168 { "twgt", XTO(31,4,TOGT), XTO_MASK, PPCCOM, { RA, RB } },
3169 { "tgt", XTO(31,4,TOGT), XTO_MASK, PWRCOM, { RA, RB } },
3170 { "twge", XTO(31,4,TOGE), XTO_MASK, PPCCOM, { RA, RB } },
3171 { "tge", XTO(31,4,TOGE), XTO_MASK, PWRCOM, { RA, RB } },
3172 { "twnl", XTO(31,4,TONL), XTO_MASK, PPCCOM, { RA, RB } },
3173 { "tnl", XTO(31,4,TONL), XTO_MASK, PWRCOM, { RA, RB } },
3174 { "twlt", XTO(31,4,TOLT), XTO_MASK, PPCCOM, { RA, RB } },
3175 { "tlt", XTO(31,4,TOLT), XTO_MASK, PWRCOM, { RA, RB } },
3176 { "twle", XTO(31,4,TOLE), XTO_MASK, PPCCOM, { RA, RB } },
3177 { "tle", XTO(31,4,TOLE), XTO_MASK, PWRCOM, { RA, RB } },
3178 { "twng", XTO(31,4,TONG), XTO_MASK, PPCCOM, { RA, RB } },
3179 { "tng", XTO(31,4,TONG), XTO_MASK, PWRCOM, { RA, RB } },
3180 { "twne", XTO(31,4,TONE), XTO_MASK, PPCCOM, { RA, RB } },
3181 { "tne", XTO(31,4,TONE), XTO_MASK, PWRCOM, { RA, RB } },
3182 { "trap", XTO(31,4,TOU), 0xffffffff, PPCCOM, { 0 } },
3183 { "tw", X(31,4), X_MASK, PPCCOM, { TO, RA, RB } },
3184 { "t", X(31,4), X_MASK, PWRCOM, { TO, RA, RB } },
3186 { "subfc", XO(31,8,0,0), XO_MASK, PPCCOM, { RT, RA, RB } },
3187 { "sf", XO(31,8,0,0), XO_MASK, PWRCOM, { RT, RA, RB } },
3188 { "subc", XO(31,8,0,0), XO_MASK, PPC, { RT, RB, RA } },
3189 { "subfc.", XO(31,8,0,1), XO_MASK, PPCCOM, { RT, RA, RB } },
3190 { "sf.", XO(31,8,0,1), XO_MASK, PWRCOM, { RT, RA, RB } },
3191 { "subc.", XO(31,8,0,1), XO_MASK, PPCCOM, { RT, RB, RA } },
3192 { "subfco", XO(31,8,1,0), XO_MASK, PPCCOM, { RT, RA, RB } },
3193 { "sfo", XO(31,8,1,0), XO_MASK, PWRCOM, { RT, RA, RB } },
3194 { "subco", XO(31,8,1,0), XO_MASK, PPC, { RT, RB, RA } },
3195 { "subfco.", XO(31,8,1,1), XO_MASK, PPCCOM, { RT, RA, RB } },
3196 { "sfo.", XO(31,8,1,1), XO_MASK, PWRCOM, { RT, RA, RB } },
3197 { "subco.", XO(31,8,1,1), XO_MASK, PPC, { RT, RB, RA } },
3199 { "mulhdu", XO(31,9,0,0), XO_MASK, PPC64, { RT, RA, RB } },
3200 { "mulhdu.", XO(31,9,0,1), XO_MASK, PPC64, { RT, RA, RB } },
3202 { "addc", XO(31,10,0,0), XO_MASK, PPCCOM, { RT, RA, RB } },
3203 { "a", XO(31,10,0,0), XO_MASK, PWRCOM, { RT, RA, RB } },
3204 { "addc.", XO(31,10,0,1), XO_MASK, PPCCOM, { RT, RA, RB } },
3205 { "a.", XO(31,10,0,1), XO_MASK, PWRCOM, { RT, RA, RB } },
3206 { "addco", XO(31,10,1,0), XO_MASK, PPCCOM, { RT, RA, RB } },
3207 { "ao", XO(31,10,1,0), XO_MASK, PWRCOM, { RT, RA, RB } },
3208 { "addco.", XO(31,10,1,1), XO_MASK, PPCCOM, { RT, RA, RB } },
3209 { "ao.", XO(31,10,1,1), XO_MASK, PWRCOM, { RT, RA, RB } },
3211 { "mulhwu", XO(31,11,0,0), XO_MASK, PPC, { RT, RA, RB } },
3212 { "mulhwu.", XO(31,11,0,1), XO_MASK, PPC, { RT, RA, RB } },
3214 { "isellt", X(31,15), X_MASK, PPCISEL, { RT, RA, RB } },
3215 { "iselgt", X(31,47), X_MASK, PPCISEL, { RT, RA, RB } },
3216 { "iseleq", X(31,79), X_MASK, PPCISEL, { RT, RA, RB } },
3217 { "isel", XISEL(31,15), XISEL_MASK, PPCISEL, { RT, RA, RB, CRB } },
3219 { "mfcr", X(31,19), XRARB_MASK, NOPOWER4, { RT } },
3220 { "mfcr", X(31,19), XFXFXM_MASK, POWER4, { RT, FXM4 } },
3222 { "lwarx", X(31,20), X_MASK, PPC, { RT, RA0, RB } },
3224 { "ldx", X(31,21), X_MASK, PPC64, { RT, RA0, RB } },
3226 { "icbt", X(31,22), X_MASK, BOOKE, { CT, RA, RB } },
3227 { "icbt", X(31,262), XRT_MASK, PPC403, { RA, RB } },
3229 { "lwzx", X(31,23), X_MASK, PPCCOM, { RT, RA0, RB } },
3230 { "lx", X(31,23), X_MASK, PWRCOM, { RT, RA, RB } },
3232 { "slw", XRC(31,24,0), X_MASK, PPCCOM, { RA, RS, RB } },
3233 { "sl", XRC(31,24,0), X_MASK, PWRCOM, { RA, RS, RB } },
3234 { "slw.", XRC(31,24,1), X_MASK, PPCCOM, { RA, RS, RB } },
3235 { "sl.", XRC(31,24,1), X_MASK, PWRCOM, { RA, RS, RB } },
3237 { "cntlzw", XRC(31,26,0), XRB_MASK, PPCCOM, { RA, RS } },
3238 { "cntlz", XRC(31,26,0), XRB_MASK, PWRCOM, { RA, RS } },
3239 { "cntlzw.", XRC(31,26,1), XRB_MASK, PPCCOM, { RA, RS } },
3240 { "cntlz.", XRC(31,26,1), XRB_MASK, PWRCOM, { RA, RS } },
3242 { "sld", XRC(31,27,0), X_MASK, PPC64, { RA, RS, RB } },
3243 { "sld.", XRC(31,27,1), X_MASK, PPC64, { RA, RS, RB } },
3245 { "and", XRC(31,28,0), X_MASK, COM, { RA, RS, RB } },
3246 { "and.", XRC(31,28,1), X_MASK, COM, { RA, RS, RB } },
3248 { "maskg", XRC(31,29,0), X_MASK, M601, { RA, RS, RB } },
3249 { "maskg.", XRC(31,29,1), X_MASK, M601, { RA, RS, RB } },
3251 { "icbte", X(31,30), X_MASK, BOOKE64, { CT, RA, RB } },
3253 { "lwzxe", X(31,31), X_MASK, BOOKE64, { RT, RA0, RB } },
3255 { "cmplw", XCMPL(31,32,0), XCMPL_MASK, PPCCOM, { OBF, RA, RB } },
3256 { "cmpld", XCMPL(31,32,1), XCMPL_MASK, PPC64, { OBF, RA, RB } },
3257 { "cmpl", X(31,32), XCMP_MASK, PPC, { BF, L, RA, RB } },
3258 { "cmpl", X(31,32), XCMPL_MASK, PWRCOM, { BF, RA, RB } },
3260 { "subf", XO(31,40,0,0), XO_MASK, PPC, { RT, RA, RB } },
3261 { "sub", XO(31,40,0,0), XO_MASK, PPC, { RT, RB, RA } },
3262 { "subf.", XO(31,40,0,1), XO_MASK, PPC, { RT, RA, RB } },
3263 { "sub.", XO(31,40,0,1), XO_MASK, PPC, { RT, RB, RA } },
3264 { "subfo", XO(31,40,1,0), XO_MASK, PPC, { RT, RA, RB } },
3265 { "subo", XO(31,40,1,0), XO_MASK, PPC, { RT, RB, RA } },
3266 { "subfo.", XO(31,40,1,1), XO_MASK, PPC, { RT, RA, RB } },
3267 { "subo.", XO(31,40,1,1), XO_MASK, PPC, { RT, RB, RA } },
3269 { "ldux", X(31,53), X_MASK, PPC64, { RT, RAL, RB } },
3271 { "dcbst", X(31,54), XRT_MASK, PPC, { RA, RB } },
3273 { "lwzux", X(31,55), X_MASK, PPCCOM, { RT, RAL, RB } },
3274 { "lux", X(31,55), X_MASK, PWRCOM, { RT, RA, RB } },
3276 { "dcbste", X(31,62), XRT_MASK, BOOKE64, { RA, RB } },
3278 { "lwzuxe", X(31,63), X_MASK, BOOKE64, { RT, RAL, RB } },
3280 { "cntlzd", XRC(31,58,0), XRB_MASK, PPC64, { RA, RS } },
3281 { "cntlzd.", XRC(31,58,1), XRB_MASK, PPC64, { RA, RS } },
3283 { "andc", XRC(31,60,0), X_MASK, COM, { RA, RS, RB } },
3284 { "andc.", XRC(31,60,1), X_MASK, COM, { RA, RS, RB } },
3286 { "tdlgt", XTO(31,68,TOLGT), XTO_MASK, PPC64, { RA, RB } },
3287 { "tdllt", XTO(31,68,TOLLT), XTO_MASK, PPC64, { RA, RB } },
3288 { "tdeq", XTO(31,68,TOEQ), XTO_MASK, PPC64, { RA, RB } },
3289 { "tdlge", XTO(31,68,TOLGE), XTO_MASK, PPC64, { RA, RB } },
3290 { "tdlnl", XTO(31,68,TOLNL), XTO_MASK, PPC64, { RA, RB } },
3291 { "tdlle", XTO(31,68,TOLLE), XTO_MASK, PPC64, { RA, RB } },
3292 { "tdlng", XTO(31,68,TOLNG), XTO_MASK, PPC64, { RA, RB } },
3293 { "tdgt", XTO(31,68,TOGT), XTO_MASK, PPC64, { RA, RB } },
3294 { "tdge", XTO(31,68,TOGE), XTO_MASK, PPC64, { RA, RB } },
3295 { "tdnl", XTO(31,68,TONL), XTO_MASK, PPC64, { RA, RB } },
3296 { "tdlt", XTO(31,68,TOLT), XTO_MASK, PPC64, { RA, RB } },
3297 { "tdle", XTO(31,68,TOLE), XTO_MASK, PPC64, { RA, RB } },
3298 { "tdng", XTO(31,68,TONG), XTO_MASK, PPC64, { RA, RB } },
3299 { "tdne", XTO(31,68,TONE), XTO_MASK, PPC64, { RA, RB } },
3300 { "td", X(31,68), X_MASK, PPC64, { TO, RA, RB } },
3302 { "mulhd", XO(31,73,0,0), XO_MASK, PPC64, { RT, RA, RB } },
3303 { "mulhd.", XO(31,73,0,1), XO_MASK, PPC64, { RT, RA, RB } },
3305 { "mulhw", XO(31,75,0,0), XO_MASK, PPC, { RT, RA, RB } },
3306 { "mulhw.", XO(31,75,0,1), XO_MASK, PPC, { RT, RA, RB } },
3308 { "dlmzb", XRC(31,78,0), X_MASK, PPC403|PPC440, { RA, RS, RB } },
3309 { "dlmzb.", XRC(31,78,1), X_MASK, PPC403|PPC440, { RA, RS, RB } },
3311 { "mtsrd", X(31,82), XRB_MASK|(1<<20), PPC64, { SR, RS } },
3313 { "mfmsr", X(31,83), XRARB_MASK, COM, { RT } },
3315 { "ldarx", X(31,84), X_MASK, PPC64, { RT, RA0, RB } },
3317 { "dcbf", X(31,86), XRT_MASK, PPC, { RA, RB } },
3319 { "lbzx", X(31,87), X_MASK, COM, { RT, RA0, RB } },
3321 { "dcbfe", X(31,94), XRT_MASK, BOOKE64, { RA, RB } },
3323 { "lbzxe", X(31,95), X_MASK, BOOKE64, { RT, RA0, RB } },
3325 { "neg", XO(31,104,0,0), XORB_MASK, COM, { RT, RA } },
3326 { "neg.", XO(31,104,0,1), XORB_MASK, COM, { RT, RA } },
3327 { "nego", XO(31,104,1,0), XORB_MASK, COM, { RT, RA } },
3328 { "nego.", XO(31,104,1,1), XORB_MASK, COM, { RT, RA } },
3330 { "mul", XO(31,107,0,0), XO_MASK, M601, { RT, RA, RB } },
3331 { "mul.", XO(31,107,0,1), XO_MASK, M601, { RT, RA, RB } },
3332 { "mulo", XO(31,107,1,0), XO_MASK, M601, { RT, RA, RB } },
3333 { "mulo.", XO(31,107,1,1), XO_MASK, M601, { RT, RA, RB } },
3335 { "mtsrdin", X(31,114), XRA_MASK, PPC64, { RS, RB } },
3337 { "clf", X(31,118), XTO_MASK, POWER, { RA, RB } },
3339 { "lbzux", X(31,119), X_MASK, COM, { RT, RAL, RB } },
3341 { "not", XRC(31,124,0), X_MASK, COM, { RA, RS, RBS } },
3342 { "nor", XRC(31,124,0), X_MASK, COM, { RA, RS, RB } },
3343 { "not.", XRC(31,124,1), X_MASK, COM, { RA, RS, RBS } },
3344 { "nor.", XRC(31,124,1), X_MASK, COM, { RA, RS, RB } },
3346 { "lwarxe", X(31,126), X_MASK, BOOKE64, { RT, RA0, RB } },
3348 { "lbzuxe", X(31,127), X_MASK, BOOKE64, { RT, RAL, RB } },
3350 { "wrtee", X(31,131), XRARB_MASK, PPC403 | BOOKE, { RS } },
3352 { "dcbtstls",X(31,134), X_MASK, PPCCHLK, { CT, RA, RB }},
3354 { "subfe", XO(31,136,0,0), XO_MASK, PPCCOM, { RT, RA, RB } },
3355 { "sfe", XO(31,136,0,0), XO_MASK, PWRCOM, { RT, RA, RB } },
3356 { "subfe.", XO(31,136,0,1), XO_MASK, PPCCOM, { RT, RA, RB } },
3357 { "sfe.", XO(31,136,0,1), XO_MASK, PWRCOM, { RT, RA, RB } },
3358 { "subfeo", XO(31,136,1,0), XO_MASK, PPCCOM, { RT, RA, RB } },
3359 { "sfeo", XO(31,136,1,0), XO_MASK, PWRCOM, { RT, RA, RB } },
3360 { "subfeo.", XO(31,136,1,1), XO_MASK, PPCCOM, { RT, RA, RB } },
3361 { "sfeo.", XO(31,136,1,1), XO_MASK, PWRCOM, { RT, RA, RB } },
3363 { "adde", XO(31,138,0,0), XO_MASK, PPCCOM, { RT, RA, RB } },
3364 { "ae", XO(31,138,0,0), XO_MASK, PWRCOM, { RT, RA, RB } },
3365 { "adde.", XO(31,138,0,1), XO_MASK, PPCCOM, { RT, RA, RB } },
3366 { "ae.", XO(31,138,0,1), XO_MASK, PWRCOM, { RT, RA, RB } },
3367 { "addeo", XO(31,138,1,0), XO_MASK, PPCCOM, { RT, RA, RB } },
3368 { "aeo", XO(31,138,1,0), XO_MASK, PWRCOM, { RT, RA, RB } },
3369 { "addeo.", XO(31,138,1,1), XO_MASK, PPCCOM, { RT, RA, RB } },
3370 { "aeo.", XO(31,138,1,1), XO_MASK, PWRCOM, { RT, RA, RB } },
3372 { "dcbtstlse",X(31,142),X_MASK, PPCCHLK64, { CT, RA, RB }},
3374 { "mtcr", XFXM(31,144,0xff), XRARB_MASK, COM, { RS }},
3375 { "mtcrf", X(31,144), XFXFXM_MASK, COM, { FXM, RS } },
3377 { "mtmsr", X(31,146), XRARB_MASK, COM, { RS } },
3379 { "stdx", X(31,149), X_MASK, PPC64, { RS, RA0, RB } },
3381 { "stwcx.", XRC(31,150,1), X_MASK, PPC, { RS, RA0, RB } },
3383 { "stwx", X(31,151), X_MASK, PPCCOM, { RS, RA0, RB } },
3384 { "stx", X(31,151), X_MASK, PWRCOM, { RS, RA, RB } },
3386 { "stwcxe.", XRC(31,158,1), X_MASK, BOOKE64, { RS, RA0, RB } },
3388 { "stwxe", X(31,159), X_MASK, BOOKE64, { RS, RA0, RB } },
3390 { "slq", XRC(31,152,0), X_MASK, M601, { RA, RS, RB } },
3391 { "slq.", XRC(31,152,1), X_MASK, M601, { RA, RS, RB } },
3393 { "sle", XRC(31,153,0), X_MASK, M601, { RA, RS, RB } },
3394 { "sle.", XRC(31,153,1), X_MASK, M601, { RA, RS, RB } },
3396 { "wrteei", X(31,163), XE_MASK, PPC403 | BOOKE, { E } },
3398 { "dcbtls", X(31,166), X_MASK, PPCCHLK, { CT, RA, RB }},
3399 { "dcbtlse", X(31,174), X_MASK, PPCCHLK64, { CT, RA, RB }},
3401 { "mtmsrd", X(31,178), XRLARB_MASK, PPC64, { RS, MTMSRD_L } },
3403 { "stdux", X(31,181), X_MASK, PPC64, { RS, RAS, RB } },
3405 { "stwux", X(31,183), X_MASK, PPCCOM, { RS, RAS, RB } },
3406 { "stux", X(31,183), X_MASK, PWRCOM, { RS, RA0, RB } },
3408 { "sliq", XRC(31,184,0), X_MASK, M601, { RA, RS, SH } },
3409 { "sliq.", XRC(31,184,1), X_MASK, M601, { RA, RS, SH } },
3411 { "stwuxe", X(31,191), X_MASK, BOOKE64, { RS, RAS, RB } },
3413 { "subfze", XO(31,200,0,0), XORB_MASK, PPCCOM, { RT, RA } },
3414 { "sfze", XO(31,200,0,0), XORB_MASK, PWRCOM, { RT, RA } },
3415 { "subfze.", XO(31,200,0,1), XORB_MASK, PPCCOM, { RT, RA } },
3416 { "sfze.", XO(31,200,0,1), XORB_MASK, PWRCOM, { RT, RA } },
3417 { "subfzeo", XO(31,200,1,0), XORB_MASK, PPCCOM, { RT, RA } },
3418 { "sfzeo", XO(31,200,1,0), XORB_MASK, PWRCOM, { RT, RA } },
3419 { "subfzeo.",XO(31,200,1,1), XORB_MASK, PPCCOM, { RT, RA } },
3420 { "sfzeo.", XO(31,200,1,1), XORB_MASK, PWRCOM, { RT, RA } },
3422 { "addze", XO(31,202,0,0), XORB_MASK, PPCCOM, { RT, RA } },
3423 { "aze", XO(31,202,0,0), XORB_MASK, PWRCOM, { RT, RA } },
3424 { "addze.", XO(31,202,0,1), XORB_MASK, PPCCOM, { RT, RA } },
3425 { "aze.", XO(31,202,0,1), XORB_MASK, PWRCOM, { RT, RA } },
3426 { "addzeo", XO(31,202,1,0), XORB_MASK, PPCCOM, { RT, RA } },
3427 { "azeo", XO(31,202,1,0), XORB_MASK, PWRCOM, { RT, RA } },
3428 { "addzeo.", XO(31,202,1,1), XORB_MASK, PPCCOM, { RT, RA } },
3429 { "azeo.", XO(31,202,1,1), XORB_MASK, PWRCOM, { RT, RA } },
3431 { "mtsr", X(31,210), XRB_MASK|(1<<20), COM32, { SR, RS } },
3433 { "stdcx.", XRC(31,214,1), X_MASK, PPC64, { RS, RA0, RB } },
3435 { "stbx", X(31,215), X_MASK, COM, { RS, RA0, RB } },
3437 { "sllq", XRC(31,216,0), X_MASK, M601, { RA, RS, RB } },
3438 { "sllq.", XRC(31,216,1), X_MASK, M601, { RA, RS, RB } },
3440 { "sleq", XRC(31,217,0), X_MASK, M601, { RA, RS, RB } },
3441 { "sleq.", XRC(31,217,1), X_MASK, M601, { RA, RS, RB } },
3443 { "stbxe", X(31,223), X_MASK, BOOKE64, { RS, RA0, RB } },
3445 { "icblc", X(31,230), X_MASK, PPCCHLK, { CT, RA, RB }},
3447 { "subfme", XO(31,232,0,0), XORB_MASK, PPCCOM, { RT, RA } },
3448 { "sfme", XO(31,232,0,0), XORB_MASK, PWRCOM, { RT, RA } },
3449 { "subfme.", XO(31,232,0,1), XORB_MASK, PPCCOM, { RT, RA } },
3450 { "sfme.", XO(31,232,0,1), XORB_MASK, PWRCOM, { RT, RA } },
3451 { "subfmeo", XO(31,232,1,0), XORB_MASK, PPCCOM, { RT, RA } },
3452 { "sfmeo", XO(31,232,1,0), XORB_MASK, PWRCOM, { RT, RA } },
3453 { "subfmeo.",XO(31,232,1,1), XORB_MASK, PPCCOM, { RT, RA } },
3454 { "sfmeo.", XO(31,232,1,1), XORB_MASK, PWRCOM, { RT, RA } },
3456 { "mulld", XO(31,233,0,0), XO_MASK, PPC64, { RT, RA, RB } },
3457 { "mulld.", XO(31,233,0,1), XO_MASK, PPC64, { RT, RA, RB } },
3458 { "mulldo", XO(31,233,1,0), XO_MASK, PPC64, { RT, RA, RB } },
3459 { "mulldo.", XO(31,233,1,1), XO_MASK, PPC64, { RT, RA, RB } },
3461 { "addme", XO(31,234,0,0), XORB_MASK, PPCCOM, { RT, RA } },
3462 { "ame", XO(31,234,0,0), XORB_MASK, PWRCOM, { RT, RA } },
3463 { "addme.", XO(31,234,0,1), XORB_MASK, PPCCOM, { RT, RA } },
3464 { "ame.", XO(31,234,0,1), XORB_MASK, PWRCOM, { RT, RA } },
3465 { "addmeo", XO(31,234,1,0), XORB_MASK, PPCCOM, { RT, RA } },
3466 { "ameo", XO(31,234,1,0), XORB_MASK, PWRCOM, { RT, RA } },
3467 { "addmeo.", XO(31,234,1,1), XORB_MASK, PPCCOM, { RT, RA } },
3468 { "ameo.", XO(31,234,1,1), XORB_MASK, PWRCOM, { RT, RA } },
3470 { "mullw", XO(31,235,0,0), XO_MASK, PPCCOM, { RT, RA, RB } },
3471 { "muls", XO(31,235,0,0), XO_MASK, PWRCOM, { RT, RA, RB } },
3472 { "mullw.", XO(31,235,0,1), XO_MASK, PPCCOM, { RT, RA, RB } },
3473 { "muls.", XO(31,235,0,1), XO_MASK, PWRCOM, { RT, RA, RB } },
3474 { "mullwo", XO(31,235,1,0), XO_MASK, PPCCOM, { RT, RA, RB } },
3475 { "mulso", XO(31,235,1,0), XO_MASK, PWRCOM, { RT, RA, RB } },
3476 { "mullwo.", XO(31,235,1,1), XO_MASK, PPCCOM, { RT, RA, RB } },
3477 { "mulso.", XO(31,235,1,1), XO_MASK, PWRCOM, { RT, RA, RB } },
3479 { "icblce", X(31,238), X_MASK, PPCCHLK64, { CT, RA, RB }},
3480 { "mtsrin", X(31,242), XRA_MASK, PPC32, { RS, RB } },
3481 { "mtsri", X(31,242), XRA_MASK, POWER32, { RS, RB } },
3483 { "dcbtst", X(31,246), X_MASK, PPC, { CT, RA, RB } },
3485 { "stbux", X(31,247), X_MASK, COM, { RS, RAS, RB } },
3487 { "slliq", XRC(31,248,0), X_MASK, M601, { RA, RS, SH } },
3488 { "slliq.", XRC(31,248,1), X_MASK, M601, { RA, RS, SH } },
3490 { "dcbtste", X(31,253), X_MASK, BOOKE64, { CT, RA, RB } },
3492 { "stbuxe", X(31,255), X_MASK, BOOKE64, { RS, RAS, RB } },
3494 { "mfdcrx", X(31,259), X_MASK, BOOKE, { RS, RA } },
3496 { "doz", XO(31,264,0,0), XO_MASK, M601, { RT, RA, RB } },
3497 { "doz.", XO(31,264,0,1), XO_MASK, M601, { RT, RA, RB } },
3498 { "dozo", XO(31,264,1,0), XO_MASK, M601, { RT, RA, RB } },
3499 { "dozo.", XO(31,264,1,1), XO_MASK, M601, { RT, RA, RB } },
3501 { "add", XO(31,266,0,0), XO_MASK, PPCCOM, { RT, RA, RB } },
3502 { "cax", XO(31,266,0,0), XO_MASK, PWRCOM, { RT, RA, RB } },
3503 { "add.", XO(31,266,0,1), XO_MASK, PPCCOM, { RT, RA, RB } },
3504 { "cax.", XO(31,266,0,1), XO_MASK, PWRCOM, { RT, RA, RB } },
3505 { "addo", XO(31,266,1,0), XO_MASK, PPCCOM, { RT, RA, RB } },
3506 { "caxo", XO(31,266,1,0), XO_MASK, PWRCOM, { RT, RA, RB } },
3507 { "addo.", XO(31,266,1,1), XO_MASK, PPCCOM, { RT, RA, RB } },
3508 { "caxo.", XO(31,266,1,1), XO_MASK, PWRCOM, { RT, RA, RB } },
3510 { "tlbiel", X(31,274), XRTRA_MASK, POWER4, { RB } },
3512 { "mfapidi", X(31,275), X_MASK, BOOKE, { RT, RA } },
3514 { "lscbx", XRC(31,277,0), X_MASK, M601, { RT, RA, RB } },
3515 { "lscbx.", XRC(31,277,1), X_MASK, M601, { RT, RA, RB } },
3517 { "dcbt", X(31,278), X_MASK, PPC, { CT, RA, RB } },
3519 { "lhzx", X(31,279), X_MASK, COM, { RT, RA0, RB } },
3521 { "eqv", XRC(31,284,0), X_MASK, COM, { RA, RS, RB } },
3522 { "eqv.", XRC(31,284,1), X_MASK, COM, { RA, RS, RB } },
3524 { "dcbte", X(31,286), X_MASK, BOOKE64, { CT, RA, RB } },
3526 { "lhzxe", X(31,287), X_MASK, BOOKE64, { RT, RA0, RB } },
3528 { "tlbie", X(31,306), XRTLRA_MASK, PPC, { RB, L } },
3529 { "tlbi", X(31,306), XRT_MASK, POWER, { RA0, RB } },
3531 { "eciwx", X(31,310), X_MASK, PPC, { RT, RA, RB } },
3533 { "lhzux", X(31,311), X_MASK, COM, { RT, RAL, RB } },
3535 { "xor", XRC(31,316,0), X_MASK, COM, { RA, RS, RB } },
3536 { "xor.", XRC(31,316,1), X_MASK, COM, { RA, RS, RB } },
3538 { "lhzuxe", X(31,319), X_MASK, BOOKE64, { RT, RAL, RB } },
3540 { "mfexisr", XSPR(31,323,64), XSPR_MASK, PPC403, { RT } },
3541 { "mfexier", XSPR(31,323,66), XSPR_MASK, PPC403, { RT } },
3542 { "mfbr0", XSPR(31,323,128), XSPR_MASK, PPC403, { RT } },
3543 { "mfbr1", XSPR(31,323,129), XSPR_MASK, PPC403, { RT } },
3544 { "mfbr2", XSPR(31,323,130), XSPR_MASK, PPC403, { RT } },
3545 { "mfbr3", XSPR(31,323,131), XSPR_MASK, PPC403, { RT } },
3546 { "mfbr4", XSPR(31,323,132), XSPR_MASK, PPC403, { RT } },
3547 { "mfbr5", XSPR(31,323,133), XSPR_MASK, PPC403, { RT } },
3548 { "mfbr6", XSPR(31,323,134), XSPR_MASK, PPC403, { RT } },
3549 { "mfbr7", XSPR(31,323,135), XSPR_MASK, PPC403, { RT } },
3550 { "mfbear", XSPR(31,323,144), XSPR_MASK, PPC403, { RT } },
3551 { "mfbesr", XSPR(31,323,145), XSPR_MASK, PPC403, { RT } },
3552 { "mfiocr", XSPR(31,323,160), XSPR_MASK, PPC403, { RT } },
3553 { "mfdmacr0", XSPR(31,323,192), XSPR_MASK, PPC403, { RT } },
3554 { "mfdmact0", XSPR(31,323,193), XSPR_MASK, PPC403, { RT } },
3555 { "mfdmada0", XSPR(31,323,194), XSPR_MASK, PPC403, { RT } },
3556 { "mfdmasa0", XSPR(31,323,195), XSPR_MASK, PPC403, { RT } },
3557 { "mfdmacc0", XSPR(31,323,196), XSPR_MASK, PPC403, { RT } },
3558 { "mfdmacr1", XSPR(31,323,200), XSPR_MASK, PPC403, { RT } },
3559 { "mfdmact1", XSPR(31,323,201), XSPR_MASK, PPC403, { RT } },
3560 { "mfdmada1", XSPR(31,323,202), XSPR_MASK, PPC403, { RT } },
3561 { "mfdmasa1", XSPR(31,323,203), XSPR_MASK, PPC403, { RT } },
3562 { "mfdmacc1", XSPR(31,323,204), XSPR_MASK, PPC403, { RT } },
3563 { "mfdmacr2", XSPR(31,323,208), XSPR_MASK, PPC403, { RT } },
3564 { "mfdmact2", XSPR(31,323,209), XSPR_MASK, PPC403, { RT } },
3565 { "mfdmada2", XSPR(31,323,210), XSPR_MASK, PPC403, { RT } },
3566 { "mfdmasa2", XSPR(31,323,211), XSPR_MASK, PPC403, { RT } },
3567 { "mfdmacc2", XSPR(31,323,212), XSPR_MASK, PPC403, { RT } },
3568 { "mfdmacr3", XSPR(31,323,216), XSPR_MASK, PPC403, { RT } },
3569 { "mfdmact3", XSPR(31,323,217), XSPR_MASK, PPC403, { RT } },
3570 { "mfdmada3", XSPR(31,323,218), XSPR_MASK, PPC403, { RT } },
3571 { "mfdmasa3", XSPR(31,323,219), XSPR_MASK, PPC403, { RT } },
3572 { "mfdmacc3", XSPR(31,323,220), XSPR_MASK, PPC403, { RT } },
3573 { "mfdmasr", XSPR(31,323,224), XSPR_MASK, PPC403, { RT } },
3574 { "mfdcr", X(31,323), X_MASK, PPC403 | BOOKE, { RT, SPR } },
3576 { "div", XO(31,331,0,0), XO_MASK, M601, { RT, RA, RB } },
3577 { "div.", XO(31,331,0,1), XO_MASK, M601, { RT, RA, RB } },
3578 { "divo", XO(31,331,1,0), XO_MASK, M601, { RT, RA, RB } },
3579 { "divo.", XO(31,331,1,1), XO_MASK, M601, { RT, RA, RB } },
3581 { "mfpmr", X(31,334), X_MASK, PPCPMR, { RT, PMR }},
3583 { "mfmq", XSPR(31,339,0), XSPR_MASK, M601, { RT } },
3584 { "mfxer", XSPR(31,339,1), XSPR_MASK, COM, { RT } },
3585 { "mfrtcu", XSPR(31,339,4), XSPR_MASK, COM, { RT } },
3586 { "mfrtcl", XSPR(31,339,5), XSPR_MASK, COM, { RT } },
3587 { "mfdec", XSPR(31,339,6), XSPR_MASK, MFDEC1, { RT } },
3588 { "mfdec", XSPR(31,339,22), XSPR_MASK, MFDEC2, { RT } },
3589 { "mflr", XSPR(31,339,8), XSPR_MASK, COM, { RT } },
3590 { "mfctr", XSPR(31,339,9), XSPR_MASK, COM, { RT } },
3591 { "mftid", XSPR(31,339,17), XSPR_MASK, POWER, { RT } },
3592 { "mfdsisr", XSPR(31,339,18), XSPR_MASK, COM, { RT } },
3593 { "mfdar", XSPR(31,339,19), XSPR_MASK, COM, { RT } },
3594 { "mfsdr0", XSPR(31,339,24), XSPR_MASK, POWER, { RT } },
3595 { "mfsdr1", XSPR(31,339,25), XSPR_MASK, COM, { RT } },
3596 { "mfsrr0", XSPR(31,339,26), XSPR_MASK, COM, { RT } },
3597 { "mfsrr1", XSPR(31,339,27), XSPR_MASK, COM, { RT } },
3598 { "mfpid", XSPR(31,339,48), XSPR_MASK, BOOKE, { RT } },
3599 { "mfpid", XSPR(31,339,945), XSPR_MASK, PPC403, { RT } },
3600 { "mfcsrr0", XSPR(31,339,58), XSPR_MASK, BOOKE, { RT } },
3601 { "mfcsrr1", XSPR(31,339,59), XSPR_MASK, BOOKE, { RT } },
3602 { "mfdear", XSPR(31,339,61), XSPR_MASK, BOOKE, { RT } },
3603 { "mfdear", XSPR(31,339,981), XSPR_MASK, PPC403, { RT } },
3604 { "mfesr", XSPR(31,339,62), XSPR_MASK, BOOKE, { RT } },
3605 { "mfesr", XSPR(31,339,980), XSPR_MASK, PPC403, { RT } },
3606 { "mfivpr", XSPR(31,339,63), XSPR_MASK, BOOKE, { RT } },
3607 { "mfcmpa", XSPR(31,339,144), XSPR_MASK, PPC860, { RT } },
3608 { "mfcmpb", XSPR(31,339,145), XSPR_MASK, PPC860, { RT } },
3609 { "mfcmpc", XSPR(31,339,146), XSPR_MASK, PPC860, { RT } },
3610 { "mfcmpd", XSPR(31,339,147), XSPR_MASK, PPC860, { RT } },
3611 { "mficr", XSPR(31,339,148), XSPR_MASK, PPC860, { RT } },
3612 { "mfder", XSPR(31,339,149), XSPR_MASK, PPC860, { RT } },
3613 { "mfcounta", XSPR(31,339,150), XSPR_MASK, PPC860, { RT } },
3614 { "mfcountb", XSPR(31,339,151), XSPR_MASK, PPC860, { RT } },
3615 { "mfcmpe", XSPR(31,339,152), XSPR_MASK, PPC860, { RT } },
3616 { "mfcmpf", XSPR(31,339,153), XSPR_MASK, PPC860, { RT } },
3617 { "mfcmpg", XSPR(31,339,154), XSPR_MASK, PPC860, { RT } },
3618 { "mfcmph", XSPR(31,339,155), XSPR_MASK, PPC860, { RT } },
3619 { "mflctrl1", XSPR(31,339,156), XSPR_MASK, PPC860, { RT } },
3620 { "mflctrl2", XSPR(31,339,157), XSPR_MASK, PPC860, { RT } },
3621 { "mfictrl", XSPR(31,339,158), XSPR_MASK, PPC860, { RT } },
3622 { "mfbar", XSPR(31,339,159), XSPR_MASK, PPC860, { RT } },
3623 { "mfvrsave", XSPR(31,339,256), XSPR_MASK, PPCVEC, { RT } },
3624 { "mfusprg0", XSPR(31,339,256), XSPR_MASK, BOOKE, { RT } },
3625 { "mfsprg4", XSPR(31,339,260), XSPR_MASK, PPC405, { RT } },
3626 { "mfsprg4", XSPR(31,339,260), XSPR_MASK, BOOKE, { RT } },
3627 { "mfsprg5", XSPR(31,339,261), XSPR_MASK, PPC405, { RT } },
3628 { "mfsprg5", XSPR(31,339,261), XSPR_MASK, BOOKE, { RT } },
3629 { "mfsprg6", XSPR(31,339,262), XSPR_MASK, PPC405, { RT } },
3630 { "mfsprg6", XSPR(31,339,262), XSPR_MASK, BOOKE, { RT } },
3631 { "mfsprg7", XSPR(31,339,263), XSPR_MASK, PPC405, { RT } },
3632 { "mfsprg7", XSPR(31,339,263), XSPR_MASK, BOOKE, { RT } },
3633 { "mftb", X(31,371), X_MASK, CLASSIC, { RT, TBR } },
3634 { "mftb", XSPR(31,339,268), XSPR_MASK, BOOKE, { RT } },
3635 { "mftbl", XSPR(31,371,268), XSPR_MASK, CLASSIC, { RT } },
3636 { "mftbl", XSPR(31,339,268), XSPR_MASK, BOOKE, { RT } },
3637 { "mftbu", XSPR(31,371,269), XSPR_MASK, CLASSIC, { RT } },
3638 { "mftbu", XSPR(31,339,269), XSPR_MASK, BOOKE, { RT } },
3639 { "mfsprg", XSPR(31,339,272), XSPRG_MASK, PPC, { RT, SPRG } },
3640 { "mfsprg0", XSPR(31,339,272), XSPR_MASK, PPC, { RT } },
3641 { "mfsprg1", XSPR(31,339,273), XSPR_MASK, PPC, { RT } },
3642 { "mfsprg2", XSPR(31,339,274), XSPR_MASK, PPC, { RT } },
3643 { "mfsprg3", XSPR(31,339,275), XSPR_MASK, PPC, { RT } },
3644 { "mfasr", XSPR(31,339,280), XSPR_MASK, PPC64, { RT } },
3645 { "mfear", XSPR(31,339,282), XSPR_MASK, PPC, { RT } },
3646 { "mfpir", XSPR(31,339,286), XSPR_MASK, BOOKE, { RT } },
3647 { "mfpvr", XSPR(31,339,287), XSPR_MASK, PPC, { RT } },
3648 { "mfdbsr", XSPR(31,339,304), XSPR_MASK, BOOKE, { RT } },
3649 { "mfdbsr", XSPR(31,339,1008), XSPR_MASK, PPC403, { RT } },
3650 { "mfdbcr0", XSPR(31,339,308), XSPR_MASK, BOOKE, { RT } },
3651 { "mfdbcr0", XSPR(31,339,1010), XSPR_MASK, PPC405, { RT } },
3652 { "mfdbcr1", XSPR(31,339,309), XSPR_MASK, BOOKE, { RT } },
3653 { "mfdbcr1", XSPR(31,339,957), XSPR_MASK, PPC405, { RT } },
3654 { "mfdbcr2", XSPR(31,339,310), XSPR_MASK, BOOKE, { RT } },
3655 { "mfiac1", XSPR(31,339,312), XSPR_MASK, BOOKE, { RT } },
3656 { "mfiac1", XSPR(31,339,1012), XSPR_MASK, PPC403, { RT } },
3657 { "mfiac2", XSPR(31,339,313), XSPR_MASK, BOOKE, { RT } },
3658 { "mfiac2", XSPR(31,339,1013), XSPR_MASK, PPC403, { RT } },
3659 { "mfiac3", XSPR(31,339,314), XSPR_MASK, BOOKE, { RT } },
3660 { "mfiac3", XSPR(31,339,948), XSPR_MASK, PPC405, { RT } },
3661 { "mfiac4", XSPR(31,339,315), XSPR_MASK, BOOKE, { RT } },
3662 { "mfiac4", XSPR(31,339,949), XSPR_MASK, PPC405, { RT } },
3663 { "mfdac1", XSPR(31,339,316), XSPR_MASK, BOOKE, { RT } },
3664 { "mfdac1", XSPR(31,339,1014), XSPR_MASK, PPC403, { RT } },
3665 { "mfdac2", XSPR(31,339,317), XSPR_MASK, BOOKE, { RT } },
3666 { "mfdac2", XSPR(31,339,1015), XSPR_MASK, PPC403, { RT } },
3667 { "mfdvc1", XSPR(31,339,318), XSPR_MASK, BOOKE, { RT } },
3668 { "mfdvc1", XSPR(31,339,950), XSPR_MASK, PPC405, { RT } },
3669 { "mfdvc2", XSPR(31,339,319), XSPR_MASK, BOOKE, { RT } },
3670 { "mfdvc2", XSPR(31,339,951), XSPR_MASK, PPC405, { RT } },
3671 { "mftsr", XSPR(31,339,336), XSPR_MASK, BOOKE, { RT } },
3672 { "mftsr", XSPR(31,339,984), XSPR_MASK, PPC403, { RT } },
3673 { "mftcr", XSPR(31,339,340), XSPR_MASK, BOOKE, { RT } },
3674 { "mftcr", XSPR(31,339,986), XSPR_MASK, PPC403, { RT } },
3675 { "mfivor0", XSPR(31,339,400), XSPR_MASK, BOOKE, { RT } },
3676 { "mfivor1", XSPR(31,339,401), XSPR_MASK, BOOKE, { RT } },
3677 { "mfivor2", XSPR(31,339,402), XSPR_MASK, BOOKE, { RT } },
3678 { "mfivor3", XSPR(31,339,403), XSPR_MASK, BOOKE, { RT } },
3679 { "mfivor4", XSPR(31,339,404), XSPR_MASK, BOOKE, { RT } },
3680 { "mfivor5", XSPR(31,339,405), XSPR_MASK, BOOKE, { RT } },
3681 { "mfivor6", XSPR(31,339,406), XSPR_MASK, BOOKE, { RT } },
3682 { "mfivor7", XSPR(31,339,407), XSPR_MASK, BOOKE, { RT } },
3683 { "mfivor8", XSPR(31,339,408), XSPR_MASK, BOOKE, { RT } },
3684 { "mfivor9", XSPR(31,339,409), XSPR_MASK, BOOKE, { RT } },
3685 { "mfivor10", XSPR(31,339,410), XSPR_MASK, BOOKE, { RT } },
3686 { "mfivor11", XSPR(31,339,411), XSPR_MASK, BOOKE, { RT } },
3687 { "mfivor12", XSPR(31,339,412), XSPR_MASK, BOOKE, { RT } },
3688 { "mfivor13", XSPR(31,339,413), XSPR_MASK, BOOKE, { RT } },
3689 { "mfivor14", XSPR(31,339,414), XSPR_MASK, BOOKE, { RT } },
3690 { "mfivor15", XSPR(31,339,415), XSPR_MASK, BOOKE, { RT } },
3691 { "mfspefscr", XSPR(31,339,512), XSPR_MASK, PPCSPE, { RT } },
3692 { "mfbbear", XSPR(31,339,513), XSPR_MASK, PPCBRLK, { RT } },
3693 { "mfbbtar", XSPR(31,339,514), XSPR_MASK, PPCBRLK, { RT } },
3694 { "mfivor32", XSPR(31,339,528), XSPR_MASK, PPCSPE, { RT } },
3695 { "mfivor33", XSPR(31,339,529), XSPR_MASK, PPCSPE, { RT } },
3696 { "mfivor34", XSPR(31,339,530), XSPR_MASK, PPCSPE, { RT } },
3697 { "mfivor35", XSPR(31,339,531), XSPR_MASK, PPCPMR, { RT } },
3698 { "mfibatu", XSPR(31,339,528), XSPRBAT_MASK, PPC, { RT, SPRBAT } },
3699 { "mfibatl", XSPR(31,339,529), XSPRBAT_MASK, PPC, { RT, SPRBAT } },
3700 { "mfdbatu", XSPR(31,339,536), XSPRBAT_MASK, PPC, { RT, SPRBAT } },
3701 { "mfdbatl", XSPR(31,339,537), XSPRBAT_MASK, PPC, { RT, SPRBAT } },
3702 { "mfic_cst", XSPR(31,339,560), XSPR_MASK, PPC860, { RT } },
3703 { "mfic_adr", XSPR(31,339,561), XSPR_MASK, PPC860, { RT } },
3704 { "mfic_dat", XSPR(31,339,562), XSPR_MASK, PPC860, { RT } },
3705 { "mfdc_cst", XSPR(31,339,568), XSPR_MASK, PPC860, { RT } },
3706 { "mfdc_adr", XSPR(31,339,569), XSPR_MASK, PPC860, { RT } },
3707 { "mfmcsrr0", XSPR(31,339,570), XSPR_MASK, PPCRFMCI, { RT } },
3708 { "mfdc_dat", XSPR(31,339,570), XSPR_MASK, PPC860, { RT } },
3709 { "mfmcsrr1", XSPR(31,339,571), XSPR_MASK, PPCRFMCI, { RT } },
3710 { "mfmcsr", XSPR(31,339,572), XSPR_MASK, PPCRFMCI, { RT } },
3711 { "mfmcar", XSPR(31,339,573), XSPR_MASK, PPCRFMCI, { RT } },
3712 { "mfdpdr", XSPR(31,339,630), XSPR_MASK, PPC860, { RT } },
3713 { "mfdpir", XSPR(31,339,631), XSPR_MASK, PPC860, { RT } },
3714 { "mfimmr", XSPR(31,339,638), XSPR_MASK, PPC860, { RT } },
3715 { "mfmi_ctr", XSPR(31,339,784), XSPR_MASK, PPC860, { RT } },
3716 { "mfmi_ap", XSPR(31,339,786), XSPR_MASK, PPC860, { RT } },
3717 { "mfmi_epn", XSPR(31,339,787), XSPR_MASK, PPC860, { RT } },
3718 { "mfmi_twc", XSPR(31,339,789), XSPR_MASK, PPC860, { RT } },
3719 { "mfmi_rpn", XSPR(31,339,790), XSPR_MASK, PPC860, { RT } },
3720 { "mfmd_ctr", XSPR(31,339,792), XSPR_MASK, PPC860, { RT } },
3721 { "mfm_casid", XSPR(31,339,793), XSPR_MASK, PPC860, { RT } },
3722 { "mfmd_ap", XSPR(31,339,794), XSPR_MASK, PPC860, { RT } },
3723 { "mfmd_epn", XSPR(31,339,795), XSPR_MASK, PPC860, { RT } },
3724 { "mfmd_twb", XSPR(31,339,796), XSPR_MASK, PPC860, { RT } },
3725 { "mfmd_twc", XSPR(31,339,797), XSPR_MASK, PPC860, { RT } },
3726 { "mfmd_rpn", XSPR(31,339,798), XSPR_MASK, PPC860, { RT } },
3727 { "mfm_tw", XSPR(31,339,799), XSPR_MASK, PPC860, { RT } },
3728 { "mfmi_dbcam", XSPR(31,339,816), XSPR_MASK, PPC860, { RT } },
3729 { "mfmi_dbram0",XSPR(31,339,817), XSPR_MASK, PPC860, { RT } },
3730 { "mfmi_dbram1",XSPR(31,339,818), XSPR_MASK, PPC860, { RT } },
3731 { "mfmd_dbcam", XSPR(31,339,824), XSPR_MASK, PPC860, { RT } },
3732 { "mfmd_dbram0",XSPR(31,339,825), XSPR_MASK, PPC860, { RT } },
3733 { "mfmd_dbram1",XSPR(31,339,826), XSPR_MASK, PPC860, { RT } },
3734 { "mfummcr0", XSPR(31,339,936), XSPR_MASK, PPC750, { RT } },
3735 { "mfupmc1", XSPR(31,339,937), XSPR_MASK, PPC750, { RT } },
3736 { "mfupmc2", XSPR(31,339,938), XSPR_MASK, PPC750, { RT } },
3737 { "mfusia", XSPR(31,339,939), XSPR_MASK, PPC750, { RT } },
3738 { "mfummcr1", XSPR(31,339,940), XSPR_MASK, PPC750, { RT } },
3739 { "mfupmc3", XSPR(31,339,941), XSPR_MASK, PPC750, { RT } },
3740 { "mfupmc4", XSPR(31,339,942), XSPR_MASK, PPC750, { RT } },
3741 { "mfzpr", XSPR(31,339,944), XSPR_MASK, PPC403, { RT } },
3742 { "mfccr0", XSPR(31,339,947), XSPR_MASK, PPC405, { RT } },
3743 { "mfmmcr0", XSPR(31,339,952), XSPR_MASK, PPC750, { RT } },
3744 { "mfpmc1", XSPR(31,339,953), XSPR_MASK, PPC750, { RT } },
3745 { "mfsgr", XSPR(31,339,953), XSPR_MASK, PPC403, { RT } },
3746 { "mfpmc2", XSPR(31,339,954), XSPR_MASK, PPC750, { RT } },
3747 { "mfdcwr", XSPR(31,339,954), XSPR_MASK, PPC403, { RT } },
3748 { "mfsia", XSPR(31,339,955), XSPR_MASK, PPC750, { RT } },
3749 { "mfsler", XSPR(31,339,955), XSPR_MASK, PPC405, { RT } },
3750 { "mfmmcr1", XSPR(31,339,956), XSPR_MASK, PPC750, { RT } },
3751 { "mfsu0r", XSPR(31,339,956), XSPR_MASK, PPC405, { RT } },
3752 { "mfpmc3", XSPR(31,339,957), XSPR_MASK, PPC750, { RT } },
3753 { "mfpmc4", XSPR(31,339,958), XSPR_MASK, PPC750, { RT } },
3754 { "mficdbdr", XSPR(31,339,979), XSPR_MASK, PPC403, { RT } },
3755 { "mfevpr", XSPR(31,339,982), XSPR_MASK, PPC403, { RT } },
3756 { "mfcdbcr", XSPR(31,339,983), XSPR_MASK, PPC403, { RT } },
3757 { "mfpit", XSPR(31,339,987), XSPR_MASK, PPC403, { RT } },
3758 { "mftbhi", XSPR(31,339,988), XSPR_MASK, PPC403, { RT } },
3759 { "mftblo", XSPR(31,339,989), XSPR_MASK, PPC403, { RT } },
3760 { "mfsrr2", XSPR(31,339,990), XSPR_MASK, PPC403, { RT } },
3761 { "mfsrr3", XSPR(31,339,991), XSPR_MASK, PPC403, { RT } },
3762 { "mfl2cr", XSPR(31,339,1017), XSPR_MASK, PPC750, { RT } },
3763 { "mfdccr", XSPR(31,339,1018), XSPR_MASK, PPC403, { RT } },
3764 { "mficcr", XSPR(31,339,1019), XSPR_MASK, PPC403, { RT } },
3765 { "mfictc", XSPR(31,339,1019), XSPR_MASK, PPC750, { RT } },
3766 { "mfpbl1", XSPR(31,339,1020), XSPR_MASK, PPC403, { RT } },
3767 { "mfthrm1", XSPR(31,339,1020), XSPR_MASK, PPC750, { RT } },
3768 { "mfpbu1", XSPR(31,339,1021), XSPR_MASK, PPC403, { RT } },
3769 { "mfthrm2", XSPR(31,339,1021), XSPR_MASK, PPC750, { RT } },
3770 { "mfpbl2", XSPR(31,339,1022), XSPR_MASK, PPC403, { RT } },
3771 { "mfthrm3", XSPR(31,339,1022), XSPR_MASK, PPC750, { RT } },
3772 { "mfpbu2", XSPR(31,339,1023), XSPR_MASK, PPC403, { RT } },
3773 { "mfspr", X(31,339), X_MASK, COM, { RT, SPR } },
3775 { "lwax", X(31,341), X_MASK, PPC64, { RT, RA0, RB } },
3777 { "dst", XDSS(31,342,0), XDSS_MASK, PPCVEC, { RA, RB, STRM } },
3778 { "dstt", XDSS(31,342,1), XDSS_MASK, PPCVEC, { RA, RB, STRM } },
3780 { "lhax", X(31,343), X_MASK, COM, { RT, RA0, RB } },
3782 { "lhaxe", X(31,351), X_MASK, BOOKE64, { RT, RA0, RB } },
3784 { "dstst", XDSS(31,374,0), XDSS_MASK, PPCVEC, { RA, RB, STRM } },
3785 { "dststt", XDSS(31,374,1), XDSS_MASK, PPCVEC, { RA, RB, STRM } },
3787 { "dccci", X(31,454), XRT_MASK, PPC403|PPC440, { RA, RB } },
3789 { "abs", XO(31,360,0,0), XORB_MASK, M601, { RT, RA } },
3790 { "abs.", XO(31,360,0,1), XORB_MASK, M601, { RT, RA } },
3791 { "abso", XO(31,360,1,0), XORB_MASK, M601, { RT, RA } },
3792 { "abso.", XO(31,360,1,1), XORB_MASK, M601, { RT, RA } },
3794 { "divs", XO(31,363,0,0), XO_MASK, M601, { RT, RA, RB } },
3795 { "divs.", XO(31,363,0,1), XO_MASK, M601, { RT, RA, RB } },
3796 { "divso", XO(31,363,1,0), XO_MASK, M601, { RT, RA, RB } },
3797 { "divso.", XO(31,363,1,1), XO_MASK, M601, { RT, RA, RB } },
3799 { "tlbia", X(31,370), 0xffffffff, PPC, { 0 } },
3801 { "lwaux", X(31,373), X_MASK, PPC64, { RT, RAL, RB } },
3803 { "lhaux", X(31,375), X_MASK, COM, { RT, RAL, RB } },
3805 { "lhauxe", X(31,383), X_MASK, BOOKE64, { RT, RAL, RB } },
3807 { "mtdcrx", X(31,387), X_MASK, BOOKE, { RA, RS } },
3809 { "dcblc", X(31,390), X_MASK, PPCCHLK, { CT, RA, RB }},
3811 { "subfe64", XO(31,392,0,0), XO_MASK, BOOKE64, { RT, RA, RB } },
3812 { "subfe64o",XO(31,392,1,0), XO_MASK, BOOKE64, { RT, RA, RB } },
3814 { "adde64", XO(31,394,0,0), XO_MASK, BOOKE64, { RT, RA, RB } },
3815 { "adde64o", XO(31,394,1,0), XO_MASK, BOOKE64, { RT, RA, RB } },
3817 { "dcblce", X(31,398), X_MASK, PPCCHLK64, { CT, RA, RB }},
3819 { "slbmte", X(31,402), XRA_MASK, PPC64, { RS, RB } },
3821 { "sthx", X(31,407), X_MASK, COM, { RS, RA0, RB } },
3823 { "lfqx", X(31,791), X_MASK, POWER2, { FRT, RA, RB } },
3825 { "lfqux", X(31,823), X_MASK, POWER2, { FRT, RA, RB } },
3827 { "stfqx", X(31,919), X_MASK, POWER2, { FRS, RA, RB } },
3829 { "stfqux", X(31,951), X_MASK, POWER2, { FRS, RA, RB } },
3831 { "orc", XRC(31,412,0), X_MASK, COM, { RA, RS, RB } },
3832 { "orc.", XRC(31,412,1), X_MASK, COM, { RA, RS, RB } },
3834 { "sradi", XS(31,413,0), XS_MASK, PPC64, { RA, RS, SH6 } },
3835 { "sradi.", XS(31,413,1), XS_MASK, PPC64, { RA, RS, SH6 } },
3837 { "sthxe", X(31,415), X_MASK, BOOKE64, { RS, RA0, RB } },
3839 { "slbie", X(31,434), XRTRA_MASK, PPC64, { RB } },
3841 { "ecowx", X(31,438), X_MASK, PPC, { RT, RA, RB } },
3843 { "sthux", X(31,439), X_MASK, COM, { RS, RAS, RB } },
3845 { "sthuxe", X(31,447), X_MASK, BOOKE64, { RS, RAS, RB } },
3847 { "mr", XRC(31,444,0), X_MASK, COM, { RA, RS, RBS } },
3848 { "or", XRC(31,444,0), X_MASK, COM, { RA, RS, RB } },
3849 { "mr.", XRC(31,444,1), X_MASK, COM, { RA, RS, RBS } },
3850 { "or.", XRC(31,444,1), X_MASK, COM, { RA, RS, RB } },
3852 { "mtexisr", XSPR(31,451,64), XSPR_MASK, PPC403, { RS } },
3853 { "mtexier", XSPR(31,451,66), XSPR_MASK, PPC403, { RS } },
3854 { "mtbr0", XSPR(31,451,128), XSPR_MASK, PPC403, { RS } },
3855 { "mtbr1", XSPR(31,451,129), XSPR_MASK, PPC403, { RS } },
3856 { "mtbr2", XSPR(31,451,130), XSPR_MASK, PPC403, { RS } },
3857 { "mtbr3", XSPR(31,451,131), XSPR_MASK, PPC403, { RS } },
3858 { "mtbr4", XSPR(31,451,132), XSPR_MASK, PPC403, { RS } },
3859 { "mtbr5", XSPR(31,451,133), XSPR_MASK, PPC403, { RS } },
3860 { "mtbr6", XSPR(31,451,134), XSPR_MASK, PPC403, { RS } },
3861 { "mtbr7", XSPR(31,451,135), XSPR_MASK, PPC403, { RS } },
3862 { "mtbear", XSPR(31,451,144), XSPR_MASK, PPC403, { RS } },
3863 { "mtbesr", XSPR(31,451,145), XSPR_MASK, PPC403, { RS } },
3864 { "mtiocr", XSPR(31,451,160), XSPR_MASK, PPC403, { RS } },
3865 { "mtdmacr0", XSPR(31,451,192), XSPR_MASK, PPC403, { RS } },
3866 { "mtdmact0", XSPR(31,451,193), XSPR_MASK, PPC403, { RS } },
3867 { "mtdmada0", XSPR(31,451,194), XSPR_MASK, PPC403, { RS } },
3868 { "mtdmasa0", XSPR(31,451,195), XSPR_MASK, PPC403, { RS } },
3869 { "mtdmacc0", XSPR(31,451,196), XSPR_MASK, PPC403, { RS } },
3870 { "mtdmacr1", XSPR(31,451,200), XSPR_MASK, PPC403, { RS } },
3871 { "mtdmact1", XSPR(31,451,201), XSPR_MASK, PPC403, { RS } },
3872 { "mtdmada1", XSPR(31,451,202), XSPR_MASK, PPC403, { RS } },
3873 { "mtdmasa1", XSPR(31,451,203), XSPR_MASK, PPC403, { RS } },
3874 { "mtdmacc1", XSPR(31,451,204), XSPR_MASK, PPC403, { RS } },
3875 { "mtdmacr2", XSPR(31,451,208), XSPR_MASK, PPC403, { RS } },
3876 { "mtdmact2", XSPR(31,451,209), XSPR_MASK, PPC403, { RS } },
3877 { "mtdmada2", XSPR(31,451,210), XSPR_MASK, PPC403, { RS } },
3878 { "mtdmasa2", XSPR(31,451,211), XSPR_MASK, PPC403, { RS } },
3879 { "mtdmacc2", XSPR(31,451,212), XSPR_MASK, PPC403, { RS } },
3880 { "mtdmacr3", XSPR(31,451,216), XSPR_MASK, PPC403, { RS } },
3881 { "mtdmact3", XSPR(31,451,217), XSPR_MASK, PPC403, { RS } },
3882 { "mtdmada3", XSPR(31,451,218), XSPR_MASK, PPC403, { RS } },
3883 { "mtdmasa3", XSPR(31,451,219), XSPR_MASK, PPC403, { RS } },
3884 { "mtdmacc3", XSPR(31,451,220), XSPR_MASK, PPC403, { RS } },
3885 { "mtdmasr", XSPR(31,451,224), XSPR_MASK, PPC403, { RS } },
3886 { "mtdcr", X(31,451), X_MASK, PPC403 | BOOKE, { SPR, RS } },
3888 { "subfze64",XO(31,456,0,0), XORB_MASK, BOOKE64, { RT, RA } },
3889 { "subfze64o",XO(31,456,1,0), XORB_MASK, BOOKE64, { RT, RA } },
3891 { "divdu", XO(31,457,0,0), XO_MASK, PPC64, { RT, RA, RB } },
3892 { "divdu.", XO(31,457,0,1), XO_MASK, PPC64, { RT, RA, RB } },
3893 { "divduo", XO(31,457,1,0), XO_MASK, PPC64, { RT, RA, RB } },
3894 { "divduo.", XO(31,457,1,1), XO_MASK, PPC64, { RT, RA, RB } },
3896 { "addze64", XO(31,458,0,0), XORB_MASK, BOOKE64, { RT, RA } },
3897 { "addze64o",XO(31,458,1,0), XORB_MASK, BOOKE64, { RT, RA } },
3899 { "divwu", XO(31,459,0,0), XO_MASK, PPC, { RT, RA, RB } },
3900 { "divwu.", XO(31,459,0,1), XO_MASK, PPC, { RT, RA, RB } },
3901 { "divwuo", XO(31,459,1,0), XO_MASK, PPC, { RT, RA, RB } },
3902 { "divwuo.", XO(31,459,1,1), XO_MASK, PPC, { RT, RA, RB } },
3904 { "mtmq", XSPR(31,467,0), XSPR_MASK, M601, { RS } },
3905 { "mtxer", XSPR(31,467,1), XSPR_MASK, COM, { RS } },
3906 { "mtlr", XSPR(31,467,8), XSPR_MASK, COM, { RS } },
3907 { "mtctr", XSPR(31,467,9), XSPR_MASK, COM, { RS } },
3908 { "mttid", XSPR(31,467,17), XSPR_MASK, POWER, { RS } },
3909 { "mtdsisr", XSPR(31,467,18), XSPR_MASK, COM, { RS } },
3910 { "mtdar", XSPR(31,467,19), XSPR_MASK, COM, { RS } },
3911 { "mtrtcu", XSPR(31,467,20), XSPR_MASK, COM, { RS } },
3912 { "mtrtcl", XSPR(31,467,21), XSPR_MASK, COM, { RS } },
3913 { "mtdec", XSPR(31,467,22), XSPR_MASK, COM, { RS } },
3914 { "mtsdr0", XSPR(31,467,24), XSPR_MASK, POWER, { RS } },
3915 { "mtsdr1", XSPR(31,467,25), XSPR_MASK, COM, { RS } },
3916 { "mtsrr0", XSPR(31,467,26), XSPR_MASK, COM, { RS } },
3917 { "mtsrr1", XSPR(31,467,27), XSPR_MASK, COM, { RS } },
3918 { "mtpid", XSPR(31,467,48), XSPR_MASK, BOOKE, { RS } },
3919 { "mtpid", XSPR(31,467,945), XSPR_MASK, PPC403, { RS } },
3920 { "mtdecar", XSPR(31,467,54), XSPR_MASK, BOOKE, { RS } },
3921 { "mtcsrr0", XSPR(31,467,58), XSPR_MASK, BOOKE, { RS } },
3922 { "mtcsrr1", XSPR(31,467,59), XSPR_MASK, BOOKE, { RS } },
3923 { "mtdear", XSPR(31,467,61), XSPR_MASK, BOOKE, { RS } },
3924 { "mtdear", XSPR(31,467,981), XSPR_MASK, PPC403, { RS } },
3925 { "mtesr", XSPR(31,467,62), XSPR_MASK, BOOKE, { RS } },
3926 { "mtesr", XSPR(31,467,980), XSPR_MASK, PPC403, { RS } },
3927 { "mtivpr", XSPR(31,467,63), XSPR_MASK, BOOKE, { RS } },
3928 { "mtcmpa", XSPR(31,467,144), XSPR_MASK, PPC860, { RS } },
3929 { "mtcmpb", XSPR(31,467,145), XSPR_MASK, PPC860, { RS } },
3930 { "mtcmpc", XSPR(31,467,146), XSPR_MASK, PPC860, { RS } },
3931 { "mtcmpd", XSPR(31,467,147), XSPR_MASK, PPC860, { RS } },
3932 { "mticr", XSPR(31,467,148), XSPR_MASK, PPC860, { RS } },
3933 { "mtder", XSPR(31,467,149), XSPR_MASK, PPC860, { RS } },
3934 { "mtcounta", XSPR(31,467,150), XSPR_MASK, PPC860, { RS } },
3935 { "mtcountb", XSPR(31,467,151), XSPR_MASK, PPC860, { RS } },
3936 { "mtcmpe", XSPR(31,467,152), XSPR_MASK, PPC860, { RS } },
3937 { "mtcmpf", XSPR(31,467,153), XSPR_MASK, PPC860, { RS } },
3938 { "mtcmpg", XSPR(31,467,154), XSPR_MASK, PPC860, { RS } },
3939 { "mtcmph", XSPR(31,467,155), XSPR_MASK, PPC860, { RS } },
3940 { "mtlctrl1", XSPR(31,467,156), XSPR_MASK, PPC860, { RS } },
3941 { "mtlctrl2", XSPR(31,467,157), XSPR_MASK, PPC860, { RS } },
3942 { "mtictrl", XSPR(31,467,158), XSPR_MASK, PPC860, { RS } },
3943 { "mtbar", XSPR(31,467,159), XSPR_MASK, PPC860, { RS } },
3944 { "mtvrsave", XSPR(31,467,256), XSPR_MASK, PPCVEC, { RS } },
3945 { "mtusprg0", XSPR(31,467,256), XSPR_MASK, BOOKE, { RS } },
3946 { "mtsprg", XSPR(31,467,272), XSPRG_MASK,PPC, { SPRG, RS } },
3947 { "mtsprg0", XSPR(31,467,272), XSPR_MASK, PPC, { RS } },
3948 { "mtsprg1", XSPR(31,467,273), XSPR_MASK, PPC, { RS } },
3949 { "mtsprg2", XSPR(31,467,274), XSPR_MASK, PPC, { RS } },
3950 { "mtsprg3", XSPR(31,467,275), XSPR_MASK, PPC, { RS } },
3951 { "mtsprg4", XSPR(31,467,276), XSPR_MASK, PPC405 | BOOKE, { RS } },
3952 { "mtsprg5", XSPR(31,467,277), XSPR_MASK, PPC405 | BOOKE, { RS } },
3953 { "mtsprg6", XSPR(31,467,278), XSPR_MASK, PPC405 | BOOKE, { RS } },
3954 { "mtsprg7", XSPR(31,467,279), XSPR_MASK, PPC405 | BOOKE, { RS } },
3955 { "mtasr", XSPR(31,467,280), XSPR_MASK, PPC64, { RS } },
3956 { "mtear", XSPR(31,467,282), XSPR_MASK, PPC, { RS } },
3957 { "mttbl", XSPR(31,467,284), XSPR_MASK, PPC, { RS } },
3958 { "mttbu", XSPR(31,467,285), XSPR_MASK, PPC, { RS } },
3959 { "mtdbsr", XSPR(31,467,304), XSPR_MASK, BOOKE, { RS } },
3960 { "mtdbsr", XSPR(31,467,1008), XSPR_MASK, PPC403, { RS } },
3961 { "mtdbcr0", XSPR(31,467,308), XSPR_MASK, BOOKE, { RS } },
3962 { "mtdbcr0", XSPR(31,467,1010), XSPR_MASK, PPC405, { RS } },
3963 { "mtdbcr1", XSPR(31,467,309), XSPR_MASK, BOOKE, { RS } },
3964 { "mtdbcr1", XSPR(31,467,957), XSPR_MASK, PPC405, { RS } },
3965 { "mtdbcr2", XSPR(31,467,310), XSPR_MASK, BOOKE, { RS } },
3966 { "mtiac1", XSPR(31,467,312), XSPR_MASK, BOOKE, { RS } },
3967 { "mtiac1", XSPR(31,467,1012), XSPR_MASK, PPC403, { RS } },
3968 { "mtiac2", XSPR(31,467,313), XSPR_MASK, BOOKE, { RS } },
3969 { "mtiac2", XSPR(31,467,1013), XSPR_MASK, PPC403, { RS } },
3970 { "mtiac3", XSPR(31,467,314), XSPR_MASK, BOOKE, { RS } },
3971 { "mtiac3", XSPR(31,467,948), XSPR_MASK, PPC405, { RS } },
3972 { "mtiac4", XSPR(31,467,315), XSPR_MASK, BOOKE, { RS } },
3973 { "mtiac4", XSPR(31,467,949), XSPR_MASK, PPC405, { RS } },
3974 { "mtdac1", XSPR(31,467,316), XSPR_MASK, BOOKE, { RS } },
3975 { "mtdac1", XSPR(31,467,1014), XSPR_MASK, PPC403, { RS } },
3976 { "mtdac2", XSPR(31,467,317), XSPR_MASK, BOOKE, { RS } },
3977 { "mtdac2", XSPR(31,467,1015), XSPR_MASK, PPC403, { RS } },
3978 { "mtdvc1", XSPR(31,467,318), XSPR_MASK, BOOKE, { RS } },
3979 { "mtdvc1", XSPR(31,467,950), XSPR_MASK, PPC405, { RS } },
3980 { "mtdvc2", XSPR(31,467,319), XSPR_MASK, BOOKE, { RS } },
3981 { "mtdvc2", XSPR(31,467,951), XSPR_MASK, PPC405, { RS } },
3982 { "mttsr", XSPR(31,467,336), XSPR_MASK, BOOKE, { RS } },
3983 { "mttsr", XSPR(31,467,984), XSPR_MASK, PPC403, { RS } },
3984 { "mttcr", XSPR(31,467,340), XSPR_MASK, BOOKE, { RS } },
3985 { "mttcr", XSPR(31,467,986), XSPR_MASK, PPC403, { RS } },
3986 { "mtivor0", XSPR(31,467,400), XSPR_MASK, BOOKE, { RS } },
3987 { "mtivor1", XSPR(31,467,401), XSPR_MASK, BOOKE, { RS } },
3988 { "mtivor2", XSPR(31,467,402), XSPR_MASK, BOOKE, { RS } },
3989 { "mtivor3", XSPR(31,467,403), XSPR_MASK, BOOKE, { RS } },
3990 { "mtivor4", XSPR(31,467,404), XSPR_MASK, BOOKE, { RS } },
3991 { "mtivor5", XSPR(31,467,405), XSPR_MASK, BOOKE, { RS } },
3992 { "mtivor6", XSPR(31,467,406), XSPR_MASK, BOOKE, { RS } },
3993 { "mtivor7", XSPR(31,467,407), XSPR_MASK, BOOKE, { RS } },
3994 { "mtivor8", XSPR(31,467,408), XSPR_MASK, BOOKE, { RS } },
3995 { "mtivor9", XSPR(31,467,409), XSPR_MASK, BOOKE, { RS } },
3996 { "mtivor10", XSPR(31,467,410), XSPR_MASK, BOOKE, { RS } },
3997 { "mtivor11", XSPR(31,467,411), XSPR_MASK, BOOKE, { RS } },
3998 { "mtivor12", XSPR(31,467,412), XSPR_MASK, BOOKE, { RS } },
3999 { "mtivor13", XSPR(31,467,413), XSPR_MASK, BOOKE, { RS } },
4000 { "mtivor14", XSPR(31,467,414), XSPR_MASK, BOOKE, { RS } },
4001 { "mtivor15", XSPR(31,467,415), XSPR_MASK, BOOKE, { RS } },
4002 { "mtspefscr", XSPR(31,467,512), XSPR_MASK, PPCSPE, { RS } },
4003 { "mtbbear", XSPR(31,467,513), XSPR_MASK, PPCBRLK, { RS } },
4004 { "mtbbtar", XSPR(31,467,514), XSPR_MASK, PPCBRLK, { RS } },
4005 { "mtivor32", XSPR(31,467,528), XSPR_MASK, PPCSPE, { RS } },
4006 { "mtivor33", XSPR(31,467,529), XSPR_MASK, PPCSPE, { RS } },
4007 { "mtivor34", XSPR(31,467,530), XSPR_MASK, PPCSPE, { RS } },
4008 { "mtivor35", XSPR(31,467,531), XSPR_MASK, PPCPMR, { RS } },
4009 { "mtibatu", XSPR(31,467,528), XSPRBAT_MASK, PPC, { SPRBAT, RS } },
4010 { "mtibatl", XSPR(31,467,529), XSPRBAT_MASK, PPC, { SPRBAT, RS } },
4011 { "mtdbatu", XSPR(31,467,536), XSPRBAT_MASK, PPC, { SPRBAT, RS } },
4012 { "mtdbatl", XSPR(31,467,537), XSPRBAT_MASK, PPC, { SPRBAT, RS } },
4013 { "mtmcsrr0", XSPR(31,467,570), XSPR_MASK, PPCRFMCI, { RS } },
4014 { "mtmcsrr1", XSPR(31,467,571), XSPR_MASK, PPCRFMCI, { RS } },
4015 { "mtmcsr", XSPR(31,467,572), XSPR_MASK, PPCRFMCI, { RS } },
4016 { "mtummcr0", XSPR(31,467,936), XSPR_MASK, PPC750, { RS } },
4017 { "mtupmc1", XSPR(31,467,937), XSPR_MASK, PPC750, { RS } },
4018 { "mtupmc2", XSPR(31,467,938), XSPR_MASK, PPC750, { RS } },
4019 { "mtusia", XSPR(31,467,939), XSPR_MASK, PPC750, { RS } },
4020 { "mtummcr1", XSPR(31,467,940), XSPR_MASK, PPC750, { RS } },
4021 { "mtupmc3", XSPR(31,467,941), XSPR_MASK, PPC750, { RS } },
4022 { "mtupmc4", XSPR(31,467,942), XSPR_MASK, PPC750, { RS } },
4023 { "mtzpr", XSPR(31,467,944), XSPR_MASK, PPC403, { RS } },
4024 { "mtccr0", XSPR(31,467,947), XSPR_MASK, PPC405, { RS } },
4025 { "mtmmcr0", XSPR(31,467,952), XSPR_MASK, PPC750, { RS } },
4026 { "mtsgr", XSPR(31,467,953), XSPR_MASK, PPC403, { RS } },
4027 { "mtpmc1", XSPR(31,467,953), XSPR_MASK, PPC750, { RS } },
4028 { "mtdcwr", XSPR(31,467,954), XSPR_MASK, PPC403, { RS } },
4029 { "mtpmc2", XSPR(31,467,954), XSPR_MASK, PPC750, { RS } },
4030 { "mtsler", XSPR(31,467,955), XSPR_MASK, PPC405, { RS } },
4031 { "mtsia", XSPR(31,467,955), XSPR_MASK, PPC750, { RS } },
4032 { "mtsu0r", XSPR(31,467,956), XSPR_MASK, PPC405, { RS } },
4033 { "mtmmcr1", XSPR(31,467,956), XSPR_MASK, PPC750, { RS } },
4034 { "mtpmc3", XSPR(31,467,957), XSPR_MASK, PPC750, { RS } },
4035 { "mtpmc4", XSPR(31,467,958), XSPR_MASK, PPC750, { RS } },
4036 { "mticdbdr", XSPR(31,467,979), XSPR_MASK, PPC403, { RS } },
4037 { "mtevpr", XSPR(31,467,982), XSPR_MASK, PPC403, { RS } },
4038 { "mtcdbcr", XSPR(31,467,983), XSPR_MASK, PPC403, { RS } },
4039 { "mtpit", XSPR(31,467,987), XSPR_MASK, PPC403, { RS } },
4040 { "mttbhi", XSPR(31,467,988), XSPR_MASK, PPC403, { RS } },
4041 { "mttblo", XSPR(31,467,989), XSPR_MASK, PPC403, { RS } },
4042 { "mtsrr2", XSPR(31,467,990), XSPR_MASK, PPC403, { RS } },
4043 { "mtsrr3", XSPR(31,467,991), XSPR_MASK, PPC403, { RS } },
4044 { "mtl2cr", XSPR(31,467,1017), XSPR_MASK, PPC750, { RS } },
4045 { "mtdccr", XSPR(31,467,1018), XSPR_MASK, PPC403, { RS } },
4046 { "mticcr", XSPR(31,467,1019), XSPR_MASK, PPC403, { RS } },
4047 { "mtictc", XSPR(31,467,1019), XSPR_MASK, PPC750, { RS } },
4048 { "mtpbl1", XSPR(31,467,1020), XSPR_MASK, PPC403, { RS } },
4049 { "mtthrm1", XSPR(31,467,1020), XSPR_MASK, PPC750, { RS } },
4050 { "mtpbu1", XSPR(31,467,1021), XSPR_MASK, PPC403, { RS } },
4051 { "mtthrm2", XSPR(31,467,1021), XSPR_MASK, PPC750, { RS } },
4052 { "mtpbl2", XSPR(31,467,1022), XSPR_MASK, PPC403, { RS } },
4053 { "mtthrm3", XSPR(31,467,1022), XSPR_MASK, PPC750, { RS } },
4054 { "mtpbu2", XSPR(31,467,1023), XSPR_MASK, PPC403, { RS } },
4055 { "mtspr", X(31,467), X_MASK, COM, { SPR, RS } },
4057 { "dcbi", X(31,470), XRT_MASK, PPC, { RA, RB } },
4059 { "nand", XRC(31,476,0), X_MASK, COM, { RA, RS, RB } },
4060 { "nand.", XRC(31,476,1), X_MASK, COM, { RA, RS, RB } },
4062 { "dcbie", X(31,478), XRT_MASK, BOOKE64, { RA, RB } },
4064 { "dcread", X(31,486), X_MASK, PPC403|PPC440, { RT, RA, RB }},
4066 { "mtpmr", X(31,462), X_MASK, PPCPMR, { PMR, RS }},
4068 { "icbtls", X(31,486), X_MASK, PPCCHLK, { CT, RA, RB }},
4070 { "nabs", XO(31,488,0,0), XORB_MASK, M601, { RT, RA } },
4071 { "subfme64",XO(31,488,0,0), XORB_MASK, BOOKE64, { RT, RA } },
4072 { "nabs.", XO(31,488,0,1), XORB_MASK, M601, { RT, RA } },
4073 { "nabso", XO(31,488,1,0), XORB_MASK, M601, { RT, RA } },
4074 { "subfme64o",XO(31,488,1,0), XORB_MASK, BOOKE64, { RT, RA } },
4075 { "nabso.", XO(31,488,1,1), XORB_MASK, M601, { RT, RA } },
4077 { "divd", XO(31,489,0,0), XO_MASK, PPC64, { RT, RA, RB } },
4078 { "divd.", XO(31,489,0,1), XO_MASK, PPC64, { RT, RA, RB } },
4079 { "divdo", XO(31,489,1,0), XO_MASK, PPC64, { RT, RA, RB } },
4080 { "divdo.", XO(31,489,1,1), XO_MASK, PPC64, { RT, RA, RB } },
4082 { "addme64", XO(31,490,0,0), XORB_MASK, BOOKE64, { RT, RA } },
4083 { "addme64o",XO(31,490,1,0), XORB_MASK, BOOKE64, { RT, RA } },
4085 { "divw", XO(31,491,0,0), XO_MASK, PPC, { RT, RA, RB } },
4086 { "divw.", XO(31,491,0,1), XO_MASK, PPC, { RT, RA, RB } },
4087 { "divwo", XO(31,491,1,0), XO_MASK, PPC, { RT, RA, RB } },
4088 { "divwo.", XO(31,491,1,1), XO_MASK, PPC, { RT, RA, RB } },
4090 { "icbtlse", X(31,494), X_MASK, PPCCHLK64, { CT, RA, RB }},
4092 { "slbia", X(31,498), 0xffffffff, PPC64, { 0 } },
4094 { "cli", X(31,502), XRB_MASK, POWER, { RT, RA } },
4096 { "stdcxe.", XRC(31,511,1), X_MASK, BOOKE64, { RS, RA, RB } },
4098 { "mcrxr", X(31,512), XRARB_MASK|(3<<21), COM, { BF } },
4100 { "bblels", X(31,518), X_MASK, PPCBRLK, { 0 }},
4101 { "mcrxr64", X(31,544), XRARB_MASK|(3<<21), BOOKE64, { BF } },
4103 { "clcs", X(31,531), XRB_MASK, M601, { RT, RA } },
4105 { "lswx", X(31,533), X_MASK, PPCCOM, { RT, RA0, RB } },
4106 { "lsx", X(31,533), X_MASK, PWRCOM, { RT, RA, RB } },
4108 { "lwbrx", X(31,534), X_MASK, PPCCOM, { RT, RA0, RB } },
4109 { "lbrx", X(31,534), X_MASK, PWRCOM, { RT, RA, RB } },
4111 { "lfsx", X(31,535), X_MASK, COM, { FRT, RA0, RB } },
4113 { "srw", XRC(31,536,0), X_MASK, PPCCOM, { RA, RS, RB } },
4114 { "sr", XRC(31,536,0), X_MASK, PWRCOM, { RA, RS, RB } },
4115 { "srw.", XRC(31,536,1), X_MASK, PPCCOM, { RA, RS, RB } },
4116 { "sr.", XRC(31,536,1), X_MASK, PWRCOM, { RA, RS, RB } },
4118 { "rrib", XRC(31,537,0), X_MASK, M601, { RA, RS, RB } },
4119 { "rrib.", XRC(31,537,1), X_MASK, M601, { RA, RS, RB } },
4121 { "srd", XRC(31,539,0), X_MASK, PPC64, { RA, RS, RB } },
4122 { "srd.", XRC(31,539,1), X_MASK, PPC64, { RA, RS, RB } },
4124 { "maskir", XRC(31,541,0), X_MASK, M601, { RA, RS, RB } },
4125 { "maskir.", XRC(31,541,1), X_MASK, M601, { RA, RS, RB } },
4127 { "lwbrxe", X(31,542), X_MASK, BOOKE64, { RT, RA0, RB } },
4129 { "lfsxe", X(31,543), X_MASK, BOOKE64, { FRT, RA0, RB } },
4131 { "bbelr", X(31,550), X_MASK, PPCBRLK, { 0 }},
4133 { "tlbsync", X(31,566), 0xffffffff, PPC, { 0 } },
4135 { "lfsux", X(31,567), X_MASK, COM, { FRT, RAS, RB } },
4137 { "lfsuxe", X(31,575), X_MASK, BOOKE64, { FRT, RAS, RB } },
4139 { "mfsr", X(31,595), XRB_MASK|(1<<20), COM32, { RT, SR } },
4141 { "lswi", X(31,597), X_MASK, PPCCOM, { RT, RA0, NB } },
4142 { "lsi", X(31,597), X_MASK, PWRCOM, { RT, RA0, NB } },
4144 { "lwsync", XSYNC(31,598,1), 0xffffffff, PPC, { 0 } },
4145 { "ptesync", XSYNC(31,598,2), 0xffffffff, PPC64, { 0 } },
4146 { "msync", X(31,598), 0xffffffff, BOOKE, { 0 } },
4147 { "sync", X(31,598), XSYNC_MASK, PPCCOM, { LS } },
4148 { "dcs", X(31,598), 0xffffffff, PWRCOM, { 0 } },
4150 { "lfdx", X(31,599), X_MASK, COM, { FRT, RA0, RB } },
4152 { "lfdxe", X(31,607), X_MASK, BOOKE64, { FRT, RA0, RB } },
4154 { "mfsri", X(31,627), X_MASK, PWRCOM, { RT, RA, RB } },
4156 { "dclst", X(31,630), XRB_MASK, PWRCOM, { RS, RA } },
4158 { "lfdux", X(31,631), X_MASK, COM, { FRT, RAS, RB } },
4160 { "lfduxe", X(31,639), X_MASK, BOOKE64, { FRT, RAS, RB } },
4162 { "mfsrin", X(31,659), XRA_MASK, PPC32, { RT, RB } },
4164 { "stswx", X(31,661), X_MASK, PPCCOM, { RS, RA0, RB } },
4165 { "stsx", X(31,661), X_MASK, PWRCOM, { RS, RA0, RB } },
4167 { "stwbrx", X(31,662), X_MASK, PPCCOM, { RS, RA0, RB } },
4168 { "stbrx", X(31,662), X_MASK, PWRCOM, { RS, RA0, RB } },
4170 { "stfsx", X(31,663), X_MASK, COM, { FRS, RA0, RB } },
4172 { "srq", XRC(31,664,0), X_MASK, M601, { RA, RS, RB } },
4173 { "srq.", XRC(31,664,1), X_MASK, M601, { RA, RS, RB } },
4175 { "sre", XRC(31,665,0), X_MASK, M601, { RA, RS, RB } },
4176 { "sre.", XRC(31,665,1), X_MASK, M601, { RA, RS, RB } },
4178 { "stwbrxe", X(31,670), X_MASK, BOOKE64, { RS, RA0, RB } },
4180 { "stfsxe", X(31,671), X_MASK, BOOKE64, { FRS, RA0, RB } },
4182 { "stfsux", X(31,695), X_MASK, COM, { FRS, RAS, RB } },
4184 { "sriq", XRC(31,696,0), X_MASK, M601, { RA, RS, SH } },
4185 { "sriq.", XRC(31,696,1), X_MASK, M601, { RA, RS, SH } },
4187 { "stfsuxe", X(31,703), X_MASK, BOOKE64, { FRS, RAS, RB } },
4189 { "stswi", X(31,725), X_MASK, PPCCOM, { RS, RA0, NB } },
4190 { "stsi", X(31,725), X_MASK, PWRCOM, { RS, RA0, NB } },
4192 { "stfdx", X(31,727), X_MASK, COM, { FRS, RA0, RB } },
4194 { "srlq", XRC(31,728,0), X_MASK, M601, { RA, RS, RB } },
4195 { "srlq.", XRC(31,728,1), X_MASK, M601, { RA, RS, RB } },
4197 { "sreq", XRC(31,729,0), X_MASK, M601, { RA, RS, RB } },
4198 { "sreq.", XRC(31,729,1), X_MASK, M601, { RA, RS, RB } },
4200 { "stfdxe", X(31,735), X_MASK, BOOKE64, { FRS, RA0, RB } },
4202 { "dcba", X(31,758), XRT_MASK, PPC405 | BOOKE, { RA, RB } },
4204 { "stfdux", X(31,759), X_MASK, COM, { FRS, RAS, RB } },
4206 { "srliq", XRC(31,760,0), X_MASK, M601, { RA, RS, SH } },
4207 { "srliq.", XRC(31,760,1), X_MASK, M601, { RA, RS, SH } },
4209 { "dcbae", X(31,766), XRT_MASK, BOOKE64, { RA, RB } },
4211 { "stfduxe", X(31,767), X_MASK, BOOKE64, { FRS, RAS, RB } },
4213 { "tlbivax", X(31,786), XRT_MASK, BOOKE, { RA, RB } },
4214 { "tlbivaxe",X(31,787), XRT_MASK, BOOKE64, { RA, RB } },
4216 { "lhbrx", X(31,790), X_MASK, COM, { RT, RA0, RB } },
4218 { "sraw", XRC(31,792,0), X_MASK, PPCCOM, { RA, RS, RB } },
4219 { "sra", XRC(31,792,0), X_MASK, PWRCOM, { RA, RS, RB } },
4220 { "sraw.", XRC(31,792,1), X_MASK, PPCCOM, { RA, RS, RB } },
4221 { "sra.", XRC(31,792,1), X_MASK, PWRCOM, { RA, RS, RB } },
4223 { "srad", XRC(31,794,0), X_MASK, PPC64, { RA, RS, RB } },
4224 { "srad.", XRC(31,794,1), X_MASK, PPC64, { RA, RS, RB } },
4226 { "lhbrxe", X(31,798), X_MASK, BOOKE64, { RT, RA0, RB } },
4228 { "ldxe", X(31,799), X_MASK, BOOKE64, { RT, RA0, RB } },
4229 { "lduxe", X(31,831), X_MASK, BOOKE64, { RT, RA0, RB } },
4231 { "rac", X(31,818), X_MASK, PWRCOM, { RT, RA, RB } },
4233 { "dss", XDSS(31,822,0), XDSS_MASK, PPCVEC, { STRM } },
4234 { "dssall", XDSS(31,822,1), XDSS_MASK, PPCVEC, { 0 } },
4236 { "srawi", XRC(31,824,0), X_MASK, PPCCOM, { RA, RS, SH } },
4237 { "srai", XRC(31,824,0), X_MASK, PWRCOM, { RA, RS, SH } },
4238 { "srawi.", XRC(31,824,1), X_MASK, PPCCOM, { RA, RS, SH } },
4239 { "srai.", XRC(31,824,1), X_MASK, PWRCOM, { RA, RS, SH } },
4241 { "slbmfev", X(31,851), XRA_MASK, PPC64, { RT, RB } },
4243 { "mbar", X(31,854), X_MASK, BOOKE, { MO } },
4244 { "eieio", X(31,854), 0xffffffff, PPC, { 0 } },
4246 { "tlbsx", XRC(31,914,0), X_MASK, BOOKE, { RA, RB } },
4247 { "tlbsx", XRC(31,914,0), X_MASK, PPC403, { RT, RA, RB } },
4248 { "tlbsx.", XRC(31,914,1), X_MASK, BOOKE, { RA, RB } },
4249 { "tlbsx.", XRC(31,914,1), X_MASK, PPC403, { RT, RA, RB } },
4250 { "tlbsxe", XRC(31,915,0), X_MASK, BOOKE64, { RA, RB } },
4251 { "tlbsxe.", XRC(31,915,1), X_MASK, BOOKE64, { RA, RB } },
4253 { "slbmfee", X(31,915), XRA_MASK, PPC64, { RT, RB } },
4255 { "sthbrx", X(31,918), X_MASK, COM, { RS, RA0, RB } },
4257 { "sraq", XRC(31,920,0), X_MASK, M601, { RA, RS, RB } },
4258 { "sraq.", XRC(31,920,1), X_MASK, M601, { RA, RS, RB } },
4260 { "srea", XRC(31,921,0), X_MASK, M601, { RA, RS, RB } },
4261 { "srea.", XRC(31,921,1), X_MASK, M601, { RA, RS, RB } },
4263 { "extsh", XRC(31,922,0), XRB_MASK, PPCCOM, { RA, RS } },
4264 { "exts", XRC(31,922,0), XRB_MASK, PWRCOM, { RA, RS } },
4265 { "extsh.", XRC(31,922,1), XRB_MASK, PPCCOM, { RA, RS } },
4266 { "exts.", XRC(31,922,1), XRB_MASK, PWRCOM, { RA, RS } },
4268 { "sthbrxe", X(31,926), X_MASK, BOOKE64, { RS, RA0, RB } },
4270 { "stdxe", X(31,927), X_MASK, BOOKE64, { RS, RA0, RB } },
4272 { "tlbrehi", XTLB(31,946,0), XTLB_MASK, PPC403, { RT, RA } },
4273 { "tlbrelo", XTLB(31,946,1), XTLB_MASK, PPC403, { RT, RA } },
4274 { "tlbre", X(31,946), X_MASK, BOOKE, { 0 } },
4275 { "tlbre", X(31,946), X_MASK, PPC403, { RS, RA, SH } },
4277 { "sraiq", XRC(31,952,0), X_MASK, M601, { RA, RS, SH } },
4278 { "sraiq.", XRC(31,952,1), X_MASK, M601, { RA, RS, SH } },
4280 { "extsb", XRC(31,954,0), XRB_MASK, PPC, { RA, RS} },
4281 { "extsb.", XRC(31,954,1), XRB_MASK, PPC, { RA, RS} },
4283 { "stduxe", X(31,959), X_MASK, BOOKE64, { RS, RAS, RB } },
4285 { "iccci", X(31,966), XRT_MASK, PPC403|PPC440, { RA, RB } },
4287 { "tlbwehi", XTLB(31,978,0), XTLB_MASK, PPC403, { RT, RA } },
4288 { "tlbwelo", XTLB(31,978,1), XTLB_MASK, PPC403, { RT, RA } },
4289 { "tlbwe", X(31,978), X_MASK, PPC403|BOOKE, { RSO, RAOPT, SHO } },
4290 { "tlbld", X(31,978), XRTRA_MASK, PPC, { RB } },
4292 { "icbi", X(31,982), XRT_MASK, PPC, { RA, RB } },
4294 { "stfiwx", X(31,983), X_MASK, PPC, { FRS, RA0, RB } },
4296 { "extsw", XRC(31,986,0), XRB_MASK, PPC64 | BOOKE64,{ RA, RS } },
4297 { "extsw.", XRC(31,986,1), XRB_MASK, PPC64, { RA, RS } },
4299 { "icread", X(31,998), XRT_MASK, PPC403|PPC440, { RA, RB } },
4301 { "icbie", X(31,990), XRT_MASK, BOOKE64, { RA, RB } },
4302 { "stfiwxe", X(31,991), X_MASK, BOOKE64, { FRS, RA0, RB } },
4304 { "tlbli", X(31,1010), XRTRA_MASK, PPC, { RB } },
4306 { "dcbz", X(31,1014), XRT_MASK, PPC, { RA, RB } },
4307 { "dclz", X(31,1014), XRT_MASK, PPC, { RA, RB } },
4309 { "dcbze", X(31,1022), XRT_MASK, BOOKE64, { RA, RB } },
4311 { "lvebx", X(31, 7), X_MASK, PPCVEC, { VD, RA, RB } },
4312 { "lvehx", X(31, 39), X_MASK, PPCVEC, { VD, RA, RB } },
4313 { "lvewx", X(31, 71), X_MASK, PPCVEC, { VD, RA, RB } },
4314 { "lvsl", X(31, 6), X_MASK, PPCVEC, { VD, RA, RB } },
4315 { "lvsr", X(31, 38), X_MASK, PPCVEC, { VD, RA, RB } },
4316 { "lvx", X(31, 103), X_MASK, PPCVEC, { VD, RA, RB } },
4317 { "lvxl", X(31, 359), X_MASK, PPCVEC, { VD, RA, RB } },
4318 { "stvebx", X(31, 135), X_MASK, PPCVEC, { VS, RA, RB } },
4319 { "stvehx", X(31, 167), X_MASK, PPCVEC, { VS, RA, RB } },
4320 { "stvewx", X(31, 199), X_MASK, PPCVEC, { VS, RA, RB } },
4321 { "stvx", X(31, 231), X_MASK, PPCVEC, { VS, RA, RB } },
4322 { "stvxl", X(31, 487), X_MASK, PPCVEC, { VS, RA, RB } },
4324 { "lwz", OP(32), OP_MASK, PPCCOM, { RT, D, RA0 } },
4325 { "l", OP(32), OP_MASK, PWRCOM, { RT, D, RA0 } },
4327 { "lwzu", OP(33), OP_MASK, PPCCOM, { RT, D, RAL } },
4328 { "lu", OP(33), OP_MASK, PWRCOM, { RT, D, RA0 } },
4330 { "lbz", OP(34), OP_MASK, COM, { RT, D, RA0 } },
4332 { "lbzu", OP(35), OP_MASK, COM, { RT, D, RAL } },
4334 { "stw", OP(36), OP_MASK, PPCCOM, { RS, D, RA0 } },
4335 { "st", OP(36), OP_MASK, PWRCOM, { RS, D, RA0 } },
4337 { "stwu", OP(37), OP_MASK, PPCCOM, { RS, D, RAS } },
4338 { "stu", OP(37), OP_MASK, PWRCOM, { RS, D, RA0 } },
4340 { "stb", OP(38), OP_MASK, COM, { RS, D, RA0 } },
4342 { "stbu", OP(39), OP_MASK, COM, { RS, D, RAS } },
4344 { "lhz", OP(40), OP_MASK, COM, { RT, D, RA0 } },
4346 { "lhzu", OP(41), OP_MASK, COM, { RT, D, RAL } },
4348 { "lha", OP(42), OP_MASK, COM, { RT, D, RA0 } },
4350 { "lhau", OP(43), OP_MASK, COM, { RT, D, RAL } },
4352 { "sth", OP(44), OP_MASK, COM, { RS, D, RA0 } },
4354 { "sthu", OP(45), OP_MASK, COM, { RS, D, RAS } },
4356 { "lmw", OP(46), OP_MASK, PPCCOM, { RT, D, RAM } },
4357 { "lm", OP(46), OP_MASK, PWRCOM, { RT, D, RA0 } },
4359 { "stmw", OP(47), OP_MASK, PPCCOM, { RS, D, RA0 } },
4360 { "stm", OP(47), OP_MASK, PWRCOM, { RS, D, RA0 } },
4362 { "lfs", OP(48), OP_MASK, COM, { FRT, D, RA0 } },
4364 { "lfsu", OP(49), OP_MASK, COM, { FRT, D, RAS } },
4366 { "lfd", OP(50), OP_MASK, COM, { FRT, D, RA0 } },
4368 { "lfdu", OP(51), OP_MASK, COM, { FRT, D, RAS } },
4370 { "stfs", OP(52), OP_MASK, COM, { FRS, D, RA0 } },
4372 { "stfsu", OP(53), OP_MASK, COM, { FRS, D, RAS } },
4374 { "stfd", OP(54), OP_MASK, COM, { FRS, D, RA0 } },
4376 { "stfdu", OP(55), OP_MASK, COM, { FRS, D, RAS } },
4378 { "lq", OP(56), OP_MASK, POWER4, { RTQ, DQ, RAQ } },
4380 { "lfq", OP(56), OP_MASK, POWER2, { FRT, D, RA0 } },
4382 { "lfqu", OP(57), OP_MASK, POWER2, { FRT, D, RA0 } },
4384 { "lbze", DEO(58,0), DE_MASK, BOOKE64, { RT, DE, RA0 } },
4385 { "lbzue", DEO(58,1), DE_MASK, BOOKE64, { RT, DE, RAL } },
4386 { "lhze", DEO(58,2), DE_MASK, BOOKE64, { RT, DE, RA0 } },
4387 { "lhzue", DEO(58,3), DE_MASK, BOOKE64, { RT, DE, RAL } },
4388 { "lhae", DEO(58,4), DE_MASK, BOOKE64, { RT, DE, RA0 } },
4389 { "lhaue", DEO(58,5), DE_MASK, BOOKE64, { RT, DE, RAL } },
4390 { "lwze", DEO(58,6), DE_MASK, BOOKE64, { RT, DE, RA0 } },
4391 { "lwzue", DEO(58,7), DE_MASK, BOOKE64, { RT, DE, RAL } },
4392 { "stbe", DEO(58,8), DE_MASK, BOOKE64, { RS, DE, RA0 } },
4393 { "stbue", DEO(58,9), DE_MASK, BOOKE64, { RS, DE, RAS } },
4394 { "sthe", DEO(58,10), DE_MASK, BOOKE64, { RS, DE, RA0 } },
4395 { "sthue", DEO(58,11), DE_MASK, BOOKE64, { RS, DE, RAS } },
4396 { "stwe", DEO(58,14), DE_MASK, BOOKE64, { RS, DE, RA0 } },
4397 { "stwue", DEO(58,15), DE_MASK, BOOKE64, { RS, DE, RAS } },
4399 { "ld", DSO(58,0), DS_MASK, PPC64, { RT, DS, RA0 } },
4401 { "ldu", DSO(58,1), DS_MASK, PPC64, { RT, DS, RAL } },
4403 { "lwa", DSO(58,2), DS_MASK, PPC64, { RT, DS, RA0 } },
4405 { "fdivs", A(59,18,0), AFRC_MASK, PPC, { FRT, FRA, FRB } },
4406 { "fdivs.", A(59,18,1), AFRC_MASK, PPC, { FRT, FRA, FRB } },
4408 { "fsubs", A(59,20,0), AFRC_MASK, PPC, { FRT, FRA, FRB } },
4409 { "fsubs.", A(59,20,1), AFRC_MASK, PPC, { FRT, FRA, FRB } },
4411 { "fadds", A(59,21,0), AFRC_MASK, PPC, { FRT, FRA, FRB } },
4412 { "fadds.", A(59,21,1), AFRC_MASK, PPC, { FRT, FRA, FRB } },
4414 { "fsqrts", A(59,22,0), AFRAFRC_MASK, PPC, { FRT, FRB } },
4415 { "fsqrts.", A(59,22,1), AFRAFRC_MASK, PPC, { FRT, FRB } },
4417 { "fres", A(59,24,0), AFRAFRC_MASK, PPC, { FRT, FRB } },
4418 { "fres.", A(59,24,1), AFRAFRC_MASK, PPC, { FRT, FRB } },
4420 { "fmuls", A(59,25,0), AFRB_MASK, PPC, { FRT, FRA, FRC } },
4421 { "fmuls.", A(59,25,1), AFRB_MASK, PPC, { FRT, FRA, FRC } },
4423 { "fmsubs", A(59,28,0), A_MASK, PPC, { FRT,FRA,FRC,FRB } },
4424 { "fmsubs.", A(59,28,1), A_MASK, PPC, { FRT,FRA,FRC,FRB } },
4426 { "fmadds", A(59,29,0), A_MASK, PPC, { FRT,FRA,FRC,FRB } },
4427 { "fmadds.", A(59,29,1), A_MASK, PPC, { FRT,FRA,FRC,FRB } },
4429 { "fnmsubs", A(59,30,0), A_MASK, PPC, { FRT,FRA,FRC,FRB } },
4430 { "fnmsubs.",A(59,30,1), A_MASK, PPC, { FRT,FRA,FRC,FRB } },
4432 { "fnmadds", A(59,31,0), A_MASK, PPC, { FRT,FRA,FRC,FRB } },
4433 { "fnmadds.",A(59,31,1), A_MASK, PPC, { FRT,FRA,FRC,FRB } },
4435 { "stfq", OP(60), OP_MASK, POWER2, { FRS, D, RA } },
4437 { "stfqu", OP(61), OP_MASK, POWER2, { FRS, D, RA } },
4439 { "lde", DEO(62,0), DE_MASK, BOOKE64, { RT, DES, RA0 } },
4440 { "ldue", DEO(62,1), DE_MASK, BOOKE64, { RT, DES, RA0 } },
4441 { "lfse", DEO(62,4), DE_MASK, BOOKE64, { FRT, DES, RA0 } },
4442 { "lfsue", DEO(62,5), DE_MASK, BOOKE64, { FRT, DES, RAS } },
4443 { "lfde", DEO(62,6), DE_MASK, BOOKE64, { FRT, DES, RA0 } },
4444 { "lfdue", DEO(62,7), DE_MASK, BOOKE64, { FRT, DES, RAS } },
4445 { "stde", DEO(62,8), DE_MASK, BOOKE64, { RS, DES, RA0 } },
4446 { "stdue", DEO(62,9), DE_MASK, BOOKE64, { RS, DES, RAS } },
4447 { "stfse", DEO(62,12), DE_MASK, BOOKE64, { FRS, DES, RA0 } },
4448 { "stfsue", DEO(62,13), DE_MASK, BOOKE64, { FRS, DES, RAS } },
4449 { "stfde", DEO(62,14), DE_MASK, BOOKE64, { FRS, DES, RA0 } },
4450 { "stfdue", DEO(62,15), DE_MASK, BOOKE64, { FRS, DES, RAS } },
4452 { "std", DSO(62,0), DS_MASK, PPC64, { RS, DS, RA0 } },
4454 { "stdu", DSO(62,1), DS_MASK, PPC64, { RS, DS, RAS } },
4456 { "stq", DSO(62,2), DS_MASK, POWER4, { RSQ, DS, RA0 } },
4458 { "fcmpu", X(63,0), X_MASK|(3<<21), COM, { BF, FRA, FRB } },
4460 { "frsp", XRC(63,12,0), XRA_MASK, COM, { FRT, FRB } },
4461 { "frsp.", XRC(63,12,1), XRA_MASK, COM, { FRT, FRB } },
4463 { "fctiw", XRC(63,14,0), XRA_MASK, PPCCOM, { FRT, FRB } },
4464 { "fcir", XRC(63,14,0), XRA_MASK, POWER2, { FRT, FRB } },
4465 { "fctiw.", XRC(63,14,1), XRA_MASK, PPCCOM, { FRT, FRB } },
4466 { "fcir.", XRC(63,14,1), XRA_MASK, POWER2, { FRT, FRB } },
4468 { "fctiwz", XRC(63,15,0), XRA_MASK, PPCCOM, { FRT, FRB } },
4469 { "fcirz", XRC(63,15,0), XRA_MASK, POWER2, { FRT, FRB } },
4470 { "fctiwz.", XRC(63,15,1), XRA_MASK, PPCCOM, { FRT, FRB } },
4471 { "fcirz.", XRC(63,15,1), XRA_MASK, POWER2, { FRT, FRB } },
4473 { "fdiv", A(63,18,0), AFRC_MASK, PPCCOM, { FRT, FRA, FRB } },
4474 { "fd", A(63,18,0), AFRC_MASK, PWRCOM, { FRT, FRA, FRB } },
4475 { "fdiv.", A(63,18,1), AFRC_MASK, PPCCOM, { FRT, FRA, FRB } },
4476 { "fd.", A(63,18,1), AFRC_MASK, PWRCOM, { FRT, FRA, FRB } },
4478 { "fsub", A(63,20,0), AFRC_MASK, PPCCOM, { FRT, FRA, FRB } },
4479 { "fs", A(63,20,0), AFRC_MASK, PWRCOM, { FRT, FRA, FRB } },
4480 { "fsub.", A(63,20,1), AFRC_MASK, PPCCOM, { FRT, FRA, FRB } },
4481 { "fs.", A(63,20,1), AFRC_MASK, PWRCOM, { FRT, FRA, FRB } },
4483 { "fadd", A(63,21,0), AFRC_MASK, PPCCOM, { FRT, FRA, FRB } },
4484 { "fa", A(63,21,0), AFRC_MASK, PWRCOM, { FRT, FRA, FRB } },
4485 { "fadd.", A(63,21,1), AFRC_MASK, PPCCOM, { FRT, FRA, FRB } },
4486 { "fa.", A(63,21,1), AFRC_MASK, PWRCOM, { FRT, FRA, FRB } },
4488 { "fsqrt", A(63,22,0), AFRAFRC_MASK, PPCPWR2, { FRT, FRB } },
4489 { "fsqrt.", A(63,22,1), AFRAFRC_MASK, PPCPWR2, { FRT, FRB } },
4491 { "fsel", A(63,23,0), A_MASK, PPC, { FRT,FRA,FRC,FRB } },
4492 { "fsel.", A(63,23,1), A_MASK, PPC, { FRT,FRA,FRC,FRB } },
4494 { "fmul", A(63,25,0), AFRB_MASK, PPCCOM, { FRT, FRA, FRC } },
4495 { "fm", A(63,25,0), AFRB_MASK, PWRCOM, { FRT, FRA, FRC } },
4496 { "fmul.", A(63,25,1), AFRB_MASK, PPCCOM, { FRT, FRA, FRC } },
4497 { "fm.", A(63,25,1), AFRB_MASK, PWRCOM, { FRT, FRA, FRC } },
4499 { "frsqrte", A(63,26,0), AFRAFRC_MASK, PPC, { FRT, FRB } },
4500 { "frsqrte.",A(63,26,1), AFRAFRC_MASK, PPC, { FRT, FRB } },
4502 { "fmsub", A(63,28,0), A_MASK, PPCCOM, { FRT,FRA,FRC,FRB } },
4503 { "fms", A(63,28,0), A_MASK, PWRCOM, { FRT,FRA,FRC,FRB } },
4504 { "fmsub.", A(63,28,1), A_MASK, PPCCOM, { FRT,FRA,FRC,FRB } },
4505 { "fms.", A(63,28,1), A_MASK, PWRCOM, { FRT,FRA,FRC,FRB } },
4507 { "fmadd", A(63,29,0), A_MASK, PPCCOM, { FRT,FRA,FRC,FRB } },
4508 { "fma", A(63,29,0), A_MASK, PWRCOM, { FRT,FRA,FRC,FRB } },
4509 { "fmadd.", A(63,29,1), A_MASK, PPCCOM, { FRT,FRA,FRC,FRB } },
4510 { "fma.", A(63,29,1), A_MASK, PWRCOM, { FRT,FRA,FRC,FRB } },
4512 { "fnmsub", A(63,30,0), A_MASK, PPCCOM, { FRT,FRA,FRC,FRB } },
4513 { "fnms", A(63,30,0), A_MASK, PWRCOM, { FRT,FRA,FRC,FRB } },
4514 { "fnmsub.", A(63,30,1), A_MASK, PPCCOM, { FRT,FRA,FRC,FRB } },
4515 { "fnms.", A(63,30,1), A_MASK, PWRCOM, { FRT,FRA,FRC,FRB } },
4517 { "fnmadd", A(63,31,0), A_MASK, PPCCOM, { FRT,FRA,FRC,FRB } },
4518 { "fnma", A(63,31,0), A_MASK, PWRCOM, { FRT,FRA,FRC,FRB } },
4519 { "fnmadd.", A(63,31,1), A_MASK, PPCCOM, { FRT,FRA,FRC,FRB } },
4520 { "fnma.", A(63,31,1), A_MASK, PWRCOM, { FRT,FRA,FRC,FRB } },
4522 { "fcmpo", X(63,32), X_MASK|(3<<21), COM, { BF, FRA, FRB } },
4524 { "mtfsb1", XRC(63,38,0), XRARB_MASK, COM, { BT } },
4525 { "mtfsb1.", XRC(63,38,1), XRARB_MASK, COM, { BT } },
4527 { "fneg", XRC(63,40,0), XRA_MASK, COM, { FRT, FRB } },
4528 { "fneg.", XRC(63,40,1), XRA_MASK, COM, { FRT, FRB } },
4530 { "mcrfs", X(63,64), XRB_MASK|(3<<21)|(3<<16), COM, { BF, BFA } },
4532 { "mtfsb0", XRC(63,70,0), XRARB_MASK, COM, { BT } },
4533 { "mtfsb0.", XRC(63,70,1), XRARB_MASK, COM, { BT } },
4535 { "fmr", XRC(63,72,0), XRA_MASK, COM, { FRT, FRB } },
4536 { "fmr.", XRC(63,72,1), XRA_MASK, COM, { FRT, FRB } },
4538 { "mtfsfi", XRC(63,134,0), XRA_MASK|(3<<21)|(1<<11), COM, { BF, U } },
4539 { "mtfsfi.", XRC(63,134,1), XRA_MASK|(3<<21)|(1<<11), COM, { BF, U } },
4541 { "fnabs", XRC(63,136,0), XRA_MASK, COM, { FRT, FRB } },
4542 { "fnabs.", XRC(63,136,1), XRA_MASK, COM, { FRT, FRB } },
4544 { "fabs", XRC(63,264,0), XRA_MASK, COM, { FRT, FRB } },
4545 { "fabs.", XRC(63,264,1), XRA_MASK, COM, { FRT, FRB } },
4547 { "mffs", XRC(63,583,0), XRARB_MASK, COM, { FRT } },
4548 { "mffs.", XRC(63,583,1), XRARB_MASK, COM, { FRT } },
4550 { "mtfsf", XFL(63,711,0), XFL_MASK, COM, { FLM, FRB } },
4551 { "mtfsf.", XFL(63,711,1), XFL_MASK, COM, { FLM, FRB } },
4553 { "fctid", XRC(63,814,0), XRA_MASK, PPC64, { FRT, FRB } },
4554 { "fctid.", XRC(63,814,1), XRA_MASK, PPC64, { FRT, FRB } },
4556 { "fctidz", XRC(63,815,0), XRA_MASK, PPC64, { FRT, FRB } },
4557 { "fctidz.", XRC(63,815,1), XRA_MASK, PPC64, { FRT, FRB } },
4559 { "fcfid", XRC(63,846,0), XRA_MASK, PPC64, { FRT, FRB } },
4560 { "fcfid.", XRC(63,846,1), XRA_MASK, PPC64, { FRT, FRB } },
4564 const int powerpc_num_opcodes =
4565 sizeof (powerpc_opcodes) / sizeof (powerpc_opcodes[0]);
4567 /* The macro table. This is only used by the assembler. */
4569 /* The expressions of the form (-x ! 31) & (x | 31) have the value 0
4570 when x=0; 32-x when x is between 1 and 31; are negative if x is
4571 negative; and are 32 or more otherwise. This is what you want
4572 when, for instance, you are emulating a right shift by a
4573 rotate-left-and-mask, because the underlying instructions support
4574 shifts of size 0 but not shifts of size 32. By comparison, when
4575 extracting x bits from some word you want to use just 32-x, because
4576 the underlying instructions don't support extracting 0 bits but do
4577 support extracting the whole word (32 bits in this case). */
4579 const struct powerpc_macro powerpc_macros[] = {
4580 { "extldi", 4, PPC64, "rldicr %0,%1,%3,(%2)-1" },
4581 { "extldi.", 4, PPC64, "rldicr. %0,%1,%3,(%2)-1" },
4582 { "extrdi", 4, PPC64, "rldicl %0,%1,(%2)+(%3),64-(%2)" },
4583 { "extrdi.", 4, PPC64, "rldicl. %0,%1,(%2)+(%3),64-(%2)" },
4584 { "insrdi", 4, PPC64, "rldimi %0,%1,64-((%2)+(%3)),%3" },
4585 { "insrdi.", 4, PPC64, "rldimi. %0,%1,64-((%2)+(%3)),%3" },
4586 { "rotrdi", 3, PPC64, "rldicl %0,%1,(-(%2)!63)&((%2)|63),0" },
4587 { "rotrdi.", 3, PPC64, "rldicl. %0,%1,(-(%2)!63)&((%2)|63),0" },
4588 { "sldi", 3, PPC64, "rldicr %0,%1,%2,63-(%2)" },
4589 { "sldi.", 3, PPC64, "rldicr. %0,%1,%2,63-(%2)" },
4590 { "srdi", 3, PPC64, "rldicl %0,%1,(-(%2)!63)&((%2)|63),%2" },
4591 { "srdi.", 3, PPC64, "rldicl. %0,%1,(-(%2)!63)&((%2)|63),%2" },
4592 { "clrrdi", 3, PPC64, "rldicr %0,%1,0,63-(%2)" },
4593 { "clrrdi.", 3, PPC64, "rldicr. %0,%1,0,63-(%2)" },
4594 { "clrlsldi",4, PPC64, "rldic %0,%1,%3,(%2)-(%3)" },
4595 { "clrlsldi.",4, PPC64, "rldic. %0,%1,%3,(%2)-(%3)" },
4597 { "extlwi", 4, PPCCOM, "rlwinm %0,%1,%3,0,(%2)-1" },
4598 { "extlwi.", 4, PPCCOM, "rlwinm. %0,%1,%3,0,(%2)-1" },
4599 { "extrwi", 4, PPCCOM, "rlwinm %0,%1,((%2)+(%3))&((%2)+(%3)<>32),32-(%2),31" },
4600 { "extrwi.", 4, PPCCOM, "rlwinm. %0,%1,((%2)+(%3))&((%2)+(%3)<>32),32-(%2),31" },
4601 { "inslwi", 4, PPCCOM, "rlwimi %0,%1,(-(%3)!31)&((%3)|31),%3,(%2)+(%3)-1" },
4602 { "inslwi.", 4, PPCCOM, "rlwimi. %0,%1,(-(%3)!31)&((%3)|31),%3,(%2)+(%3)-1"},
4603 { "insrwi", 4, PPCCOM, "rlwimi %0,%1,32-((%2)+(%3)),%3,(%2)+(%3)-1" },
4604 { "insrwi.", 4, PPCCOM, "rlwimi. %0,%1,32-((%2)+(%3)),%3,(%2)+(%3)-1"},
4605 { "rotrwi", 3, PPCCOM, "rlwinm %0,%1,(-(%2)!31)&((%2)|31),0,31" },
4606 { "rotrwi.", 3, PPCCOM, "rlwinm. %0,%1,(-(%2)!31)&((%2)|31),0,31" },
4607 { "slwi", 3, PPCCOM, "rlwinm %0,%1,%2,0,31-(%2)" },
4608 { "sli", 3, PWRCOM, "rlinm %0,%1,%2,0,31-(%2)" },
4609 { "slwi.", 3, PPCCOM, "rlwinm. %0,%1,%2,0,31-(%2)" },
4610 { "sli.", 3, PWRCOM, "rlinm. %0,%1,%2,0,31-(%2)" },
4611 { "srwi", 3, PPCCOM, "rlwinm %0,%1,(-(%2)!31)&((%2)|31),%2,31" },
4612 { "sri", 3, PWRCOM, "rlinm %0,%1,(-(%2)!31)&((%2)|31),%2,31" },
4613 { "srwi.", 3, PPCCOM, "rlwinm. %0,%1,(-(%2)!31)&((%2)|31),%2,31" },
4614 { "sri.", 3, PWRCOM, "rlinm. %0,%1,(-(%2)!31)&((%2)|31),%2,31" },
4615 { "clrrwi", 3, PPCCOM, "rlwinm %0,%1,0,0,31-(%2)" },
4616 { "clrrwi.", 3, PPCCOM, "rlwinm. %0,%1,0,0,31-(%2)" },
4617 { "clrlslwi",4, PPCCOM, "rlwinm %0,%1,%3,(%2)-(%3),31-(%3)" },
4618 { "clrlslwi.",4, PPCCOM, "rlwinm. %0,%1,%3,(%2)-(%3),31-(%3)" },
4621 const int powerpc_num_macros =
4622 sizeof (powerpc_macros) / sizeof (powerpc_macros[0]);