1 /* ppc-dis.c -- Disassemble PowerPC instructions
2 Copyright (C) 1994-2018 Free Software Foundation, Inc.
3 Written by Ian Lance Taylor, Cygnus Support
5 This file is part of the GNU opcodes library.
7 This library is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 3, or (at your option)
12 It is distributed in the hope that it will be useful, but WITHOUT
13 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
14 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
15 License for more details.
17 You should have received a copy of the GNU General Public License
18 along with this file; see the file COPYING. If not, write to the
19 Free Software Foundation, 51 Franklin Street - Fifth Floor, Boston,
20 MA 02110-1301, USA. */
24 #include "disassemble.h"
28 #include "opcode/ppc.h"
29 #include "libiberty.h"
31 /* This file provides several disassembler functions, all of which use
32 the disassembler interface defined in dis-asm.h. Several functions
33 are provided because this file handles disassembly for the PowerPC
34 in both big and little endian mode and also for the POWER (RS/6000)
36 static int print_insn_powerpc (bfd_vma, struct disassemble_info *, int,
41 /* Stash the result of parsing disassembler_options here. */
45 #define POWERPC_DIALECT(INFO) \
46 (((struct dis_private *) ((INFO)->private_data))->dialect)
49 /* Option string, without -m or -M prefix. */
51 /* CPU option flags. */
53 /* Flags that should stay on, even when combined with another cpu
54 option. This should only be used for generic options like
55 "-many" or "-maltivec" where it is reasonable to add some
56 capability to another cpu selection. The added flags are sticky
57 so that, for example, "-many -me500" and "-me500 -many" result in
58 the same assembler or disassembler behaviour. Do not use
59 "sticky" for specific cpus, as this will prevent that cpu's flags
60 from overriding the defaults set in powerpc_init_dialect or a
65 struct ppc_mopt ppc_opts[] = {
66 { "403", PPC_OPCODE_PPC | PPC_OPCODE_403,
68 { "405", PPC_OPCODE_PPC | PPC_OPCODE_403 | PPC_OPCODE_405,
70 { "440", (PPC_OPCODE_PPC | PPC_OPCODE_BOOKE | PPC_OPCODE_440
71 | PPC_OPCODE_ISEL | PPC_OPCODE_RFMCI),
73 { "464", (PPC_OPCODE_PPC | PPC_OPCODE_BOOKE | PPC_OPCODE_440
74 | PPC_OPCODE_ISEL | PPC_OPCODE_RFMCI),
76 { "476", (PPC_OPCODE_PPC | PPC_OPCODE_ISEL | PPC_OPCODE_476
77 | PPC_OPCODE_POWER4 | PPC_OPCODE_POWER5),
79 { "601", PPC_OPCODE_PPC | PPC_OPCODE_601,
81 { "603", PPC_OPCODE_PPC,
83 { "604", PPC_OPCODE_PPC,
85 { "620", PPC_OPCODE_PPC | PPC_OPCODE_64,
87 { "7400", PPC_OPCODE_PPC | PPC_OPCODE_ALTIVEC,
89 { "7410", PPC_OPCODE_PPC | PPC_OPCODE_ALTIVEC,
91 { "7450", PPC_OPCODE_PPC | PPC_OPCODE_7450 | PPC_OPCODE_ALTIVEC,
93 { "7455", PPC_OPCODE_PPC | PPC_OPCODE_ALTIVEC,
95 { "750cl", PPC_OPCODE_PPC | PPC_OPCODE_750 | PPC_OPCODE_PPCPS
97 { "821", PPC_OPCODE_PPC | PPC_OPCODE_860,
99 { "850", PPC_OPCODE_PPC | PPC_OPCODE_860,
101 { "860", PPC_OPCODE_PPC | PPC_OPCODE_860,
103 { "a2", (PPC_OPCODE_PPC | PPC_OPCODE_ISEL | PPC_OPCODE_POWER4
104 | PPC_OPCODE_POWER5 | PPC_OPCODE_CACHELCK | PPC_OPCODE_64
107 { "altivec", PPC_OPCODE_PPC,
108 PPC_OPCODE_ALTIVEC },
109 { "any", PPC_OPCODE_PPC,
111 { "booke", PPC_OPCODE_PPC | PPC_OPCODE_BOOKE,
113 { "booke32", PPC_OPCODE_PPC | PPC_OPCODE_BOOKE,
115 { "cell", (PPC_OPCODE_PPC | PPC_OPCODE_64 | PPC_OPCODE_POWER4
116 | PPC_OPCODE_CELL | PPC_OPCODE_ALTIVEC),
118 { "com", PPC_OPCODE_COMMON,
120 { "e200z4", (PPC_OPCODE_PPC | PPC_OPCODE_BOOKE| PPC_OPCODE_SPE
121 | PPC_OPCODE_ISEL | PPC_OPCODE_EFS | PPC_OPCODE_BRLOCK
122 | PPC_OPCODE_PMR | PPC_OPCODE_CACHELCK | PPC_OPCODE_RFMCI
123 | PPC_OPCODE_E500 | PPC_OPCODE_VLE | PPC_OPCODE_E200Z4
124 | PPC_OPCODE_EFS2 | PPC_OPCODE_LSP),
126 { "e300", PPC_OPCODE_PPC | PPC_OPCODE_E300,
128 { "e500", (PPC_OPCODE_PPC | PPC_OPCODE_BOOKE | PPC_OPCODE_SPE
129 | PPC_OPCODE_ISEL | PPC_OPCODE_EFS | PPC_OPCODE_BRLOCK
130 | PPC_OPCODE_PMR | PPC_OPCODE_CACHELCK | PPC_OPCODE_RFMCI
133 { "e500mc", (PPC_OPCODE_PPC | PPC_OPCODE_BOOKE | PPC_OPCODE_ISEL
134 | PPC_OPCODE_PMR | PPC_OPCODE_CACHELCK | PPC_OPCODE_RFMCI
135 | PPC_OPCODE_E500MC),
137 { "e500mc64", (PPC_OPCODE_PPC | PPC_OPCODE_BOOKE | PPC_OPCODE_ISEL
138 | PPC_OPCODE_PMR | PPC_OPCODE_CACHELCK | PPC_OPCODE_RFMCI
139 | PPC_OPCODE_E500MC | PPC_OPCODE_64 | PPC_OPCODE_POWER5
140 | PPC_OPCODE_POWER6 | PPC_OPCODE_POWER7),
142 { "e5500", (PPC_OPCODE_PPC | PPC_OPCODE_BOOKE | PPC_OPCODE_ISEL
143 | PPC_OPCODE_PMR | PPC_OPCODE_CACHELCK | PPC_OPCODE_RFMCI
144 | PPC_OPCODE_E500MC | PPC_OPCODE_64 | PPC_OPCODE_POWER4
145 | PPC_OPCODE_POWER5 | PPC_OPCODE_POWER6 | PPC_OPCODE_POWER7),
147 { "e6500", (PPC_OPCODE_PPC | PPC_OPCODE_BOOKE | PPC_OPCODE_ISEL
148 | PPC_OPCODE_PMR | PPC_OPCODE_CACHELCK | PPC_OPCODE_RFMCI
149 | PPC_OPCODE_E500MC | PPC_OPCODE_64 | PPC_OPCODE_ALTIVEC
150 | PPC_OPCODE_E6500 | PPC_OPCODE_TMR | PPC_OPCODE_POWER4
151 | PPC_OPCODE_POWER5 | PPC_OPCODE_POWER6 | PPC_OPCODE_POWER7),
153 { "e500x2", (PPC_OPCODE_PPC | PPC_OPCODE_BOOKE | PPC_OPCODE_SPE
154 | PPC_OPCODE_ISEL | PPC_OPCODE_EFS | PPC_OPCODE_BRLOCK
155 | PPC_OPCODE_PMR | PPC_OPCODE_CACHELCK | PPC_OPCODE_RFMCI
158 { "efs", PPC_OPCODE_PPC | PPC_OPCODE_EFS,
160 { "efs2", PPC_OPCODE_PPC | PPC_OPCODE_EFS | PPC_OPCODE_EFS2,
162 { "power4", PPC_OPCODE_PPC | PPC_OPCODE_64 | PPC_OPCODE_POWER4,
164 { "power5", (PPC_OPCODE_PPC | PPC_OPCODE_64 | PPC_OPCODE_POWER4
165 | PPC_OPCODE_POWER5),
167 { "power6", (PPC_OPCODE_PPC | PPC_OPCODE_64 | PPC_OPCODE_POWER4
168 | PPC_OPCODE_POWER5 | PPC_OPCODE_POWER6 | PPC_OPCODE_ALTIVEC),
170 { "power7", (PPC_OPCODE_PPC | PPC_OPCODE_ISEL | PPC_OPCODE_64
171 | PPC_OPCODE_POWER4 | PPC_OPCODE_POWER5 | PPC_OPCODE_POWER6
172 | PPC_OPCODE_POWER7 | PPC_OPCODE_ALTIVEC | PPC_OPCODE_VSX),
174 { "power8", (PPC_OPCODE_PPC | PPC_OPCODE_ISEL | PPC_OPCODE_64
175 | PPC_OPCODE_POWER4 | PPC_OPCODE_POWER5 | PPC_OPCODE_POWER6
176 | PPC_OPCODE_POWER7 | PPC_OPCODE_POWER8
177 | PPC_OPCODE_ALTIVEC | PPC_OPCODE_VSX),
179 { "power9", (PPC_OPCODE_PPC | PPC_OPCODE_ISEL | PPC_OPCODE_64
180 | PPC_OPCODE_POWER4 | PPC_OPCODE_POWER5 | PPC_OPCODE_POWER6
181 | PPC_OPCODE_POWER7 | PPC_OPCODE_POWER8 | PPC_OPCODE_POWER9
182 | PPC_OPCODE_ALTIVEC | PPC_OPCODE_VSX),
184 { "ppc", PPC_OPCODE_PPC,
186 { "ppc32", PPC_OPCODE_PPC,
188 { "32", PPC_OPCODE_PPC,
190 { "ppc64", PPC_OPCODE_PPC | PPC_OPCODE_64,
192 { "64", PPC_OPCODE_PPC | PPC_OPCODE_64,
194 { "ppc64bridge", PPC_OPCODE_PPC | PPC_OPCODE_64_BRIDGE,
196 { "ppcps", PPC_OPCODE_PPC | PPC_OPCODE_PPCPS,
198 { "pwr", PPC_OPCODE_POWER,
200 { "pwr2", PPC_OPCODE_POWER | PPC_OPCODE_POWER2,
202 { "pwr4", PPC_OPCODE_PPC | PPC_OPCODE_64 | PPC_OPCODE_POWER4,
204 { "pwr5", (PPC_OPCODE_PPC | PPC_OPCODE_64 | PPC_OPCODE_POWER4
205 | PPC_OPCODE_POWER5),
207 { "pwr5x", (PPC_OPCODE_PPC | PPC_OPCODE_64 | PPC_OPCODE_POWER4
208 | PPC_OPCODE_POWER5),
210 { "pwr6", (PPC_OPCODE_PPC | PPC_OPCODE_64 | PPC_OPCODE_POWER4
211 | PPC_OPCODE_POWER5 | PPC_OPCODE_POWER6 | PPC_OPCODE_ALTIVEC),
213 { "pwr7", (PPC_OPCODE_PPC | PPC_OPCODE_ISEL | PPC_OPCODE_64
214 | PPC_OPCODE_POWER4 | PPC_OPCODE_POWER5 | PPC_OPCODE_POWER6
215 | PPC_OPCODE_POWER7 | PPC_OPCODE_ALTIVEC | PPC_OPCODE_VSX),
217 { "pwr8", (PPC_OPCODE_PPC | PPC_OPCODE_ISEL | PPC_OPCODE_64
218 | PPC_OPCODE_POWER4 | PPC_OPCODE_POWER5 | PPC_OPCODE_POWER6
219 | PPC_OPCODE_POWER7 | PPC_OPCODE_POWER8
220 | PPC_OPCODE_ALTIVEC | PPC_OPCODE_VSX),
222 { "pwr9", (PPC_OPCODE_PPC | PPC_OPCODE_ISEL | PPC_OPCODE_64
223 | PPC_OPCODE_POWER4 | PPC_OPCODE_POWER5 | PPC_OPCODE_POWER6
224 | PPC_OPCODE_POWER7 | PPC_OPCODE_POWER8 | PPC_OPCODE_POWER9
225 | PPC_OPCODE_ALTIVEC | PPC_OPCODE_VSX),
227 { "pwrx", PPC_OPCODE_POWER | PPC_OPCODE_POWER2,
229 { "raw", PPC_OPCODE_PPC,
231 { "spe", PPC_OPCODE_PPC | PPC_OPCODE_EFS,
233 { "spe2", PPC_OPCODE_PPC | PPC_OPCODE_EFS | PPC_OPCODE_EFS2 | PPC_OPCODE_SPE,
235 { "titan", (PPC_OPCODE_PPC | PPC_OPCODE_BOOKE | PPC_OPCODE_PMR
236 | PPC_OPCODE_RFMCI | PPC_OPCODE_TITAN),
238 { "vle", (PPC_OPCODE_PPC | PPC_OPCODE_BOOKE| PPC_OPCODE_SPE
239 | PPC_OPCODE_ISEL | PPC_OPCODE_EFS | PPC_OPCODE_BRLOCK
240 | PPC_OPCODE_PMR | PPC_OPCODE_CACHELCK | PPC_OPCODE_RFMCI
241 | PPC_OPCODE_LSP | PPC_OPCODE_EFS2 | PPC_OPCODE_SPE2),
243 { "vsx", PPC_OPCODE_PPC,
247 /* Switch between Booke and VLE dialects for interlinked dumps. */
249 get_powerpc_dialect (struct disassemble_info *info)
251 ppc_cpu_t dialect = 0;
253 dialect = POWERPC_DIALECT (info);
255 /* Disassemble according to the section headers flags for VLE-mode. */
256 if (dialect & PPC_OPCODE_VLE
257 && info->section != NULL && info->section->owner != NULL
258 && bfd_get_flavour (info->section->owner) == bfd_target_elf_flavour
259 && elf_object_id (info->section->owner) == PPC32_ELF_DATA
260 && (elf_section_flags (info->section) & SHF_PPC_VLE) != 0)
263 return dialect & ~ PPC_OPCODE_VLE;
266 /* Handle -m and -M options that set cpu type, and .machine arg. */
269 ppc_parse_cpu (ppc_cpu_t ppc_cpu, ppc_cpu_t *sticky, const char *arg)
273 for (i = 0; i < ARRAY_SIZE (ppc_opts); i++)
274 if (disassembler_options_cmp (ppc_opts[i].opt, arg) == 0)
276 if (ppc_opts[i].sticky)
278 *sticky |= ppc_opts[i].sticky;
279 if ((ppc_cpu & ~*sticky) != 0)
282 ppc_cpu = ppc_opts[i].cpu;
285 if (i >= ARRAY_SIZE (ppc_opts))
292 /* Determine which set of machines to disassemble for. */
295 powerpc_init_dialect (struct disassemble_info *info)
297 ppc_cpu_t dialect = 0;
298 ppc_cpu_t sticky = 0;
299 struct dis_private *priv = calloc (sizeof (*priv), 1);
306 case bfd_mach_ppc_403:
307 case bfd_mach_ppc_403gc:
308 dialect = ppc_parse_cpu (dialect, &sticky, "403");
310 case bfd_mach_ppc_405:
311 dialect = ppc_parse_cpu (dialect, &sticky, "405");
313 case bfd_mach_ppc_601:
314 dialect = ppc_parse_cpu (dialect, &sticky, "601");
316 case bfd_mach_ppc_a35:
317 case bfd_mach_ppc_rs64ii:
318 case bfd_mach_ppc_rs64iii:
319 dialect = ppc_parse_cpu (dialect, &sticky, "pwr2") | PPC_OPCODE_64;
321 case bfd_mach_ppc_e500:
322 dialect = ppc_parse_cpu (dialect, &sticky, "e500");
324 case bfd_mach_ppc_e500mc:
325 dialect = ppc_parse_cpu (dialect, &sticky, "e500mc");
327 case bfd_mach_ppc_e500mc64:
328 dialect = ppc_parse_cpu (dialect, &sticky, "e500mc64");
330 case bfd_mach_ppc_e5500:
331 dialect = ppc_parse_cpu (dialect, &sticky, "e5500");
333 case bfd_mach_ppc_e6500:
334 dialect = ppc_parse_cpu (dialect, &sticky, "e6500");
336 case bfd_mach_ppc_titan:
337 dialect = ppc_parse_cpu (dialect, &sticky, "titan");
339 case bfd_mach_ppc_vle:
340 dialect = ppc_parse_cpu (dialect, &sticky, "vle");
343 if (info->arch == bfd_arch_powerpc)
344 dialect = ppc_parse_cpu (dialect, &sticky, "power9") | PPC_OPCODE_ANY;
346 dialect = ppc_parse_cpu (dialect, &sticky, "pwr");
351 FOR_EACH_DISASSEMBLER_OPTION (opt, info->disassembler_options)
353 ppc_cpu_t new_cpu = 0;
355 if (disassembler_options_cmp (opt, "32") == 0)
356 dialect &= ~(ppc_cpu_t) PPC_OPCODE_64;
357 else if (disassembler_options_cmp (opt, "64") == 0)
358 dialect |= PPC_OPCODE_64;
359 else if ((new_cpu = ppc_parse_cpu (dialect, &sticky, opt)) != 0)
362 /* xgettext: c-format */
363 opcodes_error_handler (_("warning: ignoring unknown -M%s option"), opt);
366 info->private_data = priv;
367 POWERPC_DIALECT(info) = dialect;
370 #define PPC_OPCD_SEGS (1 + PPC_OP (-1))
371 static unsigned short powerpc_opcd_indices[PPC_OPCD_SEGS + 1];
372 #define VLE_OPCD_SEGS (1 + VLE_OP_TO_SEG (VLE_OP (-1, 0xffff)))
373 static unsigned short vle_opcd_indices[VLE_OPCD_SEGS + 1];
374 #define SPE2_OPCD_SEGS (1 + SPE2_XOP_TO_SEG (SPE2_XOP (-1)))
375 static unsigned short spe2_opcd_indices[SPE2_OPCD_SEGS + 1];
377 /* Calculate opcode table indices to speed up disassembly,
381 disassemble_init_powerpc (struct disassemble_info *info)
383 if (powerpc_opcd_indices[PPC_OPCD_SEGS] == 0)
385 unsigned seg, idx, op;
388 for (seg = 0, idx = 0; seg <= PPC_OPCD_SEGS; seg++)
390 powerpc_opcd_indices[seg] = idx;
391 for (; idx < powerpc_num_opcodes; idx++)
392 if (seg < PPC_OP (powerpc_opcodes[idx].opcode))
397 for (seg = 0, idx = 0; seg <= VLE_OPCD_SEGS; seg++)
399 vle_opcd_indices[seg] = idx;
400 for (; idx < vle_num_opcodes; idx++)
402 op = VLE_OP (vle_opcodes[idx].opcode, vle_opcodes[idx].mask);
403 if (seg < VLE_OP_TO_SEG (op))
409 for (seg = 0, idx = 0; seg <= SPE2_OPCD_SEGS; seg++)
411 spe2_opcd_indices[seg] = idx;
412 for (; idx < spe2_num_opcodes; idx++)
414 op = SPE2_XOP (spe2_opcodes[idx].opcode);
415 if (seg < SPE2_XOP_TO_SEG (op))
421 powerpc_init_dialect (info);
424 /* Print a big endian PowerPC instruction. */
427 print_insn_big_powerpc (bfd_vma memaddr, struct disassemble_info *info)
429 return print_insn_powerpc (memaddr, info, 1, get_powerpc_dialect (info));
432 /* Print a little endian PowerPC instruction. */
435 print_insn_little_powerpc (bfd_vma memaddr, struct disassemble_info *info)
437 return print_insn_powerpc (memaddr, info, 0, get_powerpc_dialect (info));
440 /* Extract the operand value from the PowerPC or POWER instruction. */
443 operand_value_powerpc (const struct powerpc_operand *operand,
444 uint64_t insn, ppc_cpu_t dialect)
448 /* Extract the value from the instruction. */
449 if (operand->extract)
450 value = (*operand->extract) (insn, dialect, &invalid);
453 if (operand->shift >= 0)
454 value = (insn >> operand->shift) & operand->bitm;
456 value = (insn << -operand->shift) & operand->bitm;
457 if ((operand->flags & PPC_OPERAND_SIGNED) != 0)
459 /* BITM is always some number of zeros followed by some
460 number of ones, followed by some number of zeros. */
461 uint64_t top = operand->bitm;
462 /* top & -top gives the rightmost 1 bit, so this
463 fills in any trailing zeros. */
464 top |= (top & -top) - 1;
466 value = (value ^ top) - top;
473 /* Determine whether the optional operand(s) should be printed. */
476 skip_optional_operands (const unsigned char *opindex,
477 uint64_t insn, ppc_cpu_t dialect)
479 const struct powerpc_operand *operand;
481 for (; *opindex != 0; opindex++)
483 operand = &powerpc_operands[*opindex];
484 if ((operand->flags & PPC_OPERAND_NEXT) != 0
485 || ((operand->flags & PPC_OPERAND_OPTIONAL) != 0
486 && operand_value_powerpc (operand, insn, dialect) !=
487 ppc_optional_operand_value (operand)))
494 /* Find a match for INSN in the opcode table, given machine DIALECT. */
496 static const struct powerpc_opcode *
497 lookup_powerpc (uint64_t insn, ppc_cpu_t dialect)
499 const struct powerpc_opcode *opcode, *opcode_end, *last;
502 /* Get the major opcode of the instruction. */
505 /* Find the first match in the opcode table for this major opcode. */
506 opcode_end = powerpc_opcodes + powerpc_opcd_indices[op + 1];
508 for (opcode = powerpc_opcodes + powerpc_opcd_indices[op];
512 const unsigned char *opindex;
513 const struct powerpc_operand *operand;
516 if ((insn & opcode->mask) != opcode->opcode
517 || ((dialect & PPC_OPCODE_ANY) == 0
518 && ((opcode->flags & dialect) == 0
519 || (opcode->deprecated & dialect) != 0)))
522 /* Check validity of operands. */
524 for (opindex = opcode->operands; *opindex != 0; opindex++)
526 operand = powerpc_operands + *opindex;
527 if (operand->extract)
528 (*operand->extract) (insn, dialect, &invalid);
533 if ((dialect & PPC_OPCODE_RAW) == 0)
536 /* The raw machine insn is one that is not a specialization. */
538 || (last->mask & ~opcode->mask) != 0)
545 /* Find a match for INSN in the VLE opcode table. */
547 static const struct powerpc_opcode *
548 lookup_vle (uint64_t insn)
550 const struct powerpc_opcode *opcode;
551 const struct powerpc_opcode *opcode_end;
555 if (op >= 0x20 && op <= 0x37)
557 /* This insn has a 4-bit opcode. */
560 seg = VLE_OP_TO_SEG (op);
562 /* Find the first match in the opcode table for this major opcode. */
563 opcode_end = vle_opcodes + vle_opcd_indices[seg + 1];
564 for (opcode = vle_opcodes + vle_opcd_indices[seg];
568 uint64_t table_opcd = opcode->opcode;
569 uint64_t table_mask = opcode->mask;
570 bfd_boolean table_op_is_short = PPC_OP_SE_VLE(table_mask);
572 const unsigned char *opindex;
573 const struct powerpc_operand *operand;
577 if (table_op_is_short)
579 if ((insn2 & table_mask) != table_opcd)
582 /* Check validity of operands. */
584 for (opindex = opcode->operands; *opindex != 0; ++opindex)
586 operand = powerpc_operands + *opindex;
587 if (operand->extract)
588 (*operand->extract) (insn, (ppc_cpu_t)0, &invalid);
599 /* Find a match for INSN in the SPE2 opcode table. */
601 static const struct powerpc_opcode *
602 lookup_spe2 (uint64_t insn)
604 const struct powerpc_opcode *opcode, *opcode_end;
605 unsigned op, xop, seg;
610 /* This is not SPE2 insn.
611 * All SPE2 instructions have OP=4 and differs by XOP */
614 xop = SPE2_XOP (insn);
615 seg = SPE2_XOP_TO_SEG (xop);
617 /* Find the first match in the opcode table for this major opcode. */
618 opcode_end = spe2_opcodes + spe2_opcd_indices[seg + 1];
619 for (opcode = spe2_opcodes + spe2_opcd_indices[seg];
623 uint64_t table_opcd = opcode->opcode;
624 uint64_t table_mask = opcode->mask;
626 const unsigned char *opindex;
627 const struct powerpc_operand *operand;
631 if ((insn2 & table_mask) != table_opcd)
634 /* Check validity of operands. */
636 for (opindex = opcode->operands; *opindex != 0; ++opindex)
638 operand = powerpc_operands + *opindex;
639 if (operand->extract)
640 (*operand->extract) (insn, (ppc_cpu_t)0, &invalid);
651 /* Print a PowerPC or POWER instruction. */
654 print_insn_powerpc (bfd_vma memaddr,
655 struct disassemble_info *info,
662 const struct powerpc_opcode *opcode;
663 int insn_length = 4; /* Assume we have a normal 4-byte instruction. */
665 status = (*info->read_memory_func) (memaddr, buffer, 4, info);
667 /* The final instruction may be a 2-byte VLE insn. */
668 if (status != 0 && (dialect & PPC_OPCODE_VLE) != 0)
670 /* Clear buffer so unused bytes will not have garbage in them. */
671 buffer[0] = buffer[1] = buffer[2] = buffer[3] = 0;
672 status = (*info->read_memory_func) (memaddr, buffer, 2, info);
677 (*info->memory_error_func) (status, memaddr, info);
682 insn = bfd_getb32 (buffer);
684 insn = bfd_getl32 (buffer);
686 /* Get the major opcode of the insn. */
688 if ((dialect & PPC_OPCODE_VLE) != 0)
690 opcode = lookup_vle (insn);
691 if (opcode != NULL && PPC_OP_SE_VLE (opcode->mask))
693 /* The operands will be fetched out of the 16-bit instruction. */
698 if (opcode == NULL && (dialect & PPC_OPCODE_SPE2) != 0)
699 opcode = lookup_spe2 (insn);
701 opcode = lookup_powerpc (insn, dialect & ~PPC_OPCODE_ANY);
702 if (opcode == NULL && (dialect & PPC_OPCODE_ANY) != 0)
703 opcode = lookup_powerpc (insn, dialect);
707 const unsigned char *opindex;
708 const struct powerpc_operand *operand;
713 if (opcode->operands[0] != 0)
714 (*info->fprintf_func) (info->stream, "%-7s ", opcode->name);
716 (*info->fprintf_func) (info->stream, "%s", opcode->name);
718 /* Now extract and print the operands. */
722 for (opindex = opcode->operands; *opindex != 0; opindex++)
726 operand = powerpc_operands + *opindex;
728 /* If all of the optional operands have the value zero,
729 then don't print any of them. */
730 if ((operand->flags & PPC_OPERAND_OPTIONAL) != 0)
732 if (skip_optional < 0)
733 skip_optional = skip_optional_operands (opindex, insn,
739 value = operand_value_powerpc (operand, insn, dialect);
743 (*info->fprintf_func) (info->stream, ",");
747 /* Print the operand as directed by the flags. */
748 if ((operand->flags & PPC_OPERAND_GPR) != 0
749 || ((operand->flags & PPC_OPERAND_GPR_0) != 0 && value != 0))
750 (*info->fprintf_func) (info->stream, "r%" PPC_INT_FMT "d", value);
751 else if ((operand->flags & PPC_OPERAND_FPR) != 0)
752 (*info->fprintf_func) (info->stream, "f%" PPC_INT_FMT "d", value);
753 else if ((operand->flags & PPC_OPERAND_VR) != 0)
754 (*info->fprintf_func) (info->stream, "v%" PPC_INT_FMT "d", value);
755 else if ((operand->flags & PPC_OPERAND_VSR) != 0)
756 (*info->fprintf_func) (info->stream, "vs%" PPC_INT_FMT "d", value);
757 else if ((operand->flags & PPC_OPERAND_RELATIVE) != 0)
758 (*info->print_address_func) (memaddr + value, info);
759 else if ((operand->flags & PPC_OPERAND_ABSOLUTE) != 0)
760 (*info->print_address_func) ((bfd_vma) value & 0xffffffff, info);
761 else if ((operand->flags & PPC_OPERAND_FSL) != 0)
762 (*info->fprintf_func) (info->stream, "fsl%" PPC_INT_FMT "d", value);
763 else if ((operand->flags & PPC_OPERAND_FCR) != 0)
764 (*info->fprintf_func) (info->stream, "fcr%" PPC_INT_FMT "d", value);
765 else if ((operand->flags & PPC_OPERAND_UDI) != 0)
766 (*info->fprintf_func) (info->stream, "%" PPC_INT_FMT "d", value);
767 else if ((operand->flags & PPC_OPERAND_CR_REG) != 0
768 && (((dialect & PPC_OPCODE_PPC) != 0)
769 || ((dialect & PPC_OPCODE_VLE) != 0)))
770 (*info->fprintf_func) (info->stream, "cr%" PPC_INT_FMT "d", value);
771 else if (((operand->flags & PPC_OPERAND_CR_BIT) != 0)
772 && (((dialect & PPC_OPCODE_PPC) != 0)
773 || ((dialect & PPC_OPCODE_VLE) != 0)))
775 static const char *cbnames[4] = { "lt", "gt", "eq", "so" };
781 (*info->fprintf_func) (info->stream, "4*cr%d+", cr);
783 (*info->fprintf_func) (info->stream, "%s", cbnames[cc]);
786 (*info->fprintf_func) (info->stream, "%" PPC_INT_FMT "d", value);
790 (*info->fprintf_func) (info->stream, ")");
794 if ((operand->flags & PPC_OPERAND_PARENS) == 0)
798 (*info->fprintf_func) (info->stream, "(");
803 /* We have found and printed an instruction. */
807 /* We could not find a match. */
808 (*info->fprintf_func) (info->stream, ".long 0x%" PPC_INT_FMT "x", insn);
813 const disasm_options_and_args_t *
814 disassembler_options_powerpc (void)
816 static disasm_options_and_args_t *opts_and_args;
818 if (opts_and_args == NULL)
820 size_t i, num_options = ARRAY_SIZE (ppc_opts);
821 disasm_options_t *opts;
823 opts_and_args = XNEW (disasm_options_and_args_t);
824 opts_and_args->args = NULL;
826 opts = &opts_and_args->options;
827 opts->name = XNEWVEC (const char *, num_options + 1);
828 opts->description = NULL;
830 for (i = 0; i < num_options; i++)
831 opts->name[i] = ppc_opts[i].opt;
832 /* The array we return must be NULL terminated. */
833 opts->name[i] = NULL;
836 return opts_and_args;
840 print_ppc_disassembler_options (FILE *stream)
844 fprintf (stream, _("\n\
845 The following PPC specific disassembler options are supported for use with\n\
848 for (col = 0, i = 0; i < ARRAY_SIZE (ppc_opts); i++)
850 col += fprintf (stream, " %s,", ppc_opts[i].opt);
853 fprintf (stream, "\n");
857 fprintf (stream, "\n");