1 /* ppc-dis.c -- Disassemble PowerPC instructions
2 Copyright (C) 1994-2016 Free Software Foundation, Inc.
3 Written by Ian Lance Taylor, Cygnus Support
5 This file is part of the GNU opcodes library.
7 This library is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 3, or (at your option)
12 It is distributed in the hope that it will be useful, but WITHOUT
13 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
14 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
15 License for more details.
17 You should have received a copy of the GNU General Public License
18 along with this file; see the file COPYING. If not, write to the
19 Free Software Foundation, 51 Franklin Street - Fifth Floor, Boston,
20 MA 02110-1301, USA. */
28 #include "opcode/ppc.h"
30 /* This file provides several disassembler functions, all of which use
31 the disassembler interface defined in dis-asm.h. Several functions
32 are provided because this file handles disassembly for the PowerPC
33 in both big and little endian mode and also for the POWER (RS/6000)
35 static int print_insn_powerpc (bfd_vma, struct disassemble_info *, int,
40 /* Stash the result of parsing disassembler_options here. */
44 #define POWERPC_DIALECT(INFO) \
45 (((struct dis_private *) ((INFO)->private_data))->dialect)
53 struct ppc_mopt ppc_opts[] = {
54 { "403", PPC_OPCODE_PPC | PPC_OPCODE_403,
56 { "405", PPC_OPCODE_PPC | PPC_OPCODE_403 | PPC_OPCODE_405,
58 { "440", (PPC_OPCODE_PPC | PPC_OPCODE_BOOKE | PPC_OPCODE_440
59 | PPC_OPCODE_ISEL | PPC_OPCODE_RFMCI),
61 { "464", (PPC_OPCODE_PPC | PPC_OPCODE_BOOKE | PPC_OPCODE_440
62 | PPC_OPCODE_ISEL | PPC_OPCODE_RFMCI),
64 { "476", (PPC_OPCODE_PPC | PPC_OPCODE_ISEL | PPC_OPCODE_440
65 | PPC_OPCODE_476 | PPC_OPCODE_POWER4 | PPC_OPCODE_POWER5),
67 { "601", PPC_OPCODE_PPC | PPC_OPCODE_601,
69 { "603", PPC_OPCODE_PPC,
71 { "604", PPC_OPCODE_PPC,
73 { "620", PPC_OPCODE_PPC | PPC_OPCODE_64,
75 { "7400", PPC_OPCODE_PPC | PPC_OPCODE_ALTIVEC,
77 { "7410", PPC_OPCODE_PPC | PPC_OPCODE_ALTIVEC,
79 { "7450", PPC_OPCODE_PPC | PPC_OPCODE_7450 | PPC_OPCODE_ALTIVEC,
81 { "7455", PPC_OPCODE_PPC | PPC_OPCODE_ALTIVEC,
83 { "750cl", PPC_OPCODE_PPC | PPC_OPCODE_750 | PPC_OPCODE_PPCPS
85 { "821", PPC_OPCODE_PPC | PPC_OPCODE_860,
87 { "850", PPC_OPCODE_PPC | PPC_OPCODE_860,
89 { "860", PPC_OPCODE_PPC | PPC_OPCODE_860,
91 { "a2", (PPC_OPCODE_PPC | PPC_OPCODE_ISEL | PPC_OPCODE_POWER4
92 | PPC_OPCODE_POWER5 | PPC_OPCODE_CACHELCK | PPC_OPCODE_64
95 { "altivec", PPC_OPCODE_PPC,
96 PPC_OPCODE_ALTIVEC | PPC_OPCODE_ALTIVEC2 },
99 { "booke", PPC_OPCODE_PPC | PPC_OPCODE_BOOKE,
101 { "booke32", PPC_OPCODE_PPC | PPC_OPCODE_BOOKE,
103 { "cell", (PPC_OPCODE_PPC | PPC_OPCODE_64 | PPC_OPCODE_POWER4
104 | PPC_OPCODE_CELL | PPC_OPCODE_ALTIVEC),
106 { "com", PPC_OPCODE_COMMON,
108 { "e300", PPC_OPCODE_PPC | PPC_OPCODE_E300,
110 { "e500", (PPC_OPCODE_PPC | PPC_OPCODE_BOOKE | PPC_OPCODE_SPE
111 | PPC_OPCODE_ISEL | PPC_OPCODE_EFS | PPC_OPCODE_BRLOCK
112 | PPC_OPCODE_PMR | PPC_OPCODE_CACHELCK | PPC_OPCODE_RFMCI
115 { "e500mc", (PPC_OPCODE_PPC | PPC_OPCODE_BOOKE | PPC_OPCODE_ISEL
116 | PPC_OPCODE_PMR | PPC_OPCODE_CACHELCK | PPC_OPCODE_RFMCI
117 | PPC_OPCODE_E500MC),
119 { "e500mc64", (PPC_OPCODE_PPC | PPC_OPCODE_BOOKE | PPC_OPCODE_ISEL
120 | PPC_OPCODE_PMR | PPC_OPCODE_CACHELCK | PPC_OPCODE_RFMCI
121 | PPC_OPCODE_E500MC | PPC_OPCODE_64 | PPC_OPCODE_POWER5
122 | PPC_OPCODE_POWER6 | PPC_OPCODE_POWER7),
124 { "e5500", (PPC_OPCODE_PPC | PPC_OPCODE_BOOKE | PPC_OPCODE_ISEL
125 | PPC_OPCODE_PMR | PPC_OPCODE_CACHELCK | PPC_OPCODE_RFMCI
126 | PPC_OPCODE_E500MC | PPC_OPCODE_64 | PPC_OPCODE_POWER4
127 | PPC_OPCODE_POWER5 | PPC_OPCODE_POWER6
128 | PPC_OPCODE_POWER7),
130 { "e6500", (PPC_OPCODE_PPC | PPC_OPCODE_BOOKE | PPC_OPCODE_ISEL
131 | PPC_OPCODE_PMR | PPC_OPCODE_CACHELCK | PPC_OPCODE_RFMCI
132 | PPC_OPCODE_E500MC | PPC_OPCODE_64 | PPC_OPCODE_ALTIVEC
133 | PPC_OPCODE_ALTIVEC2 | PPC_OPCODE_E6500 | PPC_OPCODE_POWER4
134 | PPC_OPCODE_POWER5 | PPC_OPCODE_POWER6 | PPC_OPCODE_POWER7),
136 { "e500x2", (PPC_OPCODE_PPC | PPC_OPCODE_BOOKE | PPC_OPCODE_SPE
137 | PPC_OPCODE_ISEL | PPC_OPCODE_EFS | PPC_OPCODE_BRLOCK
138 | PPC_OPCODE_PMR | PPC_OPCODE_CACHELCK | PPC_OPCODE_RFMCI
141 { "efs", PPC_OPCODE_PPC | PPC_OPCODE_EFS,
143 { "power4", PPC_OPCODE_PPC | PPC_OPCODE_64 | PPC_OPCODE_POWER4,
145 { "power5", (PPC_OPCODE_PPC | PPC_OPCODE_64 | PPC_OPCODE_POWER4
146 | PPC_OPCODE_POWER5),
148 { "power6", (PPC_OPCODE_PPC | PPC_OPCODE_64 | PPC_OPCODE_POWER4
149 | PPC_OPCODE_POWER5 | PPC_OPCODE_POWER6 | PPC_OPCODE_ALTIVEC),
151 { "power7", (PPC_OPCODE_PPC | PPC_OPCODE_ISEL | PPC_OPCODE_64
152 | PPC_OPCODE_POWER4 | PPC_OPCODE_POWER5 | PPC_OPCODE_POWER6
153 | PPC_OPCODE_POWER7 | PPC_OPCODE_ALTIVEC | PPC_OPCODE_VSX),
155 { "power8", (PPC_OPCODE_PPC | PPC_OPCODE_ISEL | PPC_OPCODE_64
156 | PPC_OPCODE_POWER4 | PPC_OPCODE_POWER5 | PPC_OPCODE_POWER6
157 | PPC_OPCODE_POWER7 | PPC_OPCODE_POWER8 | PPC_OPCODE_HTM
158 | PPC_OPCODE_ALTIVEC | PPC_OPCODE_ALTIVEC2 | PPC_OPCODE_VSX),
160 { "power9", (PPC_OPCODE_PPC | PPC_OPCODE_ISEL | PPC_OPCODE_64
161 | PPC_OPCODE_POWER4 | PPC_OPCODE_POWER5 | PPC_OPCODE_POWER6
162 | PPC_OPCODE_POWER7 | PPC_OPCODE_POWER8 | PPC_OPCODE_POWER9
163 | PPC_OPCODE_HTM | PPC_OPCODE_ALTIVEC | PPC_OPCODE_ALTIVEC2
164 | PPC_OPCODE_VSX | PPC_OPCODE_VSX3 ),
166 { "ppc", PPC_OPCODE_PPC,
168 { "ppc32", PPC_OPCODE_PPC,
170 { "ppc64", PPC_OPCODE_PPC | PPC_OPCODE_64,
172 { "ppc64bridge", PPC_OPCODE_PPC | PPC_OPCODE_64_BRIDGE,
174 { "ppcps", PPC_OPCODE_PPC | PPC_OPCODE_PPCPS,
176 { "pwr", PPC_OPCODE_POWER,
178 { "pwr2", PPC_OPCODE_POWER | PPC_OPCODE_POWER2,
180 { "pwr4", PPC_OPCODE_PPC | PPC_OPCODE_64 | PPC_OPCODE_POWER4,
182 { "pwr5", (PPC_OPCODE_PPC | PPC_OPCODE_64 | PPC_OPCODE_POWER4
183 | PPC_OPCODE_POWER5),
185 { "pwr5x", (PPC_OPCODE_PPC | PPC_OPCODE_64 | PPC_OPCODE_POWER4
186 | PPC_OPCODE_POWER5),
188 { "pwr6", (PPC_OPCODE_PPC | PPC_OPCODE_64 | PPC_OPCODE_POWER4
189 | PPC_OPCODE_POWER5 | PPC_OPCODE_POWER6 | PPC_OPCODE_ALTIVEC),
191 { "pwr7", (PPC_OPCODE_PPC | PPC_OPCODE_ISEL | PPC_OPCODE_64
192 | PPC_OPCODE_POWER4 | PPC_OPCODE_POWER5 | PPC_OPCODE_POWER6
193 | PPC_OPCODE_POWER7 | PPC_OPCODE_ALTIVEC | PPC_OPCODE_VSX),
195 { "pwr8", (PPC_OPCODE_PPC | PPC_OPCODE_ISEL | PPC_OPCODE_64
196 | PPC_OPCODE_POWER4 | PPC_OPCODE_POWER5 | PPC_OPCODE_POWER6
197 | PPC_OPCODE_POWER7 | PPC_OPCODE_POWER8 | PPC_OPCODE_HTM
198 | PPC_OPCODE_ALTIVEC | PPC_OPCODE_ALTIVEC2 | PPC_OPCODE_VSX),
200 { "pwr9", (PPC_OPCODE_PPC | PPC_OPCODE_ISEL | PPC_OPCODE_64
201 | PPC_OPCODE_POWER4 | PPC_OPCODE_POWER5 | PPC_OPCODE_POWER6
202 | PPC_OPCODE_POWER7 | PPC_OPCODE_POWER8 | PPC_OPCODE_POWER9
203 | PPC_OPCODE_HTM | PPC_OPCODE_ALTIVEC | PPC_OPCODE_ALTIVEC2
204 | PPC_OPCODE_VSX | PPC_OPCODE_VSX3 ),
206 { "pwrx", PPC_OPCODE_POWER | PPC_OPCODE_POWER2,
208 { "spe", PPC_OPCODE_PPC | PPC_OPCODE_EFS,
210 { "titan", (PPC_OPCODE_PPC | PPC_OPCODE_BOOKE | PPC_OPCODE_PMR
211 | PPC_OPCODE_RFMCI | PPC_OPCODE_TITAN),
213 { "vle", (PPC_OPCODE_PPC | PPC_OPCODE_BOOKE| PPC_OPCODE_SPE
214 | PPC_OPCODE_ISEL | PPC_OPCODE_EFS | PPC_OPCODE_BRLOCK
215 | PPC_OPCODE_PMR | PPC_OPCODE_CACHELCK | PPC_OPCODE_RFMCI
218 { "vsx", PPC_OPCODE_PPC,
219 PPC_OPCODE_VSX | PPC_OPCODE_VSX3 },
220 { "htm", PPC_OPCODE_PPC,
224 /* Switch between Booke and VLE dialects for interlinked dumps. */
226 get_powerpc_dialect (struct disassemble_info *info)
228 ppc_cpu_t dialect = 0;
230 dialect = POWERPC_DIALECT (info);
232 /* Disassemble according to the section headers flags for VLE-mode. */
233 if (dialect & PPC_OPCODE_VLE
234 && info->section->owner != NULL
235 && bfd_get_flavour (info->section->owner) == bfd_target_elf_flavour
236 && elf_object_id (info->section->owner) == PPC32_ELF_DATA
237 && (elf_section_flags (info->section) & SHF_PPC_VLE) != 0)
240 return dialect & ~ PPC_OPCODE_VLE;
243 /* Handle -m and -M options that set cpu type, and .machine arg. */
246 ppc_parse_cpu (ppc_cpu_t ppc_cpu, ppc_cpu_t *sticky, const char *arg)
250 for (i = 0; i < sizeof (ppc_opts) / sizeof (ppc_opts[0]); i++)
251 if (strcmp (ppc_opts[i].opt, arg) == 0)
253 if (ppc_opts[i].sticky)
255 *sticky |= ppc_opts[i].sticky;
256 if ((ppc_cpu & ~*sticky) != 0)
259 ppc_cpu = ppc_opts[i].cpu;
262 if (i >= sizeof (ppc_opts) / sizeof (ppc_opts[0]))
269 /* Determine which set of machines to disassemble for. */
272 powerpc_init_dialect (struct disassemble_info *info)
274 ppc_cpu_t dialect = 0;
275 ppc_cpu_t sticky = 0;
277 struct dis_private *priv = calloc (sizeof (*priv), 1);
284 case bfd_mach_ppc_403:
285 case bfd_mach_ppc_403gc:
286 dialect = ppc_parse_cpu (dialect, &sticky, "403");
288 case bfd_mach_ppc_405:
289 dialect = ppc_parse_cpu (dialect, &sticky, "405");
291 case bfd_mach_ppc_601:
292 dialect = ppc_parse_cpu (dialect, &sticky, "601");
294 case bfd_mach_ppc_a35:
295 case bfd_mach_ppc_rs64ii:
296 case bfd_mach_ppc_rs64iii:
297 dialect = ppc_parse_cpu (dialect, &sticky, "pwr2") | PPC_OPCODE_64;
299 case bfd_mach_ppc_e500:
300 dialect = ppc_parse_cpu (dialect, &sticky, "e500");
302 case bfd_mach_ppc_e500mc:
303 dialect = ppc_parse_cpu (dialect, &sticky, "e500mc");
305 case bfd_mach_ppc_e500mc64:
306 dialect = ppc_parse_cpu (dialect, &sticky, "e500mc64");
308 case bfd_mach_ppc_e5500:
309 dialect = ppc_parse_cpu (dialect, &sticky, "e5500");
311 case bfd_mach_ppc_e6500:
312 dialect = ppc_parse_cpu (dialect, &sticky, "e6500");
314 case bfd_mach_ppc_titan:
315 dialect = ppc_parse_cpu (dialect, &sticky, "titan");
317 case bfd_mach_ppc_vle:
318 dialect = ppc_parse_cpu (dialect, &sticky, "vle");
321 dialect = ppc_parse_cpu (dialect, &sticky, "power9") | PPC_OPCODE_ANY;
324 arg = info->disassembler_options;
327 ppc_cpu_t new_cpu = 0;
328 char *end = strchr (arg, ',');
333 if ((new_cpu = ppc_parse_cpu (dialect, &sticky, arg)) != 0)
335 else if (strcmp (arg, "32") == 0)
336 dialect &= ~(ppc_cpu_t) PPC_OPCODE_64;
337 else if (strcmp (arg, "64") == 0)
338 dialect |= PPC_OPCODE_64;
340 fprintf (stderr, _("warning: ignoring unknown -M%s option\n"), arg);
347 info->private_data = priv;
348 POWERPC_DIALECT(info) = dialect;
351 #define PPC_OPCD_SEGS 64
352 static unsigned short powerpc_opcd_indices[PPC_OPCD_SEGS+1];
353 #define VLE_OPCD_SEGS 32
354 static unsigned short vle_opcd_indices[VLE_OPCD_SEGS+1];
356 /* Calculate opcode table indices to speed up disassembly,
360 disassemble_init_powerpc (struct disassemble_info *info)
365 if (powerpc_opcd_indices[PPC_OPCD_SEGS] == 0)
368 i = powerpc_num_opcodes;
371 unsigned op = PPC_OP (powerpc_opcodes[i].opcode);
373 powerpc_opcd_indices[op] = i;
376 last = powerpc_num_opcodes;
377 for (i = PPC_OPCD_SEGS; i > 0; --i)
379 if (powerpc_opcd_indices[i] == 0)
380 powerpc_opcd_indices[i] = last;
381 last = powerpc_opcd_indices[i];
387 unsigned op = VLE_OP (vle_opcodes[i].opcode, vle_opcodes[i].mask);
388 unsigned seg = VLE_OP_TO_SEG (op);
390 vle_opcd_indices[seg] = i;
393 last = vle_num_opcodes;
394 for (i = VLE_OPCD_SEGS; i > 0; --i)
396 if (vle_opcd_indices[i] == 0)
397 vle_opcd_indices[i] = last;
398 last = vle_opcd_indices[i];
402 if (info->arch == bfd_arch_powerpc)
403 powerpc_init_dialect (info);
406 /* Print a big endian PowerPC instruction. */
409 print_insn_big_powerpc (bfd_vma memaddr, struct disassemble_info *info)
411 return print_insn_powerpc (memaddr, info, 1, get_powerpc_dialect (info));
414 /* Print a little endian PowerPC instruction. */
417 print_insn_little_powerpc (bfd_vma memaddr, struct disassemble_info *info)
419 return print_insn_powerpc (memaddr, info, 0, get_powerpc_dialect (info));
422 /* Print a POWER (RS/6000) instruction. */
425 print_insn_rs6000 (bfd_vma memaddr, struct disassemble_info *info)
427 return print_insn_powerpc (memaddr, info, 1, PPC_OPCODE_POWER);
430 /* Extract the operand value from the PowerPC or POWER instruction. */
433 operand_value_powerpc (const struct powerpc_operand *operand,
434 unsigned long insn, ppc_cpu_t dialect)
438 /* Extract the value from the instruction. */
439 if (operand->extract)
440 value = (*operand->extract) (insn, dialect, &invalid);
443 if (operand->shift >= 0)
444 value = (insn >> operand->shift) & operand->bitm;
446 value = (insn << -operand->shift) & operand->bitm;
447 if ((operand->flags & PPC_OPERAND_SIGNED) != 0)
449 /* BITM is always some number of zeros followed by some
450 number of ones, followed by some number of zeros. */
451 unsigned long top = operand->bitm;
452 /* top & -top gives the rightmost 1 bit, so this
453 fills in any trailing zeros. */
454 top |= (top & -top) - 1;
456 value = (value ^ top) - top;
463 /* Determine whether the optional operand(s) should be printed. */
466 skip_optional_operands (const unsigned char *opindex,
467 unsigned long insn, ppc_cpu_t dialect)
469 const struct powerpc_operand *operand;
471 for (; *opindex != 0; opindex++)
473 operand = &powerpc_operands[*opindex];
474 if ((operand->flags & PPC_OPERAND_NEXT) != 0
475 || ((operand->flags & PPC_OPERAND_OPTIONAL) != 0
476 && operand_value_powerpc (operand, insn, dialect) !=
477 ppc_optional_operand_value (operand)))
484 /* Find a match for INSN in the opcode table, given machine DIALECT.
485 A DIALECT of -1 is special, matching all machine opcode variations. */
487 static const struct powerpc_opcode *
488 lookup_powerpc (unsigned long insn, ppc_cpu_t dialect)
490 const struct powerpc_opcode *opcode;
491 const struct powerpc_opcode *opcode_end;
494 /* Get the major opcode of the instruction. */
497 /* Find the first match in the opcode table for this major opcode. */
498 opcode_end = powerpc_opcodes + powerpc_opcd_indices[op + 1];
499 for (opcode = powerpc_opcodes + powerpc_opcd_indices[op];
503 const unsigned char *opindex;
504 const struct powerpc_operand *operand;
507 if ((insn & opcode->mask) != opcode->opcode
508 || (dialect != (ppc_cpu_t) -1
509 && ((opcode->flags & dialect) == 0
510 || (opcode->deprecated & dialect) != 0)))
513 /* Check validity of operands. */
515 for (opindex = opcode->operands; *opindex != 0; opindex++)
517 operand = powerpc_operands + *opindex;
518 if (operand->extract)
519 (*operand->extract) (insn, dialect, &invalid);
530 /* Find a match for INSN in the VLE opcode table. */
532 static const struct powerpc_opcode *
533 lookup_vle (unsigned long insn)
535 const struct powerpc_opcode *opcode;
536 const struct powerpc_opcode *opcode_end;
540 if (op >= 0x20 && op <= 0x37)
542 /* This insn has a 4-bit opcode. */
545 seg = VLE_OP_TO_SEG (op);
547 /* Find the first match in the opcode table for this major opcode. */
548 opcode_end = vle_opcodes + vle_opcd_indices[seg + 1];
549 for (opcode = vle_opcodes + vle_opcd_indices[seg];
553 unsigned long table_opcd = opcode->opcode;
554 unsigned long table_mask = opcode->mask;
555 bfd_boolean table_op_is_short = PPC_OP_SE_VLE(table_mask);
557 const unsigned char *opindex;
558 const struct powerpc_operand *operand;
562 if (table_op_is_short)
564 if ((insn2 & table_mask) != table_opcd)
567 /* Check validity of operands. */
569 for (opindex = opcode->operands; *opindex != 0; ++opindex)
571 operand = powerpc_operands + *opindex;
572 if (operand->extract)
573 (*operand->extract) (insn, (ppc_cpu_t)0, &invalid);
584 /* Print a PowerPC or POWER instruction. */
587 print_insn_powerpc (bfd_vma memaddr,
588 struct disassemble_info *info,
595 const struct powerpc_opcode *opcode;
596 bfd_boolean insn_is_short;
598 status = (*info->read_memory_func) (memaddr, buffer, 4, info);
601 /* The final instruction may be a 2-byte VLE insn. */
602 if ((dialect & PPC_OPCODE_VLE) != 0)
604 /* Clear buffer so unused bytes will not have garbage in them. */
605 buffer[0] = buffer[1] = buffer[2] = buffer[3] = 0;
606 status = (*info->read_memory_func) (memaddr, buffer, 2, info);
609 (*info->memory_error_func) (status, memaddr, info);
615 (*info->memory_error_func) (status, memaddr, info);
621 insn = bfd_getb32 (buffer);
623 insn = bfd_getl32 (buffer);
625 /* Get the major opcode of the insn. */
627 insn_is_short = FALSE;
628 if ((dialect & PPC_OPCODE_VLE) != 0)
630 opcode = lookup_vle (insn);
632 insn_is_short = PPC_OP_SE_VLE(opcode->mask);
635 opcode = lookup_powerpc (insn, dialect);
636 if (opcode == NULL && (dialect & PPC_OPCODE_ANY) != 0)
637 opcode = lookup_powerpc (insn, (ppc_cpu_t) -1);
641 const unsigned char *opindex;
642 const struct powerpc_operand *operand;
647 if (opcode->operands[0] != 0)
648 (*info->fprintf_func) (info->stream, "%-7s ", opcode->name);
650 (*info->fprintf_func) (info->stream, "%s", opcode->name);
653 /* The operands will be fetched out of the 16-bit instruction. */
656 /* Now extract and print the operands. */
660 for (opindex = opcode->operands; *opindex != 0; opindex++)
664 operand = powerpc_operands + *opindex;
666 /* Operands that are marked FAKE are simply ignored. We
667 already made sure that the extract function considered
668 the instruction to be valid. */
669 if ((operand->flags & PPC_OPERAND_FAKE) != 0)
672 /* If all of the optional operands have the value zero,
673 then don't print any of them. */
674 if ((operand->flags & PPC_OPERAND_OPTIONAL) != 0)
676 if (skip_optional < 0)
677 skip_optional = skip_optional_operands (opindex, insn,
683 value = operand_value_powerpc (operand, insn, dialect);
687 (*info->fprintf_func) (info->stream, ",");
691 /* Print the operand as directed by the flags. */
692 if ((operand->flags & PPC_OPERAND_GPR) != 0
693 || ((operand->flags & PPC_OPERAND_GPR_0) != 0 && value != 0))
694 (*info->fprintf_func) (info->stream, "r%ld", value);
695 else if ((operand->flags & PPC_OPERAND_FPR) != 0)
696 (*info->fprintf_func) (info->stream, "f%ld", value);
697 else if ((operand->flags & PPC_OPERAND_VR) != 0)
698 (*info->fprintf_func) (info->stream, "v%ld", value);
699 else if ((operand->flags & PPC_OPERAND_VSR) != 0)
700 (*info->fprintf_func) (info->stream, "vs%ld", value);
701 else if ((operand->flags & PPC_OPERAND_RELATIVE) != 0)
702 (*info->print_address_func) (memaddr + value, info);
703 else if ((operand->flags & PPC_OPERAND_ABSOLUTE) != 0)
704 (*info->print_address_func) ((bfd_vma) value & 0xffffffff, info);
705 else if ((operand->flags & PPC_OPERAND_FSL) != 0)
706 (*info->fprintf_func) (info->stream, "fsl%ld", value);
707 else if ((operand->flags & PPC_OPERAND_FCR) != 0)
708 (*info->fprintf_func) (info->stream, "fcr%ld", value);
709 else if ((operand->flags & PPC_OPERAND_UDI) != 0)
710 (*info->fprintf_func) (info->stream, "%ld", value);
711 else if ((operand->flags & PPC_OPERAND_CR_REG) != 0
712 && (((dialect & PPC_OPCODE_PPC) != 0)
713 || ((dialect & PPC_OPCODE_VLE) != 0)))
714 (*info->fprintf_func) (info->stream, "cr%ld", value);
715 else if (((operand->flags & PPC_OPERAND_CR_BIT) != 0)
716 && (((dialect & PPC_OPCODE_PPC) != 0)
717 || ((dialect & PPC_OPCODE_VLE) != 0)))
719 static const char *cbnames[4] = { "lt", "gt", "eq", "so" };
725 (*info->fprintf_func) (info->stream, "4*cr%d+", cr);
727 (*info->fprintf_func) (info->stream, "%s", cbnames[cc]);
730 (*info->fprintf_func) (info->stream, "%d", (int) value);
734 (*info->fprintf_func) (info->stream, ")");
738 if ((operand->flags & PPC_OPERAND_PARENS) == 0)
742 (*info->fprintf_func) (info->stream, "(");
747 /* We have found and printed an instruction.
748 If it was a short VLE instruction we have more to do. */
755 /* Otherwise, return. */
759 /* We could not find a match. */
760 (*info->fprintf_func) (info->stream, ".long 0x%lx", insn);
766 print_ppc_disassembler_options (FILE *stream)
770 fprintf (stream, _("\n\
771 The following PPC specific disassembler options are supported for use with\n\
774 for (col = 0, i = 0; i < sizeof (ppc_opts) / sizeof (ppc_opts[0]); i++)
776 col += fprintf (stream, " %s,", ppc_opts[i].opt);
779 fprintf (stream, "\n");
783 fprintf (stream, " 32, 64\n");