1 /* ppc-dis.c -- Disassemble PowerPC instructions
2 Copyright (C) 1994-2015 Free Software Foundation, Inc.
3 Written by Ian Lance Taylor, Cygnus Support
5 This file is part of the GNU opcodes library.
7 This library is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 3, or (at your option)
12 It is distributed in the hope that it will be useful, but WITHOUT
13 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
14 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
15 License for more details.
17 You should have received a copy of the GNU General Public License
18 along with this file; see the file COPYING. If not, write to the
19 Free Software Foundation, 51 Franklin Street - Fifth Floor, Boston,
20 MA 02110-1301, USA. */
28 #include "opcode/ppc.h"
30 /* This file provides several disassembler functions, all of which use
31 the disassembler interface defined in dis-asm.h. Several functions
32 are provided because this file handles disassembly for the PowerPC
33 in both big and little endian mode and also for the POWER (RS/6000)
35 static int print_insn_powerpc (bfd_vma, struct disassemble_info *, int,
40 /* Stash the result of parsing disassembler_options here. */
44 #define POWERPC_DIALECT(INFO) \
45 (((struct dis_private *) ((INFO)->private_data))->dialect)
53 struct ppc_mopt ppc_opts[] = {
54 { "403", (PPC_OPCODE_PPC | PPC_OPCODE_403),
56 { "405", (PPC_OPCODE_PPC | PPC_OPCODE_403 | PPC_OPCODE_405),
58 { "440", (PPC_OPCODE_PPC | PPC_OPCODE_BOOKE | PPC_OPCODE_440
59 | PPC_OPCODE_ISEL | PPC_OPCODE_RFMCI),
61 { "464", (PPC_OPCODE_PPC | PPC_OPCODE_BOOKE | PPC_OPCODE_440
62 | PPC_OPCODE_ISEL | PPC_OPCODE_RFMCI),
64 { "476", (PPC_OPCODE_PPC | PPC_OPCODE_ISEL | PPC_OPCODE_440
65 | PPC_OPCODE_476 | PPC_OPCODE_POWER4 | PPC_OPCODE_POWER5),
67 { "601", (PPC_OPCODE_PPC | PPC_OPCODE_601),
69 { "603", (PPC_OPCODE_PPC),
71 { "604", (PPC_OPCODE_PPC),
73 { "620", (PPC_OPCODE_PPC | PPC_OPCODE_64),
75 { "7400", (PPC_OPCODE_PPC | PPC_OPCODE_ALTIVEC),
77 { "7410", (PPC_OPCODE_PPC | PPC_OPCODE_ALTIVEC),
79 { "7450", (PPC_OPCODE_PPC | PPC_OPCODE_ALTIVEC),
81 { "7455", (PPC_OPCODE_PPC | PPC_OPCODE_ALTIVEC),
83 { "750cl", (PPC_OPCODE_PPC | PPC_OPCODE_PPCPS)
85 { "a2", (PPC_OPCODE_PPC | PPC_OPCODE_ISEL | PPC_OPCODE_POWER4
86 | PPC_OPCODE_POWER5 | PPC_OPCODE_CACHELCK | PPC_OPCODE_64
89 { "altivec", (PPC_OPCODE_PPC),
90 PPC_OPCODE_ALTIVEC | PPC_OPCODE_ALTIVEC2 },
93 { "booke", (PPC_OPCODE_PPC | PPC_OPCODE_BOOKE),
95 { "booke32", (PPC_OPCODE_PPC | PPC_OPCODE_BOOKE),
97 { "cell", (PPC_OPCODE_PPC | PPC_OPCODE_64 | PPC_OPCODE_POWER4
98 | PPC_OPCODE_CELL | PPC_OPCODE_ALTIVEC),
100 { "com", (PPC_OPCODE_COMMON),
102 { "e300", (PPC_OPCODE_PPC | PPC_OPCODE_E300),
104 { "e500", (PPC_OPCODE_PPC | PPC_OPCODE_BOOKE | PPC_OPCODE_SPE
105 | PPC_OPCODE_ISEL | PPC_OPCODE_EFS | PPC_OPCODE_BRLOCK
106 | PPC_OPCODE_PMR | PPC_OPCODE_CACHELCK | PPC_OPCODE_RFMCI
109 { "e500mc", (PPC_OPCODE_PPC | PPC_OPCODE_BOOKE | PPC_OPCODE_ISEL
110 | PPC_OPCODE_PMR | PPC_OPCODE_CACHELCK | PPC_OPCODE_RFMCI
111 | PPC_OPCODE_E500MC),
113 { "e500mc64", (PPC_OPCODE_PPC | PPC_OPCODE_BOOKE | PPC_OPCODE_ISEL
114 | PPC_OPCODE_PMR | PPC_OPCODE_CACHELCK | PPC_OPCODE_RFMCI
115 | PPC_OPCODE_E500MC | PPC_OPCODE_64 | PPC_OPCODE_POWER5
116 | PPC_OPCODE_POWER6 | PPC_OPCODE_POWER7),
118 { "e5500", (PPC_OPCODE_PPC | PPC_OPCODE_BOOKE | PPC_OPCODE_ISEL
119 | PPC_OPCODE_PMR | PPC_OPCODE_CACHELCK | PPC_OPCODE_RFMCI
120 | PPC_OPCODE_E500MC | PPC_OPCODE_64 | PPC_OPCODE_POWER4
121 | PPC_OPCODE_POWER5 | PPC_OPCODE_POWER6
122 | PPC_OPCODE_POWER7),
124 { "e6500", (PPC_OPCODE_PPC | PPC_OPCODE_BOOKE | PPC_OPCODE_ISEL
125 | PPC_OPCODE_PMR | PPC_OPCODE_CACHELCK | PPC_OPCODE_RFMCI
126 | PPC_OPCODE_E500MC | PPC_OPCODE_64 | PPC_OPCODE_ALTIVEC
127 | PPC_OPCODE_ALTIVEC2 | PPC_OPCODE_E6500 | PPC_OPCODE_POWER4
128 | PPC_OPCODE_POWER5 | PPC_OPCODE_POWER6 | PPC_OPCODE_POWER7),
130 { "e500x2", (PPC_OPCODE_PPC | PPC_OPCODE_BOOKE | PPC_OPCODE_SPE
131 | PPC_OPCODE_ISEL | PPC_OPCODE_EFS | PPC_OPCODE_BRLOCK
132 | PPC_OPCODE_PMR | PPC_OPCODE_CACHELCK | PPC_OPCODE_RFMCI
135 { "efs", (PPC_OPCODE_PPC | PPC_OPCODE_EFS),
137 { "power4", (PPC_OPCODE_PPC | PPC_OPCODE_64 | PPC_OPCODE_POWER4),
139 { "power5", (PPC_OPCODE_PPC | PPC_OPCODE_64 | PPC_OPCODE_POWER4
140 | PPC_OPCODE_POWER5),
142 { "power6", (PPC_OPCODE_PPC | PPC_OPCODE_64 | PPC_OPCODE_POWER4
143 | PPC_OPCODE_POWER5 | PPC_OPCODE_POWER6 | PPC_OPCODE_ALTIVEC),
145 { "power7", (PPC_OPCODE_PPC | PPC_OPCODE_ISEL | PPC_OPCODE_64
146 | PPC_OPCODE_POWER4 | PPC_OPCODE_POWER5 | PPC_OPCODE_POWER6
147 | PPC_OPCODE_POWER7 | PPC_OPCODE_ALTIVEC | PPC_OPCODE_VSX),
149 { "power8", (PPC_OPCODE_PPC | PPC_OPCODE_ISEL | PPC_OPCODE_64
150 | PPC_OPCODE_POWER4 | PPC_OPCODE_POWER5 | PPC_OPCODE_POWER6
151 | PPC_OPCODE_POWER7 | PPC_OPCODE_POWER8 | PPC_OPCODE_HTM
152 | PPC_OPCODE_ALTIVEC | PPC_OPCODE_ALTIVEC2 | PPC_OPCODE_VSX),
154 { "ppc", (PPC_OPCODE_PPC),
156 { "ppc32", (PPC_OPCODE_PPC),
158 { "ppc64", (PPC_OPCODE_PPC | PPC_OPCODE_64),
160 { "ppc64bridge", (PPC_OPCODE_PPC | PPC_OPCODE_64_BRIDGE),
162 { "ppcps", (PPC_OPCODE_PPC | PPC_OPCODE_PPCPS),
164 { "pwr", (PPC_OPCODE_POWER),
166 { "pwr2", (PPC_OPCODE_POWER | PPC_OPCODE_POWER2),
168 { "pwr4", (PPC_OPCODE_PPC | PPC_OPCODE_64 | PPC_OPCODE_POWER4),
170 { "pwr5", (PPC_OPCODE_PPC | PPC_OPCODE_64 | PPC_OPCODE_POWER4
171 | PPC_OPCODE_POWER5),
173 { "pwr5x", (PPC_OPCODE_PPC | PPC_OPCODE_64 | PPC_OPCODE_POWER4
174 | PPC_OPCODE_POWER5),
176 { "pwr6", (PPC_OPCODE_PPC | PPC_OPCODE_64 | PPC_OPCODE_POWER4
177 | PPC_OPCODE_POWER5 | PPC_OPCODE_POWER6 | PPC_OPCODE_ALTIVEC),
179 { "pwr7", (PPC_OPCODE_PPC | PPC_OPCODE_ISEL | PPC_OPCODE_64
180 | PPC_OPCODE_POWER4 | PPC_OPCODE_POWER5 | PPC_OPCODE_POWER6
181 | PPC_OPCODE_POWER7 | PPC_OPCODE_ALTIVEC | PPC_OPCODE_VSX),
183 { "pwr8", (PPC_OPCODE_PPC | PPC_OPCODE_ISEL | PPC_OPCODE_64
184 | PPC_OPCODE_POWER4 | PPC_OPCODE_POWER5 | PPC_OPCODE_POWER6
185 | PPC_OPCODE_POWER7 | PPC_OPCODE_POWER8 | PPC_OPCODE_HTM
186 | PPC_OPCODE_ALTIVEC | PPC_OPCODE_ALTIVEC2 | PPC_OPCODE_VSX),
188 { "pwrx", (PPC_OPCODE_POWER | PPC_OPCODE_POWER2),
190 { "spe", (PPC_OPCODE_PPC | PPC_OPCODE_EFS),
192 { "titan", (PPC_OPCODE_PPC | PPC_OPCODE_BOOKE | PPC_OPCODE_PMR
193 | PPC_OPCODE_RFMCI | PPC_OPCODE_TITAN),
195 { "vle", (PPC_OPCODE_PPC | PPC_OPCODE_ISEL | PPC_OPCODE_VLE),
197 { "vsx", (PPC_OPCODE_PPC),
199 { "htm", (PPC_OPCODE_PPC),
203 /* Switch between Booke and VLE dialects for interlinked dumps. */
205 get_powerpc_dialect (struct disassemble_info *info)
207 ppc_cpu_t dialect = 0;
209 dialect = POWERPC_DIALECT (info);
211 /* Disassemble according to the section headers flags for VLE-mode. */
212 if (dialect & PPC_OPCODE_VLE
213 && info->section->owner != NULL
214 && bfd_get_flavour (info->section->owner) == bfd_target_elf_flavour
215 && elf_object_id (info->section->owner) == PPC32_ELF_DATA
216 && (elf_section_flags (info->section) & SHF_PPC_VLE) != 0)
219 return dialect & ~ PPC_OPCODE_VLE;
222 /* Handle -m and -M options that set cpu type, and .machine arg. */
225 ppc_parse_cpu (ppc_cpu_t ppc_cpu, ppc_cpu_t *sticky, const char *arg)
229 for (i = 0; i < sizeof (ppc_opts) / sizeof (ppc_opts[0]); i++)
230 if (strcmp (ppc_opts[i].opt, arg) == 0)
232 if (ppc_opts[i].sticky)
234 *sticky |= ppc_opts[i].sticky;
235 if ((ppc_cpu & ~*sticky) != 0)
238 ppc_cpu = ppc_opts[i].cpu;
241 if (i >= sizeof (ppc_opts) / sizeof (ppc_opts[0]))
248 /* Determine which set of machines to disassemble for. */
251 powerpc_init_dialect (struct disassemble_info *info)
253 ppc_cpu_t dialect = 0;
254 ppc_cpu_t sticky = 0;
256 struct dis_private *priv = calloc (sizeof (*priv), 1);
263 case bfd_mach_ppc_403:
264 case bfd_mach_ppc_403gc:
265 dialect = ppc_parse_cpu (dialect, &sticky, "403");
267 case bfd_mach_ppc_405:
268 dialect = ppc_parse_cpu (dialect, &sticky, "405");
270 case bfd_mach_ppc_601:
271 dialect = ppc_parse_cpu (dialect, &sticky, "601");
273 case bfd_mach_ppc_a35:
274 case bfd_mach_ppc_rs64ii:
275 case bfd_mach_ppc_rs64iii:
276 dialect = ppc_parse_cpu (dialect, &sticky, "pwr2") | PPC_OPCODE_64;
278 case bfd_mach_ppc_e500:
279 dialect = ppc_parse_cpu (dialect, &sticky, "e500");
281 case bfd_mach_ppc_e500mc:
282 dialect = ppc_parse_cpu (dialect, &sticky, "e500mc");
284 case bfd_mach_ppc_e500mc64:
285 dialect = ppc_parse_cpu (dialect, &sticky, "e500mc64");
287 case bfd_mach_ppc_e5500:
288 dialect = ppc_parse_cpu (dialect, &sticky, "e5500");
290 case bfd_mach_ppc_e6500:
291 dialect = ppc_parse_cpu (dialect, &sticky, "e6500");
293 case bfd_mach_ppc_titan:
294 dialect = ppc_parse_cpu (dialect, &sticky, "titan");
296 case bfd_mach_ppc_vle:
297 dialect = ppc_parse_cpu (dialect, &sticky, "vle");
300 dialect = ppc_parse_cpu (dialect, &sticky, "power8") | PPC_OPCODE_ANY;
303 arg = info->disassembler_options;
306 ppc_cpu_t new_cpu = 0;
307 char *end = strchr (arg, ',');
312 if ((new_cpu = ppc_parse_cpu (dialect, &sticky, arg)) != 0)
314 else if (strcmp (arg, "32") == 0)
315 dialect &= ~(ppc_cpu_t) PPC_OPCODE_64;
316 else if (strcmp (arg, "64") == 0)
317 dialect |= PPC_OPCODE_64;
319 fprintf (stderr, _("warning: ignoring unknown -M%s option\n"), arg);
326 info->private_data = priv;
327 POWERPC_DIALECT(info) = dialect;
330 #define PPC_OPCD_SEGS 64
331 static unsigned short powerpc_opcd_indices[PPC_OPCD_SEGS+1];
332 #define VLE_OPCD_SEGS 32
333 static unsigned short vle_opcd_indices[VLE_OPCD_SEGS+1];
335 /* Calculate opcode table indices to speed up disassembly,
339 disassemble_init_powerpc (struct disassemble_info *info)
344 if (powerpc_opcd_indices[PPC_OPCD_SEGS] == 0)
347 i = powerpc_num_opcodes;
350 unsigned op = PPC_OP (powerpc_opcodes[i].opcode);
352 powerpc_opcd_indices[op] = i;
355 last = powerpc_num_opcodes;
356 for (i = PPC_OPCD_SEGS; i > 0; --i)
358 if (powerpc_opcd_indices[i] == 0)
359 powerpc_opcd_indices[i] = last;
360 last = powerpc_opcd_indices[i];
366 unsigned op = VLE_OP (vle_opcodes[i].opcode, vle_opcodes[i].mask);
367 unsigned seg = VLE_OP_TO_SEG (op);
369 vle_opcd_indices[seg] = i;
372 last = vle_num_opcodes;
373 for (i = VLE_OPCD_SEGS; i > 0; --i)
375 if (vle_opcd_indices[i] == 0)
376 vle_opcd_indices[i] = last;
377 last = vle_opcd_indices[i];
381 if (info->arch == bfd_arch_powerpc)
382 powerpc_init_dialect (info);
385 /* Print a big endian PowerPC instruction. */
388 print_insn_big_powerpc (bfd_vma memaddr, struct disassemble_info *info)
390 return print_insn_powerpc (memaddr, info, 1, get_powerpc_dialect (info));
393 /* Print a little endian PowerPC instruction. */
396 print_insn_little_powerpc (bfd_vma memaddr, struct disassemble_info *info)
398 return print_insn_powerpc (memaddr, info, 0, get_powerpc_dialect (info));
401 /* Print a POWER (RS/6000) instruction. */
404 print_insn_rs6000 (bfd_vma memaddr, struct disassemble_info *info)
406 return print_insn_powerpc (memaddr, info, 1, PPC_OPCODE_POWER);
409 /* Extract the operand value from the PowerPC or POWER instruction. */
412 operand_value_powerpc (const struct powerpc_operand *operand,
413 unsigned long insn, ppc_cpu_t dialect)
417 /* Extract the value from the instruction. */
418 if (operand->extract)
419 value = (*operand->extract) (insn, dialect, &invalid);
422 if (operand->shift >= 0)
423 value = (insn >> operand->shift) & operand->bitm;
425 value = (insn << -operand->shift) & operand->bitm;
426 if ((operand->flags & PPC_OPERAND_SIGNED) != 0)
428 /* BITM is always some number of zeros followed by some
429 number of ones, followed by some number of zeros. */
430 unsigned long top = operand->bitm;
431 /* top & -top gives the rightmost 1 bit, so this
432 fills in any trailing zeros. */
433 top |= (top & -top) - 1;
435 value = (value ^ top) - top;
442 /* Determine whether the optional operand(s) should be printed. */
445 skip_optional_operands (const unsigned char *opindex,
446 unsigned long insn, ppc_cpu_t dialect)
448 const struct powerpc_operand *operand;
450 for (; *opindex != 0; opindex++)
452 operand = &powerpc_operands[*opindex];
453 if ((operand->flags & PPC_OPERAND_NEXT) != 0
454 || ((operand->flags & PPC_OPERAND_OPTIONAL) != 0
455 && operand_value_powerpc (operand, insn, dialect) !=
456 ppc_optional_operand_value (operand)))
463 /* Find a match for INSN in the opcode table, given machine DIALECT.
464 A DIALECT of -1 is special, matching all machine opcode variations. */
466 static const struct powerpc_opcode *
467 lookup_powerpc (unsigned long insn, ppc_cpu_t dialect)
469 const struct powerpc_opcode *opcode;
470 const struct powerpc_opcode *opcode_end;
473 /* Get the major opcode of the instruction. */
476 /* Find the first match in the opcode table for this major opcode. */
477 opcode_end = powerpc_opcodes + powerpc_opcd_indices[op + 1];
478 for (opcode = powerpc_opcodes + powerpc_opcd_indices[op];
482 const unsigned char *opindex;
483 const struct powerpc_operand *operand;
486 if ((insn & opcode->mask) != opcode->opcode
487 || (dialect != (ppc_cpu_t) -1
488 && ((opcode->flags & dialect) == 0
489 || (opcode->deprecated & dialect) != 0)))
492 /* Check validity of operands. */
494 for (opindex = opcode->operands; *opindex != 0; opindex++)
496 operand = powerpc_operands + *opindex;
497 if (operand->extract)
498 (*operand->extract) (insn, dialect, &invalid);
509 /* Find a match for INSN in the VLE opcode table. */
511 static const struct powerpc_opcode *
512 lookup_vle (unsigned long insn)
514 const struct powerpc_opcode *opcode;
515 const struct powerpc_opcode *opcode_end;
519 if (op >= 0x20 && op <= 0x37)
521 /* This insn has a 4-bit opcode. */
524 seg = VLE_OP_TO_SEG (op);
526 /* Find the first match in the opcode table for this major opcode. */
527 opcode_end = vle_opcodes + vle_opcd_indices[seg + 1];
528 for (opcode = vle_opcodes + vle_opcd_indices[seg];
532 unsigned long table_opcd = opcode->opcode;
533 unsigned long table_mask = opcode->mask;
534 bfd_boolean table_op_is_short = PPC_OP_SE_VLE(table_mask);
536 const unsigned char *opindex;
537 const struct powerpc_operand *operand;
541 if (table_op_is_short)
543 if ((insn2 & table_mask) != table_opcd)
546 /* Check validity of operands. */
548 for (opindex = opcode->operands; *opindex != 0; ++opindex)
550 operand = powerpc_operands + *opindex;
551 if (operand->extract)
552 (*operand->extract) (insn, (ppc_cpu_t)0, &invalid);
563 /* Print a PowerPC or POWER instruction. */
566 print_insn_powerpc (bfd_vma memaddr,
567 struct disassemble_info *info,
574 const struct powerpc_opcode *opcode;
575 bfd_boolean insn_is_short;
577 status = (*info->read_memory_func) (memaddr, buffer, 4, info);
580 /* The final instruction may be a 2-byte VLE insn. */
581 if ((dialect & PPC_OPCODE_VLE) != 0)
583 /* Clear buffer so unused bytes will not have garbage in them. */
584 buffer[0] = buffer[1] = buffer[2] = buffer[3] = 0;
585 status = (*info->read_memory_func) (memaddr, buffer, 2, info);
588 (*info->memory_error_func) (status, memaddr, info);
594 (*info->memory_error_func) (status, memaddr, info);
600 insn = bfd_getb32 (buffer);
602 insn = bfd_getl32 (buffer);
604 /* Get the major opcode of the insn. */
606 insn_is_short = FALSE;
607 if ((dialect & PPC_OPCODE_VLE) != 0)
609 opcode = lookup_vle (insn);
611 insn_is_short = PPC_OP_SE_VLE(opcode->mask);
614 opcode = lookup_powerpc (insn, dialect);
615 if (opcode == NULL && (dialect & PPC_OPCODE_ANY) != 0)
616 opcode = lookup_powerpc (insn, (ppc_cpu_t) -1);
620 const unsigned char *opindex;
621 const struct powerpc_operand *operand;
626 if (opcode->operands[0] != 0)
627 (*info->fprintf_func) (info->stream, "%-7s ", opcode->name);
629 (*info->fprintf_func) (info->stream, "%s", opcode->name);
632 /* The operands will be fetched out of the 16-bit instruction. */
635 /* Now extract and print the operands. */
639 for (opindex = opcode->operands; *opindex != 0; opindex++)
643 operand = powerpc_operands + *opindex;
645 /* Operands that are marked FAKE are simply ignored. We
646 already made sure that the extract function considered
647 the instruction to be valid. */
648 if ((operand->flags & PPC_OPERAND_FAKE) != 0)
651 /* If all of the optional operands have the value zero,
652 then don't print any of them. */
653 if ((operand->flags & PPC_OPERAND_OPTIONAL) != 0)
655 if (skip_optional < 0)
656 skip_optional = skip_optional_operands (opindex, insn,
662 value = operand_value_powerpc (operand, insn, dialect);
666 (*info->fprintf_func) (info->stream, ",");
670 /* Print the operand as directed by the flags. */
671 if ((operand->flags & PPC_OPERAND_GPR) != 0
672 || ((operand->flags & PPC_OPERAND_GPR_0) != 0 && value != 0))
673 (*info->fprintf_func) (info->stream, "r%ld", value);
674 else if ((operand->flags & PPC_OPERAND_FPR) != 0)
675 (*info->fprintf_func) (info->stream, "f%ld", value);
676 else if ((operand->flags & PPC_OPERAND_VR) != 0)
677 (*info->fprintf_func) (info->stream, "v%ld", value);
678 else if ((operand->flags & PPC_OPERAND_VSR) != 0)
679 (*info->fprintf_func) (info->stream, "vs%ld", value);
680 else if ((operand->flags & PPC_OPERAND_RELATIVE) != 0)
681 (*info->print_address_func) (memaddr + value, info);
682 else if ((operand->flags & PPC_OPERAND_ABSOLUTE) != 0)
683 (*info->print_address_func) ((bfd_vma) value & 0xffffffff, info);
684 else if ((operand->flags & PPC_OPERAND_FSL) != 0)
685 (*info->fprintf_func) (info->stream, "fsl%ld", value);
686 else if ((operand->flags & PPC_OPERAND_FCR) != 0)
687 (*info->fprintf_func) (info->stream, "fcr%ld", value);
688 else if ((operand->flags & PPC_OPERAND_UDI) != 0)
689 (*info->fprintf_func) (info->stream, "%ld", value);
690 else if ((operand->flags & PPC_OPERAND_CR_REG) != 0
691 && (((dialect & PPC_OPCODE_PPC) != 0)
692 || ((dialect & PPC_OPCODE_VLE) != 0)))
693 (*info->fprintf_func) (info->stream, "cr%ld", value);
694 else if (((operand->flags & PPC_OPERAND_CR_BIT) != 0)
695 && (((dialect & PPC_OPCODE_PPC) != 0)
696 || ((dialect & PPC_OPCODE_VLE) != 0)))
698 static const char *cbnames[4] = { "lt", "gt", "eq", "so" };
704 (*info->fprintf_func) (info->stream, "4*cr%d+", cr);
706 (*info->fprintf_func) (info->stream, "%s", cbnames[cc]);
709 (*info->fprintf_func) (info->stream, "%d", (int) value);
713 (*info->fprintf_func) (info->stream, ")");
717 if ((operand->flags & PPC_OPERAND_PARENS) == 0)
721 (*info->fprintf_func) (info->stream, "(");
726 /* We have found and printed an instruction.
727 If it was a short VLE instruction we have more to do. */
734 /* Otherwise, return. */
738 /* We could not find a match. */
739 (*info->fprintf_func) (info->stream, ".long 0x%lx", insn);
745 print_ppc_disassembler_options (FILE *stream)
749 fprintf (stream, _("\n\
750 The following PPC specific disassembler options are supported for use with\n\
753 for (col = 0, i = 0; i < sizeof (ppc_opts) / sizeof (ppc_opts[0]); i++)
755 col += fprintf (stream, " %s,", ppc_opts[i].opt);
758 fprintf (stream, "\n");
762 fprintf (stream, " 32, 64\n");