1 /* ppc-dis.c -- Disassemble PowerPC instructions
2 Copyright 1994, 1995, 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007,
3 2008, 2009, 2010, 2011, 2012 Free Software Foundation, Inc.
4 Written by Ian Lance Taylor, Cygnus Support
6 This file is part of the GNU opcodes library.
8 This library is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 3, or (at your option)
13 It is distributed in the hope that it will be useful, but WITHOUT
14 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
15 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
16 License for more details.
18 You should have received a copy of the GNU General Public License
19 along with this file; see the file COPYING. If not, write to the
20 Free Software Foundation, 51 Franklin Street - Fifth Floor, Boston,
21 MA 02110-1301, USA. */
29 #include "opcode/ppc.h"
31 /* This file provides several disassembler functions, all of which use
32 the disassembler interface defined in dis-asm.h. Several functions
33 are provided because this file handles disassembly for the PowerPC
34 in both big and little endian mode and also for the POWER (RS/6000)
36 static int print_insn_powerpc (bfd_vma, struct disassemble_info *, int,
41 /* Stash the result of parsing disassembler_options here. */
45 #define POWERPC_DIALECT(INFO) \
46 (((struct dis_private *) ((INFO)->private_data))->dialect)
54 struct ppc_mopt ppc_opts[] = {
55 { "403", (PPC_OPCODE_PPC | PPC_OPCODE_403),
57 { "405", (PPC_OPCODE_PPC | PPC_OPCODE_403 | PPC_OPCODE_405),
59 { "440", (PPC_OPCODE_PPC | PPC_OPCODE_BOOKE | PPC_OPCODE_440
60 | PPC_OPCODE_ISEL | PPC_OPCODE_RFMCI),
62 { "464", (PPC_OPCODE_PPC | PPC_OPCODE_BOOKE | PPC_OPCODE_440
63 | PPC_OPCODE_ISEL | PPC_OPCODE_RFMCI),
65 { "476", (PPC_OPCODE_PPC | PPC_OPCODE_ISEL | PPC_OPCODE_440
66 | PPC_OPCODE_476 | PPC_OPCODE_POWER4 | PPC_OPCODE_POWER5),
68 { "601", (PPC_OPCODE_PPC | PPC_OPCODE_601),
70 { "603", (PPC_OPCODE_PPC),
72 { "604", (PPC_OPCODE_PPC),
74 { "620", (PPC_OPCODE_PPC | PPC_OPCODE_64),
76 { "7400", (PPC_OPCODE_PPC | PPC_OPCODE_ALTIVEC),
78 { "7410", (PPC_OPCODE_PPC | PPC_OPCODE_ALTIVEC),
80 { "7450", (PPC_OPCODE_PPC | PPC_OPCODE_ALTIVEC),
82 { "7455", (PPC_OPCODE_PPC | PPC_OPCODE_ALTIVEC),
84 { "750cl", (PPC_OPCODE_PPC | PPC_OPCODE_PPCPS)
86 { "a2", (PPC_OPCODE_PPC | PPC_OPCODE_ISEL | PPC_OPCODE_POWER4
87 | PPC_OPCODE_POWER5 | PPC_OPCODE_CACHELCK | PPC_OPCODE_64
90 { "altivec", (PPC_OPCODE_PPC),
91 PPC_OPCODE_ALTIVEC | PPC_OPCODE_ALTIVEC2 },
94 { "booke", (PPC_OPCODE_PPC | PPC_OPCODE_BOOKE),
96 { "booke32", (PPC_OPCODE_PPC | PPC_OPCODE_BOOKE),
98 { "cell", (PPC_OPCODE_PPC | PPC_OPCODE_64 | PPC_OPCODE_POWER4
99 | PPC_OPCODE_CELL | PPC_OPCODE_ALTIVEC),
101 { "com", (PPC_OPCODE_COMMON),
103 { "e300", (PPC_OPCODE_PPC | PPC_OPCODE_E300),
105 { "e500", (PPC_OPCODE_PPC | PPC_OPCODE_BOOKE | PPC_OPCODE_SPE
106 | PPC_OPCODE_ISEL | PPC_OPCODE_EFS | PPC_OPCODE_BRLOCK
107 | PPC_OPCODE_PMR | PPC_OPCODE_CACHELCK | PPC_OPCODE_RFMCI
110 { "e500mc", (PPC_OPCODE_PPC | PPC_OPCODE_BOOKE | PPC_OPCODE_ISEL
111 | PPC_OPCODE_PMR | PPC_OPCODE_CACHELCK | PPC_OPCODE_RFMCI
112 | PPC_OPCODE_E500MC),
114 { "e500mc64", (PPC_OPCODE_PPC | PPC_OPCODE_BOOKE | PPC_OPCODE_ISEL
115 | PPC_OPCODE_PMR | PPC_OPCODE_CACHELCK | PPC_OPCODE_RFMCI
116 | PPC_OPCODE_E500MC | PPC_OPCODE_64 | PPC_OPCODE_POWER5
117 | PPC_OPCODE_POWER6 | PPC_OPCODE_POWER7),
119 { "e5500", (PPC_OPCODE_PPC | PPC_OPCODE_BOOKE | PPC_OPCODE_ISEL
120 | PPC_OPCODE_PMR | PPC_OPCODE_CACHELCK | PPC_OPCODE_RFMCI
121 | PPC_OPCODE_E500MC | PPC_OPCODE_64 | PPC_OPCODE_POWER4
122 | PPC_OPCODE_POWER5 | PPC_OPCODE_POWER6
123 | PPC_OPCODE_POWER7),
125 { "e6500", (PPC_OPCODE_PPC | PPC_OPCODE_BOOKE | PPC_OPCODE_ISEL
126 | PPC_OPCODE_PMR | PPC_OPCODE_CACHELCK | PPC_OPCODE_RFMCI
127 | PPC_OPCODE_E500MC | PPC_OPCODE_64 | PPC_OPCODE_ALTIVEC
128 | PPC_OPCODE_ALTIVEC2 | PPC_OPCODE_E6500 | PPC_OPCODE_POWER4
129 | PPC_OPCODE_POWER5 | PPC_OPCODE_POWER6 | PPC_OPCODE_POWER7),
131 { "e500x2", (PPC_OPCODE_PPC | PPC_OPCODE_BOOKE | PPC_OPCODE_SPE
132 | PPC_OPCODE_ISEL | PPC_OPCODE_EFS | PPC_OPCODE_BRLOCK
133 | PPC_OPCODE_PMR | PPC_OPCODE_CACHELCK | PPC_OPCODE_RFMCI
136 { "efs", (PPC_OPCODE_PPC | PPC_OPCODE_EFS),
138 { "power4", (PPC_OPCODE_PPC | PPC_OPCODE_64 | PPC_OPCODE_POWER4),
140 { "power5", (PPC_OPCODE_PPC | PPC_OPCODE_64 | PPC_OPCODE_POWER4
141 | PPC_OPCODE_POWER5),
143 { "power6", (PPC_OPCODE_PPC | PPC_OPCODE_64 | PPC_OPCODE_POWER4
144 | PPC_OPCODE_POWER5 | PPC_OPCODE_POWER6 | PPC_OPCODE_ALTIVEC),
146 { "power7", (PPC_OPCODE_PPC | PPC_OPCODE_ISEL | PPC_OPCODE_64
147 | PPC_OPCODE_POWER4 | PPC_OPCODE_POWER5 | PPC_OPCODE_POWER6
148 | PPC_OPCODE_POWER7 | PPC_OPCODE_ALTIVEC | PPC_OPCODE_VSX),
150 { "ppc", (PPC_OPCODE_PPC),
152 { "ppc32", (PPC_OPCODE_PPC),
154 { "ppc64", (PPC_OPCODE_PPC | PPC_OPCODE_64),
156 { "ppc64bridge", (PPC_OPCODE_PPC | PPC_OPCODE_64_BRIDGE),
158 { "ppcps", (PPC_OPCODE_PPC | PPC_OPCODE_PPCPS),
160 { "pwr", (PPC_OPCODE_POWER),
162 { "pwr2", (PPC_OPCODE_POWER | PPC_OPCODE_POWER2),
164 { "pwr4", (PPC_OPCODE_PPC | PPC_OPCODE_64 | PPC_OPCODE_POWER4),
166 { "pwr5", (PPC_OPCODE_PPC | PPC_OPCODE_64 | PPC_OPCODE_POWER4
167 | PPC_OPCODE_POWER5),
169 { "pwr5x", (PPC_OPCODE_PPC | PPC_OPCODE_64 | PPC_OPCODE_POWER4
170 | PPC_OPCODE_POWER5),
172 { "pwr6", (PPC_OPCODE_PPC | PPC_OPCODE_64 | PPC_OPCODE_POWER4
173 | PPC_OPCODE_POWER5 | PPC_OPCODE_POWER6 | PPC_OPCODE_ALTIVEC),
175 { "pwr7", (PPC_OPCODE_PPC | PPC_OPCODE_ISEL | PPC_OPCODE_64
176 | PPC_OPCODE_POWER4 | PPC_OPCODE_POWER5 | PPC_OPCODE_POWER6
177 | PPC_OPCODE_POWER7 | PPC_OPCODE_ALTIVEC | PPC_OPCODE_VSX),
179 { "pwrx", (PPC_OPCODE_POWER | PPC_OPCODE_POWER2),
181 { "spe", (PPC_OPCODE_PPC | PPC_OPCODE_EFS),
183 { "titan", (PPC_OPCODE_PPC | PPC_OPCODE_BOOKE | PPC_OPCODE_PMR
184 | PPC_OPCODE_RFMCI | PPC_OPCODE_TITAN),
186 { "vle", (PPC_OPCODE_PPC | PPC_OPCODE_ISEL | PPC_OPCODE_VLE),
188 { "vsx", (PPC_OPCODE_PPC),
192 /* Switch between Booke and VLE dialects for interlinked dumps. */
194 get_powerpc_dialect (struct disassemble_info *info)
196 ppc_cpu_t dialect = 0;
198 dialect = POWERPC_DIALECT (info);
200 /* Disassemble according to the section headers flags for VLE-mode. */
201 if (dialect & PPC_OPCODE_VLE
202 && info->section->owner != NULL
203 && bfd_get_flavour (info->section->owner) == bfd_target_elf_flavour
204 && elf_object_id (info->section->owner) == PPC32_ELF_DATA
205 && (elf_section_flags (info->section) & SHF_PPC_VLE) != 0)
208 return dialect & ~ PPC_OPCODE_VLE;
211 /* Handle -m and -M options that set cpu type, and .machine arg. */
214 ppc_parse_cpu (ppc_cpu_t ppc_cpu, ppc_cpu_t *sticky, const char *arg)
218 for (i = 0; i < sizeof (ppc_opts) / sizeof (ppc_opts[0]); i++)
219 if (strcmp (ppc_opts[i].opt, arg) == 0)
221 if (ppc_opts[i].sticky)
223 *sticky |= ppc_opts[i].sticky;
224 if ((ppc_cpu & ~*sticky) != 0)
227 ppc_cpu = ppc_opts[i].cpu;
230 if (i >= sizeof (ppc_opts) / sizeof (ppc_opts[0]))
237 /* Determine which set of machines to disassemble for. */
240 powerpc_init_dialect (struct disassemble_info *info)
242 ppc_cpu_t dialect = 0;
243 ppc_cpu_t sticky = 0;
245 struct dis_private *priv = calloc (sizeof (*priv), 1);
252 case bfd_mach_ppc_403:
253 case bfd_mach_ppc_403gc:
254 dialect = (PPC_OPCODE_PPC | PPC_OPCODE_403);
256 case bfd_mach_ppc_405:
257 dialect = (PPC_OPCODE_PPC | PPC_OPCODE_403 | PPC_OPCODE_405);
259 case bfd_mach_ppc_601:
260 dialect = (PPC_OPCODE_PPC | PPC_OPCODE_601);
262 case bfd_mach_ppc_a35:
263 case bfd_mach_ppc_rs64ii:
264 case bfd_mach_ppc_rs64iii:
265 dialect = (PPC_OPCODE_POWER | PPC_OPCODE_POWER2 | PPC_OPCODE_64);
267 case bfd_mach_ppc_e500:
268 dialect = (PPC_OPCODE_PPC | PPC_OPCODE_BOOKE | PPC_OPCODE_SPE
269 | PPC_OPCODE_ISEL | PPC_OPCODE_EFS | PPC_OPCODE_BRLOCK
270 | PPC_OPCODE_PMR | PPC_OPCODE_CACHELCK | PPC_OPCODE_RFMCI
273 case bfd_mach_ppc_e500mc:
274 dialect = (PPC_OPCODE_PPC | PPC_OPCODE_BOOKE | PPC_OPCODE_ISEL
275 | PPC_OPCODE_PMR | PPC_OPCODE_CACHELCK | PPC_OPCODE_RFMCI
276 | PPC_OPCODE_E500MC);
278 case bfd_mach_ppc_e500mc64:
279 dialect = (PPC_OPCODE_PPC | PPC_OPCODE_BOOKE | PPC_OPCODE_ISEL
280 | PPC_OPCODE_PMR | PPC_OPCODE_CACHELCK | PPC_OPCODE_RFMCI
281 | PPC_OPCODE_E500MC | PPC_OPCODE_64 | PPC_OPCODE_POWER5
282 | PPC_OPCODE_POWER6 | PPC_OPCODE_POWER7);
284 case bfd_mach_ppc_e5500:
285 dialect = (PPC_OPCODE_PPC | PPC_OPCODE_BOOKE | PPC_OPCODE_ISEL
286 | PPC_OPCODE_PMR | PPC_OPCODE_CACHELCK | PPC_OPCODE_RFMCI
287 | PPC_OPCODE_E500MC | PPC_OPCODE_64 | PPC_OPCODE_POWER4
288 | PPC_OPCODE_POWER5 | PPC_OPCODE_POWER6
289 | PPC_OPCODE_POWER7);
291 case bfd_mach_ppc_e6500:
292 dialect = (PPC_OPCODE_PPC | PPC_OPCODE_BOOKE | PPC_OPCODE_ISEL
293 | PPC_OPCODE_PMR | PPC_OPCODE_CACHELCK | PPC_OPCODE_RFMCI
294 | PPC_OPCODE_E500MC | PPC_OPCODE_64 | PPC_OPCODE_ALTIVEC
295 | PPC_OPCODE_ALTIVEC2 | PPC_OPCODE_E6500 | PPC_OPCODE_POWER4
296 | PPC_OPCODE_POWER5 | PPC_OPCODE_POWER6 | PPC_OPCODE_POWER7);
298 case bfd_mach_ppc_titan:
299 dialect = (PPC_OPCODE_PPC | PPC_OPCODE_BOOKE | PPC_OPCODE_PMR
300 | PPC_OPCODE_RFMCI | PPC_OPCODE_TITAN);
302 case bfd_mach_ppc_vle:
303 dialect = (PPC_OPCODE_PPC | PPC_OPCODE_ISEL | PPC_OPCODE_VLE);
306 dialect = (PPC_OPCODE_PPC | PPC_OPCODE_ISEL | PPC_OPCODE_64
307 | PPC_OPCODE_POWER4 | PPC_OPCODE_POWER5 | PPC_OPCODE_POWER6
308 | PPC_OPCODE_POWER7 | PPC_OPCODE_ALTIVEC | PPC_OPCODE_VSX
312 arg = info->disassembler_options;
315 ppc_cpu_t new_cpu = 0;
316 char *end = strchr (arg, ',');
321 if ((new_cpu = ppc_parse_cpu (dialect, &sticky, arg)) != 0)
323 else if (strcmp (arg, "32") == 0)
324 dialect &= ~(ppc_cpu_t) PPC_OPCODE_64;
325 else if (strcmp (arg, "64") == 0)
326 dialect |= PPC_OPCODE_64;
328 fprintf (stderr, _("warning: ignoring unknown -M%s option\n"), arg);
335 info->private_data = priv;
336 POWERPC_DIALECT(info) = dialect;
339 #define PPC_OPCD_SEGS 64
340 static unsigned short powerpc_opcd_indices[PPC_OPCD_SEGS+1];
341 #define VLE_OPCD_SEGS 32
342 static unsigned short vle_opcd_indices[VLE_OPCD_SEGS+1];
344 /* Calculate opcode table indices to speed up disassembly,
348 disassemble_init_powerpc (struct disassemble_info *info)
353 i = powerpc_num_opcodes;
356 unsigned op = PPC_OP (powerpc_opcodes[i].opcode);
358 powerpc_opcd_indices[op] = i;
361 last = powerpc_num_opcodes;
362 for (i = PPC_OPCD_SEGS; i > 0; --i)
364 if (powerpc_opcd_indices[i] == 0)
365 powerpc_opcd_indices[i] = last;
366 last = powerpc_opcd_indices[i];
372 unsigned op = VLE_OP (vle_opcodes[i].opcode, vle_opcodes[i].mask);
373 unsigned seg = VLE_OP_TO_SEG (op);
375 vle_opcd_indices[seg] = i;
378 last = vle_num_opcodes;
379 for (i = VLE_OPCD_SEGS; i > 0; --i)
381 if (vle_opcd_indices[i] == 0)
382 vle_opcd_indices[i] = last;
383 last = vle_opcd_indices[i];
386 if (info->arch == bfd_arch_powerpc)
387 powerpc_init_dialect (info);
390 /* Print a big endian PowerPC instruction. */
393 print_insn_big_powerpc (bfd_vma memaddr, struct disassemble_info *info)
395 return print_insn_powerpc (memaddr, info, 1, get_powerpc_dialect (info));
398 /* Print a little endian PowerPC instruction. */
401 print_insn_little_powerpc (bfd_vma memaddr, struct disassemble_info *info)
403 return print_insn_powerpc (memaddr, info, 0, get_powerpc_dialect (info));
406 /* Print a POWER (RS/6000) instruction. */
409 print_insn_rs6000 (bfd_vma memaddr, struct disassemble_info *info)
411 return print_insn_powerpc (memaddr, info, 1, PPC_OPCODE_POWER);
414 /* Extract the operand value from the PowerPC or POWER instruction. */
417 operand_value_powerpc (const struct powerpc_operand *operand,
418 unsigned long insn, ppc_cpu_t dialect)
422 /* Extract the value from the instruction. */
423 if (operand->extract)
424 value = (*operand->extract) (insn, dialect, &invalid);
427 if (operand->shift >= 0)
428 value = (insn >> operand->shift) & operand->bitm;
430 value = (insn << -operand->shift) & operand->bitm;
431 if ((operand->flags & PPC_OPERAND_SIGNED) != 0)
433 /* BITM is always some number of zeros followed by some
434 number of ones, followed by some number of zeros. */
435 unsigned long top = operand->bitm;
436 /* top & -top gives the rightmost 1 bit, so this
437 fills in any trailing zeros. */
438 top |= (top & -top) - 1;
440 value = (value ^ top) - top;
447 /* Determine whether the optional operand(s) should be printed. */
450 skip_optional_operands (const unsigned char *opindex,
451 unsigned long insn, ppc_cpu_t dialect)
453 const struct powerpc_operand *operand;
455 for (; *opindex != 0; opindex++)
457 operand = &powerpc_operands[*opindex];
458 if ((operand->flags & PPC_OPERAND_NEXT) != 0
459 || ((operand->flags & PPC_OPERAND_OPTIONAL) != 0
460 && operand_value_powerpc (operand, insn, dialect) != 0))
467 /* Find a match for INSN in the opcode table, given machine DIALECT.
468 A DIALECT of -1 is special, matching all machine opcode variations. */
470 static const struct powerpc_opcode *
471 lookup_powerpc (unsigned long insn, ppc_cpu_t dialect)
473 const struct powerpc_opcode *opcode;
474 const struct powerpc_opcode *opcode_end;
477 /* Get the major opcode of the instruction. */
480 /* Find the first match in the opcode table for this major opcode. */
481 opcode_end = powerpc_opcodes + powerpc_opcd_indices[op + 1];
482 for (opcode = powerpc_opcodes + powerpc_opcd_indices[op];
486 const unsigned char *opindex;
487 const struct powerpc_operand *operand;
490 if ((insn & opcode->mask) != opcode->opcode
491 || (dialect != (ppc_cpu_t) -1
492 && ((opcode->flags & dialect) == 0
493 || (opcode->deprecated & dialect) != 0)))
496 /* Check validity of operands. */
498 for (opindex = opcode->operands; *opindex != 0; opindex++)
500 operand = powerpc_operands + *opindex;
501 if (operand->extract)
502 (*operand->extract) (insn, dialect, &invalid);
513 /* Find a match for INSN in the VLE opcode table. */
515 static const struct powerpc_opcode *
516 lookup_vle (unsigned long insn)
518 const struct powerpc_opcode *opcode;
519 const struct powerpc_opcode *opcode_end;
523 if (op >= 0x20 && op <= 0x37)
525 /* This insn has a 4-bit opcode. */
528 seg = VLE_OP_TO_SEG (op);
530 /* Find the first match in the opcode table for this major opcode. */
531 opcode_end = vle_opcodes + vle_opcd_indices[seg + 1];
532 for (opcode = vle_opcodes + vle_opcd_indices[seg];
536 unsigned long table_opcd = opcode->opcode;
537 unsigned long table_mask = opcode->mask;
538 bfd_boolean table_op_is_short = PPC_OP_SE_VLE(table_mask);
540 const unsigned char *opindex;
541 const struct powerpc_operand *operand;
545 if (table_op_is_short)
547 if ((insn2 & table_mask) != table_opcd)
550 /* Check validity of operands. */
552 for (opindex = opcode->operands; *opindex != 0; ++opindex)
554 operand = powerpc_operands + *opindex;
555 if (operand->extract)
556 (*operand->extract) (insn, (ppc_cpu_t)0, &invalid);
567 /* Print a PowerPC or POWER instruction. */
570 print_insn_powerpc (bfd_vma memaddr,
571 struct disassemble_info *info,
578 const struct powerpc_opcode *opcode;
579 bfd_boolean insn_is_short;
581 status = (*info->read_memory_func) (memaddr, buffer, 4, info);
584 /* The final instruction may be a 2-byte VLE insn. */
585 if ((dialect & PPC_OPCODE_VLE) != 0)
587 /* Clear buffer so unused bytes will not have garbage in them. */
588 buffer[0] = buffer[1] = buffer[2] = buffer[3] = 0;
589 status = (*info->read_memory_func) (memaddr, buffer, 2, info);
592 (*info->memory_error_func) (status, memaddr, info);
598 (*info->memory_error_func) (status, memaddr, info);
604 insn = bfd_getb32 (buffer);
606 insn = bfd_getl32 (buffer);
608 /* Get the major opcode of the insn. */
610 insn_is_short = FALSE;
611 if ((dialect & PPC_OPCODE_VLE) != 0)
613 opcode = lookup_vle (insn);
615 insn_is_short = PPC_OP_SE_VLE(opcode->mask);
618 opcode = lookup_powerpc (insn, dialect);
619 if (opcode == NULL && (dialect & PPC_OPCODE_ANY) != 0)
620 opcode = lookup_powerpc (insn, (ppc_cpu_t) -1);
624 const unsigned char *opindex;
625 const struct powerpc_operand *operand;
630 if (opcode->operands[0] != 0)
631 (*info->fprintf_func) (info->stream, "%-7s ", opcode->name);
633 (*info->fprintf_func) (info->stream, "%s", opcode->name);
636 /* The operands will be fetched out of the 16-bit instruction. */
639 /* Now extract and print the operands. */
643 for (opindex = opcode->operands; *opindex != 0; opindex++)
647 operand = powerpc_operands + *opindex;
649 /* Operands that are marked FAKE are simply ignored. We
650 already made sure that the extract function considered
651 the instruction to be valid. */
652 if ((operand->flags & PPC_OPERAND_FAKE) != 0)
655 /* If all of the optional operands have the value zero,
656 then don't print any of them. */
657 if ((operand->flags & PPC_OPERAND_OPTIONAL) != 0)
659 if (skip_optional < 0)
660 skip_optional = skip_optional_operands (opindex, insn,
666 value = operand_value_powerpc (operand, insn, dialect);
670 (*info->fprintf_func) (info->stream, ",");
674 /* Print the operand as directed by the flags. */
675 if ((operand->flags & PPC_OPERAND_GPR) != 0
676 || ((operand->flags & PPC_OPERAND_GPR_0) != 0 && value != 0))
677 (*info->fprintf_func) (info->stream, "r%ld", value);
678 else if ((operand->flags & PPC_OPERAND_FPR) != 0)
679 (*info->fprintf_func) (info->stream, "f%ld", value);
680 else if ((operand->flags & PPC_OPERAND_VR) != 0)
681 (*info->fprintf_func) (info->stream, "v%ld", value);
682 else if ((operand->flags & PPC_OPERAND_VSR) != 0)
683 (*info->fprintf_func) (info->stream, "vs%ld", value);
684 else if ((operand->flags & PPC_OPERAND_RELATIVE) != 0)
685 (*info->print_address_func) (memaddr + value, info);
686 else if ((operand->flags & PPC_OPERAND_ABSOLUTE) != 0)
687 (*info->print_address_func) ((bfd_vma) value & 0xffffffff, info);
688 else if ((operand->flags & PPC_OPERAND_FSL) != 0)
689 (*info->fprintf_func) (info->stream, "fsl%ld", value);
690 else if ((operand->flags & PPC_OPERAND_FCR) != 0)
691 (*info->fprintf_func) (info->stream, "fcr%ld", value);
692 else if ((operand->flags & PPC_OPERAND_UDI) != 0)
693 (*info->fprintf_func) (info->stream, "%ld", value);
694 else if ((operand->flags & PPC_OPERAND_CR_REG) != 0
695 && (((dialect & PPC_OPCODE_PPC) != 0)
696 || ((dialect & PPC_OPCODE_VLE) != 0)))
697 (*info->fprintf_func) (info->stream, "cr%ld", value);
698 else if (((operand->flags & PPC_OPERAND_CR_BIT) != 0)
699 && (((dialect & PPC_OPCODE_PPC) != 0)
700 || ((dialect & PPC_OPCODE_VLE) != 0)))
702 static const char *cbnames[4] = { "lt", "gt", "eq", "so" };
708 (*info->fprintf_func) (info->stream, "4*cr%d+", cr);
710 (*info->fprintf_func) (info->stream, "%s", cbnames[cc]);
713 (*info->fprintf_func) (info->stream, "%d", (int) value);
717 (*info->fprintf_func) (info->stream, ")");
721 if ((operand->flags & PPC_OPERAND_PARENS) == 0)
725 (*info->fprintf_func) (info->stream, "(");
730 /* We have found and printed an instruction.
731 If it was a short VLE instruction we have more to do. */
738 /* Otherwise, return. */
742 /* We could not find a match. */
743 (*info->fprintf_func) (info->stream, ".long 0x%lx", insn);
749 print_ppc_disassembler_options (FILE *stream)
753 fprintf (stream, _("\n\
754 The following PPC specific disassembler options are supported for use with\n\
757 for (col = 0, i = 0; i < sizeof (ppc_opts) / sizeof (ppc_opts[0]); i++)
759 col += fprintf (stream, " %s,", ppc_opts[i].opt);
762 fprintf (stream, "\n");
766 fprintf (stream, " 32, 64\n");