1 /* ppc-dis.c -- Disassemble PowerPC instructions
2 Copyright (C) 1994-2019 Free Software Foundation, Inc.
3 Written by Ian Lance Taylor, Cygnus Support
5 This file is part of the GNU opcodes library.
7 This library is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 3, or (at your option)
12 It is distributed in the hope that it will be useful, but WITHOUT
13 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
14 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
15 License for more details.
17 You should have received a copy of the GNU General Public License
18 along with this file; see the file COPYING. If not, write to the
19 Free Software Foundation, 51 Franklin Street - Fifth Floor, Boston,
20 MA 02110-1301, USA. */
24 #include "disassemble.h"
28 #include "opcode/ppc.h"
29 #include "libiberty.h"
31 /* This file provides several disassembler functions, all of which use
32 the disassembler interface defined in dis-asm.h. Several functions
33 are provided because this file handles disassembly for the PowerPC
34 in both big and little endian mode and also for the POWER (RS/6000)
36 static int print_insn_powerpc (bfd_vma, struct disassemble_info *, int,
41 /* Stash the result of parsing disassembler_options here. */
45 #define POWERPC_DIALECT(INFO) \
46 (((struct dis_private *) ((INFO)->private_data))->dialect)
49 /* Option string, without -m or -M prefix. */
51 /* CPU option flags. */
53 /* Flags that should stay on, even when combined with another cpu
54 option. This should only be used for generic options like
55 "-many" or "-maltivec" where it is reasonable to add some
56 capability to another cpu selection. The added flags are sticky
57 so that, for example, "-many -me500" and "-me500 -many" result in
58 the same assembler or disassembler behaviour. Do not use
59 "sticky" for specific cpus, as this will prevent that cpu's flags
60 from overriding the defaults set in powerpc_init_dialect or a
65 struct ppc_mopt ppc_opts[] = {
66 { "403", PPC_OPCODE_PPC | PPC_OPCODE_403,
68 { "405", PPC_OPCODE_PPC | PPC_OPCODE_403 | PPC_OPCODE_405,
70 { "440", (PPC_OPCODE_PPC | PPC_OPCODE_BOOKE | PPC_OPCODE_440
71 | PPC_OPCODE_ISEL | PPC_OPCODE_RFMCI),
73 { "464", (PPC_OPCODE_PPC | PPC_OPCODE_BOOKE | PPC_OPCODE_440
74 | PPC_OPCODE_ISEL | PPC_OPCODE_RFMCI),
76 { "476", (PPC_OPCODE_PPC | PPC_OPCODE_ISEL | PPC_OPCODE_476
77 | PPC_OPCODE_POWER4 | PPC_OPCODE_POWER5),
79 { "601", PPC_OPCODE_PPC | PPC_OPCODE_601,
81 { "603", PPC_OPCODE_PPC,
83 { "604", PPC_OPCODE_PPC,
85 { "620", PPC_OPCODE_PPC | PPC_OPCODE_64,
87 { "7400", PPC_OPCODE_PPC | PPC_OPCODE_ALTIVEC,
89 { "7410", PPC_OPCODE_PPC | PPC_OPCODE_ALTIVEC,
91 { "7450", PPC_OPCODE_PPC | PPC_OPCODE_7450 | PPC_OPCODE_ALTIVEC,
93 { "7455", PPC_OPCODE_PPC | PPC_OPCODE_ALTIVEC,
95 { "750cl", PPC_OPCODE_PPC | PPC_OPCODE_750 | PPC_OPCODE_PPCPS
97 { "gekko", PPC_OPCODE_PPC | PPC_OPCODE_750 | PPC_OPCODE_PPCPS
99 { "broadway", PPC_OPCODE_PPC | PPC_OPCODE_750 | PPC_OPCODE_PPCPS
101 { "821", PPC_OPCODE_PPC | PPC_OPCODE_860,
103 { "850", PPC_OPCODE_PPC | PPC_OPCODE_860,
105 { "860", PPC_OPCODE_PPC | PPC_OPCODE_860,
107 { "a2", (PPC_OPCODE_PPC | PPC_OPCODE_ISEL | PPC_OPCODE_POWER4
108 | PPC_OPCODE_POWER5 | PPC_OPCODE_CACHELCK | PPC_OPCODE_64
111 { "altivec", PPC_OPCODE_PPC,
112 PPC_OPCODE_ALTIVEC },
113 { "any", PPC_OPCODE_PPC,
115 { "booke", PPC_OPCODE_PPC | PPC_OPCODE_BOOKE,
117 { "booke32", PPC_OPCODE_PPC | PPC_OPCODE_BOOKE,
119 { "cell", (PPC_OPCODE_PPC | PPC_OPCODE_64 | PPC_OPCODE_POWER4
120 | PPC_OPCODE_CELL | PPC_OPCODE_ALTIVEC),
122 { "com", PPC_OPCODE_COMMON,
124 { "e200z4", (PPC_OPCODE_PPC | PPC_OPCODE_BOOKE| PPC_OPCODE_SPE
125 | PPC_OPCODE_ISEL | PPC_OPCODE_EFS | PPC_OPCODE_BRLOCK
126 | PPC_OPCODE_PMR | PPC_OPCODE_CACHELCK | PPC_OPCODE_RFMCI
127 | PPC_OPCODE_E500 | PPC_OPCODE_VLE | PPC_OPCODE_E200Z4
128 | PPC_OPCODE_EFS2 | PPC_OPCODE_LSP),
130 { "e300", PPC_OPCODE_PPC | PPC_OPCODE_E300,
132 { "e500", (PPC_OPCODE_PPC | PPC_OPCODE_BOOKE | PPC_OPCODE_SPE
133 | PPC_OPCODE_ISEL | PPC_OPCODE_EFS | PPC_OPCODE_BRLOCK
134 | PPC_OPCODE_PMR | PPC_OPCODE_CACHELCK | PPC_OPCODE_RFMCI
137 { "e500mc", (PPC_OPCODE_PPC | PPC_OPCODE_BOOKE | PPC_OPCODE_ISEL
138 | PPC_OPCODE_PMR | PPC_OPCODE_CACHELCK | PPC_OPCODE_RFMCI
139 | PPC_OPCODE_E500MC),
141 { "e500mc64", (PPC_OPCODE_PPC | PPC_OPCODE_BOOKE | PPC_OPCODE_ISEL
142 | PPC_OPCODE_PMR | PPC_OPCODE_CACHELCK | PPC_OPCODE_RFMCI
143 | PPC_OPCODE_E500MC | PPC_OPCODE_64 | PPC_OPCODE_POWER5
144 | PPC_OPCODE_POWER6 | PPC_OPCODE_POWER7),
146 { "e5500", (PPC_OPCODE_PPC | PPC_OPCODE_BOOKE | PPC_OPCODE_ISEL
147 | PPC_OPCODE_PMR | PPC_OPCODE_CACHELCK | PPC_OPCODE_RFMCI
148 | PPC_OPCODE_E500MC | PPC_OPCODE_64 | PPC_OPCODE_POWER4
149 | PPC_OPCODE_POWER5 | PPC_OPCODE_POWER6 | PPC_OPCODE_POWER7),
151 { "e6500", (PPC_OPCODE_PPC | PPC_OPCODE_BOOKE | PPC_OPCODE_ISEL
152 | PPC_OPCODE_PMR | PPC_OPCODE_CACHELCK | PPC_OPCODE_RFMCI
153 | PPC_OPCODE_E500MC | PPC_OPCODE_64 | PPC_OPCODE_ALTIVEC
154 | PPC_OPCODE_E6500 | PPC_OPCODE_TMR | PPC_OPCODE_POWER4
155 | PPC_OPCODE_POWER5 | PPC_OPCODE_POWER6 | PPC_OPCODE_POWER7),
157 { "e500x2", (PPC_OPCODE_PPC | PPC_OPCODE_BOOKE | PPC_OPCODE_SPE
158 | PPC_OPCODE_ISEL | PPC_OPCODE_EFS | PPC_OPCODE_BRLOCK
159 | PPC_OPCODE_PMR | PPC_OPCODE_CACHELCK | PPC_OPCODE_RFMCI
162 { "efs", PPC_OPCODE_PPC | PPC_OPCODE_EFS,
164 { "efs2", PPC_OPCODE_PPC | PPC_OPCODE_EFS | PPC_OPCODE_EFS2,
166 { "power4", PPC_OPCODE_PPC | PPC_OPCODE_64 | PPC_OPCODE_POWER4,
168 { "power5", (PPC_OPCODE_PPC | PPC_OPCODE_64 | PPC_OPCODE_POWER4
169 | PPC_OPCODE_POWER5),
171 { "power6", (PPC_OPCODE_PPC | PPC_OPCODE_64 | PPC_OPCODE_POWER4
172 | PPC_OPCODE_POWER5 | PPC_OPCODE_POWER6 | PPC_OPCODE_ALTIVEC),
174 { "power7", (PPC_OPCODE_PPC | PPC_OPCODE_ISEL | PPC_OPCODE_64
175 | PPC_OPCODE_POWER4 | PPC_OPCODE_POWER5 | PPC_OPCODE_POWER6
176 | PPC_OPCODE_POWER7 | PPC_OPCODE_ALTIVEC | PPC_OPCODE_VSX),
178 { "power8", (PPC_OPCODE_PPC | PPC_OPCODE_ISEL | PPC_OPCODE_64
179 | PPC_OPCODE_POWER4 | PPC_OPCODE_POWER5 | PPC_OPCODE_POWER6
180 | PPC_OPCODE_POWER7 | PPC_OPCODE_POWER8
181 | PPC_OPCODE_ALTIVEC | PPC_OPCODE_VSX),
183 { "power9", (PPC_OPCODE_PPC | PPC_OPCODE_ISEL | PPC_OPCODE_64
184 | PPC_OPCODE_POWER4 | PPC_OPCODE_POWER5 | PPC_OPCODE_POWER6
185 | PPC_OPCODE_POWER7 | PPC_OPCODE_POWER8 | PPC_OPCODE_POWER9
186 | PPC_OPCODE_ALTIVEC | PPC_OPCODE_VSX),
188 { "future", (PPC_OPCODE_PPC | PPC_OPCODE_ISEL | PPC_OPCODE_64
189 | PPC_OPCODE_POWER4 | PPC_OPCODE_POWER5 | PPC_OPCODE_POWER6
190 | PPC_OPCODE_POWER7 | PPC_OPCODE_POWER8 | PPC_OPCODE_POWER9
191 | PPC_OPCODE_POWERXX | PPC_OPCODE_ALTIVEC | PPC_OPCODE_VSX),
193 { "ppc", PPC_OPCODE_PPC,
195 { "ppc32", PPC_OPCODE_PPC,
197 { "32", PPC_OPCODE_PPC,
199 { "ppc64", PPC_OPCODE_PPC | PPC_OPCODE_64,
201 { "64", PPC_OPCODE_PPC | PPC_OPCODE_64,
203 { "ppc64bridge", PPC_OPCODE_PPC | PPC_OPCODE_64_BRIDGE,
205 { "ppcps", PPC_OPCODE_PPC | PPC_OPCODE_PPCPS,
207 { "pwr", PPC_OPCODE_POWER,
209 { "pwr2", PPC_OPCODE_POWER | PPC_OPCODE_POWER2,
211 { "pwr4", PPC_OPCODE_PPC | PPC_OPCODE_64 | PPC_OPCODE_POWER4,
213 { "pwr5", (PPC_OPCODE_PPC | PPC_OPCODE_64 | PPC_OPCODE_POWER4
214 | PPC_OPCODE_POWER5),
216 { "pwr5x", (PPC_OPCODE_PPC | PPC_OPCODE_64 | PPC_OPCODE_POWER4
217 | PPC_OPCODE_POWER5),
219 { "pwr6", (PPC_OPCODE_PPC | PPC_OPCODE_64 | PPC_OPCODE_POWER4
220 | PPC_OPCODE_POWER5 | PPC_OPCODE_POWER6 | PPC_OPCODE_ALTIVEC),
222 { "pwr7", (PPC_OPCODE_PPC | PPC_OPCODE_ISEL | PPC_OPCODE_64
223 | PPC_OPCODE_POWER4 | PPC_OPCODE_POWER5 | PPC_OPCODE_POWER6
224 | PPC_OPCODE_POWER7 | PPC_OPCODE_ALTIVEC | PPC_OPCODE_VSX),
226 { "pwr8", (PPC_OPCODE_PPC | PPC_OPCODE_ISEL | PPC_OPCODE_64
227 | PPC_OPCODE_POWER4 | PPC_OPCODE_POWER5 | PPC_OPCODE_POWER6
228 | PPC_OPCODE_POWER7 | PPC_OPCODE_POWER8
229 | PPC_OPCODE_ALTIVEC | PPC_OPCODE_VSX),
231 { "pwr9", (PPC_OPCODE_PPC | PPC_OPCODE_ISEL | PPC_OPCODE_64
232 | PPC_OPCODE_POWER4 | PPC_OPCODE_POWER5 | PPC_OPCODE_POWER6
233 | PPC_OPCODE_POWER7 | PPC_OPCODE_POWER8 | PPC_OPCODE_POWER9
234 | PPC_OPCODE_ALTIVEC | PPC_OPCODE_VSX),
236 { "pwrx", PPC_OPCODE_POWER | PPC_OPCODE_POWER2,
238 { "raw", PPC_OPCODE_PPC,
240 { "spe", PPC_OPCODE_PPC | PPC_OPCODE_EFS,
242 { "spe2", PPC_OPCODE_PPC | PPC_OPCODE_EFS | PPC_OPCODE_EFS2 | PPC_OPCODE_SPE,
244 { "titan", (PPC_OPCODE_PPC | PPC_OPCODE_BOOKE | PPC_OPCODE_PMR
245 | PPC_OPCODE_RFMCI | PPC_OPCODE_TITAN),
247 { "vle", (PPC_OPCODE_PPC | PPC_OPCODE_BOOKE| PPC_OPCODE_SPE
248 | PPC_OPCODE_ISEL | PPC_OPCODE_EFS | PPC_OPCODE_BRLOCK
249 | PPC_OPCODE_PMR | PPC_OPCODE_CACHELCK | PPC_OPCODE_RFMCI
250 | PPC_OPCODE_LSP | PPC_OPCODE_EFS2 | PPC_OPCODE_SPE2),
252 { "vsx", PPC_OPCODE_PPC,
256 /* Switch between Booke and VLE dialects for interlinked dumps. */
258 get_powerpc_dialect (struct disassemble_info *info)
260 ppc_cpu_t dialect = 0;
262 dialect = POWERPC_DIALECT (info);
264 /* Disassemble according to the section headers flags for VLE-mode. */
265 if (dialect & PPC_OPCODE_VLE
266 && info->section != NULL && info->section->owner != NULL
267 && bfd_get_flavour (info->section->owner) == bfd_target_elf_flavour
268 && elf_object_id (info->section->owner) == PPC32_ELF_DATA
269 && (elf_section_flags (info->section) & SHF_PPC_VLE) != 0)
272 return dialect & ~ PPC_OPCODE_VLE;
275 /* Handle -m and -M options that set cpu type, and .machine arg. */
278 ppc_parse_cpu (ppc_cpu_t ppc_cpu, ppc_cpu_t *sticky, const char *arg)
282 for (i = 0; i < ARRAY_SIZE (ppc_opts); i++)
283 if (disassembler_options_cmp (ppc_opts[i].opt, arg) == 0)
285 if (ppc_opts[i].sticky)
287 *sticky |= ppc_opts[i].sticky;
288 if ((ppc_cpu & ~*sticky) != 0)
291 ppc_cpu = ppc_opts[i].cpu;
294 if (i >= ARRAY_SIZE (ppc_opts))
301 /* Determine which set of machines to disassemble for. */
304 powerpc_init_dialect (struct disassemble_info *info)
306 ppc_cpu_t dialect = 0;
307 ppc_cpu_t sticky = 0;
308 struct dis_private *priv = calloc (sizeof (*priv), 1);
315 case bfd_mach_ppc_403:
316 case bfd_mach_ppc_403gc:
317 dialect = ppc_parse_cpu (dialect, &sticky, "403");
319 case bfd_mach_ppc_405:
320 dialect = ppc_parse_cpu (dialect, &sticky, "405");
322 case bfd_mach_ppc_601:
323 dialect = ppc_parse_cpu (dialect, &sticky, "601");
325 case bfd_mach_ppc_750:
326 dialect = ppc_parse_cpu (dialect, &sticky, "750cl");
328 case bfd_mach_ppc_a35:
329 case bfd_mach_ppc_rs64ii:
330 case bfd_mach_ppc_rs64iii:
331 dialect = ppc_parse_cpu (dialect, &sticky, "pwr2") | PPC_OPCODE_64;
333 case bfd_mach_ppc_e500:
334 dialect = ppc_parse_cpu (dialect, &sticky, "e500");
336 case bfd_mach_ppc_e500mc:
337 dialect = ppc_parse_cpu (dialect, &sticky, "e500mc");
339 case bfd_mach_ppc_e500mc64:
340 dialect = ppc_parse_cpu (dialect, &sticky, "e500mc64");
342 case bfd_mach_ppc_e5500:
343 dialect = ppc_parse_cpu (dialect, &sticky, "e5500");
345 case bfd_mach_ppc_e6500:
346 dialect = ppc_parse_cpu (dialect, &sticky, "e6500");
348 case bfd_mach_ppc_titan:
349 dialect = ppc_parse_cpu (dialect, &sticky, "titan");
351 case bfd_mach_ppc_vle:
352 dialect = ppc_parse_cpu (dialect, &sticky, "vle");
355 if (info->arch == bfd_arch_powerpc)
356 dialect = ppc_parse_cpu (dialect, &sticky, "power9") | PPC_OPCODE_ANY;
358 dialect = ppc_parse_cpu (dialect, &sticky, "pwr");
363 FOR_EACH_DISASSEMBLER_OPTION (opt, info->disassembler_options)
365 ppc_cpu_t new_cpu = 0;
367 if (disassembler_options_cmp (opt, "32") == 0)
368 dialect &= ~(ppc_cpu_t) PPC_OPCODE_64;
369 else if (disassembler_options_cmp (opt, "64") == 0)
370 dialect |= PPC_OPCODE_64;
371 else if ((new_cpu = ppc_parse_cpu (dialect, &sticky, opt)) != 0)
374 /* xgettext: c-format */
375 opcodes_error_handler (_("warning: ignoring unknown -M%s option"), opt);
378 info->private_data = priv;
379 POWERPC_DIALECT(info) = dialect;
382 #define PPC_OPCD_SEGS (1 + PPC_OP (-1))
383 static unsigned short powerpc_opcd_indices[PPC_OPCD_SEGS + 1];
384 #define PREFIX_OPCD_SEGS (1 + PPC_PREFIX_SEG (-1))
385 static unsigned short prefix_opcd_indices[PREFIX_OPCD_SEGS + 1];
386 #define VLE_OPCD_SEGS (1 + VLE_OP_TO_SEG (VLE_OP (-1, 0xffff)))
387 static unsigned short vle_opcd_indices[VLE_OPCD_SEGS + 1];
388 #define SPE2_OPCD_SEGS (1 + SPE2_XOP_TO_SEG (SPE2_XOP (-1)))
389 static unsigned short spe2_opcd_indices[SPE2_OPCD_SEGS + 1];
391 /* Calculate opcode table indices to speed up disassembly,
395 disassemble_init_powerpc (struct disassemble_info *info)
397 if (powerpc_opcd_indices[PPC_OPCD_SEGS] == 0)
399 unsigned seg, idx, op;
402 for (seg = 0, idx = 0; seg <= PPC_OPCD_SEGS; seg++)
404 powerpc_opcd_indices[seg] = idx;
405 for (; idx < powerpc_num_opcodes; idx++)
406 if (seg < PPC_OP (powerpc_opcodes[idx].opcode))
410 /* 64-bit prefix opcodes */
411 for (seg = 0, idx = 0; seg <= PREFIX_OPCD_SEGS; seg++)
413 prefix_opcd_indices[seg] = idx;
414 for (; idx < prefix_num_opcodes; idx++)
415 if (seg < PPC_PREFIX_SEG (prefix_opcodes[idx].opcode))
420 for (seg = 0, idx = 0; seg <= VLE_OPCD_SEGS; seg++)
422 vle_opcd_indices[seg] = idx;
423 for (; idx < vle_num_opcodes; idx++)
425 op = VLE_OP (vle_opcodes[idx].opcode, vle_opcodes[idx].mask);
426 if (seg < VLE_OP_TO_SEG (op))
432 for (seg = 0, idx = 0; seg <= SPE2_OPCD_SEGS; seg++)
434 spe2_opcd_indices[seg] = idx;
435 for (; idx < spe2_num_opcodes; idx++)
437 op = SPE2_XOP (spe2_opcodes[idx].opcode);
438 if (seg < SPE2_XOP_TO_SEG (op))
444 powerpc_init_dialect (info);
447 /* Print a big endian PowerPC instruction. */
450 print_insn_big_powerpc (bfd_vma memaddr, struct disassemble_info *info)
452 return print_insn_powerpc (memaddr, info, 1, get_powerpc_dialect (info));
455 /* Print a little endian PowerPC instruction. */
458 print_insn_little_powerpc (bfd_vma memaddr, struct disassemble_info *info)
460 return print_insn_powerpc (memaddr, info, 0, get_powerpc_dialect (info));
463 /* Extract the operand value from the PowerPC or POWER instruction. */
466 operand_value_powerpc (const struct powerpc_operand *operand,
467 uint64_t insn, ppc_cpu_t dialect)
471 /* Extract the value from the instruction. */
472 if (operand->extract)
473 value = (*operand->extract) (insn, dialect, &invalid);
476 if (operand->shift >= 0)
477 value = (insn >> operand->shift) & operand->bitm;
479 value = (insn << -operand->shift) & operand->bitm;
480 if ((operand->flags & PPC_OPERAND_SIGNED) != 0)
482 /* BITM is always some number of zeros followed by some
483 number of ones, followed by some number of zeros. */
484 uint64_t top = operand->bitm;
485 /* top & -top gives the rightmost 1 bit, so this
486 fills in any trailing zeros. */
487 top |= (top & -top) - 1;
489 value = (value ^ top) - top;
496 /* Determine whether the optional operand(s) should be printed. */
499 skip_optional_operands (const unsigned char *opindex,
500 uint64_t insn, ppc_cpu_t dialect)
502 const struct powerpc_operand *operand;
505 for (num_optional = 0; *opindex != 0; opindex++)
507 operand = &powerpc_operands[*opindex];
508 if ((operand->flags & PPC_OPERAND_NEXT) != 0)
510 if ((operand->flags & PPC_OPERAND_OPTIONAL) != 0)
512 /* Negative count is used as a flag to extract function. */
514 if (operand_value_powerpc (operand, insn, dialect)
515 != ppc_optional_operand_value (operand, insn, dialect,
524 /* Find a match for INSN in the opcode table, given machine DIALECT. */
526 static const struct powerpc_opcode *
527 lookup_powerpc (uint64_t insn, ppc_cpu_t dialect)
529 const struct powerpc_opcode *opcode, *opcode_end, *last;
532 /* Get the major opcode of the instruction. */
535 /* Find the first match in the opcode table for this major opcode. */
536 opcode_end = powerpc_opcodes + powerpc_opcd_indices[op + 1];
538 for (opcode = powerpc_opcodes + powerpc_opcd_indices[op];
542 const unsigned char *opindex;
543 const struct powerpc_operand *operand;
546 if ((insn & opcode->mask) != opcode->opcode
547 || ((dialect & PPC_OPCODE_ANY) == 0
548 && ((opcode->flags & dialect) == 0
549 || (opcode->deprecated & dialect) != 0)))
552 /* Check validity of operands. */
554 for (opindex = opcode->operands; *opindex != 0; opindex++)
556 operand = powerpc_operands + *opindex;
557 if (operand->extract)
558 (*operand->extract) (insn, dialect, &invalid);
563 if ((dialect & PPC_OPCODE_RAW) == 0)
566 /* The raw machine insn is one that is not a specialization. */
568 || (last->mask & ~opcode->mask) != 0)
575 /* Find a match for INSN in the PREFIX opcode table. */
577 static const struct powerpc_opcode *
578 lookup_prefix (uint64_t insn, ppc_cpu_t dialect)
580 const struct powerpc_opcode *opcode, *opcode_end, *last;
583 /* Get the opcode segment of the instruction. */
584 seg = PPC_PREFIX_SEG (insn);
586 /* Find the first match in the opcode table for this major opcode. */
587 opcode_end = prefix_opcodes + prefix_opcd_indices[seg + 1];
589 for (opcode = prefix_opcodes + prefix_opcd_indices[seg];
593 const unsigned char *opindex;
594 const struct powerpc_operand *operand;
597 if ((insn & opcode->mask) != opcode->opcode
598 || ((dialect & PPC_OPCODE_ANY) == 0
599 && ((opcode->flags & dialect) == 0
600 || (opcode->deprecated & dialect) != 0)))
603 /* Check validity of operands. */
605 for (opindex = opcode->operands; *opindex != 0; opindex++)
607 operand = powerpc_operands + *opindex;
608 if (operand->extract)
609 (*operand->extract) (insn, dialect, &invalid);
614 if ((dialect & PPC_OPCODE_RAW) == 0)
617 /* The raw machine insn is one that is not a specialization. */
619 || (last->mask & ~opcode->mask) != 0)
626 /* Find a match for INSN in the VLE opcode table. */
628 static const struct powerpc_opcode *
629 lookup_vle (uint64_t insn)
631 const struct powerpc_opcode *opcode;
632 const struct powerpc_opcode *opcode_end;
636 if (op >= 0x20 && op <= 0x37)
638 /* This insn has a 4-bit opcode. */
641 seg = VLE_OP_TO_SEG (op);
643 /* Find the first match in the opcode table for this major opcode. */
644 opcode_end = vle_opcodes + vle_opcd_indices[seg + 1];
645 for (opcode = vle_opcodes + vle_opcd_indices[seg];
649 uint64_t table_opcd = opcode->opcode;
650 uint64_t table_mask = opcode->mask;
651 bfd_boolean table_op_is_short = PPC_OP_SE_VLE(table_mask);
653 const unsigned char *opindex;
654 const struct powerpc_operand *operand;
658 if (table_op_is_short)
660 if ((insn2 & table_mask) != table_opcd)
663 /* Check validity of operands. */
665 for (opindex = opcode->operands; *opindex != 0; ++opindex)
667 operand = powerpc_operands + *opindex;
668 if (operand->extract)
669 (*operand->extract) (insn, (ppc_cpu_t)0, &invalid);
680 /* Find a match for INSN in the SPE2 opcode table. */
682 static const struct powerpc_opcode *
683 lookup_spe2 (uint64_t insn)
685 const struct powerpc_opcode *opcode, *opcode_end;
686 unsigned op, xop, seg;
691 /* This is not SPE2 insn.
692 * All SPE2 instructions have OP=4 and differs by XOP */
695 xop = SPE2_XOP (insn);
696 seg = SPE2_XOP_TO_SEG (xop);
698 /* Find the first match in the opcode table for this major opcode. */
699 opcode_end = spe2_opcodes + spe2_opcd_indices[seg + 1];
700 for (opcode = spe2_opcodes + spe2_opcd_indices[seg];
704 uint64_t table_opcd = opcode->opcode;
705 uint64_t table_mask = opcode->mask;
707 const unsigned char *opindex;
708 const struct powerpc_operand *operand;
712 if ((insn2 & table_mask) != table_opcd)
715 /* Check validity of operands. */
717 for (opindex = opcode->operands; *opindex != 0; ++opindex)
719 operand = powerpc_operands + *opindex;
720 if (operand->extract)
721 (*operand->extract) (insn, (ppc_cpu_t)0, &invalid);
732 /* Print a PowerPC or POWER instruction. */
735 print_insn_powerpc (bfd_vma memaddr,
736 struct disassemble_info *info,
743 const struct powerpc_opcode *opcode;
744 int insn_length = 4; /* Assume we have a normal 4-byte instruction. */
746 status = (*info->read_memory_func) (memaddr, buffer, 4, info);
748 /* The final instruction may be a 2-byte VLE insn. */
749 if (status != 0 && (dialect & PPC_OPCODE_VLE) != 0)
751 /* Clear buffer so unused bytes will not have garbage in them. */
752 buffer[0] = buffer[1] = buffer[2] = buffer[3] = 0;
753 status = (*info->read_memory_func) (memaddr, buffer, 2, info);
758 (*info->memory_error_func) (status, memaddr, info);
763 insn = bfd_getb32 (buffer);
765 insn = bfd_getl32 (buffer);
767 /* Get the major opcode of the insn. */
769 if ((dialect & PPC_OPCODE_POWERXX) != 0
770 && PPC_OP (insn) == 0x1)
772 uint64_t temp_insn, suffix;
773 status = (*info->read_memory_func) (memaddr + 4, buffer, 4, info);
777 suffix = bfd_getb32 (buffer);
779 suffix = bfd_getl32 (buffer);
780 temp_insn = (insn << 32) | suffix;
781 opcode = lookup_prefix (temp_insn, dialect & ~PPC_OPCODE_ANY);
782 if (opcode == NULL && (dialect & PPC_OPCODE_ANY) != 0)
783 opcode = lookup_prefix (temp_insn, dialect);
788 if ((info->flags & WIDE_OUTPUT) != 0)
789 info->bytes_per_line = 8;
793 if (opcode == NULL && (dialect & PPC_OPCODE_VLE) != 0)
795 opcode = lookup_vle (insn);
796 if (opcode != NULL && PPC_OP_SE_VLE (opcode->mask))
798 /* The operands will be fetched out of the 16-bit instruction. */
803 if (opcode == NULL && (dialect & PPC_OPCODE_SPE2) != 0)
804 opcode = lookup_spe2 (insn);
806 opcode = lookup_powerpc (insn, dialect & ~PPC_OPCODE_ANY);
807 if (opcode == NULL && (dialect & PPC_OPCODE_ANY) != 0)
808 opcode = lookup_powerpc (insn, dialect);
812 const unsigned char *opindex;
813 const struct powerpc_operand *operand;
825 bfd_boolean skip_optional;
828 (*info->fprintf_func) (info->stream, "%s", opcode->name);
829 /* gdb fprintf_func doesn't return count printed. */
830 spaces = 8 - strlen (opcode->name);
834 /* Now extract and print the operands. */
835 op_separator = spaces;
836 skip_optional = FALSE;
837 for (opindex = opcode->operands; *opindex != 0; opindex++)
841 operand = powerpc_operands + *opindex;
843 /* If all of the optional operands past this one have their
844 default value, then don't print any of them. Except in
845 raw mode, print them all. */
846 if ((operand->flags & PPC_OPERAND_OPTIONAL) != 0
847 && (dialect & PPC_OPCODE_RAW) == 0)
850 skip_optional = skip_optional_operands (opindex, insn, dialect);
855 value = operand_value_powerpc (operand, insn, dialect);
857 if (op_separator == need_comma)
858 (*info->fprintf_func) (info->stream, ",");
859 else if (op_separator == need_paren)
860 (*info->fprintf_func) (info->stream, "(");
862 (*info->fprintf_func) (info->stream, "%*s", op_separator, " ");
864 /* Print the operand as directed by the flags. */
865 if ((operand->flags & PPC_OPERAND_GPR) != 0
866 || ((operand->flags & PPC_OPERAND_GPR_0) != 0 && value != 0))
867 (*info->fprintf_func) (info->stream, "r%" PRId64, value);
868 else if ((operand->flags & PPC_OPERAND_FPR) != 0)
869 (*info->fprintf_func) (info->stream, "f%" PRId64, value);
870 else if ((operand->flags & PPC_OPERAND_VR) != 0)
871 (*info->fprintf_func) (info->stream, "v%" PRId64, value);
872 else if ((operand->flags & PPC_OPERAND_VSR) != 0)
873 (*info->fprintf_func) (info->stream, "vs%" PRId64, value);
874 else if ((operand->flags & PPC_OPERAND_RELATIVE) != 0)
875 (*info->print_address_func) (memaddr + value, info);
876 else if ((operand->flags & PPC_OPERAND_ABSOLUTE) != 0)
877 (*info->print_address_func) ((bfd_vma) value & 0xffffffff, info);
878 else if ((operand->flags & PPC_OPERAND_FSL) != 0)
879 (*info->fprintf_func) (info->stream, "fsl%" PRId64, value);
880 else if ((operand->flags & PPC_OPERAND_FCR) != 0)
881 (*info->fprintf_func) (info->stream, "fcr%" PRId64, value);
882 else if ((operand->flags & PPC_OPERAND_UDI) != 0)
883 (*info->fprintf_func) (info->stream, "%" PRId64, value);
884 else if ((operand->flags & PPC_OPERAND_CR_REG) != 0
885 && (operand->flags & PPC_OPERAND_CR_BIT) == 0
886 && (((dialect & PPC_OPCODE_PPC) != 0)
887 || ((dialect & PPC_OPCODE_VLE) != 0)))
888 (*info->fprintf_func) (info->stream, "cr%" PRId64, value);
889 else if ((operand->flags & PPC_OPERAND_CR_BIT) != 0
890 && (operand->flags & PPC_OPERAND_CR_REG) == 0
891 && (((dialect & PPC_OPCODE_PPC) != 0)
892 || ((dialect & PPC_OPCODE_VLE) != 0)))
894 static const char *cbnames[4] = { "lt", "gt", "eq", "so" };
900 (*info->fprintf_func) (info->stream, "4*cr%d+", cr);
902 (*info->fprintf_func) (info->stream, "%s", cbnames[cc]);
905 (*info->fprintf_func) (info->stream, "%" PRId64, value);
907 if (op_separator == need_paren)
908 (*info->fprintf_func) (info->stream, ")");
910 op_separator = need_comma;
911 if ((operand->flags & PPC_OPERAND_PARENS) != 0)
912 op_separator = need_paren;
915 /* We have found and printed an instruction. */
919 /* We could not find a match. */
920 (*info->fprintf_func) (info->stream, ".long 0x%" PRIx64, insn);
925 const disasm_options_and_args_t *
926 disassembler_options_powerpc (void)
928 static disasm_options_and_args_t *opts_and_args;
930 if (opts_and_args == NULL)
932 size_t i, num_options = ARRAY_SIZE (ppc_opts);
933 disasm_options_t *opts;
935 opts_and_args = XNEW (disasm_options_and_args_t);
936 opts_and_args->args = NULL;
938 opts = &opts_and_args->options;
939 opts->name = XNEWVEC (const char *, num_options + 1);
940 opts->description = NULL;
942 for (i = 0; i < num_options; i++)
943 opts->name[i] = ppc_opts[i].opt;
944 /* The array we return must be NULL terminated. */
945 opts->name[i] = NULL;
948 return opts_and_args;
952 print_ppc_disassembler_options (FILE *stream)
956 fprintf (stream, _("\n\
957 The following PPC specific disassembler options are supported for use with\n\
960 for (col = 0, i = 0; i < ARRAY_SIZE (ppc_opts); i++)
962 col += fprintf (stream, " %s,", ppc_opts[i].opt);
965 fprintf (stream, "\n");
969 fprintf (stream, "\n");