1 /* ppc-dis.c -- Disassemble PowerPC instructions
2 Copyright (C) 1994-2017 Free Software Foundation, Inc.
3 Written by Ian Lance Taylor, Cygnus Support
5 This file is part of the GNU opcodes library.
7 This library is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 3, or (at your option)
12 It is distributed in the hope that it will be useful, but WITHOUT
13 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
14 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
15 License for more details.
17 You should have received a copy of the GNU General Public License
18 along with this file; see the file COPYING. If not, write to the
19 Free Software Foundation, 51 Franklin Street - Fifth Floor, Boston,
20 MA 02110-1301, USA. */
24 #include "disassemble.h"
28 #include "opcode/ppc.h"
29 #include "libiberty.h"
31 /* This file provides several disassembler functions, all of which use
32 the disassembler interface defined in dis-asm.h. Several functions
33 are provided because this file handles disassembly for the PowerPC
34 in both big and little endian mode and also for the POWER (RS/6000)
36 static int print_insn_powerpc (bfd_vma, struct disassemble_info *, int,
41 /* Stash the result of parsing disassembler_options here. */
45 #define POWERPC_DIALECT(INFO) \
46 (((struct dis_private *) ((INFO)->private_data))->dialect)
49 /* Option string, without -m or -M prefix. */
51 /* CPU option flags. */
53 /* Flags that should stay on, even when combined with another cpu
54 option. This should only be used for generic options like
55 "-many" or "-maltivec" where it is reasonable to add some
56 capability to another cpu selection. The added flags are sticky
57 so that, for example, "-many -me500" and "-me500 -many" result in
58 the same assembler or disassembler behaviour. Do not use
59 "sticky" for specific cpus, as this will prevent that cpu's flags
60 from overriding the defaults set in powerpc_init_dialect or a
65 struct ppc_mopt ppc_opts[] = {
66 { "403", PPC_OPCODE_PPC | PPC_OPCODE_403,
68 { "405", PPC_OPCODE_PPC | PPC_OPCODE_403 | PPC_OPCODE_405,
70 { "440", (PPC_OPCODE_PPC | PPC_OPCODE_BOOKE | PPC_OPCODE_440
71 | PPC_OPCODE_ISEL | PPC_OPCODE_RFMCI),
73 { "464", (PPC_OPCODE_PPC | PPC_OPCODE_BOOKE | PPC_OPCODE_440
74 | PPC_OPCODE_ISEL | PPC_OPCODE_RFMCI),
76 { "476", (PPC_OPCODE_PPC | PPC_OPCODE_ISEL | PPC_OPCODE_476
77 | PPC_OPCODE_POWER4 | PPC_OPCODE_POWER5),
79 { "601", PPC_OPCODE_PPC | PPC_OPCODE_601,
81 { "603", PPC_OPCODE_PPC,
83 { "604", PPC_OPCODE_PPC,
85 { "620", PPC_OPCODE_PPC | PPC_OPCODE_64,
87 { "7400", PPC_OPCODE_PPC | PPC_OPCODE_ALTIVEC,
89 { "7410", PPC_OPCODE_PPC | PPC_OPCODE_ALTIVEC,
91 { "7450", PPC_OPCODE_PPC | PPC_OPCODE_7450 | PPC_OPCODE_ALTIVEC,
93 { "7455", PPC_OPCODE_PPC | PPC_OPCODE_ALTIVEC,
95 { "750cl", PPC_OPCODE_PPC | PPC_OPCODE_750 | PPC_OPCODE_PPCPS
97 { "821", PPC_OPCODE_PPC | PPC_OPCODE_860,
99 { "850", PPC_OPCODE_PPC | PPC_OPCODE_860,
101 { "860", PPC_OPCODE_PPC | PPC_OPCODE_860,
103 { "a2", (PPC_OPCODE_PPC | PPC_OPCODE_ISEL | PPC_OPCODE_POWER4
104 | PPC_OPCODE_POWER5 | PPC_OPCODE_CACHELCK | PPC_OPCODE_64
107 { "altivec", PPC_OPCODE_PPC,
108 PPC_OPCODE_ALTIVEC },
109 { "any", PPC_OPCODE_PPC,
111 { "booke", PPC_OPCODE_PPC | PPC_OPCODE_BOOKE,
113 { "booke32", PPC_OPCODE_PPC | PPC_OPCODE_BOOKE,
115 { "cell", (PPC_OPCODE_PPC | PPC_OPCODE_64 | PPC_OPCODE_POWER4
116 | PPC_OPCODE_CELL | PPC_OPCODE_ALTIVEC),
118 { "com", PPC_OPCODE_COMMON,
120 { "e200z4", (PPC_OPCODE_PPC | PPC_OPCODE_BOOKE| PPC_OPCODE_SPE
121 | PPC_OPCODE_ISEL | PPC_OPCODE_EFS | PPC_OPCODE_BRLOCK
122 | PPC_OPCODE_PMR | PPC_OPCODE_CACHELCK | PPC_OPCODE_RFMCI
123 | PPC_OPCODE_E500 | PPC_OPCODE_VLE | PPC_OPCODE_E200Z4
124 | PPC_OPCODE_EFS2 | PPC_OPCODE_LSP),
126 { "e300", PPC_OPCODE_PPC | PPC_OPCODE_E300,
128 { "e500", (PPC_OPCODE_PPC | PPC_OPCODE_BOOKE | PPC_OPCODE_SPE
129 | PPC_OPCODE_ISEL | PPC_OPCODE_EFS | PPC_OPCODE_BRLOCK
130 | PPC_OPCODE_PMR | PPC_OPCODE_CACHELCK | PPC_OPCODE_RFMCI
133 { "e500mc", (PPC_OPCODE_PPC | PPC_OPCODE_BOOKE | PPC_OPCODE_ISEL
134 | PPC_OPCODE_PMR | PPC_OPCODE_CACHELCK | PPC_OPCODE_RFMCI
135 | PPC_OPCODE_E500MC),
137 { "e500mc64", (PPC_OPCODE_PPC | PPC_OPCODE_BOOKE | PPC_OPCODE_ISEL
138 | PPC_OPCODE_PMR | PPC_OPCODE_CACHELCK | PPC_OPCODE_RFMCI
139 | PPC_OPCODE_E500MC | PPC_OPCODE_64 | PPC_OPCODE_POWER5
140 | PPC_OPCODE_POWER6 | PPC_OPCODE_POWER7),
142 { "e5500", (PPC_OPCODE_PPC | PPC_OPCODE_BOOKE | PPC_OPCODE_ISEL
143 | PPC_OPCODE_PMR | PPC_OPCODE_CACHELCK | PPC_OPCODE_RFMCI
144 | PPC_OPCODE_E500MC | PPC_OPCODE_64 | PPC_OPCODE_POWER4
145 | PPC_OPCODE_POWER5 | PPC_OPCODE_POWER6 | PPC_OPCODE_POWER7),
147 { "e6500", (PPC_OPCODE_PPC | PPC_OPCODE_BOOKE | PPC_OPCODE_ISEL
148 | PPC_OPCODE_PMR | PPC_OPCODE_CACHELCK | PPC_OPCODE_RFMCI
149 | PPC_OPCODE_E500MC | PPC_OPCODE_64 | PPC_OPCODE_ALTIVEC
150 | PPC_OPCODE_E6500 | PPC_OPCODE_TMR | PPC_OPCODE_POWER4
151 | PPC_OPCODE_POWER5 | PPC_OPCODE_POWER6 | PPC_OPCODE_POWER7),
153 { "e500x2", (PPC_OPCODE_PPC | PPC_OPCODE_BOOKE | PPC_OPCODE_SPE
154 | PPC_OPCODE_ISEL | PPC_OPCODE_EFS | PPC_OPCODE_BRLOCK
155 | PPC_OPCODE_PMR | PPC_OPCODE_CACHELCK | PPC_OPCODE_RFMCI
158 { "efs", PPC_OPCODE_PPC | PPC_OPCODE_EFS,
160 { "efs2", PPC_OPCODE_PPC | PPC_OPCODE_EFS | PPC_OPCODE_EFS2,
162 { "power4", PPC_OPCODE_PPC | PPC_OPCODE_64 | PPC_OPCODE_POWER4,
164 { "power5", (PPC_OPCODE_PPC | PPC_OPCODE_64 | PPC_OPCODE_POWER4
165 | PPC_OPCODE_POWER5),
167 { "power6", (PPC_OPCODE_PPC | PPC_OPCODE_64 | PPC_OPCODE_POWER4
168 | PPC_OPCODE_POWER5 | PPC_OPCODE_POWER6 | PPC_OPCODE_ALTIVEC),
170 { "power7", (PPC_OPCODE_PPC | PPC_OPCODE_ISEL | PPC_OPCODE_64
171 | PPC_OPCODE_POWER4 | PPC_OPCODE_POWER5 | PPC_OPCODE_POWER6
172 | PPC_OPCODE_POWER7 | PPC_OPCODE_ALTIVEC | PPC_OPCODE_VSX),
174 { "power8", (PPC_OPCODE_PPC | PPC_OPCODE_ISEL | PPC_OPCODE_64
175 | PPC_OPCODE_POWER4 | PPC_OPCODE_POWER5 | PPC_OPCODE_POWER6
176 | PPC_OPCODE_POWER7 | PPC_OPCODE_POWER8
177 | PPC_OPCODE_ALTIVEC | PPC_OPCODE_VSX),
179 { "power9", (PPC_OPCODE_PPC | PPC_OPCODE_ISEL | PPC_OPCODE_64
180 | PPC_OPCODE_POWER4 | PPC_OPCODE_POWER5 | PPC_OPCODE_POWER6
181 | PPC_OPCODE_POWER7 | PPC_OPCODE_POWER8 | PPC_OPCODE_POWER9
182 | PPC_OPCODE_ALTIVEC | PPC_OPCODE_VSX),
184 { "ppc", PPC_OPCODE_PPC,
186 { "ppc32", PPC_OPCODE_PPC,
188 { "32", PPC_OPCODE_PPC,
190 { "ppc64", PPC_OPCODE_PPC | PPC_OPCODE_64,
192 { "64", PPC_OPCODE_PPC | PPC_OPCODE_64,
194 { "ppc64bridge", PPC_OPCODE_PPC | PPC_OPCODE_64_BRIDGE,
196 { "ppcps", PPC_OPCODE_PPC | PPC_OPCODE_PPCPS,
198 { "pwr", PPC_OPCODE_POWER,
200 { "pwr2", PPC_OPCODE_POWER | PPC_OPCODE_POWER2,
202 { "pwr4", PPC_OPCODE_PPC | PPC_OPCODE_64 | PPC_OPCODE_POWER4,
204 { "pwr5", (PPC_OPCODE_PPC | PPC_OPCODE_64 | PPC_OPCODE_POWER4
205 | PPC_OPCODE_POWER5),
207 { "pwr5x", (PPC_OPCODE_PPC | PPC_OPCODE_64 | PPC_OPCODE_POWER4
208 | PPC_OPCODE_POWER5),
210 { "pwr6", (PPC_OPCODE_PPC | PPC_OPCODE_64 | PPC_OPCODE_POWER4
211 | PPC_OPCODE_POWER5 | PPC_OPCODE_POWER6 | PPC_OPCODE_ALTIVEC),
213 { "pwr7", (PPC_OPCODE_PPC | PPC_OPCODE_ISEL | PPC_OPCODE_64
214 | PPC_OPCODE_POWER4 | PPC_OPCODE_POWER5 | PPC_OPCODE_POWER6
215 | PPC_OPCODE_POWER7 | PPC_OPCODE_ALTIVEC | PPC_OPCODE_VSX),
217 { "pwr8", (PPC_OPCODE_PPC | PPC_OPCODE_ISEL | PPC_OPCODE_64
218 | PPC_OPCODE_POWER4 | PPC_OPCODE_POWER5 | PPC_OPCODE_POWER6
219 | PPC_OPCODE_POWER7 | PPC_OPCODE_POWER8
220 | PPC_OPCODE_ALTIVEC | PPC_OPCODE_VSX),
222 { "pwr9", (PPC_OPCODE_PPC | PPC_OPCODE_ISEL | PPC_OPCODE_64
223 | PPC_OPCODE_POWER4 | PPC_OPCODE_POWER5 | PPC_OPCODE_POWER6
224 | PPC_OPCODE_POWER7 | PPC_OPCODE_POWER8 | PPC_OPCODE_POWER9
225 | PPC_OPCODE_ALTIVEC | PPC_OPCODE_VSX),
227 { "pwrx", PPC_OPCODE_POWER | PPC_OPCODE_POWER2,
229 { "raw", PPC_OPCODE_PPC,
231 { "spe", PPC_OPCODE_PPC | PPC_OPCODE_EFS,
233 { "spe2", PPC_OPCODE_PPC | PPC_OPCODE_EFS | PPC_OPCODE_EFS2 | PPC_OPCODE_SPE,
235 { "titan", (PPC_OPCODE_PPC | PPC_OPCODE_BOOKE | PPC_OPCODE_PMR
236 | PPC_OPCODE_RFMCI | PPC_OPCODE_TITAN),
238 { "vle", (PPC_OPCODE_PPC | PPC_OPCODE_BOOKE| PPC_OPCODE_SPE
239 | PPC_OPCODE_ISEL | PPC_OPCODE_EFS | PPC_OPCODE_BRLOCK
240 | PPC_OPCODE_PMR | PPC_OPCODE_CACHELCK | PPC_OPCODE_RFMCI
241 | PPC_OPCODE_LSP | PPC_OPCODE_EFS2 | PPC_OPCODE_SPE2),
243 { "vsx", PPC_OPCODE_PPC,
247 /* Switch between Booke and VLE dialects for interlinked dumps. */
249 get_powerpc_dialect (struct disassemble_info *info)
251 ppc_cpu_t dialect = 0;
253 dialect = POWERPC_DIALECT (info);
255 /* Disassemble according to the section headers flags for VLE-mode. */
256 if (dialect & PPC_OPCODE_VLE
257 && info->section != NULL && info->section->owner != NULL
258 && bfd_get_flavour (info->section->owner) == bfd_target_elf_flavour
259 && elf_object_id (info->section->owner) == PPC32_ELF_DATA
260 && (elf_section_flags (info->section) & SHF_PPC_VLE) != 0)
263 return dialect & ~ PPC_OPCODE_VLE;
266 /* Handle -m and -M options that set cpu type, and .machine arg. */
269 ppc_parse_cpu (ppc_cpu_t ppc_cpu, ppc_cpu_t *sticky, const char *arg)
273 for (i = 0; i < ARRAY_SIZE (ppc_opts); i++)
274 if (disassembler_options_cmp (ppc_opts[i].opt, arg) == 0)
276 if (ppc_opts[i].sticky)
278 *sticky |= ppc_opts[i].sticky;
279 if ((ppc_cpu & ~*sticky) != 0)
282 ppc_cpu = ppc_opts[i].cpu;
285 if (i >= ARRAY_SIZE (ppc_opts))
292 /* Determine which set of machines to disassemble for. */
295 powerpc_init_dialect (struct disassemble_info *info)
297 ppc_cpu_t dialect = 0;
298 ppc_cpu_t sticky = 0;
299 struct dis_private *priv = calloc (sizeof (*priv), 1);
306 case bfd_mach_ppc_403:
307 case bfd_mach_ppc_403gc:
308 dialect = ppc_parse_cpu (dialect, &sticky, "403");
310 case bfd_mach_ppc_405:
311 dialect = ppc_parse_cpu (dialect, &sticky, "405");
313 case bfd_mach_ppc_601:
314 dialect = ppc_parse_cpu (dialect, &sticky, "601");
316 case bfd_mach_ppc_a35:
317 case bfd_mach_ppc_rs64ii:
318 case bfd_mach_ppc_rs64iii:
319 dialect = ppc_parse_cpu (dialect, &sticky, "pwr2") | PPC_OPCODE_64;
321 case bfd_mach_ppc_e500:
322 dialect = ppc_parse_cpu (dialect, &sticky, "e500");
324 case bfd_mach_ppc_e500mc:
325 dialect = ppc_parse_cpu (dialect, &sticky, "e500mc");
327 case bfd_mach_ppc_e500mc64:
328 dialect = ppc_parse_cpu (dialect, &sticky, "e500mc64");
330 case bfd_mach_ppc_e5500:
331 dialect = ppc_parse_cpu (dialect, &sticky, "e5500");
333 case bfd_mach_ppc_e6500:
334 dialect = ppc_parse_cpu (dialect, &sticky, "e6500");
336 case bfd_mach_ppc_titan:
337 dialect = ppc_parse_cpu (dialect, &sticky, "titan");
339 case bfd_mach_ppc_vle:
340 dialect = ppc_parse_cpu (dialect, &sticky, "vle");
343 dialect = ppc_parse_cpu (dialect, &sticky, "power9") | PPC_OPCODE_ANY;
348 FOR_EACH_DISASSEMBLER_OPTION (opt, info->disassembler_options)
350 ppc_cpu_t new_cpu = 0;
352 if (disassembler_options_cmp (opt, "32") == 0)
353 dialect &= ~(ppc_cpu_t) PPC_OPCODE_64;
354 else if (disassembler_options_cmp (opt, "64") == 0)
355 dialect |= PPC_OPCODE_64;
356 else if ((new_cpu = ppc_parse_cpu (dialect, &sticky, opt)) != 0)
359 fprintf (stderr, _("warning: ignoring unknown -M%s option\n"), opt);
362 info->private_data = priv;
363 POWERPC_DIALECT(info) = dialect;
366 #define PPC_OPCD_SEGS 64
367 static unsigned short powerpc_opcd_indices[PPC_OPCD_SEGS+1];
368 #define VLE_OPCD_SEGS 32
369 static unsigned short vle_opcd_indices[VLE_OPCD_SEGS+1];
370 #define SPE2_OPCD_SEGS 13
371 static unsigned short spe2_opcd_indices[SPE2_OPCD_SEGS+1];
373 /* Calculate opcode table indices to speed up disassembly,
377 disassemble_init_powerpc (struct disassemble_info *info)
382 if (powerpc_opcd_indices[PPC_OPCD_SEGS] == 0)
385 i = powerpc_num_opcodes;
388 unsigned op = PPC_OP (powerpc_opcodes[i].opcode);
390 powerpc_opcd_indices[op] = i;
393 last = powerpc_num_opcodes;
394 for (i = PPC_OPCD_SEGS; i > 0; --i)
396 if (powerpc_opcd_indices[i] == 0)
397 powerpc_opcd_indices[i] = last;
398 last = powerpc_opcd_indices[i];
404 unsigned op = VLE_OP (vle_opcodes[i].opcode, vle_opcodes[i].mask);
405 unsigned seg = VLE_OP_TO_SEG (op);
407 vle_opcd_indices[seg] = i;
410 last = vle_num_opcodes;
411 for (i = VLE_OPCD_SEGS; i > 0; --i)
413 if (vle_opcd_indices[i] == 0)
414 vle_opcd_indices[i] = last;
415 last = vle_opcd_indices[i];
420 i = spe2_num_opcodes;
423 unsigned xop = SPE2_XOP (spe2_opcodes[i].opcode);
424 unsigned seg = SPE2_XOP_TO_SEG (xop);
426 spe2_opcd_indices[seg] = i;
429 last = spe2_num_opcodes;
430 for (i = SPE2_OPCD_SEGS; i > 1; --i)
432 if (spe2_opcd_indices[i] == 0)
433 spe2_opcd_indices[i] = last;
434 last = spe2_opcd_indices[i];
437 if (info->arch == bfd_arch_powerpc)
438 powerpc_init_dialect (info);
441 /* Print a big endian PowerPC instruction. */
444 print_insn_big_powerpc (bfd_vma memaddr, struct disassemble_info *info)
446 return print_insn_powerpc (memaddr, info, 1, get_powerpc_dialect (info));
449 /* Print a little endian PowerPC instruction. */
452 print_insn_little_powerpc (bfd_vma memaddr, struct disassemble_info *info)
454 return print_insn_powerpc (memaddr, info, 0, get_powerpc_dialect (info));
457 /* Print a POWER (RS/6000) instruction. */
460 print_insn_rs6000 (bfd_vma memaddr, struct disassemble_info *info)
462 return print_insn_powerpc (memaddr, info, 1, PPC_OPCODE_POWER);
465 /* Extract the operand value from the PowerPC or POWER instruction. */
468 operand_value_powerpc (const struct powerpc_operand *operand,
469 unsigned long insn, ppc_cpu_t dialect)
473 /* Extract the value from the instruction. */
474 if (operand->extract)
475 value = (*operand->extract) (insn, dialect, &invalid);
478 if (operand->shift >= 0)
479 value = (insn >> operand->shift) & operand->bitm;
481 value = (insn << -operand->shift) & operand->bitm;
482 if ((operand->flags & PPC_OPERAND_SIGNED) != 0)
484 /* BITM is always some number of zeros followed by some
485 number of ones, followed by some number of zeros. */
486 unsigned long top = operand->bitm;
487 /* top & -top gives the rightmost 1 bit, so this
488 fills in any trailing zeros. */
489 top |= (top & -top) - 1;
491 value = (value ^ top) - top;
498 /* Determine whether the optional operand(s) should be printed. */
501 skip_optional_operands (const unsigned char *opindex,
502 unsigned long insn, ppc_cpu_t dialect)
504 const struct powerpc_operand *operand;
506 for (; *opindex != 0; opindex++)
508 operand = &powerpc_operands[*opindex];
509 if ((operand->flags & PPC_OPERAND_NEXT) != 0
510 || ((operand->flags & PPC_OPERAND_OPTIONAL) != 0
511 && operand_value_powerpc (operand, insn, dialect) !=
512 ppc_optional_operand_value (operand)))
519 /* Find a match for INSN in the opcode table, given machine DIALECT. */
521 static const struct powerpc_opcode *
522 lookup_powerpc (unsigned long insn, ppc_cpu_t dialect)
524 const struct powerpc_opcode *opcode, *opcode_end, *last;
527 /* Get the major opcode of the instruction. */
530 /* Find the first match in the opcode table for this major opcode. */
531 opcode_end = powerpc_opcodes + powerpc_opcd_indices[op + 1];
533 for (opcode = powerpc_opcodes + powerpc_opcd_indices[op];
537 const unsigned char *opindex;
538 const struct powerpc_operand *operand;
541 if ((insn & opcode->mask) != opcode->opcode
542 || ((dialect & PPC_OPCODE_ANY) == 0
543 && ((opcode->flags & dialect) == 0
544 || (opcode->deprecated & dialect) != 0)))
547 /* Check validity of operands. */
549 for (opindex = opcode->operands; *opindex != 0; opindex++)
551 operand = powerpc_operands + *opindex;
552 if (operand->extract)
553 (*operand->extract) (insn, dialect, &invalid);
558 if ((dialect & PPC_OPCODE_RAW) == 0)
561 /* The raw machine insn is one that is not a specialization. */
563 || (last->mask & ~opcode->mask) != 0)
570 /* Find a match for INSN in the VLE opcode table. */
572 static const struct powerpc_opcode *
573 lookup_vle (unsigned long insn)
575 const struct powerpc_opcode *opcode;
576 const struct powerpc_opcode *opcode_end;
580 if (op >= 0x20 && op <= 0x37)
582 /* This insn has a 4-bit opcode. */
585 seg = VLE_OP_TO_SEG (op);
587 /* Find the first match in the opcode table for this major opcode. */
588 opcode_end = vle_opcodes + vle_opcd_indices[seg + 1];
589 for (opcode = vle_opcodes + vle_opcd_indices[seg];
593 unsigned long table_opcd = opcode->opcode;
594 unsigned long table_mask = opcode->mask;
595 bfd_boolean table_op_is_short = PPC_OP_SE_VLE(table_mask);
597 const unsigned char *opindex;
598 const struct powerpc_operand *operand;
602 if (table_op_is_short)
604 if ((insn2 & table_mask) != table_opcd)
607 /* Check validity of operands. */
609 for (opindex = opcode->operands; *opindex != 0; ++opindex)
611 operand = powerpc_operands + *opindex;
612 if (operand->extract)
613 (*operand->extract) (insn, (ppc_cpu_t)0, &invalid);
624 /* Find a match for INSN in the SPE2 opcode table. */
626 static const struct powerpc_opcode *
627 lookup_spe2 (unsigned long insn)
629 const struct powerpc_opcode *opcode, *opcode_end;
630 unsigned op, xop, seg;
635 /* This is not SPE2 insn.
636 * All SPE2 instructions have OP=4 and differs by XOP */
639 xop = SPE2_XOP (insn);
640 seg = SPE2_XOP_TO_SEG (xop);
642 /* Find the first match in the opcode table for this major opcode. */
643 opcode_end = spe2_opcodes + spe2_opcd_indices[seg + 1];
644 for (opcode = spe2_opcodes + spe2_opcd_indices[seg];
648 unsigned long table_opcd = opcode->opcode;
649 unsigned long table_mask = opcode->mask;
651 const unsigned char *opindex;
652 const struct powerpc_operand *operand;
656 if ((insn2 & table_mask) != table_opcd)
659 /* Check validity of operands. */
661 for (opindex = opcode->operands; *opindex != 0; ++opindex)
663 operand = powerpc_operands + *opindex;
664 if (operand->extract)
665 (*operand->extract) (insn, (ppc_cpu_t)0, &invalid);
676 /* Print a PowerPC or POWER instruction. */
679 print_insn_powerpc (bfd_vma memaddr,
680 struct disassemble_info *info,
687 const struct powerpc_opcode *opcode;
688 bfd_boolean insn_is_short;
690 status = (*info->read_memory_func) (memaddr, buffer, 4, info);
693 /* The final instruction may be a 2-byte VLE insn. */
694 if ((dialect & PPC_OPCODE_VLE) != 0)
696 /* Clear buffer so unused bytes will not have garbage in them. */
697 buffer[0] = buffer[1] = buffer[2] = buffer[3] = 0;
698 status = (*info->read_memory_func) (memaddr, buffer, 2, info);
701 (*info->memory_error_func) (status, memaddr, info);
707 (*info->memory_error_func) (status, memaddr, info);
713 insn = bfd_getb32 (buffer);
715 insn = bfd_getl32 (buffer);
717 /* Get the major opcode of the insn. */
719 insn_is_short = FALSE;
720 if ((dialect & PPC_OPCODE_VLE) != 0)
722 opcode = lookup_vle (insn);
724 insn_is_short = PPC_OP_SE_VLE(opcode->mask);
726 if (opcode == NULL && (dialect & PPC_OPCODE_SPE2) != 0)
727 opcode = lookup_spe2 (insn);
729 opcode = lookup_powerpc (insn, dialect & ~PPC_OPCODE_ANY);
730 if (opcode == NULL && (dialect & PPC_OPCODE_ANY) != 0)
731 opcode = lookup_powerpc (insn, dialect);
735 const unsigned char *opindex;
736 const struct powerpc_operand *operand;
741 if (opcode->operands[0] != 0)
742 (*info->fprintf_func) (info->stream, "%-7s ", opcode->name);
744 (*info->fprintf_func) (info->stream, "%s", opcode->name);
747 /* The operands will be fetched out of the 16-bit instruction. */
750 /* Now extract and print the operands. */
754 for (opindex = opcode->operands; *opindex != 0; opindex++)
758 operand = powerpc_operands + *opindex;
760 /* Operands that are marked FAKE are simply ignored. We
761 already made sure that the extract function considered
762 the instruction to be valid. */
763 if ((operand->flags & PPC_OPERAND_FAKE) != 0)
766 /* If all of the optional operands have the value zero,
767 then don't print any of them. */
768 if ((operand->flags & PPC_OPERAND_OPTIONAL) != 0)
770 if (skip_optional < 0)
771 skip_optional = skip_optional_operands (opindex, insn,
777 value = operand_value_powerpc (operand, insn, dialect);
781 (*info->fprintf_func) (info->stream, ",");
785 /* Print the operand as directed by the flags. */
786 if ((operand->flags & PPC_OPERAND_GPR) != 0
787 || ((operand->flags & PPC_OPERAND_GPR_0) != 0 && value != 0))
788 (*info->fprintf_func) (info->stream, "r%ld", value);
789 else if ((operand->flags & PPC_OPERAND_FPR) != 0)
790 (*info->fprintf_func) (info->stream, "f%ld", value);
791 else if ((operand->flags & PPC_OPERAND_VR) != 0)
792 (*info->fprintf_func) (info->stream, "v%ld", value);
793 else if ((operand->flags & PPC_OPERAND_VSR) != 0)
794 (*info->fprintf_func) (info->stream, "vs%ld", value);
795 else if ((operand->flags & PPC_OPERAND_RELATIVE) != 0)
796 (*info->print_address_func) (memaddr + value, info);
797 else if ((operand->flags & PPC_OPERAND_ABSOLUTE) != 0)
798 (*info->print_address_func) ((bfd_vma) value & 0xffffffff, info);
799 else if ((operand->flags & PPC_OPERAND_FSL) != 0)
800 (*info->fprintf_func) (info->stream, "fsl%ld", value);
801 else if ((operand->flags & PPC_OPERAND_FCR) != 0)
802 (*info->fprintf_func) (info->stream, "fcr%ld", value);
803 else if ((operand->flags & PPC_OPERAND_UDI) != 0)
804 (*info->fprintf_func) (info->stream, "%ld", value);
805 else if ((operand->flags & PPC_OPERAND_CR_REG) != 0
806 && (((dialect & PPC_OPCODE_PPC) != 0)
807 || ((dialect & PPC_OPCODE_VLE) != 0)))
808 (*info->fprintf_func) (info->stream, "cr%ld", value);
809 else if (((operand->flags & PPC_OPERAND_CR_BIT) != 0)
810 && (((dialect & PPC_OPCODE_PPC) != 0)
811 || ((dialect & PPC_OPCODE_VLE) != 0)))
813 static const char *cbnames[4] = { "lt", "gt", "eq", "so" };
819 (*info->fprintf_func) (info->stream, "4*cr%d+", cr);
821 (*info->fprintf_func) (info->stream, "%s", cbnames[cc]);
824 (*info->fprintf_func) (info->stream, "%d", (int) value);
828 (*info->fprintf_func) (info->stream, ")");
832 if ((operand->flags & PPC_OPERAND_PARENS) == 0)
836 (*info->fprintf_func) (info->stream, "(");
841 /* We have found and printed an instruction.
842 If it was a short VLE instruction we have more to do. */
849 /* Otherwise, return. */
853 /* We could not find a match. */
854 (*info->fprintf_func) (info->stream, ".long 0x%lx", insn);
859 const disasm_options_t *
860 disassembler_options_powerpc (void)
862 static disasm_options_t *opts = NULL;
866 size_t i, num_options = ARRAY_SIZE (ppc_opts);
867 opts = XNEW (disasm_options_t);
868 opts->name = XNEWVEC (const char *, num_options + 1);
869 for (i = 0; i < num_options; i++)
870 opts->name[i] = ppc_opts[i].opt;
871 /* The array we return must be NULL terminated. */
872 opts->name[i] = NULL;
873 opts->description = NULL;
880 print_ppc_disassembler_options (FILE *stream)
884 fprintf (stream, _("\n\
885 The following PPC specific disassembler options are supported for use with\n\
888 for (col = 0, i = 0; i < ARRAY_SIZE (ppc_opts); i++)
890 col += fprintf (stream, " %s,", ppc_opts[i].opt);
893 fprintf (stream, "\n");
897 fprintf (stream, "\n");