1 /* Altera Nios II disassemble routines
2 Copyright (C) 2012-2017 Free Software Foundation, Inc.
3 Contributed by Nigel Gray (ngray@altera.com).
4 Contributed by Mentor Graphics, Inc.
6 This file is part of the GNU opcodes library.
8 This library is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 3, or (at your option)
13 It is distributed in the hope that it will be useful, but WITHOUT
14 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
15 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
16 License for more details.
18 You should have received a copy of the GNU General Public License
19 along with this file; see the file COPYING. If not, write to the
20 Free Software Foundation, 51 Franklin Street - Fifth Floor, Boston,
21 MA 02110-1301, USA. */
25 #include "opcode/nios2.h"
26 #include "libiberty.h"
30 /* No symbol table is available when this code runs out in an embedded
31 system as when it is used for disassembler support in a monitor. */
32 #if !defined(EMBEDDED_ENV)
33 #define SYMTAB_AVAILABLE 1
35 #include "elf/nios2.h"
38 /* Default length of Nios II instruction in bytes. */
41 /* Data structures used by the opcode hash table. */
42 typedef struct _nios2_opcode_hash
44 const struct nios2_opcode *opcode;
45 struct _nios2_opcode_hash *next;
48 /* Hash table size. */
49 #define OPCODE_HASH_SIZE (IW_R1_OP_UNSHIFTED_MASK + 1)
51 /* Extract the opcode from an instruction word. */
53 nios2_r1_extract_opcode (unsigned int x)
55 return GET_IW_R1_OP (x);
59 nios2_r2_extract_opcode (unsigned int x)
61 return GET_IW_R2_OP (x);
64 /* We maintain separate hash tables for R1 and R2 opcodes, and pseudo-ops
65 are stored in a different table than regular instructions. */
67 typedef struct _nios2_disassembler_state
69 const struct nios2_opcode *opcodes;
70 const int *num_opcodes;
71 unsigned int (*extract_opcode) (unsigned int);
72 nios2_opcode_hash *hash[OPCODE_HASH_SIZE];
73 nios2_opcode_hash *ps_hash[OPCODE_HASH_SIZE];
74 const struct nios2_opcode *nop;
76 } nios2_disassembler_state;
78 static nios2_disassembler_state
79 nios2_r1_disassembler_state = {
81 &nios2_num_r1_opcodes,
82 nios2_r1_extract_opcode,
89 static nios2_disassembler_state
90 nios2_r2_disassembler_state = {
92 &nios2_num_r2_opcodes,
93 nios2_r2_extract_opcode,
100 /* Function to initialize the opcode hash table. */
102 nios2_init_opcode_hash (nios2_disassembler_state *state)
105 register const struct nios2_opcode *op;
107 for (i = 0; i < OPCODE_HASH_SIZE; i++)
108 for (op = state->opcodes; op < &state->opcodes[*(state->num_opcodes)]; op++)
110 nios2_opcode_hash *new_hash;
111 nios2_opcode_hash **bucket = NULL;
113 if ((op->pinfo & NIOS2_INSN_MACRO) == NIOS2_INSN_MACRO)
115 if (i == state->extract_opcode (op->match)
116 && (op->pinfo & (NIOS2_INSN_MACRO_MOV | NIOS2_INSN_MACRO_MOVI)
119 bucket = &(state->ps_hash[i]);
120 if (strcmp (op->name, "nop") == 0)
124 else if (i == state->extract_opcode (op->match))
125 bucket = &(state->hash[i]);
130 (nios2_opcode_hash *) malloc (sizeof (nios2_opcode_hash));
131 if (new_hash == NULL)
134 "error allocating memory...broken disassembler\n");
137 new_hash->opcode = op;
138 new_hash->next = NULL;
140 bucket = &((*bucket)->next);
146 #ifdef DEBUG_HASHTABLE
147 for (i = 0; i < OPCODE_HASH_SIZE; ++i)
149 nios2_opcode_hash *tmp_hash = state->hash[i];
150 printf ("index: 0x%02X ops: ", i);
151 while (tmp_hash != NULL)
153 printf ("%s ", tmp_hash->opcode->name);
154 tmp_hash = tmp_hash->next;
159 for (i = 0; i < OPCODE_HASH_SIZE; ++i)
161 nios2_opcode_hash *tmp_hash = state->ps_hash[i];
162 printf ("index: 0x%02X ops: ", i);
163 while (tmp_hash != NULL)
165 printf ("%s ", tmp_hash->opcode->name);
166 tmp_hash = tmp_hash->next;
170 #endif /* DEBUG_HASHTABLE */
173 /* Return a pointer to an nios2_opcode struct for a given instruction
174 word OPCODE for bfd machine MACH, or NULL if there is an error. */
175 const struct nios2_opcode *
176 nios2_find_opcode_hash (unsigned long opcode, unsigned long mach)
178 nios2_opcode_hash *entry;
179 nios2_disassembler_state *state;
181 /* Select the right instruction set, hash tables, and opcode accessor
182 for the mach variant. */
183 if (mach == bfd_mach_nios2r2)
184 state = &nios2_r2_disassembler_state;
186 state = &nios2_r1_disassembler_state;
188 /* Build a hash table to shorten the search time. */
190 nios2_init_opcode_hash (state);
192 /* Check for NOP first. Both NOP and MOV are macros that expand into
193 an ADD instruction, and we always want to give priority to NOP. */
194 if (state->nop->match == (opcode & state->nop->mask))
197 /* First look in the pseudo-op hashtable. */
198 for (entry = state->ps_hash[state->extract_opcode (opcode)];
199 entry; entry = entry->next)
200 if (entry->opcode->match == (opcode & entry->opcode->mask))
201 return entry->opcode;
203 /* Otherwise look in the main hashtable. */
204 for (entry = state->hash[state->extract_opcode (opcode)];
205 entry; entry = entry->next)
206 if (entry->opcode->match == (opcode & entry->opcode->mask))
207 return entry->opcode;
212 /* There are 32 regular registers, 32 coprocessor registers,
213 and 32 control registers. */
214 #define NUMREGNAMES 32
216 /* Return a pointer to the base of the coprocessor register name array. */
217 static struct nios2_reg *
218 nios2_coprocessor_regs (void)
220 static struct nios2_reg *cached = NULL;
225 for (i = NUMREGNAMES; i < nios2_num_regs; i++)
226 if (!strcmp (nios2_regs[i].name, "c0"))
228 cached = nios2_regs + i;
236 /* Return a pointer to the base of the control register name array. */
237 static struct nios2_reg *
238 nios2_control_regs (void)
240 static struct nios2_reg *cached = NULL;
245 for (i = NUMREGNAMES; i < nios2_num_regs; i++)
246 if (!strcmp (nios2_regs[i].name, "status"))
248 cached = nios2_regs + i;
256 /* Helper routine to report internal errors. */
258 bad_opcode (const struct nios2_opcode *op)
260 fprintf (stderr, "Internal error: broken opcode descriptor for `%s %s'\n",
265 /* The function nios2_print_insn_arg uses the character pointed
266 to by ARGPTR to determine how it print the next token or separator
267 character in the arguments to an instruction. */
269 nios2_print_insn_arg (const char *argptr,
270 unsigned long opcode, bfd_vma address,
271 disassemble_info *info,
272 const struct nios2_opcode *op)
275 struct nios2_reg *reg_base;
282 (*info->fprintf_func) (info->stream, "%c", *argptr);
286 /* Control register index. */
290 i = GET_IW_R_IMM5 (opcode);
293 i = GET_IW_F3X6L5_IMM5 (opcode);
298 reg_base = nios2_control_regs ();
299 (*info->fprintf_func) (info->stream, "%s", reg_base[i].name);
303 reg_base = nios2_regs;
307 i = GET_IW_R_C (opcode);
310 i = GET_IW_CUSTOM_C (opcode);
311 if (GET_IW_CUSTOM_READC (opcode) == 0)
312 reg_base = nios2_coprocessor_regs ();
316 i = GET_IW_F3X6L5_C (opcode);
319 i = GET_IW_F3X8_C (opcode);
320 if (GET_IW_F3X8_READC (opcode) == 0)
321 reg_base = nios2_coprocessor_regs ();
324 i = GET_IW_F2_B (opcode);
330 (*info->fprintf_func) (info->stream, "%s", reg_base[i].name);
332 (*info->fprintf_func) (info->stream, "unknown");
336 reg_base = nios2_regs;
340 i = GET_IW_R_A (opcode);
343 i = GET_IW_I_A (opcode);
346 i = GET_IW_CUSTOM_A (opcode);
347 if (GET_IW_CUSTOM_READA (opcode) == 0)
348 reg_base = nios2_coprocessor_regs ();
351 i = GET_IW_F2I16_A (opcode);
353 case iw_F2X4I12_type:
354 i = GET_IW_F2X4I12_A (opcode);
356 case iw_F1X4I12_type:
357 i = GET_IW_F1X4I12_A (opcode);
359 case iw_F1X4L17_type:
360 i = GET_IW_F1X4L17_A (opcode);
364 i = GET_IW_F3X6L5_A (opcode);
366 case iw_F2X6L10_type:
367 i = GET_IW_F2X6L10_A (opcode);
370 i = GET_IW_F3X8_A (opcode);
371 if (GET_IW_F3X8_READA (opcode) == 0)
372 reg_base = nios2_coprocessor_regs ();
375 i = GET_IW_F1X1_A (opcode);
378 i = 27; /* Implicit stack pointer reference. */
381 i = GET_IW_F2_A (opcode);
387 (*info->fprintf_func) (info->stream, "%s", reg_base[i].name);
389 (*info->fprintf_func) (info->stream, "unknown");
393 reg_base = nios2_regs;
397 i = GET_IW_R_B (opcode);
400 i = GET_IW_I_B (opcode);
403 i = GET_IW_CUSTOM_B (opcode);
404 if (GET_IW_CUSTOM_READB (opcode) == 0)
405 reg_base = nios2_coprocessor_regs ();
408 i = GET_IW_F2I16_B (opcode);
410 case iw_F2X4I12_type:
411 i = GET_IW_F2X4I12_B (opcode);
415 i = GET_IW_F3X6L5_B (opcode);
417 case iw_F2X6L10_type:
418 i = GET_IW_F2X6L10_B (opcode);
421 i = GET_IW_F3X8_B (opcode);
422 if (GET_IW_F3X8_READB (opcode) == 0)
423 reg_base = nios2_coprocessor_regs ();
426 i = GET_IW_F1I5_B (opcode);
429 i = GET_IW_F2_B (opcode);
438 (*info->fprintf_func) (info->stream, "%s", reg_base[i].name);
440 (*info->fprintf_func) (info->stream, "unknown");
447 i = GET_IW_T1I7_A3 (opcode);
450 i = GET_IW_T2X1L3_B3 (opcode);
453 i = GET_IW_T2X1I3_B3 (opcode);
456 i = GET_IW_T3X1_C3 (opcode);
459 if (op->num_args == 3)
460 i = GET_IW_T2X3_A3 (opcode);
462 i = GET_IW_T2X3_B3 (opcode);
467 i = nios2_r2_reg3_mappings[i];
468 (*info->fprintf_func) (info->stream, "%s", nios2_regs[i].name);
472 /* 6-bit unsigned immediate with no shift. */
476 i = GET_IW_T1X1I6_IMM6 (opcode);
481 (*info->fprintf_func) (info->stream, "%ld", i);
485 /* 6-bit unsigned immediate with 2-bit shift. */
489 i = GET_IW_T1X1I6_IMM6 (opcode) << 2;
494 (*info->fprintf_func) (info->stream, "%ld", i);
501 i = GET_IW_T1I7_A3 (opcode);
504 i = GET_IW_T2I4_A3 (opcode);
507 i = GET_IW_T2X1L3_A3 (opcode);
510 i = GET_IW_T2X1I3_A3 (opcode);
513 i = GET_IW_T3X1_A3 (opcode);
516 i = GET_IW_T2X3_A3 (opcode);
519 i = GET_IW_T1X1I6_A3 (opcode);
524 i = nios2_r2_reg3_mappings[i];
525 (*info->fprintf_func) (info->stream, "%s", nios2_regs[i].name);
532 i = GET_IW_T2I4_B3 (opcode);
535 i = GET_IW_T3X1_B3 (opcode);
538 i = GET_IW_T2X3_B3 (opcode);
543 i = nios2_r2_reg3_mappings[i];
544 (*info->fprintf_func) (info->stream, "%s", nios2_regs[i].name);
548 /* 16-bit signed immediate. */
552 i = (signed) (GET_IW_I_IMM16 (opcode) << 16) >> 16;
555 i = (signed) (GET_IW_F2I16_IMM16 (opcode) << 16) >> 16;
560 (*info->fprintf_func) (info->stream, "%ld", i);
564 /* 12-bit signed immediate. */
567 case iw_F2X4I12_type:
568 i = (signed) (GET_IW_F2X4I12_IMM12 (opcode) << 20) >> 20;
570 case iw_F1X4I12_type:
571 i = (signed) (GET_IW_F1X4I12_IMM12 (opcode) << 20) >> 20;
576 (*info->fprintf_func) (info->stream, "%ld", i);
580 /* 16-bit unsigned immediate. */
584 i = GET_IW_I_IMM16 (opcode);
587 i = GET_IW_F2I16_IMM16 (opcode);
592 (*info->fprintf_func) (info->stream, "%ld", i);
596 /* 7-bit unsigned immediate with 2-bit shift. */
600 i = GET_IW_T1I7_IMM7 (opcode) << 2;
603 i = GET_IW_X1I7_IMM7 (opcode) << 2;
608 (*info->fprintf_func) (info->stream, "%ld", i);
612 /* 5-bit unsigned immediate with 2-bit shift. */
616 i = GET_IW_F1I5_IMM5 (opcode) << 2;
621 (*info->fprintf_func) (info->stream, "%ld", i);
625 /* 4-bit unsigned immediate with 2-bit shift. */
629 i = GET_IW_T2I4_IMM4 (opcode) << 2;
632 i = GET_IW_L5I4X1_IMM4 (opcode) << 2;
637 (*info->fprintf_func) (info->stream, "%ld", i);
641 /* 4-bit unsigned immediate with 1-bit shift. */
645 i = GET_IW_T2I4_IMM4 (opcode) << 1;
650 (*info->fprintf_func) (info->stream, "%ld", i);
654 /* 4-bit unsigned immediate without shift. */
658 i = GET_IW_T2I4_IMM4 (opcode);
663 (*info->fprintf_func) (info->stream, "%ld", i);
667 /* 16-bit signed immediate address offset. */
671 i = (signed) (GET_IW_I_IMM16 (opcode) << 16) >> 16;
674 i = (signed) (GET_IW_F2I16_IMM16 (opcode) << 16) >> 16;
679 address = address + 4 + i;
680 (*info->print_address_func) (address, info);
684 /* 10-bit signed address offset with 1-bit shift. */
688 i = (signed) (GET_IW_I10_IMM10 (opcode) << 22) >> 21;
693 address = address + 2 + i;
694 (*info->print_address_func) (address, info);
698 /* 7-bit signed address offset with 1-bit shift. */
702 i = (signed) (GET_IW_T1I7_IMM7 (opcode) << 25) >> 24;
707 address = address + 2 + i;
708 (*info->print_address_func) (address, info);
712 /* 5-bit unsigned immediate. */
716 i = GET_IW_R_IMM5 (opcode);
719 i = GET_IW_F3X6L5_IMM5 (opcode);
721 case iw_F2X6L10_type:
722 i = GET_IW_F2X6L10_MSB (opcode);
725 i = GET_IW_X2L5_IMM5 (opcode);
730 (*info->fprintf_func) (info->stream, "%ld", i);
734 /* Second 5-bit unsigned immediate field. */
737 case iw_F2X6L10_type:
738 i = GET_IW_F2X6L10_LSB (opcode);
743 (*info->fprintf_func) (info->stream, "%ld", i);
747 /* 8-bit unsigned immediate. */
751 i = GET_IW_CUSTOM_N (opcode);
754 i = GET_IW_F3X8_N (opcode);
759 (*info->fprintf_func) (info->stream, "%lu", i);
763 /* 26-bit unsigned immediate. */
767 i = GET_IW_J_IMM26 (opcode);
770 i = GET_IW_L26_IMM26 (opcode);
775 /* This translates to an address because it's only used in call
777 address = (address & 0xf0000000) | (i << 2);
778 (*info->print_address_func) (address, info);
782 /* Encoded enumeration for addi.n/subi.n. */
786 i = nios2_r2_asi_n_mappings[GET_IW_T2X1I3_IMM3 (opcode)];
791 (*info->fprintf_func) (info->stream, "%lu", i);
795 /* Encoded enumeration for slli.n/srli.n. */
799 i = nios2_r2_shi_n_mappings[GET_IW_T2X1I3_IMM3 (opcode)];
804 (*info->fprintf_func) (info->stream, "%lu", i);
808 /* Encoded enumeration for andi.n. */
812 i = nios2_r2_andi_n_mappings[GET_IW_T2I4_IMM4 (opcode)];
817 (*info->fprintf_func) (info->stream, "%lu", i);
821 /* Encoded enumeration for movi.n. */
825 i = GET_IW_T1I7_IMM7 (opcode);
836 (*info->fprintf_func) (info->stream, "%ld", i);
841 unsigned long reglist = 0;
847 case iw_F1X4L17_type:
848 /* Encoding for ldwm/stwm. */
849 i = GET_IW_F1X4L17_REGMASK (opcode);
850 if (GET_IW_F1X4L17_RS (opcode))
852 reglist = ((i << 14) & 0x00ffc000);
854 reglist |= (1 << 28);
856 reglist |= (1 << 31);
860 dir = GET_IW_F1X4L17_REGMASK (opcode) ? 1 : -1;
864 /* Encoding for push.n/pop.n. */
865 reglist |= (1 << 31);
866 if (GET_IW_L5I4X1_FP (opcode))
867 reglist |= (1 << 28);
868 if (GET_IW_L5I4X1_CS (opcode))
870 int val = GET_IW_L5I4X1_REGRANGE (opcode);
871 reglist |= nios2_r2_reg_range_mappings[val];
873 dir = (op->match == MATCH_R2_POP_N ? 1 : -1);
881 (*info->fprintf_func) (info->stream, "{");
882 for (k = (dir == 1 ? 0 : 31);
883 (dir == 1 && k < 32) || (dir == -1 && k >= 0);
885 if (reglist & (1 << k))
888 (*info->fprintf_func) (info->stream, ",");
891 (*info->fprintf_func) (info->stream, "%s", nios2_regs[k].name);
893 (*info->fprintf_func) (info->stream, "}");
898 /* Base register and options for ldwm/stwm. */
901 case iw_F1X4L17_type:
902 if (GET_IW_F1X4L17_ID (opcode) == 0)
903 (*info->fprintf_func) (info->stream, "--");
905 i = GET_IW_F1X4I12_A (opcode);
906 (*info->fprintf_func) (info->stream, "(%s)",
907 nios2_builtin_regs[i].name);
909 if (GET_IW_F1X4L17_ID (opcode))
910 (*info->fprintf_func) (info->stream, "++");
911 if (GET_IW_F1X4L17_WB (opcode))
912 (*info->fprintf_func) (info->stream, ",writeback");
913 if (GET_IW_F1X4L17_PC (opcode))
914 (*info->fprintf_func) (info->stream, ",ret");
922 (*info->fprintf_func) (info->stream, "unknown");
928 /* nios2_disassemble does all the work of disassembling a Nios II
929 instruction opcode. */
931 nios2_disassemble (bfd_vma address, unsigned long opcode,
932 disassemble_info *info)
934 const struct nios2_opcode *op;
936 info->bytes_per_line = INSNLEN;
937 info->bytes_per_chunk = INSNLEN;
938 info->display_endian = info->endian;
939 info->insn_info_valid = 1;
940 info->branch_delay_insns = 0;
942 info->insn_type = dis_nonbranch;
946 /* Find the major opcode and use this to disassemble
947 the instruction and its arguments. */
948 op = nios2_find_opcode_hash (opcode, info->mach);
952 const char *argstr = op->args;
953 (*info->fprintf_func) (info->stream, "%s", op->name);
954 if (argstr != NULL && *argstr != '\0')
956 (*info->fprintf_func) (info->stream, "\t");
957 while (*argstr != '\0')
959 nios2_print_insn_arg (argstr, opcode, address, info, op);
963 /* Tell the caller how far to advance the program counter. */
964 info->bytes_per_chunk = op->size;
969 /* Handle undefined instructions. */
970 info->insn_type = dis_noninsn;
971 (*info->fprintf_func) (info->stream, "0x%lx", opcode);
977 /* print_insn_nios2 is the main disassemble function for Nios II.
978 The function diassembler(abfd) (source in disassemble.c) returns a
979 pointer to this either print_insn_big_nios2 or
980 print_insn_little_nios2, which in turn call this function when the
981 bfd machine type is Nios II. print_insn_nios2 reads the
982 instruction word at the address given, and prints the disassembled
983 instruction on the stream info->stream using info->fprintf_func. */
986 print_insn_nios2 (bfd_vma address, disassemble_info *info,
987 enum bfd_endian endianness)
989 bfd_byte buffer[INSNLEN];
992 status = (*info->read_memory_func) (address, buffer, INSNLEN, info);
996 if (endianness == BFD_ENDIAN_BIG)
997 insn = (unsigned long) bfd_getb32 (buffer);
999 insn = (unsigned long) bfd_getl32 (buffer);
1000 return nios2_disassemble (address, insn, info);
1003 /* We might have a 16-bit R2 instruction at the end of memory. Try that. */
1004 if (info->mach == bfd_mach_nios2r2)
1006 status = (*info->read_memory_func) (address, buffer, 2, info);
1010 if (endianness == BFD_ENDIAN_BIG)
1011 insn = (unsigned long) bfd_getb16 (buffer);
1013 insn = (unsigned long) bfd_getl16 (buffer);
1014 return nios2_disassemble (address, insn, info);
1018 /* If we got here, we couldn't read anything. */
1019 (*info->memory_error_func) (status, address, info);
1023 /* These two functions are the main entry points, accessed from
1026 print_insn_big_nios2 (bfd_vma address, disassemble_info *info)
1028 return print_insn_nios2 (address, info, BFD_ENDIAN_BIG);
1032 print_insn_little_nios2 (bfd_vma address, disassemble_info *info)
1034 return print_insn_nios2 (address, info, BFD_ENDIAN_LITTLE);