1 /* NDS32-specific support for 32-bit ELF.
2 Copyright (C) 2012-2018 Free Software Foundation, Inc.
3 Contributed by Andes Technology Corporation.
5 This file is part of BFD, the Binary File Descriptor library.
7 This program is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 3 of the License, or
10 (at your option) any later version.
12 This program is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
17 You should have received a copy of the GNU General Public License
18 along with this program; if not, write to the Free Software
19 Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, MA
28 #include "safe-ctype.h"
29 #include "libiberty.h"
34 #include "opcode/nds32.h"
35 #include "nds32-asm.h"
37 /* There at at most MAX_LEX_NUM lexical elements in a syntax. */
38 #define MAX_LEX_NUM 32
39 /* A operand in syntax string should be at most this long. */
40 #define MAX_LEX_LEN 64
41 /* The max length of a keyword can be. */
42 #define MAX_KEYWORD_LEN 32
43 /* This LEX is a plain char or operand. */
44 #define IS_LEX_CHAR(c) (((c) >> 7) == 0)
45 #define LEX_SET_FIELD(c) ((c) | SYN_FIELD)
46 #define LEX_GET_FIELD(c) operand_fields[((c) & 0xff)]
47 /* Get the char in this lexical element. */
48 #define LEX_CHAR(c) ((c) & 0xff)
50 #define USRIDX(group, usr) ((group) | ((usr) << 5))
51 #define SRIDX(major, minor, ext) \
52 (((major) << 7) | ((minor) << 3) | (ext))
54 static int parse_re (struct nds32_asm_desc *, struct nds32_asm_insn *,
56 static int parse_re2 (struct nds32_asm_desc *, struct nds32_asm_insn *,
58 static int parse_fe5 (struct nds32_asm_desc *, struct nds32_asm_insn *,
60 static int parse_pi5 (struct nds32_asm_desc *, struct nds32_asm_insn *,
62 static int parse_aext_reg (char **, int *, int);
63 static int parse_a30b20 (struct nds32_asm_desc *, struct nds32_asm_insn *,
65 static int parse_rt21 (struct nds32_asm_desc *, struct nds32_asm_insn *,
67 static int parse_rte_start (struct nds32_asm_desc *, struct nds32_asm_insn *,
69 static int parse_rte_end (struct nds32_asm_desc *, struct nds32_asm_insn *,
71 static int parse_rte69_start (struct nds32_asm_desc *, struct nds32_asm_insn *,
73 static int parse_rte69_end (struct nds32_asm_desc *, struct nds32_asm_insn *,
75 static int parse_im5_ip (struct nds32_asm_desc *, struct nds32_asm_insn *,
77 static int parse_im5_mr (struct nds32_asm_desc *, struct nds32_asm_insn *,
79 static int parse_im6_ip (struct nds32_asm_desc *, struct nds32_asm_insn *,
81 static int parse_im6_iq (struct nds32_asm_desc *, struct nds32_asm_insn *,
83 static int parse_im6_mr (struct nds32_asm_desc *, struct nds32_asm_insn *,
85 static int parse_im6_ms (struct nds32_asm_desc *, struct nds32_asm_insn *,
88 /* These are operand prefixes for input/output semantic.
95 Field table for operands and bit-fields. */
97 const field_t operand_fields[] =
99 {"rt", 20, 5, 0, HW_GPR, NULL},
100 {"ra", 15, 5, 0, HW_GPR, NULL},
101 {"rb", 10, 5, 0, HW_GPR, NULL},
102 {"rd", 5, 5, 0, HW_GPR, NULL},
103 {"re", 10, 5, 0, HW_GPR, parse_re}, /* lmw smw lmwa smwa. */
104 {"fst", 20, 5, 0, HW_FSR, NULL},
105 {"fsa", 15, 5, 0, HW_FSR, NULL},
106 {"fsb", 10, 5, 0, HW_FSR, NULL},
107 {"fdt", 20, 5, 0, HW_FDR, NULL},
108 {"fda", 15, 5, 0, HW_FDR, NULL},
109 {"fdb", 10, 5, 0, HW_FDR, NULL},
110 {"cprt", 20, 5, 0, HW_CPR, NULL},
111 {"cp", 13, 2, 0, HW_CP, NULL},
112 {"sh", 5, 5, 0, HW_UINT, NULL}, /* sh in ALU instructions. */
113 {"sv", 8, 2, 0, HW_UINT, NULL}, /* sv in MEM instructions. */
114 {"dt", 21, 1, 0, HW_DXR, NULL},
115 {"usr", 10, 10, 0, HW_USR, NULL}, /* User Special Registers. */
116 {"sr", 10, 10, 0, HW_SR, NULL}, /* System Registers. */
117 {"ridx", 10, 10, 0, HW_UINT, NULL}, /* Raw value for mfusr/mfsr. */
118 {"enb4", 6, 4, 0, HW_UINT, NULL}, /* Enable4 for LSMW. */
119 {"swid", 5, 15, 0, HW_UINT, NULL},
120 {"stdby_st", 5, 2, 0, HW_STANDBY_ST, NULL},
121 {"tlbop_st", 5, 5, 0, HW_TLBOP_ST, NULL},
122 {"tlbop_stx", 5, 5, 0, HW_UINT, NULL},
123 {"cctl_st0", 5, 5, 0, HW_CCTL_ST0, NULL},
124 {"cctl_st1", 5, 5, 0, HW_CCTL_ST1, NULL},
125 {"cctl_st2", 5, 5, 0, HW_CCTL_ST2, NULL},
126 {"cctl_st3", 5, 5, 0, HW_CCTL_ST3, NULL},
127 {"cctl_st4", 5, 5, 0, HW_CCTL_ST4, NULL},
128 {"cctl_st5", 5, 5, 0, HW_CCTL_ST5, NULL},
129 {"cctl_stx", 5, 5, 0, HW_UINT, NULL},
130 {"cctl_lv", 10, 1, 0, HW_CCTL_LV, NULL},
131 {"msync_st", 5, 3, 0, HW_MSYNC_ST, NULL},
132 {"msync_stx", 5, 3, 0, HW_UINT, NULL},
133 {"dpref_st", 20, 4, 0, HW_DPREF_ST, NULL},
134 {"rt5", 5, 5, 0, HW_GPR, NULL},
135 {"ra5", 0, 5, 0, HW_GPR, NULL},
136 {"rt4", 5, 4, 0, HW_GPR, NULL},
137 {"rt3", 6, 3, 0, HW_GPR, NULL},
138 {"rt38", 8, 3, 0, HW_GPR, NULL}, /* rt3 used in 38 form. */
139 {"ra3", 3, 3, 0, HW_GPR, NULL},
140 {"rb3", 0, 3, 0, HW_GPR, NULL},
141 {"rt5e", 4, 4, 1, HW_GPR, NULL}, /* for movd44. */
142 {"ra5e", 0, 4, 1, HW_GPR, NULL}, /* for movd44. */
143 {"re2", 5, 2, 0, HW_GPR, parse_re2}, /* re in push25/pop25. */
144 {"fe5", 0, 5, 2, HW_UINT, parse_fe5}, /* imm5u in lwi45.fe. */
145 {"pi5", 0, 5, 0, HW_UINT, parse_pi5}, /* imm5u in movpi45. */
146 {"abdim", 2, 3, 0, HW_ABDIM, NULL}, /* Flags for LSMW. */
147 {"abm", 2, 3, 0, HW_ABM, NULL}, /* Flags for LSMWZB. */
148 {"dtiton", 8, 2, 0, HW_DTITON, NULL},
149 {"dtitoff", 8, 2, 0, HW_DTITOFF, NULL},
151 {"i5s", 0, 5, 0, HW_INT, NULL},
152 {"i10s", 0, 10, 0, HW_INT, NULL},
153 {"i15s", 0, 15, 0, HW_INT, NULL},
154 {"i19s", 0, 19, 0, HW_INT, NULL},
155 {"i20s", 0, 20, 0, HW_INT, NULL},
156 {"i8s1", 0, 8, 1, HW_INT, NULL},
157 {"i11br3", 8, 11, 0, HW_INT, NULL},
158 {"i14s1", 0, 14, 1, HW_INT, NULL},
159 {"i15s1", 0, 15, 1, HW_INT, NULL},
160 {"i16s1", 0, 16, 1, HW_INT, NULL},
161 {"i18s1", 0, 18, 1, HW_INT, NULL},
162 {"i24s1", 0, 24, 1, HW_INT, NULL},
163 {"i8s2", 0, 8, 2, HW_INT, NULL},
164 {"i12s2", 0, 12, 2, HW_INT, NULL},
165 {"i15s2", 0, 15, 2, HW_INT, NULL},
166 {"i17s2", 0, 17, 2, HW_INT, NULL},
167 {"i19s2", 0, 19, 2, HW_INT, NULL},
168 {"i3u", 0, 3, 0, HW_UINT, NULL},
169 {"i5u", 0, 5, 0, HW_UINT, NULL},
170 {"ib5u", 10, 5, 0, HW_UINT, NULL}, /* imm5 field in ALU. */
171 {"ib5s", 10, 5, 0, HW_INT, NULL}, /* imm5 field in ALU. */
172 {"i9u", 0, 9, 0, HW_UINT, NULL}, /* for ex9.it. */
173 {"ia3u", 3, 3, 0, HW_UINT, NULL}, /* for bmski33, fexti33. */
174 {"i8u", 0, 8, 0, HW_UINT, NULL},
175 {"ib8u", 7, 8, 0, HW_UINT, NULL}, /* for ffbi. */
176 {"i15u", 0, 15, 0, HW_UINT, NULL},
177 {"i20u", 0, 20, 0, HW_UINT, NULL},
178 {"i3u1", 0, 3, 1, HW_UINT, NULL},
179 {"i9u1", 0, 9, 1, HW_UINT, NULL},
180 {"i3u2", 0, 3, 2, HW_UINT, NULL},
181 {"i6u2", 0, 6, 2, HW_UINT, NULL},
182 {"i7u2", 0, 7, 2, HW_UINT, NULL},
183 {"i5u3", 0, 5, 3, HW_UINT, NULL}, /* for pop25/pop25. */
184 {"i15s3", 0, 15, 3, HW_INT, NULL}, /* for dprefi.d. */
186 {"a_rt", 15, 5, 0, HW_GPR, NULL}, /* for audio-extension. */
187 {"a_ru", 10, 5, 0, HW_GPR, NULL}, /* for audio-extension. */
188 {"a_dx", 9, 1, 0, HW_DXR, NULL}, /* for audio-extension. */
189 {"a_a30", 16, 4, 0, HW_GPR, parse_a30b20}, /* for audio-extension. */
190 {"a_b20", 12, 4, 0, HW_GPR, parse_a30b20}, /* for audio-extension. */
191 {"a_rt21", 5, 7, 0, HW_GPR, parse_rt21}, /* for audio-extension. */
192 {"a_rte", 5, 7, 0, HW_GPR, parse_rte_start}, /* for audio-extension. */
193 {"a_rte1", 5, 7, 0, HW_GPR, parse_rte_end}, /* for audio-extension. */
194 {"a_rte69", 6, 4, 0, HW_GPR, parse_rte69_start}, /* for audio-extension. */
195 {"a_rte69_1", 6, 4, 0, HW_GPR, parse_rte69_end}, /* for audio-extension. */
196 {"dhy", 5, 2, 0, HW_AEXT_ACC, NULL}, /* for audio-extension. */
197 {"dxh", 15, 2, 0, HW_AEXT_ACC, NULL}, /* for audio-extension. */
198 {"aridx", 0, 5, 0, HW_AEXT_ARIDX, NULL}, /* for audio-extension. */
199 {"aridx2", 0, 5, 0, HW_AEXT_ARIDX2, NULL}, /* for audio-extension. */
200 {"aridxi", 16, 4, 0, HW_AEXT_ARIDXI, NULL}, /* for audio-extension. */
201 {"imm16", 0, 16, 0, HW_UINT, NULL}, /* for audio-extension. */
202 {"im5_i", 0, 5, 0, HW_AEXT_IM_I, parse_im5_ip}, /* for audio-extension. */
203 {"im5_m", 0, 5, 0, HW_AEXT_IM_M, parse_im5_mr}, /* for audio-extension. */
204 {"im6_ip", 0, 2, 0, HW_AEXT_IM_I, parse_im6_ip}, /* for audio-extension. */
205 {"im6_iq", 0, 2, 0, HW_AEXT_IM_I, parse_im6_iq}, /* for audio-extension. */
206 {"im6_mr", 2, 2, 0, HW_AEXT_IM_M, parse_im6_mr}, /* for audio-extension. */
207 {"im6_ms", 4, 2, 0, HW_AEXT_IM_M, parse_im6_ms}, /* for audio-extension. */
208 {"cp45", 4, 2, 0, HW_CP, NULL}, /* for cop-extension. */
209 {"i12u", 8, 12, 0, HW_UINT, NULL}, /* for cop-extension. */
210 {"cpi19", 6, 19, 0, HW_UINT, NULL}, /* for cop-extension. */
211 {NULL, 0, 0, 0, 0, NULL}
214 #define DEF_REG(r) (N32_BIT (r))
215 #define USE_REG(r) (N32_BIT (r))
216 #define RT(r) (r << 20)
217 #define RA(r) (r << 15)
218 #define RB(r) (r << 10)
221 struct nds32_opcode nds32_opcodes[] =
223 /* opc6_encoding table OPC_6. */
224 {"lbi", "=rt,[%ra{+%i15s}]", OP6 (LBI), 4, ATTR_ALL, 0, NULL, 0, NULL},
225 {"lhi", "=rt,[%ra{+%i15s1}]", OP6 (LHI), 4, ATTR_ALL, 0, NULL, 0, NULL},
226 {"lwi", "=rt,[%ra{+%i15s2}]", OP6 (LWI), 4, ATTR_ALL, 0, NULL, 0, NULL},
227 {"lbi.bi", "=rt,[%ra],%i15s", OP6 (LBI_BI), 4, ATTR_ALL, 0, NULL, 0, NULL},
228 {"lhi.bi", "=rt,[%ra],%i15s1", OP6 (LHI_BI), 4, ATTR_ALL, 0, NULL, 0, NULL},
229 {"lwi.bi", "=rt,[%ra],%i15s2", OP6 (LWI_BI), 4, ATTR_ALL, 0, NULL, 0, NULL},
230 {"sbi", "%rt,[%ra{+%i15s}]", OP6 (SBI), 4, ATTR_ALL, 0, NULL, 0, NULL},
231 {"shi", "%rt,[%ra{+%i15s1}]", OP6 (SHI), 4, ATTR_ALL, 0, NULL, 0, NULL},
232 {"swi", "%rt,[%ra{+%i15s2}]", OP6 (SWI), 4, ATTR_ALL, 0, NULL, 0, NULL},
233 {"sbi.bi", "%rt,[%ra],%i15s", OP6 (SBI_BI), 4, ATTR_ALL, 0, NULL, 0, NULL},
234 {"shi.bi", "%rt,[%ra],%i15s1", OP6 (SHI_BI), 4, ATTR_ALL, 0, NULL, 0, NULL},
235 {"swi.bi", "%rt,[%ra],%i15s2", OP6 (SWI_BI), 4, ATTR_ALL, 0, NULL, 0, NULL},
237 {"lbsi", "=rt,[%ra{+%i15s}]", OP6 (LBSI), 4, ATTR_ALL, 0, NULL, 0, NULL},
238 {"lhsi", "=rt,[%ra{+%i15s1}]", OP6 (LHSI), 4, ATTR_ALL, 0, NULL, 0, NULL},
239 {"lbsi.bi", "=rt,[%ra],%i15s", OP6 (LBSI_BI), 4, ATTR_ALL, 0, NULL, 0, NULL},
240 {"lhsi.bi", "=rt,[%ra],%i15s1", OP6 (LHSI_BI), 4, ATTR_ALL, 0, NULL, 0, NULL},
241 {"movi", "=rt,%i20s", OP6 (MOVI), 4, ATTR_ALL, 0, NULL, 0, NULL},
242 {"sethi", "=rt,%i20u", OP6 (SETHI), 4, ATTR_ALL, 0, NULL, 0, NULL},
243 {"addi", "=rt,%ra,%i15s", OP6 (ADDI), 4, ATTR_ALL, 0, NULL, 0, NULL},
244 {"subri", "=rt,%ra,%i15s", OP6 (SUBRI), 4, ATTR_ALL, 0, NULL, 0, NULL},
245 {"andi", "=rt,%ra,%i15u", OP6 (ANDI), 4, ATTR_ALL, 0, NULL, 0, NULL},
246 {"xori", "=rt,%ra,%i15u", OP6 (XORI), 4, ATTR_ALL, 0, NULL, 0, NULL},
247 {"ori", "=rt,%ra,%i15u", OP6 (ORI), 4, ATTR_ALL, 0, NULL, 0, NULL},
248 {"slti", "=rt,%ra,%i15s", OP6 (SLTI), 4, ATTR_ALL, 0, NULL, 0, NULL},
249 {"sltsi", "=rt,%ra,%i15s", OP6 (SLTSI), 4, ATTR_ALL, 0, NULL, 0, NULL},
250 {"bitci", "=rt,%ra,%i15u", OP6 (BITCI), 4, ATTR_V3, 0, NULL, 0, NULL},
253 {"dprefi.w", "%dpref_st,[%ra{+%i15s2}]", OP6 (DPREFI), 4, ATTR_V3MEX_V1, 0, NULL, 0, NULL},
254 {"dprefi.d", "%dpref_st,[%ra{+%i15s3}]", OP6 (DPREFI) | N32_BIT (24), 4, ATTR_V3MEX_V1, 0, NULL, 0, NULL},
256 {"lbi.gp", "=rt,[+%i19s]", OP6 (LBGP), 4, ATTR (GPREL) | ATTR_V2UP, USE_REG (29), NULL, 0, NULL},
257 {"lbsi.gp", "=rt,[+%i19s]", OP6 (LBGP) | N32_BIT (19), 4, ATTR (GPREL) | ATTR_V2UP, USE_REG (29), NULL, 0, NULL},
259 {"cplwi", "%cp,=cprt,[%ra{+%i12s2}]", OP6 (LWC), 4, 0, 0, NULL, 0, NULL},
260 {"cplwi.bi", "%cp,=cprt,[%ra],%i12s2", OP6 (LWC) | N32_BIT (12), 4, 0, 0, NULL, 0, NULL},
262 {"cpswi", "%cp,=cprt,[%ra{+%i12s2}]", OP6 (SWC), 4, 0, 0, NULL, 0, NULL},
263 {"cpswi.bi", "%cp,=cprt,[%ra],%i12s2", OP6 (SWC) | N32_BIT (12), 4, 0, 0, NULL, 0, NULL},
265 {"cpldi", "%cp,%cprt,[%ra{+%i12s2}]", OP6 (LDC), 4, 0, 0, NULL, 0, NULL},
266 {"cpldi.bi", "%cp,%cprt,[%ra],%i12s2", OP6 (LDC) | N32_BIT (12), 4, 0, 0, NULL, 0, NULL},
268 {"cpsdi", "%cp,%cprt,[%ra{+%i12s2}]", OP6 (SDC), 4, 0, 0, NULL, 0, NULL},
269 {"cpsdi.bi", "%cp,%cprt,[%ra],%i12s2", OP6 (SDC) | N32_BIT (12), 4, 0, 0, NULL, 0, NULL},
271 {"lmw", "%abdim %rt,[%ra],%re{,%enb4}", LSMW (LSMW), 4, ATTR_ALL, 0, NULL, 0, NULL},
272 {"lmwa", "%abdim %rt,[%ra],%re{,%enb4}", LSMW (LSMWA), 4, ATTR_V3MEX_V2, 0, NULL, 0, NULL},
273 {"lmwzb", "%abm %rt,[%ra],%re{,%enb4}", LSMW (LSMWZB), 4, ATTR (STR_EXT), 0, NULL, 0, NULL},
274 {"smw", "%abdim %rt,[%ra],%re{,%enb4}", LSMW (LSMW) | N32_BIT (5), 4, ATTR_ALL, 0, NULL, 0, NULL},
275 {"smwa", "%abdim %rt,[%ra],%re{,%enb4}", LSMW (LSMWA) | N32_BIT (5), 4, ATTR_V3MEX_V2, 0, NULL, 0, NULL},
276 {"smwzb", "%abm %rt,[%ra],%re{,%enb4}", LSMW (LSMWZB) | N32_BIT (5), 4, ATTR (STR_EXT), 0, NULL, 0, NULL},
278 {"lhi.gp", "=rt,[+%i18s1]", OP6 (HWGP), 4, ATTR (GPREL) | ATTR_V2UP, USE_REG (29), NULL, 0, NULL},
279 {"lhsi.gp", "=rt,[+%i18s1]", OP6 (HWGP) | (2 << 17), 4, ATTR (GPREL) | ATTR_V2UP, USE_REG (29), NULL, 0, NULL},
280 {"shi.gp", "%rt,[+%i18s1]", OP6 (HWGP) | (4 << 17), 4, ATTR (GPREL) | ATTR_V2UP, USE_REG (29), NULL, 0, NULL},
281 {"lwi.gp", "=rt,[+%i17s2]", OP6 (HWGP) | (6 << 17), 4, ATTR (GPREL) | ATTR_V2UP, USE_REG (29), NULL, 0, NULL},
282 {"swi.gp", "%rt,[+%i17s2]", OP6 (HWGP) | (7 << 17), 4, ATTR (GPREL) | ATTR_V2UP, USE_REG (29), NULL, 0, NULL},
285 {"sbi.gp", "%rt,[+%i19s]", OP6 (SBGP), 4, ATTR (GPREL) | ATTR_V2UP, USE_REG (29), NULL, 0, NULL},
286 {"addi.gp", "=rt,%i19s", OP6 (SBGP) | N32_BIT (19), 4, ATTR (GPREL) | ATTR_V2UP, USE_REG (29), NULL, 0, NULL},
288 {"j", "%i24s1", OP6 (JI), 4, ATTR_PCREL | ATTR_ALL, 0, NULL, 0, NULL},
289 {"jal", "%i24s1", OP6 (JI) | N32_BIT (24), 4, ATTR_PCREL | ATTR_ALL, 0, NULL, 0, NULL},
291 {"jr", "%rb", JREG (JR), 4, ATTR (BRANCH) | ATTR_ALL, 0, NULL, 0, NULL},
292 {"jral", "%rt,%rb", JREG (JRAL), 4, ATTR (BRANCH) | ATTR_ALL, 0, NULL, 0, NULL},
293 {"jrnez", "%rb", JREG (JRNEZ), 4, ATTR (BRANCH) | ATTR_V3, 0, NULL, 0, NULL},
294 {"jralnez", "%rt,%rb", JREG (JRALNEZ), 4, ATTR (BRANCH) | ATTR_V3, 0, NULL, 0, NULL},
295 {"ret", "%rb", JREG (JR) | JREG_RET, 4, ATTR (BRANCH) | ATTR_ALL, 0, NULL, 0, NULL},
296 {"ifret", "", JREG (JR) | JREG_IFC | JREG_RET, 4, ATTR (BRANCH) | ATTR (IFC_EXT), 0, NULL, 0, NULL},
297 {"jral", "%rb", JREG (JRAL) | RT (30), 4, ATTR (BRANCH) | ATTR_ALL, 0, NULL, 0, NULL},
298 {"jralnez", "%rb", JREG (JRALNEZ) | RT (30), 4, ATTR (BRANCH) | ATTR_V3, 0, NULL, 0, NULL},
299 {"ret", "", JREG (JR) | JREG_RET | RB (30), 4, ATTR (BRANCH) | ATTR_ALL, 0, NULL, 0, NULL},
300 {"jr", "%dtitoff %rb", JREG (JR), 4, ATTR (BRANCH) | ATTR_V3MEX_V1, 0, NULL, 0, NULL},
301 {"ret", "%dtitoff %rb", JREG (JR) | JREG_RET, 4, ATTR (BRANCH) | ATTR_V3MEX_V1, 0, NULL, 0, NULL},
302 {"jral", "%dtiton %rt,%rb", JREG (JRAL), 4, ATTR (BRANCH) | ATTR_ALL, 0, NULL, 0, NULL},
303 {"jral", "%dtiton %rb", JREG (JRAL) | RT (30), 4, ATTR (BRANCH) | ATTR_ALL, 0, NULL, 0, NULL},
305 {"beq", "%rt,%ra,%i14s1", OP6 (BR1), 4, ATTR_PCREL | ATTR_ALL, 0, NULL, 0, NULL},
306 {"bne", "%rt,%ra,%i14s1", OP6 (BR1) | N32_BIT (14), 4, ATTR_PCREL | ATTR_ALL, 0, NULL, 0, NULL},
308 #define BR2(sub) (OP6 (BR2) | (N32_BR2_ ## sub << 16))
309 {"ifcall", "%i16s1", BR2 (IFCALL), 4, ATTR (IFC_EXT), 0, NULL, 0, NULL},
310 {"beqz", "%rt,%i16s1", BR2 (BEQZ), 4, ATTR_PCREL | ATTR_ALL, 0, NULL, 0, NULL},
311 {"bnez", "%rt,%i16s1", BR2 (BNEZ), 4, ATTR_PCREL | ATTR_ALL, 0, NULL, 0, NULL},
312 {"bgez", "%rt,%i16s1", BR2 (BGEZ), 4, ATTR_PCREL | ATTR_ALL, 0, NULL, 0, NULL},
313 {"bltz", "%rt,%i16s1", BR2 (BLTZ), 4, ATTR_PCREL | ATTR_ALL, 0, NULL, 0, NULL},
314 {"bgtz", "%rt,%i16s1", BR2 (BGTZ), 4, ATTR_PCREL | ATTR_ALL, 0, NULL, 0, NULL},
315 {"blez", "%rt,%i16s1", BR2 (BLEZ), 4, ATTR_PCREL | ATTR_ALL, 0, NULL, 0, NULL},
316 {"bgezal", "%rt,%i16s1", BR2 (BGEZAL), 4, ATTR_PCREL | ATTR_ALL, 0, NULL, 0, NULL},
317 {"bltzal", "%rt,%i16s1", BR2 (BLTZAL), 4, ATTR_PCREL | ATTR_ALL, 0, NULL, 0, NULL},
319 {"beqc", "%rt,%i11br3,%i8s1", OP6 (BR3), 4, ATTR_PCREL | ATTR_V3MUP, 0, NULL, 0, NULL},
320 {"bnec", "%rt,%i11br3,%i8s1", OP6 (BR3) | N32_BIT (19), 4, ATTR_PCREL | ATTR_V3MUP, 0, NULL, 0, NULL},
322 {"pbsad", "%rt,%ra,%rb", SIMD (PBSAD), 4, ATTR (PERF2_EXT), 0, NULL, 0, NULL},
323 {"pbsada", "%rt,%ra,%rb", SIMD (PBSADA), 4, ATTR (PERF2_EXT), 0, NULL, 0, NULL},
325 {"add", "=rt,%ra,%rb", ALU1 (ADD), 4, ATTR_ALL, 0, NULL, 0, NULL},
326 {"sub", "=rt,%ra,%rb", ALU1 (SUB), 4, ATTR_ALL, 0, NULL, 0, NULL},
327 {"and", "=rt,%ra,%rb", ALU1 (AND), 4, ATTR_ALL, 0, NULL, 0, NULL},
328 {"xor", "=rt,%ra,%rb", ALU1 (XOR), 4, ATTR_ALL, 0, NULL, 0, NULL},
329 {"or", "=rt,%ra,%rb", ALU1 (OR), 4, ATTR_ALL, 0, NULL, 0, NULL},
330 {"nor", "=rt,%ra,%rb", ALU1 (NOR), 4, ATTR_ALL, 0, NULL, 0, NULL},
331 {"slt", "=rt,%ra,%rb", ALU1 (SLT), 4, ATTR_ALL, 0, NULL, 0, NULL},
332 {"slts", "=rt,%ra,%rb", ALU1 (SLTS), 4, ATTR_ALL, 0, NULL, 0, NULL},
333 {"slli", "=rt,%ra,%ib5u", ALU1 (SLLI), 4, ATTR_ALL, 0, NULL, 0, NULL},
334 {"srli", "=rt,%ra,%ib5u", ALU1 (SRLI), 4, ATTR_ALL, 0, NULL, 0, NULL},
335 {"srai", "=rt,%ra,%ib5u", ALU1 (SRAI), 4, ATTR_ALL, 0, NULL, 0, NULL},
336 {"rotri", "=rt,%ra,%ib5u", ALU1 (ROTRI), 4, ATTR_ALL, 0, NULL, 0, NULL},
337 {"sll", "=rt,%ra,%rb", ALU1 (SLL), 4, ATTR_ALL, 0, NULL, 0, NULL},
338 {"srl", "=rt,%ra,%rb", ALU1 (SRL), 4, ATTR_ALL, 0, NULL, 0, NULL},
339 {"sra", "=rt,%ra,%rb", ALU1 (SRA), 4, ATTR_ALL, 0, NULL, 0, NULL},
340 {"rotr", "=rt,%ra,%rb", ALU1 (ROTR), 4, ATTR_ALL, 0, NULL, 0, NULL},
341 {"seb", "=rt,%ra", ALU1 (SEB), 4, ATTR_ALL, 0, NULL, 0, NULL},
342 {"seh", "=rt,%ra", ALU1 (SEH), 4, ATTR_ALL, 0, NULL, 0, NULL},
343 {"bitc", "=rt,%ra,%rb", ALU1 (BITC), 4, ATTR_V3, 0, NULL, 0, NULL},
344 {"zeh", "=rt,%ra", ALU1 (ZEH), 4, ATTR_ALL, 0, NULL, 0, NULL},
345 {"wsbh", "=rt,%ra", ALU1 (WSBH), 4, ATTR_ALL, 0, NULL, 0, NULL},
346 {"divsr", "=rt,=rd,%ra,%rb", ALU1 (DIVSR), 4, ATTR (DIV) | ATTR_V2UP, 0, NULL, 0, NULL},
347 {"divr", "=rt,=rd,%ra,%rb", ALU1 (DIVR), 4, ATTR (DIV) | ATTR_V2UP, 0, NULL, 0, NULL},
348 {"sva", "=rt,%ra,%rb", ALU1 (SVA), 4, ATTR_ALL, 0, NULL, 0, NULL},
349 {"svs", "=rt,%ra,%rb", ALU1 (SVS), 4, ATTR_ALL, 0, NULL, 0, NULL},
350 {"cmovz", "=rt,%ra,%rb", ALU1 (CMOVZ), 4, ATTR_ALL, 0, NULL, 0, NULL},
351 {"cmovn", "=rt,%ra,%rb", ALU1 (CMOVN), 4, ATTR_ALL, 0, NULL, 0, NULL},
352 {"or_srli", "=rt,%ra,%rb,%sh", ALU1 (OR_SRLI), 4, ATTR_V3, 0, NULL, 0, NULL},
353 {"add_srli", "=rt,%ra,%rb,%sh", ALU1 (ADD_SRLI), 4, ATTR_V3, 0, NULL, 0, NULL},
354 {"sub_srli", "=rt,%ra,%rb,%sh", ALU1 (SUB_SRLI), 4, ATTR_V3, 0, NULL, 0, NULL},
355 {"and_srli", "=rt,%ra,%rb,%sh", ALU1 (AND_SRLI), 4, ATTR_V3, 0, NULL, 0, NULL},
356 {"xor_srli", "=rt,%ra,%rb,%sh", ALU1 (XOR_SRLI), 4, ATTR_V3, 0, NULL, 0, NULL},
357 {"add_slli", "=rt,%ra,%rb,%sh", ALU1 (ADD), 4, ATTR_V3, 0, NULL, 0, NULL},
358 {"sub_slli", "=rt,%ra,%rb,%sh", ALU1 (SUB), 4, ATTR_V3, 0, NULL, 0, NULL},
359 {"and_slli", "=rt,%ra,%rb,%sh", ALU1 (AND), 4, ATTR_V3, 0, NULL, 0, NULL},
360 {"xor_slli", "=rt,%ra,%rb,%sh", ALU1 (XOR), 4, ATTR_V3, 0, NULL, 0, NULL},
361 {"or_slli", "=rt,%ra,%rb,%sh", ALU1 (OR), 4, ATTR_V3, 0, NULL, 0, NULL},
362 {"nop", "", ALU1 (SRLI), 4, ATTR_ALL, 0, NULL, 0, NULL},
364 {"max", "=rt,%ra,%rb", ALU2 (MAX), 4, ATTR (PERF_EXT), 0, NULL, 0, NULL},
365 {"min", "=rt,%ra,%rb", ALU2 (MIN), 4, ATTR (PERF_EXT), 0, NULL, 0, NULL},
366 {"ave", "=rt,%ra,%rb", ALU2 (AVE), 4, ATTR (PERF_EXT), 0, NULL, 0, NULL},
367 {"abs", "=rt,%ra", ALU2 (ABS), 4, ATTR (PERF_EXT), 0, NULL, 0, NULL},
368 {"clips", "=rt,%ra,%ib5u", ALU2 (CLIPS), 4, ATTR (PERF_EXT), 0, NULL, 0, NULL},
369 {"clip", "=rt,%ra,%ib5u", ALU2 (CLIP), 4, ATTR (PERF_EXT), 0, NULL, 0, NULL},
370 {"clo", "=rt,%ra", ALU2 (CLO), 4, ATTR (PERF_EXT), 0, NULL, 0, NULL},
371 {"clz", "=rt,%ra", ALU2 (CLZ), 4, ATTR (PERF_EXT), 0, NULL, 0, NULL},
372 {"bset", "=rt,%ra,%ib5u", ALU2 (BSET), 4, ATTR (PERF_EXT), 0, NULL, 0, NULL},
373 {"bclr", "=rt,%ra,%ib5u", ALU2 (BCLR), 4, ATTR (PERF_EXT), 0, NULL, 0, NULL},
374 {"btgl", "=rt,%ra,%ib5u", ALU2 (BTGL), 4, ATTR (PERF_EXT), 0, NULL, 0, NULL},
375 {"btst", "=rt,%ra,%ib5u", ALU2 (BTST), 4, ATTR (PERF_EXT), 0, NULL, 0, NULL},
376 {"bse", "=rt,%ra,=rb", ALU2 (BSE), 4, ATTR (PERF2_EXT), 0, NULL, 0, NULL},
377 {"bsp", "=rt,%ra,=rb", ALU2 (BSP), 4, ATTR (PERF2_EXT), 0, NULL, 0, NULL},
378 {"ffzmism", "=rt,%ra,%rb", ALU2 (FFZMISM), 4, ATTR (STR_EXT), 0, NULL, 0, NULL},
379 {"mfusr", "=rt,%usr", ALU2 (MFUSR), 4, ATTR_V3MEX_V1, 0, NULL, 0, NULL},
380 {"mtusr", "%rt,%usr", ALU2 (MTUSR), 4, ATTR_V3MEX_V1, 0, NULL, 0, NULL},
381 {"mfusr", "=rt,%ridx", ALU2 (MFUSR), 4, ATTR_V3MEX_V1, 0, NULL, 0, NULL},
382 {"mtusr", "%rt,%ridx", ALU2 (MTUSR), 4, ATTR_V3MEX_V1, 0, NULL, 0, NULL},
383 {"mul", "=rt,%ra,%rb", ALU2 (MUL), 4, ATTR_ALL, 0, NULL, 0, NULL},
384 {"madds64", "=dt,%ra,%rb", ALU2 (MADDS64), 4, ATTR (MAC) | ATTR_ALL, 0, NULL, 0, NULL},
385 {"madd64", "=dt,%ra,%rb", ALU2 (MADD64), 4, ATTR (MAC) | ATTR_ALL, 0, NULL, 0, NULL},
386 {"msubs64", "=dt,%ra,%rb", ALU2 (MSUBS64), 4, ATTR (MAC) | ATTR_ALL, 0, NULL, 0, NULL},
387 {"msub64", "=dt,%ra,%rb", ALU2 (MSUB64), 4, ATTR (MAC) | ATTR_ALL, 0, NULL, 0, NULL},
388 {"divs", "=dt,%ra,%rb", ALU2 (DIVS), 4, ATTR (DIV) | ATTR (DXREG), 0, NULL, 0, NULL},
389 {"div", "=dt,%ra,%rb", ALU2 (DIV), 4, ATTR (DIV) | ATTR (DXREG), 0, NULL, 0, NULL},
390 {"mult32", "=dt,%ra,%rb", ALU2 (MULT32), 4, ATTR (DXREG) | ATTR_ALL, 0, NULL, 0, NULL},
393 {"ffb", "=rt,%ra,%rb", ALU2 (FFB), 4, ATTR (STR_EXT), 0, NULL, 0, NULL},
394 {"ffbi", "=rt,%ra,%ib8u", ALU2 (FFBI) | N32_BIT (6), 4, ATTR (STR_EXT), 0, NULL, 0, NULL},
395 /* seg-ALU2_FLMISM. */
396 {"ffmism", "=rt,%ra,%rb", ALU2 (FFMISM), 4, ATTR (STR_EXT), 0, NULL, 0, NULL},
397 {"flmism", "=rt,%ra,%rb", ALU2 (FLMISM) | N32_BIT (6), 4, ATTR (STR_EXT), 0, NULL, 0, NULL},
398 /* seg-ALU2_MULSR64. */
399 {"mults64", "=dt,%ra,%rb", ALU2 (MULTS64), 4, ATTR_ALL, 0, NULL, 0, NULL},
400 {"mulsr64", "=rt,%ra,%rb", ALU2 (MULSR64)| N32_BIT (6), 4, ATTR_V3MEX_V2, 0, NULL, 0, NULL},
401 /* seg-ALU2_MULR64. */
402 {"mult64", "=dt,%ra,%rb", ALU2 (MULT64), 4, ATTR_ALL, 0, NULL, 0, NULL},
403 {"mulr64", "=rt,%ra,%rb", ALU2 (MULR64) | N32_BIT (6), 4, ATTR_V3MEX_V2, 0, NULL, 0, NULL},
404 /* seg-ALU2_MADDR32. */
405 {"madd32", "=dt,%ra,%rb", ALU2 (MADD32), 4, ATTR (MAC) | ATTR (DXREG) | ATTR_ALL, 0, NULL, 0, NULL},
406 {"maddr32", "=rt,%ra,%rb", ALU2 (MADDR32) | N32_BIT (6), 4, ATTR (MAC) | ATTR_V2UP, 0, NULL, 0, NULL},
407 /* seg-ALU2_MSUBR32. */
408 {"msub32", "=dt,%ra,%rb", ALU2 (MSUB32), 4, ATTR (MAC) | ATTR (DXREG) | ATTR_ALL, 0, NULL, 0, NULL},
409 {"msubr32", "=rt,%ra,%rb", ALU2 (MSUBR32) | N32_BIT (6), 4, ATTR (MAC) | ATTR_V2UP, 0, NULL, 0, NULL},
412 {"standby", "%stdby_st", MISC (STANDBY), 4, ATTR_ALL, 0, NULL, 0, NULL},
413 {"mfsr", "=rt,%sr", MISC (MFSR), 4, ATTR_ALL, 0, NULL, 0, NULL},
414 {"iret", "", MISC (IRET), 4, ATTR_ALL, 0, NULL, 0, NULL},
415 {"trap", "%swid", MISC (TRAP), 4, ATTR_V3MEX_V1, 0, NULL, 0, NULL},
416 {"teqz", "%rt{,%swid}", MISC (TEQZ), 4, ATTR_V3MEX_V1, 0, NULL, 0, NULL},
417 {"tnez", "%rt{,%swid}", MISC (TNEZ), 4, ATTR_V3MEX_V1, 0, NULL, 0, NULL},
418 {"dsb", "", MISC (DSB), 4, ATTR_ALL, 0, NULL, 0, NULL},
419 {"isb", "", MISC (ISB), 4, ATTR_ALL, 0, NULL, 0, NULL},
420 {"break", "%swid", MISC (BREAK), 4, ATTR_ALL, 0, NULL, 0, NULL},
421 {"syscall", "%swid", MISC (SYSCALL), 4, ATTR_ALL, 0, NULL, 0, NULL},
422 {"msync", "%msync_st", MISC (MSYNC), 4, ATTR_ALL, 0, NULL, 0, NULL},
423 {"isync", "%rt", MISC (ISYNC), 4, ATTR_ALL, 0, NULL, 0, NULL},
425 {"mtsr", "%rt,%sr", MISC (MTSR), 4, ATTR_ALL, 0, NULL, 0, NULL},
426 /* seg-MISC_SETEND. */
427 {"setend.l", "", MISC (MTSR) | (SRIDX (1, 0, 0) << 10) | N32_BIT (5), 4, ATTR_ALL, 0, NULL, 0, NULL},
428 {"setend.b", "", MISC (MTSR) | (SRIDX (1, 0, 0) << 10) | N32_BIT (5) | N32_BIT (20), 4, ATTR_ALL, 0, NULL, 0, NULL},
429 /* seg-MISC_SETGIE. */
430 {"setgie.d", "", MISC (MTSR) | (SRIDX (1, 0, 0) << 10) | N32_BIT (6), 4, ATTR_ALL, 0, NULL, 0, NULL},
431 {"setgie.e", "", MISC (MTSR) | (SRIDX (1, 0, 0) << 10) | N32_BIT (6) | N32_BIT (20), 4, ATTR_ALL, 0, NULL, 0, NULL},
432 {"mfsr", "=rt,%ridx", MISC (MFSR), 4, ATTR_ALL, 0, NULL, 0, NULL},
433 {"mtsr", "%rt,%ridx", MISC (MTSR), 4, ATTR_ALL, 0, NULL, 0, NULL},
434 {"trap", "", MISC (TRAP), 4, ATTR_V3MEX_V1, 0, NULL, 0, NULL},
435 {"break", "", MISC (BREAK), 4, ATTR_ALL, 0, NULL, 0, NULL},
436 {"msync", "", MISC (MSYNC), 4, ATTR_ALL, 0, NULL, 0, NULL},
437 /* seg-MISC_TLBOP. */
438 {"tlbop", "%ra,%tlbop_st", MISC (TLBOP), 4, ATTR_ALL, 0, NULL, 0, NULL},
439 {"tlbop", "%ra,%tlbop_stx", MISC (TLBOP), 4, ATTR_ALL, 0, NULL, 0, NULL},
440 {"tlbop", "%rt,%ra,pb", MISC (TLBOP) | (5 << 5), 4, ATTR_ALL, 0, NULL, 0, NULL},
441 {"tlbop", "flua", MISC (TLBOP) | (7 << 5), 4, ATTR_ALL, 0, NULL, 0, NULL},
442 {"tlbop", "flushall", MISC (TLBOP) | (7 << 5), 4, ATTR_ALL, 0, NULL, 0, NULL},
445 {"lb", "=rt,[%ra+(%rb<<%sv)]", MEM (LB), 4, ATTR_ALL, 0, NULL, 0, NULL},
446 {"lb", "=rt,[%ra+%rb{<<%sv}]", MEM (LB), 4, ATTR_ALL, 0, NULL, 0, NULL},
447 {"lh", "=rt,[%ra+(%rb<<%sv)]", MEM (LH), 4, ATTR_ALL, 0, NULL, 0, NULL},
448 {"lh", "=rt,[%ra+%rb{<<%sv}]", MEM (LH), 4, ATTR_ALL, 0, NULL, 0, NULL},
449 {"lw", "=rt,[%ra+(%rb<<%sv)]", MEM (LW), 4, ATTR_ALL, 0, NULL, 0, NULL},
450 {"lw", "=rt,[%ra+%rb{<<%sv}]", MEM (LW), 4, ATTR_ALL, 0, NULL, 0, NULL},
451 {"ld", "=rt,[%ra+(%rb<<%sv)]", MEM (LD), 4, ATTR_ALL, 0, NULL, 0, NULL},
452 {"lb.bi", "=rt,[%ra],%rb{<<%sv}", MEM (LB_BI), 4, ATTR_ALL, 0, NULL, 0, NULL},
453 {"lb.bi", "=rt,[%ra],(%rb<<%sv)", MEM (LB_BI), 4, ATTR_ALL, 0, NULL, 0, NULL},
454 {"lb.p", "=rt,[%ra],%rb{<<%sv}", MEM (LB_BI), 4, ATTR_ALL, 0, NULL, 0, NULL},
455 {"lh.bi", "=rt,[%ra],%rb{<<%sv}", MEM (LH_BI), 4, ATTR_ALL, 0, NULL, 0, NULL},
456 {"lh.bi", "=rt,[%ra],(%rb<<%sv)", MEM (LH_BI), 4, ATTR_ALL, 0, NULL, 0, NULL},
457 {"lh.p", "=rt,[%ra],%rb{<<%sv}", MEM (LH_BI), 4, ATTR_ALL, 0, NULL, 0, NULL},
458 {"lw.bi", "=rt,[%ra],%rb{<<%sv}", MEM (LW_BI), 4, ATTR_ALL, 0, NULL, 0, NULL},
459 {"lw.bi", "=rt,[%ra],(%rb<<%sv)", MEM (LW_BI), 4, ATTR_ALL, 0, NULL, 0, NULL},
460 {"lw.p", "=rt,[%ra],%rb{<<%sv}", MEM (LW_BI), 4, ATTR_ALL, 0, NULL, 0, NULL},
461 {"ld.bi", "=rt,[%ra],(%rb<<%sv)", MEM (LD_BI), 4, ATTR_ALL, 0, NULL, 0, NULL},
462 {"sb", "=rt,[%ra+(%rb<<%sv)]", MEM (SB), 4, ATTR_ALL, 0, NULL, 0, NULL},
463 {"sb", "%rt,[%ra+%rb{<<%sv}]", MEM (SB), 4, ATTR_ALL, 0, NULL, 0, NULL},
464 {"sh", "=rt,[%ra+(%rb<<%sv)]", MEM (SH), 4, ATTR_ALL, 0, NULL, 0, NULL},
465 {"sh", "%rt,[%ra+%rb{<<%sv}]", MEM (SH), 4, ATTR_ALL, 0, NULL, 0, NULL},
466 {"sw", "=rt,[%ra+(%rb<<%sv)]", MEM (SW), 4, ATTR_ALL, 0, NULL, 0, NULL},
467 {"sw", "%rt,[%ra+%rb{<<%sv}]", MEM (SW), 4, ATTR_ALL, 0, NULL, 0, NULL},
468 {"sd", "=rt,[%ra+(%rb<<%sv)]", MEM (SD), 4, ATTR_ALL, 0, NULL, 0, NULL},
469 {"sb.bi", "%rt,[%ra],%rb{<<%sv}", MEM (SB_BI), 4, ATTR_ALL, 0, NULL, 0, NULL},
470 {"sb.bi", "=rt,[%ra],(%rb<<%sv)", MEM (SB_BI), 4, ATTR_ALL, 0, NULL, 0, NULL},
471 {"sb.p", "%rt,[%ra],%rb{<<%sv}", MEM (SB_BI), 4, ATTR_ALL, 0, NULL, 0, NULL},
472 {"sh.bi", "%rt,[%ra],%rb{<<%sv}", MEM (SH_BI), 4, ATTR_ALL, 0, NULL, 0, NULL},
473 {"sh.bi", "=rt,[%ra],(%rb<<%sv)", MEM (SH_BI), 4, ATTR_ALL, 0, NULL, 0, NULL},
474 {"sh.p", "%rt,[%ra],%rb{<<%sv}", MEM (SH_BI), 4, ATTR_ALL, 0, NULL, 0, NULL},
475 {"sw.bi", "%rt,[%ra],%rb{<<%sv}", MEM (SW_BI), 4, ATTR_ALL, 0, NULL, 0, NULL},
476 {"sw.bi", "=rt,[%ra],(%rb<<%sv)", MEM (SW_BI), 4, ATTR_ALL, 0, NULL, 0, NULL},
477 {"sw.p", "%rt,[%ra],%rb{<<%sv}", MEM (SW_BI), 4, ATTR_ALL, 0, NULL, 0, NULL},
478 {"sd.bi", "=rt,[%ra],(%rb<<%sv)", MEM (SD_BI), 4, ATTR_ALL, 0, NULL, 0, NULL},
480 {"lbs", "=rt,[%ra+(%rb<<%sv)]", MEM (LBS), 4, ATTR_ALL, 0, NULL, 0, NULL},
481 {"lbs", "=rt,[%ra+%rb{<<%sv}]", MEM (LBS), 4, ATTR_ALL, 0, NULL, 0, NULL},
482 {"lhs", "=rt,[%ra+(%rb<<%sv)]", MEM (LHS), 4, ATTR_ALL, 0, NULL, 0, NULL},
483 {"lhs", "=rt,[%ra+%rb{<<%sv}]", MEM (LHS), 4, ATTR_ALL, 0, NULL, 0, NULL},
484 {"lbs.bi", "=rt,[%ra],%rb{<<%sv}", MEM (LBS_BI),4, ATTR_ALL, 0, NULL, 0, NULL},
485 {"lbs.bi", "=rt,[%ra],(%rb<<%sv)", MEM (LBS_BI), 4, ATTR_ALL, 0, NULL, 0, NULL},
486 {"lbs.p", "=rt,[%ra],%rb{<<%sv}", MEM (LBS_BI),4, ATTR_ALL, 0, NULL, 0, NULL},
487 {"lhs.bi", "=rt,[%ra],%rb{<<%sv}", MEM (LHS_BI),4, ATTR_ALL, 0, NULL, 0, NULL},
488 {"lhs.bi", "=rt,[%ra],(%rb<<%sv)", MEM (LHS_BI), 4, ATTR_ALL, 0, NULL, 0, NULL},
489 {"lhs.p", "=rt,[%ra],%rb{<<%sv}", MEM (LHS_BI),4, ATTR_ALL, 0, NULL, 0, NULL},
490 {"llw", "=rt,[%ra+(%rb<<%sv)]", MEM (LLW), 4, ATTR_V3MEX_V1, 0, NULL, 0, NULL},
491 {"llw", "=rt,[%ra+%rb{<<%sv}]", MEM (LLW), 4, ATTR_V3MEX_V1, 0, NULL, 0, NULL},
492 {"scw", "%rt,[%ra+(%rb<<%sv)]", MEM (SCW), 4, ATTR_V3MEX_V1, 0, NULL, 0, NULL},
493 {"scw", "%rt,[%ra+%rb{<<%sv}]", MEM (SCW), 4, ATTR_V3MEX_V1, 0, NULL, 0, NULL},
495 {"lbup", "=rt,[%ra+(%rb<<%sv)]", MEM (LBUP), 4, ATTR_V3MEX_V2, 0, NULL, 0, NULL},
496 {"lbup", "=rt,[%ra+%rb{<<%sv}]", MEM (LBUP), 4, ATTR_V3MEX_V2, 0, NULL, 0, NULL},
497 {"lwup", "=rt,[%ra+(%rb<<%sv)]", MEM (LWUP), 4, ATTR_V3MEX_V1, 0, NULL, 0, NULL},
498 {"lwup", "=rt,[%ra+%rb{<<%sv}]", MEM (LWUP), 4, ATTR_V3MEX_V1, 0, NULL, 0, NULL},
499 {"sbup", "%rt,[%ra+(%rb<<%sv)]", MEM (SBUP), 4, ATTR_V3MEX_V2, 0, NULL, 0, NULL},
500 {"sbup", "%rt,[%ra+%rb{<<%sv}]", MEM (SBUP), 4, ATTR_V3MEX_V2, 0, NULL, 0, NULL},
501 {"swup", "%rt,[%ra+(%rb<<%sv)]", MEM (SWUP), 4, ATTR_V3MEX_V1, 0, NULL, 0, NULL},
502 {"swup", "%rt,[%ra+%rb{<<%sv}]", MEM (SWUP), 4, ATTR_V3MEX_V1, 0, NULL, 0, NULL},
504 {"dpref", "%dpref_st,[%ra]", OP6 (DPREFI), 4, ATTR_V3MEX_V1, 0, NULL, 0, NULL},
505 {"dpref", "%dpref_st,[%ra+(%rb<<%sv)]", MEM (DPREF), 4, ATTR_V3MEX_V1, 0, NULL, 0, NULL},
506 {"dpref", "%dpref_st,[%ra+%rb{<<%sv}]", MEM (DPREF), 4, ATTR_V3MEX_V1, 0, NULL, 0, NULL},
508 /* For missing-operand-load/store instructions. */
509 {"lb", "=rt,[%ra]", OP6 (LBI), 4, ATTR_ALL, 0, NULL, 0, NULL},
510 {"lh", "=rt,[%ra]", OP6 (LHI), 4, ATTR_ALL, 0, NULL, 0, NULL},
511 {"lw", "=rt,[%ra]", OP6 (LWI), 4, ATTR_ALL, 0, NULL, 0, NULL},
512 {"lbs", "=rt,[%ra]", OP6 (LBSI), 4, ATTR_ALL, 0, NULL, 0, NULL},
513 {"lhs", "=rt,[%ra]", OP6 (LHSI), 4, ATTR_ALL, 0, NULL, 0, NULL},
514 {"sb", "%rt,[%ra]", OP6 (SBI), 4, ATTR_ALL, 0, NULL, 0, NULL},
515 {"sh", "%rt,[%ra]", OP6 (SHI), 4, ATTR_ALL, 0, NULL, 0, NULL},
516 {"sw", "%rt,[%ra]", OP6 (SWI), 4, ATTR_ALL, 0, NULL, 0, NULL},
519 {"flsi", "=fst,[%ra{+%i12s2}]", OP6 (LWC), 4, ATTR (FPU), 0, NULL, 0, NULL},
520 {"flsi.bi", "=fst,[%ra],%i12s2", FPU_RA_IMMBI (LWC), 4, ATTR (FPU), 0, NULL, 0, NULL},
522 {"fssi", "=fst,[%ra{+%i12s2}]", OP6 (SWC), 4, ATTR (FPU), 0, NULL, 0, NULL},
523 {"fssi.bi", "=fst,[%ra],%i12s2", FPU_RA_IMMBI (SWC), 4, ATTR (FPU), 0, NULL, 0, NULL},
525 {"fldi", "=fdt,[%ra{+%i12s2}]", OP6 (LDC), 4, ATTR (FPU), 0, NULL, 0, NULL},
526 {"fldi.bi", "=fdt,[%ra],%i12s2", FPU_RA_IMMBI (LDC), 4, ATTR (FPU), 0, NULL, 0, NULL},
528 {"fsdi", "=fdt,[%ra{+%i12s2}]", OP6 (SDC), 4, ATTR (FPU), 0, NULL, 0, NULL},
529 {"fsdi.bi", "=fdt,[%ra],%i12s2", FPU_RA_IMMBI (SDC), 4, ATTR (FPU), 0, NULL, 0, NULL},
532 {"fadds", "=fst,%fsa,%fsb", FS1 (FADDS), 4, ATTR (FPU) | ATTR (FPU_SP_EXT), 0, NULL, 0, NULL},
533 {"fsubs", "=fst,%fsa,%fsb", FS1 (FSUBS), 4, ATTR (FPU) | ATTR (FPU_SP_EXT), 0, NULL, 0, NULL},
534 {"fcpynss", "=fst,%fsa,%fsb", FS1 (FCPYNSS), 4, ATTR (FPU) | ATTR (FPU_SP_EXT), 0, NULL, 0, NULL},
535 {"fcpyss", "=fst,%fsa,%fsb", FS1 (FCPYSS), 4, ATTR (FPU) | ATTR (FPU_SP_EXT), 0, NULL, 0, NULL},
536 {"fmadds", "=fst,%fsa,%fsb", FS1 (FMADDS), 4, ATTR (FPU) | ATTR (FPU_SP_EXT), 0, NULL, 0, NULL},
537 {"fmsubs", "=fst,%fsa,%fsb", FS1 (FMSUBS), 4, ATTR (FPU) | ATTR (FPU_SP_EXT), 0, NULL, 0, NULL},
538 {"fcmovns", "=fst,%fsa,%fsb", FS1 (FCMOVNS), 4, ATTR (FPU) | ATTR (FPU_SP_EXT), 0, NULL, 0, NULL},
539 {"fcmovzs", "=fst,%fsa,%fsb", FS1 (FCMOVZS), 4, ATTR (FPU) | ATTR (FPU_SP_EXT), 0, NULL, 0, NULL},
540 {"fnmadds", "=fst,%fsa,%fsb", FS1 (FNMADDS), 4, ATTR (FPU) | ATTR (FPU_SP_EXT), 0, NULL, 0, NULL},
541 {"fnmsubs", "=fst,%fsa,%fsb", FS1 (FNMSUBS), 4, ATTR (FPU) | ATTR (FPU_SP_EXT), 0, NULL, 0, NULL},
542 {"fmuls", "=fst,%fsa,%fsb", FS1 (FMULS), 4, ATTR (FPU) | ATTR (FPU_SP_EXT), 0, NULL, 0, NULL},
543 {"fdivs", "=fst,%fsa,%fsb", FS1 (FDIVS), 4, ATTR (FPU) | ATTR (FPU_SP_EXT), 0, NULL, 0, NULL},
545 /* seg-FPU_FS1_F2OP. */
546 {"fs2d", "=fdt,%fsa", FS1_F2OP (FS2D), 4, ATTR (FPU) | ATTR (FPU_SP_EXT) | ATTR (FPU_DP_EXT), 0, NULL, 0, NULL},
547 {"fsqrts", "=fst,%fsa", FS1_F2OP (FSQRTS), 4, ATTR (FPU) | ATTR (FPU_SP_EXT), 0, NULL, 0, NULL},
548 {"fabss", "=fst,%fsa", FS1_F2OP (FABSS), 4, ATTR (FPU) | ATTR (FPU_SP_EXT), 0, NULL, 0, NULL},
549 {"fui2s", "=fst,%fsa", FS1_F2OP (FUI2S), 4, ATTR (FPU) | ATTR (FPU_SP_EXT), 0, NULL, 0, NULL},
550 {"fsi2s", "=fst,%fsa", FS1_F2OP (FSI2S), 4, ATTR (FPU) | ATTR (FPU_SP_EXT), 0, NULL, 0, NULL},
551 {"fs2ui", "=fst,%fsa", FS1_F2OP (FS2UI), 4, ATTR (FPU) | ATTR (FPU_SP_EXT), 0, NULL, 0, NULL},
552 {"fs2ui.z", "=fst,%fsa", FS1_F2OP (FS2UI_Z), 4, ATTR (FPU) | ATTR (FPU_SP_EXT), 0, NULL, 0, NULL},
553 {"fs2si", "=fst,%fsa", FS1_F2OP (FS2SI), 4, ATTR (FPU) | ATTR (FPU_SP_EXT), 0, NULL, 0, NULL},
554 {"fs2si.z", "=fst,%fsa", FS1_F2OP (FS2SI_Z), 4, ATTR (FPU) | ATTR (FPU_SP_EXT), 0, NULL, 0, NULL},
556 {"fcmpeqs", "=fst,%fsa,%fsb", FS2 (FCMPEQS), 4, ATTR (FPU) | ATTR (FPU_SP_EXT), 0, NULL, 0, NULL},
557 {"fcmpeqs.e", "=fst,%fsa,%fsb", FS2 (FCMPEQS_E), 4, ATTR (FPU) | ATTR (FPU_SP_EXT), 0, NULL, 0, NULL},
558 {"fcmplts", "=fst,%fsa,%fsb", FS2 (FCMPLTS), 4, ATTR (FPU) | ATTR (FPU_SP_EXT), 0, NULL, 0, NULL},
559 {"fcmplts.e", "=fst,%fsa,%fsb", FS2 (FCMPLTS_E), 4, ATTR (FPU) | ATTR (FPU_SP_EXT), 0, NULL, 0, NULL},
560 {"fcmples", "=fst,%fsa,%fsb", FS2 (FCMPLES), 4, ATTR (FPU) | ATTR (FPU_SP_EXT), 0, NULL, 0, NULL},
561 {"fcmples.e", "=fst,%fsa,%fsb", FS2 (FCMPLES_E), 4, ATTR (FPU) | ATTR (FPU_SP_EXT), 0, NULL, 0, NULL},
562 {"fcmpuns", "=fst,%fsa,%fsb", FS2 (FCMPUNS), 4, ATTR (FPU) | ATTR (FPU_SP_EXT), 0, NULL, 0, NULL},
563 {"fcmpuns.e", "=fst,%fsa,%fsb", FS2 (FCMPUNS_E), 4, ATTR (FPU) | ATTR (FPU_SP_EXT), 0, NULL, 0, NULL},
565 {"faddd", "=fdt,%fda,%fdb", FD1 (FADDD), 4, ATTR (FPU) | ATTR (FPU_DP_EXT), 0, NULL, 0, NULL},
566 {"fsubd", "=fdt,%fda,%fdb", FD1 (FSUBD), 4, ATTR (FPU) | ATTR (FPU_DP_EXT), 0, NULL, 0, NULL},
567 {"fcpynsd", "=fdt,%fda,%fdb", FD1 (FCPYNSD), 4, ATTR (FPU) | ATTR (FPU_DP_EXT), 0, NULL, 0, NULL},
568 {"fcpysd", "=fdt,%fda,%fdb", FD1 (FCPYSD), 4, ATTR (FPU), 0, NULL, 0, NULL},
569 {"fmaddd", "=fdt,%fda,%fdb", FD1 (FMADDD), 4, ATTR (FPU) | ATTR (FPU_DP_EXT), 0, NULL, 0, NULL},
570 {"fmsubd", "=fdt,%fda,%fdb", FD1 (FMSUBD), 4, ATTR (FPU) | ATTR (FPU_DP_EXT), 0, NULL, 0, NULL},
571 {"fcmovnd", "=fdt,%fda,%fsb", FD1 (FCMOVND), 4, ATTR (FPU) | ATTR (FPU_DP_EXT), 0, NULL, 0, NULL},
572 {"fcmovzd", "=fdt,%fda,%fsb", FD1 (FCMOVZD), 4, ATTR (FPU) | ATTR (FPU_DP_EXT), 0, NULL, 0, NULL},
573 {"fnmaddd", "=fdt,%fda,%fdb", FD1 (FNMADDD), 4, ATTR (FPU) | ATTR (FPU_DP_EXT), 0, NULL, 0, NULL},
574 {"fnmsubd", "=fdt,%fda,%fdb", FD1 (FNMSUBD), 4, ATTR (FPU) | ATTR (FPU_DP_EXT), 0, NULL, 0, NULL},
575 {"fmuld", "=fdt,%fda,%fdb", FD1 (FMULD), 4, ATTR (FPU) | ATTR (FPU_DP_EXT), 0, NULL, 0, NULL},
576 {"fdivd", "=fdt,%fda,%fdb", FD1 (FDIVD), 4, ATTR (FPU) | ATTR (FPU_DP_EXT), 0, NULL, 0, NULL},
577 /* seg-FPU_FD1_F2OP. */
578 {"fd2s", "=fst,%fda", FD1_F2OP (FD2S), 4, ATTR (FPU) | ATTR (FPU_SP_EXT) | ATTR (FPU_DP_EXT), 0, NULL, 0, NULL},
579 {"fsqrtd", "=fdt,%fda", FD1_F2OP (FSQRTD), 4, ATTR (FPU) | ATTR (FPU_DP_EXT), 0, NULL, 0, NULL},
580 {"fabsd", "=fdt,%fda", FD1_F2OP (FABSD), 4, ATTR (FPU) | ATTR (FPU_DP_EXT), 0, NULL, 0, NULL},
581 {"fui2d", "=fdt,%fsa", FD1_F2OP (FUI2D), 4, ATTR (FPU) | ATTR (FPU_DP_EXT), 0, NULL, 0, NULL},
582 {"fsi2d", "=fdt,%fsa", FD1_F2OP (FSI2D), 4, ATTR (FPU) | ATTR (FPU_DP_EXT), 0, NULL, 0, NULL},
583 {"fd2ui", "=fst,%fda", FD1_F2OP (FD2UI), 4, ATTR (FPU) | ATTR (FPU_DP_EXT), 0, NULL, 0, NULL},
584 {"fd2ui.z", "=fst,%fda", FD1_F2OP (FD2UI_Z), 4, ATTR (FPU) | ATTR (FPU_DP_EXT), 0, NULL, 0, NULL},
585 {"fd2si", "=fst,%fda", FD1_F2OP (FD2SI), 4, ATTR (FPU) | ATTR (FPU_DP_EXT), 0, NULL, 0, NULL},
586 {"fd2si.z", "=fst,%fda", FD1_F2OP (FD2SI_Z), 4, ATTR (FPU) | ATTR (FPU_DP_EXT), 0, NULL, 0, NULL},
588 {"fcmpeqd", "=fst,%fda,%fdb", FD2 (FCMPEQD), 4, ATTR (FPU) | ATTR (FPU_DP_EXT), 0, NULL, 0, NULL},
589 {"fcmpeqd.e", "=fst,%fda,%fdb", FD2 (FCMPEQD_E), 4, ATTR (FPU) | ATTR (FPU_DP_EXT), 0, NULL, 0, NULL},
590 {"fcmpltd", "=fst,%fda,%fdb", FD2 (FCMPLTD), 4, ATTR (FPU) | ATTR (FPU_DP_EXT), 0, NULL, 0, NULL},
591 {"fcmpltd.e", "=fst,%fda,%fdb", FD2 (FCMPLTD_E), 4, ATTR (FPU) | ATTR (FPU_DP_EXT), 0, NULL, 0, NULL},
592 {"fcmpled", "=fst,%fda,%fdb", FD2 (FCMPLED), 4, ATTR (FPU) | ATTR (FPU_DP_EXT), 0, NULL, 0, NULL},
593 {"fcmpled.e", "=fst,%fda,%fdb", FD2 (FCMPLED_E), 4, ATTR (FPU) | ATTR (FPU_DP_EXT), 0, NULL, 0, NULL},
594 {"fcmpund", "=fst,%fda,%fdb", FD2 (FCMPUND), 4, ATTR (FPU) | ATTR (FPU_DP_EXT), 0, NULL, 0, NULL},
595 {"fcmpund.e", "=fst,%fda,%fdb", FD2 (FCMPUND_E), 4, ATTR (FPU) | ATTR (FPU_DP_EXT), 0, NULL, 0, NULL},
597 {"fmfsr", "=rt,%fsa", MFCP (FMFSR), 4, ATTR (FPU), 0, NULL, 0, NULL},
598 {"fmfdr", "=rt,%fda", MFCP (FMFDR), 4, ATTR (FPU), 0, NULL, 0, NULL},
599 /* seg-FPU_MFCP_XR. */
600 {"fmfcfg", "=rt", MFCP_XR(FMFCFG), 4, ATTR (FPU), 0, NULL, 0, NULL},
601 {"fmfcsr", "=rt", MFCP_XR(FMFCSR), 4, ATTR (FPU), 0, NULL, 0, NULL},
604 {"fmtsr", "%rt,=fsa", MTCP (FMTSR), 4, ATTR (FPU), 0, NULL, 0, NULL},
605 {"fmtdr", "%rt,=fda", MTCP (FMTDR), 4, ATTR (FPU), 0, NULL, 0, NULL},
606 /* seg-FPU_MTCP_XR. */
607 {"fmtcsr", "%rt", MTCP_XR(FMTCSR), 4, ATTR (FPU), 0, NULL, 0, NULL},
609 {"fls", "=fst,[%ra+(%rb<<%sv)]", FPU_MEM(FLS), 4, ATTR (FPU), 0, NULL, 0, NULL},
610 {"fls.bi", "=fst,[%ra],(%rb<<%sv)", FPU_MEMBI(FLS), 4, ATTR (FPU), 0, NULL, 0, NULL},
612 {"fld", "=fdt,[%ra+(%rb<<%sv)]", FPU_MEM(FLD), 4, ATTR (FPU), 0, NULL, 0, NULL},
613 {"fld.bi", "=fdt,[%ra],(%rb<<%sv)", FPU_MEMBI(FLD), 4, ATTR (FPU), 0, NULL, 0, NULL},
615 {"fss", "=fst,[%ra+(%rb<<%sv)]", FPU_MEM(FSS), 4, ATTR (FPU), 0, NULL, 0, NULL},
616 {"fss.bi", "=fst,[%ra],(%rb<<%sv)", FPU_MEMBI(FSS), 4, ATTR (FPU), 0, NULL, 0, NULL},
618 {"fsd", "=fdt,[%ra+(%rb<<%sv)]", FPU_MEM(FSD), 4, ATTR (FPU), 0, NULL, 0, NULL},
619 {"fsd.bi", "=fdt,[%ra],(%rb<<%sv)", FPU_MEMBI(FSD), 4, ATTR (FPU), 0, NULL, 0, NULL},
620 {"fls", "=fst,[%ra+%rb{<<%sv}]", FPU_MEM(FLS), 4, ATTR (FPU), 0, NULL, 0, NULL},
621 {"fls.bi", "=fst,[%ra],%rb{<<%sv}", FPU_MEMBI(FLS), 4, ATTR (FPU), 0, NULL, 0, NULL},
622 {"fld", "=fdt,[%ra+%rb{<<%sv}]", FPU_MEM(FLD), 4, ATTR (FPU), 0, NULL, 0, NULL},
623 {"fld.bi", "=fdt,[%ra],%rb{<<%sv}", FPU_MEMBI(FLD), 4, ATTR (FPU), 0, NULL, 0, NULL},
624 {"fss", "=fst,[%ra+%rb{<<%sv}]", FPU_MEM(FSS), 4, ATTR (FPU), 0, NULL, 0, NULL},
625 {"fss.bi", "=fst,[%ra],%rb{<<%sv}", FPU_MEMBI(FSS), 4, ATTR (FPU), 0, NULL, 0, NULL},
626 {"fsd", "=fdt,[%ra+%rb{<<%sv}]", FPU_MEM(FSD), 4, ATTR (FPU), 0, NULL, 0, NULL},
627 {"fsd.bi", "=fdt,[%ra],%rb{<<%sv}", FPU_MEMBI(FSD), 4, ATTR (FPU), 0, NULL, 0, NULL},
628 {"cctl", "%ra,%cctl_st0", MISC (CCTL), 4, ATTR_V3MEX_V1, 0, NULL, 0, NULL},
629 {"cctl", "%ra,%cctl_st1{,%cctl_lv}", MISC (CCTL), 4, ATTR_V3MEX_V1, 0, NULL, 0, NULL},
630 {"cctl", "=rt,%ra,%cctl_st2", MISC (CCTL), 4, ATTR_V3MEX_V1, 0, NULL, 0, NULL},
631 {"cctl", "%rt,%ra,%cctl_st3", MISC (CCTL), 4, ATTR_V3MEX_V1, 0, NULL, 0, NULL},
632 {"cctl", "%cctl_st4", MISC (CCTL), 4, ATTR_V3MEX_V1, 0, NULL, 0, NULL},
633 {"cctl", "%cctl_st5{,%cctl_lv}", MISC (CCTL), 4, ATTR_V3, 0, NULL, 0, NULL},
634 {"cctl", "=rt,%ra,%cctl_stx,%cctl_lv", MISC (CCTL), 4, ATTR_V3MEX_V1, 0, NULL, 0, NULL},
635 /* seg-Alias instructions. */
636 {"neg", "=rt,%ra", OP6 (SUBRI), 4, ATTR_ALL, 0, NULL, 0, NULL},
637 {"zeb", "=rt,%ra", OP6 (ANDI) | 0xff, 4, ATTR_ALL, 0, NULL, 0, NULL},
640 {"cpe1", "%cp45,%cpi19", OP6 (COP) | 0x00, 4, ATTR_ALL, 0, NULL, 0, NULL},
641 {"cpe2", "%cp45,%cpi19", OP6 (COP) | 0x04, 4, ATTR_ALL, 0, NULL, 0, NULL},
642 {"cpe3", "%cp45,%cpi19", OP6 (COP) | 0x08, 4, ATTR_ALL, 0, NULL, 0, NULL},
643 {"cpe4", "%cp45,%cpi19", OP6 (COP) | 0x0C, 4, ATTR_ALL, 0, NULL, 0, NULL},
645 {"mfcpw", "%cp45,=rt,%i12u", OP6 (COP) | 0x01, 4, ATTR_ALL, 0, NULL, 0, NULL},
646 {"mfcpd", "%cp45,=rt,%i12u", OP6 (COP) | 0x41, 4, ATTR_ALL, 0, NULL, 0, NULL},
647 {"mfcppw", "%cp45,=rt,%i12u", OP6 (COP) | 0xc1, 4, ATTR_ALL, 0, NULL, 0, NULL},
649 {"cplw", "%cp45,%cprt,[%ra+%rb<<%sv]", OP6 (COP) | 0x02, 4, ATTR_ALL, 0, NULL, 0, NULL},
650 {"cplw.bi", "%cp45,%cprt,[%ra],%rb<<%sv", OP6 (COP) | 0x82, 4, ATTR_ALL, 0, NULL, 0, NULL},
652 {"cpld", "%cp45,%cprt,[%ra+%rb<<%sv]", OP6 (COP) | 0x03, 4, ATTR_ALL, 0, NULL, 0, NULL},
653 {"cpld.bi", "%cp45,%cprt,[%ra],%rb<<%sv", OP6 (COP) | 0x83, 4, ATTR_ALL, 0, NULL, 0, NULL},
655 {"mtcpw", "%cp45,%rt,%i12u", OP6 (COP) | 0x09, 4, ATTR_ALL, 0, NULL, 0, NULL},
656 {"mtcpd", "%cp45,%rt,%i12u", OP6 (COP) | 0x49, 4, ATTR_ALL, 0, NULL, 0, NULL},
657 {"mtcppw", "%cp45,%rt,%i12u", OP6 (COP) | 0xc9, 4, ATTR_ALL, 0, NULL, 0, NULL},
659 {"cpsw", "%cp45,%cprt,[%ra+%rb<<%sv]", OP6 (COP) | 0x0a, 4, ATTR_ALL, 0, NULL, 0, NULL},
660 {"cpsw.bi", "%cp45,%cprt,[%ra],%rb<<%sv", OP6 (COP) | 0x8a, 4, ATTR_ALL, 0, NULL, 0, NULL},
662 {"cpsd", "%cp45,%cprt,[%ra+%rb<<%sv]", OP6 (COP) | 0x0b, 4, ATTR_ALL, 0, NULL, 0, NULL},
663 {"cpsd.bi", "%cp45,%cprt,[%ra],%rb<<%sv", OP6 (COP) | 0x8b, 4, ATTR_ALL, 0, NULL, 0, NULL},
665 /* 16-bit instructions. */
666 /* get bit14~bit11 of 16-bit instruction. */
667 {"beqz38", "%rt38,%i8s1", 0xc000, 2, ATTR_PCREL | ATTR_ALL, 0, NULL, 0, NULL},
668 {"bnez38", "%rt38,%i8s1", 0xc800, 2, ATTR_PCREL | ATTR_ALL, 0, NULL, 0, NULL},
669 {"beqs38", "%rt38,%i8s1", 0xd000, 2, ATTR_PCREL | ATTR_ALL, USE_REG (5), NULL, 0, NULL},
670 {"bnes38", "%rt38,%i8s1", 0xd800, 2, ATTR_PCREL | ATTR_ALL, USE_REG (5), NULL, 0, NULL},
672 /* SEG00, get bit10. */
673 {"mov55", "=rt5,%ra5", 0x8000, 2, ATTR_ALL, 0, NULL, 0, NULL},
674 {"movi55", "=rt5,%i5s", 0x8400, 2, ATTR_ALL, 0, NULL, 0, NULL},
675 /* SEG01 bit10~bit9. */
676 {"add45", "=rt4,%ra5", 0x8800, 2, ATTR_ALL, 0, NULL, 0, NULL},
677 {"sub45", "=rt4,%ra5", 0x8a00, 2, ATTR_ALL, 0, NULL, 0, NULL},
678 {"addi45", "=rt4,%i5u", 0x8c00, 2, ATTR_ALL, 0, NULL, 0, NULL},
679 {"subi45", "=rt4,%i5u", 0x8e00, 2, ATTR_ALL, 0, NULL, 0, NULL},
680 /* SEG02 bit10~bit9. */
681 {"srai45", "=rt4,%i5u", 0x9000, 2, ATTR_ALL, 0, NULL, 0, NULL},
682 {"srli45", "=rt4,%i5u", 0x9200, 2, ATTR_ALL, 0, NULL, 0, NULL},
683 {"slli333", "=rt3,%ra3,%i3u", 0x9400, 2, ATTR_ALL, 0, NULL, 0, NULL},
684 /* SEG03 bit10~bit9. */
685 {"add333", "=rt3,%ra3,%rb3", 0x9800, 2, ATTR_ALL, 0, NULL, 0, NULL},
686 {"sub333", "=rt3,%ra3,%rb3", 0x9a00, 2, ATTR_ALL, 0, NULL, 0, NULL},
687 {"addi333", "=rt3,%ra3,%i3u", 0x9c00, 2, ATTR_ALL, 0, NULL, 0, NULL},
688 {"subi333", "=rt3,%ra3,%i3u", 0x9e00, 2, ATTR_ALL, 0, NULL, 0, NULL},
689 /* SEG04 bit10~bit9. */
690 {"lwi333", "=rt3,[%ra3{+%i3u2}]", 0xa000, 2, ATTR_ALL, 0, NULL, 0, NULL},
691 {"lwi333.bi", "=rt3,[%ra3],%i3u2", 0xa200, 2, ATTR_ALL, 0, NULL, 0, NULL},
692 {"lhi333", "=rt3,[%ra3{+%i3u1}]", 0xa400, 2, ATTR_ALL, 0, NULL, 0, NULL},
693 {"lbi333", "=rt3,[%ra3{+%i3u}]", 0xa600, 2, ATTR_ALL, 0, NULL, 0, NULL},
694 /* SEG05 bit10~bit9. */
695 {"swi333", "%rt3,[%ra3{+%i3u2}]", 0xa800, 2, ATTR_ALL, 0, NULL, 0, NULL},
696 {"swi333.bi", "%rt3,[%ra3],%i3u2", 0xaa00, 2, ATTR_ALL, 0, NULL, 0, NULL},
697 {"shi333", "%rt3,[%ra3{+%i3u1}]", 0xac00, 2, ATTR_ALL, 0, NULL, 0, NULL},
698 {"sbi333", "%rt3,[%ra3{+%i3u}]", 0xae00, 2, ATTR_ALL, 0, NULL, 0, NULL},
699 /* SEG06 bit10~bit9. */
700 {"addri36.sp", "%rt3,%i6u2", 0xb000, 2, ATTR_V3MUP, USE_REG (31), NULL, 0, NULL},
701 {"lwi45.fe", "=rt4,%fe5", 0xb200, 2, ATTR_V3MUP, USE_REG (8), NULL, 0, NULL},
702 {"lwi450", "=rt4,[%ra5]", 0xb400, 2, ATTR_ALL, 0, NULL, 0, NULL},
703 {"swi450", "%rt4,[%ra5]", 0xb600, 2, ATTR_ALL, 0, NULL, 0, NULL},
705 {"lwi37", "=rt38,[$fp{+%i7u2}]", 0xb800, 2, ATTR_ALL, USE_REG (28), NULL, 0, NULL},
706 {"swi37", "%rt38,[$fp{+%i7u2}]", 0xb880, 2, ATTR_ALL, USE_REG (28), NULL, 0, NULL},
707 /* SEG10_1 if Rt3=5. */
708 {"j8", "%i8s1", 0xd500, 2, ATTR_PCREL | ATTR_ALL, 0, NULL, 0, NULL},
709 /* SEG11_2 bit7~bit5. */
710 {"jr5", "%ra5", 0xdd00, 2, ATTR_ALL, 0, NULL, 0, NULL},
711 {"jral5", "%ra5", 0xdd20, 2, ATTR_ALL, 0, NULL, 0, NULL},
712 {"ex9.it", "%i5u", 0xdd40, 2, ATTR (EX9_EXT), 0, NULL, 0, NULL},
713 {"ret5", "%ra5", 0xdd80, 2, ATTR_ALL, 0, NULL, 0, NULL},
714 {"add5.pc", "%ra5", 0xdda0, 2, ATTR_V3, 0, NULL, 0, NULL},
715 /* SEG11_3 if Ra5=30. */
716 {"ret5", "", 0xdd80 | RA5 (30), 2, ATTR_ALL, 0, NULL, 0, NULL},
717 /* SEG12 bit10~bit9. */
718 {"slts45", "%rt4,%ra5", 0xe000, 2, ATTR_ALL, DEF_REG (15), NULL, 0, NULL},
719 {"slt45", "%rt4,%ra5", 0xe200, 2, ATTR_ALL, DEF_REG (15), NULL, 0, NULL},
720 {"sltsi45", "%rt4,%i5u", 0xe400, 2, ATTR_ALL, DEF_REG (15), NULL, 0, NULL},
721 {"slti45", "%rt4,%i5u", 0xe600, 2, ATTR_ALL, DEF_REG (15), NULL, 0, NULL},
722 /* SEG13 bit10~bit9. */
723 {"break16", "%i5u", 0xea00, 2, ATTR_ALL, 0, NULL, 0, NULL},
724 {"addi10.sp", "%i10s", 0xec00, 2, ATTR_V2UP, USE_REG (31) | DEF_REG (31), NULL, 0, NULL},
725 {"addi10.sp", "%i10s", 0xec00, 2, ATTR_V2UP, USE_REG (31) | DEF_REG (31), NULL, 0, NULL},
727 {"beqzs8", "%i8s1", 0xe800, 2, ATTR_PCREL | ATTR_ALL, USE_REG (15), NULL, 0, NULL},
728 {"bnezs8", "%i8s1", 0xe900, 2, ATTR_PCREL | ATTR_ALL, USE_REG (15), NULL, 0, NULL},
729 /* SEG13_2 bit8~bit5. */
730 {"ex9.it", "%i9u", 0xea00, 2, ATTR (EX9_EXT), 0, NULL, 0, NULL},
732 {"lwi37.sp", "=rt38,[+%i7u2]", 0xf000, 2, ATTR_V2UP, USE_REG (31), NULL, 0, NULL},
733 {"swi37.sp", "%rt38,[+%i7u2]", 0xf080, 2, ATTR_V2UP, USE_REG (31), NULL, 0, NULL},
734 /* SEG15 bit10~bit9. */
735 {"ifcall9", "%i9u1", 0xf800, 2, ATTR (IFC_EXT), 0, NULL, 0, NULL},
736 {"movpi45", "=rt4,%pi5", 0xfa00, 2, ATTR_V3MUP, 0, NULL, 0, NULL},
738 {"movd44", "=rt5e,%ra5e", 0xfd00, 2, ATTR_V3MUP, 0, NULL, 0, NULL},
740 /* SEG-BFMI333 bit2~bit0. */
741 {"zeb33", "=rt3,%ra3", 0x9600, 2, ATTR_ALL, 0, NULL, 0, NULL},
742 {"zeh33", "=rt3,%ra3", 0x9601, 2, ATTR_ALL, 0, NULL, 0, NULL},
743 {"seb33", "=rt3,%ra3", 0x9602, 2, ATTR_ALL, 0, NULL, 0, NULL},
744 {"seh33", "=rt3,%ra3", 0x9603, 2, ATTR_ALL, 0, NULL, 0, NULL},
745 {"xlsb33", "=rt3,%ra3", 0x9604, 2, ATTR_ALL, 0, NULL, 0, NULL},
746 {"x11b33", "=rt3,%ra3", 0x9605, 2, ATTR_ALL, 0, NULL, 0, NULL},
747 {"bmski33", "=rt3,%ia3u", 0x9606, 2, ATTR_V3MUP, 0, NULL, 0, NULL},
748 {"fexti33", "=rt3,%ia3u", 0x9607, 2, ATTR_V3MUP, 0, NULL, 0, NULL},
749 /* SEG-PUSHPOP25 bit8~bit7. */
750 {"push25", "%re2,%i5u3", 0xfc00, 2, ATTR_V3MUP, USE_REG (31) | DEF_REG (31), NULL, 0, NULL},
751 {"pop25", "%re2,%i5u3", 0xfc80, 2, ATTR_V3MUP, USE_REG (31) | DEF_REG (31), NULL, 0, NULL},
752 /* SEG-MISC33 bit2~bit0. */
753 {"neg33", "=rt3,%ra3", 0xfe02, 2, ATTR_V3MUP, 0, NULL, 0, NULL},
754 {"not33", "=rt3,%ra3", 0xfe03, 2, ATTR_V3MUP, 0, NULL, 0, NULL},
755 {"mul33", "=rt3,%ra3", 0xfe04, 2, ATTR_V3MUP, 0, NULL, 0, NULL},
756 {"xor33", "=rt3,%ra3", 0xfe05, 2, ATTR_V3MUP, 0, NULL, 0, NULL},
757 {"and33", "=rt3,%ra3", 0xfe06, 2, ATTR_V3MUP, 0, NULL, 0, NULL},
758 {"or33", "=rt3,%ra3", 0xfe07, 2, ATTR_V3MUP, 0, NULL, 0, NULL},
759 /* SEG-Alias instructions. */
760 {"nop16", "", 0x9200, 2, ATTR_ALL, 0, NULL, 0, NULL},
761 {"ifret16", "", 0x83ff, 2, ATTR (IFC_EXT), 0, NULL, 0, NULL},
763 /* Saturation ext ISA. */
764 {"kaddw", "=rt,%ra,%rb", ALU2 (KADD), 4, ATTR (SATURATION_EXT), 0, NULL, 0, NULL},
765 {"ksubw", "=rt,%ra,%rb", ALU2 (KSUB), 4, ATTR (SATURATION_EXT), 0, NULL, 0, NULL},
766 {"kaddh", "=rt,%ra,%rb", ALU2 (KADD) | N32_BIT (6), 4, ATTR (SATURATION_EXT), 0, NULL, 0, NULL},
767 {"ksubh", "=rt,%ra,%rb", ALU2 (KSUB) | N32_BIT (6), 4, ATTR (SATURATION_EXT), 0, NULL, 0, NULL},
768 {"kdmbb", "=rt,%ra,%rb", ALU2 (KMxy), 4, ATTR (SATURATION_EXT), 0, NULL, 0, NULL},
769 {"kdmbt", "=rt,%ra,%rb", ALU2 (KMxy) | N32_BIT (6), 4, ATTR (SATURATION_EXT), 0, NULL, 0, NULL},
770 {"kdmtb", "=rt,%ra,%rb", ALU2 (KMxy) | N32_BIT (7), 4, ATTR (SATURATION_EXT), 0, NULL, 0, NULL},
771 {"kdmtt", "=rt,%ra,%rb", ALU2 (KMxy) | N32_BIT (6) | N32_BIT (7), 4, ATTR (SATURATION_EXT), 0, NULL, 0, NULL},
772 {"khmbb", "=rt,%ra,%rb", ALU2 (KMxy) | N32_BIT (8), 4, ATTR (SATURATION_EXT), 0, NULL, 0, NULL},
773 {"khmbt", "=rt,%ra,%rb", ALU2 (KMxy) | N32_BIT (8) | N32_BIT (6), 4, ATTR (SATURATION_EXT), 0, NULL, 0, NULL},
774 {"khmtb", "=rt,%ra,%rb", ALU2 (KMxy) | N32_BIT (8) | N32_BIT (7), 4, ATTR (SATURATION_EXT), 0, NULL, 0, NULL},
775 {"khmtt", "=rt,%ra,%rb", ALU2 (KMxy) | N32_BIT (8) | N32_BIT (6) | N32_BIT (7), 4, ATTR (SATURATION_EXT), 0, NULL, 0, NULL},
776 {"kslraw", "=rt,%ra,%rb", ALU2 (KSLRA), 4, ATTR (SATURATION_EXT), 0, NULL, 0, NULL},
777 {"rdov", "=rt", ALU2 (MFUSR) | N32_BIT (6) | ( 0x1e << 15), 4, ATTR (SATURATION_EXT), 0, NULL, 0, NULL},
778 {"clrov", "", ALU2 (MTUSR) | N32_BIT (6) | ( 0x1e << 15), 4, ATTR (SATURATION_EXT), 0, NULL, 0, NULL},
780 /* Audio ext. instructions. */
782 {"amtari", "%aridxi,%imm16", AUDIO (AMTARI), 4, ATTR (AUDIO_ISAEXT), 0, NULL, 0, NULL},
784 {"alr2", "=a_rt,=a_ru,[%im6_ip],[%im6_iq],%im6_mr,%im6_ms", AUDIO (AMADD) | (0x1 << 6), 4, ATTR (AUDIO_ISAEXT), 0, NULL, 0, NULL},
785 {"amaddl.s", "=a_dx,%ra,%rb,[%im5_i],%im5_m", AUDIO (AMADD) | (0x04 << 5), 4, ATTR (AUDIO_ISAEXT), 0, NULL, 0, NULL},
786 {"amaddl.l", "=a_dx,%a_a30,%a_b20,%a_rt21,[%im5_i],%im5_m", AUDIO (AMADD) | (0x06 << 5), 4, ATTR (AUDIO_ISAEXT), 0, NULL, 0, NULL},
787 {"amaddl2.s", "=a_dx,%ra,%rb,[%im6_ip],[%im6_iq],%im6_mr,%im6_ms", AUDIO (AMADD) | (0x08 << 5), 4, ATTR (AUDIO_ISAEXT), 0, NULL, 0, NULL},
788 {"amaddl2.l", "=a_dx,%a_a30,%a_b20,%a_rte,%a_rte1,[%im6_ip],[%im6_iq],%im6_mr,%im6_ms", AUDIO (AMADD) | (0x0A << 5), 4, ATTR (AUDIO_ISAEXT), 0, NULL, 0, NULL},
789 {"amaddsa", "=a_dx,%ra,%rb,%dhy,[%im5_i],%im5_m", AUDIO (AMADD) | (0x0C << 5), 4, ATTR (AUDIO_ISAEXT), 0, NULL, 0, NULL},
790 {"alr", "=a_rt,[%im5_i],%im5_m", AUDIO (AMADD) | (0x01 << 5), 4, ATTR (AUDIO_ISAEXT), 0, NULL, 0, NULL},
791 {"amadd", "=a_dx,%ra,%rb", AUDIO (AMADD), 4, ATTR (AUDIO_ISAEXT), 0, NULL, 0, NULL},
792 {"amabbs", "=a_dx,%ra,%rb", AUDIO (AMADD) | 0x01, 4, ATTR (AUDIO_ISAEXT), 0, NULL, 0, NULL},
794 {"amsubl.s", "=a_dx,%ra,%rb,[%im5_i],%im5_m", AUDIO (AMSUB) | (0x04 << 5), 4, ATTR (AUDIO_ISAEXT), 0, NULL, 0, NULL},
795 {"amsubl.l", "=a_dx,%a_a30,%a_b20,%a_rt21,[%im5_i],%im5_m", AUDIO (AMSUB) | (0x06 << 5), 4, ATTR (AUDIO_ISAEXT), 0, NULL, 0, NULL},
796 {"amsubl2.s", "=a_dx,%ra,%rb,[%im6_ip],[%im6_iq],%im6_mr,%im6_ms", AUDIO (AMSUB) | (0x08 << 5), 4, ATTR (AUDIO_ISAEXT), 0, NULL, 0, NULL},
797 {"amsubl2.l", "=a_dx,%a_a30,%a_b20,%a_rte,%a_rte1,[%im6_ip],[%im6_iq],%im6_mr,%im6_ms", AUDIO (AMSUB) | (0x0A << 5), 4, ATTR (AUDIO_ISAEXT), 0, NULL, 0, NULL},
798 {"amsubsa", "=a_dx,%ra,%rb,%dhy,[%im5_i],%im5_m", AUDIO (AMSUB) | (0x0C << 5), 4, ATTR (AUDIO_ISAEXT), 0, NULL, 0, NULL},
799 {"asr", "%ra,[%im5_i],%im5_m", AUDIO (AMSUB) | (0x01 << 5), 4, ATTR (AUDIO_ISAEXT), 0, NULL, 0, NULL},
800 {"amsub", "=a_dx,%ra,%rb", AUDIO (AMSUB), 4, ATTR (AUDIO_ISAEXT), 0, NULL, 0, NULL},
801 {"amabts", "=a_dx,%ra,%rb", AUDIO (AMSUB) |0x01, 4, ATTR (AUDIO_ISAEXT), 0, NULL, 0, NULL},
803 {"amultl.s", "=a_dx,%ra,%rb,[%im5_i],%im5_m", AUDIO (AMULT) | (0x04 << 5), 4, ATTR (AUDIO_ISAEXT), 0, NULL, 0, NULL},
804 {"amultl.l", "=a_dx,%a_a30,%a_b20,%a_rt21,[%im5_i],%im5_m", AUDIO (AMULT) | (0x06 << 5), 4, ATTR (AUDIO_ISAEXT), 0, NULL, 0, NULL},
805 {"amultl2.s", "=a_dx,%ra,%rb,[%im6_ip],[%im6_iq],%im6_mr,%im6_ms", AUDIO (AMULT) | (0x08 << 5), 4, ATTR (AUDIO_ISAEXT), 0, NULL, 0, NULL},
806 {"amultl2.l", "=a_dx,%a_a30,%a_b20,%a_rte,%a_rte1,[%im6_ip],[%im6_iq],%im6_mr,%im6_ms", AUDIO (AMULT) | (0x0A << 5), 4, ATTR (AUDIO_ISAEXT), 0, NULL, 0, NULL},
807 {"amultsa", "=a_dx,%ra,%rb,%dhy,[%im5_i],%im5_m", AUDIO (AMULT) | (0x0C << 5), 4, ATTR (AUDIO_ISAEXT), 0, NULL, 0, NULL},
808 {"ala", "=dxh,[%im5_i],%im5_m", AUDIO (AMULT) | (0x01 << 5), 4, ATTR (AUDIO_ISAEXT), 0, NULL, 0, NULL},
809 {"amult", "=a_dx,%ra,%rb", AUDIO (AMULT), 4, ATTR (AUDIO_ISAEXT), 0, NULL, 0, NULL},
810 {"amatbs", "=a_dx,%ra,%rb", AUDIO (AMULT) |0x01, 4, ATTR (AUDIO_ISAEXT), 0, NULL, 0, NULL},
811 {"asats48", "=a_dx", AUDIO (AMULT) | (0x02 << 5), 4, ATTR (AUDIO_ISAEXT), 0, NULL, 0, NULL},
812 {"awext", "%ra,%a_dx,%i5u", AUDIO (AMULT) | (0x03 << 5), 4, ATTR (AUDIO_ISAEXT), 0, NULL, 0, NULL},
814 {"amatts", "=a_dx,%ra,%rb", AUDIO (AMFAR) | 0x01, 4, ATTR (AUDIO_ISAEXT), 0, NULL, 0, NULL},
815 {"asa", "=dxh,[%im5_i],%im5_m", AUDIO (AMFAR) | (0x01 << 5), 4, ATTR (AUDIO_ISAEXT), 0, NULL, 0, NULL},
816 {"amtar", "%ra,%aridx", AUDIO (AMFAR) | (0x02 << 5), 4, ATTR (AUDIO_ISAEXT), 0, NULL, 0, NULL},
817 {"amtar2", "%ra,%aridx2", AUDIO (AMFAR) | (0x12 << 5), 4, ATTR (AUDIO_ISAEXT), 0, NULL, 0, NULL},
818 {"amfar", "=ra,%aridx", AUDIO (AMFAR) | (0x03 << 5), 4, ATTR (AUDIO_ISAEXT), 0, NULL, 0, NULL},
819 {"amfar2", "=ra,%aridx2", AUDIO (AMFAR) | (0x13 << 5), 4, ATTR (AUDIO_ISAEXT), 0, NULL, 0, NULL},
820 /* N32_AEXT_AMADDS */
821 {"amaddsl.s", "=a_dx,%ra,%rb,[%im5_i],%im5_m", AUDIO (AMADDS) | (0x04 << 5), 4, ATTR (AUDIO_ISAEXT), 0, NULL, 0, NULL},
822 {"amaddsl.l", "=a_dx,%a_a30,%a_b20,%a_rt21,[%im5_i],%im5_m", AUDIO (AMADDS) | (0x06 << 5), 4, ATTR (AUDIO_ISAEXT), 0, NULL, 0, NULL},
823 {"amaddsl2.s", "=a_dx,%ra,%rb,[%im6_ip],[%im6_iq],%im6_mr,%im6_ms", AUDIO (AMADDS) | (0x08 << 5), 4, ATTR (AUDIO_ISAEXT), 0, NULL, 0, NULL},
824 {"amaddsl2.l", "=a_dx,%a_a30,%a_b20,%a_rte,%a_rte1,[%im6_ip],[%im6_iq],%im6_mr,%im6_ms", AUDIO (AMADDS) | (0x0A << 5), 4, ATTR (AUDIO_ISAEXT), 0, NULL, 0, NULL},
825 {"amaddssa", "=a_dx,%ra,%rb,%dhy,[%im5_i],%im5_m", AUDIO (AMADDS) | (0x0C << 5), 4, ATTR (AUDIO_ISAEXT), 0, NULL, 0, NULL},
826 {"aupi", "%im5_i,%im5_m", AUDIO (AMADDS) | (0x01 << 5), 4, ATTR (AUDIO_ISAEXT), 0, NULL, 0, NULL},
827 {"amadds", "=a_dx,%ra,%rb", AUDIO (AMADDS), 4, ATTR (AUDIO_ISAEXT), 0, NULL, 0, NULL},
828 {"ambbs", "=a_dx,%ra,%rb", AUDIO (AMADDS) |0x01, 4, ATTR (AUDIO_ISAEXT), 0, NULL, 0, NULL},
829 {"amawbs", "=a_dx,%ra,%rb", AUDIO (AMADDS) |0x02, 4, ATTR (AUDIO_ISAEXT), 0, NULL, 0, NULL},
830 /* N32_AEXT_AMSUBS */
831 {"amsubsl.s", "=a_dx,%ra,%rb,[%im5_i],%im5_m", AUDIO (AMSUBS) | (0x04 << 5), 4, ATTR (AUDIO_ISAEXT), 0, NULL, 0, NULL},
832 {"amsubsl.l", "=a_dx,%a_a30,%a_b20,%a_rt21,[%im5_i],%im5_m", AUDIO (AMSUBS) | (0x06 << 5), 4, ATTR (AUDIO_ISAEXT), 0, NULL, 0, NULL},
833 {"amsubsl2.s", "=a_dx,%ra,%rb,[%im6_ip],[%im6_iq],%im6_mr,%im6_ms", AUDIO (AMSUBS) | (0x08 << 5), 4, ATTR (AUDIO_ISAEXT), 0, NULL, 0, NULL},
834 {"amsubsl2.l", "=a_dx,%a_a30,%a_b20,%a_rte,%a_rte1,[%im6_ip],[%im6_iq],%im6_mr,%im6_ms", AUDIO (AMSUBS) | (0x0A << 5), 4, ATTR (AUDIO_ISAEXT), 0, NULL, 0, NULL},
835 {"amsubssa", "=a_dx,%ra,%rb,%dhy,[%im5_i],%im5_m", AUDIO (AMSUBS) | (0x0C << 5), 4, ATTR (AUDIO_ISAEXT), 0, NULL, 0, NULL},
836 {"amsubs", "=a_dx,%ra,%rb", AUDIO (AMSUBS), 4, ATTR (AUDIO_ISAEXT), 0, NULL, 0, NULL},
837 {"ambts", "=a_dx,%ra,%rb", AUDIO (AMSUBS) |0x01, 4, ATTR (AUDIO_ISAEXT), 0, NULL, 0, NULL},
838 {"amawts", "=a_dx,%ra,%rb", AUDIO (AMSUBS) |0x02, 4, ATTR (AUDIO_ISAEXT), 0, NULL, 0, NULL},
839 /* N32_AEXT_AMULTS */
840 {"amultsl.s", "=a_dx,%ra,%rb,[%im5_i],%im5_m", AUDIO (AMULTS) | (0x04 << 5), 4, ATTR (AUDIO_ISAEXT), 0, NULL, 0, NULL},
841 {"amultsl.l", "=a_dx,%a_a30,%a_b20,%a_rt21,[%im5_i],%im5_m", AUDIO (AMULTS) | (0x06 << 5), 4, ATTR (AUDIO_ISAEXT), 0, NULL, 0, NULL},
842 {"amultsl2.s", "=a_dx,%ra,%rb,[%im6_ip],[%im6_iq],%im6_mr,%im6_ms", AUDIO (AMULTS) | (0x08 << 5), 4, ATTR (AUDIO_ISAEXT), 0, NULL, 0, NULL},
843 {"amultsl2.l", "=a_dx,%a_a30,%a_b20,%a_rte,%a_rte1,[%im6_ip],[%im6_iq],%im6_mr,%im6_ms", AUDIO (AMULTS) | (0x0A << 5), 4, ATTR (AUDIO_ISAEXT), 0, NULL, 0, NULL},
844 {"amultssa", "=a_dx,%ra,%rb,%dhy,[%im5_i],%im5_m", AUDIO (AMULTS) | (0x0C << 5), 4, ATTR (AUDIO_ISAEXT), 0, NULL, 0, NULL},
845 {"amults", "=a_dx,%ra,%rb", AUDIO (AMULTS), 4, ATTR (AUDIO_ISAEXT), 0, NULL, 0, NULL},
846 {"amtbs", "=a_dx,%ra,%rb", AUDIO (AMULTS) |0x01, 4, ATTR (AUDIO_ISAEXT), 0, NULL, 0, NULL},
847 {"amwbs", "=a_dx,%ra,%rb", AUDIO (AMULTS) |0x02, 4, ATTR (AUDIO_ISAEXT), 0, NULL, 0, NULL},
848 /* N32_AEXT_AMNEGS */
849 {"amnegsl.s", "=a_dx,%ra,%rb,[%im5_i],%im5_m", AUDIO (AMNEGS) | (0x04 << 5), 4, ATTR (AUDIO_ISAEXT), 0, NULL, 0, NULL},
850 {"amnegsl.l", "=a_dx,%a_a30,%a_b20,%a_rt21,[%im5_i],%im5_m", AUDIO (AMNEGS) | (0x06 << 5), 4, ATTR (AUDIO_ISAEXT), 0, NULL, 0, NULL},
851 {"amnegsl2.s", "=a_dx,%ra,%rb,[%im6_ip],[%im6_iq],%im6_mr,%im6_ms", AUDIO (AMNEGS) | (0x08 << 5), 4, ATTR (AUDIO_ISAEXT), 0, NULL, 0, NULL},
852 {"amnegsl2.l", "=a_dx,%a_a30,%a_b20,%a_rte,%a_rte1,[%im6_ip],[%im6_iq],%im6_mr,%im6_ms", AUDIO (AMNEGS) | (0x0A << 5), 4, ATTR (AUDIO_ISAEXT), 0, NULL, 0, NULL},
853 {"amnegssa", "=a_dx,%ra,%rb,%dhy,[%im5_i],%im5_m", AUDIO (AMNEGS) | (0x0C << 5), 4, ATTR (AUDIO_ISAEXT), 0, NULL, 0, NULL},
854 {"amnegs", "=a_dx,%ra,%rb", AUDIO (AMNEGS), 4, ATTR (AUDIO_ISAEXT), 0, NULL, 0, NULL},
855 {"amtts", "=a_dx,%ra,%rb", AUDIO (AMNEGS) |0x01, 4, ATTR (AUDIO_ISAEXT), 0, NULL, 0, NULL},
856 {"amwts", "=a_dx,%ra,%rb", AUDIO (AMNEGS) |0x02, 4, ATTR (AUDIO_ISAEXT), 0, NULL, 0, NULL},
858 {"aaddl", "=a_rte69,%ra,%rb,%a_rte69_1,[%im5_i],%im5_m", AUDIO (AADDL), 4, ATTR (AUDIO_ISAEXT), 0, NULL, 0, NULL},
859 {"asubl", "=a_rte69,%ra,%rb,%a_rte69_1,[%im5_i],%im5_m", AUDIO (AADDL) | (0x01 << 5), 4, ATTR (AUDIO_ISAEXT), 0, NULL, 0, NULL},
860 /* N32_AEXT_AMAWBS */
861 {"amawbsl.s", "=a_dx,%ra,%rb,[%im5_i],%im5_m", AUDIO (AMAWBS) | (0x04 << 5), 4, ATTR (AUDIO_ISAEXT), 0, NULL, 0, NULL},
862 {"amawbsl.l", "=a_dx,%a_a30,%a_b20,%a_rt21,[%im5_i],%im5_m", AUDIO (AMAWBS) | (0x06 << 5), 4, ATTR (AUDIO_ISAEXT), 0, NULL, 0, NULL},
863 {"amawbsl2.s", "=a_dx,%ra,%rb,[%im6_ip],[%im6_iq],%im6_mr,%im6_ms", AUDIO (AMAWBS) | (0x08 << 5), 4, ATTR (AUDIO_ISAEXT), 0, NULL, 0, NULL},
864 {"amawbsl2.l", "=a_dx,%a_a30,%a_b20,%a_rte,%a_rte1,[%im6_ip],[%im6_iq],%im6_mr,%im6_ms", AUDIO (AMAWBS) | (0x0A << 5), 4, ATTR (AUDIO_ISAEXT), 0, NULL, 0, NULL},
865 {"amawbssa", "=a_dx,%ra,%rb,%dhy,[%im5_i],%im5_m", AUDIO (AMAWBS) | (0x0C << 5), 4, ATTR (AUDIO_ISAEXT), 0, NULL, 0, NULL},
866 /* N32_AEXT_AMAWTS */
867 {"amawtsl.s", "=a_dx,%ra,%rb,[%im5_i],%im5_m", AUDIO (AMAWTS) | (0x04 << 5), 4, ATTR (AUDIO_ISAEXT), 0, NULL, 0, NULL},
868 {"amawtsl.l", "=a_dx,%a_a30,%a_b20,%a_rt21,[%im5_i],%im5_m", AUDIO (AMAWTS) | (0x06 << 5), 4, ATTR (AUDIO_ISAEXT), 0, NULL, 0, NULL},
869 {"amawtsl2.s", "=a_dx,%ra,%rb,[%im6_ip],[%im6_iq],%im6_mr,%im6_ms", AUDIO (AMAWTS) | (0x08 << 5), 4, ATTR (AUDIO_ISAEXT), 0, NULL, 0, NULL},
870 {"amawtsl2.l", "=a_dx,%a_a30,%a_b20,%a_rte,%a_rte1,[%im6_ip],[%im6_iq],%im6_mr,%im6_ms", AUDIO (AMAWTS) | (0x0A << 5), 4, ATTR (AUDIO_ISAEXT), 0, NULL, 0, NULL},
871 {"amawtssa", "=a_dx,%ra,%rb,%dhy,[%im5_i],%im5_m", AUDIO (AMAWTS) | (0x0C << 5), 4, ATTR (AUDIO_ISAEXT), 0, NULL, 0, NULL},
873 {"amwbsl.s", "=a_dx,%ra,%rb,[%im5_i],%im5_m", AUDIO (AMWBS) | (0x04 << 5), 4, ATTR (AUDIO_ISAEXT), 0, NULL, 0, NULL},
874 {"amwbsl.l", "=a_dx,%a_a30,%a_b20,%a_rt21,[%im5_i],%im5_m", AUDIO (AMWBS) | (0x06 << 5), 4, ATTR (AUDIO_ISAEXT), 0, NULL, 0, NULL},
875 {"amwbsl2.s", "=a_dx,%ra,%rb,[%im6_ip],[%im6_iq],%im6_mr,%im6_ms", AUDIO (AMWBS) | (0x08 << 5), 4, ATTR (AUDIO_ISAEXT), 0, NULL, 0, NULL},
876 {"amwbsl2.l", "=a_dx,%a_a30,%a_b20,%a_rte,%a_rte1,[%im6_ip],[%im6_iq],%im6_mr,%im6_ms", AUDIO (AMWBS) | (0x0A << 5), 4, ATTR (AUDIO_ISAEXT), 0, NULL, 0, NULL},
877 {"amwbssa", "=a_dx,%ra,%rb,%dhy,[%im5_i],%im5_m", AUDIO (AMWBS) | (0x0C << 5), 4, ATTR (AUDIO_ISAEXT), 0, NULL, 0, NULL},
878 {"amwbssa", "=a_dx,%ra,%rb,%dhy,[%im5_i],%im5_m", AUDIO (AMWBS) | (0x0C << 5), 4, ATTR (AUDIO_ISAEXT), 0, NULL, 0, NULL},
880 {"amwtsl.s", "=a_dx,%ra,%rb,[%im5_i],%im5_m", AUDIO (AMWTS) | (0x04 << 5), 4, ATTR (AUDIO_ISAEXT), 0, NULL, 0, NULL},
881 {"amwtsl.l", "=a_dx,%a_a30,%a_b20,%a_rt21,[%im5_i],%im5_m", AUDIO (AMWTS) | (0x06 << 5), 4, ATTR (AUDIO_ISAEXT), 0, NULL, 0, NULL},
882 {"amwtsl2.s", "=a_dx,%ra,%rb,[%im6_ip],[%im6_iq],%im6_mr,%im6_ms", AUDIO (AMWTS) | (0x08 << 5), 4, ATTR (AUDIO_ISAEXT), 0, NULL, 0, NULL},
883 {"amwtsl2.l", "=a_dx,%a_a30,%a_b20,%a_rte,%a_rte1,[%im6_ip],[%im6_iq],%im6_mr,%im6_ms", AUDIO (AMWTS) | (0x0A << 5), 4, ATTR (AUDIO_ISAEXT), 0, NULL, 0, NULL},
884 {"amwtssa", "=a_dx,%ra,%rb,%dhy,[%im5_i],%im5_m", AUDIO (AMWTS) | (0x0C << 5), 4, ATTR (AUDIO_ISAEXT), 0, NULL, 0, NULL},
885 /* N32_AEXT_AMABBS */
886 {"amabbsl.s", "=a_dx,%ra,%rb,[%im5_i],%im5_m", AUDIO (AMABBS) | (0x04 << 5), 4, ATTR (AUDIO_ISAEXT), 0, NULL, 0, NULL},
887 {"amabbsl.l", "=a_dx,%a_a30,%a_b20,%a_rt21,[%im5_i],%im5_m", AUDIO (AMABBS) | (0x06 << 5), 4, ATTR (AUDIO_ISAEXT), 0, NULL, 0, NULL},
888 {"amabbsl2.s", "=a_dx,%ra,%rb,[%im6_ip],[%im6_iq],%im6_mr,%im6_ms", AUDIO (AMABBS) | (0x08 << 5), 4, ATTR (AUDIO_ISAEXT), 0, NULL, 0, NULL},
889 {"amabbsl2.l", "=a_dx,%a_a30,%a_b20,%a_rte,%a_rte1,[%im6_ip],[%im6_iq],%im6_mr,%im6_ms", AUDIO (AMABBS) | (0x0A << 5), 4, ATTR (AUDIO_ISAEXT), 0, NULL, 0, NULL},
890 {"amabbssa", "=a_dx,%ra,%rb,%dhy,[%im5_i],%im5_m", AUDIO (AMABBS) | (0x0C << 5), 4, ATTR (AUDIO_ISAEXT), 0, NULL, 0, NULL},
891 /* N32_AEXT_AMABTS */
892 {"amabtsl.s", "=a_dx,%ra,%rb,[%im5_i],%im5_m", AUDIO (AMABTS) | (0x04 << 5), 4, ATTR (AUDIO_ISAEXT), 0, NULL, 0, NULL},
893 {"amabtsl.l", "=a_dx,%a_a30,%a_b20,%a_rt21,[%im5_i],%im5_m", AUDIO (AMABTS) | (0x06 << 5), 4, ATTR (AUDIO_ISAEXT), 0, NULL, 0, NULL},
894 {"amabtsl2.s", "=a_dx,%ra,%rb,[%im6_ip],[%im6_iq],%im6_mr,%im6_ms", AUDIO (AMABTS) | (0x08 << 5), 4, ATTR (AUDIO_ISAEXT), 0, NULL, 0, NULL},
895 {"amabtsl2.l", "=a_dx,%a_a30,%a_b20,%a_rte,%a_rte1,[%im6_ip],[%im6_iq],%im6_mr,%im6_ms", AUDIO (AMABTS) | (0x0A << 5), 4, ATTR (AUDIO_ISAEXT), 0, NULL, 0, NULL},
896 {"amabtssa", "=a_dx,%ra,%rb,%dhy,[%im5_i],%im5_m", AUDIO (AMABTS) | (0x0C << 5), 4, ATTR (AUDIO_ISAEXT), 0, NULL, 0, NULL},
897 /* N32_AEXT_AMATBS */
898 {"amatbsl.s", "=a_dx,%ra,%rb,[%im5_i],%im5_m", AUDIO (AMATBS) | (0x04 << 5), 4, ATTR (AUDIO_ISAEXT), 0, NULL, 0, NULL},
899 {"amatbsl.l", "=a_dx,%a_a30,%a_b20,%a_rt21,[%im5_i],%im5_m", AUDIO (AMATBS) | (0x06 << 5), 4, ATTR (AUDIO_ISAEXT), 0, NULL, 0, NULL},
900 {"amatbsl2.s", "=a_dx,%ra,%rb,[%im6_ip],[%im6_iq],%im6_mr,%im6_ms", AUDIO (AMATBS) | (0x08 << 5), 4, ATTR (AUDIO_ISAEXT), 0, NULL, 0, NULL},
901 {"amatbsl2.l", "=a_dx,%a_a30,%a_b20,%a_rte,%a_rte1,[%im6_ip],[%im6_iq],%im6_mr,%im6_ms", AUDIO (AMATBS) | (0x0A << 5), 4, ATTR (AUDIO_ISAEXT), 0, NULL, 0, NULL},
902 {"amatbssa", "=a_dx,%ra,%rb,%dhy,[%im5_i],%im5_m", AUDIO (AMATBS) | (0x0C << 5), 4, ATTR (AUDIO_ISAEXT), 0, NULL, 0, NULL},
903 /* N32_AEXT_AMATTS */
904 {"amattsl.s", "=a_dx,%ra,%rb,[%im5_i],%im5_m", AUDIO (AMATTS) | (0x04 << 5), 4, ATTR (AUDIO_ISAEXT), 0, NULL, 0, NULL},
905 {"amattsl.l", "=a_dx,%a_a30,%a_b20,%a_rt21,[%im5_i],%im5_m", AUDIO (AMATTS) | (0x06 << 5), 4, ATTR (AUDIO_ISAEXT), 0, NULL, 0, NULL},
906 {"amattsl2.s", "=a_dx,%ra,%rb,[%im6_ip],[%im6_iq],%im6_mr,%im6_ms", AUDIO (AMATTS) | (0x08 << 5), 4, ATTR (AUDIO_ISAEXT), 0, NULL, 0, NULL},
907 {"amattsl2.l", "=a_dx,%a_a30,%a_b20,%a_rte,%a_rte1,[%im6_ip],[%im6_iq],%im6_mr,%im6_ms", AUDIO (AMATTS) | (0x0A << 5), 4, ATTR (AUDIO_ISAEXT), 0, NULL, 0, NULL},
908 {"amattssa", "=a_dx,%ra,%rb,%dhy,[%im5_i],%im5_m", AUDIO (AMATTS) | (0x0C << 5), 4, ATTR (AUDIO_ISAEXT), 0, NULL, 0, NULL},
910 {"ambbsl.s", "=a_dx,%ra,%rb,[%im5_i],%im5_m", AUDIO (AMBBS) | (0x04 << 5), 4, ATTR (AUDIO_ISAEXT), 0, NULL, 0, NULL},
911 {"ambbsl.l", "=a_dx,%a_a30,%a_b20,%a_rt21,[%im5_i],%im5_m", AUDIO (AMBBS) | (0x06 << 5), 4, ATTR (AUDIO_ISAEXT), 0, NULL, 0, NULL},
912 {"ambbsl2.s", "=a_dx,%ra,%rb,[%im6_ip],[%im6_iq],%im6_mr,%im6_ms", AUDIO (AMBBS) | (0x08 << 5), 4, ATTR (AUDIO_ISAEXT), 0, NULL, 0, NULL},
913 {"ambbsl2.l", "=a_dx,%a_a30,%a_b20,%a_rte,%a_rte1,[%im6_ip],[%im6_iq],%im6_mr,%im6_ms", AUDIO (AMBBS) | (0x0A << 5), 4, ATTR (AUDIO_ISAEXT), 0, NULL, 0, NULL},
914 {"ambbssa", "=a_dx,%ra,%rb,%dhy,[%im5_i],%im5_m", AUDIO (AMBBS) | (0x0C << 5), 4, ATTR (AUDIO_ISAEXT), 0, NULL, 0, NULL},
916 {"ambtsl.s", "=a_dx,%ra,%rb,[%im5_i],%im5_m", AUDIO (AMBTS) | (0x04 << 5), 4, ATTR (AUDIO_ISAEXT), 0, NULL, 0, NULL},
917 {"ambtsl.l", "=a_dx,%a_a30,%a_b20,%a_rt21,[%im5_i],%im5_m", AUDIO (AMBTS) | (0x06 << 5), 4, ATTR (AUDIO_ISAEXT), 0, NULL, 0, NULL},
918 {"ambtsl2.s", "=a_dx,%ra,%rb,[%im6_ip],[%im6_iq],%im6_mr,%im6_ms", AUDIO (AMBTS) | (0x08 << 5), 4, ATTR (AUDIO_ISAEXT), 0, NULL, 0, NULL},
919 {"ambtsl2.l", "=a_dx,%a_a30,%a_b20,%a_rte,%a_rte1,[%im6_ip],[%im6_iq],%im6_mr,%im6_ms", AUDIO (AMBTS) | (0x0A << 5), 4, ATTR (AUDIO_ISAEXT), 0, NULL, 0, NULL},
920 {"ambtssa", "=a_dx,%ra,%rb,%dhy,[%im5_i],%im5_m", AUDIO (AMBTS) | (0x0C << 5), 4, ATTR (AUDIO_ISAEXT), 0, NULL, 0, NULL},
922 {"amtbsl.s", "=a_dx,%ra,%rb,[%im5_i],%im5_m", AUDIO (AMTBS) | (0x04 << 5), 4, ATTR (AUDIO_ISAEXT), 0, NULL, 0, NULL},
923 {"amtbsl.l", "=a_dx,%a_a30,%a_b20,%a_rt21,[%im5_i],%im5_m", AUDIO (AMTBS) | (0x06 << 5), 4, ATTR (AUDIO_ISAEXT), 0, NULL, 0, NULL},
924 {"amtbsl2.s", "=a_dx,%ra,%rb,[%im6_ip],[%im6_iq],%im6_mr,%im6_ms", AUDIO (AMTBS) | (0x08 << 5), 4, ATTR (AUDIO_ISAEXT), 0, NULL, 0, NULL},
925 {"amtbsl2.l", "=a_dx,%a_a30,%a_b20,%a_rte,%a_rte1,[%im6_ip],[%im6_iq],%im6_mr,%im6_ms", AUDIO (AMTBS) | (0x0A << 5), 4, ATTR (AUDIO_ISAEXT), 0, NULL, 0, NULL},
926 {"amtbssa", "=a_dx,%ra,%rb,%dhy,[%im5_i],%im5_m", AUDIO (AMTBS) | (0x0C << 5), 4, ATTR (AUDIO_ISAEXT), 0, NULL, 0, NULL},
928 {"amttsl.s", "=a_dx,%ra,%rb,[%im5_i],%im5_m", AUDIO (AMTTS) | (0x04 << 5), 4, ATTR (AUDIO_ISAEXT), 0, NULL, 0, NULL},
929 {"amttsl.l", "=a_dx,%a_a30,%a_b20,%a_rt21,[%im5_i],%im5_m", AUDIO (AMTTS) | (0x06 << 5), 4, ATTR (AUDIO_ISAEXT), 0, NULL, 0, NULL},
930 {"amttsl2.s", "=a_dx,%ra,%rb,[%im6_ip],[%im6_iq],%im6_mr,%im6_ms", AUDIO (AMTTS) | (0x08 << 5), 4, ATTR (AUDIO_ISAEXT), 0, NULL, 0, NULL},
931 {"amttsl2.l", "=a_dx,%a_a30,%a_b20,%a_rte,%a_rte1,[%im6_ip],[%im6_iq],%im6_mr,%im6_ms", AUDIO (AMTTS) | (0x0A << 5), 4, ATTR (AUDIO_ISAEXT), 0, NULL, 0, NULL},
932 {"amttssa", "=a_dx,%ra,%rb,%dhy,[%im5_i],%im5_m", AUDIO (AMTTS) | (0x0C << 5), 4, ATTR (AUDIO_ISAEXT), 0, NULL, 0, NULL},
933 {NULL, NULL, 0, 0, 0, 0, NULL, 0, NULL},
936 const keyword_t keyword_gpr[] =
938 /* Standard names. */
939 {"r0", 0, ATTR (RDREG)}, {"r1", 1, ATTR (RDREG)}, {"r2", 2, ATTR (RDREG)},
940 {"r3", 3, ATTR (RDREG)}, {"r4", 4, ATTR (RDREG)}, {"r5", 5, ATTR (RDREG)},
941 {"r6", 6, ATTR (RDREG)}, {"r7", 7, ATTR (RDREG)}, {"r8", 8, ATTR (RDREG)},
942 {"r9", 9, ATTR (RDREG)}, {"r10", 10, ATTR (RDREG)}, {"r11", 11, 0},
943 {"r12", 12, 0}, {"r13", 13, 0}, {"r14", 14, 0}, {"r15", 15, ATTR (RDREG)},
944 {"r16", 16, 0}, {"r17", 17, 0}, {"r18", 18, 0}, {"r19", 19, 0},
945 {"r20", 20, 0}, {"r21", 21, 0}, {"r22", 22, 0}, {"r23", 23, 0},
946 {"r24", 24, 0}, {"r25", 25, 0},
947 {"p0", 26, 0}, {"p1", 27, 0},
948 {"fp", 28, ATTR (RDREG)}, {"gp", 29, ATTR (RDREG)},
949 {"lp", 30, ATTR (RDREG)}, {"sp", 31, ATTR (RDREG)},
950 {"r26", 26, 0}, {"r27", 27, 0},
951 {"r28", 28, ATTR (RDREG)}, {"r29", 29, ATTR (RDREG)},
952 {"r30", 30, ATTR (RDREG)}, {"r31", 31, ATTR (RDREG)},
953 /* Names for parameter passing. */
954 {"a0", 0, ATTR (RDREG)}, {"a1", 1, ATTR (RDREG)},
955 {"a2", 2, ATTR (RDREG)}, {"a3", 3, ATTR (RDREG)},
956 {"a4", 4, ATTR (RDREG)}, {"a5", 5, ATTR (RDREG)},
957 /* Names reserved for 5-bit addressing only. */
958 {"s0", 6, ATTR (RDREG)}, {"s1", 7, ATTR (RDREG)},
959 {"s2", 8, ATTR (RDREG)}, {"s3", 9, ATTR (RDREG)},
960 {"s4", 10, ATTR (RDREG)}, {"s5", 11, 0}, {"s6", 12, 0}, {"s7", 13, 0},
961 {"s8", 14, 0}, {"s9", 28, ATTR (RDREG)},
962 {"ta", 15, ATTR (RDREG)},
963 {"t0", 16, 0}, {"t1", 17, 0}, {"t2", 18, 0}, {"t3", 19, 0},
964 {"t4", 20, 0}, {"t5", 21, 0}, {"t6", 22, 0}, {"t7", 23, 0},
965 {"t8", 24, 0}, {"t9", 25, 0},
966 /* Names reserved for 4-bit addressing only. */
967 {"h0", 0, ATTR (RDREG)}, {"h1", 1, ATTR (RDREG)},
968 {"h2", 2, ATTR (RDREG)}, {"h3", 3, ATTR (RDREG)},
969 {"h4", 4, ATTR (RDREG)}, {"h5", 5, ATTR (RDREG)},
970 {"h6", 6, ATTR (RDREG)}, {"h7", 7, ATTR (RDREG)},
971 {"h8", 8, ATTR (RDREG)}, {"h9", 9, ATTR (RDREG)},
972 {"h10", 10, ATTR (RDREG)}, {"h11", 11, 0},
973 {"h12", 16, 0}, {"h13", 17, 0}, {"h14", 18, 0}, {"h15", 19, 0},
974 /* Names reserved for 3-bit addressing only. */
975 {"o0", 0, ATTR (RDREG)}, {"o1", 1, ATTR (RDREG)},
976 {"o2", 2, ATTR (RDREG)}, {"o3", 3, ATTR (RDREG)},
977 {"o4", 4, ATTR (RDREG)}, {"o5", 5, ATTR (RDREG)},
978 {"o6", 6, ATTR (RDREG)}, {"o7", 7, ATTR (RDREG)},
982 const keyword_t keyword_usr[] =
984 {"d0.lo", USRIDX (0, 0), 0},
985 {"d0.hi", USRIDX (0, 1), 0},
986 {"d1.lo", USRIDX (0, 2), 0},
987 {"d1.hi", USRIDX (0, 3), 0},
988 {"itb", USRIDX (0, 28), 0},
989 {"ifc_lp", USRIDX (0, 29), 0},
990 {"pc", USRIDX (0, 31), 0},
992 {"dma_cfg", USRIDX (1, 0), 0},
993 {"dma_gcsw", USRIDX (1, 1), 0},
994 {"dma_chnsel", USRIDX (1, 2), 0},
995 {"dma_act", USRIDX (1, 3), 0},
996 {"dma_setup", USRIDX (1, 4), 0},
997 {"dma_isaddr", USRIDX (1, 5), 0},
998 {"dma_esaddr", USRIDX (1, 6), 0},
999 {"dma_tcnt", USRIDX (1, 7), 0},
1000 {"dma_status", USRIDX (1, 8), 0},
1001 {"dma_2dset", USRIDX (1, 9), 0},
1002 {"dma_rcnt", USRIDX (1, 23), 0},
1003 {"dma_hstatus", USRIDX (1, 24), 0},
1004 {"dma_2dsctl", USRIDX (1, 25), 0},
1006 {"pfmc0", USRIDX (2, 0), 0},
1007 {"pfmc1", USRIDX (2, 1), 0},
1008 {"pfmc2", USRIDX (2, 2), 0},
1009 {"pfm_ctl", USRIDX (2, 4), 0},
1014 const keyword_t keyword_dxr[] =
1016 {"d0", 0, 0}, {"d1", 1, 0}, {NULL, 0, 0}
1019 const keyword_t keyword_sr[] =
1021 {"cpu_ver", SRIDX (0, 0, 0), 0}, {"cr0", SRIDX (0, 0, 0), 0},
1022 {"icm_cfg", SRIDX (0, 1, 0), 0}, {"cr1", SRIDX (0, 1, 0), 0},
1023 {"dcm_cfg", SRIDX (0, 2, 0), 0}, {"cr2", SRIDX (0, 2, 0), 0},
1024 {"mmu_cfg", SRIDX (0, 3, 0), 0}, {"cr3", SRIDX (0, 3, 0), 0},
1025 {"msc_cfg", SRIDX (0, 4, 0), 0}, {"cr4", SRIDX (0, 4, 0), 0},
1026 {"msc_cfg2", SRIDX (0, 4, 1), 0}, {"cr7", SRIDX (0, 4, 1), 0},
1027 {"core_id", SRIDX (0, 0, 1), 0}, {"cr5", SRIDX (0, 0, 1), 0},
1028 {"fucop_exist", SRIDX (0, 5, 0), 0}, {"cr6", SRIDX (0, 5, 0), 0},
1030 {"psw", SRIDX (1, 0, 0), 0}, {"ir0", SRIDX (1, 0, 0), 0},
1031 {"ipsw", SRIDX (1, 0, 1), 0}, {"ir1", SRIDX (1, 0, 1), 0},
1032 {"p_ipsw", SRIDX (1, 0, 2), 0}, {"ir2", SRIDX (1, 0, 2), 0},
1033 {"ivb", SRIDX (1, 1, 1), 0}, {"ir3", SRIDX (1, 1, 1), 0},
1034 {"eva", SRIDX (1, 2, 1), 0}, {"ir4", SRIDX (1, 2, 1), 0},
1035 {"p_eva", SRIDX (1, 2, 2), 0}, {"ir5", SRIDX (1, 2, 2), 0},
1036 {"itype", SRIDX (1, 3, 1), 0}, {"ir6", SRIDX (1, 3, 1), 0},
1037 {"p_itype", SRIDX (1, 3, 2), 0}, {"ir7", SRIDX (1, 3, 2), 0},
1038 {"merr", SRIDX (1, 4, 1), 0}, {"ir8", SRIDX (1, 4, 1), 0},
1039 {"ipc", SRIDX (1, 5, 1), 0}, {"ir9", SRIDX (1, 5, 1), 0},
1040 {"p_ipc", SRIDX (1, 5, 2), 0}, {"ir10", SRIDX (1, 5, 2), 0},
1041 {"oipc", SRIDX (1, 5, 3), 0}, {"ir11", SRIDX (1, 5, 3), 0},
1042 {"p_p0", SRIDX (1, 6, 2), 0}, {"ir12", SRIDX (1, 6, 2), 0},
1043 {"p_p1", SRIDX (1, 7, 2), 0}, {"ir13", SRIDX (1, 7, 2), 0},
1044 {"int_mask", SRIDX (1, 8, 0), 0}, {"ir14", SRIDX (1, 8, 0), 0},
1045 {"int_pend", SRIDX (1, 9, 0), 0}, {"ir15", SRIDX (1, 9, 0), 0},
1046 {"sp_usr", SRIDX (1, 10, 0), 0}, {"ir16", SRIDX (1, 10, 0), 0},
1047 {"sp_priv", SRIDX (1, 10, 1), 0}, {"ir17", SRIDX (1, 10, 1), 0},
1048 {"int_pri", SRIDX (1, 11, 0), 0}, {"ir18", SRIDX (1, 11, 0), 0},
1049 {"int_ctrl", SRIDX (1, 1, 2), 0}, {"ir19", SRIDX (1, 1, 2), 0},
1050 {"sp_usr1", SRIDX (1, 10, 2), 0}, {"ir20", SRIDX (1, 10, 2), 0},
1051 {"sp_priv1", SRIDX (1, 10, 3), 0}, {"ir21", SRIDX (1, 10, 3), 0},
1052 {"sp_usr2", SRIDX (1, 10, 4), 0}, {"ir22", SRIDX (1, 10, 4), 0},
1053 {"sp_priv2", SRIDX (1, 10, 5), 0}, {"ir23", SRIDX (1, 10, 5), 0},
1054 {"sp_usr3", SRIDX (1, 10, 6), 0}, {"ir24", SRIDX (1, 10, 6), 0},
1055 {"sp_priv3", SRIDX (1, 10, 7), 0}, {"ir25", SRIDX (1, 10, 7), 0},
1056 {"int_mask2", SRIDX (1, 8, 1), 0}, {"ir26", SRIDX (1, 8, 1), 0},
1057 {"int_pend2", SRIDX (1, 9, 1), 0}, {"ir27", SRIDX (1, 9, 1), 0},
1058 {"int_pri2", SRIDX (1, 11, 1), 0}, {"ir28", SRIDX (1, 11, 1), 0},
1059 {"int_trigger", SRIDX (1, 9, 4), 0}, {"ir29", SRIDX (1, 9, 4), 0},
1060 {"int_gpr_push_dis", SRIDX(1, 1, 3), 0}, {"ir30", SRIDX (1, 1, 3), 0},
1062 {"mmu_ctl", SRIDX (2, 0, 0), 0}, {"mr0", SRIDX (2, 0, 0), 0},
1063 {"l1_pptb", SRIDX (2, 1, 0), 0}, {"mr1", SRIDX (2, 1, 0), 0},
1064 {"tlb_vpn", SRIDX (2, 2, 0), 0}, {"mr2", SRIDX (2, 2, 0), 0},
1065 {"tlb_data", SRIDX (2, 3, 0), 0}, {"mr3", SRIDX (2, 3, 0), 0},
1066 {"tlb_misc", SRIDX (2, 4, 0), 0}, {"mr4", SRIDX (2, 4, 0), 0},
1067 {"vlpt_idx", SRIDX (2, 5, 0), 0}, {"mr5", SRIDX (2, 5, 0), 0},
1068 {"ilmb", SRIDX (2, 6, 0), 0}, {"mr6", SRIDX (2, 6, 0), 0},
1069 {"dlmb", SRIDX (2, 7, 0), 0}, {"mr7", SRIDX (2, 7, 0), 0},
1070 {"cache_ctl", SRIDX (2, 8, 0), 0}, {"mr8", SRIDX (2, 8, 0), 0},
1071 {"hsmp_saddr", SRIDX (2, 9, 0), 0}, {"mr9", SRIDX (2, 9, 0), 0},
1072 {"hsmp_eaddr", SRIDX (2, 9, 1), 0}, {"mr10", SRIDX (2, 9, 1), 0},
1073 {"bg_region", SRIDX (2, 0, 1), 0}, {"mr11", SRIDX (2, 0, 1), 0},
1075 {"pfmc0", SRIDX (4, 0, 0), 0}, {"pfr0", SRIDX (4, 0, 0), 0},
1076 {"pfmc1", SRIDX (4, 0, 1), 0}, {"pfr1", SRIDX (4, 0, 1), 0},
1077 {"pfmc2", SRIDX (4, 0, 2), 0}, {"pfr2", SRIDX (4, 0, 2), 0},
1078 {"pfm_ctl", SRIDX (4, 1, 0), 0}, {"pfr3", SRIDX (4, 1, 0), 0},
1079 {"hsp_ctl", SRIDX (4, 6, 0), 0}, {"hspr0", SRIDX (4, 6, 0), 0},
1080 {"sp_bound", SRIDX (4, 6, 1), 0}, {"hspr1", SRIDX (4, 6, 1), 0},
1081 {"sp_bound_priv", SRIDX (4, 6, 2), 0},{"hspr2", SRIDX (4, 6, 2), 0},
1083 {"dma_cfg", SRIDX (5, 0, 0), 0}, {"dmar0", SRIDX (5, 0, 0), 0},
1084 {"dma_gcsw", SRIDX (5, 1, 0), 0}, {"dmar1", SRIDX (5, 1, 0), 0},
1085 {"dma_chnsel", SRIDX (5, 2, 0), 0}, {"dmar2", SRIDX (5, 2, 0), 0},
1086 {"dma_act", SRIDX (5, 3, 0), 0}, {"dmar3", SRIDX (5, 3, 0), 0},
1087 {"dma_setup", SRIDX (5, 4, 0), 0}, {"dmar4", SRIDX (5, 4, 0), 0},
1088 {"dma_isaddr", SRIDX (5, 5, 0), 0}, {"dmar5", SRIDX (5, 5, 0), 0},
1089 {"dma_esaddr", SRIDX (5, 6, 0), 0}, {"dmar6", SRIDX (5, 6, 0), 0},
1090 {"dma_tcnt", SRIDX (5, 7, 0), 0}, {"dmar7", SRIDX (5, 7, 0), 0},
1091 {"dma_status", SRIDX (5, 8, 0), 0}, {"dmar8", SRIDX (5, 8, 0), 0},
1092 {"dma_2dset", SRIDX (5, 9, 0), 0}, {"dmar9", SRIDX (5, 9, 0), 0},
1093 {"dma_2dsctl", SRIDX (5, 9, 1), 0}, {"dmar10", SRIDX (5, 9, 1), 0},
1094 {"dma_rcnt", SRIDX (5, 7, 1), 0}, {"dmar11", SRIDX (5, 7, 1), 0},
1095 {"dma_hstatus", SRIDX (5, 8, 1), 0}, {"dmar12", SRIDX (5, 8, 1), 0},
1097 {"sdz_ctl", SRIDX (2, 15, 0), 0}, {"idr0", SRIDX (2, 15, 0), 0},
1098 {"misc_ctl", SRIDX (2, 15, 1), 0}, {"n12misc_ctl", SRIDX (2, 15, 1), 0},
1099 {"idr1", SRIDX (2, 15, 1), 0},
1100 {"ecc_misc", SRIDX (2, 15, 2), 0}, {"idr2", SRIDX (2, 15, 2), 0},
1102 {"secur0", SRIDX (6, 0, 0), 0}, {"sfcr", SRIDX (6, 0, 0), 0},
1103 {"secur1", SRIDX (6, 1, 0), 0}, {"sign", SRIDX (6, 1, 0), 0},
1104 {"secur2", SRIDX (6, 1, 1), 0}, {"isign", SRIDX (6, 1, 1), 0},
1105 {"secur3", SRIDX (6, 1, 2), 0}, {"p_isign", SRIDX (6, 1, 2), 0},
1107 {"prusr_acc_ctl", SRIDX (4, 4, 0), 0},
1108 {"fucpr", SRIDX (4, 5, 0), 0}, {"fucop_ctl", SRIDX (4, 5, 0), 0},
1110 {"bpc0", SRIDX (3, 0, 0), 0}, {"dr0", SRIDX (3, 0, 0), 0},
1111 {"bpc1", SRIDX (3, 0, 1), 0}, {"dr1", SRIDX (3, 0, 1), 0},
1112 {"bpc2", SRIDX (3, 0, 2), 0}, {"dr2", SRIDX (3, 0, 2), 0},
1113 {"bpc3", SRIDX (3, 0, 3), 0}, {"dr3", SRIDX (3, 0, 3), 0},
1114 {"bpc4", SRIDX (3, 0, 4), 0}, {"dr4", SRIDX (3, 0, 4), 0},
1115 {"bpc5", SRIDX (3, 0, 5), 0}, {"dr5", SRIDX (3, 0, 5), 0},
1116 {"bpc6", SRIDX (3, 0, 6), 0}, {"dr6", SRIDX (3, 0, 6), 0},
1117 {"bpc7", SRIDX (3, 0, 7), 0}, {"dr7", SRIDX (3, 0, 7), 0},
1118 {"bpa0", SRIDX (3, 1, 0), 0}, {"dr8", SRIDX (3, 1, 0), 0},
1119 {"bpa1", SRIDX (3, 1, 1), 0}, {"dr9", SRIDX (3, 1, 1), 0},
1120 {"bpa2", SRIDX (3, 1, 2), 0}, {"dr10", SRIDX (3, 1, 2), 0},
1121 {"bpa3", SRIDX (3, 1, 3), 0}, {"dr11", SRIDX (3, 1, 3), 0},
1122 {"bpa4", SRIDX (3, 1, 4), 0}, {"dr12", SRIDX (3, 1, 4), 0},
1123 {"bpa5", SRIDX (3, 1, 5), 0}, {"dr13", SRIDX (3, 1, 5), 0},
1124 {"bpa6", SRIDX (3, 1, 6), 0}, {"dr14", SRIDX (3, 1, 6), 0},
1125 {"bpa7", SRIDX (3, 1, 7), 0}, {"dr15", SRIDX (3, 1, 7), 0},
1126 {"bpam0", SRIDX (3, 2, 0), 0}, {"dr16", SRIDX (3, 2, 0), 0},
1127 {"bpam1", SRIDX (3, 2, 1), 0}, {"dr17", SRIDX (3, 2, 1), 0},
1128 {"bpam2", SRIDX (3, 2, 2), 0}, {"dr18", SRIDX (3, 2, 2), 0},
1129 {"bpam3", SRIDX (3, 2, 3), 0}, {"dr19", SRIDX (3, 2, 3), 0},
1130 {"bpam4", SRIDX (3, 2, 4), 0}, {"dr20", SRIDX (3, 2, 4), 0},
1131 {"bpam5", SRIDX (3, 2, 5), 0}, {"dr21", SRIDX (3, 2, 5), 0},
1132 {"bpam6", SRIDX (3, 2, 6), 0}, {"dr22", SRIDX (3, 2, 6), 0},
1133 {"bpam7", SRIDX (3, 2, 7), 0}, {"dr23", SRIDX (3, 2, 7), 0},
1134 {"bpv0", SRIDX (3, 3, 0), 0}, {"dr24", SRIDX (3, 3, 0), 0},
1135 {"bpv1", SRIDX (3, 3, 1), 0}, {"dr25", SRIDX (3, 3, 1), 0},
1136 {"bpv2", SRIDX (3, 3, 2), 0}, {"dr26", SRIDX (3, 3, 2), 0},
1137 {"bpv3", SRIDX (3, 3, 3), 0}, {"dr27", SRIDX (3, 3, 3), 0},
1138 {"bpv4", SRIDX (3, 3, 4), 0}, {"dr28", SRIDX (3, 3, 4), 0},
1139 {"bpv5", SRIDX (3, 3, 5), 0}, {"dr29", SRIDX (3, 3, 5), 0},
1140 {"bpv6", SRIDX (3, 3, 6), 0}, {"dr30", SRIDX (3, 3, 6), 0},
1141 {"bpv7", SRIDX (3, 3, 7), 0}, {"dr31", SRIDX (3, 3, 7), 0},
1142 {"bpcid0", SRIDX (3, 4, 0), 0}, {"dr32", SRIDX (3, 4, 0), 0},
1143 {"bpcid1", SRIDX (3, 4, 1), 0}, {"dr33", SRIDX (3, 4, 1), 0},
1144 {"bpcid2", SRIDX (3, 4, 2), 0}, {"dr34", SRIDX (3, 4, 2), 0},
1145 {"bpcid3", SRIDX (3, 4, 3), 0}, {"dr35", SRIDX (3, 4, 3), 0},
1146 {"bpcid4", SRIDX (3, 4, 4), 0}, {"dr36", SRIDX (3, 4, 4), 0},
1147 {"bpcid5", SRIDX (3, 4, 5), 0}, {"dr37", SRIDX (3, 4, 5), 0},
1148 {"bpcid6", SRIDX (3, 4, 6), 0}, {"dr38", SRIDX (3, 4, 6), 0},
1149 {"bpcid7", SRIDX (3, 4, 7), 0}, {"dr39", SRIDX (3, 4, 7), 0},
1150 {"edm_cfg", SRIDX (3, 5, 0), 0}, {"dr40", SRIDX (3, 5, 0), 0},
1151 {"edmsw", SRIDX (3, 6, 0), 0}, {"dr41", SRIDX (3, 6, 0), 0},
1152 {"edm_ctl", SRIDX (3, 7, 0), 0}, {"dr42", SRIDX (3, 7, 0), 0},
1153 {"edm_dtr", SRIDX (3, 8, 0), 0}, {"dr43", SRIDX (3, 8, 0), 0},
1154 {"bpmtc", SRIDX (3, 9, 0), 0}, {"dr44", SRIDX (3, 9, 0), 0},
1155 {"dimbr", SRIDX (3, 10, 0), 0}, {"dr45", SRIDX (3, 10, 0), 0},
1156 {"tecr0", SRIDX (3, 14, 0), 0}, {"dr46", SRIDX (3, 14, 0), 0},
1157 {"tecr1", SRIDX (3, 14, 1), 0}, {"dr47", SRIDX (3, 14, 1), 0},
1161 const keyword_t keyword_cp[] =
1163 {"cp0", 0, 0}, {"cp1", 1, 0}, {"cp2", 2, 0}, {"cp3", 3, 0}, {NULL, 0, 0}
1166 const keyword_t keyword_cpr[] =
1168 {"cpr0", 0, 0}, {"cpr1", 1, 0}, {"cpr2", 2, 0}, {"cpr3", 3, 0},
1169 {"cpr4", 4, 0}, {"cpr5", 5, 0}, {"cpr6", 6, 0}, {"cpr7", 7, 0},
1170 {"cpr8", 8, 0}, {"cpr9", 9, 0}, {"cpr10", 10, 0}, {"cpr11", 11, 0},
1171 {"cpr12", 12, 0}, {"cpr13", 13, 0}, {"cpr14", 14, 0}, {"cpr15", 15, 0},
1172 {"cpr16", 16, 0}, {"cpr17", 17, 0}, {"cpr18", 18, 0}, {"cpr19", 19, 0},
1173 {"cpr20", 20, 0}, {"cpr21", 21, 0}, {"cpr22", 22, 0}, {"cpr23", 23, 0},
1174 {"cpr24", 24, 0}, {"cpr25", 25, 0}, {"cpr26", 26, 0}, {"cpr27", 27, 0},
1175 {"cpr28", 28, 0}, {"cpr29", 29, 0}, {"cpr30", 30, 0}, {"cpr31", 31, 0},
1179 const keyword_t keyword_fsr[] =
1181 {"fs0", 0, 0}, {"fs1", 1, 0}, {"fs2", 2, 0}, {"fs3", 3, 0}, {"fs4", 4, 0},
1182 {"fs5", 5, 0}, {"fs6", 6, 0}, {"fs7", 7, 0}, {"fs8", 8, 0}, {"fs9", 9, 0},
1183 {"fs10", 10, 0}, {"fs11", 11, 0}, {"fs12", 12, 0}, {"fs13", 13, 0},
1184 {"fs14", 14, 0}, {"fs15", 15, 0}, {"fs16", 16, 0}, {"fs17", 17, 0},
1185 {"fs18", 18, 0}, {"fs19", 19, 0}, {"fs20", 20, 0}, {"fs21", 21, 0},
1186 {"fs22", 22, 0}, {"fs23", 23, 0}, {"fs24", 24, 0}, {"fs25", 25, 0},
1187 {"fs26", 26, 0}, {"fs27", 27, 0}, {"fs28", 28, 0}, {"fs29", 29, 0},
1188 {"fs30", 30, 0}, {"fs31", 31, 0}, {NULL, 0 ,0}
1191 const keyword_t keyword_fdr[] =
1193 {"fd0", 0, 0}, {"fd1", 1, 0}, {"fd2", 2, 0}, {"fd3", 3, 0}, {"fd4", 4, 0},
1194 {"fd5", 5, 0}, {"fd6", 6, 0}, {"fd7", 7, 0}, {"fd8", 8, 0}, {"fd9", 9, 0},
1195 {"fd10", 10, 0}, {"fd11", 11, 0}, {"fd12", 12, 0}, {"fd13", 13, 0},
1196 {"fd14", 14, 0}, {"fd15", 15, 0}, {"fd16", 16, 0}, {"fd17", 17, 0},
1197 {"fd18", 18, 0}, {"fd19", 19, 0}, {"fd20", 20, 0}, {"fd21", 21, 0},
1198 {"fd22", 22, 0}, {"fd23", 23, 0}, {"fd24", 24, 0}, {"fd25", 25, 0},
1199 {"fd26", 26, 0}, {"fd27", 27, 0}, {"fd28", 28, 0}, {"fd29", 29, 0},
1200 {"fd30", 30, 0}, {"fd31", 31, 0}, {NULL, 0, 0}
1203 const keyword_t keyword_abdim[] =
1205 {"bi", 0, 0}, {"bim", 1, 0}, {"bd", 2, 0}, {"bdm", 3, 0},
1206 {"ai", 4, 0}, {"aim", 5, 0}, {"ad", 6, 0}, {"adm", 7, 0},
1210 const keyword_t keyword_abm[] =
1212 {"b", 0, 0}, {"bm", 1, 0}, {"bx", 2, 0}, {"bmx", 3, 0},
1213 {"a", 4, 0}, {"am", 5, 0}, {"ax", 6, 0}, {"amx", 7, 0},
1217 static const keyword_t keyword_dtiton[] =
1219 {"iton", 1, 0}, {"ton", 3, 0}, {NULL, 0, 0}
1222 static const keyword_t keyword_dtitoff[] =
1224 {"itoff", 1, 0}, {"toff", 3, 0}, {NULL, 0, 0}
1227 const keyword_t keyword_dpref_st[] =
1229 {"srd", 0, 0}, {"mrd", 1, 0}, {"swr", 2, 0}, {"mwr", 3, 0},
1230 {"pte", 4, 0}, {"clwr", 5, 0}, {NULL, 0, 0}
1233 /* CCTL Ra, SubType. */
1234 static const keyword_t keyword_cctl_st0[] =
1236 {"l1d_ix_inval", 0X0, 0}, {"l1d_ix_wb", 0X1, 0}, {"l1d_ix_wbinval", 0X2, 0},
1237 {"l1d_va_fillck", 0XB, 0}, {"l1d_va_ulck", 0XC, 0}, {"l1i_ix_inval", 0X10, 0},
1238 {"l1i_va_fillck", 0X1B, 0}, {"l1i_va_ulck", 0X1C, 0},
1242 /* CCTL Ra, SubType, level. */
1243 static const keyword_t keyword_cctl_st1[] =
1245 {"l1d_va_inval", 0X8, 0}, {"l1d_va_wb", 0X9, 0},
1246 {"l1d_va_wbinval", 0XA, 0}, {"l1i_va_inval", 0X18, 0},
1250 /* CCTL Rt, Ra, SubType. */
1251 static const keyword_t keyword_cctl_st2[] =
1253 {"l1d_ix_rtag", 0X3, 0}, {"l1d_ix_rwd", 0X4, 0},
1254 {"l1i_ix_rtag", 0X13, 0}, {"l1i_ix_rwd", 0X14, 0},
1258 /* CCTL Rb, Ra, SubType. */
1259 static const keyword_t keyword_cctl_st3[] =
1261 {"l1d_ix_wtag", 0X5, 0}, {"l1d_ix_wwd", 0X6, 0},
1262 {"l1i_ix_wtag", 0X15, 0}, {"l1i_ix_wwd", 0X16, 0},
1266 /* CCTL L1D_INVALALL. */
1267 static const keyword_t keyword_cctl_st4[] =
1269 {"l1d_invalall", 0x7, 0}, {NULL, 0, 0}
1272 /* CCTL L1D_WBALL, level. */
1273 static const keyword_t keyword_cctl_st5[] =
1275 {"l1d_wball", 0xf, 0}, {NULL, 0, 0}
1278 const keyword_t keyword_cctl_lv[] =
1280 {"1level", 0, 0}, {"alevel", 1, 0}, {"0", 0, 0}, {"1", 1, 0},
1284 static const keyword_t keyword_tlbop_st[] =
1286 {"targetread", 0, 0}, {"trd", 0, 0},
1287 {"targetwrite", 1, 0}, {"twr", 1, 0},
1288 {"rwrite", 2, 0}, {"rwr", 2, 0},
1289 {"rwritelock", 3, 0}, {"rwlk", 3, 0},
1290 {"unlock", 4, 0}, {"unlk", 4, 0},
1291 {"invalidate", 6, 0}, {"inv", 6, 0},
1295 const keyword_t keyword_standby_st[] =
1297 {"no_wake_grant", 0, 0},
1298 {"wake_grant", 1, 0},
1299 {"wait_done", 2, 0},
1307 const keyword_t keyword_msync_st[] =
1309 {"all", 0, 0}, {"store", 1, 0},
1313 const keyword_t keyword_im5_i[] =
1315 {"i0", 0, 0}, {"i1", 1, 0}, {"i2", 2, 0}, {"i3", 3, 0},
1316 {"i4", 4, 0}, {"i5", 5, 0}, {"i6", 6, 0}, {"i7", 7, 0},
1320 const keyword_t keyword_im5_m[] =
1322 {"m0", 0, 0}, {"m1", 1, 0}, {"m2", 2, 0}, {"m3", 3, 0},
1323 {"m4", 4, 0}, {"m5", 5, 0}, {"m6", 6, 0}, {"m7", 7, 0},
1327 const keyword_t keyword_accumulator[] =
1329 {"d0.lo", 0, 0}, {"d0.hi", 1, 0}, {"d1.lo", 2, 0}, {"d1.hi", 3, 0},
1333 const keyword_t keyword_aridx[] =
1335 {"i0", 0, 0}, {"i1", 1, 0}, {"i2", 2, 0}, {"i3", 3, 0},
1336 {"i4", 4, 0}, {"i5", 5, 0}, {"i6", 6, 0}, {"i7", 7, 0},
1337 {"mod", 8, 0}, {"m1", 9, 0}, {"m2", 10, 0}, {"m3",11, 0},
1338 {"m5",13, 0}, {"m6",14, 0}, {"m7",15, 0},
1339 {"d0.l24", 16, 0}, {"d1.l24", 17, 0},
1340 {"shft_ctl0", 18, 0}, {"shft_ctl1", 19, 0},
1341 {"lb", 24, 0}, {"le", 25, 0}, {"lc", 26, 0}, {"adm_vbase", 27, 0},
1345 const keyword_t keyword_aridx2[] =
1347 {"cbb0", 0, 0}, {"cbb1", 1, 0}, {"cbb2", 2, 0}, {"cbb3", 3, 0},
1348 {"cbe0", 4, 0}, {"cbe1", 5, 0}, {"cbe2", 6, 0}, {"cbe3", 7, 0},
1353 const keyword_t keyword_aridxi[] =
1355 {"i0", 0, 0}, {"i1", 1, 0}, {"i2", 2, 0}, {"i3", 3, 0},
1356 {"i4", 4, 0}, {"i5", 5, 0}, {"i6", 6, 0}, {"i7", 7, 0},
1357 {"mod", 8, 0}, {"m1", 9, 0}, {"m2", 10, 0}, {"m3",11, 0},
1358 {"m5",13, 0}, {"m6",14, 0}, {"m7",15, 0},
1362 const keyword_t *keywords[_HW_LAST] =
1364 keyword_gpr, keyword_usr, keyword_dxr, keyword_sr, keyword_fsr,
1365 keyword_fdr, keyword_cp, keyword_cpr, keyword_abdim, keyword_abm,
1366 keyword_dtiton, keyword_dtitoff, keyword_dpref_st,
1367 keyword_cctl_st0, keyword_cctl_st1, keyword_cctl_st2,
1368 keyword_cctl_st3, keyword_cctl_st4, keyword_cctl_st5,
1369 keyword_cctl_lv, keyword_tlbop_st, keyword_standby_st,
1371 keyword_im5_i, keyword_im5_m,
1372 keyword_accumulator, keyword_aridx, keyword_aridx2, keyword_aridxi
1375 /* Hash table for syntax lex. */
1376 static htab_t field_htab;
1377 /* Hash table for opcodes. */
1378 static htab_t opcode_htab;
1379 /* Hash table for hardware resources. */
1380 static htab_t hw_ktabs[_HW_LAST];
1383 htab_hash_hash (const void *p)
1385 struct nds32_hash_entry *h = (struct nds32_hash_entry *) p;
1387 return htab_hash_string (h->name);
1391 htab_hash_eq (const void *p, const void *q)
1393 struct nds32_hash_entry *h = (struct nds32_hash_entry *) p;
1394 const char *name = (const char *) q;
1396 return strcmp (name, h->name) == 0;
1399 /* Build a hash table for array BASE. Each element is in size of SIZE,
1400 and it's first element is a pointer to the key of string.
1401 It stops inserting elements until reach an NULL key. */
1404 build_hash_table (const void *base, size_t size)
1410 htab = htab_create_alloc (128, htab_hash_hash, htab_hash_eq,
1411 NULL, xcalloc, free);
1416 struct nds32_hash_entry **slot;
1417 struct nds32_hash_entry *h;
1419 h = (struct nds32_hash_entry *) p;
1421 if (h->name == NULL)
1424 hash = htab_hash_string (h->name);
1425 slot = (struct nds32_hash_entry **)
1426 htab_find_slot_with_hash (htab, h->name, hash, INSERT);
1428 assert (slot != NULL && *slot == NULL);
1438 /* Build the syntax for a given opcode OPC. It parses the string
1439 pointed by INSTRUCTION and store the result on SYNTAX, so
1440 when we assemble an instruction, we don't have to parse the syntax
1444 build_opcode_syntax (struct nds32_opcode *opc)
1446 char odstr[MAX_LEX_LEN];
1455 /* Check whether it has been initialized. */
1459 opc->syntax = xmalloc (MAX_LEX_NUM * sizeof (lex_t));
1461 str = opc->instruction;
1476 *plex = SYN_INPUT | SYN_OUTPUT;
1493 /* Extract operand. */
1495 while (ISALNUM (*end) || *end == '_')
1498 memcpy (odstr, str, len);
1501 hash = htab_hash_string (odstr);
1502 fd = (field_t *) htab_find_with_hash (field_htab, odstr, hash);
1503 fidx = fd - operand_fields;
1507 /* xgettext: c-format */
1508 opcodes_error_handler (_("internal error: unknown operand, %s"), str);
1511 assert (fidx >= 0 && fidx < (int) ARRAY_SIZE (operand_fields));
1512 *plex |= LEX_SET_FIELD (fidx);
1523 /* Initialize the assembler. It must be called before assembling. */
1526 nds32_asm_init (nds32_asm_desc_t *pdesc, int flags)
1531 pdesc->flags = flags;
1532 pdesc->mach = flags & NASM_OPEN_ARCH_MASK;
1534 /* Build keyword tables. */
1535 field_htab = build_hash_table (operand_fields,
1536 sizeof (operand_fields[0]));
1538 for (i = 0; i < _HW_LAST; i++)
1539 hw_ktabs[i] = build_hash_table (keywords[i], sizeof (keyword_t));
1541 /* Build opcode table. */
1542 opcode_htab = htab_create_alloc (128, htab_hash_hash, htab_hash_eq,
1543 NULL, xcalloc, free);
1545 for (i = 0; i < (int) ARRAY_SIZE (nds32_opcodes); i++)
1547 struct nds32_opcode **slot;
1548 struct nds32_opcode *opc;
1550 opc = &nds32_opcodes[i];
1551 if ((opc->opcode != NULL) && (opc->instruction != NULL))
1553 hash = htab_hash_string (opc->opcode);
1554 slot = (struct nds32_opcode **)
1555 htab_find_slot_with_hash (opcode_htab, opc->opcode, hash, INSERT);
1557 #define NDS32_PREINIT_SYNTAX
1558 #if defined (NDS32_PREINIT_SYNTAX)
1559 /* Initial SYNTAX when build opcode table, so bug in syntax can be
1560 found when initialized rather than used. */
1561 build_opcode_syntax (opc);
1566 /* This is the new one. */
1571 /* Already exists. Append to the list. */
1575 opc->next = &nds32_opcodes[i];
1581 /* Parse the input and store operand keyword string in ODSTR.
1582 This function is only used for parsing keywords,
1583 HW_INT/HW_UINT are parsed parse_operand callback handler. */
1586 parse_to_delimiter (char *str, char odstr[MAX_KEYWORD_LEN])
1590 while (ISALNUM (*str) || *str == '.' || *str == '_')
1591 *outp++ = TOLOWER (*str++);
1597 /* Parse the operand of lmw/smw/lmwa/smwa. */
1600 parse_re (struct nds32_asm_desc *pdesc ATTRIBUTE_UNUSED,
1601 struct nds32_asm_insn *pinsn, char **pstr, int64_t *value)
1604 char odstr[MAX_KEYWORD_LEN];
1610 end = parse_to_delimiter (end, odstr);
1612 hash = htab_hash_string (odstr);
1613 k = htab_find_with_hash (hw_ktabs[HW_GPR], odstr, hash);
1616 return NASM_ERR_OPERAND;
1618 if (__GF (pinsn->insn, 20, 5) > (unsigned int) k->value)
1619 return NASM_ERR_OPERAND;
1623 return NASM_R_CONST;
1626 /* Parse the operand of push25/pop25. */
1629 parse_re2 (struct nds32_asm_desc *pdesc ATTRIBUTE_UNUSED,
1630 struct nds32_asm_insn *pinsn ATTRIBUTE_UNUSED,
1631 char **pstr, int64_t *value)
1634 char odstr[MAX_KEYWORD_LEN];
1640 end = parse_to_delimiter (end, odstr);
1642 hash = htab_hash_string (odstr);
1643 k = htab_find_with_hash (hw_ktabs[HW_GPR], odstr, hash);
1646 return NASM_ERR_OPERAND;
1650 else if (k->value == 8)
1652 else if (k->value == 10)
1654 else if (k->value == 14)
1657 return NASM_ERR_OPERAND;
1660 return NASM_R_CONST;
1663 /* Parse the operand of lwi45.fe. */
1666 parse_fe5 (struct nds32_asm_desc *pdesc, struct nds32_asm_insn *pinsn,
1667 char **pstr, int64_t *value)
1671 r = pdesc->parse_operand (pdesc, pinsn, pstr, value);
1672 if (r != NASM_R_CONST)
1673 return NASM_ERR_OPERAND;
1675 /* 128 == 32 << 2. Leave the shift to parse_opreand,
1676 so it can check whether it is a multiple of 4. */
1677 *value = 128 + *value;
1681 /* Parse the operand of movpi45. */
1684 parse_pi5 (struct nds32_asm_desc *pdesc, struct nds32_asm_insn *pinsn,
1685 char **pstr, int64_t *value)
1689 r = pdesc->parse_operand (pdesc, pinsn, pstr, value);
1690 if (r != NASM_R_CONST)
1691 return NASM_ERR_OPERAND;
1697 static int aext_a30b20 = 0;
1698 static int aext_rte = 0;
1699 static int aext_im5_ip = 0;
1700 static int aext_im6_ip = 0;
1701 /* Parse the operand of audio ext. */
1703 parse_aext_reg (char **pstr, int *value, int hw_res)
1706 char odstr[MAX_KEYWORD_LEN];
1712 end = parse_to_delimiter (end, odstr);
1714 hash = htab_hash_string (odstr);
1715 k = htab_find_with_hash (hw_ktabs[hw_res], odstr, hash);
1718 return NASM_ERR_OPERAND;
1722 return NASM_R_CONST;
1726 parse_a30b20 (struct nds32_asm_desc *pdesc ATTRIBUTE_UNUSED,
1727 struct nds32_asm_insn *pinsn ATTRIBUTE_UNUSED,
1728 char **pstr, int64_t *value)
1732 ret = parse_aext_reg (pstr, &rt_value, HW_GPR);
1734 if ((ret == NASM_ERR_OPERAND) || (rt_value > 15))
1735 return NASM_ERR_OPERAND;
1738 aext_a30b20 = rt_value;
1739 return NASM_R_CONST;
1743 parse_rt21 (struct nds32_asm_desc *pdesc ATTRIBUTE_UNUSED,
1744 struct nds32_asm_insn *pinsn ATTRIBUTE_UNUSED,
1745 char **pstr, int64_t *value)
1747 int rt_value, ret, tmp_value, tmp1, tmp2;
1749 ret = parse_aext_reg (pstr, &rt_value, HW_GPR);
1751 if ((ret == NASM_ERR_OPERAND) || (rt_value > 15))
1752 return NASM_ERR_OPERAND;
1753 tmp1 = (aext_a30b20 & 0x08);
1754 tmp2 = (rt_value & 0x08);
1756 return NASM_ERR_OPERAND;
1758 /* Rt=CONCAT(c, t21, t0), t21:bit11-10, t0:bit5. */
1759 tmp_value = (rt_value & 0x06) << 4;
1760 tmp_value |= (rt_value & 0x01);
1762 return NASM_R_CONST;
1766 parse_rte_start (struct nds32_asm_desc *pdesc ATTRIBUTE_UNUSED,
1767 struct nds32_asm_insn *pinsn ATTRIBUTE_UNUSED,
1768 char **pstr, int64_t *value)
1770 int rt_value, ret, tmp1, tmp2;
1772 ret = parse_aext_reg (pstr, &rt_value, HW_GPR);
1774 if ((ret == NASM_ERR_OPERAND) || (rt_value > 15)
1775 || (rt_value & 0x01))
1776 return NASM_ERR_OPERAND;
1777 tmp1 = (aext_a30b20 & 0x08);
1778 tmp2 = (rt_value & 0x08);
1780 return NASM_ERR_OPERAND;
1782 aext_rte = rt_value;
1783 /* Rt=CONCAT(c, t21, 0), t21:bit11-10. */
1784 rt_value = (rt_value & 0x06) << 4;
1786 return NASM_R_CONST;
1790 parse_rte_end (struct nds32_asm_desc *pdesc ATTRIBUTE_UNUSED,
1791 struct nds32_asm_insn *pinsn ATTRIBUTE_UNUSED,
1792 char **pstr, int64_t *value)
1794 int rt_value, ret, tmp1, tmp2;
1796 ret = parse_aext_reg (pstr, &rt_value, HW_GPR);
1797 if ((ret == NASM_ERR_OPERAND) || (rt_value > 15)
1798 || ((rt_value & 0x01) == 0)
1799 || (rt_value != (aext_rte + 1)))
1800 return NASM_ERR_OPERAND;
1801 tmp1 = (aext_a30b20 & 0x08);
1802 tmp2 = (rt_value & 0x08);
1804 return NASM_ERR_OPERAND;
1805 /* Rt=CONCAT(c, t21, 0), t21:bit11-10. */
1806 rt_value = (rt_value & 0x06) << 4;
1808 return NASM_R_CONST;
1812 parse_rte69_start (struct nds32_asm_desc *pdesc ATTRIBUTE_UNUSED,
1813 struct nds32_asm_insn *pinsn ATTRIBUTE_UNUSED,
1814 char **pstr, int64_t *value)
1818 ret = parse_aext_reg (pstr, &rt_value, HW_GPR);
1819 if ((ret == NASM_ERR_OPERAND)
1820 || (rt_value & 0x01))
1821 return NASM_ERR_OPERAND;
1822 aext_rte = rt_value;
1823 rt_value = (rt_value >> 1);
1825 return NASM_R_CONST;
1829 parse_rte69_end (struct nds32_asm_desc *pdesc ATTRIBUTE_UNUSED,
1830 struct nds32_asm_insn *pinsn ATTRIBUTE_UNUSED,
1831 char **pstr, int64_t *value)
1835 ret = parse_aext_reg (pstr, &rt_value, HW_GPR);
1836 if ((ret == NASM_ERR_OPERAND)
1837 || ((rt_value & 0x01) == 0)
1838 || (rt_value != (aext_rte + 1)))
1839 return NASM_ERR_OPERAND;
1840 aext_rte = rt_value;
1841 rt_value = (rt_value >> 1);
1843 return NASM_R_CONST;
1847 parse_im5_ip (struct nds32_asm_desc *pdesc ATTRIBUTE_UNUSED,
1848 struct nds32_asm_insn *pinsn ATTRIBUTE_UNUSED,
1849 char **pstr, int64_t *value)
1851 int rt_value, ret, new_value;
1853 ret = parse_aext_reg (pstr, &rt_value, HW_AEXT_IM_I);
1854 if (ret == NASM_ERR_OPERAND)
1855 return NASM_ERR_OPERAND;
1856 /* p = bit[4].bit[1:0], r = bit[4].bit[3:2]. */
1857 new_value = (rt_value & 0x04) << 2;
1858 new_value |= (rt_value & 0x03);
1860 aext_im5_ip = new_value;
1861 return NASM_R_CONST;
1865 parse_im5_mr (struct nds32_asm_desc *pdesc ATTRIBUTE_UNUSED,
1866 struct nds32_asm_insn *pinsn ATTRIBUTE_UNUSED,
1867 char **pstr, int64_t *value)
1869 int rt_value, ret, new_value, tmp1, tmp2;
1871 ret = parse_aext_reg (pstr, &rt_value, HW_AEXT_IM_M);
1872 if (ret == NASM_ERR_OPERAND)
1873 return NASM_ERR_OPERAND;
1874 /* p = bit[4].bit[1:0], r = bit[4].bit[3:2]. */
1875 new_value = (rt_value & 0x07) << 2;
1876 tmp1 = (aext_im5_ip & 0x10);
1877 tmp2 = (new_value & 0x10);
1879 return NASM_ERR_OPERAND;
1881 return NASM_R_CONST;
1885 parse_im6_ip (struct nds32_asm_desc *pdesc ATTRIBUTE_UNUSED,
1886 struct nds32_asm_insn *pinsn ATTRIBUTE_UNUSED,
1887 char **pstr, int64_t *value)
1891 ret = parse_aext_reg (pstr, &rt_value, HW_AEXT_IM_I);
1892 if ((ret == NASM_ERR_OPERAND) || (rt_value > 3))
1893 return NASM_ERR_OPERAND;
1894 /* p = 0.bit[1:0]. */
1895 aext_im6_ip = rt_value;
1896 *value = aext_im6_ip;
1897 return NASM_R_CONST;
1901 parse_im6_iq (struct nds32_asm_desc *pdesc ATTRIBUTE_UNUSED,
1902 struct nds32_asm_insn *pinsn ATTRIBUTE_UNUSED,
1903 char **pstr, int64_t *value)
1907 ret = parse_aext_reg (pstr, &rt_value, HW_AEXT_IM_I);
1908 if ((ret == NASM_ERR_OPERAND) || (rt_value < 4))
1909 return NASM_ERR_OPERAND;
1910 /* q = 1.bit[1:0]. */
1911 if ((rt_value & 0x03) != aext_im6_ip)
1912 return NASM_ERR_OPERAND;
1913 *value = aext_im6_ip;
1914 return NASM_R_CONST;
1918 parse_im6_mr (struct nds32_asm_desc *pdesc ATTRIBUTE_UNUSED,
1919 struct nds32_asm_insn *pinsn ATTRIBUTE_UNUSED,
1920 char **pstr, int64_t *value)
1924 ret = parse_aext_reg (pstr, &rt_value, HW_AEXT_IM_M);
1925 if ((ret == NASM_ERR_OPERAND) || (rt_value > 3))
1926 return NASM_ERR_OPERAND;
1927 /* r = 0.bit[3:2]. */
1928 *value = (rt_value & 0x03);
1929 return NASM_R_CONST;
1933 parse_im6_ms (struct nds32_asm_desc *pdesc ATTRIBUTE_UNUSED,
1934 struct nds32_asm_insn *pinsn ATTRIBUTE_UNUSED,
1935 char **pstr, int64_t *value)
1939 ret = parse_aext_reg (pstr, &rt_value, HW_AEXT_IM_M);
1940 if ((ret == NASM_ERR_OPERAND) || (rt_value < 4))
1941 return NASM_ERR_OPERAND;
1942 /* s = 1.bit[5:4]. */
1943 *value = (rt_value & 0x03);
1944 return NASM_R_CONST;
1947 /* Generic operand parse base on the information provided by the field. */
1950 parse_operand (nds32_asm_desc_t *pdesc, nds32_asm_insn_t *pinsn,
1951 char **str, int syn)
1953 char odstr[MAX_KEYWORD_LEN];
1956 const field_t *fld = &LEX_GET_FIELD (syn);
1960 uint64_t modifier = 0;
1966 r = fld->parse (pdesc, pinsn, &end, &value);
1967 if (r == NASM_ERR_OPERAND)
1969 pdesc->result = NASM_ERR_OPERAND;
1975 if (fld->hw_res < _HW_LAST)
1977 /* Parse the operand in assembly code. */
1980 end = parse_to_delimiter (end, odstr);
1982 hash = htab_hash_string (odstr);
1983 k = htab_find_with_hash (hw_ktabs[fld->hw_res], odstr, hash);
1987 pdesc->result = NASM_ERR_OPERAND;
1991 if (fld->hw_res == HW_GPR && (pdesc->flags & NASM_OPEN_REDUCED_REG)
1992 && (k->attr & ATTR (RDREG)) == 0)
1994 /* Register not allowed in reduced register. */
1995 pdesc->result = NASM_ERR_REG_REDUCED;
1999 if (fld->hw_res == HW_GPR)
2001 if (syn & SYN_INPUT)
2002 pinsn->defuse |= USE_REG (k->value);
2003 if (syn & SYN_OUTPUT)
2004 pinsn->defuse |= DEF_REG (k->value);
2008 if (fld->hw_res == HW_GPR && (fld->bitsize + fld->shift) == 4)
2009 value = nds32_r54map[value];
2011 else if (fld->hw_res == HW_INT || fld->hw_res == HW_UINT)
2016 /* Handle modifiers. Do we need to make a table for modifiers?
2017 Do we need to check unknown modifier? */
2018 if (strncasecmp (end, "hi20(", 5) == 0)
2020 modifier |= NASM_ATTR_HI20;
2023 else if (strncasecmp (end, "lo12(", 5) == 0)
2025 modifier |= NASM_ATTR_LO12;
2028 else if (strncasecmp (end, "lo20(", 5) == 0)
2031 modifier |= NASM_ATTR_LO20;
2035 r = pdesc->parse_operand (pdesc, pinsn, &end, &value);
2038 /* Consume the ')' of modifier. */
2040 pinsn->attr |= modifier;
2045 case NASM_R_ILLEGAL:
2046 pdesc->result = NASM_ERR_OPERAND;
2049 /* This field needs special fix-up. */
2053 if (modifier & NASM_ATTR_HI20)
2054 value = (value >> 12) & 0xfffff;
2055 else if (modifier & NASM_ATTR_LO12)
2056 value = value & 0xfff;
2057 else if (modifier & NASM_ATTR_LO20)
2058 value = value & 0xfffff;
2061 /* xgettext: c-format */
2062 opcodes_error_handler (_("internal error: don't know how to handle "
2063 "parsing results"));
2069 /* xgettext: c-format */
2070 opcodes_error_handler (_("internal error: unknown hardware resource"));
2075 /* Don't silently discarding bits. */
2076 if (value & __MASK (fld->shift))
2078 pdesc->result = NASM_ERR_OUT_OF_RANGE;
2082 /* Check the range of signed or unsigned result. */
2083 if (fld->hw_res != HW_INT && ((int32_t) value >> (fld->bitsize + fld->shift)))
2085 pdesc->result = NASM_ERR_OUT_OF_RANGE;
2088 else if (fld->hw_res == HW_INT)
2090 /* Sign-ext the value. */
2091 if (((value >> 32) == 0) && (value & 0x80000000))
2092 value |= (int64_t) -1U << 31;
2095 /* Shift the value to positive domain. */
2096 if ((value + (1 << (fld->bitsize + fld->shift - 1)))
2097 >> (fld->bitsize + fld->shift))
2099 pdesc->result = NASM_ERR_OUT_OF_RANGE;
2105 (((value >> fld->shift) & __MASK (fld->bitsize)) << fld->bitpos);
2110 /* Try to parse an instruction string based on opcode syntax. */
2113 parse_insn (nds32_asm_desc_t *pdesc, nds32_asm_insn_t *pinsn,
2114 char *str, struct nds32_opcode *opc)
2119 /* A syntax may has optional operands, so we have to try each possible
2120 combination to see if the input is accepted. In order to do so,
2121 bit-N represent whether optional-operand-N is used in this combination.
2122 That is, if bit-N is set, optional-operand-N is not used.
2124 For example, there are 2 optional operands in this syntax,
2128 we can try it 4 times (i.e., 1 << 2)
2136 /* The outer do-while loop is used to try each possible optional
2137 operand combination, and VARIANT is the bit mask. The inner loop
2138 iterates each lexeme in the syntax. */
2142 /* OPT is the number of optional operands we've seen. */
2146 /* PLEX is the syntax iterator and P is the iterator for input
2150 /* Initial the base value. */
2151 pinsn->insn = opc->value;
2155 if (IS_LEX_CHAR (*plex))
2157 /* If it's a plain char, just compare it. */
2158 if (LEX_CHAR (*plex) != TOLOWER (*p))
2160 if (LEX_CHAR (*plex) == '+' && TOLOWER (*p) == '-')
2162 /* We don't define minus format for some signed
2163 immediate case, so ignoring '+' here to parse
2164 negative value eazily. Besides, the minus format
2165 can not support for instruction with relocation.
2166 Ex: lwi $r0, [$r0 + imm] */
2170 pdesc->result = NASM_ERR_SYNTAX;
2175 else if (*plex & SYN_LOPT)
2177 /* If it's '{' and it's not used in this iteration,
2178 just skip the whole optional operand. */
2179 if ((1 << (opt++)) & variant)
2181 while ((*plex & SYN_ROPT) == 0)
2185 else if (*plex & SYN_ROPT)
2191 /* If it's a operand, parse the input operand from input. */
2192 if (!parse_operand (pdesc, pinsn, &p, *plex))
2198 /* Check whether this syntax is accepted. */
2199 if (*plex == 0 && (*p == '\0' || *p == '!' || *p == '#'))
2203 /* If not accepted, try another combination. */
2206 while (variant < (1 << opc->variant));
2212 nds32_assemble (nds32_asm_desc_t *pdesc, nds32_asm_insn_t *pinsn,
2215 struct nds32_opcode *opc;
2221 /* Duplicate the string, so we can modify it for convenience. */
2226 /* Find opcode mnemoic. */
2227 while (*s != ' ' && *s != '\t' && *s != '\0')
2231 dot = strchr (mnemoic, '.');
2234 /* Lookup the opcode syntax. */
2235 hash = htab_hash_string (mnemoic);
2236 opc = (struct nds32_opcode *)
2237 htab_find_with_hash (opcode_htab, mnemoic, hash);
2239 /* If we cannot find a match syntax, try it again without `.'.
2240 For example, try "lmw.adm" first and then try "lmw" again. */
2241 if (opc == NULL && dot != NULL)
2249 else if (opc == NULL)
2251 pdesc->result = NASM_ERR_UNKNOWN_OP;
2255 /* There may be multiple syntaxes for a given opcode.
2256 Try each one until a match is found. */
2257 for (; opc; opc = opc->next)
2259 /* Build opcode syntax, if it's not been initialized yet. */
2260 if (opc->syntax == NULL)
2261 build_opcode_syntax (opc);
2263 /* Reset status before assemble. */
2264 pinsn->defuse = opc->defuse;
2266 pinsn->field = NULL;
2267 /* Use opcode attributes to initial instruction attributes. */
2268 pinsn->attr = opc->attr;
2269 if (parse_insn (pdesc, pinsn, s, opc))
2273 pinsn->opcode = opc;
2276 if (pdesc->result == NASM_OK)
2277 pdesc->result = NASM_ERR_SYNTAX;
2281 /* A matched opcode is found. Write the result to instruction buffer. */
2282 pdesc->result = NASM_OK;
projects / external / binutils.git / blob