opcodes/mips-opc.c

   1 /* mips.h.  Mips opcode list for GDB, the GNU debugger.
   2    Copyright 1993, 1994, 1995, 1996, 1997 Free Software Foundation, Inc.
   3    Contributed by Ralph Campbell and OSF
   4    Commented and modified by Ian Lance Taylor, Cygnus Support
   5
   6 This file is part of GDB, GAS, and the GNU binutils.
   7
   8 GDB, GAS, and the GNU binutils are free software; you can redistribute
   9 them and/or modify them under the terms of the GNU General Public
  10 License as published by the Free Software Foundation; either version
  11 1, or (at your option) any later version.
  12
  13 GDB, GAS, and the GNU binutils are distributed in the hope that they
  14 will be useful, but WITHOUT ANY WARRANTY; without even the implied
  15 warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See
  16 the GNU General Public License for more details.
  17
  18 You should have received a copy of the GNU General Public License
  19 along with this file; see the file COPYING.  If not, write to the Free
  20 Software Foundation, 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.  */
  21
  22 #include <stdio.h>
  23 #include "ansidecl.h"
  24 #include "opcode/mips.h"
  25
  26 /* Short hand so the lines aren't too long.  */
  27
  28 #define LDD     INSN_LOAD_MEMORY_DELAY
  29 #define LCD     INSN_LOAD_COPROC_DELAY
  30 #define UBD     INSN_UNCOND_BRANCH_DELAY
  31 #define CBD     INSN_COND_BRANCH_DELAY
  32 #define COD     INSN_COPROC_MOVE_DELAY
  33 #define CLD     INSN_COPROC_MEMORY_DELAY
  34 #define CBL     INSN_COND_BRANCH_LIKELY
  35 #define TRAP    INSN_TRAP
  36 #define SM      INSN_STORE_MEMORY
  37
  38 #define WR_d    INSN_WRITE_GPR_D
  39 #define WR_t    INSN_WRITE_GPR_T
  40 #define WR_31   INSN_WRITE_GPR_31
  41 #define WR_D    INSN_WRITE_FPR_D
  42 #define WR_T    INSN_WRITE_FPR_T
  43 #define WR_S    INSN_WRITE_FPR_S
  44 #define RD_s    INSN_READ_GPR_S
  45 #define RD_b    INSN_READ_GPR_S
  46 #define RD_t    INSN_READ_GPR_T
  47 #define RD_S    INSN_READ_FPR_S
  48 #define RD_T    INSN_READ_FPR_T
  49 #define RD_R    INSN_READ_FPR_R
  50 #define WR_CC   INSN_WRITE_COND_CODE
  51 #define RD_CC   INSN_READ_COND_CODE
  52 #define RD_C0   INSN_COP
  53 #define RD_C1   INSN_COP
  54 #define RD_C2   INSN_COP
  55 #define RD_C3   INSN_COP
  56 #define WR_C0   INSN_COP
  57 #define WR_C1   INSN_COP
  58 #define WR_C2   INSN_COP
  59 #define WR_C3   INSN_COP
  60 #define WR_HI   INSN_WRITE_HI
  61 #define WR_LO   INSN_WRITE_LO
  62 #define RD_HI   INSN_READ_HI
  63 #define RD_LO   INSN_READ_LO
  64
  65 #define I2      INSN_ISA2
  66 #define I3      INSN_ISA3
  67 #define P3      INSN_4650
  68 #define I4      INSN_ISA4
  69 #define L1      INSN_4010
  70 #define V1      INSN_4100
  71 #define T3      INSN_3900
  72 #define A3      INSN_3900  /* see note below about A5 */
  73
  74 /* start-sanitize-r5900 */
  75 /*
  76    A5,X5 - the 5900 is mostly a mips3 machine with a few mips4
  77    instructions.  I've kluged this by duplicating the particular
  78    mips4 instructions and marking them INSN_5900.  This solution
  79    to the mostly mipsX but some mipsX+1 problem does not scale
  80    well, and has the drawback of duplicating some of the data
  81    in this table.  Also, this solution will loose if you specify
  82    a mips4 + 5900 machine, because it will include the same
  83    insn twice.  But it works for now.
  84
  85    T5 - r5900 extension instructions (not mips anything)
  86    A5 is used to mark mips4 insns that are on the 5900.
  87    X5 is used to mark mips4 insns (mostly double math insns)
  88       that are NOT on the 5900, but are needed until I can
  89       fix the compiler and librarys not to use or generate them.
  90    */
  91
  92 #define T5      INSN_5900
  93 #define A5      INSN_5900
  94 #define X5      INSN_5900
  95 /* end-sanitize-r5900 */
  96
  97
  98
  99 /* The order of overloaded instructions matters.  Label arguments and
 100    register arguments look the same. Instructions that can have either
 101    for arguments must apear in the correct order in this table for the
 102    assembler to pick the right one. In other words, entries with
 103    immediate operands must apear after the same instruction with
 104    registers.
 105
 106    Many instructions are short hand for other instructions (i.e., The
 107    jal <register> instruction is short for jalr <register>).  */
 108
 109 const struct mips_opcode mips_builtin_opcodes[] = {
 110 /* These instructions appear first so that the disassembler will find
 111    them first.  The assemblers uses a hash table based on the
 112    instruction name anyhow.  */
 113 /* name,        args,   mask,           match,  pinfo */
 114 {"nop",     "",         0x00000000, 0xffffffff, 0                       },
 115 {"li",      "t,j",      0x24000000, 0xffe00000, WR_t                    }, /* addiu */
 116 {"li",      "t,i",      0x34000000, 0xffe00000, WR_t                    }, /* ori */
 117 {"li",      "t,I",      0,    (int) M_LI,       INSN_MACRO              },
 118 {"move",    "d,s",      0x0000002d, 0xfc1f07ff, WR_d|RD_s,      I3      },/* daddu */
 119 {"move",    "d,s",      0x00000021, 0xfc1f07ff, WR_d|RD_s               },/* addu */
 120 {"move",    "d,s",      0x00000025, 0xfc1f07ff, WR_d|RD_s               },/* or */
 121 {"b",       "p",        0x10000000, 0xffff0000, UBD                     },/* beq 0,0 */
 122 {"b",       "p",        0x04010000, 0xffff0000, UBD                     },/* bgez 0 */
 123 {"bal",     "p",        0x04110000, 0xffff0000, UBD|WR_31               },/* bgezal 0*/
 124
 125 {"abs",     "d,v",      0,    (int) M_ABS,      INSN_MACRO              },
 126 {"abs.s",   "D,V",      0x46000005, 0xffff003f, WR_D|RD_S               },
 127 {"abs.d",   "D,V",      0x46200005, 0xffff003f, WR_D|RD_S               },
 128 {"add",     "d,v,t",    0x00000020, 0xfc0007ff, WR_d|RD_s|RD_t          },
 129 {"add",     "t,r,I",    0,    (int) M_ADD_I,    INSN_MACRO              },
 130 {"add.s",   "D,V,T",    0x46000000, 0xffe0003f, WR_D|RD_S|RD_T          },
 131 {"add.d",   "D,V,T",    0x46200000, 0xffe0003f, WR_D|RD_S|RD_T          },
 132 {"addi",    "t,r,j",    0x20000000, 0xfc000000, WR_t|RD_s               },
 133 {"addiu",   "t,r,j",    0x24000000, 0xfc000000, WR_t|RD_s               },
 134 {"addu",    "d,v,t",    0x00000021, 0xfc0007ff, WR_d|RD_s|RD_t          },
 135 {"addu",    "t,r,I",    0,    (int) M_ADDU_I,   INSN_MACRO              },
 136 {"and",     "d,v,t",    0x00000024, 0xfc0007ff, WR_d|RD_s|RD_t          },
 137 {"and",     "t,r,I",    0,    (int) M_AND_I,    INSN_MACRO              },
 138 {"andi",    "t,r,i",    0x30000000, 0xfc000000, WR_t|RD_s               },
 139 /* b is at the top of the table.  */
 140 /* bal is at the top of the table.  */
 141 {"bc0f",    "p",        0x41000000, 0xffff0000, CBD|RD_CC               },
 142 {"bc0fl",   "p",        0x41020000, 0xffff0000, CBL|RD_CC,      A3      },
 143 {"bc0fl",   "p",        0x41020000, 0xffff0000, CBL|RD_CC,      I2      },
 144 {"bc1f",    "p",        0x45000000, 0xffff0000, CBD|RD_CC               },
 145 {"bc1f",    "N,p",      0x45000000, 0xffe30000, CBD|RD_CC,      I4      },
 146 {"bc1fl",   "p",        0x45020000, 0xffff0000, CBL|RD_CC,      A3      },
 147 {"bc1fl",   "p",        0x45020000, 0xffff0000, CBL|RD_CC,      I2      },
 148 {"bc1fl",   "N,p",      0x45020000, 0xffe30000, CBL|RD_CC,      I4      },
 149 {"bc2f",    "p",        0x49000000, 0xffff0000, CBD|RD_CC               },
 150 {"bc2fl",   "p",        0x49020000, 0xffff0000, CBL|RD_CC,      A3      },
 151 {"bc2fl",   "p",        0x49020000, 0xffff0000, CBL|RD_CC,      I2      },
 152 {"bc3f",    "p",        0x4d000000, 0xffff0000, CBD|RD_CC               },
 153 {"bc3fl",   "p",        0x4d020000, 0xffff0000, CBL|RD_CC,      A3      },
 154 {"bc3fl",   "p",        0x4d020000, 0xffff0000, CBL|RD_CC,      I2      },
 155 {"bc0t",    "p",        0x41010000, 0xffff0000, CBD|RD_CC               },
 156 {"bc0tl",   "p",        0x41030000, 0xffff0000, CBL|RD_CC,      A3      },
 157 {"bc0tl",   "p",        0x41030000, 0xffff0000, CBL|RD_CC,      I2      },
 158 {"bc1t",    "p",        0x45010000, 0xffff0000, CBD|RD_CC               },
 159 {"bc1t",    "N,p",      0x45010000, 0xffe30000, CBD|RD_CC,      I4      },
 160 {"bc1tl",   "p",        0x45030000, 0xffff0000, CBL|RD_CC,      A3      },
 161 {"bc1tl",   "p",        0x45030000, 0xffff0000, CBL|RD_CC,      I2      },
 162 {"bc1tl",   "N,p",      0x45030000, 0xffe30000, CBL|RD_CC,      I4      },
 163 {"bc2t",    "p",        0x49010000, 0xffff0000, CBD|RD_CC               },
 164 {"bc2tl",   "p",        0x49030000, 0xffff0000, CBL|RD_CC,      A3      },
 165 {"bc2tl",   "p",        0x49030000, 0xffff0000, CBL|RD_CC,      I2      },
 166 {"bc3t",    "p",        0x4d010000, 0xffff0000, CBD|RD_CC               },
 167 {"bc3tl",   "p",        0x4d030000, 0xffff0000, CBL|RD_CC,      A3      },
 168 {"bc3tl",   "p",        0x4d030000, 0xffff0000, CBL|RD_CC,      I2      },
 169 {"beqz",    "s,p",      0x10000000, 0xfc1f0000, CBD|RD_s                },
 170 {"beqzl",   "s,p",      0x50000000, 0xfc1f0000, CBL|RD_s,       I2      },
 171 {"beq",     "s,t,p",    0x10000000, 0xfc000000, CBD|RD_s|RD_t           },
 172 {"beq",     "s,I,p",    0,    (int) M_BEQ_I,    INSN_MACRO              },
 173 {"beql",    "s,t,p",    0x50000000, 0xfc000000, CBL|RD_s|RD_t,  A3      },
 174 {"beql",    "s,t,p",    0x50000000, 0xfc000000, CBL|RD_s|RD_t,  I2      },
 175 {"beql",    "s,I,p",    2,    (int) M_BEQL_I,   INSN_MACRO              },
 176 {"bge",     "s,t,p",    0,    (int) M_BGE,      INSN_MACRO              },
 177 {"bge",     "s,I,p",    0,    (int) M_BGE_I,    INSN_MACRO              },
 178 {"bgel",    "s,t,p",    2,    (int) M_BGEL,     INSN_MACRO              },
 179 {"bgel",    "s,I,p",    2,    (int) M_BGEL_I,   INSN_MACRO              },
 180 {"bgeu",    "s,t,p",    0,    (int) M_BGEU,     INSN_MACRO              },
 181 {"bgeu",    "s,I,p",    0,    (int) M_BGEU_I,   INSN_MACRO              },
 182 {"bgeul",   "s,t,p",    2,    (int) M_BGEUL,    INSN_MACRO              },
 183 {"bgeul",   "s,I,p",    2,    (int) M_BGEUL_I,  INSN_MACRO              },
 184 {"bgez",    "s,p",      0x04010000, 0xfc1f0000, CBD|RD_s                },
 185 {"bgezl",   "s,p",      0x04030000, 0xfc1f0000, CBL|RD_s,       A3      },
 186 {"bgezl",   "s,p",      0x04030000, 0xfc1f0000, CBL|RD_s,       I2      },
 187 {"bgezal",  "s,p",      0x04110000, 0xfc1f0000, CBD|RD_s|WR_31          },
 188 {"bgezall", "s,p",      0x04130000, 0xfc1f0000, CBL|RD_s,       A3      },
 189 {"bgezall", "s,p",      0x04130000, 0xfc1f0000, CBL|RD_s,       I2      },
 190 {"bgt",     "s,t,p",    0,    (int) M_BGT,      INSN_MACRO              },
 191 {"bgt",     "s,I,p",    0,    (int) M_BGT_I,    INSN_MACRO              },
 192 {"bgtl",    "s,t,p",    2,    (int) M_BGTL,     INSN_MACRO              },
 193 {"bgtl",    "s,I,p",    2,    (int) M_BGTL_I,   INSN_MACRO              },
 194 {"bgtu",    "s,t,p",    0,    (int) M_BGTU,     INSN_MACRO              },
 195 {"bgtu",    "s,I,p",    0,    (int) M_BGTU_I,   INSN_MACRO              },
 196 {"bgtul",   "s,t,p",    2,    (int) M_BGTUL,    INSN_MACRO              },
 197 {"bgtul",   "s,I,p",    2,    (int) M_BGTUL_I,  INSN_MACRO              },
 198 {"bgtz",    "s,p",      0x1c000000, 0xfc1f0000, CBD|RD_s                },
 199 {"bgtzl",   "s,p",      0x5c000000, 0xfc1f0000, CBL|RD_s,       A3      },
 200 {"bgtzl",   "s,p",      0x5c000000, 0xfc1f0000, CBL|RD_s,       I2      },
 201 {"ble",     "s,t,p",    0,    (int) M_BLE,      INSN_MACRO              },
 202 {"ble",     "s,I,p",    0,    (int) M_BLE_I,    INSN_MACRO              },
 203 {"blel",    "s,t,p",    2,    (int) M_BLEL,     INSN_MACRO              },
 204 {"blel",    "s,I,p",    2,    (int) M_BLEL_I,   INSN_MACRO              },
 205 {"bleu",    "s,t,p",    0,    (int) M_BLEU,     INSN_MACRO              },
 206 {"bleu",    "s,I,p",    0,    (int) M_BLEU_I,   INSN_MACRO              },
 207 {"bleul",   "s,t,p",    2,    (int) M_BLEUL,    INSN_MACRO              },
 208 {"bleul",   "s,I,p",    2,    (int) M_BLEUL_I,  INSN_MACRO              },
 209 {"blez",    "s,p",      0x18000000, 0xfc1f0000, CBD|RD_s                },
 210 {"blezl",   "s,p",      0x58000000, 0xfc1f0000, CBL|RD_s,       A3      },
 211 {"blezl",   "s,p",      0x58000000, 0xfc1f0000, CBL|RD_s,       I2      },
 212 {"blt",     "s,t,p",    0,    (int) M_BLT,      INSN_MACRO              },
 213 {"blt",     "s,I,p",    0,    (int) M_BLT_I,    INSN_MACRO              },
 214 {"bltl",    "s,t,p",    2,    (int) M_BLTL,     INSN_MACRO              },
 215 {"bltl",    "s,I,p",    2,    (int) M_BLTL_I,   INSN_MACRO              },
 216 {"bltu",    "s,t,p",    0,    (int) M_BLTU,     INSN_MACRO              },
 217 {"bltu",    "s,I,p",    0,    (int) M_BLTU_I,   INSN_MACRO              },
 218 {"bltul",   "s,t,p",    2,    (int) M_BLTUL,    INSN_MACRO              },
 219 {"bltul",   "s,I,p",    2,    (int) M_BLTUL_I,  INSN_MACRO                      },
 220 {"bltz",    "s,p",      0x04000000, 0xfc1f0000, CBD|RD_s                        },
 221 {"bltzl",   "s,p",      0x04020000, 0xfc1f0000, CBL|RD_s,               A3      },
 222 {"bltzl",   "s,p",      0x04020000, 0xfc1f0000, CBL|RD_s,               I2      },
 223 {"bltzal",  "s,p",      0x04100000, 0xfc1f0000, CBD|RD_s|WR_31                  },
 224 {"bltzall", "s,p",      0x04120000, 0xfc1f0000, CBL|RD_s,               A3      },
 225 {"bltzall", "s,p",      0x04120000, 0xfc1f0000, CBL|RD_s,               I2      },
 226 {"bnez",    "s,p",      0x14000000, 0xfc1f0000, CBD|RD_s                        },
 227 {"bnezl",   "s,p",      0x54000000, 0xfc1f0000, CBL|RD_s,               I2      },
 228 {"bne",     "s,t,p",    0x14000000, 0xfc000000, CBD|RD_s|RD_t                   },
 229 {"bne",     "s,I,p",    0,    (int) M_BNE_I,    INSN_MACRO                      },
 230 {"bnel",    "s,t,p",    0x54000000, 0xfc000000, CBL|RD_s|RD_t,          A3      },
 231 {"bnel",    "s,t,p",    0x54000000, 0xfc000000, CBL|RD_s|RD_t,          I2      },
 232 {"bnel",    "s,I,p",    2,    (int) M_BNEL_I,   INSN_MACRO                      },
 233 {"break",   "",         0x0000000d, 0xffffffff, TRAP                            },
 234 {"break",   "c",        0x0000000d, 0xfc00003f, TRAP                            },
 235 {"c.f.d",   "S,T",      0x46200030, 0xffe007ff, RD_S|RD_T|WR_CC                 },
 236 {"c.f.d",   "M,S,T",    0x46200030, 0xffe000ff, RD_S|RD_T|WR_CC,        I4      },
 237 {"c.f.s",   "S,T",      0x46000030, 0xffe007ff, RD_S|RD_T|WR_CC                 },
 238 {"c.f.s",   "M,S,T",    0x46000030, 0xffe000ff, RD_S|RD_T|WR_CC,        I4      },
 239 {"c.un.d",  "S,T",      0x46200031, 0xffe007ff, RD_S|RD_T|WR_CC                 },
 240 {"c.un.d",  "M,S,T",    0x46200031, 0xffe000ff, RD_S|RD_T|WR_CC,        I4      },
 241 {"c.un.s",  "S,T",      0x46000031, 0xffe007ff, RD_S|RD_T|WR_CC                 },
 242 {"c.un.s",  "M,S,T",    0x46000031, 0xffe000ff, RD_S|RD_T|WR_CC,        I4      },
 243 {"c.eq.d",  "S,T",      0x46200032, 0xffe007ff, RD_S|RD_T|WR_CC                 },
 244 {"c.eq.d",  "M,S,T",    0x46200032, 0xffe000ff, RD_S|RD_T|WR_CC,        I4      },
 245 {"c.eq.s",  "S,T",      0x46000032, 0xffe007ff, RD_S|RD_T|WR_CC                 },
 246 {"c.eq.s",  "M,S,T",    0x46000032, 0xffe000ff, RD_S|RD_T|WR_CC,        I4      },
 247 {"c.ueq.d", "S,T",      0x46200033, 0xffe007ff, RD_S|RD_T|WR_CC                 },
 248 {"c.ueq.d", "M,S,T",    0x46200033, 0xffe000ff, RD_S|RD_T|WR_CC,        I4      },
 249 {"c.ueq.s", "S,T",      0x46000033, 0xffe007ff, RD_S|RD_T|WR_CC                 },
 250 {"c.ueq.s", "M,S,T",    0x46000033, 0xffe000ff, RD_S|RD_T|WR_CC,        I4      },
 251 {"c.olt.d", "S,T",      0x46200034, 0xffe007ff, RD_S|RD_T|WR_CC                 },
 252 {"c.olt.d", "M,S,T",    0x46200034, 0xffe000ff, RD_S|RD_T|WR_CC,        I4      },
 253 {"c.olt.s", "S,T",      0x46000034, 0xffe007ff, RD_S|RD_T|WR_CC                 },
 254 {"c.olt.s", "M,S,T",    0x46000034, 0xffe000ff, RD_S|RD_T|WR_CC,        I4      },
 255 {"c.ult.d", "S,T",      0x46200035, 0xffe007ff, RD_S|RD_T|WR_CC                 },
 256 {"c.ult.d", "M,S,T",    0x46200035, 0xffe000ff, RD_S|RD_T|WR_CC,        I4      },
 257 {"c.ult.s", "S,T",      0x46000035, 0xffe007ff, RD_S|RD_T|WR_CC },
 258 {"c.ult.s", "M,S,T",    0x46000035, 0xffe000ff, RD_S|RD_T|WR_CC,        I4      },
 259 {"c.ole.d", "S,T",      0x46200036, 0xffe007ff, RD_S|RD_T|WR_CC },
 260 {"c.ole.d", "M,S,T",    0x46200036, 0xffe000ff, RD_S|RD_T|WR_CC,        I4      },
 261 {"c.ole.s", "S,T",      0x46000036, 0xffe007ff, RD_S|RD_T|WR_CC },
 262 {"c.ole.s", "M,S,T",    0x46000036, 0xffe000ff, RD_S|RD_T|WR_CC,        I4      },
 263 {"c.ule.d", "S,T",      0x46200037, 0xffe007ff, RD_S|RD_T|WR_CC },
 264 {"c.ule.d", "M,S,T",    0x46200037, 0xffe000ff, RD_S|RD_T|WR_CC,        I4      },
 265 {"c.ule.s", "S,T",      0x46000037, 0xffe007ff, RD_S|RD_T|WR_CC },
 266 {"c.ule.s", "M,S,T",    0x46000037, 0xffe000ff, RD_S|RD_T|WR_CC,        I4      },
 267 {"c.sf.d",  "S,T",      0x46200038, 0xffe007ff, RD_S|RD_T|WR_CC },
 268 {"c.sf.d",  "M,S,T",    0x46200038, 0xffe000ff, RD_S|RD_T|WR_CC,        I4      },
 269 {"c.sf.s",  "S,T",      0x46000038, 0xffe007ff, RD_S|RD_T|WR_CC },
 270 {"c.sf.s",  "M,S,T",    0x46000038, 0xffe000ff, RD_S|RD_T|WR_CC,        I4      },
 271 {"c.ngle.d","S,T",      0x46200039, 0xffe007ff, RD_S|RD_T|WR_CC },
 272 {"c.ngle.d","M,S,T",    0x46200039, 0xffe000ff, RD_S|RD_T|WR_CC,        I4      },
 273 {"c.ngle.s","S,T",      0x46000039, 0xffe007ff, RD_S|RD_T|WR_CC },
 274 {"c.ngle.s","M,S,T",    0x46000039, 0xffe000ff, RD_S|RD_T|WR_CC,        I4      },
 275 {"c.seq.d", "S,T",      0x4620003a, 0xffe007ff, RD_S|RD_T|WR_CC },
 276 {"c.seq.d", "M,S,T",    0x4620003a, 0xffe000ff, RD_S|RD_T|WR_CC,        I4      },
 277 {"c.seq.s", "S,T",      0x4600003a, 0xffe007ff, RD_S|RD_T|WR_CC },
 278 {"c.seq.s", "M,S,T",    0x4600003a, 0xffe000ff, RD_S|RD_T|WR_CC,        I4      },
 279 {"c.ngl.d", "S,T",      0x4620003b, 0xffe007ff, RD_S|RD_T|WR_CC },
 280 {"c.ngl.d", "M,S,T",    0x4620003b, 0xffe000ff, RD_S|RD_T|WR_CC,        I4      },
 281 {"c.ngl.s", "S,T",      0x4600003b, 0xffe007ff, RD_S|RD_T|WR_CC },
 282 {"c.ngl.s", "M,S,T",    0x4600003b, 0xffe000ff, RD_S|RD_T|WR_CC,        I4      },
 283 {"c.lt.d",  "S,T",      0x4620003c, 0xffe007ff, RD_S|RD_T|WR_CC },
 284 {"c.lt.d",  "M,S,T",    0x4620003c, 0xffe000ff, RD_S|RD_T|WR_CC,        I4      },
 285 {"c.lt.s",  "S,T",      0x4600003c, 0xffe007ff, RD_S|RD_T|WR_CC },
 286 {"c.lt.s",  "M,S,T",    0x4600003c, 0xffe000ff, RD_S|RD_T|WR_CC,        I4      },
 287 {"c.nge.d", "S,T",      0x4620003d, 0xffe007ff, RD_S|RD_T|WR_CC },
 288 {"c.nge.d", "M,S,T",    0x4620003d, 0xffe000ff, RD_S|RD_T|WR_CC,        I4      },
 289 {"c.nge.s", "S,T",      0x4600003d, 0xffe007ff, RD_S|RD_T|WR_CC },
 290 {"c.nge.s", "M,S,T",    0x4600003d, 0xffe000ff, RD_S|RD_T|WR_CC,        I4      },
 291 {"c.le.d",  "S,T",      0x4620003e, 0xffe007ff, RD_S|RD_T|WR_CC },
 292 {"c.le.d",  "M,S,T",    0x4620003e, 0xffe000ff, RD_S|RD_T|WR_CC,        I4      },
 293 {"c.le.s",  "S,T",      0x4600003e, 0xffe007ff, RD_S|RD_T|WR_CC },
 294 {"c.le.s",  "M,S,T",    0x4600003e, 0xffe000ff, RD_S|RD_T|WR_CC,        I4      },
 295 {"c.ngt.d", "S,T",      0x4620003f, 0xffe007ff, RD_S|RD_T|WR_CC },
 296 {"c.ngt.d", "M,S,T",    0x4620003f, 0xffe000ff, RD_S|RD_T|WR_CC,        I4      },
 297 {"c.ngt.s", "S,T",      0x4600003f, 0xffe007ff, RD_S|RD_T|WR_CC },
 298 {"c.ngt.s", "M,S,T",    0x4600003f, 0xffe000ff, RD_S|RD_T|WR_CC,        I4      },
 299 {"cache",   "k,o(b)",   0xbc000000, 0xfc000000, RD_b,           I3      },
 300 {"ceil.l.d", "D,S",     0x4620000a, 0xffff003f, WR_D|RD_S,      I3      },
 301 {"ceil.l.s", "D,S",     0x4600000a, 0xffff003f, WR_D|RD_S,      I3      },
 302 {"ceil.w.d", "D,S",     0x4620000e, 0xffff003f, WR_D|RD_S,      I2      },
 303 {"ceil.w.s", "D,S",     0x4600000e, 0xffff003f, WR_D|RD_S,      I2      },
 304 {"cfc0",    "t,G",      0x40400000, 0xffe007ff, LCD|WR_t|RD_C0          },
 305 {"cfc1",    "t,G",      0x44400000, 0xffe007ff, LCD|WR_t|RD_C1          },
 306 {"cfc1",    "t,S",      0x44400000, 0xffe007ff, LCD|WR_t|RD_C1          },
 307 {"cfc2",    "t,G",      0x48400000, 0xffe007ff, LCD|WR_t|RD_C2          },
 308 {"cfc3",    "t,G",      0x4c400000, 0xffe007ff, LCD|WR_t|RD_C3          },
 309 {"ctc0",    "t,G",      0x40c00000, 0xffe007ff, COD|RD_t|WR_CC          },
 310 {"ctc1",    "t,G",      0x44c00000, 0xffe007ff, COD|RD_t|WR_CC          },
 311 {"ctc1",    "t,S",      0x44c00000, 0xffe007ff, COD|RD_t|WR_CC          },
 312 {"ctc2",    "t,G",      0x48c00000, 0xffe007ff, COD|RD_t|WR_CC          },
 313 {"ctc3",    "t,G",      0x4cc00000, 0xffe007ff, COD|RD_t|WR_CC          },
 314 {"cvt.d.l", "D,S",      0x46a00021, 0xffff003f, WR_D|RD_S,      I3      },
 315 {"cvt.d.s", "D,S",      0x46000021, 0xffff003f, WR_D|RD_S               },
 316 {"cvt.d.w", "D,S",      0x46800021, 0xffff003f, WR_D|RD_S               },
 317 {"cvt.l.d", "D,S",      0x46200025, 0xffff003f, WR_D|RD_S,      I3      },
 318 {"cvt.l.s", "D,S",      0x46000025, 0xffff003f, WR_D|RD_S,      I3      },
 319 {"cvt.s.l", "D,S",      0x46a00020, 0xffff003f, WR_D|RD_S,      I3      },
 320 {"cvt.s.d", "D,S",      0x46200020, 0xffff003f, WR_D|RD_S       },
 321 {"cvt.s.w", "D,S",      0x46800020, 0xffff003f, WR_D|RD_S       },
 322 {"cvt.w.d", "D,S",      0x46200024, 0xffff003f, WR_D|RD_S       },
 323 {"cvt.w.s", "D,S",      0x46000024, 0xffff003f, WR_D|RD_S       },
 324 {"dabs",    "d,v",      3,    (int) M_DABS,     INSN_MACRO      },
 325 {"dadd",    "d,v,t",    0x0000002c, 0xfc0007ff, WR_d|RD_s|RD_t, I3      },
 326 {"dadd",    "t,r,I",    3,    (int) M_DADD_I,   INSN_MACRO      },
 327 {"daddi",   "t,r,j",    0x60000000, 0xfc000000, WR_t|RD_s,      I3      },
 328 {"daddiu",  "t,r,j",    0x64000000, 0xfc000000, WR_t|RD_s,      I3      },
 329 {"daddu",   "d,v,t",    0x0000002d, 0xfc0007ff, WR_d|RD_s|RD_t, I3      },
 330 {"daddu",   "t,r,I",    3,    (int) M_DADDU_I,  INSN_MACRO      },
 331 /* dctr and dctw are used on the r5000.  */
 332 {"dctr",    "o(b)",     0xbc050000, 0xfc1f0000, RD_b,   I3      },
 333 {"dctw",    "o(b)",     0xbc090000, 0xfc1f0000, RD_b,   I3      },
 334 /* For ddiv, see the comments about div.  */
 335 {"ddiv",    "z,s,t",    0x0000001e, 0xfc00ffff, RD_s|RD_t|WR_HI|WR_LO,  I3      },
 336 {"ddiv",    "d,v,t",    3,    (int) M_DDIV_3,   INSN_MACRO      },
 337 {"ddiv",    "d,v,I",    3,    (int) M_DDIV_3I,  INSN_MACRO      },
 338 /* For ddivu, see the comments about div.  */
 339 {"ddivu",   "z,s,t",    0x0000001f, 0xfc00ffff, RD_s|RD_t|WR_HI|WR_LO,  I3      },
 340 {"ddivu",   "d,v,t",    3,    (int) M_DDIVU_3,  INSN_MACRO      },
 341 {"ddivu",   "d,v,I",    3,    (int) M_DDIVU_3I, INSN_MACRO      },
 342 /* The MIPS assembler treats the div opcode with two operands as
 343    though the first operand appeared twice (the first operand is both
 344    a source and a destination).  To get the div machine instruction,
 345    you must use an explicit destination of $0.  */
 346 {"div",     "z,s,t",    0x0000001a, 0xfc00ffff, RD_s|RD_t|WR_HI|WR_LO   },
 347 {"div",     "z,t",      0x0000001a, 0xffe0ffff, RD_s|RD_t|WR_HI|WR_LO   },
 348 {"div",     "d,v,t",    0,    (int) M_DIV_3,    INSN_MACRO      },
 349 {"div",     "d,v,I",    0,    (int) M_DIV_3I,   INSN_MACRO      },
 350   /* start-sanitize-r5900 */
 351 {"div1",    "s,t",      0x7000001a, 0xfc00ffff, RD_s|RD_t|WR_HI|WR_LO,  T5      },
 352   /* end-sanitize-r5900 */
 353 {"div.d",   "D,V,T",    0x46200003, 0xffe0003f, WR_D|RD_S|RD_T  },
 354 {"div.s",   "D,V,T",    0x46000003, 0xffe0003f, WR_D|RD_S|RD_T  },
 355 /* For divu, see the comments about div.  */
 356 {"divu",    "z,s,t",    0x0000001b, 0xfc00ffff, RD_s|RD_t|WR_HI|WR_LO   },
 357 {"divu",    "z,t",      0x0000001b, 0xffe0ffff, RD_s|RD_t|WR_HI|WR_LO   },
 358 {"divu",    "d,v,t",    0,    (int) M_DIVU_3,   INSN_MACRO      },
 359 {"divu",    "d,v,I",    0,    (int) M_DIVU_3I,  INSN_MACRO      },
 360   /* start-sanitize-r5900 */
 361 {"divu1",   "s,t",      0x7000001b, 0xfc00ffff, RD_s|RD_t|WR_HI|WR_LO,  T5      },
 362   /* end-sanitize-r5900 */
 363 {"dla",     "t,A(b)",   3,    (int) M_DLA_AB,   INSN_MACRO      },
 364 {"dli",     "t,j",      0x24000000, 0xffe00000, WR_t,   I3      }, /* addiu */
 365 {"dli",     "t,i",      0x34000000, 0xffe00000, WR_t,   I3      }, /* ori */
 366 {"dli",     "t,I",      3,    (int) M_DLI,      INSN_MACRO      },
 367 {"dmadd16", "s,t",      0x00000029, 0xfc00ffff, RD_s|RD_t|WR_LO|RD_LO,  V1      },
 368 {"dmfc0",   "t,G",      0x40200000, 0xffe007ff, LCD|WR_t|RD_C0, I3      },
 369 {"dmtc0",   "t,G",      0x40a00000, 0xffe007ff, COD|RD_t|WR_C0|WR_CC,   I3      },
 370 {"dmfc1",   "t,S",      0x44200000, 0xffe007ff, LCD|WR_t|RD_S,  I3      },
 371 {"dmtc1",   "t,S",      0x44a00000, 0xffe007ff, COD|RD_t|WR_S,  I3      },
 372 {"dmul",    "d,v,t",    3,    (int) M_DMUL,     INSN_MACRO      },
 373 {"dmul",    "d,v,I",    3,    (int) M_DMUL_I,   INSN_MACRO      },
 374 {"dmulo",   "d,v,t",    3,    (int) M_DMULO,    INSN_MACRO      },
 375 {"dmulo",   "d,v,I",    3,    (int) M_DMULO_I,  INSN_MACRO      },
 376 {"dmulou",  "d,v,t",    3,    (int) M_DMULOU,   INSN_MACRO      },
 377 {"dmulou",  "d,v,I",    3,    (int) M_DMULOU_I, INSN_MACRO      },
 378 {"dmult",   "s,t",      0x0000001c, 0xfc00ffff, RD_s|RD_t|WR_HI|WR_LO,  I3      },
 379 {"dmultu",  "s,t",      0x0000001d, 0xfc00ffff, RD_s|RD_t|WR_HI|WR_LO,  I3      },
 380 {"dneg",    "d,w",      0x0000002e, 0xffe007ff, WR_d|RD_t,      I3      }, /* dsub 0 */
 381 {"dnegu",   "d,w",      0x0000002f, 0xffe007ff, WR_d|RD_t,      I3      }, /* dsubu 0*/
 382 {"drem",    "z,s,t",    0x0000001e, 0xfc00ffff, RD_s|RD_t|WR_HI|WR_LO,  I3      },
 383 {"drem",    "d,v,t",    3,    (int) M_DREM_3,   INSN_MACRO      },
 384 {"drem",    "d,v,I",    3,    (int) M_DREM_3I,  INSN_MACRO      },
 385 {"dremu",   "z,s,t",    0x0000001f, 0xfc00ffff, RD_s|RD_t|WR_HI|WR_LO,  I3      },
 386 {"dremu",   "d,v,t",    3,    (int) M_DREMU_3,  INSN_MACRO      },
 387 {"dremu",   "d,v,I",    3,    (int) M_DREMU_3I, INSN_MACRO      },
 388 {"dsllv",   "d,t,s",    0x00000014, 0xfc0007ff, WR_d|RD_t|RD_s, I3      },
 389 {"dsll32",  "d,w,<",    0x0000003c, 0xffe0003f, WR_d|RD_t,      I3      },
 390 {"dsll",    "d,w,s",    0x00000014, 0xfc0007ff, WR_d|RD_t|RD_s, I3      }, /* dsllv */
 391 {"dsll",    "d,w,>",    0x0000003c, 0xffe0003f, WR_d|RD_t,      I3      }, /* dsll32 */
 392 {"dsll",    "d,w,<",    0x00000038, 0xffe0003f, WR_d|RD_t,      I3      },
 393 {"dsrav",   "d,t,s",    0x00000017, 0xfc0007ff, WR_d|RD_t|RD_s, I3      },
 394 {"dsra32",  "d,w,<",    0x0000003f, 0xffe0003f, WR_d|RD_t,      I3      },
 395 {"dsra",    "d,w,s",    0x00000017, 0xfc0007ff, WR_d|RD_t|RD_s, I3      }, /* dsrav */
 396 {"dsra",    "d,w,>",    0x0000003f, 0xffe0003f, WR_d|RD_t,      I3      }, /* dsra32 */
 397 {"dsra",    "d,w,<",    0x0000003b, 0xffe0003f, WR_d|RD_t,      I3      },
 398 {"dsrlv",   "d,t,s",    0x00000016, 0xfc0007ff, WR_d|RD_t|RD_s, I3      },
 399 {"dsrl32",  "d,w,<",    0x0000003e, 0xffe0003f, WR_d|RD_t,      I3      },
 400 {"dsrl",    "d,w,s",    0x00000016, 0xfc0007ff, WR_d|RD_t|RD_s, I3      }, /* dsrlv */
 401 {"dsrl",    "d,w,>",    0x0000003e, 0xffe0003f, WR_d|RD_t,      I3      }, /* dsrl32 */
 402 {"dsrl",    "d,w,<",    0x0000003a, 0xffe0003f, WR_d|RD_t,      I3      },
 403 {"dsub",    "d,v,t",    0x0000002e, 0xfc0007ff, WR_d|RD_s|RD_t, I3      },
 404 {"dsub",    "d,v,I",    3,    (int) M_DSUB_I,   INSN_MACRO      },
 405 {"dsubu",   "d,v,t",    0x0000002f, 0xfc0007ff, WR_d|RD_s|RD_t, I3      },
 406 {"dsubu",   "d,v,I",    3,    (int) M_DSUBU_I,  INSN_MACRO      },
 407 {"eret",    "",         0x42000018, 0xffffffff, I3      },
 408 {"floor.l.d", "D,S",    0x4620000b, 0xffff003f, WR_D|RD_S,      I3      },
 409 {"floor.l.s", "D,S",    0x4600000b, 0xffff003f, WR_D|RD_S,      I3      },
 410 {"floor.w.d", "D,S",    0x4620000f, 0xffff003f, WR_D|RD_S,      I2      },
 411 {"floor.w.s", "D,S",    0x4600000f, 0xffff003f, WR_D|RD_S,      I2      },
 412 {"flushi",  "",         0xbc010000, 0xffffffff, 0,              L1      },
 413 {"flushd",  "",         0xbc020000, 0xffffffff, 0, L1           },
 414 {"flushid", "",         0xbc030000, 0xffffffff, 0, L1           },
 415 {"hibernate","",        0x42000023, 0xffffffff, 0, V1   },
 416 {"jr",      "s",        0x00000008, 0xfc1fffff, UBD|RD_s        },
 417 {"j",       "s",        0x00000008, 0xfc1fffff, UBD|RD_s        }, /* jr */
 418 /* SVR4 PIC code requires special handling for j, so it must be a
 419    macro.  */
 420 {"j",       "a",        0,     (int) M_J_A,     INSN_MACRO      },
 421 /* This form of j is used by the disassembler and internally by the
 422    assembler, but will never match user input (because the line above
 423    will match first).  */
 424 {"j",       "a",        0x08000000, 0xfc000000, UBD             },
 425 {"jalr",    "s",        0x0000f809, 0xfc1fffff, UBD|RD_s|WR_d   },
 426 {"jalr",    "d,s",      0x00000009, 0xfc1f07ff, UBD|RD_s|WR_d   },
 427 /* SVR4 PIC code requires special handling for jal, so it must be a
 428    macro.  */
 429 {"jal",     "d,s",      0,     (int) M_JAL_2,   INSN_MACRO      },
 430 {"jal",     "s",        0,     (int) M_JAL_1,   INSN_MACRO      },
 431 {"jal",     "a",        0,     (int) M_JAL_A,   INSN_MACRO      },
 432 /* This form of jal is used by the disassembler and internally by the
 433    assembler, but will never match user input (because the line above
 434    will match first).  */
 435 {"jal",     "a",        0x0c000000, 0xfc000000, UBD|WR_31       },
 436 {"jalx",    "a",        0x74000000, 0xfc000000, UBD|WR_31       },
 437 {"la",      "t,A(b)",   0,    (int) M_LA_AB,    INSN_MACRO      },
 438 {"lb",      "t,o(b)",   0x80000000, 0xfc000000, LDD|RD_b|WR_t   },
 439 {"lb",      "t,A(b)",   0,    (int) M_LB_AB,    INSN_MACRO      },
 440 {"lbu",     "t,o(b)",   0x90000000, 0xfc000000, LDD|RD_b|WR_t   },
 441 {"lbu",     "t,A(b)",   0,    (int) M_LBU_AB,   INSN_MACRO      },
 442 {"ld",      "t,o(b)",   0xdc000000, 0xfc000000, WR_t|RD_b,      I3      },
 443 {"ld",      "t,o(b)",   0,    (int) M_LD_OB,    INSN_MACRO      },
 444 {"ld",      "t,A(b)",   0,    (int) M_LD_AB,    INSN_MACRO      },
 445 {"ldc1",    "T,o(b)",   0xd4000000, 0xfc000000, CLD|RD_b|WR_T,  I2      },
 446 {"ldc1",    "E,o(b)",   0xd4000000, 0xfc000000, CLD|RD_b|WR_T,  I2      },
 447 {"ldc1",    "T,A(b)",   2,    (int) M_LDC1_AB,  INSN_MACRO      },
 448 {"ldc1",    "E,A(b)",   2,    (int) M_LDC1_AB,  INSN_MACRO      },
 449 {"l.d",     "T,o(b)",   0xd4000000, 0xfc000000, CLD|RD_b|WR_T,  I2      }, /* ldc1 */
 450 {"l.d",     "T,o(b)",   0,    (int) M_L_DOB,    INSN_MACRO      },
 451 {"l.d",     "T,A(b)",   0,    (int) M_L_DAB,    INSN_MACRO      },
 452 {"ldc2",    "E,o(b)",   0xd8000000, 0xfc000000, CLD|RD_b|WR_CC, I2      },
 453 {"ldc2",    "E,A(b)",   2,    (int) M_LDC2_AB,  INSN_MACRO      },
 454 {"ldc3",    "E,o(b)",   0xdc000000, 0xfc000000, CLD|RD_b|WR_CC, I2      },
 455 {"ldc3",    "E,A(b)",   2,    (int) M_LDC3_AB,  INSN_MACRO      },
 456 {"ldl",     "t,o(b)",   0x68000000, 0xfc000000, LDD|WR_t|RD_b,  I3      },
 457 {"ldl",     "t,A(b)",   3,    (int) M_LDL_AB,   INSN_MACRO      },
 458 {"ldr",     "t,o(b)",   0x6c000000, 0xfc000000, LDD|WR_t|RD_b,  I3      },
 459 {"ldr",     "t,A(b)",   3,    (int) M_LDR_AB,   INSN_MACRO      },
 460 {"ldxc1",   "D,t(b)",   0x4c000001, 0xfc00f83f, LDD|WR_D|RD_t|RD_b,     I4      },
 461   /* start-sanitize-r5900 */
 462 {"ldxc1",   "D,t(b)",   0x4c000001, 0xfc00f83f, LDD|WR_D|RD_t|RD_b,     X5      },
 463   /* end-sanitize-r5900 */
 464 {"lh",      "t,o(b)",   0x84000000, 0xfc000000, LDD|RD_b|WR_t   },
 465 {"lh",      "t,A(b)",   0,    (int) M_LH_AB,    INSN_MACRO      },
 466 {"lhu",     "t,o(b)",   0x94000000, 0xfc000000, LDD|RD_b|WR_t   },
 467 {"lhu",     "t,A(b)",   0,    (int) M_LHU_AB,   INSN_MACRO      },
 468 /* li is at the start of the table.  */
 469 {"li.d",    "t,F",      0,    (int) M_LI_D,     INSN_MACRO      },
 470 {"li.d",    "T,L",      0,    (int) M_LI_DD,    INSN_MACRO      },
 471 {"li.s",    "t,f",      0,    (int) M_LI_S,     INSN_MACRO      },
 472 {"li.s",    "T,l",      0,    (int) M_LI_SS,    INSN_MACRO      },
 473 {"ll",      "t,o(b)",   0xc0000000, 0xfc000000, LDD|RD_b|WR_t,  I2      },
 474 {"ll",      "t,A(b)",   2,    (int) M_LL_AB,    INSN_MACRO      },
 475 {"lld",     "t,o(b)",   0xd0000000, 0xfc000000, LDD|RD_b|WR_t,  I3      },
 476 {"lld",     "t,A(b)",   3,    (int) M_LLD_AB,   INSN_MACRO      },
 477 {"lui",     "t,u",      0x3c000000, 0xffe00000, WR_t            },
 478   /* start-sanitize-r5900 */
 479 {"lq",      "t,o(b)",   0x78000000, 0xfc000000, WR_t|RD_b,      T5      },
 480   /* end-sanitize-r5900 */
 481 {"lw",      "t,o(b)",   0x8c000000, 0xfc000000, LDD|RD_b|WR_t   },
 482 {"lw",      "t,A(b)",   0,    (int) M_LW_AB,    INSN_MACRO      },
 483 {"lwc0",    "E,o(b)",   0xc0000000, 0xfc000000, CLD|RD_b|WR_CC  },
 484 {"lwc0",    "E,A(b)",   0,    (int) M_LWC0_AB,  INSN_MACRO      },
 485 {"lwc1",    "T,o(b)",   0xc4000000, 0xfc000000, CLD|RD_b|WR_T   },
 486 {"lwc1",    "E,o(b)",   0xc4000000, 0xfc000000, CLD|RD_b|WR_T   },
 487 {"lwc1",    "T,A(b)",   0,    (int) M_LWC1_AB,  INSN_MACRO      },
 488 {"lwc1",    "E,A(b)",   0,    (int) M_LWC1_AB,  INSN_MACRO      },
 489 {"l.s",     "T,o(b)",   0xc4000000, 0xfc000000, CLD|RD_b|WR_T   }, /* lwc1 */
 490 {"l.s",     "T,A(b)",   0,    (int) M_LWC1_AB,  INSN_MACRO      },
 491 {"lwc2",    "E,o(b)",   0xc8000000, 0xfc000000, CLD|RD_b|WR_CC  },
 492 {"lwc2",    "E,A(b)",   0,    (int) M_LWC2_AB,  INSN_MACRO      },
 493 {"lwc3",    "E,o(b)",   0xcc000000, 0xfc000000, CLD|RD_b|WR_CC  },
 494 {"lwc3",    "E,A(b)",   0,    (int) M_LWC3_AB,  INSN_MACRO      },
 495 {"lwl",     "t,o(b)",   0x88000000, 0xfc000000, LDD|RD_b|WR_t   },
 496 {"lwl",     "t,A(b)",   0,    (int) M_LWL_AB,   INSN_MACRO      },
 497 {"lcache",  "t,o(b)",   0x88000000, 0xfc000000, LDD|RD_b|WR_t,  I2      }, /* same */
 498 {"lcache",  "t,A(b)",   2,    (int) M_LWL_AB,   INSN_MACRO      }, /* as lwl */
 499 {"lwr",     "t,o(b)",   0x98000000, 0xfc000000, LDD|RD_b|WR_t   },
 500 {"lwr",     "t,A(b)",   0,    (int) M_LWR_AB,   INSN_MACRO      },
 501 {"flush",   "t,o(b)",   0x98000000, 0xfc000000, LDD|RD_b|WR_t,  I2      }, /* same */
 502 {"flush",   "t,A(b)",   2,    (int) M_LWR_AB,   INSN_MACRO      }, /* as lwr */
 503 {"lwu",     "t,o(b)",   0x9c000000, 0xfc000000, LDD|RD_b|WR_t,  I3      },
 504 {"lwu",     "t,A(b)",   3,    (int) M_LWU_AB,   INSN_MACRO      },
 505 {"lwxc1",   "D,t(b)",   0x4c000000, 0xfc00f83f, LDD|WR_D|RD_t|RD_b,     I4      },
 506   /* start-sanitize-r5900 */
 507 {"lwxc1",   "D,t(b)",   0x4c000000, 0xfc00f83f, LDD|WR_D|RD_t|RD_b,     X5      },
 508   /* end-sanitize-r5900 */
 509 {"mad",     "s,t",      0x70000000, 0xfc00ffff, RD_s|RD_t|WR_HI|WR_LO|RD_HI|RD_LO,      P3      },
 510 {"madu",    "s,t",      0x70000001, 0xfc00ffff, RD_s|RD_t|WR_HI|WR_LO|RD_HI|RD_LO,      P3      },
 511 {"addciu",  "t,r,j",    0x70000000, 0xfc000000, WR_t|RD_s,L1    },
 512 {"madd.d",  "D,R,S,T",  0x4c000021, 0xfc00003f, RD_R|RD_S|RD_T|WR_D,    I4      },
 513   /* start-sanitize-r5900 */
 514 {"madd.d",  "D,R,S,T",  0x4c000021, 0xfc00003f, RD_R|RD_S|RD_T|WR_D,    X5      },
 515   /* end-sanitize-r5900 */
 516 {"madd.s",  "D,R,S,T",  0x4c000020, 0xfc00003f, RD_R|RD_S|RD_T|WR_D,    I4      },
 517   /* start-sanitize-r5900 */
 518 {"madd.s",  "D,R,S,T",  0x4c000020, 0xfc00003f, RD_R|RD_S|RD_T|WR_D,    X5      },
 519   /* end-sanitize-r5900 */
 520 {"madd",    "s,t",      0x0000001c, 0xfc00ffff, RD_s|RD_t|WR_HI|WR_LO,          L1      },
 521 {"madd",    "s,t",      0x70000000, 0xfc00ffff, RD_s|RD_t|WR_HI|WR_LO,          T3      },
 522 {"madd",    "d,s,t",    0x70000000, 0xfc0007ff, RD_s|RD_t|WR_HI|WR_LO|WR_d,     T3      },
 523   /* start-sanitize-r5900 */
 524 {"madd",    "s,t",      0x70000000, 0xfc00ffff, RD_s|RD_t|WR_HI|WR_LO,          T5      },
 525 {"madd",    "d,s,t",    0x70000000, 0xfc0007ff, RD_s|RD_t|WR_HI|WR_LO|WR_d,     T5      },
 526 {"madd1",   "s,t",      0x70000020, 0xfc00ffff, RD_s|RD_t|WR_HI|WR_LO,          T5      },
 527 {"madd1",   "d,s,t",    0x70000020, 0xfc0007ff, RD_s|RD_t|WR_HI|WR_LO|WR_d,     T5      },
 528   /* end-sanitize-r5900 */
 529 {"maddu",   "s,t",      0x0000001d, 0xfc00ffff, RD_s|RD_t|WR_HI|WR_LO,          L1      },
 530 {"maddu",   "s,t",      0x70000001, 0xfc00ffff, RD_s|RD_t|WR_HI|WR_LO,          T3      },
 531 {"maddu",   "d,s,t",    0x70000001, 0xfc0007ff, RD_s|RD_t|WR_HI|WR_LO|WR_d,     T3      },
 532   /* start-sanitize-r5900 */
 533 {"maddu",   "s,t",      0x70000001, 0xfc00ffff, RD_s|RD_t|WR_HI|WR_LO,          T5      },
 534 {"maddu",   "d,s,t",    0x70000001, 0xfc0007ff, RD_s|RD_t|WR_HI|WR_LO|WR_d,     T5      },
 535 {"maddu1",  "s,t",      0x70000021, 0xfc00ffff, RD_s|RD_t|WR_HI|WR_LO,          T5      },
 536 {"maddu1",  "d,s,t",    0x70000021, 0xfc0007ff, RD_s|RD_t|WR_HI|WR_LO|WR_d,     T5      },
 537   /* end-sanitize-r5900 */
 538 {"madd16",  "s,t",      0x00000028, 0xfc00ffff, RD_s|RD_t|WR_HI|WR_LO|RD_HI|RD_LO,      V1      },
 539 {"mfc0",    "t,G",      0x40000000, 0xffe007ff, LCD|WR_t|RD_C0  },
 540 {"mfc1",    "t,S",      0x44000000, 0xffe007ff, LCD|WR_t|RD_S   },
 541 {"mfc1",    "t,G",      0x44000000, 0xffe007ff, LCD|WR_t|RD_S   },
 542 {"mfc2",    "t,G",      0x48000000, 0xffe007ff, LCD|WR_t|RD_C2  },
 543 {"mfc3",    "t,G",      0x4c000000, 0xffe007ff, LCD|WR_t|RD_C3  },
 544 {"mfhi",    "d",        0x00000010, 0xffff07ff, WR_d|RD_HI      },
 545   /* start-sanitize-r5900 */
 546 {"mfhi1",   "d",        0x70000010, 0xffff07ff, WR_d|RD_HI,     T5      },
 547   /* end-sanitize-r5900 */
 548 {"mflo",    "d",        0x00000012, 0xffff07ff, WR_d|RD_LO      },
 549   /* start-sanitize-r5900 */
 550 {"mflo1",   "d",        0x70000012, 0xffff07ff, WR_d|RD_LO,     T5      },
 551 {"mfsa",    "d",        0x00000028, 0xffff07ff, WR_d,   T5      },
 552   /* end-sanitize-r5900 */
 553 {"mov.d",   "D,S",      0x46200006, 0xffff003f, WR_D|RD_S       },
 554 {"mov.s",   "D,S",      0x46000006, 0xffff003f, WR_D|RD_S       },
 555 {"movf",    "d,s,N",    0x00000001, 0xfc0307ff, WR_d|RD_s|RD_CC,        I4      },
 556   /* start-sanitize-r5900 */
 557 {"movf",    "d,s,N",    0x00000001, 0xfc0307ff, WR_d|RD_s|RD_CC,        X5      },
 558   /* end-sanitize-r5900 */
 559 {"movf.d",  "D,S,N",    0x46200011, 0xffe3003f, WR_D|RD_S|RD_CC,        I4      },
 560   /* start-sanitize-r5900 */
 561 {"movf.d",  "D,S,N",    0x46200011, 0xffe3003f, WR_D|RD_S|RD_CC,        X5      },
 562   /* end-sanitize-r5900 */
 563 {"movf.s",  "D,S,N",    0x46000011, 0xffe3003f, WR_D|RD_S|RD_CC,        I4      },
 564   /* start-sanitize-r5900 */
 565 {"movf.s",  "D,S,N",    0x46000011, 0xffe3003f, WR_D|RD_S|RD_CC,        X5      },
 566   /* end-sanitize-r5900 */
 567 {"movn",    "d,v,t",    0x0000000b, 0xfc0007ff, WR_d|RD_s|RD_t, I4      },
 568   /* start-sanitize-r5900 */
 569 {"movn",    "d,v,t",    0x0000000b, 0xfc0007ff, WR_d|RD_s|RD_t, A5      },
 570   /* end-sanitize-r5900 */
 571 {"ffc",     "d,v",      0x0000000b, 0xfc0007ff, WR_d|RD_s,L1    },
 572 {"movn.d",  "D,S,t",    0x46200013, 0xffe0003f, WR_D|RD_S|RD_t, I4      },
 573   /* start-sanitize-r5900 */
 574 {"movn.d",  "D,S,t",    0x46200013, 0xffe0003f, WR_D|RD_S|RD_t, X5      },
 575   /* end-sanitize-r5900 */
 576 {"movn.s",  "D,S,t",    0x46000013, 0xffe0003f, WR_D|RD_S|RD_t, I4      },
 577   /* start-sanitize-r5900 */
 578 {"movn.s",  "D,S,t",    0x46000013, 0xffe0003f, WR_D|RD_S|RD_t, X5      },
 579   /* end-sanitize-r5900 */
 580 {"movt",    "d,s,N",    0x00010001, 0xfc0307ff, WR_d|RD_s|RD_CC,        I4      },
 581   /* start-sanitize-r5900 */
 582 {"movt",    "d,s,N",    0x00010001, 0xfc0307ff, WR_d|RD_s|RD_CC,        X5      },
 583   /* end-sanitize-r5900 */
 584 {"movt.d",  "D,S,N",    0x46210011, 0xffe3003f, WR_D|RD_S|RD_CC,        I4      },
 585 {"movt.s",  "D,S,N",    0x46010011, 0xffe3003f, WR_D|RD_S|RD_CC,        I4      },
 586 {"movz",    "d,v,t",    0x0000000a, 0xfc0007ff, WR_d|RD_s|RD_t, I4      },
 587   /* start-sanitize-r5900 */
 588 {"movz",    "d,v,t",    0x0000000a, 0xfc0007ff, WR_d|RD_s|RD_t, A5      },
 589   /* end-sanitize-r5900 */
 590 {"ffs",     "d,v",      0x0000000a, 0xfc0007ff, WR_d|RD_s,L1    },
 591 {"movz.d",  "D,S,t",    0x46200012, 0xffe0003f, WR_D|RD_S|RD_t, I4      },
 592   /* start-sanitize-r5900 */
 593 {"movz.d",  "D,S,t",    0x46200012, 0xffe0003f, WR_D|RD_S|RD_t, X5      },
 594   /* end-sanitize-r5900 */
 595 {"movz.s",  "D,S,t",    0x46000012, 0xffe0003f, WR_D|RD_S|RD_t, I4      },
 596   /* start-sanitize-r5900 */
 597 {"movz.s",  "D,S,t",    0x46000012, 0xffe0003f, WR_D|RD_S|RD_t, X5      },
 598   /* end-sanitize-r5900 */
 599 /* move is at the top of the table.  */
 600 {"msub.d",  "D,R,S,T",  0x4c000029, 0xfc00003f, RD_R|RD_S|RD_T|WR_D,    I4      },
 601   /* start-sanitize-r5900 */
 602 {"msub.d",  "D,R,S,T",  0x4c000029, 0xfc00003f, RD_R|RD_S|RD_T|WR_D,    X5      },
 603   /* end-sanitize-r5900 */
 604 {"msub.s",  "D,R,S,T",  0x4c000028, 0xfc00003f, RD_R|RD_S|RD_T|WR_D,    I4      },
 605   /* start-sanitize-r5900 */
 606 {"msub.s",  "D,R,S,T",  0x4c000028, 0xfc00003f, RD_R|RD_S|RD_T|WR_D,    X5      },
 607   /* end-sanitize-r5900 */
 608 {"msub",    "s,t",      0x0000001e, 0xfc00ffff, RD_s|RD_t|WR_HI|WR_LO,L1 },
 609 {"msubu",   "s,t",      0x0000001f, 0xfc00ffff, RD_s|RD_t|WR_HI|WR_LO,L1 },
 610 {"mtc0",    "t,G",      0x40800000, 0xffe007ff, COD|RD_t|WR_C0|WR_CC    },
 611 {"mtc1",    "t,S",      0x44800000, 0xffe007ff, COD|RD_t|WR_S   },
 612 {"mtc1",    "t,G",      0x44800000, 0xffe007ff, COD|RD_t|WR_S   },
 613 {"mtc2",    "t,G",      0x48800000, 0xffe007ff, COD|RD_t|WR_C2|WR_CC    },
 614 {"mtc3",    "t,G",      0x4c800000, 0xffe007ff, COD|RD_t|WR_C3|WR_CC    },
 615 {"mthi",    "s",        0x00000011, 0xfc1fffff, RD_s|WR_HI      },
 616   /* start-sanitize-r5900 */
 617 {"mthi1",   "s",        0x70000011, 0xfc1fffff, RD_s|WR_HI,     T5      },
 618   /* end-sanitize-r5900 */
 619 {"mtlo",    "s",        0x00000013, 0xfc1fffff, RD_s|WR_LO      },
 620   /* start-sanitize-r5900 */
 621 {"mtlo1",   "s",        0x70000013, 0xfc1fffff, RD_s|WR_LO,     T5      },
 622 {"mtsa",    "s",        0x00000019, 0xfc1fffff, RD_s,   T5      },
 623 {"mtsab",   "s,j",      0x04180000, 0xfc1f0000, RD_s,   T5      },
 624 {"mtsah",   "s,j",      0x04190000, 0xfc1f0000, RD_s,   T5      },
 625   /* end-sanitize-r5900 */
 626 {"mul.d",   "D,V,T",    0x46200002, 0xffe0003f, WR_D|RD_S|RD_T  },
 627 {"mul.s",   "D,V,T",    0x46000002, 0xffe0003f, WR_D|RD_S|RD_T  },
 628 {"mul",     "d,v,t",    0x70000002, 0xfc0007ff, WR_d|RD_s|RD_t|WR_HI|WR_LO,     P3      },
 629 {"mul",     "d,v,t",    0,    (int) M_MUL,      INSN_MACRO      },
 630 {"mul",     "d,v,I",    0,    (int) M_MUL_I,    INSN_MACRO      },
 631 {"mulo",    "d,v,t",    0,    (int) M_MULO,     INSN_MACRO      },
 632 {"mulo",    "d,v,I",    0,    (int) M_MULO_I,   INSN_MACRO      },
 633 {"mulou",   "d,v,t",    0,    (int) M_MULOU,    INSN_MACRO      },
 634 {"mulou",   "d,v,I",    0,    (int) M_MULOU_I,  INSN_MACRO      },
 635 {"mult",    "s,t",      0x00000018, 0xfc00ffff, RD_s|RD_t|WR_HI|WR_LO   },
 636 {"mult",    "d,s,t",    0x00000018, 0xfc0007ff, RD_s|RD_t|WR_HI|WR_LO|WR_d, A3 },
 637 {"mult",    "d,s,t",    0x00000018, 0xfc0007ff, RD_s|RD_t|WR_HI|WR_LO|WR_d },
 638   /* start-sanitize-r5900 */
 639 {"mult1",   "d,s,t",    0x70000018, 0xfc0007ff, RD_s|RD_t|WR_HI|WR_LO|WR_d,     T5      },
 640   /* end-sanitize-r5900 */
 641 {"multu",   "s,t",      0x00000019, 0xfc00ffff, RD_s|RD_t|WR_HI|WR_LO   },
 642 {"multu",   "d,s,t",    0x00000019, 0xfc0007ff, RD_s|RD_t|WR_HI|WR_LO|WR_d, A3 },
 643 {"multu",   "d,s,t",    0x00000019, 0xfc0007ff, RD_s|RD_t|WR_HI|WR_LO|WR_d },
 644   /* start-sanitize-r5900 */
 645 {"multu1",  "d,s,t",    0x70000019, 0xfc0007ff, RD_s|RD_t|WR_HI|WR_LO|WR_d,     T5      },
 646   /* end-sanitize-r5900 */
 647 {"neg",     "d,w",      0x00000022, 0xffe007ff, WR_d|RD_t       }, /* sub 0 */
 648 {"negu",    "d,w",      0x00000023, 0xffe007ff, WR_d|RD_t       }, /* subu 0 */
 649 {"neg.d",   "D,V",      0x46200007, 0xffff003f, WR_D|RD_S       },
 650 {"neg.s",   "D,V",      0x46000007, 0xffff003f, WR_D|RD_S       },
 651 {"nmadd.d", "D,R,S,T",  0x4c000031, 0xfc00003f, RD_R|RD_S|RD_T|WR_D,    I4      },
 652 {"nmadd.s", "D,R,S,T",  0x4c000030, 0xfc00003f, RD_R|RD_S|RD_T|WR_D,    I4      },
 653 {"nmsub.d", "D,R,S,T",  0x4c000039, 0xfc00003f, RD_R|RD_S|RD_T|WR_D,    I4      },
 654   /* start-sanitize-r5900 */
 655 {"nmsub.d", "D,R,S,T",  0x4c000039, 0xfc00003f, RD_R|RD_S|RD_T|WR_D,    X5      },
 656   /* end-sanitize-r5900 */
 657 {"nmsub.s", "D,R,S,T",  0x4c000038, 0xfc00003f, RD_R|RD_S|RD_T|WR_D,    I4      },
 658   /* start-sanitize-r5900 */
 659 {"nmsub.s", "D,R,S,T",  0x4c000038, 0xfc00003f, RD_R|RD_S|RD_T|WR_D,    X5      },
 660   /* end-sanitize-r5900 */
 661 /* nop is at the start of the table.  */
 662 {"nor",     "d,v,t",    0x00000027, 0xfc0007ff, WR_d|RD_s|RD_t  },
 663 {"nor",     "t,r,I",    0,    (int) M_NOR_I,    INSN_MACRO      },
 664 {"not",     "d,v",      0x00000027, 0xfc0007ff, WR_d|RD_s|RD_t  },/*nor d,s,0*/
 665 {"or",      "d,v,t",    0x00000025, 0xfc0007ff, WR_d|RD_s|RD_t  },
 666 {"or",      "t,r,I",    0,    (int) M_OR_I,     INSN_MACRO      },
 667 {"ori",     "t,r,i",    0x34000000, 0xfc000000, WR_t|RD_s       },
 668
 669   /* start-sanitize-r5900 */
 670 {"pabsh",   "d,t",      0x70000168, 0xffe007ff, WR_d|RD_t,      T5      },
 671 {"pabsw",   "d,t",      0x70000068, 0xffe007ff, WR_d|RD_t,      T5      },
 672 {"paddb",   "d,v,t",    0x70000208, 0xfc0007ff, WR_d|RD_s|RD_t, T5      },
 673 {"paddh",   "d,v,t",    0x70000108, 0xfc0007ff, WR_d|RD_s|RD_t, T5      },
 674 {"paddw",   "d,v,t",    0x70000008, 0xfc0007ff, WR_d|RD_s|RD_t, T5      },
 675 {"paddsb",  "d,v,t",    0x70000608, 0xfc0007ff, WR_d|RD_s|RD_t, T5      },
 676 {"paddsh",  "d,v,t",    0x70000508, 0xfc0007ff, WR_d|RD_s|RD_t, T5      },
 677 {"paddsw",  "d,v,t",    0x70000408, 0xfc0007ff, WR_d|RD_s|RD_t, T5      },
 678 {"paddub",  "d,v,t",    0x70000628, 0xfc0007ff, WR_d|RD_s|RD_t, T5      },
 679 {"padduh",  "d,v,t",    0x70000528, 0xfc0007ff, WR_d|RD_s|RD_t, T5      },
 680 {"padduw",  "d,v,t",    0x70000428, 0xfc0007ff, WR_d|RD_s|RD_t, T5      },
 681 {"padsbh",  "d,v,t",    0x70000128, 0xfc0007ff, WR_d|RD_s|RD_t, T5      },
 682 {"pand",    "d,v,t",    0x70000489, 0xfc0007ff, WR_d|RD_s|RD_t, T5      },
 683 {"pceqb",   "d,v,t",    0x700002a8, 0xfc0007ff, WR_d|RD_s|RD_t, T5      },
 684 {"pceqh",   "d,v,t",    0x700001a8, 0xfc0007ff, WR_d|RD_s|RD_t, T5      },
 685 {"pceqw",   "d,v,t",    0x700000a8, 0xfc0007ff, WR_d|RD_s|RD_t, T5      },
 686
 687 {"pcgtb",   "d,v,t",    0x70000288, 0xfc0007ff, WR_d|RD_s|RD_t, T5      },
 688 {"pcgth",   "d,v,t",    0x70000188, 0xfc0007ff, WR_d|RD_s|RD_t, T5      },
 689 {"pcgtw",   "d,v,t",    0x70000088, 0xfc0007ff, WR_d|RD_s|RD_t, T5      },
 690
 691 {"pcpyh",   "d,t",      0x700006e9, 0xffe007ff, WR_d|RD_t,      T5      },
 692
 693 {"pcpyld",  "d,v,t",    0x70000389, 0xfc0007ff, WR_d|RD_s|RD_t, T5      },
 694 {"pcpyud",  "d,v,t",    0x700003a9, 0xfc0007ff, WR_d|RD_s|RD_t, T5      },
 695
 696 {"pdivbw",   "s,t",     0x70000749, 0xfc00ffff, RD_s|RD_t|WR_HI|WR_LO,  T5      },
 697 {"pdivuw",   "s,t",     0x70000369, 0xfc00ffff, RD_s|RD_t|WR_HI|WR_LO,  T5      },
 698 {"pdivw",    "s,t",     0x70000349, 0xfc00ffff, RD_s|RD_t|WR_HI|WR_LO,  T5      },
 699
 700 {"pexch",    "d,t",     0x700006a9, 0xffe007ff, WR_d|RD_t,      T5      },
 701 {"pexcw",    "d,t",     0x700007a9, 0xffe007ff, WR_d|RD_t,      T5      },
 702 {"pexeh",    "d,t",     0x70000689, 0xffe007ff, WR_d|RD_t,      T5      },
 703 {"pexoh",    "d,t",     0x70000689, 0xffe007ff, WR_d|RD_t,      T5      },
 704 {"pexew",    "d,t",     0x70000789, 0xffe007ff, WR_d|RD_t,      T5      },
 705 {"pexow",    "d,t",     0x70000789, 0xffe007ff, WR_d|RD_t,      T5      },
 706
 707 {"pext5",    "d,t",     0x70000788, 0xffe007ff, WR_d|RD_t,      T5      },
 708
 709 {"pextlb",   "d,v,t",   0x70000688, 0xfc0007ff, WR_d|RD_s|RD_t, T5      },
 710 {"pextlh",   "d,v,t",   0x70000588, 0xfc0007ff, WR_d|RD_s|RD_t, T5      },
 711 {"pextlw",   "d,v,t",   0x70000488, 0xfc0007ff, WR_d|RD_s|RD_t, T5      },
 712 {"pextub",   "d,v,t",   0x700006a8, 0xfc0007ff, WR_d|RD_s|RD_t, T5      },
 713 {"pextuh",   "d,v,t",   0x700005a8, 0xfc0007ff, WR_d|RD_s|RD_t, T5      },
 714 {"pextuw",   "d,v,t",   0x700004a8, 0xfc0007ff, WR_d|RD_s|RD_t, T5      },
 715
 716 {"phmaddh",  "d,v,t",   0x70000449, 0xfc0007ff, WR_d|RD_s|RD_t|WR_HI|WR_LO,     T5      },
 717 {"phmsubh",  "d,v,t",   0x70000549, 0xfc0007ff, WR_d|RD_s|RD_t|WR_HI|WR_LO,     T5      },
 718
 719 {"pinth",    "d,v,t",   0x70000289, 0xfc0007ff, WR_d|RD_s|RD_t, T5      },
 720 {"pinteh",   "d,v,t",   0x700002a9, 0xfc0007ff, WR_d|RD_s|RD_t, T5      },
 721 {"pintoh",   "d,v,t",   0x700002a9, 0xfc0007ff, WR_d|RD_s|RD_t, T5      },
 722
 723 {"plzcw",    "d,v",     0x70000004, 0xfc1f07ff, WR_d|RD_s,      T5      },
 724
 725 {"pmaddh",   "d,v,t",   0x70000409, 0xfc0007ff, WR_d|RD_s|RD_t|WR_HI|WR_LO,     T5      },
 726 {"pmadduw",  "d,v,t",   0x70000029, 0xfc0007ff, WR_d|RD_s|RD_t|WR_HI|WR_LO,     T5      },
 727 {"pmaddw",   "d,v,t",   0x70000009, 0xfc0007ff, WR_d|RD_s|RD_t|WR_HI|WR_LO,     T5      },
 728
 729 {"pmaxh",    "d,v,t",   0x700001c8, 0xfc0007ff, WR_d|RD_s|RD_t, T5      },
 730 {"pmaxw",    "d,v,t",   0x700000c8, 0xfc0007ff, WR_d|RD_s|RD_t, T5      },
 731
 732 {"pmfhi",    "d",       0x70000209, 0xffff07ff, WR_d|RD_HI,     T5      },
 733 {"pmflo",    "d",       0x70000249, 0xffff07ff, WR_d|RD_LO,     T5      },
 734
 735 {"pmfhl.lw", "d",       0x70000030, 0xffff07ff, WR_d|RD_LO|RD_HI,       T5      },
 736 {"pmfhl.uw", "d",       0x70000070, 0xffff07ff, WR_d|RD_LO|RD_HI,       T5      },
 737 {"pmfhl.slw","d",       0x700000b0, 0xffff07ff, WR_d|RD_LO|RD_HI,       T5      },
 738 {"pmfhl.lh", "d",       0x700000f0, 0xffff07ff, WR_d|RD_LO|RD_HI,       T5      },
 739 {"pmfhl.sh", "d",       0x70000130, 0xffff07ff, WR_d|RD_LO|RD_HI,       T5      },
 740
 741 {"pminh",    "d,v,t",   0x700001e8, 0xfc0007ff, WR_d|RD_s|RD_t, T5      },
 742 {"pminw",    "d,v,t",   0x700000e8, 0xfc0007ff, WR_d|RD_s|RD_t, T5      },
 743
 744 {"pmsubh",   "d,v,t",   0x70000509, 0xfc0007ff, WR_d|RD_s|RD_t|WR_HI|WR_LO,     T5      },
 745 {"pmsubw",   "d,v,t",   0x70000109, 0xfc0007ff, WR_d|RD_s|RD_t|WR_HI|WR_LO,     T5      },
 746
 747 {"pmthi",    "v",       0x70000229, 0xfc1fffff, WR_HI|RD_s,     T5      },
 748 {"pmtlo",    "v",       0x70000269, 0xfc1fffff, WR_LO|RD_s,     T5      },
 749
 750 {"pmthl.lw", "v",       0x70000031, 0xfc1fffff, WR_HI|WR_LO|RD_s,       T5      },
 751
 752 {"pmulth",   "d,v,t",   0x70000709, 0xfc0007ff, WR_d|RD_s|RD_t|WR_HI|WR_LO,     T5      },
 753 {"pmultuw",  "d,v,t",   0x70000329, 0xfc0007ff, WR_d|RD_s|RD_t|WR_HI|WR_LO,     T5      },
 754 {"pmultw",   "d,v,t",   0x70000309, 0xfc0007ff, WR_d|RD_s|RD_t|WR_HI|WR_LO,     T5      },
 755
 756 {"pnor",    "d,v,t",    0x700004e9, 0xfc0007ff, WR_d|RD_s|RD_t, T5      },
 757 {"por",     "d,v,t",    0x700004a9, 0xfc0007ff, WR_d|RD_s|RD_t, T5      },
 758
 759 {"ppac5",   "d,t",      0x700007c8, 0xffe007ff, WR_d|RD_t,      T5      },
 760
 761 {"ppacb",   "d,v,t",    0x700006c8, 0xfc0007ff, WR_d|RD_s|RD_t, T5      },
 762 {"ppach",   "d,v,t",    0x700005c8, 0xfc0007ff, WR_d|RD_s|RD_t, T5      },
 763 {"ppacw",   "d,v,t",    0x700004c8, 0xfc0007ff, WR_d|RD_s|RD_t, T5      },
 764
 765 {"prevh",   "d,t",      0x700006c9, 0xffe007ff, WR_d|RD_t,      T5      },
 766 {"prot3w",  "d,t",      0x700007c9, 0xffe007ff, WR_d|RD_t,      T5      },
 767
 768 {"psllh",  "d,t,<",     0x70000034, 0xffe0003f, WR_d|RD_t,      T5      },
 769 {"psllvw", "d,t,s",     0x70000089, 0xfc0007ff, WR_d|RD_t|RD_s, T5      },
 770 {"psllw",  "d,t,<",     0x7000003c, 0xffe0003f, WR_d|RD_t,      T5      },
 771
 772 {"psrah",  "d,t,<",     0x70000037, 0xffe0003f, WR_d|RD_t,      T5      },
 773 {"psravw", "d,t,s",     0x700000e9, 0xfc0007ff, WR_d|RD_t|RD_s, T5      },
 774 {"psraw",  "d,t,<",     0x7000003f, 0xffe0003f, WR_d|RD_t,      T5      },
 775
 776 {"psrlh",  "d,t,<",     0x70000036, 0xffe0003f, WR_d|RD_t,      T5      },
 777 {"psrlvw", "d,t,s",     0x700000c9, 0xfc0007ff, WR_d|RD_t|RD_s, T5      },
 778 {"psrlw",  "d,t,<",     0x7000003e, 0xffe0003f, WR_d|RD_t,      T5      },
 779
 780 {"psubb",  "d,v,t",     0x70000248, 0xfc0007ff, WR_d|RD_s|RD_t, T5      },
 781 {"psubh",  "d,v,t",     0x70000148, 0xfc0007ff, WR_d|RD_s|RD_t, T5      },
 782 {"psubsb", "d,v,t",     0x70000648, 0xfc0007ff, WR_d|RD_s|RD_t, T5      },
 783 {"psubsh", "d,v,t",     0x70000548, 0xfc0007ff, WR_d|RD_s|RD_t, T5      },
 784 {"psubsw", "d,v,t",     0x70000448, 0xfc0007ff, WR_d|RD_s|RD_t, T5      },
 785 {"psubub", "d,v,t",     0x70000668, 0xfc0007ff, WR_d|RD_s|RD_t, T5      },
 786 {"psubuh", "d,v,t",     0x70000568, 0xfc0007ff, WR_d|RD_s|RD_t, T5      },
 787 {"psubuw", "d,v,t",     0x70000468, 0xfc0007ff, WR_d|RD_s|RD_t, T5      },
 788 {"psubw",  "d,v,t",     0x70000048, 0xfc0007ff, WR_d|RD_s|RD_t, T5      },
 789
 790 {"pxor",   "d,v,t",     0x700004c9, 0xfc0007ff, WR_d|RD_s|RD_t, T5      },
 791   /* end-sanitize-r5900 */
 792
 793 {"pref",    "k,o(b)",   0xcc000000, 0xfc000000, RD_b,   I4      },
 794 {"prefx",   "h,t(b)",   0x4c00000f, 0xfc0007ff, RD_b|RD_t,      I4      },
 795
 796   /* start-sanitize-r5900 */
 797 {"qfsrv",   "d,v,t",    0x700006e8, 0xfc0007ff, WR_d|RD_s|RD_t, T5      },
 798   /* end-sanitize-r5900 */
 799
 800 {"recip.d", "D,S",      0x46200015, 0xffff003f, WR_D|RD_S,      I4      },
 801 {"recip.s", "D,S",      0x46000015, 0xffff003f, WR_D|RD_S,      I4      },
 802 {"rem",     "z,s,t",    0x0000001a, 0xfc00ffff, RD_s|RD_t|WR_HI|WR_LO },
 803 {"rem",     "d,v,t",    0,    (int) M_REM_3,    INSN_MACRO      },
 804 {"rem",     "d,v,I",    0,    (int) M_REM_3I,   INSN_MACRO      },
 805 {"remu",    "z,s,t",    0x0000001b, 0xfc00ffff, RD_s|RD_t|WR_HI|WR_LO },
 806 {"remu",    "d,v,t",    0,    (int) M_REMU_3,   INSN_MACRO      },
 807 {"remu",    "d,v,I",    0,    (int) M_REMU_3I,  INSN_MACRO      },
 808 {"rfe",     "",         0x42000010, 0xffffffff, 0               },
 809 {"rol",     "d,v,t",    0,    (int) M_ROL,      INSN_MACRO      },
 810 {"rol",     "d,v,I",    0,    (int) M_ROL_I,    INSN_MACRO      },
 811 {"ror",     "d,v,t",    0,    (int) M_ROR,      INSN_MACRO      },
 812 {"ror",     "d,v,I",    0,    (int) M_ROR_I,    INSN_MACRO      },
 813 {"round.l.d", "D,S",    0x46200008, 0xffff003f, WR_D|RD_S,      I3      },
 814 {"round.l.s", "D,S",    0x46000008, 0xffff003f, WR_D|RD_S,      I3      },
 815 {"round.w.d", "D,S",    0x4620000c, 0xffff003f, WR_D|RD_S,      I2      },
 816 {"round.w.s", "D,S",    0x4600000c, 0xffff003f, WR_D|RD_S,      I2      },
 817 {"rsqrt.d", "D,S",      0x46200016, 0xffff003f, WR_D|RD_S,      I4      },
 818 {"rsqrt.s", "D,S",      0x46000016, 0xffff003f, WR_D|RD_S,      I4      },
 819 {"sb",      "t,o(b)",   0xa0000000, 0xfc000000, SM|RD_t|RD_b    },
 820 {"sb",      "t,A(b)",   0,    (int) M_SB_AB,    INSN_MACRO      },
 821 {"sc",      "t,o(b)",   0xe0000000, 0xfc000000, SM|RD_t|WR_t|RD_b,      I2      },
 822 {"sc",      "t,A(b)",   2,    (int) M_SC_AB,    INSN_MACRO      },
 823 {"scd",     "t,o(b)",   0xf0000000, 0xfc000000, SM|RD_t|WR_t|RD_b,      I3      },
 824 {"scd",     "t,A(b)",   3,    (int) M_SCD_AB,   INSN_MACRO      },
 825 {"sd",      "t,o(b)",   0xfc000000, 0xfc000000, SM|RD_t|RD_b,   I3      },
 826 {"sd",      "t,o(b)",   0,    (int) M_SD_OB,    INSN_MACRO      },
 827 {"sd",      "t,A(b)",   0,    (int) M_SD_AB,    INSN_MACRO      },
 828 {"sdc1",    "T,o(b)",   0xf4000000, 0xfc000000, SM|RD_T|RD_b,   I2      },
 829 {"sdc1",    "E,o(b)",   0xf4000000, 0xfc000000, SM|RD_T|RD_b,   I2      },
 830 {"sdc1",    "T,A(b)",   2,    (int) M_SDC1_AB,  INSN_MACRO      },
 831 {"sdc1",    "E,A(b)",   2,    (int) M_SDC1_AB,  INSN_MACRO      },
 832 {"sdc2",    "E,o(b)",   0xf8000000, 0xfc000000, SM|RD_C2|RD_b,  I2      },
 833 {"sdc2",    "E,A(b)",   2,    (int) M_SDC2_AB,  INSN_MACRO      },
 834 {"sdc3",    "E,o(b)",   0xfc000000, 0xfc000000, SM|RD_C3|RD_b,  I2      },
 835 {"sdc3",    "E,A(b)",   2,    (int) M_SDC3_AB,  INSN_MACRO      },
 836 {"s.d",     "T,o(b)",   0xf4000000, 0xfc000000, SM|RD_T|RD_b,   I2      },
 837 {"s.d",     "T,o(b)",   0,    (int) M_S_DOB,    INSN_MACRO      },
 838 {"s.d",     "T,A(b)",   0,    (int) M_S_DAB,    INSN_MACRO      },
 839 {"sdl",     "t,o(b)",   0xb0000000, 0xfc000000, SM|RD_t|RD_b,   I3      },
 840 {"sdl",     "t,A(b)",   3,    (int) M_SDL_AB,   INSN_MACRO      },
 841 {"sdr",     "t,o(b)",   0xb4000000, 0xfc000000, SM|RD_t|RD_b,   I3      },
 842 {"sdr",     "t,A(b)",   3,    (int) M_SDR_AB,   INSN_MACRO      },
 843 {"sdxc1",   "S,t(b)",   0x4c000009, 0xfc0007ff, SM|RD_S|RD_t|RD_b,      I4      },
 844   /* start-sanitize-r5900 */
 845 {"sdxc1",   "S,t(b)",   0x4c000009, 0xfc0007ff, SM|RD_S|RD_t|RD_b,      X5      },
 846   /* end-sanitize-r5900 */
 847 {"selsl",   "d,v,t",    0x00000005, 0xfc0007ff, WR_d|RD_s|RD_t,L1 },
 848 {"selsr",   "d,v,t",    0x00000001, 0xfc0007ff, WR_d|RD_s|RD_t,L1 },
 849 {"seq",     "d,v,t",    0,    (int) M_SEQ,      INSN_MACRO      },
 850 {"seq",     "d,v,I",    0,    (int) M_SEQ_I,    INSN_MACRO      },
 851 {"sge",     "d,v,t",    0,    (int) M_SGE,      INSN_MACRO      },
 852 {"sge",     "d,v,I",    0,    (int) M_SGE_I,    INSN_MACRO      },
 853 {"sgeu",    "d,v,t",    0,    (int) M_SGEU,     INSN_MACRO      },
 854 {"sgeu",    "d,v,I",    0,    (int) M_SGEU_I,   INSN_MACRO      },
 855 {"sgt",     "d,v,t",    0,    (int) M_SGT,      INSN_MACRO      },
 856 {"sgt",     "d,v,I",    0,    (int) M_SGT_I,    INSN_MACRO      },
 857 {"sgtu",    "d,v,t",    0,    (int) M_SGTU,     INSN_MACRO      },
 858 {"sgtu",    "d,v,I",    0,    (int) M_SGTU_I,   INSN_MACRO      },
 859 {"sh",      "t,o(b)",   0xa4000000, 0xfc000000, SM|RD_t|RD_b    },
 860 {"sh",      "t,A(b)",   0,    (int) M_SH_AB,    INSN_MACRO      },
 861 {"sle",     "d,v,t",    0,    (int) M_SLE,      INSN_MACRO      },
 862 {"sle",     "d,v,I",    0,    (int) M_SLE_I,    INSN_MACRO      },
 863 {"sleu",    "d,v,t",    0,    (int) M_SLEU,     INSN_MACRO      },
 864 {"sleu",    "d,v,I",    0,    (int) M_SLEU_I,   INSN_MACRO      },
 865 {"sllv",    "d,t,s",    0x00000004, 0xfc0007ff, WR_d|RD_t|RD_s  },
 866 {"sll",     "d,w,s",    0x00000004, 0xfc0007ff, WR_d|RD_t|RD_s  }, /* sllv */
 867 {"sll",     "d,w,<",    0x00000000, 0xffe0003f, WR_d|RD_t       },
 868 {"slt",     "d,v,t",    0x0000002a, 0xfc0007ff, WR_d|RD_s|RD_t  },
 869 {"slt",     "d,v,I",    0,    (int) M_SLT_I,    INSN_MACRO      },
 870 {"slti",    "t,r,j",    0x28000000, 0xfc000000, WR_t|RD_s       },
 871 {"sltiu",   "t,r,j",    0x2c000000, 0xfc000000, WR_t|RD_s       },
 872 {"sltu",    "d,v,t",    0x0000002b, 0xfc0007ff, WR_d|RD_s|RD_t  },
 873 {"sltu",    "d,v,I",    0,    (int) M_SLTU_I,   INSN_MACRO      },
 874 {"sne",     "d,v,t",    0,    (int) M_SNE,      INSN_MACRO      },
 875 {"sne",     "d,v,I",    0,    (int) M_SNE_I,    INSN_MACRO      },
 876   /* start-sanitize-r5900 */
 877 {"sq",      "t,o(b)",   0x7c000000, 0xfc000000, SM|RD_t|RD_b,   T5      },
 878   /* end-sanitize-r5900 */
 879 {"sqrt.d",  "D,S",      0x46200004, 0xffff003f, WR_D|RD_S,      I2      },
 880 {"sqrt.s",  "D,S",      0x46000004, 0xffff003f, WR_D|RD_S,      I2      },
 881 {"srav",    "d,t,s",    0x00000007, 0xfc0007ff, WR_d|RD_t|RD_s  },
 882 {"sra",     "d,w,s",    0x00000007, 0xfc0007ff, WR_d|RD_t|RD_s  }, /* srav */
 883 {"sra",     "d,w,<",    0x00000003, 0xffe0003f, WR_d|RD_t       },
 884 {"srlv",    "d,t,s",    0x00000006, 0xfc0007ff, WR_d|RD_t|RD_s  },
 885 {"srl",     "d,w,s",    0x00000006, 0xfc0007ff, WR_d|RD_t|RD_s  }, /* srlv */
 886 {"srl",     "d,w,<",    0x00000002, 0xffe0003f, WR_d|RD_t       },
 887 {"standby", "",         0x42000021, 0xffffffff, 0,              V1      },
 888 {"sub",     "d,v,t",    0x00000022, 0xfc0007ff, WR_d|RD_s|RD_t  },
 889 {"sub",     "d,v,I",    0,    (int) M_SUB_I,    INSN_MACRO      },
 890 {"sub.d",   "D,V,T",    0x46200001, 0xffe0003f, WR_D|RD_S|RD_T  },
 891 {"sub.s",   "D,V,T",    0x46000001, 0xffe0003f, WR_D|RD_S|RD_T  },
 892 {"subu",    "d,v,t",    0x00000023, 0xfc0007ff, WR_d|RD_s|RD_t  },
 893 {"subu",    "d,v,I",    0,    (int) M_SUBU_I,   INSN_MACRO      },
 894 {"suspend", "",         0x42000022, 0xffffffff, 0,              V1      },
 895 {"sw",      "t,o(b)",   0xac000000, 0xfc000000, SM|RD_t|RD_b    },
 896 {"sw",      "t,A(b)",   0,    (int) M_SW_AB,    INSN_MACRO      },
 897 {"swc0",    "E,o(b)",   0xe0000000, 0xfc000000, SM|RD_C0|RD_b   },
 898 {"swc0",    "E,A(b)",   0,    (int) M_SWC0_AB,  INSN_MACRO      },
 899 {"swc1",    "T,o(b)",   0xe4000000, 0xfc000000, SM|RD_T|RD_b    },
 900 {"swc1",    "E,o(b)",   0xe4000000, 0xfc000000, SM|RD_T|RD_b    },
 901 {"swc1",    "T,A(b)",   0,    (int) M_SWC1_AB,  INSN_MACRO      },
 902 {"swc1",    "E,A(b)",   0,    (int) M_SWC1_AB,  INSN_MACRO      },
 903 {"s.s",     "T,o(b)",   0xe4000000, 0xfc000000, SM|RD_T|RD_b    }, /* swc1 */
 904 {"s.s",     "T,A(b)",   0,    (int) M_SWC1_AB,  INSN_MACRO      },
 905 {"swc2",    "E,o(b)",   0xe8000000, 0xfc000000, SM|RD_C2|RD_b   },
 906 {"swc2",    "E,A(b)",   0,    (int) M_SWC2_AB,  INSN_MACRO      },
 907 {"swc3",    "E,o(b)",   0xec000000, 0xfc000000, SM|RD_C3|RD_b   },
 908 {"swc3",    "E,A(b)",   0,    (int) M_SWC3_AB,  INSN_MACRO      },
 909 {"swl",     "t,o(b)",   0xa8000000, 0xfc000000, SM|RD_t|RD_b    },
 910 {"swl",     "t,A(b)",   0,    (int) M_SWL_AB,   INSN_MACRO      },
 911 {"scache",  "t,o(b)",   0xa8000000, 0xfc000000, RD_t|RD_b,      I2      }, /* same */
 912 {"scache",  "t,A(b)",   2,    (int) M_SWL_AB,   INSN_MACRO      }, /* as swl */
 913 {"swr",     "t,o(b)",   0xb8000000, 0xfc000000, SM|RD_t|RD_b    },
 914 {"swr",     "t,A(b)",   0,    (int) M_SWR_AB,   INSN_MACRO      },
 915 {"invalidate", "t,o(b)",0xb8000000, 0xfc000000, RD_t|RD_b,      I2      }, /* same */
 916 {"invalidate", "t,A(b)",2,    (int) M_SWR_AB,   INSN_MACRO      }, /* as swr */
 917 {"swxc1",   "S,t(b)",   0x4c000008, 0xfc0007ff, SM|RD_S|RD_t|RD_b,      I4      },
 918   /* start-sanitize-r5900 */
 919 {"swxc1",   "S,t(b)",   0x4c000008, 0xfc0007ff, SM|RD_S|RD_t|RD_b,      X5      },
 920   /* end-sanitize-r5900 */
 921 {"sync",    "",         0x0000000f, 0xffffffff, 0,              I2      },
 922 {"syscall", "",         0x0000000c, 0xffffffff, TRAP            },
 923 {"syscall", "B",        0x0000000c, 0xfc00003f, TRAP            },
 924 {"teqi",    "s,j",      0x040c0000, 0xfc1f0000, RD_s|TRAP,      I2      },
 925 {"teq",     "s,t",      0x00000034, 0xfc00003f, RD_s|RD_t|TRAP, I2      },
 926 {"teq",     "s,j",      0x040c0000, 0xfc1f0000, RD_s|TRAP,      I2      }, /* teqi */
 927 {"teq",     "s,I",      2,    (int) M_TEQ_I,    INSN_MACRO      },
 928 {"tgei",    "s,j",      0x04080000, 0xfc1f0000, RD_s|TRAP,      I2      },
 929 {"tge",     "s,t",      0x00000030, 0xfc00003f, RD_s|RD_t|TRAP, I2      },
 930 {"tge",     "s,j",      0x04080000, 0xfc1f0000, RD_s|TRAP,      I2      }, /* tgei */
 931 {"tge",     "s,I",      2,    (int) M_TGE_I,    INSN_MACRO      },
 932 {"tgeiu",   "s,j",      0x04090000, 0xfc1f0000, RD_s|TRAP,      I2              },
 933 {"tgeu",    "s,t",      0x00000031, 0xfc00003f, RD_s|RD_t|TRAP, I2       },
 934 {"tgeu",    "s,j",      0x04090000, 0xfc1f0000, RD_s|TRAP,      I2              }, /* tgeiu */
 935 {"tgeu",    "s,I",      2,    (int) M_TGEU_I,   INSN_MACRO      },
 936 {"tlbp",    "",         0x42000008, 0xffffffff, INSN_TLB        },
 937 {"tlbr",    "",         0x42000001, 0xffffffff, INSN_TLB        },
 938 {"tlbwi",   "",         0x42000002, 0xffffffff, INSN_TLB        },
 939 {"tlbwr",   "",         0x42000006, 0xffffffff, INSN_TLB        },
 940 {"tlti",    "s,j",      0x040a0000, 0xfc1f0000, RD_s|TRAP,      I2              },
 941 {"tlt",     "s,t",      0x00000032, 0xfc00003f, RD_s|RD_t|TRAP, I2       },
 942 {"tlt",     "s,j",      0x040a0000, 0xfc1f0000, RD_s|TRAP,      I2              }, /* tlti */
 943 {"tlt",     "s,I",      2,    (int) M_TLT_I,    INSN_MACRO      },
 944 {"tltiu",   "s,j",      0x040b0000, 0xfc1f0000, RD_s|TRAP,      I2              },
 945 {"tltu",    "s,t",      0x00000033, 0xfc00003f, RD_s|RD_t|TRAP, I2       },
 946 {"tltu",    "s,j",      0x040b0000, 0xfc1f0000, RD_s|TRAP,      I2              }, /* tltiu */
 947 {"tltu",    "s,I",      2,    (int) M_TLTU_I,   INSN_MACRO      },
 948 {"tnei",    "s,j",      0x040e0000, 0xfc1f0000, RD_s|TRAP,      I2              },
 949 {"tne",     "s,t",      0x00000036, 0xfc00003f, RD_s|RD_t|TRAP, I2       },
 950 {"tne",     "s,j",      0x040e0000, 0xfc1f0000, RD_s|TRAP,      I2              }, /* tnei */
 951 {"tne",     "s,I",      2,    (int) M_TNE_I,    INSN_MACRO      },
 952 {"trunc.l.d", "D,S",    0x46200009, 0xffff003f, WR_D|RD_S,      I3      },
 953 {"trunc.l.s", "D,S",    0x46000009, 0xffff003f, WR_D|RD_S,      I3      },
 954 {"trunc.w.d", "D,S",    0x4620000d, 0xffff003f, WR_D|RD_S,      I2      },
 955 {"trunc.w.d", "D,S,x",  0x4620000d, 0xffff003f, WR_D|RD_S,      I2      },
 956 {"trunc.w.d", "D,S,t",  0,    (int) M_TRUNCWD,  INSN_MACRO      },
 957 {"trunc.w.s", "D,S",    0x4600000d, 0xffff003f, WR_D|RD_S,      I2      },
 958 {"trunc.w.s", "D,S,x",  0x4600000d, 0xffff003f, WR_D|RD_S,      I2      },
 959 {"trunc.w.s", "D,S,t",  0,    (int) M_TRUNCWS,  INSN_MACRO      },
 960 {"uld",     "t,o(b)",   3,    (int) M_ULD,      INSN_MACRO      },
 961 {"uld",     "t,A(b)",   3,    (int) M_ULD_A,    INSN_MACRO      },
 962 {"ulh",     "t,o(b)",   0,    (int) M_ULH,      INSN_MACRO      },
 963 {"ulh",     "t,A(b)",   0,    (int) M_ULH_A,    INSN_MACRO      },
 964 {"ulhu",    "t,o(b)",   0,    (int) M_ULHU,     INSN_MACRO      },
 965 {"ulhu",    "t,A(b)",   0,    (int) M_ULHU_A,   INSN_MACRO      },
 966 {"ulw",     "t,o(b)",   0,    (int) M_ULW,      INSN_MACRO      },
 967 {"ulw",     "t,A(b)",   0,    (int) M_ULW_A,    INSN_MACRO      },
 968 {"usd",     "t,o(b)",   3,    (int) M_USD,      INSN_MACRO      },
 969 {"usd",     "t,A(b)",   3,    (int) M_USD_A,    INSN_MACRO      },
 970 {"ush",     "t,o(b)",   0,    (int) M_USH,      INSN_MACRO      },
 971 {"ush",     "t,A(b)",   0,    (int) M_USH_A,    INSN_MACRO      },
 972 {"usw",     "t,o(b)",   0,    (int) M_USW,      INSN_MACRO      },
 973 {"usw",     "t,A(b)",   0,    (int) M_USW_A,    INSN_MACRO      },
 974 {"xor",     "d,v,t",    0x00000026, 0xfc0007ff, WR_d|RD_s|RD_t  },
 975 {"xor",     "t,r,I",    0,    (int) M_XOR_I,    INSN_MACRO      },
 976 {"xori",    "t,r,i",    0x38000000, 0xfc000000, WR_t|RD_s       },
 977 {"wait",    "",         0x42000020, 0xffffffff, TRAP,   I3      },
 978 {"waiti",   "",         0x42000020, 0xffffffff, TRAP,   L1      },
 979 {"wb",      "o(b)",     0xbc040000, 0xfc1f0000, SM|RD_b,        L1      },
 980 /* No hazard protection on coprocessor instructions--they shouldn't
 981    change the state of the processor and if they do it's up to the
 982    user to put in nops as necessary.  These are at the end so that the
 983    disasembler recognizes more specific versions first.  */
 984 {"c0",      "C",        0x42000000, 0xfe000000, 0               },
 985 {"c1",      "C",        0x46000000, 0xfe000000, 0               },
 986 {"c2",      "C",        0x4a000000, 0xfe000000, 0               },
 987 {"c3",      "C",        0x4e000000, 0xfe000000, 0               },
 988 {"cop0",     "C",       0,    (int) M_COP0,         INSN_MACRO  },
 989 {"cop1",     "C",       0,    (int) M_COP1,         INSN_MACRO  },
 990 {"cop2",     "C",       0,    (int) M_COP2,         INSN_MACRO  },
 991 {"cop3",     "C",       0,    (int) M_COP3,         INSN_MACRO  },
 992 };
 993
 994 #define MIPS_NUM_OPCODES \
 995         ((sizeof mips_builtin_opcodes) / (sizeof (mips_builtin_opcodes[0])))
 996 const int bfd_mips_num_builtin_opcodes = MIPS_NUM_OPCODES;
 997
 998 /* const removed from the following to allow for dynamic extensions to the
 999  * built-in instruction set. */
1000 struct mips_opcode *mips_opcodes =
1001   (struct mips_opcode *) mips_builtin_opcodes;
1002 int bfd_mips_num_opcodes = MIPS_NUM_OPCODES;
1003 #undef MIPS_NUM_OPCODES
1004