opcodes/mips-opc.c

   1 /* mips.h.  Mips opcode list for GDB, the GNU debugger.
   2    Copyright 1993, 1994, 1995, 1996 Free Software Foundation, Inc.
   3    Contributed by Ralph Campbell and OSF
   4    Commented and modified by Ian Lance Taylor, Cygnus Support
   5
   6 This file is part of GDB, GAS, and the GNU binutils.
   7
   8 GDB, GAS, and the GNU binutils are free software; you can redistribute
   9 them and/or modify them under the terms of the GNU General Public
  10 License as published by the Free Software Foundation; either version
  11 1, or (at your option) any later version.
  12
  13 GDB, GAS, and the GNU binutils are distributed in the hope that they
  14 will be useful, but WITHOUT ANY WARRANTY; without even the implied
  15 warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See
  16 the GNU General Public License for more details.
  17
  18 You should have received a copy of the GNU General Public License
  19 along with this file; see the file COPYING.  If not, write to the Free
  20 Software Foundation, 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.  */
  21
  22 #include <stdio.h>
  23 #include "ansidecl.h"
  24 #include "opcode/mips.h"
  25
  26 /* Short hand so the lines aren't too long.  */
  27
  28 #define LDD     INSN_LOAD_MEMORY_DELAY
  29 #define LCD     INSN_LOAD_COPROC_DELAY
  30 #define UBD     INSN_UNCOND_BRANCH_DELAY
  31 #define CBD     INSN_COND_BRANCH_DELAY
  32 #define COD     INSN_COPROC_MOVE_DELAY
  33 #define CLD     INSN_COPROC_MEMORY_DELAY
  34 #define CBL     INSN_COND_BRANCH_LIKELY
  35 #define TRAP    INSN_TRAP
  36 #define SM      INSN_STORE_MEMORY
  37
  38 #define WR_d    INSN_WRITE_GPR_D
  39 #define WR_t    INSN_WRITE_GPR_T
  40 #define WR_31   INSN_WRITE_GPR_31
  41 #define WR_D    INSN_WRITE_FPR_D
  42 #define WR_T    INSN_WRITE_FPR_T
  43 #define WR_S    INSN_WRITE_FPR_S
  44 #define RD_s    INSN_READ_GPR_S
  45 #define RD_b    INSN_READ_GPR_S
  46 #define RD_t    INSN_READ_GPR_T
  47 #define RD_S    INSN_READ_FPR_S
  48 #define RD_T    INSN_READ_FPR_T
  49 #define RD_R    INSN_READ_FPR_R
  50 #define WR_CC   INSN_WRITE_COND_CODE
  51 #define RD_CC   INSN_READ_COND_CODE
  52 #define RD_C0   INSN_COP
  53 #define RD_C1   INSN_COP
  54 #define RD_C2   INSN_COP
  55 #define RD_C3   INSN_COP
  56 #define WR_C0   INSN_COP
  57 #define WR_C1   INSN_COP
  58 #define WR_C2   INSN_COP
  59 #define WR_C3   INSN_COP
  60 #define WR_HI   INSN_WRITE_HI
  61 #define WR_LO   INSN_WRITE_LO
  62 #define RD_HI   INSN_READ_HI
  63 #define RD_LO   INSN_READ_LO
  64
  65 #define I2      INSN_ISA2
  66 #define I3      INSN_ISA3
  67 #define P3      INSN_4650
  68 #define I4      INSN_ISA4
  69 #define L1      INSN_4010
  70 #define V1      INSN_4100
  71
  72 /* start-sanitize-r5900 */
  73 /*
  74    A5,X5 - the 5900 is mostly a mips3 machine with a few mips4
  75    instructions.  I've kluged this by duplicating the particular
  76    mips4 instructions and marking them INSN_5900.  This solution
  77    to the mostly mipsX but some mipsX+1 problem does not scale
  78    well, and has the drawback of duplicating some of the data
  79    in this table.  Also, this solution will loose if you specify
  80    a mips4 + 5900 machine, because it will include the same
  81    insn twice.  But it works for now.
  82
  83    T5 - r5900 extension instructions (not mips anything)
  84    A5 is used to mark mips4 insns that are on the 5900.
  85    X5 is used to mark mips4 insns (mostly double math insns)
  86       that are NOT on the 5900, but are needed until I can
  87       fix the compiler and librarys not to use or generate them.
  88    */
  89
  90 #define T5      INSN_5900
  91 #define A5      INSN_5900
  92 #define X5      INSN_5900
  93 /* end-sanitize-r5900 */
  94
  95
  96
  97 /* The order of overloaded instructions matters.  Label arguments and
  98    register arguments look the same. Instructions that can have either
  99    for arguments must apear in the correct order in this table for the
 100    assembler to pick the right one. In other words, entries with
 101    immediate operands must apear after the same instruction with
 102    registers.
 103
 104    Many instructions are short hand for other instructions (i.e., The
 105    jal <register> instruction is short for jalr <register>).  */
 106
 107 const struct mips_opcode mips_builtin_opcodes[] = {
 108 /* These instructions appear first so that the disassembler will find
 109    them first.  The assemblers uses a hash table based on the
 110    instruction name anyhow.  */
 111 /* name,        args,   mask,           match,  pinfo */
 112 {"nop",     "",         0x00000000, 0xffffffff, 0               },
 113 {"li",      "t,j",      0x24000000, 0xffe00000, WR_t            }, /* addiu */
 114 {"li",      "t,i",      0x34000000, 0xffe00000, WR_t            }, /* ori */
 115 {"li",      "t,I",      0,    (int) M_LI,       INSN_MACRO      },
 116 {"move",    "d,s",      0x0000002d, 0xfc1f07ff, WR_d|RD_s|I3    },/* daddu */
 117 {"move",    "d,s",      0x00000021, 0xfc1f07ff, WR_d|RD_s       },/* addu */
 118 {"move",    "d,s",      0x00000025, 0xfc1f07ff, WR_d|RD_s       },/* or */
 119 {"b",       "p",        0x10000000, 0xffff0000, UBD             },/* beq 0,0 */
 120 {"b",       "p",        0x04010000, 0xffff0000, UBD             },/* bgez 0 */
 121 {"bal",     "p",        0x04110000, 0xffff0000, UBD|WR_31       },/* bgezal 0*/
 122
 123 {"abs",     "d,v",      0,    (int) M_ABS,      INSN_MACRO      },
 124 {"abs.s",   "D,V",      0x46000005, 0xffff003f, WR_D|RD_S       },
 125 {"abs.d",   "D,V",      0x46200005, 0xffff003f, WR_D|RD_S       },
 126 {"add",     "d,v,t",    0x00000020, 0xfc0007ff, WR_d|RD_s|RD_t  },
 127 {"add",     "t,r,I",    0,    (int) M_ADD_I,    INSN_MACRO      },
 128 {"add.s",   "D,V,T",    0x46000000, 0xffe0003f, WR_D|RD_S|RD_T  },
 129 {"add.d",   "D,V,T",    0x46200000, 0xffe0003f, WR_D|RD_S|RD_T  },
 130 {"addi",    "t,r,j",    0x20000000, 0xfc000000, WR_t|RD_s       },
 131 {"addiu",   "t,r,j",    0x24000000, 0xfc000000, WR_t|RD_s       },
 132 {"addu",    "d,v,t",    0x00000021, 0xfc0007ff, WR_d|RD_s|RD_t  },
 133 {"addu",    "t,r,I",    0,    (int) M_ADDU_I,   INSN_MACRO      },
 134 {"and",     "d,v,t",    0x00000024, 0xfc0007ff, WR_d|RD_s|RD_t  },
 135 {"and",     "t,r,I",    0,    (int) M_AND_I,    INSN_MACRO      },
 136 {"andi",    "t,r,i",    0x30000000, 0xfc000000, WR_t|RD_s       },
 137 /* b is at the top of the table.  */
 138 /* bal is at the top of the table.  */
 139 {"bc0f",    "p",        0x41000000, 0xffff0000, CBD|RD_CC       },
 140 {"bc0fl",   "p",        0x41020000, 0xffff0000, CBL|RD_CC|I2    },
 141 {"bc1f",    "p",        0x45000000, 0xffff0000, CBD|RD_CC       },
 142 {"bc1f",    "N,p",      0x45000000, 0xffe30000, CBD|RD_CC|I4    },
 143 {"bc1fl",   "p",        0x45020000, 0xffff0000, CBL|RD_CC|I2    },
 144 {"bc1fl",   "N,p",      0x45020000, 0xffe30000, CBL|RD_CC|I4    },
 145 {"bc2f",    "p",        0x49000000, 0xffff0000, CBD|RD_CC       },
 146 {"bc2fl",   "p",        0x49020000, 0xffff0000, CBL|RD_CC|I2    },
 147 {"bc3f",    "p",        0x4d000000, 0xffff0000, CBD|RD_CC       },
 148 {"bc3fl",   "p",        0x4d020000, 0xffff0000, CBL|RD_CC|I2    },
 149 {"bc0t",    "p",        0x41010000, 0xffff0000, CBD|RD_CC       },
 150 {"bc0tl",   "p",        0x41030000, 0xffff0000, CBL|RD_CC|I2    },
 151 {"bc1t",    "p",        0x45010000, 0xffff0000, CBD|RD_CC       },
 152 {"bc1t",    "N,p",      0x45010000, 0xffe30000, CBD|RD_CC|I4    },
 153 {"bc1tl",   "p",        0x45030000, 0xffff0000, CBL|RD_CC|I2    },
 154 {"bc1tl",   "N,p",      0x45030000, 0xffe30000, CBL|RD_CC|I4    },
 155 {"bc2t",    "p",        0x49010000, 0xffff0000, CBD|RD_CC       },
 156 {"bc2tl",   "p",        0x49030000, 0xffff0000, CBL|RD_CC|I2    },
 157 {"bc3t",    "p",        0x4d010000, 0xffff0000, CBD|RD_CC       },
 158 {"bc3tl",   "p",        0x4d030000, 0xffff0000, CBL|RD_CC|I2    },
 159 {"beqz",    "s,p",      0x10000000, 0xfc1f0000, CBD|RD_s        },
 160 {"beqzl",   "s,p",      0x50000000, 0xfc1f0000, CBL|RD_s|I2     },
 161 {"beq",     "s,t,p",    0x10000000, 0xfc000000, CBD|RD_s|RD_t   },
 162 {"beq",     "s,I,p",    0,    (int) M_BEQ_I,    INSN_MACRO      },
 163 {"beql",    "s,t,p",    0x50000000, 0xfc000000, CBL|RD_s|RD_t|I2},
 164 {"beql",    "s,I,p",    2,    (int) M_BEQL_I,   INSN_MACRO      },
 165 {"bge",     "s,t,p",    0,    (int) M_BGE,      INSN_MACRO      },
 166 {"bge",     "s,I,p",    0,    (int) M_BGE_I,    INSN_MACRO      },
 167 {"bgel",    "s,t,p",    2,    (int) M_BGEL,     INSN_MACRO      },
 168 {"bgel",    "s,I,p",    2,    (int) M_BGEL_I,   INSN_MACRO      },
 169 {"bgeu",    "s,t,p",    0,    (int) M_BGEU,     INSN_MACRO      },
 170 {"bgeu",    "s,I,p",    0,    (int) M_BGEU_I,   INSN_MACRO      },
 171 {"bgeul",   "s,t,p",    2,    (int) M_BGEUL,    INSN_MACRO      },
 172 {"bgeul",   "s,I,p",    2,    (int) M_BGEUL_I,  INSN_MACRO      },
 173 {"bgez",    "s,p",      0x04010000, 0xfc1f0000, CBD|RD_s        },
 174 {"bgezl",   "s,p",      0x04030000, 0xfc1f0000, CBL|RD_s|I2     },
 175 {"bgezal",  "s,p",      0x04110000, 0xfc1f0000, CBD|RD_s|WR_31  },
 176 {"bgezall", "s,p",      0x04130000, 0xfc1f0000, CBL|RD_s|I2     },
 177 {"bgt",     "s,t,p",    0,    (int) M_BGT,      INSN_MACRO      },
 178 {"bgt",     "s,I,p",    0,    (int) M_BGT_I,    INSN_MACRO      },
 179 {"bgtl",    "s,t,p",    2,    (int) M_BGTL,     INSN_MACRO      },
 180 {"bgtl",    "s,I,p",    2,    (int) M_BGTL_I,   INSN_MACRO      },
 181 {"bgtu",    "s,t,p",    0,    (int) M_BGTU,     INSN_MACRO      },
 182 {"bgtu",    "s,I,p",    0,    (int) M_BGTU_I,   INSN_MACRO      },
 183 {"bgtul",   "s,t,p",    2,    (int) M_BGTUL,    INSN_MACRO      },
 184 {"bgtul",   "s,I,p",    2,    (int) M_BGTUL_I,  INSN_MACRO      },
 185 {"bgtz",    "s,p",      0x1c000000, 0xfc1f0000, CBD|RD_s        },
 186 {"bgtzl",   "s,p",      0x5c000000, 0xfc1f0000, CBL|RD_s|I2     },
 187 {"ble",     "s,t,p",    0,    (int) M_BLE,      INSN_MACRO      },
 188 {"ble",     "s,I,p",    0,    (int) M_BLE_I,    INSN_MACRO      },
 189 {"blel",    "s,t,p",    2,    (int) M_BLEL,     INSN_MACRO      },
 190 {"blel",    "s,I,p",    2,    (int) M_BLEL_I,   INSN_MACRO      },
 191 {"bleu",    "s,t,p",    0,    (int) M_BLEU,     INSN_MACRO      },
 192 {"bleu",    "s,I,p",    0,    (int) M_BLEU_I,   INSN_MACRO      },
 193 {"bleul",   "s,t,p",    2,    (int) M_BLEUL,    INSN_MACRO      },
 194 {"bleul",   "s,I,p",    2,    (int) M_BLEUL_I,  INSN_MACRO      },
 195 {"blez",    "s,p",      0x18000000, 0xfc1f0000, CBD|RD_s        },
 196 {"blezl",   "s,p",      0x58000000, 0xfc1f0000, CBL|RD_s|I2     },
 197 {"blt",     "s,t,p",    0,    (int) M_BLT,      INSN_MACRO      },
 198 {"blt",     "s,I,p",    0,    (int) M_BLT_I,    INSN_MACRO      },
 199 {"bltl",    "s,t,p",    2,    (int) M_BLTL,     INSN_MACRO      },
 200 {"bltl",    "s,I,p",    2,    (int) M_BLTL_I,   INSN_MACRO      },
 201 {"bltu",    "s,t,p",    0,    (int) M_BLTU,     INSN_MACRO      },
 202 {"bltu",    "s,I,p",    0,    (int) M_BLTU_I,   INSN_MACRO      },
 203 {"bltul",   "s,t,p",    2,    (int) M_BLTUL,    INSN_MACRO      },
 204 {"bltul",   "s,I,p",    2,    (int) M_BLTUL_I,  INSN_MACRO      },
 205 {"bltz",    "s,p",      0x04000000, 0xfc1f0000, CBD|RD_s        },
 206 {"bltzl",   "s,p",      0x04020000, 0xfc1f0000, CBL|RD_s|I2     },
 207 {"bltzal",  "s,p",      0x04100000, 0xfc1f0000, CBD|RD_s|WR_31  },
 208 {"bltzall", "s,p",      0x04120000, 0xfc1f0000, CBL|RD_s|I2     },
 209 {"bnez",    "s,p",      0x14000000, 0xfc1f0000, CBD|RD_s        },
 210 {"bnezl",   "s,p",      0x54000000, 0xfc1f0000, CBL|RD_s|I2     },
 211 {"bne",     "s,t,p",    0x14000000, 0xfc000000, CBD|RD_s|RD_t   },
 212 {"bne",     "s,I,p",    0,    (int) M_BNE_I,    INSN_MACRO      },
 213 {"bnel",    "s,t,p",    0x54000000, 0xfc000000, CBL|RD_s|RD_t|I2},
 214 {"bnel",    "s,I,p",    2,    (int) M_BNEL_I,   INSN_MACRO      },
 215 {"break",   "",         0x0000000d, 0xffffffff, TRAP            },
 216 {"break",   "c",        0x0000000d, 0xfc00003f, TRAP            },
 217 {"c.f.d",   "S,T",      0x46200030, 0xffe007ff, RD_S|RD_T|WR_CC },
 218 {"c.f.d",   "M,S,T",    0x46200030, 0xffe000ff, RD_S|RD_T|WR_CC|I4 },
 219 {"c.f.s",   "S,T",      0x46000030, 0xffe007ff, RD_S|RD_T|WR_CC },
 220 {"c.f.s",   "M,S,T",    0x46000030, 0xffe000ff, RD_S|RD_T|WR_CC|I4 },
 221 {"c.un.d",  "S,T",      0x46200031, 0xffe007ff, RD_S|RD_T|WR_CC },
 222 {"c.un.d",  "M,S,T",    0x46200031, 0xffe000ff, RD_S|RD_T|WR_CC|I4 },
 223 {"c.un.s",  "S,T",      0x46000031, 0xffe007ff, RD_S|RD_T|WR_CC },
 224 {"c.un.s",  "M,S,T",    0x46000031, 0xffe000ff, RD_S|RD_T|WR_CC|I4 },
 225 {"c.eq.d",  "S,T",      0x46200032, 0xffe007ff, RD_S|RD_T|WR_CC },
 226 {"c.eq.d",  "M,S,T",    0x46200032, 0xffe000ff, RD_S|RD_T|WR_CC|I4 },
 227 {"c.eq.s",  "S,T",      0x46000032, 0xffe007ff, RD_S|RD_T|WR_CC },
 228 {"c.eq.s",  "M,S,T",    0x46000032, 0xffe000ff, RD_S|RD_T|WR_CC|I4 },
 229 {"c.ueq.d", "S,T",      0x46200033, 0xffe007ff, RD_S|RD_T|WR_CC },
 230 {"c.ueq.d", "M,S,T",    0x46200033, 0xffe000ff, RD_S|RD_T|WR_CC|I4 },
 231 {"c.ueq.s", "S,T",      0x46000033, 0xffe007ff, RD_S|RD_T|WR_CC },
 232 {"c.ueq.s", "M,S,T",    0x46000033, 0xffe000ff, RD_S|RD_T|WR_CC|I4 },
 233 {"c.olt.d", "S,T",      0x46200034, 0xffe007ff, RD_S|RD_T|WR_CC },
 234 {"c.olt.d", "M,S,T",    0x46200034, 0xffe000ff, RD_S|RD_T|WR_CC|I4 },
 235 {"c.olt.s", "S,T",      0x46000034, 0xffe007ff, RD_S|RD_T|WR_CC },
 236 {"c.olt.s", "M,S,T",    0x46000034, 0xffe000ff, RD_S|RD_T|WR_CC|I4 },
 237 {"c.ult.d", "S,T",      0x46200035, 0xffe007ff, RD_S|RD_T|WR_CC },
 238 {"c.ult.d", "M,S,T",    0x46200035, 0xffe000ff, RD_S|RD_T|WR_CC|I4 },
 239 {"c.ult.s", "S,T",      0x46000035, 0xffe007ff, RD_S|RD_T|WR_CC },
 240 {"c.ult.s", "M,S,T",    0x46000035, 0xffe000ff, RD_S|RD_T|WR_CC|I4 },
 241 {"c.ole.d", "S,T",      0x46200036, 0xffe007ff, RD_S|RD_T|WR_CC },
 242 {"c.ole.d", "M,S,T",    0x46200036, 0xffe000ff, RD_S|RD_T|WR_CC|I4 },
 243 {"c.ole.s", "S,T",      0x46000036, 0xffe007ff, RD_S|RD_T|WR_CC },
 244 {"c.ole.s", "M,S,T",    0x46000036, 0xffe000ff, RD_S|RD_T|WR_CC|I4 },
 245 {"c.ule.d", "S,T",      0x46200037, 0xffe007ff, RD_S|RD_T|WR_CC },
 246 {"c.ule.d", "M,S,T",    0x46200037, 0xffe000ff, RD_S|RD_T|WR_CC|I4 },
 247 {"c.ule.s", "S,T",      0x46000037, 0xffe007ff, RD_S|RD_T|WR_CC },
 248 {"c.ule.s", "M,S,T",    0x46000037, 0xffe000ff, RD_S|RD_T|WR_CC|I4 },
 249 {"c.sf.d",  "S,T",      0x46200038, 0xffe007ff, RD_S|RD_T|WR_CC },
 250 {"c.sf.d",  "M,S,T",    0x46200038, 0xffe000ff, RD_S|RD_T|WR_CC|I4 },
 251 {"c.sf.s",  "S,T",      0x46000038, 0xffe007ff, RD_S|RD_T|WR_CC },
 252 {"c.sf.s",  "M,S,T",    0x46000038, 0xffe000ff, RD_S|RD_T|WR_CC|I4 },
 253 {"c.ngle.d","S,T",      0x46200039, 0xffe007ff, RD_S|RD_T|WR_CC },
 254 {"c.ngle.d","M,S,T",    0x46200039, 0xffe000ff, RD_S|RD_T|WR_CC|I4 },
 255 {"c.ngle.s","S,T",      0x46000039, 0xffe007ff, RD_S|RD_T|WR_CC },
 256 {"c.ngle.s","M,S,T",    0x46000039, 0xffe000ff, RD_S|RD_T|WR_CC|I4 },
 257 {"c.seq.d", "S,T",      0x4620003a, 0xffe007ff, RD_S|RD_T|WR_CC },
 258 {"c.seq.d", "M,S,T",    0x4620003a, 0xffe000ff, RD_S|RD_T|WR_CC|I4 },
 259 {"c.seq.s", "S,T",      0x4600003a, 0xffe007ff, RD_S|RD_T|WR_CC },
 260 {"c.seq.s", "M,S,T",    0x4600003a, 0xffe000ff, RD_S|RD_T|WR_CC|I4 },
 261 {"c.ngl.d", "S,T",      0x4620003b, 0xffe007ff, RD_S|RD_T|WR_CC },
 262 {"c.ngl.d", "M,S,T",    0x4620003b, 0xffe000ff, RD_S|RD_T|WR_CC|I4 },
 263 {"c.ngl.s", "S,T",      0x4600003b, 0xffe007ff, RD_S|RD_T|WR_CC },
 264 {"c.ngl.s", "M,S,T",    0x4600003b, 0xffe000ff, RD_S|RD_T|WR_CC|I4 },
 265 {"c.lt.d",  "S,T",      0x4620003c, 0xffe007ff, RD_S|RD_T|WR_CC },
 266 {"c.lt.d",  "M,S,T",    0x4620003c, 0xffe000ff, RD_S|RD_T|WR_CC|I4 },
 267 {"c.lt.s",  "S,T",      0x4600003c, 0xffe007ff, RD_S|RD_T|WR_CC },
 268 {"c.lt.s",  "M,S,T",    0x4600003c, 0xffe000ff, RD_S|RD_T|WR_CC|I4 },
 269 {"c.nge.d", "S,T",      0x4620003d, 0xffe007ff, RD_S|RD_T|WR_CC },
 270 {"c.nge.d", "M,S,T",    0x4620003d, 0xffe000ff, RD_S|RD_T|WR_CC|I4 },
 271 {"c.nge.s", "S,T",      0x4600003d, 0xffe007ff, RD_S|RD_T|WR_CC },
 272 {"c.nge.s", "M,S,T",    0x4600003d, 0xffe000ff, RD_S|RD_T|WR_CC|I4 },
 273 {"c.le.d",  "S,T",      0x4620003e, 0xffe007ff, RD_S|RD_T|WR_CC },
 274 {"c.le.d",  "M,S,T",    0x4620003e, 0xffe000ff, RD_S|RD_T|WR_CC|I4 },
 275 {"c.le.s",  "S,T",      0x4600003e, 0xffe007ff, RD_S|RD_T|WR_CC },
 276 {"c.le.s",  "M,S,T",    0x4600003e, 0xffe000ff, RD_S|RD_T|WR_CC|I4 },
 277 {"c.ngt.d", "S,T",      0x4620003f, 0xffe007ff, RD_S|RD_T|WR_CC },
 278 {"c.ngt.d", "M,S,T",    0x4620003f, 0xffe000ff, RD_S|RD_T|WR_CC|I4 },
 279 {"c.ngt.s", "S,T",      0x4600003f, 0xffe007ff, RD_S|RD_T|WR_CC },
 280 {"c.ngt.s", "M,S,T",    0x4600003f, 0xffe000ff, RD_S|RD_T|WR_CC|I4 },
 281 {"cache",   "k,o(b)",   0xbc000000, 0xfc000000, RD_b|I3         },
 282 {"ceil.l.d", "D,S",     0x4620000a, 0xffff003f, WR_D|RD_S|I3    },
 283 {"ceil.l.s", "D,S",     0x4600000a, 0xffff003f, WR_D|RD_S|I3    },
 284 {"ceil.w.d", "D,S",     0x4620000e, 0xffff003f, WR_D|RD_S|I2    },
 285 {"ceil.w.s", "D,S",     0x4600000e, 0xffff003f, WR_D|RD_S|I2    },
 286 {"cfc0",    "t,G",      0x40400000, 0xffe007ff, LCD|WR_t|RD_C0  },
 287 {"cfc1",    "t,G",      0x44400000, 0xffe007ff, LCD|WR_t|RD_C1  },
 288 {"cfc1",    "t,S",      0x44400000, 0xffe007ff, LCD|WR_t|RD_C1  },
 289 {"cfc2",    "t,G",      0x48400000, 0xffe007ff, LCD|WR_t|RD_C2  },
 290 {"cfc3",    "t,G",      0x4c400000, 0xffe007ff, LCD|WR_t|RD_C3  },
 291 {"ctc0",    "t,G",      0x40c00000, 0xffe007ff, COD|RD_t|WR_CC  },
 292 {"ctc1",    "t,G",      0x44c00000, 0xffe007ff, COD|RD_t|WR_CC  },
 293 {"ctc1",    "t,S",      0x44c00000, 0xffe007ff, COD|RD_t|WR_CC  },
 294 {"ctc2",    "t,G",      0x48c00000, 0xffe007ff, COD|RD_t|WR_CC  },
 295 {"ctc3",    "t,G",      0x4cc00000, 0xffe007ff, COD|RD_t|WR_CC  },
 296 {"cvt.d.l", "D,S",      0x46a00021, 0xffff003f, WR_D|RD_S|I3    },
 297 {"cvt.d.s", "D,S",      0x46000021, 0xffff003f, WR_D|RD_S       },
 298 {"cvt.d.w", "D,S",      0x46800021, 0xffff003f, WR_D|RD_S       },
 299 {"cvt.l.d", "D,S",      0x46200025, 0xffff003f, WR_D|RD_S|I3    },
 300 {"cvt.l.s", "D,S",      0x46000025, 0xffff003f, WR_D|RD_S|I3    },
 301 {"cvt.s.l", "D,S",      0x46a00020, 0xffff003f, WR_D|RD_S|I3    },
 302 {"cvt.s.d", "D,S",      0x46200020, 0xffff003f, WR_D|RD_S       },
 303 {"cvt.s.w", "D,S",      0x46800020, 0xffff003f, WR_D|RD_S       },
 304 {"cvt.w.d", "D,S",      0x46200024, 0xffff003f, WR_D|RD_S       },
 305 {"cvt.w.s", "D,S",      0x46000024, 0xffff003f, WR_D|RD_S       },
 306 {"dabs",    "d,v",      3,    (int) M_DABS,     INSN_MACRO      },
 307 {"dadd",    "d,v,t",    0x0000002c, 0xfc0007ff, WR_d|RD_s|RD_t|I3},
 308 {"dadd",    "t,r,I",    3,    (int) M_DADD_I,   INSN_MACRO      },
 309 {"daddi",   "t,r,j",    0x60000000, 0xfc000000, WR_t|RD_s|I3    },
 310 {"daddiu",  "t,r,j",    0x64000000, 0xfc000000, WR_t|RD_s|I3    },
 311 {"daddu",   "d,v,t",    0x0000002d, 0xfc0007ff, WR_d|RD_s|RD_t|I3},
 312 {"daddu",   "t,r,I",    3,    (int) M_DADDU_I,  INSN_MACRO      },
 313 /* For ddiv, see the comments about div.  */
 314 {"ddiv",    "z,s,t",    0x0000001e, 0xfc00ffff, RD_s|RD_t|WR_HI|WR_LO|I3 },
 315 {"ddiv",    "d,v,t",    3,    (int) M_DDIV_3,   INSN_MACRO      },
 316 {"ddiv",    "d,v,I",    3,    (int) M_DDIV_3I,  INSN_MACRO      },
 317 /* For ddivu, see the comments about div.  */
 318 {"ddivu",   "z,s,t",    0x0000001f, 0xfc00ffff, RD_s|RD_t|WR_HI|WR_LO|I3 },
 319 {"ddivu",   "d,v,t",    3,    (int) M_DDIVU_3,  INSN_MACRO      },
 320 {"ddivu",   "d,v,I",    3,    (int) M_DDIVU_3I, INSN_MACRO      },
 321 /* The MIPS assembler treats the div opcode with two operands as
 322    though the first operand appeared twice (the first operand is both
 323    a source and a destination).  To get the div machine instruction,
 324    you must use an explicit destination of $0.  */
 325 {"div",     "z,s,t",    0x0000001a, 0xfc00ffff, RD_s|RD_t|WR_HI|WR_LO   },
 326 {"div",     "z,t",      0x0000001a, 0xffe0ffff, RD_s|RD_t|WR_HI|WR_LO   },
 327 {"div",     "d,v,t",    0,    (int) M_DIV_3,    INSN_MACRO      },
 328 {"div",     "d,v,I",    0,    (int) M_DIV_3I,   INSN_MACRO      },
 329   /* start-sanitize-r5900 */
 330 {"div1",    "s,t",      0x7000001a, 0xfc00ffff, RD_s|RD_t|WR_HI|WR_LO|T5},
 331   /* end-sanitize-r5900 */
 332 {"div.d",   "D,V,T",    0x46200003, 0xffe0003f, WR_D|RD_S|RD_T  },
 333 {"div.s",   "D,V,T",    0x46000003, 0xffe0003f, WR_D|RD_S|RD_T  },
 334 /* For divu, see the comments about div.  */
 335 {"divu",    "z,s,t",    0x0000001b, 0xfc00ffff, RD_s|RD_t|WR_HI|WR_LO   },
 336 {"divu",    "z,t",      0x0000001b, 0xffe0ffff, RD_s|RD_t|WR_HI|WR_LO   },
 337 {"divu",    "d,v,t",    0,    (int) M_DIVU_3,   INSN_MACRO      },
 338 {"divu",    "d,v,I",    0,    (int) M_DIVU_3I,  INSN_MACRO      },
 339   /* start-sanitize-r5900 */
 340 {"divu1",   "s,t",      0x7000001b, 0xfc00ffff, RD_s|RD_t|WR_HI|WR_LO|T5},
 341   /* end-sanitize-r5900 */
 342 {"dla",     "t,A(b)",   3,    (int) M_DLA_AB,   INSN_MACRO      },
 343 {"dli",     "t,j",      0x24000000, 0xffe00000, WR_t|I3         }, /* addiu */
 344 {"dli",     "t,i",      0x34000000, 0xffe00000, WR_t|I3         }, /* ori */
 345 {"dli",     "t,I",      3,    (int) M_DLI,      INSN_MACRO      },
 346 {"dmadd16", "s,t",      0x00000029, 0xfc00ffff, RD_s|RD_t|WR_LO|RD_LO|V1 },
 347 {"dmfc0",   "t,G",      0x40200000, 0xffe007ff, LCD|WR_t|RD_C0|I3 },
 348 {"dmtc0",   "t,G",      0x40a00000, 0xffe007ff, COD|RD_t|WR_C0|WR_CC|I3 },
 349 {"dmfc1",   "t,S",      0x44200000, 0xffe007ff, LCD|WR_t|RD_S|I3 },
 350 {"dmtc1",   "t,S",      0x44a00000, 0xffe007ff, COD|RD_t|WR_S|I3 },
 351 {"dmul",    "d,v,t",    3,    (int) M_DMUL,     INSN_MACRO      },
 352 {"dmul",    "d,v,I",    3,    (int) M_DMUL_I,   INSN_MACRO      },
 353 {"dmulo",   "d,v,t",    3,    (int) M_DMULO,    INSN_MACRO      },
 354 {"dmulo",   "d,v,I",    3,    (int) M_DMULO_I,  INSN_MACRO      },
 355 {"dmulou",  "d,v,t",    3,    (int) M_DMULOU,   INSN_MACRO      },
 356 {"dmulou",  "d,v,I",    3,    (int) M_DMULOU_I, INSN_MACRO      },
 357 {"dmult",   "s,t",      0x0000001c, 0xfc00ffff, RD_s|RD_t|WR_HI|WR_LO|I3 },
 358 {"dmultu",  "s,t",      0x0000001d, 0xfc00ffff, RD_s|RD_t|WR_HI|WR_LO|I3 },
 359 {"dneg",    "d,w",      0x0000002e, 0xffe007ff, WR_d|RD_t|I3    }, /* dsub 0 */
 360 {"dnegu",   "d,w",      0x0000002f, 0xffe007ff, WR_d|RD_t|I3    }, /* dsubu 0*/
 361 {"drem",    "z,s,t",    0x0000001e, 0xfc00ffff, RD_s|RD_t|WR_HI|WR_LO|I3 },
 362 {"drem",    "d,v,t",    3,    (int) M_DREM_3,   INSN_MACRO      },
 363 {"drem",    "d,v,I",    3,    (int) M_DREM_3I,  INSN_MACRO      },
 364 {"dremu",   "z,s,t",    0x0000001f, 0xfc00ffff, RD_s|RD_t|WR_HI|WR_LO|I3 },
 365 {"dremu",   "d,v,t",    3,    (int) M_DREMU_3,  INSN_MACRO      },
 366 {"dremu",   "d,v,I",    3,    (int) M_DREMU_3I, INSN_MACRO      },
 367 {"dsllv",   "d,t,s",    0x00000014, 0xfc0007ff, WR_d|RD_t|RD_s|I3},
 368 {"dsll32",  "d,w,<",    0x0000003c, 0xffe0003f, WR_d|RD_t|I3    },
 369 {"dsll",    "d,w,s",    0x00000014, 0xfc0007ff, WR_d|RD_t|RD_s|I3}, /* dsllv */
 370 {"dsll",    "d,w,>",    0x0000003c, 0xffe0003f, WR_d|RD_t|I3    }, /* dsll32 */
 371 {"dsll",    "d,w,<",    0x00000038, 0xffe0003f, WR_d|RD_t|I3    },
 372 {"dsrav",   "d,t,s",    0x00000017, 0xfc0007ff, WR_d|RD_t|RD_s|I3},
 373 {"dsra32",  "d,w,<",    0x0000003f, 0xffe0003f, WR_d|RD_t|I3    },
 374 {"dsra",    "d,w,s",    0x00000017, 0xfc0007ff, WR_d|RD_t|RD_s|I3}, /* dsrav */
 375 {"dsra",    "d,w,>",    0x0000003f, 0xffe0003f, WR_d|RD_t|I3    }, /* dsra32 */
 376 {"dsra",    "d,w,<",    0x0000003b, 0xffe0003f, WR_d|RD_t|I3    },
 377 {"dsrlv",   "d,t,s",    0x00000016, 0xfc0007ff, WR_d|RD_t|RD_s|I3},
 378 {"dsrl32",  "d,w,<",    0x0000003e, 0xffe0003f, WR_d|RD_t|I3    },
 379 {"dsrl",    "d,w,s",    0x00000016, 0xfc0007ff, WR_d|RD_t|RD_s|I3}, /* dsrlv */
 380 {"dsrl",    "d,w,>",    0x0000003e, 0xffe0003f, WR_d|RD_t|I3    }, /* dsrl32 */
 381 {"dsrl",    "d,w,<",    0x0000003a, 0xffe0003f, WR_d|RD_t|I3    },
 382 {"dsub",    "d,v,t",    0x0000002e, 0xfc0007ff, WR_d|RD_s|RD_t|I3},
 383 {"dsub",    "d,v,I",    3,    (int) M_DSUB_I,   INSN_MACRO      },
 384 {"dsubu",   "d,v,t",    0x0000002f, 0xfc0007ff, WR_d|RD_s|RD_t|I3},
 385 {"dsubu",   "d,v,I",    3,    (int) M_DSUBU_I,  INSN_MACRO      },
 386 {"eret",    "",         0x42000018, 0xffffffff, I3              },
 387 {"floor.l.d", "D,S",    0x4620000b, 0xffff003f, WR_D|RD_S|I3    },
 388 {"floor.l.s", "D,S",    0x4600000b, 0xffff003f, WR_D|RD_S|I3    },
 389 {"floor.w.d", "D,S",    0x4620000f, 0xffff003f, WR_D|RD_S|I2    },
 390 {"floor.w.s", "D,S",    0x4600000f, 0xffff003f, WR_D|RD_S|I2    },
 391 {"flushi",  "",         0xbc010000, 0xffffffff, L1              },
 392 {"flushd",  "",         0xbc020000, 0xffffffff, L1              },
 393 {"flushid", "",         0xbc030000, 0xffffffff, L1              },
 394 {"hibernate","",        0x42000023, 0xffffffff, V1              },
 395 {"jr",      "s",        0x00000008, 0xfc1fffff, UBD|RD_s        },
 396 {"j",       "s",        0x00000008, 0xfc1fffff, UBD|RD_s        }, /* jr */
 397 /* SVR4 PIC code requires special handling for j, so it must be a
 398    macro.  */
 399 {"j",       "a",        0,     (int) M_J_A,     INSN_MACRO      },
 400 /* This form of j is used by the disassembler and internally by the
 401    assembler, but will never match user input (because the line above
 402    will match first).  */
 403 {"j",       "a",        0x08000000, 0xfc000000, UBD             },
 404 {"jalr",    "s",        0x0000f809, 0xfc1fffff, UBD|RD_s|WR_d   },
 405 {"jalr",    "d,s",      0x00000009, 0xfc1f07ff, UBD|RD_s|WR_d   },
 406 /* SVR4 PIC code requires special handling for jal, so it must be a
 407    macro.  */
 408 {"jal",     "d,s",      0,     (int) M_JAL_2,   INSN_MACRO      },
 409 {"jal",     "s",        0,     (int) M_JAL_1,   INSN_MACRO      },
 410 {"jal",     "a",        0,     (int) M_JAL_A,   INSN_MACRO      },
 411 /* This form of jal is used by the disassembler and internally by the
 412    assembler, but will never match user input (because the line above
 413    will match first).  */
 414 {"jal",     "a",        0x0c000000, 0xfc000000, UBD|WR_31       },
 415 {"jalx",    "a",        0x74000000, 0xfc000000, UBD|WR_31       },
 416 {"la",      "t,A(b)",   0,    (int) M_LA_AB,    INSN_MACRO      },
 417 {"lb",      "t,o(b)",   0x80000000, 0xfc000000, LDD|RD_b|WR_t   },
 418 {"lb",      "t,A(b)",   0,    (int) M_LB_AB,    INSN_MACRO      },
 419 {"lbu",     "t,o(b)",   0x90000000, 0xfc000000, LDD|RD_b|WR_t   },
 420 {"lbu",     "t,A(b)",   0,    (int) M_LBU_AB,   INSN_MACRO      },
 421 {"ld",      "t,o(b)",   0xdc000000, 0xfc000000, WR_t|RD_b|I3    },
 422 {"ld",      "t,o(b)",   0,    (int) M_LD_OB,    INSN_MACRO      },
 423 {"ld",      "t,A(b)",   0,    (int) M_LD_AB,    INSN_MACRO      },
 424 {"ldc1",    "T,o(b)",   0xd4000000, 0xfc000000, CLD|RD_b|WR_T|I2},
 425 {"ldc1",    "E,o(b)",   0xd4000000, 0xfc000000, CLD|RD_b|WR_T|I2},
 426 {"ldc1",    "T,A(b)",   2,    (int) M_LDC1_AB,  INSN_MACRO      },
 427 {"ldc1",    "E,A(b)",   2,    (int) M_LDC1_AB,  INSN_MACRO      },
 428 {"l.d",     "T,o(b)",   0xd4000000, 0xfc000000, CLD|RD_b|WR_T|I2}, /* ldc1 */
 429 {"l.d",     "T,o(b)",   0,    (int) M_L_DOB,    INSN_MACRO      },
 430 {"l.d",     "T,A(b)",   0,    (int) M_L_DAB,    INSN_MACRO      },
 431 {"ldc2",    "E,o(b)",   0xd8000000, 0xfc000000, CLD|RD_b|WR_CC|I2},
 432 {"ldc2",    "E,A(b)",   2,    (int) M_LDC2_AB,  INSN_MACRO      },
 433 {"ldc3",    "E,o(b)",   0xdc000000, 0xfc000000, CLD|RD_b|WR_CC|I2},
 434 {"ldc3",    "E,A(b)",   2,    (int) M_LDC3_AB,  INSN_MACRO      },
 435 {"ldl",     "t,o(b)",   0x68000000, 0xfc000000, LDD|WR_t|RD_b|I3},
 436 {"ldl",     "t,A(b)",   3,    (int) M_LDL_AB,   INSN_MACRO      },
 437 {"ldr",     "t,o(b)",   0x6c000000, 0xfc000000, LDD|WR_t|RD_b|I3},
 438 {"ldr",     "t,A(b)",   3,    (int) M_LDR_AB,   INSN_MACRO      },
 439 {"ldxc1",   "D,t(b)",   0x4c000001, 0xfc00f83f, LDD|WR_D|RD_t|RD_b|I4 },
 440   /* start-sanitize-r5900 */
 441 {"ldxc1",   "D,t(b)",   0x4c000001, 0xfc00f83f, LDD|WR_D|RD_t|RD_b|X5 },
 442   /* end-sanitize-r5900 */
 443 {"lh",      "t,o(b)",   0x84000000, 0xfc000000, LDD|RD_b|WR_t   },
 444 {"lh",      "t,A(b)",   0,    (int) M_LH_AB,    INSN_MACRO      },
 445 {"lhu",     "t,o(b)",   0x94000000, 0xfc000000, LDD|RD_b|WR_t   },
 446 {"lhu",     "t,A(b)",   0,    (int) M_LHU_AB,   INSN_MACRO      },
 447 /* li is at the start of the table.  */
 448 {"li.d",    "t,F",      0,    (int) M_LI_D,     INSN_MACRO      },
 449 {"li.d",    "T,L",      0,    (int) M_LI_DD,    INSN_MACRO      },
 450 {"li.s",    "t,f",      0,    (int) M_LI_S,     INSN_MACRO      },
 451 {"li.s",    "T,l",      0,    (int) M_LI_SS,    INSN_MACRO      },
 452 {"ll",      "t,o(b)",   0xc0000000, 0xfc000000, LDD|RD_b|WR_t|I2},
 453 {"ll",      "t,A(b)",   2,    (int) M_LL_AB,    INSN_MACRO      },
 454 {"lld",     "t,o(b)",   0xd0000000, 0xfc000000, LDD|RD_b|WR_t|I3},
 455 {"lld",     "t,A(b)",   3,    (int) M_LLD_AB,   INSN_MACRO      },
 456 {"lui",     "t,u",      0x3c000000, 0xffe00000, WR_t            },
 457   /* start-sanitize-r5900 */
 458 {"lq",      "t,o(b)",   0x78000000, 0xfc000000, WR_t|RD_b|T5    },
 459   /* end-sanitize-r5900 */
 460 {"lw",      "t,o(b)",   0x8c000000, 0xfc000000, LDD|RD_b|WR_t   },
 461 {"lw",      "t,A(b)",   0,    (int) M_LW_AB,    INSN_MACRO      },
 462 {"lwc0",    "E,o(b)",   0xc0000000, 0xfc000000, CLD|RD_b|WR_CC  },
 463 {"lwc0",    "E,A(b)",   0,    (int) M_LWC0_AB,  INSN_MACRO      },
 464 {"lwc1",    "T,o(b)",   0xc4000000, 0xfc000000, CLD|RD_b|WR_T   },
 465 {"lwc1",    "E,o(b)",   0xc4000000, 0xfc000000, CLD|RD_b|WR_T   },
 466 {"lwc1",    "T,A(b)",   0,    (int) M_LWC1_AB,  INSN_MACRO      },
 467 {"lwc1",    "E,A(b)",   0,    (int) M_LWC1_AB,  INSN_MACRO      },
 468 {"l.s",     "T,o(b)",   0xc4000000, 0xfc000000, CLD|RD_b|WR_T   }, /* lwc1 */
 469 {"l.s",     "T,A(b)",   0,    (int) M_LWC1_AB,  INSN_MACRO      },
 470 {"lwc2",    "E,o(b)",   0xc8000000, 0xfc000000, CLD|RD_b|WR_CC  },
 471 {"lwc2",    "E,A(b)",   0,    (int) M_LWC2_AB,  INSN_MACRO      },
 472 {"lwc3",    "E,o(b)",   0xcc000000, 0xfc000000, CLD|RD_b|WR_CC  },
 473 {"lwc3",    "E,A(b)",   0,    (int) M_LWC3_AB,  INSN_MACRO      },
 474 {"lwl",     "t,o(b)",   0x88000000, 0xfc000000, LDD|RD_b|WR_t   },
 475 {"lwl",     "t,A(b)",   0,    (int) M_LWL_AB,   INSN_MACRO      },
 476 {"lcache",  "t,o(b)",   0x88000000, 0xfc000000, LDD|RD_b|WR_t|I2}, /* same */
 477 {"lcache",  "t,A(b)",   2,    (int) M_LWL_AB,   INSN_MACRO      }, /* as lwl */
 478 {"lwr",     "t,o(b)",   0x98000000, 0xfc000000, LDD|RD_b|WR_t   },
 479 {"lwr",     "t,A(b)",   0,    (int) M_LWR_AB,   INSN_MACRO      },
 480 {"flush",   "t,o(b)",   0x98000000, 0xfc000000, LDD|RD_b|WR_t|I2}, /* same */
 481 {"flush",   "t,A(b)",   2,    (int) M_LWR_AB,   INSN_MACRO      }, /* as lwr */
 482 {"lwu",     "t,o(b)",   0x9c000000, 0xfc000000, LDD|RD_b|WR_t|I3},
 483 {"lwu",     "t,A(b)",   3,    (int) M_LWU_AB,   INSN_MACRO      },
 484 {"lwxc1",   "D,t(b)",   0x4c000000, 0xfc00f83f, LDD|WR_D|RD_t|RD_b|I4 },
 485   /* start-sanitize-r5900 */
 486 {"lwxc1",   "D,t(b)",   0x4c000000, 0xfc00f83f, LDD|WR_D|RD_t|RD_b|X5 },
 487   /* end-sanitize-r5900 */
 488 {"mad",     "s,t",      0x70000000, 0xfc00ffff, RD_s|RD_t|WR_HI|WR_LO|RD_HI|RD_LO|P3},
 489 {"madu",    "s,t",      0x70000001, 0xfc00ffff, RD_s|RD_t|WR_HI|WR_LO|RD_HI|RD_LO|P3},
 490 {"addciu",  "t,r,j",    0x70000000, 0xfc000000, WR_t|RD_s|L1    },
 491 {"madd.d",  "D,R,S,T",  0x4c000021, 0xfc00003f, RD_R|RD_S|RD_T|WR_D|I4 },
 492   /* start-sanitize-r5900 */
 493 {"madd.d",  "D,R,S,T",  0x4c000021, 0xfc00003f, RD_R|RD_S|RD_T|WR_D|X5 },
 494   /* end-sanitize-r5900 */
 495 {"madd.s",  "D,R,S,T",  0x4c000020, 0xfc00003f, RD_R|RD_S|RD_T|WR_D|I4 },
 496   /* start-sanitize-r5900 */
 497 {"madd.s",  "D,R,S,T",  0x4c000020, 0xfc00003f, RD_R|RD_S|RD_T|WR_D|X5 },
 498   /* end-sanitize-r5900 */
 499 {"madd",    "s,t",      0x0000001c, 0xfc00ffff, RD_s|RD_t|WR_HI|WR_LO|L1 },
 500   /* start-sanitize-r5900 */
 501 {"madd",    "s,t",      0x70000000, 0xfc00ffff, RD_s|RD_t|WR_HI|WR_LO|T5},
 502 {"madd",    "d,s,t",    0x70000000, 0xfc0007ff, RD_s|RD_t|WR_HI|WR_LO|WR_d|T5},
 503 {"madd1",   "s,t",      0x70000020, 0xfc00ffff, RD_s|RD_t|WR_HI|WR_LO|T5},
 504 {"madd1",   "d,s,t",    0x70000020, 0xfc0007ff, RD_s|RD_t|WR_HI|WR_LO|WR_d|T5},
 505   /* end-sanitize-r5900 */
 506 {"maddu",   "s,t",      0x0000001d, 0xfc00ffff, RD_s|RD_t|WR_HI|WR_LO|L1 },
 507   /* start-sanitize-r5900 */
 508 {"maddu",   "s,t",      0x70000001, 0xfc00ffff, RD_s|RD_t|WR_HI|WR_LO|T5},
 509 {"maddu",   "d,s,t",    0x70000001, 0xfc0007ff, RD_s|RD_t|WR_HI|WR_LO|WR_d|T5},
 510 {"maddu1",  "s,t",      0x70000021, 0xfc00ffff, RD_s|RD_t|WR_HI|WR_LO|T5},
 511 {"maddu1",  "d,s,t",    0x70000021, 0xfc0007ff, RD_s|RD_t|WR_HI|WR_LO|WR_d|T5},
 512   /* end-sanitize-r5900 */
 513 {"madd16",  "s,t",      0x00000028, 0xfc00ffff, RD_s|RD_t|WR_HI|WR_LO|RD_HI|RD_LO|V1 },
 514 {"mfc0",    "t,G",      0x40000000, 0xffe007ff, LCD|WR_t|RD_C0  },
 515 {"mfc1",    "t,S",      0x44000000, 0xffe007ff, LCD|WR_t|RD_S   },
 516 {"mfc1",    "t,G",      0x44000000, 0xffe007ff, LCD|WR_t|RD_S   },
 517 {"mfc2",    "t,G",      0x48000000, 0xffe007ff, LCD|WR_t|RD_C2  },
 518 {"mfc3",    "t,G",      0x4c000000, 0xffe007ff, LCD|WR_t|RD_C3  },
 519 {"mfhi",    "d",        0x00000010, 0xffff07ff, WR_d|RD_HI      },
 520   /* start-sanitize-r5900 */
 521 {"mfhi1",   "d",        0x70000010, 0xffff07ff, WR_d|RD_HI|T5   },
 522   /* end-sanitize-r5900 */
 523 {"mflo",    "d",        0x00000012, 0xffff07ff, WR_d|RD_LO      },
 524   /* start-sanitize-r5900 */
 525 {"mflo1",   "d",        0x70000012, 0xffff07ff, WR_d|RD_LO|T5   },
 526 {"mfsa",    "d",        0x00000028, 0xffff07ff, WR_d|T5         },
 527   /* end-sanitize-r5900 */
 528 {"mov.d",   "D,S",      0x46200006, 0xffff003f, WR_D|RD_S       },
 529 {"mov.s",   "D,S",      0x46000006, 0xffff003f, WR_D|RD_S       },
 530 {"movf",    "d,s,N",    0x00000001, 0xfc0307ff, WR_d|RD_s|RD_CC|I4 },
 531   /* start-sanitize-r5900 */
 532 {"movf",    "d,s,N",    0x00000001, 0xfc0307ff, WR_d|RD_s|RD_CC|X5 },
 533   /* end-sanitize-r5900 */
 534 {"movf.d",  "D,S,N",    0x46200011, 0xffe3003f, WR_D|RD_S|RD_CC|I4 },
 535   /* start-sanitize-r5900 */
 536 {"movf.d",  "D,S,N",    0x46200011, 0xffe3003f, WR_D|RD_S|RD_CC|X5 },
 537   /* end-sanitize-r5900 */
 538 {"movf.s",  "D,S,N",    0x46000011, 0xffe3003f, WR_D|RD_S|RD_CC|I4 },
 539   /* start-sanitize-r5900 */
 540 {"movf.s",  "D,S,N",    0x46000011, 0xffe3003f, WR_D|RD_S|RD_CC|X5 },
 541   /* end-sanitize-r5900 */
 542 {"movn",    "d,v,t",    0x0000000b, 0xfc0007ff, WR_d|RD_s|RD_t|I4 },
 543   /* start-sanitize-r5900 */
 544 {"movn",    "d,v,t",    0x0000000b, 0xfc0007ff, WR_d|RD_s|RD_t|A5 },
 545   /* end-sanitize-r5900 */
 546 {"ffc",     "d,v",      0x0000000b, 0xfc0007ff, WR_d|RD_s|L1    },
 547 {"movn.d",  "D,S,t",    0x46200013, 0xffe0003f, WR_D|RD_S|RD_t|I4 },
 548   /* start-sanitize-r5900 */
 549 {"movn.d",  "D,S,t",    0x46200013, 0xffe0003f, WR_D|RD_S|RD_t|X5 },
 550   /* end-sanitize-r5900 */
 551 {"movn.s",  "D,S,t",    0x46000013, 0xffe0003f, WR_D|RD_S|RD_t|I4 },
 552   /* start-sanitize-r5900 */
 553 {"movn.s",  "D,S,t",    0x46000013, 0xffe0003f, WR_D|RD_S|RD_t|X5 },
 554   /* end-sanitize-r5900 */
 555 {"movt",    "d,s,N",    0x00010001, 0xfc0307ff, WR_d|RD_s|RD_CC|I4 },
 556   /* start-sanitize-r5900 */
 557 {"movt",    "d,s,N",    0x00010001, 0xfc0307ff, WR_d|RD_s|RD_CC|X5 },
 558   /* end-sanitize-r5900 */
 559 {"movt.d",  "D,S,N",    0x46210011, 0xffe3003f, WR_D|RD_S|RD_CC|I4 },
 560 {"movt.s",  "D,S,N",    0x46010011, 0xffe3003f, WR_D|RD_S|RD_CC|I4 },
 561 {"movz",    "d,v,t",    0x0000000a, 0xfc0007ff, WR_d|RD_s|RD_t|I4 },
 562   /* start-sanitize-r5900 */
 563 {"movz",    "d,v,t",    0x0000000a, 0xfc0007ff, WR_d|RD_s|RD_t|A5 },
 564   /* end-sanitize-r5900 */
 565 {"ffs",     "d,v",      0x0000000a, 0xfc0007ff, WR_d|RD_s|L1    },
 566 {"movz.d",  "D,S,t",    0x46200012, 0xffe0003f, WR_D|RD_S|RD_t|I4 },
 567   /* start-sanitize-r5900 */
 568 {"movz.d",  "D,S,t",    0x46200012, 0xffe0003f, WR_D|RD_S|RD_t|X5 },
 569   /* end-sanitize-r5900 */
 570 {"movz.s",  "D,S,t",    0x46000012, 0xffe0003f, WR_D|RD_S|RD_t|I4 },
 571   /* start-sanitize-r5900 */
 572 {"movz.s",  "D,S,t",    0x46000012, 0xffe0003f, WR_D|RD_S|RD_t|X5 },
 573   /* end-sanitize-r5900 */
 574 /* move is at the top of the table.  */
 575 {"msub.d",  "D,R,S,T",  0x4c000029, 0xfc00003f, RD_R|RD_S|RD_T|WR_D|I4 },
 576   /* start-sanitize-r5900 */
 577 {"msub.d",  "D,R,S,T",  0x4c000029, 0xfc00003f, RD_R|RD_S|RD_T|WR_D|X5 },
 578   /* end-sanitize-r5900 */
 579 {"msub.s",  "D,R,S,T",  0x4c000028, 0xfc00003f, RD_R|RD_S|RD_T|WR_D|I4 },
 580   /* start-sanitize-r5900 */
 581 {"msub.s",  "D,R,S,T",  0x4c000028, 0xfc00003f, RD_R|RD_S|RD_T|WR_D|X5 },
 582   /* end-sanitize-r5900 */
 583 {"msub",    "s,t",      0x0000001e, 0xfc00ffff, RD_s|RD_t|WR_HI|WR_LO|L1 },
 584 {"msubu",   "s,t",      0x0000001f, 0xfc00ffff, RD_s|RD_t|WR_HI|WR_LO|L1 },
 585 {"mtc0",    "t,G",      0x40800000, 0xffe007ff, COD|RD_t|WR_C0|WR_CC    },
 586 {"mtc1",    "t,S",      0x44800000, 0xffe007ff, COD|RD_t|WR_S   },
 587 {"mtc1",    "t,G",      0x44800000, 0xffe007ff, COD|RD_t|WR_S   },
 588 {"mtc2",    "t,G",      0x48800000, 0xffe007ff, COD|RD_t|WR_C2|WR_CC    },
 589 {"mtc3",    "t,G",      0x4c800000, 0xffe007ff, COD|RD_t|WR_C3|WR_CC    },
 590 {"mthi",    "s",        0x00000011, 0xfc1fffff, RD_s|WR_HI      },
 591   /* start-sanitize-r5900 */
 592 {"mthi1",   "s",        0x70000011, 0xfc1fffff, RD_s|WR_HI|T5   },
 593   /* end-sanitize-r5900 */
 594 {"mtlo",    "s",        0x00000013, 0xfc1fffff, RD_s|WR_LO      },
 595   /* start-sanitize-r5900 */
 596 {"mtlo1",   "s",        0x70000013, 0xfc1fffff, RD_s|WR_LO|T5   },
 597 {"mtsa",    "s",        0x00000019, 0xfc1fffff, RD_s|T5         },
 598 {"mtsab",   "s,j",      0x04180000, 0xfc1f0000, RD_s|T5         },
 599 {"mtsah",   "s,j",      0x04190000, 0xfc1f0000, RD_s|T5         },
 600   /* end-sanitize-r5900 */
 601 {"mul.d",   "D,V,T",    0x46200002, 0xffe0003f, WR_D|RD_S|RD_T  },
 602 {"mul.s",   "D,V,T",    0x46000002, 0xffe0003f, WR_D|RD_S|RD_T  },
 603 {"mul",     "d,v,t",    0x70000002, 0xfc0007ff, WR_d|RD_s|RD_t|WR_HI|WR_LO|P3},
 604 {"mul",     "d,v,t",    0,    (int) M_MUL,      INSN_MACRO      },
 605 {"mul",     "d,v,I",    0,    (int) M_MUL_I,    INSN_MACRO      },
 606 {"mulo",    "d,v,t",    0,    (int) M_MULO,     INSN_MACRO      },
 607 {"mulo",    "d,v,I",    0,    (int) M_MULO_I,   INSN_MACRO      },
 608 {"mulou",   "d,v,t",    0,    (int) M_MULOU,    INSN_MACRO      },
 609 {"mulou",   "d,v,I",    0,    (int) M_MULOU_I,  INSN_MACRO      },
 610 {"mult",    "s,t",      0x00000018, 0xfc00ffff, RD_s|RD_t|WR_HI|WR_LO   },
 611 {"mult",    "d,s,t",    0x00000018, 0xfc0007ff, RD_s|RD_t|WR_HI|WR_LO|WR_d },
 612   /* start-sanitize-r5900 */
 613 {"mult1",   "d,s,t",    0x70000018, 0xfc0007ff, RD_s|RD_t|WR_HI|WR_LO|WR_d|T5},
 614   /* end-sanitize-r5900 */
 615 {"multu",   "s,t",      0x00000019, 0xfc00ffff, RD_s|RD_t|WR_HI|WR_LO   },
 616 {"multu",   "d,s,t",    0x00000019, 0xfc0007ff, RD_s|RD_t|WR_HI|WR_LO|WR_d },
 617   /* start-sanitize-r5900 */
 618 {"multu1",  "d,s,t",    0x70000019, 0xfc0007ff, RD_s|RD_t|WR_HI|WR_LO|WR_d|T5},
 619   /* end-sanitize-r5900 */
 620 {"neg",     "d,w",      0x00000022, 0xffe007ff, WR_d|RD_t       }, /* sub 0 */
 621 {"negu",    "d,w",      0x00000023, 0xffe007ff, WR_d|RD_t       }, /* subu 0 */
 622 {"neg.d",   "D,V",      0x46200007, 0xffff003f, WR_D|RD_S       },
 623 {"neg.s",   "D,V",      0x46000007, 0xffff003f, WR_D|RD_S       },
 624 {"nmadd.d", "D,R,S,T",  0x4c000031, 0xfc00003f, RD_R|RD_S|RD_T|WR_D|I4 },
 625 {"nmadd.s", "D,R,S,T",  0x4c000030, 0xfc00003f, RD_R|RD_S|RD_T|WR_D|I4 },
 626 {"nmsub.d", "D,R,S,T",  0x4c000039, 0xfc00003f, RD_R|RD_S|RD_T|WR_D|I4 },
 627   /* start-sanitize-r5900 */
 628 {"nmsub.d", "D,R,S,T",  0x4c000039, 0xfc00003f, RD_R|RD_S|RD_T|WR_D|X5 },
 629   /* end-sanitize-r5900 */
 630 {"nmsub.s", "D,R,S,T",  0x4c000038, 0xfc00003f, RD_R|RD_S|RD_T|WR_D|I4 },
 631   /* start-sanitize-r5900 */
 632 {"nmsub.s", "D,R,S,T",  0x4c000038, 0xfc00003f, RD_R|RD_S|RD_T|WR_D|X5 },
 633   /* end-sanitize-r5900 */
 634 /* nop is at the start of the table.  */
 635 {"nor",     "d,v,t",    0x00000027, 0xfc0007ff, WR_d|RD_s|RD_t  },
 636 {"nor",     "t,r,I",    0,    (int) M_NOR_I,    INSN_MACRO      },
 637 {"not",     "d,v",      0x00000027, 0xfc0007ff, WR_d|RD_s|RD_t  },/*nor d,s,0*/
 638 {"or",      "d,v,t",    0x00000025, 0xfc0007ff, WR_d|RD_s|RD_t  },
 639 {"or",      "t,r,I",    0,    (int) M_OR_I,     INSN_MACRO      },
 640 {"ori",     "t,r,i",    0x34000000, 0xfc000000, WR_t|RD_s       },
 641
 642   /* start-sanitize-r5900 */
 643 {"pabsh",   "d,t",      0x70000168, 0xffe007ff, WR_d|RD_t|T5    },
 644 {"pabsw",   "d,t",      0x70000068, 0xffe007ff, WR_d|RD_t|T5    },
 645 {"paddb",   "d,v,t",    0x70000208, 0xfc0007ff, WR_d|RD_s|RD_t|T5  },
 646 {"paddh",   "d,v,t",    0x70000108, 0xfc0007ff, WR_d|RD_s|RD_t|T5  },
 647 {"paddw",   "d,v,t",    0x70000008, 0xfc0007ff, WR_d|RD_s|RD_t|T5  },
 648 {"paddsb",  "d,v,t",    0x70000608, 0xfc0007ff, WR_d|RD_s|RD_t|T5  },
 649 {"paddsh",  "d,v,t",    0x70000508, 0xfc0007ff, WR_d|RD_s|RD_t|T5  },
 650 {"paddsw",  "d,v,t",    0x70000408, 0xfc0007ff, WR_d|RD_s|RD_t|T5  },
 651 {"paddub",  "d,v,t",    0x70000628, 0xfc0007ff, WR_d|RD_s|RD_t|T5  },
 652 {"padduh",  "d,v,t",    0x70000528, 0xfc0007ff, WR_d|RD_s|RD_t|T5  },
 653 {"padduw",  "d,v,t",    0x70000428, 0xfc0007ff, WR_d|RD_s|RD_t|T5  },
 654 {"padsbh",  "d,v,t",    0x70000128, 0xfc0007ff, WR_d|RD_s|RD_t|T5  },
 655 {"pand",    "d,v,t",    0x70000489, 0xfc0007ff, WR_d|RD_s|RD_t|T5  },
 656 {"pceqb",   "d,v,t",    0x700002a8, 0xfc0007ff, WR_d|RD_s|RD_t|T5  },
 657 {"pceqh",   "d,v,t",    0x700001a8, 0xfc0007ff, WR_d|RD_s|RD_t|T5  },
 658 {"pceqw",   "d,v,t",    0x700000a8, 0xfc0007ff, WR_d|RD_s|RD_t|T5  },
 659
 660 {"pcgtb",   "d,v,t",    0x70000288, 0xfc0007ff, WR_d|RD_s|RD_t|T5  },
 661 {"pcgth",   "d,v,t",    0x70000188, 0xfc0007ff, WR_d|RD_s|RD_t|T5  },
 662 {"pcgtw",   "d,v,t",    0x70000088, 0xfc0007ff, WR_d|RD_s|RD_t|T5  },
 663
 664 {"pcpyh",   "d,t",      0x700006e9, 0xffe007ff, WR_d|RD_t|T5    },
 665
 666 {"pcpyld",  "d,v,t",    0x70000389, 0xfc0007ff, WR_d|RD_s|RD_t|T5  },
 667 {"pcpyud",  "d,v,t",    0x700003a9, 0xfc0007ff, WR_d|RD_s|RD_t|T5  },
 668
 669 {"pdivbw",   "s,t",     0x70000749, 0xfc00ffff, RD_s|RD_t|WR_HI|WR_LO|T5},
 670 {"pdivuw",   "s,t",     0x70000369, 0xfc00ffff, RD_s|RD_t|WR_HI|WR_LO|T5},
 671 {"pdivw",    "s,t",     0x70000349, 0xfc00ffff, RD_s|RD_t|WR_HI|WR_LO|T5},
 672
 673 {"pexch",    "d,t",     0x700006a9, 0xffe007ff, WR_d|RD_t|T5    },
 674 {"pexcw",    "d,t",     0x700007a9, 0xffe007ff, WR_d|RD_t|T5    },
 675 {"pexoh",    "d,t",     0x70000689, 0xffe007ff, WR_d|RD_t|T5    },
 676 {"pexow",    "d,t",     0x70000789, 0xffe007ff, WR_d|RD_t|T5    },
 677
 678 {"pext5",    "d,t",     0x70000788, 0xffe007ff, WR_d|RD_t|T5    },
 679
 680 {"pextlb",   "d,v,t",   0x70000688, 0xfc0007ff, WR_d|RD_s|RD_t|T5 },
 681 {"pextlh",   "d,v,t",   0x70000588, 0xfc0007ff, WR_d|RD_s|RD_t|T5 },
 682 {"pextlw",   "d,v,t",   0x70000488, 0xfc0007ff, WR_d|RD_s|RD_t|T5 },
 683 {"pextub",   "d,v,t",   0x700006a8, 0xfc0007ff, WR_d|RD_s|RD_t|T5 },
 684 {"pextuh",   "d,v,t",   0x700005a8, 0xfc0007ff, WR_d|RD_s|RD_t|T5 },
 685 {"pextuw",   "d,v,t",   0x700004a8, 0xfc0007ff, WR_d|RD_s|RD_t|T5 },
 686
 687 {"phmaddh",  "d,v,t",   0x70000449, 0xfc0007ff,WR_d|RD_s|RD_t|WR_HI|WR_LO|T5 },
 688 {"phmsubh",  "d,v,t",   0x70000549, 0xfc0007ff,WR_d|RD_s|RD_t|WR_HI|WR_LO|T5 },
 689
 690 {"pinth",    "d,v,t",   0x70000289, 0xfc0007ff, WR_d|RD_s|RD_t|T5 },
 691 {"pintoh",   "d,v,t",   0x700002a9, 0xfc0007ff, WR_d|RD_s|RD_t|T5 },
 692
 693 {"plzcw",    "d,v",     0x70000004, 0xfc1f07ff, WR_d|RD_s|T5 },
 694
 695 {"pmaddh",   "d,v,t",   0x70000409, 0xfc0007ff,WR_d|RD_s|RD_t|WR_HI|WR_LO|T5 },
 696 {"pmadduw",  "d,v,t",   0x70000029, 0xfc0007ff,WR_d|RD_s|RD_t|WR_HI|WR_LO|T5 },
 697 {"pmaddw",   "d,v,t",   0x70000009, 0xfc0007ff,WR_d|RD_s|RD_t|WR_HI|WR_LO|T5 },
 698
 699 {"pmaxh",    "d,v,t",   0x700001c8, 0xfc0007ff, WR_d|RD_s|RD_t|T5 },
 700 {"pmaxw",    "d,v,t",   0x700000c8, 0xfc0007ff, WR_d|RD_s|RD_t|T5 },
 701
 702 {"pmfhi",    "d",       0x70000209, 0xffff07ff, WR_d|RD_HI|T5 },
 703 {"pmflo",    "d",       0x70000249, 0xffff07ff, WR_d|RD_LO|T5 },
 704
 705 {"pmfhl.lw", "d",       0x70000030, 0xffff07ff, WR_d|RD_LO|RD_HI|T5 },
 706 {"pmfhl.uw", "d",       0x70000070, 0xffff07ff, WR_d|RD_LO|RD_HI|T5 },
 707 {"pmfhl.slw","d",       0x700000b0, 0xffff07ff, WR_d|RD_LO|RD_HI|T5 },
 708 {"pmfhl.lh", "d",       0x700000f0, 0xffff07ff, WR_d|RD_LO|RD_HI|T5 },
 709 {"pmfhl.sh", "d",       0x70000130, 0xffff07ff, WR_d|RD_LO|RD_HI|T5 },
 710
 711 {"pminh",    "d,v,t",   0x700001e8, 0xfc0007ff, WR_d|RD_s|RD_t|T5 },
 712 {"pminw",    "d,v,t",   0x700000e8, 0xfc0007ff, WR_d|RD_s|RD_t|T5 },
 713
 714 {"pmsubh",   "d,v,t",   0x70000509, 0xfc0007ff,WR_d|RD_s|RD_t|WR_HI|WR_LO|T5 },
 715 {"pmsubw",   "d,v,t",   0x70000109, 0xfc0007ff,WR_d|RD_s|RD_t|WR_HI|WR_LO|T5 },
 716
 717 {"pmthi",    "v",       0x70000229, 0xfc1fffff, WR_HI|RD_s|T5 },
 718 {"pmtlo",    "v",       0x70000269, 0xfc1fffff, WR_LO|RD_s|T5 },
 719
 720 {"pmthl.lw", "v",       0x70000031, 0xfc1fffff, WR_HI|WR_LO|RD_s|T5 },
 721
 722 {"pmulth",   "d,v,t",   0x70000709, 0xfc0007ff,WR_d|RD_s|RD_t|WR_HI|WR_LO|T5 },
 723 {"pmultuw",  "d,v,t",   0x70000329, 0xfc0007ff,WR_d|RD_s|RD_t|WR_HI|WR_LO|T5 },
 724 {"pmultw",   "d,v,t",   0x70000309, 0xfc0007ff,WR_d|RD_s|RD_t|WR_HI|WR_LO|T5 },
 725
 726 {"pnor",    "d,v,t",    0x700004e9, 0xfc0007ff, WR_d|RD_s|RD_t|T5  },
 727 {"por",     "d,v,t",    0x700004a9, 0xfc0007ff, WR_d|RD_s|RD_t|T5  },
 728
 729 {"ppac5",   "d,t",      0x700007c8, 0xffe007ff, WR_d|RD_t|T5    },
 730
 731 {"ppacb",   "d,v,t",    0x700006c8, 0xfc0007ff, WR_d|RD_s|RD_t|T5  },
 732 {"ppach",   "d,v,t",    0x700005c8, 0xfc0007ff, WR_d|RD_s|RD_t|T5  },
 733 {"ppacw",   "d,v,t",    0x700004c8, 0xfc0007ff, WR_d|RD_s|RD_t|T5  },
 734
 735 {"prevh",   "d,t",      0x700006c9, 0xffe007ff, WR_d|RD_t|T5    },
 736 {"prot3w",  "d,t",      0x700007c9, 0xffe007ff, WR_d|RD_t|T5    },
 737
 738 {"psllh",  "d,t,<",     0x70000034, 0xffe0003f, WR_d|RD_t|T5    },
 739 {"psllvw", "d,t,s",     0x70000089, 0xfc0007ff, WR_d|RD_t|RD_s|T5 },
 740 {"psllw",  "d,t,<",     0x7000003c, 0xffe0003f, WR_d|RD_t|T5    },
 741
 742 {"psrah",  "d,t,<",     0x70000037, 0xffe0003f, WR_d|RD_t|T5    },
 743 {"psravw", "d,t,s",     0x700000e9, 0xfc0007ff, WR_d|RD_t|RD_s|T5 },
 744 {"psraw",  "d,t,<",     0x7000003f, 0xffe0003f, WR_d|RD_t|T5    },
 745
 746 {"psrlh",  "d,t,<",     0x70000036, 0xffe0003f, WR_d|RD_t|T5    },
 747 {"psrlvw", "d,t,s",     0x700000c9, 0xfc0007ff, WR_d|RD_t|RD_s|T5 },
 748 {"psrlw",  "d,t,<",     0x7000003e, 0xffe0003f, WR_d|RD_t|T5    },
 749
 750 {"psubb",  "d,v,t",     0x70000248, 0xfc0007ff, WR_d|RD_s|RD_t|T5  },
 751 {"psubh",  "d,v,t",     0x70000148, 0xfc0007ff, WR_d|RD_s|RD_t|T5  },
 752 {"psubsb", "d,v,t",     0x70000648, 0xfc0007ff, WR_d|RD_s|RD_t|T5  },
 753 {"psubsh", "d,v,t",     0x70000548, 0xfc0007ff, WR_d|RD_s|RD_t|T5  },
 754 {"psubsw", "d,v,t",     0x70000448, 0xfc0007ff, WR_d|RD_s|RD_t|T5  },
 755 {"psubub", "d,v,t",     0x70000668, 0xfc0007ff, WR_d|RD_s|RD_t|T5  },
 756 {"psubuh", "d,v,t",     0x70000568, 0xfc0007ff, WR_d|RD_s|RD_t|T5  },
 757 {"psubuw", "d,v,t",     0x70000468, 0xfc0007ff, WR_d|RD_s|RD_t|T5  },
 758 {"psubw",  "d,v,t",     0x70000048, 0xfc0007ff, WR_d|RD_s|RD_t|T5  },
 759
 760 {"pxor",   "d,v,t",     0x700004c9, 0xfc0007ff, WR_d|RD_s|RD_t|T5  },
 761   /* end-sanitize-r5900 */
 762
 763 {"pref",    "k,o(b)",   0xcc000000, 0xfc000000, RD_b|I4         },
 764 {"prefx",   "h,t(b)",   0x4c00000f, 0xfc0007ff, RD_b|RD_t|I4    },
 765
 766   /* start-sanitize-r5900 */
 767 {"qfsrv",   "d,v,t",    0x700006e8, 0xfc0007ff, WR_d|RD_s|RD_t|T5  },
 768   /* end-sanitize-r5900 */
 769
 770 {"recip.d", "D,S",      0x46200015, 0xffff003f, WR_D|RD_S|I4    },
 771 {"recip.s", "D,S",      0x46000015, 0xffff003f, WR_D|RD_S|I4    },
 772 {"rem",     "z,s,t",    0x0000001a, 0xfc00ffff, RD_s|RD_t|WR_HI|WR_LO },
 773 {"rem",     "d,v,t",    0,    (int) M_REM_3,    INSN_MACRO      },
 774 {"rem",     "d,v,I",    0,    (int) M_REM_3I,   INSN_MACRO      },
 775 {"remu",    "z,s,t",    0x0000001b, 0xfc00ffff, RD_s|RD_t|WR_HI|WR_LO },
 776 {"remu",    "d,v,t",    0,    (int) M_REMU_3,   INSN_MACRO      },
 777 {"remu",    "d,v,I",    0,    (int) M_REMU_3I,  INSN_MACRO      },
 778 {"rfe",     "",         0x42000010, 0xffffffff, 0               },
 779 {"rol",     "d,v,t",    0,    (int) M_ROL,      INSN_MACRO      },
 780 {"rol",     "d,v,I",    0,    (int) M_ROL_I,    INSN_MACRO      },
 781 {"ror",     "d,v,t",    0,    (int) M_ROR,      INSN_MACRO      },
 782 {"ror",     "d,v,I",    0,    (int) M_ROR_I,    INSN_MACRO      },
 783 {"round.l.d", "D,S",    0x46200008, 0xffff003f, WR_D|RD_S|I3    },
 784 {"round.l.s", "D,S",    0x46000008, 0xffff003f, WR_D|RD_S|I3    },
 785 {"round.w.d", "D,S",    0x4620000c, 0xffff003f, WR_D|RD_S|I2    },
 786 {"round.w.s", "D,S",    0x4600000c, 0xffff003f, WR_D|RD_S|I2    },
 787 {"rsqrt.d", "D,S",      0x46200016, 0xffff003f, WR_D|RD_S|I4    },
 788 {"rsqrt.s", "D,S",      0x46000016, 0xffff003f, WR_D|RD_S|I4    },
 789 {"sb",      "t,o(b)",   0xa0000000, 0xfc000000, SM|RD_t|RD_b    },
 790 {"sb",      "t,A(b)",   0,    (int) M_SB_AB,    INSN_MACRO      },
 791 {"sc",      "t,o(b)",   0xe0000000, 0xfc000000, SM|RD_t|WR_t|RD_b|I2 },
 792 {"sc",      "t,A(b)",   2,    (int) M_SC_AB,    INSN_MACRO      },
 793 {"scd",     "t,o(b)",   0xf0000000, 0xfc000000, SM|RD_t|WR_t|RD_b|I3 },
 794 {"scd",     "t,A(b)",   3,    (int) M_SCD_AB,   INSN_MACRO      },
 795 {"sd",      "t,o(b)",   0xfc000000, 0xfc000000, SM|RD_t|RD_b|I3 },
 796 {"sd",      "t,o(b)",   0,    (int) M_SD_OB,    INSN_MACRO      },
 797 {"sd",      "t,A(b)",   0,    (int) M_SD_AB,    INSN_MACRO      },
 798 {"sdc1",    "T,o(b)",   0xf4000000, 0xfc000000, SM|RD_T|RD_b|I2 },
 799 {"sdc1",    "E,o(b)",   0xf4000000, 0xfc000000, SM|RD_T|RD_b|I2 },
 800 {"sdc1",    "T,A(b)",   2,    (int) M_SDC1_AB,  INSN_MACRO      },
 801 {"sdc1",    "E,A(b)",   2,    (int) M_SDC1_AB,  INSN_MACRO      },
 802 {"sdc2",    "E,o(b)",   0xf8000000, 0xfc000000, SM|RD_C2|RD_b|I2 },
 803 {"sdc2",    "E,A(b)",   2,    (int) M_SDC2_AB,  INSN_MACRO      },
 804 {"sdc3",    "E,o(b)",   0xfc000000, 0xfc000000, SM|RD_C3|RD_b|I2 },
 805 {"sdc3",    "E,A(b)",   2,    (int) M_SDC3_AB,  INSN_MACRO      },
 806 {"s.d",     "T,o(b)",   0xf4000000, 0xfc000000, SM|RD_T|RD_b|I2 },
 807 {"s.d",     "T,o(b)",   0,    (int) M_S_DOB,    INSN_MACRO      },
 808 {"s.d",     "T,A(b)",   0,    (int) M_S_DAB,    INSN_MACRO      },
 809 {"sdl",     "t,o(b)",   0xb0000000, 0xfc000000, SM|RD_t|RD_b|I3 },
 810 {"sdl",     "t,A(b)",   3,    (int) M_SDL_AB,   INSN_MACRO      },
 811 {"sdr",     "t,o(b)",   0xb4000000, 0xfc000000, SM|RD_t|RD_b|I3 },
 812 {"sdr",     "t,A(b)",   3,    (int) M_SDR_AB,   INSN_MACRO      },
 813 {"sdxc1",   "S,t(b)",   0x4c000009, 0xfc0007ff, SM|RD_S|RD_t|RD_b|I4 },
 814   /* start-sanitize-r5900 */
 815 {"sdxc1",   "S,t(b)",   0x4c000009, 0xfc0007ff, SM|RD_S|RD_t|RD_b|X5 },
 816   /* end-sanitize-r5900 */
 817 {"selsl",   "d,v,t",    0x00000005, 0xfc0007ff, WR_d|RD_s|RD_t|L1 },
 818 {"selsr",   "d,v,t",    0x00000001, 0xfc0007ff, WR_d|RD_s|RD_t|L1 },
 819 {"seq",     "d,v,t",    0,    (int) M_SEQ,      INSN_MACRO      },
 820 {"seq",     "d,v,I",    0,    (int) M_SEQ_I,    INSN_MACRO      },
 821 {"sge",     "d,v,t",    0,    (int) M_SGE,      INSN_MACRO      },
 822 {"sge",     "d,v,I",    0,    (int) M_SGE_I,    INSN_MACRO      },
 823 {"sgeu",    "d,v,t",    0,    (int) M_SGEU,     INSN_MACRO      },
 824 {"sgeu",    "d,v,I",    0,    (int) M_SGEU_I,   INSN_MACRO      },
 825 {"sgt",     "d,v,t",    0,    (int) M_SGT,      INSN_MACRO      },
 826 {"sgt",     "d,v,I",    0,    (int) M_SGT_I,    INSN_MACRO      },
 827 {"sgtu",    "d,v,t",    0,    (int) M_SGTU,     INSN_MACRO      },
 828 {"sgtu",    "d,v,I",    0,    (int) M_SGTU_I,   INSN_MACRO      },
 829 {"sh",      "t,o(b)",   0xa4000000, 0xfc000000, SM|RD_t|RD_b    },
 830 {"sh",      "t,A(b)",   0,    (int) M_SH_AB,    INSN_MACRO      },
 831 {"sle",     "d,v,t",    0,    (int) M_SLE,      INSN_MACRO      },
 832 {"sle",     "d,v,I",    0,    (int) M_SLE_I,    INSN_MACRO      },
 833 {"sleu",    "d,v,t",    0,    (int) M_SLEU,     INSN_MACRO      },
 834 {"sleu",    "d,v,I",    0,    (int) M_SLEU_I,   INSN_MACRO      },
 835 {"sllv",    "d,t,s",    0x00000004, 0xfc0007ff, WR_d|RD_t|RD_s  },
 836 {"sll",     "d,w,s",    0x00000004, 0xfc0007ff, WR_d|RD_t|RD_s  }, /* sllv */
 837 {"sll",     "d,w,<",    0x00000000, 0xffe0003f, WR_d|RD_t       },
 838 {"slt",     "d,v,t",    0x0000002a, 0xfc0007ff, WR_d|RD_s|RD_t  },
 839 {"slt",     "d,v,I",    0,    (int) M_SLT_I,    INSN_MACRO      },
 840 {"slti",    "t,r,j",    0x28000000, 0xfc000000, WR_t|RD_s       },
 841 {"sltiu",   "t,r,j",    0x2c000000, 0xfc000000, WR_t|RD_s       },
 842 {"sltu",    "d,v,t",    0x0000002b, 0xfc0007ff, WR_d|RD_s|RD_t  },
 843 {"sltu",    "d,v,I",    0,    (int) M_SLTU_I,   INSN_MACRO      },
 844 {"sne",     "d,v,t",    0,    (int) M_SNE,      INSN_MACRO      },
 845 {"sne",     "d,v,I",    0,    (int) M_SNE_I,    INSN_MACRO      },
 846   /* start-sanitize-r5900 */
 847 {"sq",      "t,o(b)",   0x7c000000, 0xfc000000, SM|RD_t|RD_b|T5 },
 848   /* end-sanitize-r5900 */
 849 {"sqrt.d",  "D,S",      0x46200004, 0xffff003f, WR_D|RD_S|I2    },
 850 {"sqrt.s",  "D,S",      0x46000004, 0xffff003f, WR_D|RD_S|I2    },
 851 {"srav",    "d,t,s",    0x00000007, 0xfc0007ff, WR_d|RD_t|RD_s  },
 852 {"sra",     "d,w,s",    0x00000007, 0xfc0007ff, WR_d|RD_t|RD_s  }, /* srav */
 853 {"sra",     "d,w,<",    0x00000003, 0xffe0003f, WR_d|RD_t       },
 854 {"srlv",    "d,t,s",    0x00000006, 0xfc0007ff, WR_d|RD_t|RD_s  },
 855 {"srl",     "d,w,s",    0x00000006, 0xfc0007ff, WR_d|RD_t|RD_s  }, /* srlv */
 856 {"srl",     "d,w,<",    0x00000002, 0xffe0003f, WR_d|RD_t       },
 857 {"standby", "",         0x42000021, 0xffffffff, V1              },
 858 {"sub",     "d,v,t",    0x00000022, 0xfc0007ff, WR_d|RD_s|RD_t  },
 859 {"sub",     "d,v,I",    0,    (int) M_SUB_I,    INSN_MACRO      },
 860 {"sub.d",   "D,V,T",    0x46200001, 0xffe0003f, WR_D|RD_S|RD_T  },
 861 {"sub.s",   "D,V,T",    0x46000001, 0xffe0003f, WR_D|RD_S|RD_T  },
 862 {"subu",    "d,v,t",    0x00000023, 0xfc0007ff, WR_d|RD_s|RD_t  },
 863 {"subu",    "d,v,I",    0,    (int) M_SUBU_I,   INSN_MACRO      },
 864 {"suspend", "",         0x42000022, 0xffffffff, V1              },
 865 {"sw",      "t,o(b)",   0xac000000, 0xfc000000, SM|RD_t|RD_b    },
 866 {"sw",      "t,A(b)",   0,    (int) M_SW_AB,    INSN_MACRO      },
 867 {"swc0",    "E,o(b)",   0xe0000000, 0xfc000000, SM|RD_C0|RD_b   },
 868 {"swc0",    "E,A(b)",   0,    (int) M_SWC0_AB,  INSN_MACRO      },
 869 {"swc1",    "T,o(b)",   0xe4000000, 0xfc000000, SM|RD_T|RD_b    },
 870 {"swc1",    "E,o(b)",   0xe4000000, 0xfc000000, SM|RD_T|RD_b    },
 871 {"swc1",    "T,A(b)",   0,    (int) M_SWC1_AB,  INSN_MACRO      },
 872 {"swc1",    "E,A(b)",   0,    (int) M_SWC1_AB,  INSN_MACRO      },
 873 {"s.s",     "T,o(b)",   0xe4000000, 0xfc000000, SM|RD_T|RD_b    }, /* swc1 */
 874 {"s.s",     "T,A(b)",   0,    (int) M_SWC1_AB,  INSN_MACRO      },
 875 {"swc2",    "E,o(b)",   0xe8000000, 0xfc000000, SM|RD_C2|RD_b   },
 876 {"swc2",    "E,A(b)",   0,    (int) M_SWC2_AB,  INSN_MACRO      },
 877 {"swc3",    "E,o(b)",   0xec000000, 0xfc000000, SM|RD_C3|RD_b   },
 878 {"swc3",    "E,A(b)",   0,    (int) M_SWC3_AB,  INSN_MACRO      },
 879 {"swl",     "t,o(b)",   0xa8000000, 0xfc000000, SM|RD_t|RD_b    },
 880 {"swl",     "t,A(b)",   0,    (int) M_SWL_AB,   INSN_MACRO      },
 881 {"scache",  "t,o(b)",   0xa8000000, 0xfc000000, RD_t|RD_b|I2    }, /* same */
 882 {"scache",  "t,A(b)",   2,    (int) M_SWL_AB,   INSN_MACRO      }, /* as swl */
 883 {"swr",     "t,o(b)",   0xb8000000, 0xfc000000, SM|RD_t|RD_b    },
 884 {"swr",     "t,A(b)",   0,    (int) M_SWR_AB,   INSN_MACRO      },
 885 {"invalidate", "t,o(b)",0xb8000000, 0xfc000000, RD_t|RD_b|I2    }, /* same */
 886 {"invalidate", "t,A(b)",2,    (int) M_SWR_AB,   INSN_MACRO      }, /* as swr */
 887 {"swxc1",   "S,t(b)",   0x4c000008, 0xfc0007ff, SM|RD_S|RD_t|RD_b|I4 },
 888   /* start-sanitize-r5900 */
 889 {"swxc1",   "S,t(b)",   0x4c000008, 0xfc0007ff, SM|RD_S|RD_t|RD_b|X5 },
 890   /* end-sanitize-r5900 */
 891 {"sync",    "",         0x0000000f, 0xffffffff, I2              },
 892 {"syscall", "",         0x0000000c, 0xffffffff, TRAP            },
 893 {"syscall", "B",        0x0000000c, 0xfc00003f, TRAP            },
 894 {"teqi",    "s,j",      0x040c0000, 0xfc1f0000, RD_s|I2|TRAP    },
 895 {"teq",     "s,t",      0x00000034, 0xfc00003f, RD_s|RD_t|I2|TRAP },
 896 {"teq",     "s,j",      0x040c0000, 0xfc1f0000, RD_s|I2|TRAP    }, /* teqi */
 897 {"teq",     "s,I",      2,    (int) M_TEQ_I,    INSN_MACRO      },
 898 {"tgei",    "s,j",      0x04080000, 0xfc1f0000, RD_s|I2|TRAP    },
 899 {"tge",     "s,t",      0x00000030, 0xfc00003f, RD_s|RD_t|I2|TRAP },
 900 {"tge",     "s,j",      0x04080000, 0xfc1f0000, RD_s|I2|TRAP    }, /* tgei */
 901 {"tge",     "s,I",      2,    (int) M_TGE_I,    INSN_MACRO      },
 902 {"tgeiu",   "s,j",      0x04090000, 0xfc1f0000, RD_s|I2|TRAP    },
 903 {"tgeu",    "s,t",      0x00000031, 0xfc00003f, RD_s|RD_t|I2|TRAP },
 904 {"tgeu",    "s,j",      0x04090000, 0xfc1f0000, RD_s|I2|TRAP    }, /* tgeiu */
 905 {"tgeu",    "s,I",      2,    (int) M_TGEU_I,   INSN_MACRO      },
 906 {"tlbp",    "",         0x42000008, 0xffffffff, INSN_TLB        },
 907 {"tlbr",    "",         0x42000001, 0xffffffff, INSN_TLB        },
 908 {"tlbwi",   "",         0x42000002, 0xffffffff, INSN_TLB        },
 909 {"tlbwr",   "",         0x42000006, 0xffffffff, INSN_TLB        },
 910 {"tlti",    "s,j",      0x040a0000, 0xfc1f0000, RD_s|I2|TRAP    },
 911 {"tlt",     "s,t",      0x00000032, 0xfc00003f, RD_s|RD_t|I2|TRAP },
 912 {"tlt",     "s,j",      0x040a0000, 0xfc1f0000, RD_s|I2|TRAP    }, /* tlti */
 913 {"tlt",     "s,I",      2,    (int) M_TLT_I,    INSN_MACRO      },
 914 {"tltiu",   "s,j",      0x040b0000, 0xfc1f0000, RD_s|I2|TRAP    },
 915 {"tltu",    "s,t",      0x00000033, 0xfc00003f, RD_s|RD_t|I2|TRAP },
 916 {"tltu",    "s,j",      0x040b0000, 0xfc1f0000, RD_s|I2|TRAP    }, /* tltiu */
 917 {"tltu",    "s,I",      2,    (int) M_TLTU_I,   INSN_MACRO      },
 918 {"tnei",    "s,j",      0x040e0000, 0xfc1f0000, RD_s|I2|TRAP    },
 919 {"tne",     "s,t",      0x00000036, 0xfc00003f, RD_s|RD_t|I2|TRAP },
 920 {"tne",     "s,j",      0x040e0000, 0xfc1f0000, RD_s|I2|TRAP    }, /* tnei */
 921 {"tne",     "s,I",      2,    (int) M_TNE_I,    INSN_MACRO      },
 922 {"trunc.l.d", "D,S",    0x46200009, 0xffff003f, WR_D|RD_S|I3    },
 923 {"trunc.l.s", "D,S",    0x46000009, 0xffff003f, WR_D|RD_S|I3    },
 924 {"trunc.w.d", "D,S",    0x4620000d, 0xffff003f, WR_D|RD_S|I2    },
 925 {"trunc.w.d", "D,S,x",  0x4620000d, 0xffff003f, WR_D|RD_S|I2    },
 926 {"trunc.w.d", "D,S,t",  0,    (int) M_TRUNCWD,  INSN_MACRO      },
 927 {"trunc.w.s", "D,S",    0x4600000d, 0xffff003f, WR_D|RD_S|I2    },
 928 {"trunc.w.s", "D,S,x",  0x4600000d, 0xffff003f, WR_D|RD_S|I2    },
 929 {"trunc.w.s", "D,S,t",  0,    (int) M_TRUNCWS,  INSN_MACRO      },
 930 {"uld",     "t,o(b)",   3,    (int) M_ULD,      INSN_MACRO      },
 931 {"uld",     "t,A(b)",   3,    (int) M_ULD_A,    INSN_MACRO      },
 932 {"ulh",     "t,o(b)",   0,    (int) M_ULH,      INSN_MACRO      },
 933 {"ulh",     "t,A(b)",   0,    (int) M_ULH_A,    INSN_MACRO      },
 934 {"ulhu",    "t,o(b)",   0,    (int) M_ULHU,     INSN_MACRO      },
 935 {"ulhu",    "t,A(b)",   0,    (int) M_ULHU_A,   INSN_MACRO      },
 936 {"ulw",     "t,o(b)",   0,    (int) M_ULW,      INSN_MACRO      },
 937 {"ulw",     "t,A(b)",   0,    (int) M_ULW_A,    INSN_MACRO      },
 938 {"usd",     "t,o(b)",   3,    (int) M_USD,      INSN_MACRO      },
 939 {"usd",     "t,A(b)",   3,    (int) M_USD_A,    INSN_MACRO      },
 940 {"ush",     "t,o(b)",   0,    (int) M_USH,      INSN_MACRO      },
 941 {"ush",     "t,A(b)",   0,    (int) M_USH_A,    INSN_MACRO      },
 942 {"usw",     "t,o(b)",   0,    (int) M_USW,      INSN_MACRO      },
 943 {"usw",     "t,A(b)",   0,    (int) M_USW_A,    INSN_MACRO      },
 944 {"xor",     "d,v,t",    0x00000026, 0xfc0007ff, WR_d|RD_s|RD_t  },
 945 {"xor",     "t,r,I",    0,    (int) M_XOR_I,    INSN_MACRO      },
 946 {"xori",    "t,r,i",    0x38000000, 0xfc000000, WR_t|RD_s       },
 947 {"waiti",   "",         0x42000020, 0xffffffff, TRAP|L1         },
 948 {"wb",      "o(b)",     0xbc040000, 0xfc1f0000, SM|RD_b|L1      },
 949 /* No hazard protection on coprocessor instructions--they shouldn't
 950    change the state of the processor and if they do it's up to the
 951    user to put in nops as necessary.  These are at the end so that the
 952    disasembler recognizes more specific versions first.  */
 953 {"c0",      "C",        0x42000000, 0xfe000000, 0               },
 954 {"c1",      "C",        0x46000000, 0xfe000000, 0               },
 955 {"c2",      "C",        0x4a000000, 0xfe000000, 0               },
 956 {"c3",      "C",        0x4e000000, 0xfe000000, 0               },
 957 {"cop0",     "C",       0,    (int) M_COP0,         INSN_MACRO  },
 958 {"cop1",     "C",       0,    (int) M_COP1,         INSN_MACRO  },
 959 {"cop2",     "C",       0,    (int) M_COP2,         INSN_MACRO  },
 960 {"cop3",     "C",       0,    (int) M_COP3,         INSN_MACRO  },
 961 };
 962
 963 /* const removed from definition to allow for dynamic extensions to the
 964  * built-in instruction set. */
 965 const int bfd_mips_num_builtin_opcodes =
 966   ((sizeof mips_builtin_opcodes) / (sizeof (mips_builtin_opcodes[0])));
 967
 968 struct mips_opcode *mips_opcodes = 0;
 969 int bfd_mips_num_opcodes = 0;