1 /* Print mips instructions for GDB, the GNU debugger, or for objdump.
2 Copyright 1989, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999,
3 2000, 2001, 2002, 2003, 2005, 2007, 2008
4 Free Software Foundation, Inc.
5 Contributed by Nobuyuki Hikichi(hikichi@sra.co.jp).
7 This file is part of the GNU opcodes library.
9 This library is free software; you can redistribute it and/or modify
10 it under the terms of the GNU General Public License as published by
11 the Free Software Foundation; either version 3, or (at your option)
14 It is distributed in the hope that it will be useful, but WITHOUT
15 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
16 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
17 License for more details.
19 You should have received a copy of the GNU General Public License
20 along with this program; if not, write to the Free Software
21 Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
22 MA 02110-1301, USA. */
26 #include "libiberty.h"
27 #include "opcode/mips.h"
30 /* FIXME: These are needed to figure out if the code is mips16 or
31 not. The low bit of the address is often a good indicator. No
32 symbol table is available when this code runs out in an embedded
33 system as when it is used for disassembler support in a monitor. */
35 #if !defined(EMBEDDED_ENV)
36 #define SYMTAB_AVAILABLE 1
41 /* Mips instructions are at maximum this many bytes long. */
45 /* FIXME: These should be shared with gdb somehow. */
47 struct mips_cp0sel_name
51 const char * const name;
54 /* The mips16 registers. */
55 static const unsigned int mips16_to_32_reg_map[] =
57 16, 17, 2, 3, 4, 5, 6, 7
60 #define mips16_reg_names(rn) mips_gpr_names[mips16_to_32_reg_map[rn]]
63 static const char * const mips_gpr_names_numeric[32] =
65 "$0", "$1", "$2", "$3", "$4", "$5", "$6", "$7",
66 "$8", "$9", "$10", "$11", "$12", "$13", "$14", "$15",
67 "$16", "$17", "$18", "$19", "$20", "$21", "$22", "$23",
68 "$24", "$25", "$26", "$27", "$28", "$29", "$30", "$31"
71 static const char * const mips_gpr_names_oldabi[32] =
73 "zero", "at", "v0", "v1", "a0", "a1", "a2", "a3",
74 "t0", "t1", "t2", "t3", "t4", "t5", "t6", "t7",
75 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7",
76 "t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra"
79 static const char * const mips_gpr_names_newabi[32] =
81 "zero", "at", "v0", "v1", "a0", "a1", "a2", "a3",
82 "a4", "a5", "a6", "a7", "t0", "t1", "t2", "t3",
83 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7",
84 "t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra"
87 static const char * const mips_fpr_names_numeric[32] =
89 "$f0", "$f1", "$f2", "$f3", "$f4", "$f5", "$f6", "$f7",
90 "$f8", "$f9", "$f10", "$f11", "$f12", "$f13", "$f14", "$f15",
91 "$f16", "$f17", "$f18", "$f19", "$f20", "$f21", "$f22", "$f23",
92 "$f24", "$f25", "$f26", "$f27", "$f28", "$f29", "$f30", "$f31"
95 static const char * const mips_fpr_names_32[32] =
97 "fv0", "fv0f", "fv1", "fv1f", "ft0", "ft0f", "ft1", "ft1f",
98 "ft2", "ft2f", "ft3", "ft3f", "fa0", "fa0f", "fa1", "fa1f",
99 "ft4", "ft4f", "ft5", "ft5f", "fs0", "fs0f", "fs1", "fs1f",
100 "fs2", "fs2f", "fs3", "fs3f", "fs4", "fs4f", "fs5", "fs5f"
103 static const char * const mips_fpr_names_n32[32] =
105 "fv0", "ft14", "fv1", "ft15", "ft0", "ft1", "ft2", "ft3",
106 "ft4", "ft5", "ft6", "ft7", "fa0", "fa1", "fa2", "fa3",
107 "fa4", "fa5", "fa6", "fa7", "fs0", "ft8", "fs1", "ft9",
108 "fs2", "ft10", "fs3", "ft11", "fs4", "ft12", "fs5", "ft13"
111 static const char * const mips_fpr_names_64[32] =
113 "fv0", "ft12", "fv1", "ft13", "ft0", "ft1", "ft2", "ft3",
114 "ft4", "ft5", "ft6", "ft7", "fa0", "fa1", "fa2", "fa3",
115 "fa4", "fa5", "fa6", "fa7", "ft8", "ft9", "ft10", "ft11",
116 "fs0", "fs1", "fs2", "fs3", "fs4", "fs5", "fs6", "fs7"
119 static const char * const mips_cp0_names_numeric[32] =
121 "$0", "$1", "$2", "$3", "$4", "$5", "$6", "$7",
122 "$8", "$9", "$10", "$11", "$12", "$13", "$14", "$15",
123 "$16", "$17", "$18", "$19", "$20", "$21", "$22", "$23",
124 "$24", "$25", "$26", "$27", "$28", "$29", "$30", "$31"
127 static const char * const mips_cp0_names_r3000[32] =
129 "c0_index", "c0_random", "c0_entrylo", "$3",
130 "c0_context", "$5", "$6", "$7",
131 "c0_badvaddr", "$9", "c0_entryhi", "$11",
132 "c0_sr", "c0_cause", "c0_epc", "c0_prid",
133 "$16", "$17", "$18", "$19",
134 "$20", "$21", "$22", "$23",
135 "$24", "$25", "$26", "$27",
136 "$28", "$29", "$30", "$31",
139 static const char * const mips_cp0_names_r4000[32] =
141 "c0_index", "c0_random", "c0_entrylo0", "c0_entrylo1",
142 "c0_context", "c0_pagemask", "c0_wired", "$7",
143 "c0_badvaddr", "c0_count", "c0_entryhi", "c0_compare",
144 "c0_sr", "c0_cause", "c0_epc", "c0_prid",
145 "c0_config", "c0_lladdr", "c0_watchlo", "c0_watchhi",
146 "c0_xcontext", "$21", "$22", "$23",
147 "$24", "$25", "c0_ecc", "c0_cacheerr",
148 "c0_taglo", "c0_taghi", "c0_errorepc", "$31",
151 static const char * const mips_cp0_names_mips3264[32] =
153 "c0_index", "c0_random", "c0_entrylo0", "c0_entrylo1",
154 "c0_context", "c0_pagemask", "c0_wired", "$7",
155 "c0_badvaddr", "c0_count", "c0_entryhi", "c0_compare",
156 "c0_status", "c0_cause", "c0_epc", "c0_prid",
157 "c0_config", "c0_lladdr", "c0_watchlo", "c0_watchhi",
158 "c0_xcontext", "$21", "$22", "c0_debug",
159 "c0_depc", "c0_perfcnt", "c0_errctl", "c0_cacheerr",
160 "c0_taglo", "c0_taghi", "c0_errorepc", "c0_desave",
163 static const struct mips_cp0sel_name mips_cp0sel_names_mips3264[] =
165 { 16, 1, "c0_config1" },
166 { 16, 2, "c0_config2" },
167 { 16, 3, "c0_config3" },
168 { 18, 1, "c0_watchlo,1" },
169 { 18, 2, "c0_watchlo,2" },
170 { 18, 3, "c0_watchlo,3" },
171 { 18, 4, "c0_watchlo,4" },
172 { 18, 5, "c0_watchlo,5" },
173 { 18, 6, "c0_watchlo,6" },
174 { 18, 7, "c0_watchlo,7" },
175 { 19, 1, "c0_watchhi,1" },
176 { 19, 2, "c0_watchhi,2" },
177 { 19, 3, "c0_watchhi,3" },
178 { 19, 4, "c0_watchhi,4" },
179 { 19, 5, "c0_watchhi,5" },
180 { 19, 6, "c0_watchhi,6" },
181 { 19, 7, "c0_watchhi,7" },
182 { 25, 1, "c0_perfcnt,1" },
183 { 25, 2, "c0_perfcnt,2" },
184 { 25, 3, "c0_perfcnt,3" },
185 { 25, 4, "c0_perfcnt,4" },
186 { 25, 5, "c0_perfcnt,5" },
187 { 25, 6, "c0_perfcnt,6" },
188 { 25, 7, "c0_perfcnt,7" },
189 { 27, 1, "c0_cacheerr,1" },
190 { 27, 2, "c0_cacheerr,2" },
191 { 27, 3, "c0_cacheerr,3" },
192 { 28, 1, "c0_datalo" },
193 { 29, 1, "c0_datahi" }
196 static const char * const mips_cp0_names_mips3264r2[32] =
198 "c0_index", "c0_random", "c0_entrylo0", "c0_entrylo1",
199 "c0_context", "c0_pagemask", "c0_wired", "c0_hwrena",
200 "c0_badvaddr", "c0_count", "c0_entryhi", "c0_compare",
201 "c0_status", "c0_cause", "c0_epc", "c0_prid",
202 "c0_config", "c0_lladdr", "c0_watchlo", "c0_watchhi",
203 "c0_xcontext", "$21", "$22", "c0_debug",
204 "c0_depc", "c0_perfcnt", "c0_errctl", "c0_cacheerr",
205 "c0_taglo", "c0_taghi", "c0_errorepc", "c0_desave",
208 static const struct mips_cp0sel_name mips_cp0sel_names_mips3264r2[] =
210 { 4, 1, "c0_contextconfig" },
211 { 0, 1, "c0_mvpcontrol" },
212 { 0, 2, "c0_mvpconf0" },
213 { 0, 3, "c0_mvpconf1" },
214 { 1, 1, "c0_vpecontrol" },
215 { 1, 2, "c0_vpeconf0" },
216 { 1, 3, "c0_vpeconf1" },
217 { 1, 4, "c0_yqmask" },
218 { 1, 5, "c0_vpeschedule" },
219 { 1, 6, "c0_vpeschefback" },
220 { 2, 1, "c0_tcstatus" },
221 { 2, 2, "c0_tcbind" },
222 { 2, 3, "c0_tcrestart" },
223 { 2, 4, "c0_tchalt" },
224 { 2, 5, "c0_tccontext" },
225 { 2, 6, "c0_tcschedule" },
226 { 2, 7, "c0_tcschefback" },
227 { 5, 1, "c0_pagegrain" },
228 { 6, 1, "c0_srsconf0" },
229 { 6, 2, "c0_srsconf1" },
230 { 6, 3, "c0_srsconf2" },
231 { 6, 4, "c0_srsconf3" },
232 { 6, 5, "c0_srsconf4" },
233 { 12, 1, "c0_intctl" },
234 { 12, 2, "c0_srsctl" },
235 { 12, 3, "c0_srsmap" },
236 { 15, 1, "c0_ebase" },
237 { 16, 1, "c0_config1" },
238 { 16, 2, "c0_config2" },
239 { 16, 3, "c0_config3" },
240 { 18, 1, "c0_watchlo,1" },
241 { 18, 2, "c0_watchlo,2" },
242 { 18, 3, "c0_watchlo,3" },
243 { 18, 4, "c0_watchlo,4" },
244 { 18, 5, "c0_watchlo,5" },
245 { 18, 6, "c0_watchlo,6" },
246 { 18, 7, "c0_watchlo,7" },
247 { 19, 1, "c0_watchhi,1" },
248 { 19, 2, "c0_watchhi,2" },
249 { 19, 3, "c0_watchhi,3" },
250 { 19, 4, "c0_watchhi,4" },
251 { 19, 5, "c0_watchhi,5" },
252 { 19, 6, "c0_watchhi,6" },
253 { 19, 7, "c0_watchhi,7" },
254 { 23, 1, "c0_tracecontrol" },
255 { 23, 2, "c0_tracecontrol2" },
256 { 23, 3, "c0_usertracedata" },
257 { 23, 4, "c0_tracebpc" },
258 { 25, 1, "c0_perfcnt,1" },
259 { 25, 2, "c0_perfcnt,2" },
260 { 25, 3, "c0_perfcnt,3" },
261 { 25, 4, "c0_perfcnt,4" },
262 { 25, 5, "c0_perfcnt,5" },
263 { 25, 6, "c0_perfcnt,6" },
264 { 25, 7, "c0_perfcnt,7" },
265 { 27, 1, "c0_cacheerr,1" },
266 { 27, 2, "c0_cacheerr,2" },
267 { 27, 3, "c0_cacheerr,3" },
268 { 28, 1, "c0_datalo" },
269 { 28, 2, "c0_taglo1" },
270 { 28, 3, "c0_datalo1" },
271 { 28, 4, "c0_taglo2" },
272 { 28, 5, "c0_datalo2" },
273 { 28, 6, "c0_taglo3" },
274 { 28, 7, "c0_datalo3" },
275 { 29, 1, "c0_datahi" },
276 { 29, 2, "c0_taghi1" },
277 { 29, 3, "c0_datahi1" },
278 { 29, 4, "c0_taghi2" },
279 { 29, 5, "c0_datahi2" },
280 { 29, 6, "c0_taghi3" },
281 { 29, 7, "c0_datahi3" },
284 /* SB-1: MIPS64 (mips_cp0_names_mips3264) with minor mods. */
285 static const char * const mips_cp0_names_sb1[32] =
287 "c0_index", "c0_random", "c0_entrylo0", "c0_entrylo1",
288 "c0_context", "c0_pagemask", "c0_wired", "$7",
289 "c0_badvaddr", "c0_count", "c0_entryhi", "c0_compare",
290 "c0_status", "c0_cause", "c0_epc", "c0_prid",
291 "c0_config", "c0_lladdr", "c0_watchlo", "c0_watchhi",
292 "c0_xcontext", "$21", "$22", "c0_debug",
293 "c0_depc", "c0_perfcnt", "c0_errctl", "c0_cacheerr_i",
294 "c0_taglo_i", "c0_taghi_i", "c0_errorepc", "c0_desave",
297 static const struct mips_cp0sel_name mips_cp0sel_names_sb1[] =
299 { 16, 1, "c0_config1" },
300 { 18, 1, "c0_watchlo,1" },
301 { 19, 1, "c0_watchhi,1" },
302 { 22, 0, "c0_perftrace" },
303 { 23, 3, "c0_edebug" },
304 { 25, 1, "c0_perfcnt,1" },
305 { 25, 2, "c0_perfcnt,2" },
306 { 25, 3, "c0_perfcnt,3" },
307 { 25, 4, "c0_perfcnt,4" },
308 { 25, 5, "c0_perfcnt,5" },
309 { 25, 6, "c0_perfcnt,6" },
310 { 25, 7, "c0_perfcnt,7" },
311 { 26, 1, "c0_buserr_pa" },
312 { 27, 1, "c0_cacheerr_d" },
313 { 27, 3, "c0_cacheerr_d_pa" },
314 { 28, 1, "c0_datalo_i" },
315 { 28, 2, "c0_taglo_d" },
316 { 28, 3, "c0_datalo_d" },
317 { 29, 1, "c0_datahi_i" },
318 { 29, 2, "c0_taghi_d" },
319 { 29, 3, "c0_datahi_d" },
322 static const char * const mips_hwr_names_numeric[32] =
324 "$0", "$1", "$2", "$3", "$4", "$5", "$6", "$7",
325 "$8", "$9", "$10", "$11", "$12", "$13", "$14", "$15",
326 "$16", "$17", "$18", "$19", "$20", "$21", "$22", "$23",
327 "$24", "$25", "$26", "$27", "$28", "$29", "$30", "$31"
330 static const char * const mips_hwr_names_mips3264r2[32] =
332 "hwr_cpunum", "hwr_synci_step", "hwr_cc", "hwr_ccres",
333 "$4", "$5", "$6", "$7",
334 "$8", "$9", "$10", "$11", "$12", "$13", "$14", "$15",
335 "$16", "$17", "$18", "$19", "$20", "$21", "$22", "$23",
336 "$24", "$25", "$26", "$27", "$28", "$29", "$30", "$31"
339 struct mips_abi_choice
342 const char * const *gpr_names;
343 const char * const *fpr_names;
346 struct mips_abi_choice mips_abi_choices[] =
348 { "numeric", mips_gpr_names_numeric, mips_fpr_names_numeric },
349 { "32", mips_gpr_names_oldabi, mips_fpr_names_32 },
350 { "n32", mips_gpr_names_newabi, mips_fpr_names_n32 },
351 { "64", mips_gpr_names_newabi, mips_fpr_names_64 },
354 struct mips_arch_choice
358 unsigned long bfd_mach;
361 const char * const *cp0_names;
362 const struct mips_cp0sel_name *cp0sel_names;
363 unsigned int cp0sel_names_len;
364 const char * const *hwr_names;
367 const struct mips_arch_choice mips_arch_choices[] =
369 { "numeric", 0, 0, 0, 0,
370 mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
372 { "r3000", 1, bfd_mach_mips3000, CPU_R3000, ISA_MIPS1,
373 mips_cp0_names_r3000, NULL, 0, mips_hwr_names_numeric },
374 { "r3900", 1, bfd_mach_mips3900, CPU_R3900, ISA_MIPS1,
375 mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
376 { "r4000", 1, bfd_mach_mips4000, CPU_R4000, ISA_MIPS3,
377 mips_cp0_names_r4000, NULL, 0, mips_hwr_names_numeric },
378 { "r4010", 1, bfd_mach_mips4010, CPU_R4010, ISA_MIPS2,
379 mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
380 { "vr4100", 1, bfd_mach_mips4100, CPU_VR4100, ISA_MIPS3,
381 mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
382 { "vr4111", 1, bfd_mach_mips4111, CPU_R4111, ISA_MIPS3,
383 mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
384 { "vr4120", 1, bfd_mach_mips4120, CPU_VR4120, ISA_MIPS3,
385 mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
386 { "r4300", 1, bfd_mach_mips4300, CPU_R4300, ISA_MIPS3,
387 mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
388 { "r4400", 1, bfd_mach_mips4400, CPU_R4400, ISA_MIPS3,
389 mips_cp0_names_r4000, NULL, 0, mips_hwr_names_numeric },
390 { "r4600", 1, bfd_mach_mips4600, CPU_R4600, ISA_MIPS3,
391 mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
392 { "r4650", 1, bfd_mach_mips4650, CPU_R4650, ISA_MIPS3,
393 mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
394 { "r5000", 1, bfd_mach_mips5000, CPU_R5000, ISA_MIPS4,
395 mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
396 { "vr5400", 1, bfd_mach_mips5400, CPU_VR5400, ISA_MIPS4,
397 mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
398 { "vr5500", 1, bfd_mach_mips5500, CPU_VR5500, ISA_MIPS4,
399 mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
400 { "r6000", 1, bfd_mach_mips6000, CPU_R6000, ISA_MIPS2,
401 mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
402 { "rm7000", 1, bfd_mach_mips7000, CPU_RM7000, ISA_MIPS4,
403 mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
404 { "rm9000", 1, bfd_mach_mips7000, CPU_RM7000, ISA_MIPS4,
405 mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
406 { "r8000", 1, bfd_mach_mips8000, CPU_R8000, ISA_MIPS4,
407 mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
408 { "r10000", 1, bfd_mach_mips10000, CPU_R10000, ISA_MIPS4,
409 mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
410 { "r12000", 1, bfd_mach_mips12000, CPU_R12000, ISA_MIPS4,
411 mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
412 { "mips5", 1, bfd_mach_mips5, CPU_MIPS5, ISA_MIPS5,
413 mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
415 /* For stock MIPS32, disassemble all applicable MIPS-specified ASEs.
416 Note that MIPS-3D and MDMX are not applicable to MIPS32. (See
417 _MIPS32 Architecture For Programmers Volume I: Introduction to the
418 MIPS32 Architecture_ (MIPS Document Number MD00082, Revision 0.95),
420 { "mips32", 1, bfd_mach_mipsisa32, CPU_MIPS32,
421 ISA_MIPS32 | INSN_MIPS16 | INSN_SMARTMIPS,
422 mips_cp0_names_mips3264,
423 mips_cp0sel_names_mips3264, ARRAY_SIZE (mips_cp0sel_names_mips3264),
424 mips_hwr_names_numeric },
426 { "mips32r2", 1, bfd_mach_mipsisa32r2, CPU_MIPS32R2,
427 (ISA_MIPS32R2 | INSN_MIPS16 | INSN_SMARTMIPS | INSN_DSP | INSN_DSPR2
428 | INSN_MIPS3D | INSN_MT),
429 mips_cp0_names_mips3264r2,
430 mips_cp0sel_names_mips3264r2, ARRAY_SIZE (mips_cp0sel_names_mips3264r2),
431 mips_hwr_names_mips3264r2 },
433 /* For stock MIPS64, disassemble all applicable MIPS-specified ASEs. */
434 { "mips64", 1, bfd_mach_mipsisa64, CPU_MIPS64,
435 ISA_MIPS64 | INSN_MIPS16 | INSN_MIPS3D | INSN_MDMX,
436 mips_cp0_names_mips3264,
437 mips_cp0sel_names_mips3264, ARRAY_SIZE (mips_cp0sel_names_mips3264),
438 mips_hwr_names_numeric },
440 { "mips64r2", 1, bfd_mach_mipsisa64r2, CPU_MIPS64R2,
441 (ISA_MIPS64R2 | INSN_MIPS16 | INSN_MIPS3D | INSN_DSP | INSN_DSPR2
442 | INSN_DSP64 | INSN_MT | INSN_MDMX),
443 mips_cp0_names_mips3264r2,
444 mips_cp0sel_names_mips3264r2, ARRAY_SIZE (mips_cp0sel_names_mips3264r2),
445 mips_hwr_names_mips3264r2 },
447 { "sb1", 1, bfd_mach_mips_sb1, CPU_SB1,
448 ISA_MIPS64 | INSN_MIPS3D | INSN_SB1,
450 mips_cp0sel_names_sb1, ARRAY_SIZE (mips_cp0sel_names_sb1),
451 mips_hwr_names_numeric },
453 { "loongson2e", 1, bfd_mach_mips_loongson_2e, CPU_LOONGSON_2E,
454 ISA_MIPS3 | INSN_LOONGSON_2E, mips_cp0_names_numeric,
455 NULL, 0, mips_hwr_names_numeric },
457 { "loongson2f", 1, bfd_mach_mips_loongson_2f, CPU_LOONGSON_2F,
458 ISA_MIPS3 | INSN_LOONGSON_2F, mips_cp0_names_numeric,
459 NULL, 0, mips_hwr_names_numeric },
461 { "octeon", 1, bfd_mach_mips_octeon, CPU_OCTEON,
462 ISA_MIPS64R2 | INSN_OCTEON, mips_cp0_names_numeric, NULL, 0,
463 mips_hwr_names_numeric },
465 /* This entry, mips16, is here only for ISA/processor selection; do
466 not print its name. */
467 { "", 1, bfd_mach_mips16, CPU_MIPS16, ISA_MIPS3 | INSN_MIPS16,
468 mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
471 /* ISA and processor type to disassemble for, and register names to use.
472 set_default_mips_dis_options and parse_mips_dis_options fill in these
474 static int mips_processor;
476 static const char * const *mips_gpr_names;
477 static const char * const *mips_fpr_names;
478 static const char * const *mips_cp0_names;
479 static const struct mips_cp0sel_name *mips_cp0sel_names;
480 static int mips_cp0sel_names_len;
481 static const char * const *mips_hwr_names;
484 static int no_aliases; /* If set disassemble as most general inst. */
486 static const struct mips_abi_choice *
487 choose_abi_by_name (const char *name, unsigned int namelen)
489 const struct mips_abi_choice *c;
492 for (i = 0, c = NULL; i < ARRAY_SIZE (mips_abi_choices) && c == NULL; i++)
493 if (strncmp (mips_abi_choices[i].name, name, namelen) == 0
494 && strlen (mips_abi_choices[i].name) == namelen)
495 c = &mips_abi_choices[i];
500 static const struct mips_arch_choice *
501 choose_arch_by_name (const char *name, unsigned int namelen)
503 const struct mips_arch_choice *c = NULL;
506 for (i = 0, c = NULL; i < ARRAY_SIZE (mips_arch_choices) && c == NULL; i++)
507 if (strncmp (mips_arch_choices[i].name, name, namelen) == 0
508 && strlen (mips_arch_choices[i].name) == namelen)
509 c = &mips_arch_choices[i];
514 static const struct mips_arch_choice *
515 choose_arch_by_number (unsigned long mach)
517 static unsigned long hint_bfd_mach;
518 static const struct mips_arch_choice *hint_arch_choice;
519 const struct mips_arch_choice *c;
522 /* We optimize this because even if the user specifies no
523 flags, this will be done for every instruction! */
524 if (hint_bfd_mach == mach
525 && hint_arch_choice != NULL
526 && hint_arch_choice->bfd_mach == hint_bfd_mach)
527 return hint_arch_choice;
529 for (i = 0, c = NULL; i < ARRAY_SIZE (mips_arch_choices) && c == NULL; i++)
531 if (mips_arch_choices[i].bfd_mach_valid
532 && mips_arch_choices[i].bfd_mach == mach)
534 c = &mips_arch_choices[i];
535 hint_bfd_mach = mach;
536 hint_arch_choice = c;
542 /* Check if the object uses NewABI conventions. */
545 is_newabi (Elf_Internal_Ehdr *header)
547 /* There are no old-style ABIs which use 64-bit ELF. */
548 if (header->e_ident[EI_CLASS] == ELFCLASS64)
551 /* If a 32-bit ELF file, n32 is a new-style ABI. */
552 if ((header->e_flags & EF_MIPS_ABI2) != 0)
559 set_default_mips_dis_options (struct disassemble_info *info)
561 const struct mips_arch_choice *chosen_arch;
563 /* Defaults: mipsIII/r3000 (?!), (o)32-style ("oldabi") GPR names,
564 and numeric FPR, CP0 register, and HWR names. */
565 mips_isa = ISA_MIPS3;
566 mips_processor = CPU_R3000;
567 mips_gpr_names = mips_gpr_names_oldabi;
568 mips_fpr_names = mips_fpr_names_numeric;
569 mips_cp0_names = mips_cp0_names_numeric;
570 mips_cp0sel_names = NULL;
571 mips_cp0sel_names_len = 0;
572 mips_hwr_names = mips_hwr_names_numeric;
575 /* If an ELF "newabi" binary, use the n32/(n)64 GPR names. */
576 if (info->flavour == bfd_target_elf_flavour && info->section != NULL)
578 Elf_Internal_Ehdr *header;
580 header = elf_elfheader (info->section->owner);
581 if (is_newabi (header))
582 mips_gpr_names = mips_gpr_names_newabi;
585 /* Set ISA, architecture, and cp0 register names as best we can. */
586 #if ! SYMTAB_AVAILABLE
587 /* This is running out on a target machine, not in a host tool.
588 FIXME: Where does mips_target_info come from? */
589 target_processor = mips_target_info.processor;
590 mips_isa = mips_target_info.isa;
592 chosen_arch = choose_arch_by_number (info->mach);
593 if (chosen_arch != NULL)
595 mips_processor = chosen_arch->processor;
596 mips_isa = chosen_arch->isa;
597 mips_cp0_names = chosen_arch->cp0_names;
598 mips_cp0sel_names = chosen_arch->cp0sel_names;
599 mips_cp0sel_names_len = chosen_arch->cp0sel_names_len;
600 mips_hwr_names = chosen_arch->hwr_names;
606 parse_mips_dis_option (const char *option, unsigned int len)
608 unsigned int i, optionlen, vallen;
610 const struct mips_abi_choice *chosen_abi;
611 const struct mips_arch_choice *chosen_arch;
613 /* Try to match options that are simple flags */
614 if (CONST_STRNEQ (option, "no-aliases"))
620 /* Look for the = that delimits the end of the option name. */
621 for (i = 0; i < len; i++)
622 if (option[i] == '=')
625 if (i == 0) /* Invalid option: no name before '='. */
627 if (i == len) /* Invalid option: no '='. */
629 if (i == (len - 1)) /* Invalid option: no value after '='. */
633 val = option + (optionlen + 1);
634 vallen = len - (optionlen + 1);
636 if (strncmp ("gpr-names", option, optionlen) == 0
637 && strlen ("gpr-names") == optionlen)
639 chosen_abi = choose_abi_by_name (val, vallen);
640 if (chosen_abi != NULL)
641 mips_gpr_names = chosen_abi->gpr_names;
645 if (strncmp ("fpr-names", option, optionlen) == 0
646 && strlen ("fpr-names") == optionlen)
648 chosen_abi = choose_abi_by_name (val, vallen);
649 if (chosen_abi != NULL)
650 mips_fpr_names = chosen_abi->fpr_names;
654 if (strncmp ("cp0-names", option, optionlen) == 0
655 && strlen ("cp0-names") == optionlen)
657 chosen_arch = choose_arch_by_name (val, vallen);
658 if (chosen_arch != NULL)
660 mips_cp0_names = chosen_arch->cp0_names;
661 mips_cp0sel_names = chosen_arch->cp0sel_names;
662 mips_cp0sel_names_len = chosen_arch->cp0sel_names_len;
667 if (strncmp ("hwr-names", option, optionlen) == 0
668 && strlen ("hwr-names") == optionlen)
670 chosen_arch = choose_arch_by_name (val, vallen);
671 if (chosen_arch != NULL)
672 mips_hwr_names = chosen_arch->hwr_names;
676 if (strncmp ("reg-names", option, optionlen) == 0
677 && strlen ("reg-names") == optionlen)
679 /* We check both ABI and ARCH here unconditionally, so
680 that "numeric" will do the desirable thing: select
681 numeric register names for all registers. Other than
682 that, a given name probably won't match both. */
683 chosen_abi = choose_abi_by_name (val, vallen);
684 if (chosen_abi != NULL)
686 mips_gpr_names = chosen_abi->gpr_names;
687 mips_fpr_names = chosen_abi->fpr_names;
689 chosen_arch = choose_arch_by_name (val, vallen);
690 if (chosen_arch != NULL)
692 mips_cp0_names = chosen_arch->cp0_names;
693 mips_cp0sel_names = chosen_arch->cp0sel_names;
694 mips_cp0sel_names_len = chosen_arch->cp0sel_names_len;
695 mips_hwr_names = chosen_arch->hwr_names;
700 /* Invalid option. */
704 parse_mips_dis_options (const char *options)
706 const char *option_end;
711 while (*options != '\0')
713 /* Skip empty options. */
720 /* We know that *options is neither NUL or a comma. */
721 option_end = options + 1;
722 while (*option_end != ',' && *option_end != '\0')
725 parse_mips_dis_option (options, option_end - options);
727 /* Go on to the next one. If option_end points to a comma, it
728 will be skipped above. */
729 options = option_end;
733 static const struct mips_cp0sel_name *
734 lookup_mips_cp0sel_name (const struct mips_cp0sel_name *names,
741 for (i = 0; i < len; i++)
742 if (names[i].cp0reg == cp0reg && names[i].sel == sel)
747 /* Print insn arguments for 32/64-bit code. */
750 print_insn_args (const char *d,
751 register unsigned long int l,
753 struct disassemble_info *info,
754 const struct mips_opcode *opp)
757 unsigned int lsb, msb, msbd;
761 for (; *d != '\0'; d++)
770 (*info->fprintf_func) (info->stream, "%c", *d);
774 /* Extension character; switch for second char. */
779 /* xgettext:c-format */
780 (*info->fprintf_func) (info->stream,
781 _("# internal error, incomplete extension sequence (+)"));
785 lsb = (l >> OP_SH_SHAMT) & OP_MASK_SHAMT;
786 (*info->fprintf_func) (info->stream, "0x%x", lsb);
790 msb = (l >> OP_SH_INSMSB) & OP_MASK_INSMSB;
791 (*info->fprintf_func) (info->stream, "0x%x", msb - lsb + 1);
795 (*info->fprintf_func) (info->stream, "0x%lx",
796 (l >> OP_SH_UDI1) & OP_MASK_UDI1);
800 (*info->fprintf_func) (info->stream, "0x%lx",
801 (l >> OP_SH_UDI2) & OP_MASK_UDI2);
805 (*info->fprintf_func) (info->stream, "0x%lx",
806 (l >> OP_SH_UDI3) & OP_MASK_UDI3);
810 (*info->fprintf_func) (info->stream, "0x%lx",
811 (l >> OP_SH_UDI4) & OP_MASK_UDI4);
816 msbd = (l >> OP_SH_EXTMSBD) & OP_MASK_EXTMSBD;
817 (*info->fprintf_func) (info->stream, "0x%x", msbd + 1);
822 const struct mips_cp0sel_name *n;
823 unsigned int cp0reg, sel;
825 cp0reg = (l >> OP_SH_RD) & OP_MASK_RD;
826 sel = (l >> OP_SH_SEL) & OP_MASK_SEL;
828 /* CP0 register including 'sel' code for mtcN (et al.), to be
829 printed textually if known. If not known, print both
830 CP0 register name and sel numerically since CP0 register
831 with sel 0 may have a name unrelated to register being
833 n = lookup_mips_cp0sel_name(mips_cp0sel_names,
834 mips_cp0sel_names_len, cp0reg, sel);
836 (*info->fprintf_func) (info->stream, "%s", n->name);
838 (*info->fprintf_func) (info->stream, "$%d,%d", cp0reg, sel);
843 lsb = ((l >> OP_SH_SHAMT) & OP_MASK_SHAMT) + 32;
844 (*info->fprintf_func) (info->stream, "0x%x", lsb);
848 msb = ((l >> OP_SH_INSMSB) & OP_MASK_INSMSB) + 32;
849 (*info->fprintf_func) (info->stream, "0x%x", msb - lsb + 1);
853 msbd = ((l >> OP_SH_EXTMSBD) & OP_MASK_EXTMSBD) + 32;
854 (*info->fprintf_func) (info->stream, "0x%x", msbd + 1);
857 case 't': /* Coprocessor 0 reg name */
858 (*info->fprintf_func) (info->stream, "%s",
859 mips_cp0_names[(l >> OP_SH_RT) &
863 case 'T': /* Coprocessor 0 reg name */
865 const struct mips_cp0sel_name *n;
866 unsigned int cp0reg, sel;
868 cp0reg = (l >> OP_SH_RT) & OP_MASK_RT;
869 sel = (l >> OP_SH_SEL) & OP_MASK_SEL;
871 /* CP0 register including 'sel' code for mftc0, to be
872 printed textually if known. If not known, print both
873 CP0 register name and sel numerically since CP0 register
874 with sel 0 may have a name unrelated to register being
876 n = lookup_mips_cp0sel_name(mips_cp0sel_names,
877 mips_cp0sel_names_len, cp0reg, sel);
879 (*info->fprintf_func) (info->stream, "%s", n->name);
881 (*info->fprintf_func) (info->stream, "$%d,%d", cp0reg, sel);
885 case 'x': /* bbit bit index */
886 (*info->fprintf_func) (info->stream, "0x%lx",
887 (l >> OP_SH_BBITIND) & OP_MASK_BBITIND);
890 case 'p': /* cins, cins32, exts and exts32 position */
891 (*info->fprintf_func) (info->stream, "0x%lx",
892 (l >> OP_SH_CINSPOS) & OP_MASK_CINSPOS);
895 case 's': /* cins and exts length-minus-one */
896 (*info->fprintf_func) (info->stream, "0x%lx",
897 (l >> OP_SH_CINSLM1) & OP_MASK_CINSLM1);
900 case 'S': /* cins32 and exts32 length-minus-one field */
901 (*info->fprintf_func) (info->stream, "0x%lx",
902 (l >> OP_SH_CINSLM1) & OP_MASK_CINSLM1);
905 case 'Q': /* seqi/snei immediate field */
906 op = (l >> OP_SH_SEQI) & OP_MASK_SEQI;
907 /* Sign-extend it. */
908 op = (op ^ 512) - 512;
909 (*info->fprintf_func) (info->stream, "%d", op);
913 /* xgettext:c-format */
914 (*info->fprintf_func) (info->stream,
915 _("# internal error, undefined extension sequence (+%c)"),
922 (*info->fprintf_func) (info->stream, "0x%lx",
923 (l >> OP_SH_BP) & OP_MASK_BP);
927 (*info->fprintf_func) (info->stream, "0x%lx",
928 (l >> OP_SH_SA3) & OP_MASK_SA3);
932 (*info->fprintf_func) (info->stream, "0x%lx",
933 (l >> OP_SH_SA4) & OP_MASK_SA4);
937 (*info->fprintf_func) (info->stream, "0x%lx",
938 (l >> OP_SH_IMM8) & OP_MASK_IMM8);
942 (*info->fprintf_func) (info->stream, "0x%lx",
943 (l >> OP_SH_RS) & OP_MASK_RS);
947 (*info->fprintf_func) (info->stream, "$ac%ld",
948 (l >> OP_SH_DSPACC) & OP_MASK_DSPACC);
952 (*info->fprintf_func) (info->stream, "0x%lx",
953 (l >> OP_SH_WRDSP) & OP_MASK_WRDSP);
957 (*info->fprintf_func) (info->stream, "$ac%ld",
958 (l >> OP_SH_DSPACC_S) & OP_MASK_DSPACC_S);
961 case '0': /* dsp 6-bit signed immediate in bit 20 */
962 delta = ((l >> OP_SH_DSPSFT) & OP_MASK_DSPSFT);
963 if (delta & 0x20) /* test sign bit */
964 delta |= ~OP_MASK_DSPSFT;
965 (*info->fprintf_func) (info->stream, "%d", delta);
968 case ':': /* dsp 7-bit signed immediate in bit 19 */
969 delta = ((l >> OP_SH_DSPSFT_7) & OP_MASK_DSPSFT_7);
970 if (delta & 0x40) /* test sign bit */
971 delta |= ~OP_MASK_DSPSFT_7;
972 (*info->fprintf_func) (info->stream, "%d", delta);
976 (*info->fprintf_func) (info->stream, "0x%lx",
977 (l >> OP_SH_RDDSP) & OP_MASK_RDDSP);
980 case '@': /* dsp 10-bit signed immediate in bit 16 */
981 delta = ((l >> OP_SH_IMM10) & OP_MASK_IMM10);
982 if (delta & 0x200) /* test sign bit */
983 delta |= ~OP_MASK_IMM10;
984 (*info->fprintf_func) (info->stream, "%d", delta);
988 (*info->fprintf_func) (info->stream, "%ld",
989 (l >> OP_SH_MT_U) & OP_MASK_MT_U);
993 (*info->fprintf_func) (info->stream, "%ld",
994 (l >> OP_SH_MT_H) & OP_MASK_MT_H);
998 (*info->fprintf_func) (info->stream, "$ac%ld",
999 (l >> OP_SH_MTACC_T) & OP_MASK_MTACC_T);
1003 (*info->fprintf_func) (info->stream, "$ac%ld",
1004 (l >> OP_SH_MTACC_D) & OP_MASK_MTACC_D);
1008 /* Coprocessor register for CTTC1, MTTC2, MTHC2, CTTC2. */
1009 (*info->fprintf_func) (info->stream, "$%ld",
1010 (l >> OP_SH_RD) & OP_MASK_RD);
1017 (*info->fprintf_func) (info->stream, "%s",
1018 mips_gpr_names[(l >> OP_SH_RS) & OP_MASK_RS]);
1023 (*info->fprintf_func) (info->stream, "%s",
1024 mips_gpr_names[(l >> OP_SH_RT) & OP_MASK_RT]);
1029 (*info->fprintf_func) (info->stream, "0x%lx",
1030 (l >> OP_SH_IMMEDIATE) & OP_MASK_IMMEDIATE);
1033 case 'j': /* Same as i, but sign-extended. */
1035 delta = (l >> OP_SH_DELTA) & OP_MASK_DELTA;
1038 (*info->fprintf_func) (info->stream, "%d",
1043 (*info->fprintf_func) (info->stream, "0x%x",
1044 (unsigned int) ((l >> OP_SH_PREFX)
1049 (*info->fprintf_func) (info->stream, "0x%x",
1050 (unsigned int) ((l >> OP_SH_CACHE)
1055 info->target = (((pc + 4) & ~(bfd_vma) 0x0fffffff)
1056 | (((l >> OP_SH_TARGET) & OP_MASK_TARGET) << 2));
1057 /* For gdb disassembler, force odd address on jalx. */
1058 if (info->flavour == bfd_target_unknown_flavour
1059 && strcmp (opp->name, "jalx") == 0)
1061 (*info->print_address_func) (info->target, info);
1065 /* Sign extend the displacement. */
1066 delta = (l >> OP_SH_DELTA) & OP_MASK_DELTA;
1069 info->target = (delta << 2) + pc + INSNLEN;
1070 (*info->print_address_func) (info->target, info);
1074 (*info->fprintf_func) (info->stream, "%s",
1075 mips_gpr_names[(l >> OP_SH_RD) & OP_MASK_RD]);
1080 /* First check for both rd and rt being equal. */
1081 unsigned int reg = (l >> OP_SH_RD) & OP_MASK_RD;
1082 if (reg == ((l >> OP_SH_RT) & OP_MASK_RT))
1083 (*info->fprintf_func) (info->stream, "%s",
1084 mips_gpr_names[reg]);
1087 /* If one is zero use the other. */
1089 (*info->fprintf_func) (info->stream, "%s",
1090 mips_gpr_names[(l >> OP_SH_RT) & OP_MASK_RT]);
1091 else if (((l >> OP_SH_RT) & OP_MASK_RT) == 0)
1092 (*info->fprintf_func) (info->stream, "%s",
1093 mips_gpr_names[reg]);
1094 else /* Bogus, result depends on processor. */
1095 (*info->fprintf_func) (info->stream, "%s or %s",
1096 mips_gpr_names[reg],
1097 mips_gpr_names[(l >> OP_SH_RT) & OP_MASK_RT]);
1103 (*info->fprintf_func) (info->stream, "%s", mips_gpr_names[0]);
1107 (*info->fprintf_func) (info->stream, "0x%lx",
1108 (l >> OP_SH_SHAMT) & OP_MASK_SHAMT);
1112 (*info->fprintf_func) (info->stream, "0x%lx",
1113 (l >> OP_SH_CODE) & OP_MASK_CODE);
1117 (*info->fprintf_func) (info->stream, "0x%lx",
1118 (l >> OP_SH_CODE2) & OP_MASK_CODE2);
1122 (*info->fprintf_func) (info->stream, "0x%lx",
1123 (l >> OP_SH_COPZ) & OP_MASK_COPZ);
1127 (*info->fprintf_func) (info->stream, "0x%lx",
1129 (l >> OP_SH_CODE20) & OP_MASK_CODE20);
1133 (*info->fprintf_func) (info->stream, "0x%lx",
1134 (l >> OP_SH_CODE19) & OP_MASK_CODE19);
1139 (*info->fprintf_func) (info->stream, "%s",
1140 mips_fpr_names[(l >> OP_SH_FS) & OP_MASK_FS]);
1145 (*info->fprintf_func) (info->stream, "%s",
1146 mips_fpr_names[(l >> OP_SH_FT) & OP_MASK_FT]);
1150 (*info->fprintf_func) (info->stream, "%s",
1151 mips_fpr_names[(l >> OP_SH_FD) & OP_MASK_FD]);
1155 (*info->fprintf_func) (info->stream, "%s",
1156 mips_fpr_names[(l >> OP_SH_FR) & OP_MASK_FR]);
1160 /* Coprocessor register for lwcN instructions, et al.
1162 Note that there is no load/store cp0 instructions, and
1163 that FPU (cp1) instructions disassemble this field using
1164 'T' format. Therefore, until we gain understanding of
1165 cp2 register names, we can simply print the register
1167 (*info->fprintf_func) (info->stream, "$%ld",
1168 (l >> OP_SH_RT) & OP_MASK_RT);
1172 /* Coprocessor register for mtcN instructions, et al. Note
1173 that FPU (cp1) instructions disassemble this field using
1174 'S' format. Therefore, we only need to worry about cp0,
1176 op = (l >> OP_SH_OP) & OP_MASK_OP;
1177 if (op == OP_OP_COP0)
1178 (*info->fprintf_func) (info->stream, "%s",
1179 mips_cp0_names[(l >> OP_SH_RD) & OP_MASK_RD]);
1181 (*info->fprintf_func) (info->stream, "$%ld",
1182 (l >> OP_SH_RD) & OP_MASK_RD);
1186 (*info->fprintf_func) (info->stream, "%s",
1187 mips_hwr_names[(l >> OP_SH_RD) & OP_MASK_RD]);
1191 (*info->fprintf_func) (info->stream,
1192 ((opp->pinfo & (FP_D | FP_S)) != 0
1193 ? "$fcc%ld" : "$cc%ld"),
1194 (l >> OP_SH_BCC) & OP_MASK_BCC);
1198 (*info->fprintf_func) (info->stream, "$fcc%ld",
1199 (l >> OP_SH_CCC) & OP_MASK_CCC);
1203 (*info->fprintf_func) (info->stream, "%ld",
1204 (l >> OP_SH_PERFREG) & OP_MASK_PERFREG);
1208 (*info->fprintf_func) (info->stream, "%ld",
1209 (l >> OP_SH_VECBYTE) & OP_MASK_VECBYTE);
1213 (*info->fprintf_func) (info->stream, "%ld",
1214 (l >> OP_SH_VECALIGN) & OP_MASK_VECALIGN);
1218 (*info->fprintf_func) (info->stream, "%ld",
1219 (l >> OP_SH_SEL) & OP_MASK_SEL);
1223 (*info->fprintf_func) (info->stream, "%ld",
1224 (l >> OP_SH_ALN) & OP_MASK_ALN);
1229 unsigned int vsel = (l >> OP_SH_VSEL) & OP_MASK_VSEL;
1231 if ((vsel & 0x10) == 0)
1236 for (fmt = 0; fmt < 3; fmt++, vsel >>= 1)
1237 if ((vsel & 1) == 0)
1239 (*info->fprintf_func) (info->stream, "$v%ld[%d]",
1240 (l >> OP_SH_FT) & OP_MASK_FT,
1243 else if ((vsel & 0x08) == 0)
1245 (*info->fprintf_func) (info->stream, "$v%ld",
1246 (l >> OP_SH_FT) & OP_MASK_FT);
1250 (*info->fprintf_func) (info->stream, "0x%lx",
1251 (l >> OP_SH_FT) & OP_MASK_FT);
1257 (*info->fprintf_func) (info->stream, "$v%ld",
1258 (l >> OP_SH_FD) & OP_MASK_FD);
1262 (*info->fprintf_func) (info->stream, "$v%ld",
1263 (l >> OP_SH_FS) & OP_MASK_FS);
1267 (*info->fprintf_func) (info->stream, "$v%ld",
1268 (l >> OP_SH_FT) & OP_MASK_FT);
1272 /* xgettext:c-format */
1273 (*info->fprintf_func) (info->stream,
1274 _("# internal error, undefined modifier (%c)"),
1281 /* Print the mips instruction at address MEMADDR in debugged memory,
1282 on using INFO. Returns length of the instruction, in bytes, which is
1283 always INSNLEN. BIGENDIAN must be 1 if this is big-endian code, 0 if
1284 this is little-endian code. */
1287 print_insn_mips (bfd_vma memaddr,
1288 unsigned long int word,
1289 struct disassemble_info *info)
1291 const struct mips_opcode *op;
1292 static bfd_boolean init = 0;
1293 static const struct mips_opcode *mips_hash[OP_MASK_OP + 1];
1295 /* Build a hash table to shorten the search time. */
1300 for (i = 0; i <= OP_MASK_OP; i++)
1302 for (op = mips_opcodes; op < &mips_opcodes[NUMOPCODES]; op++)
1304 if (op->pinfo == INSN_MACRO
1305 || (no_aliases && (op->pinfo2 & INSN2_ALIAS)))
1307 if (i == ((op->match >> OP_SH_OP) & OP_MASK_OP))
1318 info->bytes_per_chunk = INSNLEN;
1319 info->display_endian = info->endian;
1320 info->insn_info_valid = 1;
1321 info->branch_delay_insns = 0;
1322 info->data_size = 0;
1323 info->insn_type = dis_nonbranch;
1327 op = mips_hash[(word >> OP_SH_OP) & OP_MASK_OP];
1330 for (; op < &mips_opcodes[NUMOPCODES]; op++)
1332 if (op->pinfo != INSN_MACRO
1333 && !(no_aliases && (op->pinfo2 & INSN2_ALIAS))
1334 && (word & op->mask) == op->match)
1338 /* We always allow to disassemble the jalx instruction. */
1339 if (! OPCODE_IS_MEMBER (op, mips_isa, mips_processor)
1340 && strcmp (op->name, "jalx"))
1343 /* Figure out instruction type and branch delay information. */
1344 if ((op->pinfo & INSN_UNCOND_BRANCH_DELAY) != 0)
1346 if ((info->insn_type & INSN_WRITE_GPR_31) != 0)
1347 info->insn_type = dis_jsr;
1349 info->insn_type = dis_branch;
1350 info->branch_delay_insns = 1;
1352 else if ((op->pinfo & (INSN_COND_BRANCH_DELAY
1353 | INSN_COND_BRANCH_LIKELY)) != 0)
1355 if ((info->insn_type & INSN_WRITE_GPR_31) != 0)
1356 info->insn_type = dis_condjsr;
1358 info->insn_type = dis_condbranch;
1359 info->branch_delay_insns = 1;
1361 else if ((op->pinfo & (INSN_STORE_MEMORY
1362 | INSN_LOAD_MEMORY_DELAY)) != 0)
1363 info->insn_type = dis_dref;
1365 (*info->fprintf_func) (info->stream, "%s", op->name);
1368 if (d != NULL && *d != '\0')
1370 (*info->fprintf_func) (info->stream, "\t");
1371 print_insn_args (d, word, memaddr, info, op);
1379 /* Handle undefined instructions. */
1380 info->insn_type = dis_noninsn;
1381 (*info->fprintf_func) (info->stream, "0x%lx", word);
1385 /* Disassemble an operand for a mips16 instruction. */
1388 print_mips16_insn_arg (char type,
1389 const struct mips_opcode *op,
1391 bfd_boolean use_extend,
1394 struct disassemble_info *info)
1401 (*info->fprintf_func) (info->stream, "%c", type);
1406 (*info->fprintf_func) (info->stream, "%s",
1407 mips16_reg_names(((l >> MIPS16OP_SH_RY)
1408 & MIPS16OP_MASK_RY)));
1413 (*info->fprintf_func) (info->stream, "%s",
1414 mips16_reg_names(((l >> MIPS16OP_SH_RX)
1415 & MIPS16OP_MASK_RX)));
1419 (*info->fprintf_func) (info->stream, "%s",
1420 mips16_reg_names(((l >> MIPS16OP_SH_RZ)
1421 & MIPS16OP_MASK_RZ)));
1425 (*info->fprintf_func) (info->stream, "%s",
1426 mips16_reg_names(((l >> MIPS16OP_SH_MOVE32Z)
1427 & MIPS16OP_MASK_MOVE32Z)));
1431 (*info->fprintf_func) (info->stream, "%s", mips_gpr_names[0]);
1435 (*info->fprintf_func) (info->stream, "%s", mips_gpr_names[29]);
1439 (*info->fprintf_func) (info->stream, "$pc");
1443 (*info->fprintf_func) (info->stream, "%s", mips_gpr_names[31]);
1447 (*info->fprintf_func) (info->stream, "%s",
1448 mips_gpr_names[((l >> MIPS16OP_SH_REGR32)
1449 & MIPS16OP_MASK_REGR32)]);
1453 (*info->fprintf_func) (info->stream, "%s",
1454 mips_gpr_names[MIPS16OP_EXTRACT_REG32R (l)]);
1480 int immed, nbits, shift, signedp, extbits, pcrel, extu, branch;
1492 immed = (l >> MIPS16OP_SH_RZ) & MIPS16OP_MASK_RZ;
1498 immed = (l >> MIPS16OP_SH_RX) & MIPS16OP_MASK_RX;
1504 immed = (l >> MIPS16OP_SH_RZ) & MIPS16OP_MASK_RZ;
1510 immed = (l >> MIPS16OP_SH_RX) & MIPS16OP_MASK_RX;
1516 immed = (l >> MIPS16OP_SH_IMM4) & MIPS16OP_MASK_IMM4;
1522 immed = (l >> MIPS16OP_SH_IMM5) & MIPS16OP_MASK_IMM5;
1523 info->insn_type = dis_dref;
1524 info->data_size = 1;
1529 immed = (l >> MIPS16OP_SH_IMM5) & MIPS16OP_MASK_IMM5;
1530 info->insn_type = dis_dref;
1531 info->data_size = 2;
1536 immed = (l >> MIPS16OP_SH_IMM5) & MIPS16OP_MASK_IMM5;
1537 if ((op->pinfo & MIPS16_INSN_READ_PC) == 0
1538 && (op->pinfo & MIPS16_INSN_READ_SP) == 0)
1540 info->insn_type = dis_dref;
1541 info->data_size = 4;
1547 immed = (l >> MIPS16OP_SH_IMM5) & MIPS16OP_MASK_IMM5;
1548 info->insn_type = dis_dref;
1549 info->data_size = 8;
1553 immed = (l >> MIPS16OP_SH_IMM5) & MIPS16OP_MASK_IMM5;
1558 immed = (l >> MIPS16OP_SH_IMM6) & MIPS16OP_MASK_IMM6;
1562 immed = (l >> MIPS16OP_SH_IMM8) & MIPS16OP_MASK_IMM8;
1567 immed = (l >> MIPS16OP_SH_IMM8) & MIPS16OP_MASK_IMM8;
1568 /* FIXME: This might be lw, or it might be addiu to $sp or
1569 $pc. We assume it's load. */
1570 info->insn_type = dis_dref;
1571 info->data_size = 4;
1576 immed = (l >> MIPS16OP_SH_IMM8) & MIPS16OP_MASK_IMM8;
1577 info->insn_type = dis_dref;
1578 info->data_size = 8;
1582 immed = (l >> MIPS16OP_SH_IMM8) & MIPS16OP_MASK_IMM8;
1587 immed = (l >> MIPS16OP_SH_IMM8) & MIPS16OP_MASK_IMM8;
1593 immed = (l >> MIPS16OP_SH_IMM8) & MIPS16OP_MASK_IMM8;
1598 immed = (l >> MIPS16OP_SH_IMM8) & MIPS16OP_MASK_IMM8;
1602 info->insn_type = dis_condbranch;
1606 immed = (l >> MIPS16OP_SH_IMM11) & MIPS16OP_MASK_IMM11;
1610 info->insn_type = dis_branch;
1615 immed = (l >> MIPS16OP_SH_IMM8) & MIPS16OP_MASK_IMM8;
1617 /* FIXME: This can be lw or la. We assume it is lw. */
1618 info->insn_type = dis_dref;
1619 info->data_size = 4;
1624 immed = (l >> MIPS16OP_SH_IMM5) & MIPS16OP_MASK_IMM5;
1626 info->insn_type = dis_dref;
1627 info->data_size = 8;
1632 immed = (l >> MIPS16OP_SH_IMM5) & MIPS16OP_MASK_IMM5;
1641 if (signedp && immed >= (1 << (nbits - 1)))
1642 immed -= 1 << nbits;
1644 if ((type == '<' || type == '>' || type == '[' || type == ']')
1651 immed |= ((extend & 0x1f) << 11) | (extend & 0x7e0);
1652 else if (extbits == 15)
1653 immed |= ((extend & 0xf) << 11) | (extend & 0x7f0);
1655 immed = ((extend >> 6) & 0x1f) | (extend & 0x20);
1656 immed &= (1 << extbits) - 1;
1657 if (! extu && immed >= (1 << (extbits - 1)))
1658 immed -= 1 << extbits;
1662 (*info->fprintf_func) (info->stream, "%d", immed);
1670 baseaddr = memaddr + 2;
1672 else if (use_extend)
1673 baseaddr = memaddr - 2;
1681 /* If this instruction is in the delay slot of a jr
1682 instruction, the base address is the address of the
1683 jr instruction. If it is in the delay slot of jalr
1684 instruction, the base address is the address of the
1685 jalr instruction. This test is unreliable: we have
1686 no way of knowing whether the previous word is
1687 instruction or data. */
1688 status = (*info->read_memory_func) (memaddr - 4, buffer, 2,
1691 && (((info->endian == BFD_ENDIAN_BIG
1692 ? bfd_getb16 (buffer)
1693 : bfd_getl16 (buffer))
1694 & 0xf800) == 0x1800))
1695 baseaddr = memaddr - 4;
1698 status = (*info->read_memory_func) (memaddr - 2, buffer,
1701 && (((info->endian == BFD_ENDIAN_BIG
1702 ? bfd_getb16 (buffer)
1703 : bfd_getl16 (buffer))
1704 & 0xf81f) == 0xe800))
1705 baseaddr = memaddr - 2;
1708 info->target = (baseaddr & ~((1 << shift) - 1)) + immed;
1710 && info->flavour == bfd_target_unknown_flavour)
1711 /* For gdb disassembler, maintain odd address. */
1713 (*info->print_address_func) (info->target, info);
1720 int jalx = l & 0x400;
1724 l = ((l & 0x1f) << 23) | ((l & 0x3e0) << 13) | (extend << 2);
1725 if (!jalx && info->flavour == bfd_target_unknown_flavour)
1726 /* For gdb disassembler, maintain odd address. */
1729 info->target = ((memaddr + 4) & ~(bfd_vma) 0x0fffffff) | l;
1730 (*info->print_address_func) (info->target, info);
1731 info->insn_type = dis_jsr;
1732 info->branch_delay_insns = 1;
1738 int need_comma, amask, smask;
1742 l = (l >> MIPS16OP_SH_IMM6) & MIPS16OP_MASK_IMM6;
1744 amask = (l >> 3) & 7;
1746 if (amask > 0 && amask < 5)
1748 (*info->fprintf_func) (info->stream, "%s", mips_gpr_names[4]);
1750 (*info->fprintf_func) (info->stream, "-%s",
1751 mips_gpr_names[amask + 3]);
1755 smask = (l >> 1) & 3;
1758 (*info->fprintf_func) (info->stream, "%s??",
1759 need_comma ? "," : "");
1764 (*info->fprintf_func) (info->stream, "%s%s",
1765 need_comma ? "," : "",
1766 mips_gpr_names[16]);
1768 (*info->fprintf_func) (info->stream, "-%s",
1769 mips_gpr_names[smask + 15]);
1775 (*info->fprintf_func) (info->stream, "%s%s",
1776 need_comma ? "," : "",
1777 mips_gpr_names[31]);
1781 if (amask == 5 || amask == 6)
1783 (*info->fprintf_func) (info->stream, "%s$f0",
1784 need_comma ? "," : "");
1786 (*info->fprintf_func) (info->stream, "-$f1");
1793 /* MIPS16e save/restore. */
1796 int amask, args, statics;
1805 amask = (l >> 16) & 0xf;
1806 if (amask == MIPS16_ALL_ARGS)
1811 else if (amask == MIPS16_ALL_STATICS)
1819 statics = amask & 3;
1823 (*info->fprintf_func) (info->stream, "%s", mips_gpr_names[4]);
1825 (*info->fprintf_func) (info->stream, "-%s",
1826 mips_gpr_names[4 + args - 1]);
1830 framesz = (((l >> 16) & 0xf0) | (l & 0x0f)) * 8;
1831 if (framesz == 0 && !use_extend)
1834 (*info->fprintf_func) (info->stream, "%s%d",
1835 need_comma ? "," : "",
1838 if (l & 0x40) /* $ra */
1839 (*info->fprintf_func) (info->stream, ",%s", mips_gpr_names[31]);
1841 nsreg = (l >> 24) & 0x7;
1843 if (l & 0x20) /* $s0 */
1845 if (l & 0x10) /* $s1 */
1847 if (nsreg > 0) /* $s2-$s8 */
1848 smask |= ((1 << nsreg) - 1) << 2;
1850 /* Find first set static reg bit. */
1851 for (i = 0; i < 9; i++)
1853 if (smask & (1 << i))
1855 (*info->fprintf_func) (info->stream, ",%s",
1856 mips_gpr_names[i == 8 ? 30 : (16 + i)]);
1857 /* Skip over string of set bits. */
1858 for (j = i; smask & (2 << j); j++)
1861 (*info->fprintf_func) (info->stream, "-%s",
1862 mips_gpr_names[j == 8 ? 30 : (16 + j)]);
1867 /* Statics $ax - $a3. */
1869 (*info->fprintf_func) (info->stream, ",%s", mips_gpr_names[7]);
1870 else if (statics > 0)
1871 (*info->fprintf_func) (info->stream, ",%s-%s",
1872 mips_gpr_names[7 - statics + 1],
1878 /* xgettext:c-format */
1879 (*info->fprintf_func)
1881 _("# internal disassembler error, unrecognised modifier (%c)"),
1887 /* Disassemble mips16 instructions. */
1890 print_insn_mips16 (bfd_vma memaddr, struct disassemble_info *info)
1896 bfd_boolean use_extend;
1898 const struct mips_opcode *op, *opend;
1900 info->bytes_per_chunk = 2;
1901 info->display_endian = info->endian;
1902 info->insn_info_valid = 1;
1903 info->branch_delay_insns = 0;
1904 info->data_size = 0;
1905 info->insn_type = dis_nonbranch;
1909 status = (*info->read_memory_func) (memaddr, buffer, 2, info);
1912 (*info->memory_error_func) (status, memaddr, info);
1918 if (info->endian == BFD_ENDIAN_BIG)
1919 insn = bfd_getb16 (buffer);
1921 insn = bfd_getl16 (buffer);
1923 /* Handle the extend opcode specially. */
1925 if ((insn & 0xf800) == 0xf000)
1928 extend = insn & 0x7ff;
1932 status = (*info->read_memory_func) (memaddr, buffer, 2, info);
1935 (*info->fprintf_func) (info->stream, "extend 0x%x",
1936 (unsigned int) extend);
1937 (*info->memory_error_func) (status, memaddr, info);
1941 if (info->endian == BFD_ENDIAN_BIG)
1942 insn = bfd_getb16 (buffer);
1944 insn = bfd_getl16 (buffer);
1946 /* Check for an extend opcode followed by an extend opcode. */
1947 if ((insn & 0xf800) == 0xf000)
1949 (*info->fprintf_func) (info->stream, "extend 0x%x",
1950 (unsigned int) extend);
1951 info->insn_type = dis_noninsn;
1958 /* FIXME: Should probably use a hash table on the major opcode here. */
1960 opend = mips16_opcodes + bfd_mips16_num_opcodes;
1961 for (op = mips16_opcodes; op < opend; op++)
1963 if (op->pinfo != INSN_MACRO
1964 && !(no_aliases && (op->pinfo2 & INSN2_ALIAS))
1965 && (insn & op->mask) == op->match)
1969 if (strchr (op->args, 'a') != NULL)
1973 (*info->fprintf_func) (info->stream, "extend 0x%x",
1974 (unsigned int) extend);
1975 info->insn_type = dis_noninsn;
1983 status = (*info->read_memory_func) (memaddr, buffer, 2,
1988 if (info->endian == BFD_ENDIAN_BIG)
1989 extend = bfd_getb16 (buffer);
1991 extend = bfd_getl16 (buffer);
1996 (*info->fprintf_func) (info->stream, "%s", op->name);
1997 if (op->args[0] != '\0')
1998 (*info->fprintf_func) (info->stream, "\t");
2000 for (s = op->args; *s != '\0'; s++)
2004 && (((insn >> MIPS16OP_SH_RX) & MIPS16OP_MASK_RX)
2005 == ((insn >> MIPS16OP_SH_RY) & MIPS16OP_MASK_RY)))
2007 /* Skip the register and the comma. */
2013 && (((insn >> MIPS16OP_SH_RZ) & MIPS16OP_MASK_RZ)
2014 == ((insn >> MIPS16OP_SH_RX) & MIPS16OP_MASK_RX)))
2016 /* Skip the register and the comma. */
2020 print_mips16_insn_arg (*s, op, insn, use_extend, extend, memaddr,
2024 if ((op->pinfo & INSN_UNCOND_BRANCH_DELAY) != 0)
2026 info->branch_delay_insns = 1;
2027 if (info->insn_type != dis_jsr)
2028 info->insn_type = dis_branch;
2036 (*info->fprintf_func) (info->stream, "0x%x", extend | 0xf000);
2037 (*info->fprintf_func) (info->stream, "0x%x", insn);
2038 info->insn_type = dis_noninsn;
2043 /* In an environment where we do not know the symbol type of the
2044 instruction we are forced to assume that the low order bit of the
2045 instructions' address may mark it as a mips16 instruction. If we
2046 are single stepping, or the pc is within the disassembled function,
2047 this works. Otherwise, we need a clue. Sometimes. */
2050 _print_insn_mips (bfd_vma memaddr,
2051 struct disassemble_info *info,
2052 enum bfd_endian endianness)
2054 bfd_byte buffer[INSNLEN];
2057 set_default_mips_dis_options (info);
2058 parse_mips_dis_options (info->disassembler_options);
2061 /* FIXME: If odd address, this is CLEARLY a mips 16 instruction. */
2062 /* Only a few tools will work this way. */
2064 return print_insn_mips16 (memaddr, info);
2067 #if SYMTAB_AVAILABLE
2068 if (info->mach == bfd_mach_mips16
2069 || (info->symbols != NULL
2070 && bfd_asymbol_flavour (*info->symbols) == bfd_target_elf_flavour
2071 && ELF_ST_IS_MIPS16 ((*(elf_symbol_type **) info->symbols)
2072 ->internal_elf_sym.st_other)))
2073 return print_insn_mips16 (memaddr, info);
2076 status = (*info->read_memory_func) (memaddr, buffer, INSNLEN, info);
2081 if (endianness == BFD_ENDIAN_BIG)
2082 insn = (unsigned long) bfd_getb32 (buffer);
2084 insn = (unsigned long) bfd_getl32 (buffer);
2086 return print_insn_mips (memaddr, insn, info);
2090 (*info->memory_error_func) (status, memaddr, info);
2096 print_insn_big_mips (bfd_vma memaddr, struct disassemble_info *info)
2098 return _print_insn_mips (memaddr, info, BFD_ENDIAN_BIG);
2102 print_insn_little_mips (bfd_vma memaddr, struct disassemble_info *info)
2104 return _print_insn_mips (memaddr, info, BFD_ENDIAN_LITTLE);
2108 print_mips_disassembler_options (FILE *stream)
2112 fprintf (stream, _("\n\
2113 The following MIPS specific disassembler options are supported for use\n\
2114 with the -M switch (multiple options should be separated by commas):\n"));
2116 fprintf (stream, _("\n\
2117 gpr-names=ABI Print GPR names according to specified ABI.\n\
2118 Default: based on binary being disassembled.\n"));
2120 fprintf (stream, _("\n\
2121 fpr-names=ABI Print FPR names according to specified ABI.\n\
2122 Default: numeric.\n"));
2124 fprintf (stream, _("\n\
2125 cp0-names=ARCH Print CP0 register names according to\n\
2126 specified architecture.\n\
2127 Default: based on binary being disassembled.\n"));
2129 fprintf (stream, _("\n\
2130 hwr-names=ARCH Print HWR names according to specified \n\
2132 Default: based on binary being disassembled.\n"));
2134 fprintf (stream, _("\n\
2135 reg-names=ABI Print GPR and FPR names according to\n\
2136 specified ABI.\n"));
2138 fprintf (stream, _("\n\
2139 reg-names=ARCH Print CP0 register and HWR names according to\n\
2140 specified architecture.\n"));
2142 fprintf (stream, _("\n\
2143 For the options above, the following values are supported for \"ABI\":\n\
2145 for (i = 0; i < ARRAY_SIZE (mips_abi_choices); i++)
2146 fprintf (stream, " %s", mips_abi_choices[i].name);
2147 fprintf (stream, _("\n"));
2149 fprintf (stream, _("\n\
2150 For the options above, The following values are supported for \"ARCH\":\n\
2152 for (i = 0; i < ARRAY_SIZE (mips_arch_choices); i++)
2153 if (*mips_arch_choices[i].name != '\0')
2154 fprintf (stream, " %s", mips_arch_choices[i].name);
2155 fprintf (stream, _("\n"));
2157 fprintf (stream, _("\n"));