1 /* Print mips instructions for GDB, the GNU debugger, or for objdump.
2 Copyright 1989, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999,
3 2000, 2001, 2002, 2003, 2005, 2006, 2007, 2008, 2009, 2012
4 Free Software Foundation, Inc.
5 Contributed by Nobuyuki Hikichi(hikichi@sra.co.jp).
7 This file is part of the GNU opcodes library.
9 This library is free software; you can redistribute it and/or modify
10 it under the terms of the GNU General Public License as published by
11 the Free Software Foundation; either version 3, or (at your option)
14 It is distributed in the hope that it will be useful, but WITHOUT
15 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
16 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
17 License for more details.
19 You should have received a copy of the GNU General Public License
20 along with this program; if not, write to the Free Software
21 Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
22 MA 02110-1301, USA. */
26 #include "libiberty.h"
27 #include "opcode/mips.h"
30 /* FIXME: These are needed to figure out if the code is mips16 or
31 not. The low bit of the address is often a good indicator. No
32 symbol table is available when this code runs out in an embedded
33 system as when it is used for disassembler support in a monitor. */
35 #if !defined(EMBEDDED_ENV)
36 #define SYMTAB_AVAILABLE 1
41 /* Mips instructions are at maximum this many bytes long. */
45 /* FIXME: These should be shared with gdb somehow. */
47 struct mips_cp0sel_name
51 const char * const name;
54 /* The mips16 registers. */
55 static const unsigned int mips16_to_32_reg_map[] =
57 16, 17, 2, 3, 4, 5, 6, 7
60 /* The microMIPS registers with type b. */
61 #define micromips_to_32_reg_b_map mips16_to_32_reg_map
63 /* The microMIPS registers with type c. */
64 #define micromips_to_32_reg_c_map mips16_to_32_reg_map
66 /* The microMIPS registers with type d. */
67 #define micromips_to_32_reg_d_map mips16_to_32_reg_map
69 /* The microMIPS registers with type e. */
70 #define micromips_to_32_reg_e_map mips16_to_32_reg_map
72 /* The microMIPS registers with type f. */
73 #define micromips_to_32_reg_f_map mips16_to_32_reg_map
75 /* The microMIPS registers with type g. */
76 #define micromips_to_32_reg_g_map mips16_to_32_reg_map
78 /* The microMIPS registers with type h. */
79 static const unsigned int micromips_to_32_reg_h_map[] =
81 5, 5, 6, 4, 4, 4, 4, 4
84 /* The microMIPS registers with type i. */
85 static const unsigned int micromips_to_32_reg_i_map[] =
87 6, 7, 7, 21, 22, 5, 6, 7
90 /* The microMIPS registers with type j: 32 registers. */
92 /* The microMIPS registers with type l. */
93 #define micromips_to_32_reg_l_map mips16_to_32_reg_map
95 /* The microMIPS registers with type m. */
96 static const unsigned int micromips_to_32_reg_m_map[] =
98 0, 17, 2, 3, 16, 18, 19, 20
101 /* The microMIPS registers with type n. */
102 #define micromips_to_32_reg_n_map micromips_to_32_reg_m_map
104 /* The microMIPS registers with type p: 32 registers. */
106 /* The microMIPS registers with type q. */
107 static const unsigned int micromips_to_32_reg_q_map[] =
109 0, 17, 2, 3, 4, 5, 6, 7
112 /* reg type s is $29. */
114 /* reg type t is the same as the last register. */
116 /* reg type y is $31. */
118 /* reg type z is $0. */
120 /* micromips imm B type. */
121 static const int micromips_imm_b_map[8] =
123 1, 4, 8, 12, 16, 20, 24, -1
126 /* micromips imm C type. */
127 static const int micromips_imm_c_map[16] =
129 128, 1, 2, 3, 4, 7, 8, 15, 16, 31, 32, 63, 64, 255, 32768, 65535
132 /* micromips imm D type: (-512..511)<<1. */
133 /* micromips imm E type: (-64..63)<<1. */
134 /* micromips imm F type: (0..63). */
135 /* micromips imm G type: (-1..14). */
136 /* micromips imm H type: (0..15)<<1. */
137 /* micromips imm I type: (-1..126). */
138 /* micromips imm J type: (0..15)<<2. */
139 /* micromips imm L type: (0..15). */
140 /* micromips imm M type: (1..8). */
141 /* micromips imm W type: (0..63)<<2. */
142 /* micromips imm X type: (-8..7). */
143 /* micromips imm Y type: (-258..-3, 2..257)<<2. */
145 #define mips16_reg_names(rn) mips_gpr_names[mips16_to_32_reg_map[rn]]
148 static const char * const mips_gpr_names_numeric[32] =
150 "$0", "$1", "$2", "$3", "$4", "$5", "$6", "$7",
151 "$8", "$9", "$10", "$11", "$12", "$13", "$14", "$15",
152 "$16", "$17", "$18", "$19", "$20", "$21", "$22", "$23",
153 "$24", "$25", "$26", "$27", "$28", "$29", "$30", "$31"
156 static const char * const mips_gpr_names_oldabi[32] =
158 "zero", "at", "v0", "v1", "a0", "a1", "a2", "a3",
159 "t0", "t1", "t2", "t3", "t4", "t5", "t6", "t7",
160 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7",
161 "t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra"
164 static const char * const mips_gpr_names_newabi[32] =
166 "zero", "at", "v0", "v1", "a0", "a1", "a2", "a3",
167 "a4", "a5", "a6", "a7", "t0", "t1", "t2", "t3",
168 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7",
169 "t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra"
172 static const char * const mips_fpr_names_numeric[32] =
174 "$f0", "$f1", "$f2", "$f3", "$f4", "$f5", "$f6", "$f7",
175 "$f8", "$f9", "$f10", "$f11", "$f12", "$f13", "$f14", "$f15",
176 "$f16", "$f17", "$f18", "$f19", "$f20", "$f21", "$f22", "$f23",
177 "$f24", "$f25", "$f26", "$f27", "$f28", "$f29", "$f30", "$f31"
180 static const char * const mips_fpr_names_32[32] =
182 "fv0", "fv0f", "fv1", "fv1f", "ft0", "ft0f", "ft1", "ft1f",
183 "ft2", "ft2f", "ft3", "ft3f", "fa0", "fa0f", "fa1", "fa1f",
184 "ft4", "ft4f", "ft5", "ft5f", "fs0", "fs0f", "fs1", "fs1f",
185 "fs2", "fs2f", "fs3", "fs3f", "fs4", "fs4f", "fs5", "fs5f"
188 static const char * const mips_fpr_names_n32[32] =
190 "fv0", "ft14", "fv1", "ft15", "ft0", "ft1", "ft2", "ft3",
191 "ft4", "ft5", "ft6", "ft7", "fa0", "fa1", "fa2", "fa3",
192 "fa4", "fa5", "fa6", "fa7", "fs0", "ft8", "fs1", "ft9",
193 "fs2", "ft10", "fs3", "ft11", "fs4", "ft12", "fs5", "ft13"
196 static const char * const mips_fpr_names_64[32] =
198 "fv0", "ft12", "fv1", "ft13", "ft0", "ft1", "ft2", "ft3",
199 "ft4", "ft5", "ft6", "ft7", "fa0", "fa1", "fa2", "fa3",
200 "fa4", "fa5", "fa6", "fa7", "ft8", "ft9", "ft10", "ft11",
201 "fs0", "fs1", "fs2", "fs3", "fs4", "fs5", "fs6", "fs7"
204 static const char * const mips_cp0_names_numeric[32] =
206 "$0", "$1", "$2", "$3", "$4", "$5", "$6", "$7",
207 "$8", "$9", "$10", "$11", "$12", "$13", "$14", "$15",
208 "$16", "$17", "$18", "$19", "$20", "$21", "$22", "$23",
209 "$24", "$25", "$26", "$27", "$28", "$29", "$30", "$31"
212 static const char * const mips_cp0_names_r3000[32] =
214 "c0_index", "c0_random", "c0_entrylo", "$3",
215 "c0_context", "$5", "$6", "$7",
216 "c0_badvaddr", "$9", "c0_entryhi", "$11",
217 "c0_sr", "c0_cause", "c0_epc", "c0_prid",
218 "$16", "$17", "$18", "$19",
219 "$20", "$21", "$22", "$23",
220 "$24", "$25", "$26", "$27",
221 "$28", "$29", "$30", "$31",
224 static const char * const mips_cp0_names_r4000[32] =
226 "c0_index", "c0_random", "c0_entrylo0", "c0_entrylo1",
227 "c0_context", "c0_pagemask", "c0_wired", "$7",
228 "c0_badvaddr", "c0_count", "c0_entryhi", "c0_compare",
229 "c0_sr", "c0_cause", "c0_epc", "c0_prid",
230 "c0_config", "c0_lladdr", "c0_watchlo", "c0_watchhi",
231 "c0_xcontext", "$21", "$22", "$23",
232 "$24", "$25", "c0_ecc", "c0_cacheerr",
233 "c0_taglo", "c0_taghi", "c0_errorepc", "$31",
236 static const char * const mips_cp0_names_r5900[32] =
238 "c0_index", "c0_random", "c0_entrylo0", "c0_entrylo1",
239 "c0_context", "c0_pagemask", "c0_wired", "$7",
240 "c0_badvaddr", "c0_count", "c0_entryhi", "c0_compare",
241 "c0_sr", "c0_cause", "c0_epc", "c0_prid",
242 "c0_config", "$17", "$18", "$19",
243 "$20", "$21", "$22", "c0_badpaddr",
244 "c0_depc", "c0_perfcnt", "$26", "$27",
245 "c0_taglo", "c0_taghi", "c0_errorepc", "$31"
248 static const struct mips_cp0sel_name mips_cp0sel_names_mipsr5900[] =
251 { 24, 3, "c0_iabm" },
253 { 24, 5, "c0_dabm" },
255 { 24, 7, "c0_dvbm" },
256 { 25, 1, "c0_perfcnt,1" },
257 { 25, 2, "c0_perfcnt,2" }
260 static const char * const mips_cp0_names_mips3264[32] =
262 "c0_index", "c0_random", "c0_entrylo0", "c0_entrylo1",
263 "c0_context", "c0_pagemask", "c0_wired", "$7",
264 "c0_badvaddr", "c0_count", "c0_entryhi", "c0_compare",
265 "c0_status", "c0_cause", "c0_epc", "c0_prid",
266 "c0_config", "c0_lladdr", "c0_watchlo", "c0_watchhi",
267 "c0_xcontext", "$21", "$22", "c0_debug",
268 "c0_depc", "c0_perfcnt", "c0_errctl", "c0_cacheerr",
269 "c0_taglo", "c0_taghi", "c0_errorepc", "c0_desave",
272 static const struct mips_cp0sel_name mips_cp0sel_names_mips3264[] =
274 { 16, 1, "c0_config1" },
275 { 16, 2, "c0_config2" },
276 { 16, 3, "c0_config3" },
277 { 18, 1, "c0_watchlo,1" },
278 { 18, 2, "c0_watchlo,2" },
279 { 18, 3, "c0_watchlo,3" },
280 { 18, 4, "c0_watchlo,4" },
281 { 18, 5, "c0_watchlo,5" },
282 { 18, 6, "c0_watchlo,6" },
283 { 18, 7, "c0_watchlo,7" },
284 { 19, 1, "c0_watchhi,1" },
285 { 19, 2, "c0_watchhi,2" },
286 { 19, 3, "c0_watchhi,3" },
287 { 19, 4, "c0_watchhi,4" },
288 { 19, 5, "c0_watchhi,5" },
289 { 19, 6, "c0_watchhi,6" },
290 { 19, 7, "c0_watchhi,7" },
291 { 25, 1, "c0_perfcnt,1" },
292 { 25, 2, "c0_perfcnt,2" },
293 { 25, 3, "c0_perfcnt,3" },
294 { 25, 4, "c0_perfcnt,4" },
295 { 25, 5, "c0_perfcnt,5" },
296 { 25, 6, "c0_perfcnt,6" },
297 { 25, 7, "c0_perfcnt,7" },
298 { 27, 1, "c0_cacheerr,1" },
299 { 27, 2, "c0_cacheerr,2" },
300 { 27, 3, "c0_cacheerr,3" },
301 { 28, 1, "c0_datalo" },
302 { 29, 1, "c0_datahi" }
305 static const char * const mips_cp0_names_mips3264r2[32] =
307 "c0_index", "c0_random", "c0_entrylo0", "c0_entrylo1",
308 "c0_context", "c0_pagemask", "c0_wired", "c0_hwrena",
309 "c0_badvaddr", "c0_count", "c0_entryhi", "c0_compare",
310 "c0_status", "c0_cause", "c0_epc", "c0_prid",
311 "c0_config", "c0_lladdr", "c0_watchlo", "c0_watchhi",
312 "c0_xcontext", "$21", "$22", "c0_debug",
313 "c0_depc", "c0_perfcnt", "c0_errctl", "c0_cacheerr",
314 "c0_taglo", "c0_taghi", "c0_errorepc", "c0_desave",
317 static const struct mips_cp0sel_name mips_cp0sel_names_mips3264r2[] =
319 { 4, 1, "c0_contextconfig" },
320 { 0, 1, "c0_mvpcontrol" },
321 { 0, 2, "c0_mvpconf0" },
322 { 0, 3, "c0_mvpconf1" },
323 { 1, 1, "c0_vpecontrol" },
324 { 1, 2, "c0_vpeconf0" },
325 { 1, 3, "c0_vpeconf1" },
326 { 1, 4, "c0_yqmask" },
327 { 1, 5, "c0_vpeschedule" },
328 { 1, 6, "c0_vpeschefback" },
329 { 2, 1, "c0_tcstatus" },
330 { 2, 2, "c0_tcbind" },
331 { 2, 3, "c0_tcrestart" },
332 { 2, 4, "c0_tchalt" },
333 { 2, 5, "c0_tccontext" },
334 { 2, 6, "c0_tcschedule" },
335 { 2, 7, "c0_tcschefback" },
336 { 5, 1, "c0_pagegrain" },
337 { 6, 1, "c0_srsconf0" },
338 { 6, 2, "c0_srsconf1" },
339 { 6, 3, "c0_srsconf2" },
340 { 6, 4, "c0_srsconf3" },
341 { 6, 5, "c0_srsconf4" },
342 { 12, 1, "c0_intctl" },
343 { 12, 2, "c0_srsctl" },
344 { 12, 3, "c0_srsmap" },
345 { 15, 1, "c0_ebase" },
346 { 16, 1, "c0_config1" },
347 { 16, 2, "c0_config2" },
348 { 16, 3, "c0_config3" },
349 { 18, 1, "c0_watchlo,1" },
350 { 18, 2, "c0_watchlo,2" },
351 { 18, 3, "c0_watchlo,3" },
352 { 18, 4, "c0_watchlo,4" },
353 { 18, 5, "c0_watchlo,5" },
354 { 18, 6, "c0_watchlo,6" },
355 { 18, 7, "c0_watchlo,7" },
356 { 19, 1, "c0_watchhi,1" },
357 { 19, 2, "c0_watchhi,2" },
358 { 19, 3, "c0_watchhi,3" },
359 { 19, 4, "c0_watchhi,4" },
360 { 19, 5, "c0_watchhi,5" },
361 { 19, 6, "c0_watchhi,6" },
362 { 19, 7, "c0_watchhi,7" },
363 { 23, 1, "c0_tracecontrol" },
364 { 23, 2, "c0_tracecontrol2" },
365 { 23, 3, "c0_usertracedata" },
366 { 23, 4, "c0_tracebpc" },
367 { 25, 1, "c0_perfcnt,1" },
368 { 25, 2, "c0_perfcnt,2" },
369 { 25, 3, "c0_perfcnt,3" },
370 { 25, 4, "c0_perfcnt,4" },
371 { 25, 5, "c0_perfcnt,5" },
372 { 25, 6, "c0_perfcnt,6" },
373 { 25, 7, "c0_perfcnt,7" },
374 { 27, 1, "c0_cacheerr,1" },
375 { 27, 2, "c0_cacheerr,2" },
376 { 27, 3, "c0_cacheerr,3" },
377 { 28, 1, "c0_datalo" },
378 { 28, 2, "c0_taglo1" },
379 { 28, 3, "c0_datalo1" },
380 { 28, 4, "c0_taglo2" },
381 { 28, 5, "c0_datalo2" },
382 { 28, 6, "c0_taglo3" },
383 { 28, 7, "c0_datalo3" },
384 { 29, 1, "c0_datahi" },
385 { 29, 2, "c0_taghi1" },
386 { 29, 3, "c0_datahi1" },
387 { 29, 4, "c0_taghi2" },
388 { 29, 5, "c0_datahi2" },
389 { 29, 6, "c0_taghi3" },
390 { 29, 7, "c0_datahi3" },
393 /* SB-1: MIPS64 (mips_cp0_names_mips3264) with minor mods. */
394 static const char * const mips_cp0_names_sb1[32] =
396 "c0_index", "c0_random", "c0_entrylo0", "c0_entrylo1",
397 "c0_context", "c0_pagemask", "c0_wired", "$7",
398 "c0_badvaddr", "c0_count", "c0_entryhi", "c0_compare",
399 "c0_status", "c0_cause", "c0_epc", "c0_prid",
400 "c0_config", "c0_lladdr", "c0_watchlo", "c0_watchhi",
401 "c0_xcontext", "$21", "$22", "c0_debug",
402 "c0_depc", "c0_perfcnt", "c0_errctl", "c0_cacheerr_i",
403 "c0_taglo_i", "c0_taghi_i", "c0_errorepc", "c0_desave",
406 static const struct mips_cp0sel_name mips_cp0sel_names_sb1[] =
408 { 16, 1, "c0_config1" },
409 { 18, 1, "c0_watchlo,1" },
410 { 19, 1, "c0_watchhi,1" },
411 { 22, 0, "c0_perftrace" },
412 { 23, 3, "c0_edebug" },
413 { 25, 1, "c0_perfcnt,1" },
414 { 25, 2, "c0_perfcnt,2" },
415 { 25, 3, "c0_perfcnt,3" },
416 { 25, 4, "c0_perfcnt,4" },
417 { 25, 5, "c0_perfcnt,5" },
418 { 25, 6, "c0_perfcnt,6" },
419 { 25, 7, "c0_perfcnt,7" },
420 { 26, 1, "c0_buserr_pa" },
421 { 27, 1, "c0_cacheerr_d" },
422 { 27, 3, "c0_cacheerr_d_pa" },
423 { 28, 1, "c0_datalo_i" },
424 { 28, 2, "c0_taglo_d" },
425 { 28, 3, "c0_datalo_d" },
426 { 29, 1, "c0_datahi_i" },
427 { 29, 2, "c0_taghi_d" },
428 { 29, 3, "c0_datahi_d" },
431 /* Xlr cop0 register names. */
432 static const char * const mips_cp0_names_xlr[32] = {
433 "c0_index", "c0_random", "c0_entrylo0", "c0_entrylo1",
434 "c0_context", "c0_pagemask", "c0_wired", "$7",
435 "c0_badvaddr", "c0_count", "c0_entryhi", "c0_compare",
436 "c0_status", "c0_cause", "c0_epc", "c0_prid",
437 "c0_config", "c0_lladdr", "c0_watchlo", "c0_watchhi",
438 "c0_xcontext", "$21", "$22", "c0_debug",
439 "c0_depc", "c0_perfcnt", "c0_errctl", "c0_cacheerr_i",
440 "c0_taglo_i", "c0_taghi_i", "c0_errorepc", "c0_desave",
443 /* XLR's CP0 Select Registers. */
445 static const struct mips_cp0sel_name mips_cp0sel_names_xlr[] = {
446 { 9, 6, "c0_extintreq" },
447 { 9, 7, "c0_extintmask" },
448 { 15, 1, "c0_ebase" },
449 { 16, 1, "c0_config1" },
450 { 16, 2, "c0_config2" },
451 { 16, 3, "c0_config3" },
452 { 16, 7, "c0_procid2" },
453 { 18, 1, "c0_watchlo,1" },
454 { 18, 2, "c0_watchlo,2" },
455 { 18, 3, "c0_watchlo,3" },
456 { 18, 4, "c0_watchlo,4" },
457 { 18, 5, "c0_watchlo,5" },
458 { 18, 6, "c0_watchlo,6" },
459 { 18, 7, "c0_watchlo,7" },
460 { 19, 1, "c0_watchhi,1" },
461 { 19, 2, "c0_watchhi,2" },
462 { 19, 3, "c0_watchhi,3" },
463 { 19, 4, "c0_watchhi,4" },
464 { 19, 5, "c0_watchhi,5" },
465 { 19, 6, "c0_watchhi,6" },
466 { 19, 7, "c0_watchhi,7" },
467 { 25, 1, "c0_perfcnt,1" },
468 { 25, 2, "c0_perfcnt,2" },
469 { 25, 3, "c0_perfcnt,3" },
470 { 25, 4, "c0_perfcnt,4" },
471 { 25, 5, "c0_perfcnt,5" },
472 { 25, 6, "c0_perfcnt,6" },
473 { 25, 7, "c0_perfcnt,7" },
474 { 27, 1, "c0_cacheerr,1" },
475 { 27, 2, "c0_cacheerr,2" },
476 { 27, 3, "c0_cacheerr,3" },
477 { 28, 1, "c0_datalo" },
478 { 29, 1, "c0_datahi" }
481 static const char * const mips_hwr_names_numeric[32] =
483 "$0", "$1", "$2", "$3", "$4", "$5", "$6", "$7",
484 "$8", "$9", "$10", "$11", "$12", "$13", "$14", "$15",
485 "$16", "$17", "$18", "$19", "$20", "$21", "$22", "$23",
486 "$24", "$25", "$26", "$27", "$28", "$29", "$30", "$31"
489 static const char * const mips_hwr_names_mips3264r2[32] =
491 "hwr_cpunum", "hwr_synci_step", "hwr_cc", "hwr_ccres",
492 "$4", "$5", "$6", "$7",
493 "$8", "$9", "$10", "$11", "$12", "$13", "$14", "$15",
494 "$16", "$17", "$18", "$19", "$20", "$21", "$22", "$23",
495 "$24", "$25", "$26", "$27", "$28", "$29", "$30", "$31"
498 struct mips_abi_choice
501 const char * const *gpr_names;
502 const char * const *fpr_names;
505 struct mips_abi_choice mips_abi_choices[] =
507 { "numeric", mips_gpr_names_numeric, mips_fpr_names_numeric },
508 { "32", mips_gpr_names_oldabi, mips_fpr_names_32 },
509 { "n32", mips_gpr_names_newabi, mips_fpr_names_n32 },
510 { "64", mips_gpr_names_newabi, mips_fpr_names_64 },
513 struct mips_arch_choice
517 unsigned long bfd_mach;
520 const char * const *cp0_names;
521 const struct mips_cp0sel_name *cp0sel_names;
522 unsigned int cp0sel_names_len;
523 const char * const *hwr_names;
526 const struct mips_arch_choice mips_arch_choices[] =
528 { "numeric", 0, 0, 0, 0,
529 mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
531 { "r3000", 1, bfd_mach_mips3000, CPU_R3000, ISA_MIPS1,
532 mips_cp0_names_r3000, NULL, 0, mips_hwr_names_numeric },
533 { "r3900", 1, bfd_mach_mips3900, CPU_R3900, ISA_MIPS1,
534 mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
535 { "r4000", 1, bfd_mach_mips4000, CPU_R4000, ISA_MIPS3,
536 mips_cp0_names_r4000, NULL, 0, mips_hwr_names_numeric },
537 { "r4010", 1, bfd_mach_mips4010, CPU_R4010, ISA_MIPS2,
538 mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
539 { "vr4100", 1, bfd_mach_mips4100, CPU_VR4100, ISA_MIPS3,
540 mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
541 { "vr4111", 1, bfd_mach_mips4111, CPU_R4111, ISA_MIPS3,
542 mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
543 { "vr4120", 1, bfd_mach_mips4120, CPU_VR4120, ISA_MIPS3,
544 mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
545 { "r4300", 1, bfd_mach_mips4300, CPU_R4300, ISA_MIPS3,
546 mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
547 { "r4400", 1, bfd_mach_mips4400, CPU_R4400, ISA_MIPS3,
548 mips_cp0_names_r4000, NULL, 0, mips_hwr_names_numeric },
549 { "r4600", 1, bfd_mach_mips4600, CPU_R4600, ISA_MIPS3,
550 mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
551 { "r4650", 1, bfd_mach_mips4650, CPU_R4650, ISA_MIPS3,
552 mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
553 { "r5000", 1, bfd_mach_mips5000, CPU_R5000, ISA_MIPS4,
554 mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
555 { "vr5400", 1, bfd_mach_mips5400, CPU_VR5400, ISA_MIPS4,
556 mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
557 { "vr5500", 1, bfd_mach_mips5500, CPU_VR5500, ISA_MIPS4,
558 mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
559 { "r5900", 1, bfd_mach_mips5900, CPU_R5900, ISA_MIPS3,
560 mips_cp0_names_r5900, NULL, 0, mips_hwr_names_numeric },
561 { "r6000", 1, bfd_mach_mips6000, CPU_R6000, ISA_MIPS2,
562 mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
563 { "rm7000", 1, bfd_mach_mips7000, CPU_RM7000, ISA_MIPS4,
564 mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
565 { "rm9000", 1, bfd_mach_mips7000, CPU_RM7000, ISA_MIPS4,
566 mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
567 { "r8000", 1, bfd_mach_mips8000, CPU_R8000, ISA_MIPS4,
568 mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
569 { "r10000", 1, bfd_mach_mips10000, CPU_R10000, ISA_MIPS4,
570 mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
571 { "r12000", 1, bfd_mach_mips12000, CPU_R12000, ISA_MIPS4,
572 mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
573 { "r14000", 1, bfd_mach_mips14000, CPU_R14000, ISA_MIPS4,
574 mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
575 { "r16000", 1, bfd_mach_mips16000, CPU_R16000, ISA_MIPS4,
576 mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
577 { "mips5", 1, bfd_mach_mips5, CPU_MIPS5, ISA_MIPS5,
578 mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
580 /* For stock MIPS32, disassemble all applicable MIPS-specified ASEs.
581 Note that MIPS-3D and MDMX are not applicable to MIPS32. (See
582 _MIPS32 Architecture For Programmers Volume I: Introduction to the
583 MIPS32 Architecture_ (MIPS Document Number MD00082, Revision 0.95),
585 { "mips32", 1, bfd_mach_mipsisa32, CPU_MIPS32,
586 ISA_MIPS32 | INSN_SMARTMIPS,
587 mips_cp0_names_mips3264,
588 mips_cp0sel_names_mips3264, ARRAY_SIZE (mips_cp0sel_names_mips3264),
589 mips_hwr_names_numeric },
591 { "mips32r2", 1, bfd_mach_mipsisa32r2, CPU_MIPS32R2,
592 (ISA_MIPS32R2 | INSN_SMARTMIPS | INSN_DSP | INSN_DSPR2
593 | INSN_MIPS3D | INSN_MT | INSN_MCU | INSN_VIRT),
594 mips_cp0_names_mips3264r2,
595 mips_cp0sel_names_mips3264r2, ARRAY_SIZE (mips_cp0sel_names_mips3264r2),
596 mips_hwr_names_mips3264r2 },
598 /* For stock MIPS64, disassemble all applicable MIPS-specified ASEs. */
599 { "mips64", 1, bfd_mach_mipsisa64, CPU_MIPS64,
600 ISA_MIPS64 | INSN_MIPS3D | INSN_MDMX,
601 mips_cp0_names_mips3264,
602 mips_cp0sel_names_mips3264, ARRAY_SIZE (mips_cp0sel_names_mips3264),
603 mips_hwr_names_numeric },
605 { "mips64r2", 1, bfd_mach_mipsisa64r2, CPU_MIPS64R2,
606 (ISA_MIPS64R2 | INSN_MIPS3D | INSN_DSP | INSN_DSPR2
607 | INSN_DSP64 | INSN_MT | INSN_MDMX | INSN_MCU | INSN_VIRT | INSN_VIRT64),
608 mips_cp0_names_mips3264r2,
609 mips_cp0sel_names_mips3264r2, ARRAY_SIZE (mips_cp0sel_names_mips3264r2),
610 mips_hwr_names_mips3264r2 },
612 { "sb1", 1, bfd_mach_mips_sb1, CPU_SB1,
613 ISA_MIPS64 | INSN_MIPS3D | INSN_SB1,
615 mips_cp0sel_names_sb1, ARRAY_SIZE (mips_cp0sel_names_sb1),
616 mips_hwr_names_numeric },
618 { "loongson2e", 1, bfd_mach_mips_loongson_2e, CPU_LOONGSON_2E,
619 ISA_MIPS3 | INSN_LOONGSON_2E, mips_cp0_names_numeric,
620 NULL, 0, mips_hwr_names_numeric },
622 { "loongson2f", 1, bfd_mach_mips_loongson_2f, CPU_LOONGSON_2F,
623 ISA_MIPS3 | INSN_LOONGSON_2F, mips_cp0_names_numeric,
624 NULL, 0, mips_hwr_names_numeric },
626 { "loongson3a", 1, bfd_mach_mips_loongson_3a, CPU_LOONGSON_3A,
627 ISA_MIPS64 | INSN_LOONGSON_3A, mips_cp0_names_numeric,
628 NULL, 0, mips_hwr_names_numeric },
630 { "octeon", 1, bfd_mach_mips_octeon, CPU_OCTEON,
631 ISA_MIPS64R2 | INSN_OCTEON, mips_cp0_names_numeric, NULL, 0,
632 mips_hwr_names_numeric },
634 { "octeon+", 1, bfd_mach_mips_octeonp, CPU_OCTEONP,
635 ISA_MIPS64R2 | INSN_OCTEONP, mips_cp0_names_numeric,
636 NULL, 0, mips_hwr_names_numeric },
638 { "octeon2", 1, bfd_mach_mips_octeon2, CPU_OCTEON2,
639 ISA_MIPS64R2 | INSN_OCTEON2, mips_cp0_names_numeric,
640 NULL, 0, mips_hwr_names_numeric },
642 { "xlr", 1, bfd_mach_mips_xlr, CPU_XLR,
643 ISA_MIPS64 | INSN_XLR,
645 mips_cp0sel_names_xlr, ARRAY_SIZE (mips_cp0sel_names_xlr),
646 mips_hwr_names_numeric },
648 /* XLP is mostly like XLR, with the prominent exception it is being
650 { "xlp", 1, bfd_mach_mips_xlr, CPU_XLR,
651 ISA_MIPS64R2 | INSN_XLR,
653 mips_cp0sel_names_xlr, ARRAY_SIZE (mips_cp0sel_names_xlr),
654 mips_hwr_names_numeric },
656 /* This entry, mips16, is here only for ISA/processor selection; do
657 not print its name. */
658 { "", 1, bfd_mach_mips16, CPU_MIPS16, ISA_MIPS3,
659 mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
662 /* ISA and processor type to disassemble for, and register names to use.
663 set_default_mips_dis_options and parse_mips_dis_options fill in these
665 static int mips_processor;
667 static int micromips_ase;
668 static const char * const *mips_gpr_names;
669 static const char * const *mips_fpr_names;
670 static const char * const *mips_cp0_names;
671 static const struct mips_cp0sel_name *mips_cp0sel_names;
672 static int mips_cp0sel_names_len;
673 static const char * const *mips_hwr_names;
676 static int no_aliases; /* If set disassemble as most general inst. */
678 static const struct mips_abi_choice *
679 choose_abi_by_name (const char *name, unsigned int namelen)
681 const struct mips_abi_choice *c;
684 for (i = 0, c = NULL; i < ARRAY_SIZE (mips_abi_choices) && c == NULL; i++)
685 if (strncmp (mips_abi_choices[i].name, name, namelen) == 0
686 && strlen (mips_abi_choices[i].name) == namelen)
687 c = &mips_abi_choices[i];
692 static const struct mips_arch_choice *
693 choose_arch_by_name (const char *name, unsigned int namelen)
695 const struct mips_arch_choice *c = NULL;
698 for (i = 0, c = NULL; i < ARRAY_SIZE (mips_arch_choices) && c == NULL; i++)
699 if (strncmp (mips_arch_choices[i].name, name, namelen) == 0
700 && strlen (mips_arch_choices[i].name) == namelen)
701 c = &mips_arch_choices[i];
706 static const struct mips_arch_choice *
707 choose_arch_by_number (unsigned long mach)
709 static unsigned long hint_bfd_mach;
710 static const struct mips_arch_choice *hint_arch_choice;
711 const struct mips_arch_choice *c;
714 /* We optimize this because even if the user specifies no
715 flags, this will be done for every instruction! */
716 if (hint_bfd_mach == mach
717 && hint_arch_choice != NULL
718 && hint_arch_choice->bfd_mach == hint_bfd_mach)
719 return hint_arch_choice;
721 for (i = 0, c = NULL; i < ARRAY_SIZE (mips_arch_choices) && c == NULL; i++)
723 if (mips_arch_choices[i].bfd_mach_valid
724 && mips_arch_choices[i].bfd_mach == mach)
726 c = &mips_arch_choices[i];
727 hint_bfd_mach = mach;
728 hint_arch_choice = c;
734 /* Check if the object uses NewABI conventions. */
737 is_newabi (Elf_Internal_Ehdr *header)
739 /* There are no old-style ABIs which use 64-bit ELF. */
740 if (header->e_ident[EI_CLASS] == ELFCLASS64)
743 /* If a 32-bit ELF file, n32 is a new-style ABI. */
744 if ((header->e_flags & EF_MIPS_ABI2) != 0)
750 /* Check if the object has microMIPS ASE code. */
753 is_micromips (Elf_Internal_Ehdr *header)
755 if ((header->e_flags & EF_MIPS_ARCH_ASE_MICROMIPS) != 0)
762 set_default_mips_dis_options (struct disassemble_info *info)
764 const struct mips_arch_choice *chosen_arch;
766 /* Defaults: mipsIII/r3000 (?!), no microMIPS ASE (any compressed code
767 is MIPS16 ASE) (o)32-style ("oldabi") GPR names, and numeric FPR,
768 CP0 register, and HWR names. */
769 mips_isa = ISA_MIPS3;
770 mips_processor = CPU_R3000;
772 mips_gpr_names = mips_gpr_names_oldabi;
773 mips_fpr_names = mips_fpr_names_numeric;
774 mips_cp0_names = mips_cp0_names_numeric;
775 mips_cp0sel_names = NULL;
776 mips_cp0sel_names_len = 0;
777 mips_hwr_names = mips_hwr_names_numeric;
780 /* Update settings according to the ELF file header flags. */
781 if (info->flavour == bfd_target_elf_flavour && info->section != NULL)
783 Elf_Internal_Ehdr *header;
785 header = elf_elfheader (info->section->owner);
786 /* If an ELF "newabi" binary, use the n32/(n)64 GPR names. */
787 if (is_newabi (header))
788 mips_gpr_names = mips_gpr_names_newabi;
789 /* If a microMIPS binary, then don't use MIPS16 bindings. */
790 micromips_ase = is_micromips (header);
793 /* Set ISA, architecture, and cp0 register names as best we can. */
794 #if ! SYMTAB_AVAILABLE
795 /* This is running out on a target machine, not in a host tool.
796 FIXME: Where does mips_target_info come from? */
797 target_processor = mips_target_info.processor;
798 mips_isa = mips_target_info.isa;
800 chosen_arch = choose_arch_by_number (info->mach);
801 if (chosen_arch != NULL)
803 mips_processor = chosen_arch->processor;
804 mips_isa = chosen_arch->isa;
805 mips_cp0_names = chosen_arch->cp0_names;
806 mips_cp0sel_names = chosen_arch->cp0sel_names;
807 mips_cp0sel_names_len = chosen_arch->cp0sel_names_len;
808 mips_hwr_names = chosen_arch->hwr_names;
814 parse_mips_dis_option (const char *option, unsigned int len)
816 unsigned int i, optionlen, vallen;
818 const struct mips_abi_choice *chosen_abi;
819 const struct mips_arch_choice *chosen_arch;
821 /* Try to match options that are simple flags */
822 if (CONST_STRNEQ (option, "no-aliases"))
828 if (CONST_STRNEQ (option, "virt"))
830 mips_isa |= INSN_VIRT;
831 if (mips_isa & ISA_MIPS64R2)
832 mips_isa |= INSN_VIRT64;
836 /* Look for the = that delimits the end of the option name. */
837 for (i = 0; i < len; i++)
838 if (option[i] == '=')
841 if (i == 0) /* Invalid option: no name before '='. */
843 if (i == len) /* Invalid option: no '='. */
845 if (i == (len - 1)) /* Invalid option: no value after '='. */
849 val = option + (optionlen + 1);
850 vallen = len - (optionlen + 1);
852 if (strncmp ("gpr-names", option, optionlen) == 0
853 && strlen ("gpr-names") == optionlen)
855 chosen_abi = choose_abi_by_name (val, vallen);
856 if (chosen_abi != NULL)
857 mips_gpr_names = chosen_abi->gpr_names;
861 if (strncmp ("fpr-names", option, optionlen) == 0
862 && strlen ("fpr-names") == optionlen)
864 chosen_abi = choose_abi_by_name (val, vallen);
865 if (chosen_abi != NULL)
866 mips_fpr_names = chosen_abi->fpr_names;
870 if (strncmp ("cp0-names", option, optionlen) == 0
871 && strlen ("cp0-names") == optionlen)
873 chosen_arch = choose_arch_by_name (val, vallen);
874 if (chosen_arch != NULL)
876 mips_cp0_names = chosen_arch->cp0_names;
877 mips_cp0sel_names = chosen_arch->cp0sel_names;
878 mips_cp0sel_names_len = chosen_arch->cp0sel_names_len;
883 if (strncmp ("hwr-names", option, optionlen) == 0
884 && strlen ("hwr-names") == optionlen)
886 chosen_arch = choose_arch_by_name (val, vallen);
887 if (chosen_arch != NULL)
888 mips_hwr_names = chosen_arch->hwr_names;
892 if (strncmp ("reg-names", option, optionlen) == 0
893 && strlen ("reg-names") == optionlen)
895 /* We check both ABI and ARCH here unconditionally, so
896 that "numeric" will do the desirable thing: select
897 numeric register names for all registers. Other than
898 that, a given name probably won't match both. */
899 chosen_abi = choose_abi_by_name (val, vallen);
900 if (chosen_abi != NULL)
902 mips_gpr_names = chosen_abi->gpr_names;
903 mips_fpr_names = chosen_abi->fpr_names;
905 chosen_arch = choose_arch_by_name (val, vallen);
906 if (chosen_arch != NULL)
908 mips_cp0_names = chosen_arch->cp0_names;
909 mips_cp0sel_names = chosen_arch->cp0sel_names;
910 mips_cp0sel_names_len = chosen_arch->cp0sel_names_len;
911 mips_hwr_names = chosen_arch->hwr_names;
916 /* Invalid option. */
920 parse_mips_dis_options (const char *options)
922 const char *option_end;
927 while (*options != '\0')
929 /* Skip empty options. */
936 /* We know that *options is neither NUL or a comma. */
937 option_end = options + 1;
938 while (*option_end != ',' && *option_end != '\0')
941 parse_mips_dis_option (options, option_end - options);
943 /* Go on to the next one. If option_end points to a comma, it
944 will be skipped above. */
945 options = option_end;
949 static const struct mips_cp0sel_name *
950 lookup_mips_cp0sel_name (const struct mips_cp0sel_name *names,
957 for (i = 0; i < len; i++)
958 if (names[i].cp0reg == cp0reg && names[i].sel == sel)
963 /* Print insn arguments for 32/64-bit code. */
966 print_insn_args (const char *d,
969 struct disassemble_info *info,
970 const struct mips_opcode *opp)
972 const fprintf_ftype infprintf = info->fprintf_func;
973 unsigned int lsb, msb, msbd;
974 void *is = info->stream;
979 #define GET_OP(insn, field) \
980 (((insn) >> OP_SH_##field) & OP_MASK_##field)
981 #define GET_OP_S(insn, field) \
982 ((GET_OP (insn, field) ^ ((OP_MASK_##field >> 1) + 1)) \
983 - ((OP_MASK_##field >> 1) + 1))
984 for (; *d != '\0'; d++)
993 infprintf (is, "%c", *d);
997 /* Extension character; switch for second char. */
1002 /* xgettext:c-format */
1004 _("# internal error, "
1005 "incomplete extension sequence (+)"));
1009 lsb = GET_OP (l, SHAMT);
1010 infprintf (is, "0x%x", lsb);
1014 msb = GET_OP (l, INSMSB);
1015 infprintf (is, "0x%x", msb - lsb + 1);
1019 infprintf (is, "0x%x", GET_OP (l, UDI1));
1023 infprintf (is, "0x%x", GET_OP (l, UDI2));
1027 infprintf (is, "0x%x", GET_OP (l, UDI3));
1031 infprintf (is, "0x%x", GET_OP (l, UDI4));
1036 msbd = GET_OP (l, EXTMSBD);
1037 infprintf (is, "0x%x", msbd + 1);
1042 const struct mips_cp0sel_name *n;
1043 unsigned int cp0reg, sel;
1045 cp0reg = GET_OP (l, RD);
1046 sel = GET_OP (l, SEL);
1048 /* CP0 register including 'sel' code for mtcN (et al.), to be
1049 printed textually if known. If not known, print both
1050 CP0 register name and sel numerically since CP0 register
1051 with sel 0 may have a name unrelated to register being
1053 n = lookup_mips_cp0sel_name(mips_cp0sel_names,
1054 mips_cp0sel_names_len, cp0reg, sel);
1056 infprintf (is, "%s", n->name);
1058 infprintf (is, "$%d,%d", cp0reg, sel);
1063 lsb = GET_OP (l, SHAMT) + 32;
1064 infprintf (is, "0x%x", lsb);
1068 msb = GET_OP (l, INSMSB) + 32;
1069 infprintf (is, "0x%x", msb - lsb + 1);
1073 msbd = GET_OP (l, EXTMSBD) + 32;
1074 infprintf (is, "0x%x", msbd + 1);
1077 case 'J': /* hypcall operand */
1078 infprintf (is, "0x%x", GET_OP (l, CODE10));
1081 case 't': /* Coprocessor 0 reg name */
1082 infprintf (is, "%s", mips_cp0_names[GET_OP (l, RT)]);
1085 case 'T': /* Coprocessor 0 reg name */
1087 const struct mips_cp0sel_name *n;
1088 unsigned int cp0reg, sel;
1090 cp0reg = GET_OP (l, RT);
1091 sel = GET_OP (l, SEL);
1093 /* CP0 register including 'sel' code for mftc0, to be
1094 printed textually if known. If not known, print both
1095 CP0 register name and sel numerically since CP0 register
1096 with sel 0 may have a name unrelated to register being
1098 n = lookup_mips_cp0sel_name(mips_cp0sel_names,
1099 mips_cp0sel_names_len, cp0reg, sel);
1101 infprintf (is, "%s", n->name);
1103 infprintf (is, "$%d,%d", cp0reg, sel);
1107 case 'x': /* bbit bit index */
1108 infprintf (is, "0x%x", GET_OP (l, BBITIND));
1111 case 'p': /* cins, cins32, exts and exts32 position */
1112 infprintf (is, "0x%x", GET_OP (l, CINSPOS));
1115 case 's': /* cins and exts length-minus-one */
1116 infprintf (is, "0x%x", GET_OP (l, CINSLM1));
1119 case 'S': /* cins32 and exts32 length-minus-one field */
1120 infprintf (is, "0x%x", GET_OP (l, CINSLM1));
1123 case 'Q': /* seqi/snei immediate field */
1124 infprintf (is, "%d", GET_OP_S (l, SEQI));
1127 case 'a': /* 8-bit signed offset in bit 6 */
1128 infprintf (is, "%d", GET_OP_S (l, OFFSET_A));
1131 case 'b': /* 8-bit signed offset in bit 3 */
1132 infprintf (is, "%d", GET_OP_S (l, OFFSET_B));
1135 case 'c': /* 9-bit signed offset in bit 6 */
1136 /* Left shift 4 bits to print the real offset. */
1137 infprintf (is, "%d", GET_OP_S (l, OFFSET_C) << 4);
1141 infprintf (is, "%s", mips_gpr_names[GET_OP (l, RZ)]);
1145 infprintf (is, "%s", mips_fpr_names[GET_OP (l, FZ)]);
1149 /* xgettext:c-format */
1151 _("# internal error, "
1152 "undefined extension sequence (+%c)"),
1159 infprintf (is, "0x%x", GET_OP (l, BP));
1163 infprintf (is, "0x%x", GET_OP (l, SA3));
1167 infprintf (is, "0x%x", GET_OP (l, SA4));
1171 infprintf (is, "0x%x", GET_OP (l, IMM8));
1175 infprintf (is, "0x%x", GET_OP (l, RS));
1179 infprintf (is, "$ac%d", GET_OP (l, DSPACC));
1183 infprintf (is, "0x%x", GET_OP (l, WRDSP));
1187 infprintf (is, "$ac%d", GET_OP (l, DSPACC_S));
1190 case '0': /* dsp 6-bit signed immediate in bit 20 */
1191 infprintf (is, "%d", GET_OP_S (l, DSPSFT));
1194 case ':': /* dsp 7-bit signed immediate in bit 19 */
1195 infprintf (is, "%d", GET_OP_S (l, DSPSFT_7));
1199 infprintf (is, "%d", GET_OP_S (l, OFFSET12));
1203 infprintf (is, "0x%x", GET_OP (l, 3BITPOS));
1207 infprintf (is, "0x%x", GET_OP (l, RDDSP));
1210 case '@': /* dsp 10-bit signed immediate in bit 16 */
1211 infprintf (is, "%d", GET_OP_S (l, IMM10));
1215 infprintf (is, "%d", GET_OP (l, MT_U));
1219 infprintf (is, "%d", GET_OP (l, MT_H));
1223 infprintf (is, "$ac%d", GET_OP (l, MTACC_T));
1227 infprintf (is, "$ac%d", GET_OP (l, MTACC_D));
1231 /* Coprocessor register for CTTC1, MTTC2, MTHC2, CTTC2. */
1232 infprintf (is, "$%d", GET_OP (l, RD));
1239 infprintf (is, "%s", mips_gpr_names[GET_OP (l, RS)]);
1244 infprintf (is, "%s", mips_gpr_names[GET_OP (l, RT)]);
1249 infprintf (is, "0x%x", GET_OP (l, IMMEDIATE));
1252 case 'j': /* Same as i, but sign-extended. */
1254 infprintf (is, "%d", GET_OP_S (l, DELTA));
1258 infprintf (is, "0x%x", GET_OP (l, PREFX));
1262 infprintf (is, "0x%x", GET_OP (l, CACHE));
1266 info->target = (((pc + 4) & ~(bfd_vma) 0x0fffffff)
1267 | (GET_OP (l, TARGET) << 2));
1268 /* For gdb disassembler, force odd address on jalx. */
1269 if (info->flavour == bfd_target_unknown_flavour
1270 && strcmp (opp->name, "jalx") == 0)
1272 (*info->print_address_func) (info->target, info);
1276 /* Sign extend the displacement. */
1277 info->target = (GET_OP_S (l, DELTA) << 2) + pc + INSNLEN;
1278 (*info->print_address_func) (info->target, info);
1282 infprintf (is, "%s", mips_gpr_names[GET_OP (l, RD)]);
1287 /* First check for both rd and rt being equal. */
1290 reg = GET_OP (l, RD);
1291 if (reg == GET_OP (l, RT))
1292 infprintf (is, "%s", mips_gpr_names[reg]);
1295 /* If one is zero use the other. */
1297 infprintf (is, "%s", mips_gpr_names[GET_OP (l, RT)]);
1298 else if (GET_OP (l, RT) == 0)
1299 infprintf (is, "%s", mips_gpr_names[reg]);
1300 else /* Bogus, result depends on processor. */
1301 infprintf (is, "%s or %s",
1302 mips_gpr_names[reg],
1303 mips_gpr_names[GET_OP (l, RT)]);
1309 infprintf (is, "%s", mips_gpr_names[0]);
1314 infprintf (is, "0x%x", GET_OP (l, SHAMT));
1318 infprintf (is, "0x%x", GET_OP (l, CODE));
1322 infprintf (is, "0x%x", GET_OP (l, CODE2));
1326 infprintf (is, "0x%x", GET_OP (l, COPZ));
1330 infprintf (is, "0x%x", GET_OP (l, CODE20));
1334 infprintf (is, "0x%x", GET_OP (l, CODE19));
1339 infprintf (is, "%s", mips_fpr_names[GET_OP (l, FS)]);
1344 infprintf (is, "%s", mips_fpr_names[GET_OP (l, FT)]);
1348 infprintf (is, "%s", mips_fpr_names[GET_OP (l, FD)]);
1352 infprintf (is, "%s", mips_fpr_names[GET_OP (l, FR)]);
1356 /* Coprocessor register for lwcN instructions, et al.
1358 Note that there is no load/store cp0 instructions, and
1359 that FPU (cp1) instructions disassemble this field using
1360 'T' format. Therefore, until we gain understanding of
1361 cp2 register names, we can simply print the register
1363 infprintf (is, "$%d", GET_OP (l, RT));
1367 /* Coprocessor register for mtcN instructions, et al. Note
1368 that FPU (cp1) instructions disassemble this field using
1369 'S' format. Therefore, we only need to worry about cp0,
1371 op = GET_OP (l, OP);
1372 if (op == OP_OP_COP0)
1373 infprintf (is, "%s", mips_cp0_names[GET_OP (l, RD)]);
1375 infprintf (is, "$%d", GET_OP (l, RD));
1379 infprintf (is, "%s", mips_hwr_names[GET_OP (l, RD)]);
1384 (opp->pinfo & (FP_D | FP_S)) != 0 ? "$fcc%d" : "$cc%d",
1389 infprintf (is, "$fcc%d", GET_OP (l, CCC));
1393 infprintf (is, "%d", GET_OP (l, PERFREG));
1397 infprintf (is, "%d", GET_OP (l, VECBYTE));
1401 infprintf (is, "%d", GET_OP (l, VECALIGN));
1405 infprintf (is, "%d", GET_OP (l, SEL));
1409 infprintf (is, "%d", GET_OP (l, ALN));
1414 unsigned int vsel = GET_OP (l, VSEL);
1416 if ((vsel & 0x10) == 0)
1421 for (fmt = 0; fmt < 3; fmt++, vsel >>= 1)
1422 if ((vsel & 1) == 0)
1424 infprintf (is, "$v%d[%d]", GET_OP (l, FT), vsel >> 1);
1426 else if ((vsel & 0x08) == 0)
1428 infprintf (is, "$v%d", GET_OP (l, FT));
1432 infprintf (is, "0x%x", GET_OP (l, FT));
1438 infprintf (is, "$v%d", GET_OP (l, FD));
1442 infprintf (is, "$v%d", GET_OP (l, FS));
1446 infprintf (is, "$v%d", GET_OP (l, FT));
1450 /* xgettext:c-format */
1451 infprintf (is, _("# internal error, undefined modifier (%c)"), *d);
1457 /* Print the mips instruction at address MEMADDR in debugged memory,
1458 on using INFO. Returns length of the instruction, in bytes, which is
1459 always INSNLEN. BIGENDIAN must be 1 if this is big-endian code, 0 if
1460 this is little-endian code. */
1463 print_insn_mips (bfd_vma memaddr,
1465 struct disassemble_info *info)
1467 static const struct mips_opcode *mips_hash[OP_MASK_OP + 1];
1468 const fprintf_ftype infprintf = info->fprintf_func;
1469 const struct mips_opcode *op;
1470 static bfd_boolean init = 0;
1471 void *is = info->stream;
1473 /* Build a hash table to shorten the search time. */
1478 for (i = 0; i <= OP_MASK_OP; i++)
1480 for (op = mips_opcodes; op < &mips_opcodes[NUMOPCODES]; op++)
1482 if (op->pinfo == INSN_MACRO
1483 || (no_aliases && (op->pinfo2 & INSN2_ALIAS)))
1485 if (i == GET_OP (op->match, OP))
1496 info->bytes_per_chunk = INSNLEN;
1497 info->display_endian = info->endian;
1498 info->insn_info_valid = 1;
1499 info->branch_delay_insns = 0;
1500 info->data_size = 0;
1501 info->insn_type = dis_nonbranch;
1505 op = mips_hash[GET_OP (word, OP)];
1508 for (; op < &mips_opcodes[NUMOPCODES]; op++)
1510 if (op->pinfo != INSN_MACRO
1511 && !(no_aliases && (op->pinfo2 & INSN2_ALIAS))
1512 && (word & op->mask) == op->match)
1516 /* We always allow to disassemble the jalx instruction. */
1517 if (!opcode_is_member (op, mips_isa, mips_processor)
1518 && strcmp (op->name, "jalx"))
1521 /* Figure out instruction type and branch delay information. */
1522 if ((op->pinfo & INSN_UNCOND_BRANCH_DELAY) != 0)
1524 if ((op->pinfo & (INSN_WRITE_GPR_31
1525 | INSN_WRITE_GPR_D)) != 0)
1526 info->insn_type = dis_jsr;
1528 info->insn_type = dis_branch;
1529 info->branch_delay_insns = 1;
1531 else if ((op->pinfo & (INSN_COND_BRANCH_DELAY
1532 | INSN_COND_BRANCH_LIKELY)) != 0)
1534 if ((op->pinfo & INSN_WRITE_GPR_31) != 0)
1535 info->insn_type = dis_condjsr;
1537 info->insn_type = dis_condbranch;
1538 info->branch_delay_insns = 1;
1540 else if ((op->pinfo & (INSN_STORE_MEMORY
1541 | INSN_LOAD_MEMORY_DELAY)) != 0)
1542 info->insn_type = dis_dref;
1544 infprintf (is, "%s", op->name);
1547 if (d != NULL && *d != '\0')
1549 infprintf (is, "\t");
1550 print_insn_args (d, word, memaddr, info, op);
1560 /* Handle undefined instructions. */
1561 info->insn_type = dis_noninsn;
1562 infprintf (is, "0x%x", word);
1566 /* Disassemble an operand for a mips16 instruction. */
1569 print_mips16_insn_arg (char type,
1570 const struct mips_opcode *op,
1572 bfd_boolean use_extend,
1575 struct disassemble_info *info)
1577 const fprintf_ftype infprintf = info->fprintf_func;
1578 void *is = info->stream;
1580 #define GET_OP(insn, field) \
1581 (((insn) >> MIPS16OP_SH_##field) & MIPS16OP_MASK_##field)
1582 #define GET_OP_S(insn, field) \
1583 ((GET_OP (insn, field) ^ ((MIPS16OP_MASK_##field >> 1) + 1)) \
1584 - ((MIPS16OP_MASK_##field >> 1) + 1))
1590 infprintf (is, "%c", type);
1595 infprintf (is, "%s", mips16_reg_names (GET_OP (l, RY)));
1600 infprintf (is, "%s", mips16_reg_names (GET_OP (l, RX)));
1604 infprintf (is, "%s", mips16_reg_names (GET_OP (l, RZ)));
1608 infprintf (is, "%s", mips16_reg_names (GET_OP (l, MOVE32Z)));
1612 infprintf (is, "%s", mips_gpr_names[0]);
1616 infprintf (is, "%s", mips_gpr_names[29]);
1620 infprintf (is, "$pc");
1624 infprintf (is, "%s", mips_gpr_names[31]);
1628 infprintf (is, "%s", mips_gpr_names[GET_OP (l, REGR32)]);
1632 infprintf (is, "%s", mips_gpr_names[MIPS16OP_EXTRACT_REG32R (l)]);
1658 int immed, nbits, shift, signedp, extbits, pcrel, extu, branch;
1670 immed = GET_OP (l, RZ);
1676 immed = GET_OP (l, RX);
1682 immed = GET_OP (l, RZ);
1688 immed = GET_OP (l, RX);
1694 immed = GET_OP (l, IMM4);
1700 immed = GET_OP (l, IMM5);
1701 info->insn_type = dis_dref;
1702 info->data_size = 1;
1707 immed = GET_OP (l, IMM5);
1708 info->insn_type = dis_dref;
1709 info->data_size = 2;
1714 immed = GET_OP (l, IMM5);
1715 if ((op->pinfo & MIPS16_INSN_READ_PC) == 0
1716 && (op->pinfo & MIPS16_INSN_READ_SP) == 0)
1718 info->insn_type = dis_dref;
1719 info->data_size = 4;
1725 immed = GET_OP (l, IMM5);
1726 info->insn_type = dis_dref;
1727 info->data_size = 8;
1731 immed = GET_OP (l, IMM5);
1736 immed = GET_OP (l, IMM6);
1740 immed = GET_OP (l, IMM8);
1745 immed = GET_OP (l, IMM8);
1746 /* FIXME: This might be lw, or it might be addiu to $sp or
1747 $pc. We assume it's load. */
1748 info->insn_type = dis_dref;
1749 info->data_size = 4;
1754 immed = GET_OP (l, IMM8);
1755 info->insn_type = dis_dref;
1756 info->data_size = 8;
1760 immed = GET_OP (l, IMM8);
1765 immed = GET_OP (l, IMM8);
1771 immed = GET_OP (l, IMM8);
1776 immed = GET_OP (l, IMM8);
1783 immed = GET_OP (l, IMM11);
1791 immed = GET_OP (l, IMM8);
1793 /* FIXME: This can be lw or la. We assume it is lw. */
1794 info->insn_type = dis_dref;
1795 info->data_size = 4;
1800 immed = GET_OP (l, IMM5);
1802 info->insn_type = dis_dref;
1803 info->data_size = 8;
1808 immed = GET_OP (l, IMM5);
1817 if (signedp && immed >= (1 << (nbits - 1)))
1818 immed -= 1 << nbits;
1820 if ((type == '<' || type == '>' || type == '[' || type == ']')
1827 immed |= ((extend & 0x1f) << 11) | (extend & 0x7e0);
1828 else if (extbits == 15)
1829 immed |= ((extend & 0xf) << 11) | (extend & 0x7f0);
1831 immed = ((extend >> 6) & 0x1f) | (extend & 0x20);
1832 immed &= (1 << extbits) - 1;
1833 if (! extu && immed >= (1 << (extbits - 1)))
1834 immed -= 1 << extbits;
1838 infprintf (is, "%d", immed);
1846 baseaddr = memaddr + 2;
1848 else if (use_extend)
1849 baseaddr = memaddr - 2;
1857 /* If this instruction is in the delay slot of a jr
1858 instruction, the base address is the address of the
1859 jr instruction. If it is in the delay slot of jalr
1860 instruction, the base address is the address of the
1861 jalr instruction. This test is unreliable: we have
1862 no way of knowing whether the previous word is
1863 instruction or data. */
1864 status = (*info->read_memory_func) (memaddr - 4, buffer, 2,
1867 && (((info->endian == BFD_ENDIAN_BIG
1868 ? bfd_getb16 (buffer)
1869 : bfd_getl16 (buffer))
1870 & 0xf800) == 0x1800))
1871 baseaddr = memaddr - 4;
1874 status = (*info->read_memory_func) (memaddr - 2, buffer,
1877 && (((info->endian == BFD_ENDIAN_BIG
1878 ? bfd_getb16 (buffer)
1879 : bfd_getl16 (buffer))
1880 & 0xf81f) == 0xe800))
1881 baseaddr = memaddr - 2;
1884 info->target = (baseaddr & ~((1 << shift) - 1)) + immed;
1886 && info->flavour == bfd_target_unknown_flavour)
1887 /* For gdb disassembler, maintain odd address. */
1889 (*info->print_address_func) (info->target, info);
1896 int jalx = l & 0x400;
1900 l = ((l & 0x1f) << 23) | ((l & 0x3e0) << 13) | (extend << 2);
1901 if (!jalx && info->flavour == bfd_target_unknown_flavour)
1902 /* For gdb disassembler, maintain odd address. */
1905 info->target = ((memaddr + 4) & ~(bfd_vma) 0x0fffffff) | l;
1906 (*info->print_address_func) (info->target, info);
1912 int need_comma, amask, smask;
1916 l = GET_OP (l, IMM6);
1918 amask = (l >> 3) & 7;
1920 if (amask > 0 && amask < 5)
1922 infprintf (is, "%s", mips_gpr_names[4]);
1924 infprintf (is, "-%s", mips_gpr_names[amask + 3]);
1928 smask = (l >> 1) & 3;
1931 infprintf (is, "%s??", need_comma ? "," : "");
1936 infprintf (is, "%s%s", need_comma ? "," : "", mips_gpr_names[16]);
1938 infprintf (is, "-%s", mips_gpr_names[smask + 15]);
1944 infprintf (is, "%s%s", need_comma ? "," : "", mips_gpr_names[31]);
1948 if (amask == 5 || amask == 6)
1950 infprintf (is, "%s$f0", need_comma ? "," : "");
1952 infprintf (is, "-$f1");
1959 /* MIPS16e save/restore. */
1962 int amask, args, statics;
1971 amask = (l >> 16) & 0xf;
1972 if (amask == MIPS16_ALL_ARGS)
1977 else if (amask == MIPS16_ALL_STATICS)
1985 statics = amask & 3;
1989 infprintf (is, "%s", mips_gpr_names[4]);
1991 infprintf (is, "-%s", mips_gpr_names[4 + args - 1]);
1995 framesz = (((l >> 16) & 0xf0) | (l & 0x0f)) * 8;
1996 if (framesz == 0 && !use_extend)
1999 infprintf (is, "%s%d", need_comma ? "," : "", framesz);
2001 if (l & 0x40) /* $ra */
2002 infprintf (is, ",%s", mips_gpr_names[31]);
2004 nsreg = (l >> 24) & 0x7;
2006 if (l & 0x20) /* $s0 */
2008 if (l & 0x10) /* $s1 */
2010 if (nsreg > 0) /* $s2-$s8 */
2011 smask |= ((1 << nsreg) - 1) << 2;
2013 /* Find first set static reg bit. */
2014 for (i = 0; i < 9; i++)
2016 if (smask & (1 << i))
2018 infprintf (is, ",%s", mips_gpr_names[i == 8 ? 30 : (16 + i)]);
2019 /* Skip over string of set bits. */
2020 for (j = i; smask & (2 << j); j++)
2023 infprintf (is, "-%s", mips_gpr_names[j == 8 ? 30 : (16 + j)]);
2028 /* Statics $ax - $a3. */
2030 infprintf (is, ",%s", mips_gpr_names[7]);
2031 else if (statics > 0)
2032 infprintf (is, ",%s-%s",
2033 mips_gpr_names[7 - statics + 1],
2039 /* xgettext:c-format */
2041 _("# internal disassembler error, "
2042 "unrecognised modifier (%c)"),
2048 /* Disassemble mips16 instructions. */
2051 print_insn_mips16 (bfd_vma memaddr, struct disassemble_info *info)
2053 const fprintf_ftype infprintf = info->fprintf_func;
2058 bfd_boolean use_extend;
2060 const struct mips_opcode *op, *opend;
2061 void *is = info->stream;
2063 info->bytes_per_chunk = 2;
2064 info->display_endian = info->endian;
2065 info->insn_info_valid = 1;
2066 info->branch_delay_insns = 0;
2067 info->data_size = 0;
2068 info->insn_type = dis_nonbranch;
2072 status = (*info->read_memory_func) (memaddr, buffer, 2, info);
2075 (*info->memory_error_func) (status, memaddr, info);
2081 if (info->endian == BFD_ENDIAN_BIG)
2082 insn = bfd_getb16 (buffer);
2084 insn = bfd_getl16 (buffer);
2086 /* Handle the extend opcode specially. */
2088 if ((insn & 0xf800) == 0xf000)
2091 extend = insn & 0x7ff;
2095 status = (*info->read_memory_func) (memaddr, buffer, 2, info);
2098 infprintf (is, "extend 0x%x", (unsigned int) extend);
2099 (*info->memory_error_func) (status, memaddr, info);
2103 if (info->endian == BFD_ENDIAN_BIG)
2104 insn = bfd_getb16 (buffer);
2106 insn = bfd_getl16 (buffer);
2108 /* Check for an extend opcode followed by an extend opcode. */
2109 if ((insn & 0xf800) == 0xf000)
2111 infprintf (is, "extend 0x%x", (unsigned int) extend);
2112 info->insn_type = dis_noninsn;
2119 /* FIXME: Should probably use a hash table on the major opcode here. */
2121 opend = mips16_opcodes + bfd_mips16_num_opcodes;
2122 for (op = mips16_opcodes; op < opend; op++)
2124 if (op->pinfo != INSN_MACRO
2125 && !(no_aliases && (op->pinfo2 & INSN2_ALIAS))
2126 && (insn & op->mask) == op->match)
2130 if (strchr (op->args, 'a') != NULL)
2134 infprintf (is, "extend 0x%x", (unsigned int) extend);
2135 info->insn_type = dis_noninsn;
2143 status = (*info->read_memory_func) (memaddr, buffer, 2,
2148 if (info->endian == BFD_ENDIAN_BIG)
2149 extend = bfd_getb16 (buffer);
2151 extend = bfd_getl16 (buffer);
2156 infprintf (is, "%s", op->name);
2157 if (op->args[0] != '\0')
2158 infprintf (is, "\t");
2160 for (s = op->args; *s != '\0'; s++)
2164 && GET_OP (insn, RX) == GET_OP (insn, RY))
2166 /* Skip the register and the comma. */
2172 && GET_OP (insn, RZ) == GET_OP (insn, RX))
2174 /* Skip the register and the comma. */
2178 print_mips16_insn_arg (*s, op, insn, use_extend, extend, memaddr,
2182 /* Figure out branch instruction type and delay slot information. */
2183 if ((op->pinfo & INSN_UNCOND_BRANCH_DELAY) != 0)
2184 info->branch_delay_insns = 1;
2185 if ((op->pinfo & (INSN_UNCOND_BRANCH_DELAY
2186 | MIPS16_INSN_UNCOND_BRANCH)) != 0)
2188 if ((op->pinfo & INSN_WRITE_GPR_31) != 0)
2189 info->insn_type = dis_jsr;
2191 info->insn_type = dis_branch;
2193 else if ((op->pinfo & MIPS16_INSN_COND_BRANCH) != 0)
2194 info->insn_type = dis_condbranch;
2203 infprintf (is, "0x%x", extend | 0xf000);
2204 infprintf (is, "0x%x", insn);
2205 info->insn_type = dis_noninsn;
2210 /* Disassemble microMIPS instructions. */
2213 print_insn_micromips (bfd_vma memaddr, struct disassemble_info *info)
2215 const fprintf_ftype infprintf = info->fprintf_func;
2216 const struct mips_opcode *op, *opend;
2217 unsigned int lsb, msbd, msb;
2218 void *is = info->stream;
2231 info->bytes_per_chunk = 2;
2232 info->display_endian = info->endian;
2233 info->insn_info_valid = 1;
2234 info->branch_delay_insns = 0;
2235 info->data_size = 0;
2236 info->insn_type = dis_nonbranch;
2240 status = (*info->read_memory_func) (memaddr, buffer, 2, info);
2243 (*info->memory_error_func) (status, memaddr, info);
2249 if (info->endian == BFD_ENDIAN_BIG)
2250 insn = bfd_getb16 (buffer);
2252 insn = bfd_getl16 (buffer);
2254 if ((insn & 0xfc00) == 0x7c00)
2256 /* This is a 48-bit microMIPS instruction. */
2259 status = (*info->read_memory_func) (memaddr + 2, buffer, 2, info);
2262 infprintf (is, "micromips 0x%x", higher);
2263 (*info->memory_error_func) (status, memaddr + 2, info);
2266 if (info->endian == BFD_ENDIAN_BIG)
2267 insn = bfd_getb16 (buffer);
2269 insn = bfd_getl16 (buffer);
2270 higher = (higher << 16) | insn;
2272 status = (*info->read_memory_func) (memaddr + 4, buffer, 2, info);
2275 infprintf (is, "micromips 0x%x", higher);
2276 (*info->memory_error_func) (status, memaddr + 4, info);
2279 if (info->endian == BFD_ENDIAN_BIG)
2280 insn = bfd_getb16 (buffer);
2282 insn = bfd_getl16 (buffer);
2283 infprintf (is, "0x%x%04x (48-bit insn)", higher, insn);
2285 info->insn_type = dis_noninsn;
2288 else if ((insn & 0x1c00) == 0x0000 || (insn & 0x1000) == 0x1000)
2290 /* This is a 32-bit microMIPS instruction. */
2293 status = (*info->read_memory_func) (memaddr + 2, buffer, 2, info);
2296 infprintf (is, "micromips 0x%x", higher);
2297 (*info->memory_error_func) (status, memaddr + 2, info);
2301 if (info->endian == BFD_ENDIAN_BIG)
2302 insn = bfd_getb16 (buffer);
2304 insn = bfd_getl16 (buffer);
2306 insn = insn | (higher << 16);
2311 /* FIXME: Should probably use a hash table on the major opcode here. */
2313 #define GET_OP(insn, field) \
2314 (((insn) >> MICROMIPSOP_SH_##field) & MICROMIPSOP_MASK_##field)
2315 #define GET_OP_S(insn, field) \
2316 ((GET_OP (insn, field) ^ ((MICROMIPSOP_MASK_##field >> 1) + 1)) \
2317 - ((MICROMIPSOP_MASK_##field >> 1) + 1))
2318 opend = micromips_opcodes + bfd_micromips_num_opcodes;
2319 for (op = micromips_opcodes; op < opend; op++)
2321 if (op->pinfo != INSN_MACRO
2322 && !(no_aliases && (op->pinfo2 & INSN2_ALIAS))
2323 && (insn & op->mask) == op->match
2324 && ((length == 2 && (op->mask & 0xffff0000) == 0)
2325 || (length == 4 && (op->mask & 0xffff0000) != 0)))
2329 infprintf (is, "%s", op->name);
2330 if (op->args[0] != '\0')
2331 infprintf (is, "\t");
2333 for (s = op->args; *s != '\0'; s++)
2340 infprintf (is, "%c", *s);
2344 infprintf (is, "%d", GET_OP_S (insn, OFFSET10));
2348 infprintf (is, "0x%x", GET_OP (insn, STYPE));
2352 infprintf (is, "0x%x", GET_OP (insn, BP));
2356 infprintf (is, "0x%x", GET_OP (insn, SA3));
2360 infprintf (is, "0x%x", GET_OP (insn, SA4));
2364 infprintf (is, "0x%x", GET_OP (insn, IMM8));
2368 infprintf (is, "0x%x", GET_OP (insn, RS));
2372 infprintf (is, "$ac%d", GET_OP (insn, DSPACC));
2376 infprintf (is, "0x%x", GET_OP (insn, WRDSP));
2379 case '0': /* DSP 6-bit signed immediate in bit 16. */
2380 delta = (GET_OP (insn, DSPSFT) ^ 0x20) - 0x20;
2381 infprintf (is, "%d", delta);
2385 infprintf (is, "0x%x", GET_OP (insn, SHAMT));
2389 infprintf (is, "0x%x", GET_OP (insn, 3BITPOS));
2393 infprintf (is, "0x%x", GET_OP (insn, RD));
2397 infprintf (is, "0x%x", GET_OP (insn, TRAP));
2401 infprintf (is, "%d", GET_OP_S (insn, OFFSET12));
2405 if (strcmp (op->name, "jalx") == 0)
2406 info->target = (((memaddr + 4) & ~(bfd_vma) 0x0fffffff)
2407 | (GET_OP (insn, TARGET) << 2));
2409 info->target = (((memaddr + 4) & ~(bfd_vma) 0x07ffffff)
2410 | (GET_OP (insn, TARGET) << 1));
2411 /* For gdb disassembler, force odd address on jalx. */
2412 if (info->flavour == bfd_target_unknown_flavour
2413 && strcmp (op->name, "jalx") == 0)
2415 (*info->print_address_func) (info->target, info);
2422 infprintf (is, "%s", mips_gpr_names[GET_OP (insn, RS)]);
2426 infprintf (is, "0x%x", GET_OP (insn, CODE));
2430 infprintf (is, "%s", mips_gpr_names[GET_OP (insn, RD)]);
2434 infprintf (is, "0x%x", GET_OP (insn, PREFX));
2439 infprintf (is, "0x%x", GET_OP (insn, IMMEDIATE));
2442 case 'j': /* Same as i, but sign-extended. */
2444 infprintf (is, "%d", GET_OP_S (insn, DELTA));
2448 infprintf (is, "0x%x", GET_OP (insn, CACHE));
2455 immed = GET_OP (insn, RT);
2456 s_reg_encode = immed & 0xf;
2457 if (s_reg_encode != 0)
2459 if (s_reg_encode == 1)
2460 infprintf (is, "%s", mips_gpr_names[16]);
2461 else if (s_reg_encode < 9)
2462 infprintf (is, "%s-%s",
2464 mips_gpr_names[15 + s_reg_encode]);
2465 else if (s_reg_encode == 9)
2466 infprintf (is, "%s-%s,%s",
2469 mips_gpr_names[30]);
2471 infprintf (is, "UNKNOWN");
2474 if (immed & 0x10) /* For ra. */
2476 if (s_reg_encode == 0)
2477 infprintf (is, "%s", mips_gpr_names[31]);
2479 infprintf (is, ",%s", mips_gpr_names[31]);
2485 /* Sign-extend the displacement. */
2486 delta = GET_OP_S (insn, DELTA);
2487 info->target = (delta << 1) + memaddr + length;
2488 (*info->print_address_func) (info->target, info);
2492 infprintf (is, "0x%x", GET_OP (insn, CODE2));
2497 infprintf (is, "%s", mips_gpr_names[GET_OP (insn, RT)]);
2501 infprintf (is, "%s", mips_gpr_names[GET_OP (insn, RS3)]);
2505 infprintf (is, "%s", mips_gpr_names[0]);
2508 case '@': /* DSP 10-bit signed immediate in bit 16. */
2509 delta = (GET_OP (insn, IMM10) ^ 0x200) - 0x200;
2510 infprintf (is, "%d", delta);
2514 infprintf (is, "0x%x", GET_OP (insn, CODE10));
2518 infprintf (is, "0x%x", GET_OP (insn, COPZ));
2522 infprintf (is, "%s", mips_fpr_names[GET_OP (insn, FD)]);
2526 /* Coprocessor register for lwcN instructions, et al.
2528 Note that there is no load/store cp0 instructions, and
2529 that FPU (cp1) instructions disassemble this field using
2530 'T' format. Therefore, until we gain understanding of
2531 cp2 register names, we can simply print the register
2533 infprintf (is, "$%d", GET_OP (insn, RT));
2537 /* Coprocessor register for mtcN instructions, et al. Note
2538 that FPU (cp1) instructions disassemble this field using
2539 'S' format. Therefore, we only need to worry about cp0,
2541 The microMIPS encoding does not have a coprocessor
2542 identifier field as such, so we must work out the
2543 coprocessor number by looking at the opcode. */
2545 & ~((MICROMIPSOP_MASK_RT << MICROMIPSOP_SH_RT)
2546 | (MICROMIPSOP_MASK_RS << MICROMIPSOP_SH_RS)))
2548 case 0x000000fc: /* mfc0 */
2549 case 0x000002fc: /* mtc0 */
2550 case 0x580000fc: /* dmfc0 */
2551 case 0x580002fc: /* dmtc0 */
2552 infprintf (is, "%s", mips_cp0_names[GET_OP (insn, RS)]);
2555 infprintf (is, "$%d", GET_OP (insn, RS));
2561 infprintf (is, "%d", GET_OP (insn, SEL));
2565 infprintf (is, "%s", mips_hwr_names[GET_OP (insn, RS)]);
2569 infprintf (is, "$fcc%d", GET_OP (insn, CCC));
2574 (op->pinfo & (FP_D | FP_S)) != 0
2575 ? "$fcc%d" : "$cc%d",
2576 GET_OP (insn, BCC));
2580 infprintf (is, "%s", mips_fpr_names[GET_OP (insn, FR)]);
2585 infprintf (is, "%s", mips_fpr_names[GET_OP (insn, FS)]);
2589 infprintf (is, "%s", mips_fpr_names[GET_OP (insn, FT)]);
2593 /* Extension character; switch for second char. */
2598 lsb = GET_OP (insn, EXTLSB);
2599 infprintf (is, "0x%x", lsb);
2603 msb = GET_OP (insn, INSMSB);
2604 infprintf (is, "0x%x", msb - lsb + 1);
2609 msbd = GET_OP (insn, EXTMSBD);
2610 infprintf (is, "0x%x", msbd + 1);
2615 const struct mips_cp0sel_name *n;
2616 unsigned int cp0reg, sel;
2618 cp0reg = GET_OP (insn, RS);
2619 sel = GET_OP (insn, SEL);
2621 /* CP0 register including 'sel' code for mtcN
2622 (et al.), to be printed textually if known.
2623 If not known, print both CP0 register name and
2624 sel numerically since CP0 register with sel 0 may
2625 have a name unrelated to register being printed. */
2626 n = lookup_mips_cp0sel_name (mips_cp0sel_names,
2627 mips_cp0sel_names_len,
2630 infprintf (is, "%s", n->name);
2632 infprintf (is, "$%d,%d", cp0reg, sel);
2637 lsb = GET_OP (insn, EXTLSB) + 32;
2638 infprintf (is, "0x%x", lsb);
2642 msb = GET_OP (insn, INSMSB) + 32;
2643 infprintf (is, "0x%x", msb - lsb + 1);
2647 msbd = GET_OP (insn, EXTMSBD) + 32;
2648 infprintf (is, "0x%x", msbd + 1);
2652 /* xgettext:c-format */
2654 _("# internal disassembler error, "
2655 "unrecognized modifier (+%c)"),
2662 /* Extension character; switch for second char. */
2666 case 'a': /* global pointer. */
2667 infprintf (is, "%s", mips_gpr_names[28]);
2671 regno = micromips_to_32_reg_b_map[GET_OP (insn, MB)];
2672 infprintf (is, "%s", mips_gpr_names[regno]);
2676 regno = micromips_to_32_reg_c_map[GET_OP (insn, MC)];
2677 infprintf (is, "%s", mips_gpr_names[regno]);
2681 regno = micromips_to_32_reg_d_map[GET_OP (insn, MD)];
2682 infprintf (is, "%s", mips_gpr_names[regno]);
2686 regno = micromips_to_32_reg_e_map[GET_OP (insn, ME)];
2687 infprintf (is, "%s", mips_gpr_names[regno]);
2691 /* Save lastregno for "mt" to print out later. */
2692 lastregno = micromips_to_32_reg_f_map[GET_OP (insn, MF)];
2693 infprintf (is, "%s", mips_gpr_names[lastregno]);
2697 regno = micromips_to_32_reg_g_map[GET_OP (insn, MG)];
2698 infprintf (is, "%s", mips_gpr_names[regno]);
2702 regno = micromips_to_32_reg_h_map[GET_OP (insn, MH)];
2703 infprintf (is, "%s", mips_gpr_names[regno]);
2707 regno = micromips_to_32_reg_i_map[GET_OP (insn, MI)];
2708 infprintf (is, "%s", mips_gpr_names[regno]);
2712 infprintf (is, "%s", mips_gpr_names[GET_OP (insn, MJ)]);
2716 regno = micromips_to_32_reg_l_map[GET_OP (insn, ML)];
2717 infprintf (is, "%s", mips_gpr_names[regno]);
2721 regno = micromips_to_32_reg_m_map[GET_OP (insn, MM)];
2722 infprintf (is, "%s", mips_gpr_names[regno]);
2726 regno = micromips_to_32_reg_n_map[GET_OP (insn, MN)];
2727 infprintf (is, "%s", mips_gpr_names[regno]);
2731 /* Save lastregno for "mt" to print out later. */
2732 lastregno = GET_OP (insn, MP);
2733 infprintf (is, "%s", mips_gpr_names[lastregno]);
2737 regno = micromips_to_32_reg_q_map[GET_OP (insn, MQ)];
2738 infprintf (is, "%s", mips_gpr_names[regno]);
2741 case 'r': /* program counter. */
2742 infprintf (is, "$pc");
2745 case 's': /* stack pointer. */
2747 infprintf (is, "%s", mips_gpr_names[29]);
2751 infprintf (is, "%s", mips_gpr_names[lastregno]);
2755 infprintf (is, "%s", mips_gpr_names[0]);
2759 /* Sign-extend the immediate. */
2760 immed = GET_OP_S (insn, IMMA) << 2;
2761 infprintf (is, "%d", immed);
2765 immed = micromips_imm_b_map[GET_OP (insn, IMMB)];
2766 infprintf (is, "%d", immed);
2770 immed = micromips_imm_c_map[GET_OP (insn, IMMC)];
2771 infprintf (is, "0x%x", immed);
2775 /* Sign-extend the displacement. */
2776 delta = GET_OP_S (insn, IMMD);
2777 info->target = (delta << 1) + memaddr + length;
2778 (*info->print_address_func) (info->target, info);
2782 /* Sign-extend the displacement. */
2783 delta = GET_OP_S (insn, IMME);
2784 info->target = (delta << 1) + memaddr + length;
2785 (*info->print_address_func) (info->target, info);
2789 immed = GET_OP (insn, IMMF);
2790 infprintf (is, "0x%x", immed);
2794 immed = (insn >> MICROMIPSOP_SH_IMMG) + 1;
2795 immed = (immed & MICROMIPSOP_MASK_IMMG) - 1;
2796 infprintf (is, "%d", immed);
2800 immed = GET_OP (insn, IMMH) << 1;
2801 infprintf (is, "%d", immed);
2805 immed = (insn >> MICROMIPSOP_SH_IMMI) + 1;
2806 immed = (immed & MICROMIPSOP_MASK_IMMI) - 1;
2807 infprintf (is, "%d", immed);
2811 immed = GET_OP (insn, IMMJ) << 2;
2812 infprintf (is, "%d", immed);
2816 immed = GET_OP (insn, IMML);
2817 infprintf (is, "%d", immed);
2821 immed = (insn >> MICROMIPSOP_SH_IMMM) - 1;
2822 immed = (immed & MICROMIPSOP_MASK_IMMM) + 1;
2823 infprintf (is, "%d", immed);
2827 immed = GET_OP (insn, IMMN);
2829 infprintf (is, "%s,%s",
2831 mips_gpr_names[31]);
2833 infprintf (is, "%s-%s,%s",
2835 mips_gpr_names[16 + immed],
2836 mips_gpr_names[31]);
2840 immed = GET_OP (insn, IMMO);
2841 infprintf (is, "0x%x", immed);
2845 immed = GET_OP (insn, IMMP) << 2;
2846 infprintf (is, "%d", immed);
2850 /* Sign-extend the immediate. */
2851 immed = GET_OP_S (insn, IMMQ) << 2;
2852 infprintf (is, "%d", immed);
2856 immed = GET_OP (insn, IMMU) << 2;
2857 infprintf (is, "%d", immed);
2861 immed = GET_OP (insn, IMMW) << 2;
2862 infprintf (is, "%d", immed);
2866 /* Sign-extend the immediate. */
2867 immed = GET_OP_S (insn, IMMX);
2868 infprintf (is, "%d", immed);
2872 /* Sign-extend the immediate. */
2873 immed = GET_OP_S (insn, IMMY) << 2;
2874 if ((unsigned int) (immed + 8) < 16)
2876 infprintf (is, "%d", immed);
2880 /* xgettext:c-format */
2882 _("# internal disassembler error, "
2883 "unrecognized modifier (m%c)"),
2890 /* xgettext:c-format */
2892 _("# internal disassembler error, "
2893 "unrecognized modifier (%c)"),
2899 /* Figure out instruction type and branch delay information. */
2901 & (INSN_UNCOND_BRANCH_DELAY | INSN_COND_BRANCH_DELAY)) != 0)
2902 info->branch_delay_insns = 1;
2903 if (((op->pinfo & INSN_UNCOND_BRANCH_DELAY)
2904 | (op->pinfo2 & INSN2_UNCOND_BRANCH)) != 0)
2906 if ((op->pinfo & (INSN_WRITE_GPR_31 | INSN_WRITE_GPR_T)) != 0)
2907 info->insn_type = dis_jsr;
2909 info->insn_type = dis_branch;
2911 else if (((op->pinfo & INSN_COND_BRANCH_DELAY)
2912 | (op->pinfo2 & INSN2_COND_BRANCH)) != 0)
2914 if ((op->pinfo & INSN_WRITE_GPR_31) != 0)
2915 info->insn_type = dis_condjsr;
2917 info->insn_type = dis_condbranch;
2920 & (INSN_STORE_MEMORY | INSN_LOAD_MEMORY_DELAY)) != 0)
2921 info->insn_type = dis_dref;
2929 infprintf (is, "0x%x", insn);
2930 info->insn_type = dis_noninsn;
2935 /* Return 1 if a symbol associated with the location being disassembled
2936 indicates a compressed (MIPS16 or microMIPS) mode. We iterate over
2937 all the symbols at the address being considered assuming if at least
2938 one of them indicates code compression, then such code has been
2939 genuinely produced here (other symbols could have been derived from
2940 function symbols defined elsewhere or could define data). Otherwise,
2944 is_compressed_mode_p (struct disassemble_info *info)
2946 elf_symbol_type *symbol;
2950 for (i = 0; i < info->num_symbols; i++)
2952 pos = info->symtab_pos + i;
2954 if (bfd_asymbol_flavour (info->symtab[pos]) != bfd_target_elf_flavour)
2957 if (info->symtab[pos]->section != info->section)
2960 symbol = (elf_symbol_type *) info->symtab[pos];
2962 && ELF_ST_IS_MIPS16 (symbol->internal_elf_sym.st_other))
2964 && ELF_ST_IS_MICROMIPS (symbol->internal_elf_sym.st_other)))
2971 /* In an environment where we do not know the symbol type of the
2972 instruction we are forced to assume that the low order bit of the
2973 instructions' address may mark it as a mips16 instruction. If we
2974 are single stepping, or the pc is within the disassembled function,
2975 this works. Otherwise, we need a clue. Sometimes. */
2978 _print_insn_mips (bfd_vma memaddr,
2979 struct disassemble_info *info,
2980 enum bfd_endian endianness)
2982 int (*print_insn_compr) (bfd_vma, struct disassemble_info *);
2983 bfd_byte buffer[INSNLEN];
2986 set_default_mips_dis_options (info);
2987 parse_mips_dis_options (info->disassembler_options);
2989 if (info->mach == bfd_mach_mips16)
2990 return print_insn_mips16 (memaddr, info);
2991 if (info->mach == bfd_mach_mips_micromips)
2992 return print_insn_micromips (memaddr, info);
2994 print_insn_compr = !micromips_ase ? print_insn_mips16 : print_insn_micromips;
2997 /* FIXME: If odd address, this is CLEARLY a compressed instruction. */
2998 /* Only a few tools will work this way. */
3000 return print_insn_compr (memaddr, info);
3003 #if SYMTAB_AVAILABLE
3004 if (is_compressed_mode_p (info))
3005 return print_insn_compr (memaddr, info);
3008 status = (*info->read_memory_func) (memaddr, buffer, INSNLEN, info);
3013 if (endianness == BFD_ENDIAN_BIG)
3014 insn = bfd_getb32 (buffer);
3016 insn = bfd_getl32 (buffer);
3018 return print_insn_mips (memaddr, insn, info);
3022 (*info->memory_error_func) (status, memaddr, info);
3028 print_insn_big_mips (bfd_vma memaddr, struct disassemble_info *info)
3030 return _print_insn_mips (memaddr, info, BFD_ENDIAN_BIG);
3034 print_insn_little_mips (bfd_vma memaddr, struct disassemble_info *info)
3036 return _print_insn_mips (memaddr, info, BFD_ENDIAN_LITTLE);
3040 print_mips_disassembler_options (FILE *stream)
3044 fprintf (stream, _("\n\
3045 The following MIPS specific disassembler options are supported for use\n\
3046 with the -M switch (multiple options should be separated by commas):\n"));
3048 fprintf (stream, _("\n\
3049 virt Recognize the virtualization ASE instructions.\n"));
3051 fprintf (stream, _("\n\
3052 gpr-names=ABI Print GPR names according to specified ABI.\n\
3053 Default: based on binary being disassembled.\n"));
3055 fprintf (stream, _("\n\
3056 fpr-names=ABI Print FPR names according to specified ABI.\n\
3057 Default: numeric.\n"));
3059 fprintf (stream, _("\n\
3060 cp0-names=ARCH Print CP0 register names according to\n\
3061 specified architecture.\n\
3062 Default: based on binary being disassembled.\n"));
3064 fprintf (stream, _("\n\
3065 hwr-names=ARCH Print HWR names according to specified \n\
3067 Default: based on binary being disassembled.\n"));
3069 fprintf (stream, _("\n\
3070 reg-names=ABI Print GPR and FPR names according to\n\
3071 specified ABI.\n"));
3073 fprintf (stream, _("\n\
3074 reg-names=ARCH Print CP0 register and HWR names according to\n\
3075 specified architecture.\n"));
3077 fprintf (stream, _("\n\
3078 For the options above, the following values are supported for \"ABI\":\n\
3080 for (i = 0; i < ARRAY_SIZE (mips_abi_choices); i++)
3081 fprintf (stream, " %s", mips_abi_choices[i].name);
3082 fprintf (stream, _("\n"));
3084 fprintf (stream, _("\n\
3085 For the options above, The following values are supported for \"ARCH\":\n\
3087 for (i = 0; i < ARRAY_SIZE (mips_arch_choices); i++)
3088 if (*mips_arch_choices[i].name != '\0')
3089 fprintf (stream, " %s", mips_arch_choices[i].name);
3090 fprintf (stream, _("\n"));
3092 fprintf (stream, _("\n"));