1 /* Print mips instructions for GDB, the GNU debugger, or for objdump.
2 Copyright 1989, 91-97, 1998 Free Software Foundation, Inc.
3 Contributed by Nobuyuki Hikichi(hikichi@sra.co.jp).
5 This file is part of GDB, GAS, and the GNU binutils.
7 This program is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 2 of the License, or
10 (at your option) any later version.
12 This program is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
17 You should have received a copy of the GNU General Public License
18 along with this program; if not, write to the Free Software
19 Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */
24 #include "opcode/mips.h"
26 /* FIXME: These are needed to figure out if this is a mips16 symbol or
27 not. It would be better to think of a cleaner way to do this. */
31 static int print_insn_mips16 PARAMS ((bfd_vma, struct disassemble_info *));
32 static void print_mips16_insn_arg
33 PARAMS ((int, const struct mips_opcode *, int, boolean, int, bfd_vma,
34 struct disassemble_info *));
36 /* Mips instructions are never longer than this many bytes. */
39 static void print_insn_arg PARAMS ((const char *, unsigned long, bfd_vma,
40 struct disassemble_info *));
41 static int _print_insn_mips PARAMS ((bfd_vma, unsigned long int,
42 struct disassemble_info *));
45 /* FIXME: This should be shared with gdb somehow. */
46 #define REGISTER_NAMES \
47 { "zero", "at", "v0", "v1", "a0", "a1", "a2", "a3", \
48 "t0", "t1", "t2", "t3", "t4", "t5", "t6", "t7", \
49 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7", \
50 "t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra", \
51 "sr", "lo", "hi", "bad", "cause","pc", \
52 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7", \
53 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15", \
54 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",\
55 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31",\
56 "fsr", "fir", "fp", "inx", "rand", "tlblo","ctxt", "tlbhi",\
60 static CONST char * CONST reg_names[] = REGISTER_NAMES;
62 /* The mips16 register names. */
63 static const char * const mips16_reg_names[] =
65 "s0", "s1", "v0", "v1", "a0", "a1", "a2", "a3"
70 print_insn_arg (d, l, pc, info)
72 register unsigned long int l;
74 struct disassemble_info *info;
83 /* start-sanitize-vr5400 */
86 /* end-sanitize-vr5400 */
87 (*info->fprintf_func) (info->stream, "%c", *d);
94 (*info->fprintf_func) (info->stream, "$%s",
95 reg_names[(l >> OP_SH_RS) & OP_MASK_RS]);
100 (*info->fprintf_func) (info->stream, "$%s",
101 reg_names[(l >> OP_SH_RT) & OP_MASK_RT]);
106 (*info->fprintf_func) (info->stream, "0x%x",
107 (l >> OP_SH_IMMEDIATE) & OP_MASK_IMMEDIATE);
110 case 'j': /* same as i, but sign-extended */
112 delta = (l >> OP_SH_DELTA) & OP_MASK_DELTA;
115 (*info->fprintf_func) (info->stream, "%d",
120 (*info->fprintf_func) (info->stream, "0x%x",
121 (unsigned int) ((l >> OP_SH_PREFX)
126 (*info->fprintf_func) (info->stream, "0x%x",
127 (unsigned int) ((l >> OP_SH_CACHE)
132 (*info->print_address_func)
133 (((pc & 0xF0000000) | (((l >> OP_SH_TARGET) & OP_MASK_TARGET) << 2)),
138 /* sign extend the displacement */
139 delta = (l >> OP_SH_DELTA) & OP_MASK_DELTA;
142 (*info->print_address_func)
143 ((delta << 2) + pc + 4,
148 (*info->fprintf_func) (info->stream, "$%s",
149 reg_names[(l >> OP_SH_RD) & OP_MASK_RD]);
153 (*info->fprintf_func) (info->stream, "$%s", reg_names[0]);
157 (*info->fprintf_func) (info->stream, "0x%x",
158 (l >> OP_SH_SHAMT) & OP_MASK_SHAMT);
162 (*info->fprintf_func) (info->stream, "0x%x",
163 (l >> OP_SH_CODE) & OP_MASK_CODE);
167 (*info->fprintf_func) (info->stream, "0x%x",
168 (l >> OP_SH_COPZ) & OP_MASK_COPZ);
172 (*info->fprintf_func) (info->stream, "0x%x",
173 (l >> OP_SH_SYSCALL) & OP_MASK_SYSCALL);
178 (*info->fprintf_func) (info->stream, "$f%d",
179 (l >> OP_SH_FS) & OP_MASK_FS);
184 (*info->fprintf_func) (info->stream, "$f%d",
185 (l >> OP_SH_FT) & OP_MASK_FT);
189 (*info->fprintf_func) (info->stream, "$f%d",
190 (l >> OP_SH_FD) & OP_MASK_FD);
194 (*info->fprintf_func) (info->stream, "$f%d",
195 (l >> OP_SH_FR) & OP_MASK_FR);
199 (*info->fprintf_func) (info->stream, "$%d",
200 (l >> OP_SH_RT) & OP_MASK_RT);
204 (*info->fprintf_func) (info->stream, "$%d",
205 (l >> OP_SH_RD) & OP_MASK_RD);
209 (*info->fprintf_func) (info->stream, "$fcc%d",
210 (l >> OP_SH_BCC) & OP_MASK_BCC);
214 (*info->fprintf_func) (info->stream, "$fcc%d",
215 (l >> OP_SH_CCC) & OP_MASK_CCC);
219 (*info->fprintf_func) (info->stream, "$%d",
220 (l >> OP_SH_PERFREG) & OP_MASK_PERFREG);
223 /* start-sanitize-vr5400 */
225 (*info->fprintf_func) (info->stream, "%d",
226 (l >> OP_SH_VECBYTE) & OP_MASK_VECBYTE);
230 (*info->fprintf_func) (info->stream, "%d",
231 (l >> OP_SH_VECALIGN) & OP_MASK_VECALIGN);
233 /* end-sanitize-vr5400 */
236 (*info->fprintf_func) (info->stream,
237 "# internal error, undefined modifier(%c)", *d);
242 /* Print the mips instruction at address MEMADDR in debugged memory,
243 on using INFO. Returns length of the instruction, in bytes, which is
244 always 4. BIGENDIAN must be 1 if this is big-endian code, 0 if
245 this is little-endian code. */
248 _print_insn_mips (memaddr, word, info)
250 unsigned long int word;
251 struct disassemble_info *info;
253 register const struct mips_opcode *op;
254 int target_processor, mips_isa;
255 static boolean init = 0;
256 static const struct mips_opcode *mips_hash[OP_MASK_OP + 1];
258 /* Build a hash table to shorten the search time. */
263 for (i = 0; i <= OP_MASK_OP; i++)
265 for (op = mips_opcodes; op < &mips_opcodes[NUMOPCODES]; op++)
267 if (op->pinfo == INSN_MACRO)
269 if (i == ((op->match >> OP_SH_OP) & OP_MASK_OP))
282 /* start-sanitize-tx19 */
283 case bfd_mach_mips1900:
284 target_processor = 1900;
287 /* end-sanitize-tx19 */
288 case bfd_mach_mips3000:
289 target_processor = 3000;
292 case bfd_mach_mips3900:
293 target_processor = 3900;
296 case bfd_mach_mips4000:
297 target_processor = 4000;
300 case bfd_mach_mips4010:
301 target_processor = 4010;
304 case bfd_mach_mips4100:
305 target_processor = 4100;
308 case bfd_mach_mips4300:
309 target_processor = 4300;
312 case bfd_mach_mips4400:
313 target_processor = 4400;
316 case bfd_mach_mips4600:
317 target_processor = 4600;
320 case bfd_mach_mips4650:
321 target_processor = 4650;
324 /* start-sanitize-tx49 */
325 case bfd_mach_mips4900:
326 target_processor = 4900;
329 /* end-sanitize-tx49 */
330 case bfd_mach_mips5000:
331 target_processor = 5000;
334 /* start-sanitize-vr5400 */
335 case bfd_mach_mips5400:
336 target_processor = 5400;
339 /* end-sanitize-vr5400 */
340 /* start-sanitize-r5900 */
341 case bfd_mach_mips5900:
342 target_processor = 5900;
345 /* end-sanitize-r5900 */
346 case bfd_mach_mips6000:
347 target_processor = 6000;
350 case bfd_mach_mips8000:
351 target_processor = 8000;
354 case bfd_mach_mips10000:
355 target_processor = 10000;
358 case bfd_mach_mips16:
359 target_processor = 16;
363 target_processor = 3000;
369 info->bytes_per_chunk = 4;
370 info->display_endian = info->endian;
372 op = mips_hash[(word >> OP_SH_OP) & OP_MASK_OP];
375 for (; op < &mips_opcodes[NUMOPCODES]; op++)
377 if (op->pinfo != INSN_MACRO && (word & op->mask) == op->match)
379 register const char *d;
382 if ((op->membership & INSN_ISA) == INSN_ISA1)
384 else if ((op->membership & INSN_ISA) == INSN_ISA2)
386 else if ((op->membership & INSN_ISA) == INSN_ISA3)
388 else if ((op->membership & INSN_ISA) == INSN_ISA4)
393 if (insn_isa > mips_isa
394 && (target_processor == 4650
395 && op->membership & INSN_4650) == 0
396 && (target_processor == 4010
397 && op->membership & INSN_4010) == 0
398 && (target_processor == 4100
399 && op->membership & INSN_4100) == 0
400 /* start-sanitize-vr5400 */
401 && (target_processor == 5400
402 && op->membership & INSN_5400) == 0
403 /* end-santiize-vr5400 */
404 /* start-sanitize-r5900 */
405 && (target_processor == 5900
406 && op->membership & INSN_5900) == 0
407 /* end-sanitize-r5900 */
408 /* start-sanitize-tx49 */
409 && (target_processor == 4900
410 && op->membership & INSN_4900) == 0
411 /* end-sanitize-tx49 */
412 && (target_processor == 3900
413 && op->membership & INSN_3900) == 0)
416 (*info->fprintf_func) (info->stream, "%s", op->name);
419 if (d != NULL && *d != '\0')
421 (*info->fprintf_func) (info->stream, "\t");
422 for (; *d != '\0'; d++)
423 print_insn_arg (d, word, memaddr, info);
431 /* Handle undefined instructions. */
432 (*info->fprintf_func) (info->stream, "0x%x", word);
437 print_insn_big_mips (memaddr, info)
439 struct disassemble_info *info;
445 || (info->flavour == bfd_target_elf_flavour
446 && info->symbol != NULL
447 && (((elf_symbol_type *) info->symbol)->internal_elf_sym.st_other
449 return print_insn_mips16 (memaddr, info);
451 status = (*info->read_memory_func) (memaddr, buffer, 4, info);
453 return _print_insn_mips (memaddr, (unsigned long) bfd_getb32 (buffer),
457 (*info->memory_error_func) (status, memaddr, info);
463 print_insn_little_mips (memaddr, info)
465 struct disassemble_info *info;
470 /* start-sanitize-sky */
472 if (bfd_mach_dvp_p (info->mach)
473 || (info->flavour == bfd_target_elf_flavour
474 && info->symbol != NULL
475 && STO_DVP_P (((elf_symbol_type *) info->symbol)->internal_elf_sym.st_other)))
476 return print_insn_dvp (memaddr, info);
478 /* end-sanitize-sky */
481 || (info->flavour == bfd_target_elf_flavour
482 && info->symbol != NULL
483 && (((elf_symbol_type *) info->symbol)->internal_elf_sym.st_other
485 return print_insn_mips16 (memaddr, info);
487 status = (*info->read_memory_func) (memaddr, buffer, 4, info);
489 return _print_insn_mips (memaddr, (unsigned long) bfd_getl32 (buffer),
493 (*info->memory_error_func) (status, memaddr, info);
498 /* Disassemble mips16 instructions. */
501 print_insn_mips16 (memaddr, info)
503 struct disassemble_info *info;
511 const struct mips_opcode *op, *opend;
513 info->bytes_per_chunk = 2;
514 info->display_endian = info->endian;
516 info->insn_info_valid = 1;
517 info->branch_delay_insns = 0;
519 info->insn_type = dis_nonbranch;
523 status = (*info->read_memory_func) (memaddr, buffer, 2, info);
526 (*info->memory_error_func) (status, memaddr, info);
532 if (info->endian == BFD_ENDIAN_BIG)
533 insn = bfd_getb16 (buffer);
535 insn = bfd_getl16 (buffer);
537 /* Handle the extend opcode specially. */
539 if ((insn & 0xf800) == 0xf000)
542 extend = insn & 0x7ff;
546 status = (*info->read_memory_func) (memaddr, buffer, 2, info);
549 (*info->fprintf_func) (info->stream, "extend 0x%x",
550 (unsigned int) extend);
551 (*info->memory_error_func) (status, memaddr, info);
555 if (info->endian == BFD_ENDIAN_BIG)
556 insn = bfd_getb16 (buffer);
558 insn = bfd_getl16 (buffer);
560 /* Check for an extend opcode followed by an extend opcode. */
561 if ((insn & 0xf800) == 0xf000)
563 (*info->fprintf_func) (info->stream, "extend 0x%x",
564 (unsigned int) extend);
565 info->insn_type = dis_noninsn;
572 /* FIXME: Should probably use a hash table on the major opcode here. */
574 opend = mips16_opcodes + bfd_mips16_num_opcodes;
575 for (op = mips16_opcodes; op < opend; op++)
577 if (op->pinfo != INSN_MACRO && (insn & op->mask) == op->match)
581 if (strchr (op->args, 'a') != NULL)
585 (*info->fprintf_func) (info->stream, "extend 0x%x",
586 (unsigned int) extend);
587 info->insn_type = dis_noninsn;
595 status = (*info->read_memory_func) (memaddr, buffer, 2,
600 if (info->endian == BFD_ENDIAN_BIG)
601 extend = bfd_getb16 (buffer);
603 extend = bfd_getl16 (buffer);
608 (*info->fprintf_func) (info->stream, "%s", op->name);
609 if (op->args[0] != '\0')
610 (*info->fprintf_func) (info->stream, "\t");
612 for (s = op->args; *s != '\0'; s++)
616 && (((insn >> MIPS16OP_SH_RX) & MIPS16OP_MASK_RX)
617 == ((insn >> MIPS16OP_SH_RY) & MIPS16OP_MASK_RY)))
619 /* Skip the register and the comma. */
625 && (((insn >> MIPS16OP_SH_RZ) & MIPS16OP_MASK_RZ)
626 == ((insn >> MIPS16OP_SH_RX) & MIPS16OP_MASK_RX)))
628 /* Skip the register and the comma. */
632 print_mips16_insn_arg (*s, op, insn, use_extend, extend, memaddr,
636 if ((op->pinfo & INSN_UNCOND_BRANCH_DELAY) != 0)
638 info->branch_delay_insns = 1;
639 if (info->insn_type != dis_jsr)
640 info->insn_type = dis_branch;
648 (*info->fprintf_func) (info->stream, "0x%x", extend | 0xf000);
649 (*info->fprintf_func) (info->stream, "0x%x", insn);
650 info->insn_type = dis_noninsn;
655 /* Disassemble an operand for a mips16 instruction. */
658 print_mips16_insn_arg (type, op, l, use_extend, extend, memaddr, info)
660 const struct mips_opcode *op;
665 struct disassemble_info *info;
672 (*info->fprintf_func) (info->stream, "%c", type);
677 (*info->fprintf_func) (info->stream, "$%s",
678 mips16_reg_names[((l >> MIPS16OP_SH_RY)
679 & MIPS16OP_MASK_RY)]);
684 (*info->fprintf_func) (info->stream, "$%s",
685 mips16_reg_names[((l >> MIPS16OP_SH_RX)
686 & MIPS16OP_MASK_RX)]);
690 (*info->fprintf_func) (info->stream, "$%s",
691 mips16_reg_names[((l >> MIPS16OP_SH_RZ)
692 & MIPS16OP_MASK_RZ)]);
696 (*info->fprintf_func) (info->stream, "$%s",
697 mips16_reg_names[((l >> MIPS16OP_SH_MOVE32Z)
698 & MIPS16OP_MASK_MOVE32Z)]);
702 (*info->fprintf_func) (info->stream, "$%s", reg_names[0]);
706 (*info->fprintf_func) (info->stream, "$%s", reg_names[29]);
710 (*info->fprintf_func) (info->stream, "$pc");
714 (*info->fprintf_func) (info->stream, "$%s", reg_names[31]);
718 (*info->fprintf_func) (info->stream, "$%s",
719 reg_names[((l >> MIPS16OP_SH_REGR32)
720 & MIPS16OP_MASK_REGR32)]);
724 (*info->fprintf_func) (info->stream, "$%s",
725 reg_names[MIPS16OP_EXTRACT_REG32R (l)]);
751 int immed, nbits, shift, signedp, extbits, pcrel, extu, branch;
763 immed = (l >> MIPS16OP_SH_RZ) & MIPS16OP_MASK_RZ;
769 immed = (l >> MIPS16OP_SH_RX) & MIPS16OP_MASK_RX;
775 immed = (l >> MIPS16OP_SH_RZ) & MIPS16OP_MASK_RZ;
781 immed = (l >> MIPS16OP_SH_RX) & MIPS16OP_MASK_RX;
787 immed = (l >> MIPS16OP_SH_IMM4) & MIPS16OP_MASK_IMM4;
793 immed = (l >> MIPS16OP_SH_IMM5) & MIPS16OP_MASK_IMM5;
794 info->insn_type = dis_dref;
800 immed = (l >> MIPS16OP_SH_IMM5) & MIPS16OP_MASK_IMM5;
801 info->insn_type = dis_dref;
807 immed = (l >> MIPS16OP_SH_IMM5) & MIPS16OP_MASK_IMM5;
808 if ((op->pinfo & MIPS16_INSN_READ_PC) == 0
809 && (op->pinfo & MIPS16_INSN_READ_SP) == 0)
811 info->insn_type = dis_dref;
818 immed = (l >> MIPS16OP_SH_IMM5) & MIPS16OP_MASK_IMM5;
819 info->insn_type = dis_dref;
824 immed = (l >> MIPS16OP_SH_IMM5) & MIPS16OP_MASK_IMM5;
829 immed = (l >> MIPS16OP_SH_IMM6) & MIPS16OP_MASK_IMM6;
833 immed = (l >> MIPS16OP_SH_IMM8) & MIPS16OP_MASK_IMM8;
838 immed = (l >> MIPS16OP_SH_IMM8) & MIPS16OP_MASK_IMM8;
839 /* FIXME: This might be lw, or it might be addiu to $sp or
840 $pc. We assume it's load. */
841 info->insn_type = dis_dref;
847 immed = (l >> MIPS16OP_SH_IMM8) & MIPS16OP_MASK_IMM8;
848 info->insn_type = dis_dref;
853 immed = (l >> MIPS16OP_SH_IMM8) & MIPS16OP_MASK_IMM8;
858 immed = (l >> MIPS16OP_SH_IMM8) & MIPS16OP_MASK_IMM8;
864 immed = (l >> MIPS16OP_SH_IMM8) & MIPS16OP_MASK_IMM8;
869 immed = (l >> MIPS16OP_SH_IMM8) & MIPS16OP_MASK_IMM8;
873 info->insn_type = dis_condbranch;
877 immed = (l >> MIPS16OP_SH_IMM11) & MIPS16OP_MASK_IMM11;
881 info->insn_type = dis_branch;
886 immed = (l >> MIPS16OP_SH_IMM8) & MIPS16OP_MASK_IMM8;
888 /* FIXME: This can be lw or la. We assume it is lw. */
889 info->insn_type = dis_dref;
895 immed = (l >> MIPS16OP_SH_IMM5) & MIPS16OP_MASK_IMM5;
897 info->insn_type = dis_dref;
903 immed = (l >> MIPS16OP_SH_IMM5) & MIPS16OP_MASK_IMM5;
912 if (signedp && immed >= (1 << (nbits - 1)))
915 if ((type == '<' || type == '>' || type == '[' || type == '[')
922 immed |= ((extend & 0x1f) << 11) | (extend & 0x7e0);
923 else if (extbits == 15)
924 immed |= ((extend & 0xf) << 11) | (extend & 0x7f0);
926 immed = ((extend >> 6) & 0x1f) | (extend & 0x20);
927 immed &= (1 << extbits) - 1;
928 if (! extu && immed >= (1 << (extbits - 1)))
929 immed -= 1 << extbits;
933 (*info->fprintf_func) (info->stream, "%d", immed);
942 baseaddr = memaddr + 2;
945 baseaddr = memaddr - 2;
953 /* If this instruction is in the delay slot of a jr
954 instruction, the base address is the address of the
955 jr instruction. If it is in the delay slot of jalr
956 instruction, the base address is the address of the
957 jalr instruction. This test is unreliable: we have
958 no way of knowing whether the previous word is
959 instruction or data. */
960 status = (*info->read_memory_func) (memaddr - 4, buffer, 2,
963 && (((info->endian == BFD_ENDIAN_BIG
964 ? bfd_getb16 (buffer)
965 : bfd_getl16 (buffer))
966 & 0xf800) == 0x1800))
967 baseaddr = memaddr - 4;
970 status = (*info->read_memory_func) (memaddr - 2, buffer,
973 && (((info->endian == BFD_ENDIAN_BIG
974 ? bfd_getb16 (buffer)
975 : bfd_getl16 (buffer))
976 & 0xf81f) == 0xe800))
977 baseaddr = memaddr - 2;
980 val = (baseaddr & ~ ((1 << shift) - 1)) + immed;
981 (*info->print_address_func) (val, info);
990 l = ((l & 0x1f) << 23) | ((l & 0x3e0) << 13) | (extend << 2);
991 (*info->print_address_func) ((memaddr & 0xf0000000) | l, info);
992 info->insn_type = dis_jsr;
993 info->target = (memaddr & 0xf0000000) | l;
994 info->branch_delay_insns = 1;
1000 int need_comma, amask, smask;
1004 l = (l >> MIPS16OP_SH_IMM6) & MIPS16OP_MASK_IMM6;
1006 amask = (l >> 3) & 7;
1008 if (amask > 0 && amask < 5)
1010 (*info->fprintf_func) (info->stream, "$%s", reg_names[4]);
1012 (*info->fprintf_func) (info->stream, "-$%s",
1013 reg_names[amask + 3]);
1017 smask = (l >> 1) & 3;
1020 (*info->fprintf_func) (info->stream, "%s??",
1021 need_comma ? "," : "");
1026 (*info->fprintf_func) (info->stream, "%s$%s",
1027 need_comma ? "," : "",
1030 (*info->fprintf_func) (info->stream, "-$%s",
1031 reg_names[smask + 15]);
1037 (*info->fprintf_func) (info->stream, "%s$%s",
1038 need_comma ? "," : "",
1043 if (amask == 5 || amask == 6)
1045 (*info->fprintf_func) (info->stream, "%s$f0",
1046 need_comma ? "," : "");
1048 (*info->fprintf_func) (info->stream, "-$f1");