1 /* Print mips instructions for GDB, the GNU debugger, or for objdump.
2 Copyright (c) 1989, 91, 92, 93, 94, 95, 96, 97, 98, 99, 2000
3 Free Software Foundation, Inc.
4 Contributed by Nobuyuki Hikichi(hikichi@sra.co.jp).
6 This file is part of GDB, GAS, and the GNU binutils.
8 This program is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 2 of the License, or
11 (at your option) any later version.
13 This program is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
18 You should have received a copy of the GNU General Public License
19 along with this program; if not, write to the Free Software
20 Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */
24 #include "opcode/mips.h"
27 /* FIXME: These are needed to figure out if the code is mips16 or
28 not. The low bit of the address is often a good indicator. No
29 symbol table is available when this code runs out in an embedded
30 system as when it is used for disassembler support in a monitor. */
32 #if !defined(EMBEDDED_ENV)
33 #define SYMTAB_AVAILABLE 1
38 static int print_insn_mips16 PARAMS ((bfd_vma, struct disassemble_info *));
39 static void print_mips16_insn_arg
40 PARAMS ((int, const struct mips_opcode *, int, boolean, int, bfd_vma,
41 struct disassemble_info *));
43 /* Mips instructions are never longer than this many bytes. */
46 static void print_insn_arg PARAMS ((const char *, unsigned long, bfd_vma,
47 struct disassemble_info *));
48 static int _print_insn_mips PARAMS ((bfd_vma, unsigned long int,
49 struct disassemble_info *));
52 /* FIXME: This should be shared with gdb somehow. */
53 #define STD_REGISTER_NAMES \
54 { "zero", "at", "v0", "v1", "a0", "a1", "a2", "a3", \
55 "t0", "t1", "t2", "t3", "t4", "t5", "t6", "t7", \
56 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7", \
57 "t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra", \
58 "sr", "lo", "hi", "bad", "cause","pc", \
59 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7", \
60 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15", \
61 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",\
62 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31",\
63 "fsr", "fir", "fp", "inx", "rand", "tlblo","ctxt", "tlbhi",\
67 static CONST char * CONST std_reg_names[] = STD_REGISTER_NAMES;
69 /* The mips16 register names. */
70 static const char * const mips16_reg_names[] =
72 "s0", "s1", "v0", "v1", "a0", "a1", "a2", "a3"
75 /* Scalar register names. set_mips_isa_type() decides which register name
77 static CONST char * CONST *reg_names = NULL;
81 print_insn_arg (d, l, pc, info)
83 register unsigned long int l;
85 struct disassemble_info *info;
94 (*info->fprintf_func) (info->stream, "%c", *d);
101 (*info->fprintf_func) (info->stream, "$%s",
102 reg_names[(l >> OP_SH_RS) & OP_MASK_RS]);
107 (*info->fprintf_func) (info->stream, "$%s",
108 reg_names[(l >> OP_SH_RT) & OP_MASK_RT]);
113 (*info->fprintf_func) (info->stream, "0x%x",
114 (l >> OP_SH_IMMEDIATE) & OP_MASK_IMMEDIATE);
117 case 'j': /* same as i, but sign-extended */
119 delta = (l >> OP_SH_DELTA) & OP_MASK_DELTA;
122 (*info->fprintf_func) (info->stream, "%d",
127 (*info->fprintf_func) (info->stream, "0x%x",
128 (unsigned int) ((l >> OP_SH_PREFX)
133 (*info->fprintf_func) (info->stream, "0x%x",
134 (unsigned int) ((l >> OP_SH_CACHE)
139 (*info->print_address_func)
140 (((pc & ~ (bfd_vma) 0x0fffffff)
141 | (((l >> OP_SH_TARGET) & OP_MASK_TARGET) << 2)),
146 /* sign extend the displacement */
147 delta = (l >> OP_SH_DELTA) & OP_MASK_DELTA;
150 (*info->print_address_func)
151 ((delta << 2) + pc + 4,
156 (*info->fprintf_func) (info->stream, "$%s",
157 reg_names[(l >> OP_SH_RD) & OP_MASK_RD]);
162 /* First check for both rd and rt being equal. */
163 int reg = (l >> OP_SH_RD) & OP_MASK_RD;
164 if (reg == ((l >> OP_SH_RT) & OP_MASK_RT))
165 (*info->fprintf_func) (info->stream, "$%s",
169 /* If one is zero use the other. */
171 (*info->fprintf_func) (info->stream, "$%s",
172 reg_names[(l >> OP_SH_RT) & OP_MASK_RT]);
173 else if (((l >> OP_SH_RT) & OP_MASK_RT) == 0)
174 (*info->fprintf_func) (info->stream, "$%s",
176 else /* Bogus, result depends on processor. */
177 (*info->fprintf_func) (info->stream, "$%s or $%s",
179 reg_names[(l >> OP_SH_RT) & OP_MASK_RT]);
185 (*info->fprintf_func) (info->stream, "$%s", reg_names[0]);
189 (*info->fprintf_func) (info->stream, "0x%x",
190 (l >> OP_SH_SHAMT) & OP_MASK_SHAMT);
194 (*info->fprintf_func) (info->stream, "0x%x",
195 (l >> OP_SH_CODE) & OP_MASK_CODE);
199 (*info->fprintf_func) (info->stream, "0x%x",
200 (l >> OP_SH_CODE2) & OP_MASK_CODE2);
204 (*info->fprintf_func) (info->stream, "0x%x",
205 (l >> OP_SH_COPZ) & OP_MASK_COPZ);
209 (*info->fprintf_func) (info->stream, "0x%x",
210 (l >> OP_SH_CODE20) & OP_MASK_CODE20);
214 (*info->fprintf_func) (info->stream, "0x%x",
215 (l >> OP_SH_CODE19) & OP_MASK_CODE19);
220 (*info->fprintf_func) (info->stream, "$f%d",
221 (l >> OP_SH_FS) & OP_MASK_FS);
226 (*info->fprintf_func) (info->stream, "$f%d",
227 (l >> OP_SH_FT) & OP_MASK_FT);
231 (*info->fprintf_func) (info->stream, "$f%d",
232 (l >> OP_SH_FD) & OP_MASK_FD);
236 (*info->fprintf_func) (info->stream, "$f%d",
237 (l >> OP_SH_FR) & OP_MASK_FR);
241 (*info->fprintf_func) (info->stream, "$%d",
242 (l >> OP_SH_RT) & OP_MASK_RT);
246 (*info->fprintf_func) (info->stream, "$%d",
247 (l >> OP_SH_RD) & OP_MASK_RD);
251 (*info->fprintf_func) (info->stream, "$fcc%d",
252 (l >> OP_SH_BCC) & OP_MASK_BCC);
256 (*info->fprintf_func) (info->stream, "$fcc%d",
257 (l >> OP_SH_CCC) & OP_MASK_CCC);
261 (*info->fprintf_func) (info->stream, "%d",
262 (l >> OP_SH_PERFREG) & OP_MASK_PERFREG);
266 (*info->fprintf_func) (info->stream, "%d",
267 (l >> OP_SH_SEL) & OP_MASK_SEL);
271 /* xgettext:c-format */
272 (*info->fprintf_func) (info->stream,
273 _("# internal error, undefined modifier(%c)"),
281 /* Figure out the MIPS ISA and CPU based on the machine number.
282 FIXME: What does this have to do with SYMTAB_AVAILABLE? */
285 set_mips_isa_type (mach, isa, cputype)
290 int target_processor = 0;
293 /* Use standard MIPS register names by default. */
294 reg_names = std_reg_names;
298 case bfd_mach_mips3000:
299 target_processor = CPU_R3000;
302 case bfd_mach_mips3900:
303 target_processor = CPU_R3900;
306 case bfd_mach_mips4000:
307 target_processor = CPU_R4000;
310 case bfd_mach_mips4010:
311 target_processor = CPU_R4010;
314 case bfd_mach_mips4100:
315 target_processor = CPU_VR4100;
318 case bfd_mach_mips4111:
319 target_processor = CPU_VR4100; /* FIXME: Shouldn't this be CPU_R4111 ??? */
322 case bfd_mach_mips4300:
323 target_processor = CPU_R4300;
326 case bfd_mach_mips4400:
327 target_processor = CPU_R4400;
330 case bfd_mach_mips4600:
331 target_processor = CPU_R4600;
334 case bfd_mach_mips4650:
335 target_processor = CPU_R4650;
338 case bfd_mach_mips4K:
339 target_processor = CPU_4K;
342 case bfd_mach_mips5000:
343 target_processor = CPU_R5000;
346 case bfd_mach_mips6000:
347 target_processor = CPU_R6000;
350 case bfd_mach_mips8000:
351 target_processor = CPU_R8000;
354 case bfd_mach_mips10000:
355 target_processor = CPU_R10000;
358 case bfd_mach_mips16:
359 target_processor = CPU_MIPS16;
363 target_processor = CPU_R3000;
369 *cputype = target_processor;
372 #endif /* SYMTAB_AVAILABLE */
374 /* Print the mips instruction at address MEMADDR in debugged memory,
375 on using INFO. Returns length of the instruction, in bytes, which is
376 always 4. BIGENDIAN must be 1 if this is big-endian code, 0 if
377 this is little-endian code. */
380 _print_insn_mips (memaddr, word, info)
382 unsigned long int word;
383 struct disassemble_info *info;
385 register const struct mips_opcode *op;
386 int target_processor, mips_isa;
387 static boolean init = 0;
388 static const struct mips_opcode *mips_hash[OP_MASK_OP + 1];
390 /* Build a hash table to shorten the search time. */
395 for (i = 0; i <= OP_MASK_OP; i++)
397 for (op = mips_opcodes; op < &mips_opcodes[NUMOPCODES]; op++)
399 if (op->pinfo == INSN_MACRO)
401 if (i == ((op->match >> OP_SH_OP) & OP_MASK_OP))
412 #if ! SYMTAB_AVAILABLE
413 /* This is running out on a target machine, not in a host tool.
414 FIXME: Where does mips_target_info come from? */
415 target_processor = mips_target_info.processor;
416 mips_isa = mips_target_info.isa;
418 set_mips_isa_type (info->mach, &mips_isa, &target_processor);
421 info->bytes_per_chunk = 4;
422 info->display_endian = info->endian;
424 op = mips_hash[(word >> OP_SH_OP) & OP_MASK_OP];
427 for (; op < &mips_opcodes[NUMOPCODES]; op++)
429 if (op->pinfo != INSN_MACRO && (word & op->mask) == op->match)
431 register const char *d;
433 if (! OPCODE_IS_MEMBER (op, mips_isa, target_processor, 0))
436 (*info->fprintf_func) (info->stream, "%s", op->name);
439 if (d != NULL && *d != '\0')
441 (*info->fprintf_func) (info->stream, "\t");
442 for (; *d != '\0'; d++)
443 print_insn_arg (d, word, memaddr, info);
451 /* Handle undefined instructions. */
452 (*info->fprintf_func) (info->stream, "0x%x", word);
457 /* In an environment where we do not know the symbol type of the
458 instruction we are forced to assume that the low order bit of the
459 instructions' address may mark it as a mips16 instruction. If we
460 are single stepping, or the pc is within the disassembled function,
461 this works. Otherwise, we need a clue. Sometimes. */
464 print_insn_big_mips (memaddr, info)
466 struct disassemble_info *info;
472 /* FIXME: If odd address, this is CLEARLY a mips 16 instruction. */
473 /* Only a few tools will work this way. */
475 return print_insn_mips16 (memaddr, info);
480 || (info->flavour == bfd_target_elf_flavour
481 && info->symbols != NULL
482 && ((*(elf_symbol_type **) info->symbols)->internal_elf_sym.st_other
484 return print_insn_mips16 (memaddr, info);
487 status = (*info->read_memory_func) (memaddr, buffer, 4, info);
489 return _print_insn_mips (memaddr, (unsigned long) bfd_getb32 (buffer),
493 (*info->memory_error_func) (status, memaddr, info);
499 print_insn_little_mips (memaddr, info)
501 struct disassemble_info *info;
509 return print_insn_mips16 (memaddr, info);
514 || (info->flavour == bfd_target_elf_flavour
515 && info->symbols != NULL
516 && ((*(elf_symbol_type **) info->symbols)->internal_elf_sym.st_other
518 return print_insn_mips16 (memaddr, info);
521 status = (*info->read_memory_func) (memaddr, buffer, 4, info);
523 return _print_insn_mips (memaddr, (unsigned long) bfd_getl32 (buffer),
527 (*info->memory_error_func) (status, memaddr, info);
532 /* Disassemble mips16 instructions. */
535 print_insn_mips16 (memaddr, info)
537 struct disassemble_info *info;
545 const struct mips_opcode *op, *opend;
547 info->bytes_per_chunk = 2;
548 info->display_endian = info->endian;
550 info->insn_info_valid = 1;
551 info->branch_delay_insns = 0;
553 info->insn_type = dis_nonbranch;
557 status = (*info->read_memory_func) (memaddr, buffer, 2, info);
560 (*info->memory_error_func) (status, memaddr, info);
566 if (info->endian == BFD_ENDIAN_BIG)
567 insn = bfd_getb16 (buffer);
569 insn = bfd_getl16 (buffer);
571 /* Handle the extend opcode specially. */
573 if ((insn & 0xf800) == 0xf000)
576 extend = insn & 0x7ff;
580 status = (*info->read_memory_func) (memaddr, buffer, 2, info);
583 (*info->fprintf_func) (info->stream, "extend 0x%x",
584 (unsigned int) extend);
585 (*info->memory_error_func) (status, memaddr, info);
589 if (info->endian == BFD_ENDIAN_BIG)
590 insn = bfd_getb16 (buffer);
592 insn = bfd_getl16 (buffer);
594 /* Check for an extend opcode followed by an extend opcode. */
595 if ((insn & 0xf800) == 0xf000)
597 (*info->fprintf_func) (info->stream, "extend 0x%x",
598 (unsigned int) extend);
599 info->insn_type = dis_noninsn;
606 /* FIXME: Should probably use a hash table on the major opcode here. */
608 opend = mips16_opcodes + bfd_mips16_num_opcodes;
609 for (op = mips16_opcodes; op < opend; op++)
611 if (op->pinfo != INSN_MACRO && (insn & op->mask) == op->match)
615 if (strchr (op->args, 'a') != NULL)
619 (*info->fprintf_func) (info->stream, "extend 0x%x",
620 (unsigned int) extend);
621 info->insn_type = dis_noninsn;
629 status = (*info->read_memory_func) (memaddr, buffer, 2,
634 if (info->endian == BFD_ENDIAN_BIG)
635 extend = bfd_getb16 (buffer);
637 extend = bfd_getl16 (buffer);
642 (*info->fprintf_func) (info->stream, "%s", op->name);
643 if (op->args[0] != '\0')
644 (*info->fprintf_func) (info->stream, "\t");
646 for (s = op->args; *s != '\0'; s++)
650 && (((insn >> MIPS16OP_SH_RX) & MIPS16OP_MASK_RX)
651 == ((insn >> MIPS16OP_SH_RY) & MIPS16OP_MASK_RY)))
653 /* Skip the register and the comma. */
659 && (((insn >> MIPS16OP_SH_RZ) & MIPS16OP_MASK_RZ)
660 == ((insn >> MIPS16OP_SH_RX) & MIPS16OP_MASK_RX)))
662 /* Skip the register and the comma. */
666 print_mips16_insn_arg (*s, op, insn, use_extend, extend, memaddr,
670 if ((op->pinfo & INSN_UNCOND_BRANCH_DELAY) != 0)
672 info->branch_delay_insns = 1;
673 if (info->insn_type != dis_jsr)
674 info->insn_type = dis_branch;
682 (*info->fprintf_func) (info->stream, "0x%x", extend | 0xf000);
683 (*info->fprintf_func) (info->stream, "0x%x", insn);
684 info->insn_type = dis_noninsn;
689 /* Disassemble an operand for a mips16 instruction. */
692 print_mips16_insn_arg (type, op, l, use_extend, extend, memaddr, info)
694 const struct mips_opcode *op;
699 struct disassemble_info *info;
706 (*info->fprintf_func) (info->stream, "%c", type);
711 (*info->fprintf_func) (info->stream, "$%s",
712 mips16_reg_names[((l >> MIPS16OP_SH_RY)
713 & MIPS16OP_MASK_RY)]);
718 (*info->fprintf_func) (info->stream, "$%s",
719 mips16_reg_names[((l >> MIPS16OP_SH_RX)
720 & MIPS16OP_MASK_RX)]);
724 (*info->fprintf_func) (info->stream, "$%s",
725 mips16_reg_names[((l >> MIPS16OP_SH_RZ)
726 & MIPS16OP_MASK_RZ)]);
730 (*info->fprintf_func) (info->stream, "$%s",
731 mips16_reg_names[((l >> MIPS16OP_SH_MOVE32Z)
732 & MIPS16OP_MASK_MOVE32Z)]);
736 (*info->fprintf_func) (info->stream, "$%s", reg_names[0]);
740 (*info->fprintf_func) (info->stream, "$%s", reg_names[29]);
744 (*info->fprintf_func) (info->stream, "$pc");
748 (*info->fprintf_func) (info->stream, "$%s", reg_names[31]);
752 (*info->fprintf_func) (info->stream, "$%s",
753 reg_names[((l >> MIPS16OP_SH_REGR32)
754 & MIPS16OP_MASK_REGR32)]);
758 (*info->fprintf_func) (info->stream, "$%s",
759 reg_names[MIPS16OP_EXTRACT_REG32R (l)]);
785 int immed, nbits, shift, signedp, extbits, pcrel, extu, branch;
797 immed = (l >> MIPS16OP_SH_RZ) & MIPS16OP_MASK_RZ;
803 immed = (l >> MIPS16OP_SH_RX) & MIPS16OP_MASK_RX;
809 immed = (l >> MIPS16OP_SH_RZ) & MIPS16OP_MASK_RZ;
815 immed = (l >> MIPS16OP_SH_RX) & MIPS16OP_MASK_RX;
821 immed = (l >> MIPS16OP_SH_IMM4) & MIPS16OP_MASK_IMM4;
827 immed = (l >> MIPS16OP_SH_IMM5) & MIPS16OP_MASK_IMM5;
828 info->insn_type = dis_dref;
834 immed = (l >> MIPS16OP_SH_IMM5) & MIPS16OP_MASK_IMM5;
835 info->insn_type = dis_dref;
841 immed = (l >> MIPS16OP_SH_IMM5) & MIPS16OP_MASK_IMM5;
842 if ((op->pinfo & MIPS16_INSN_READ_PC) == 0
843 && (op->pinfo & MIPS16_INSN_READ_SP) == 0)
845 info->insn_type = dis_dref;
852 immed = (l >> MIPS16OP_SH_IMM5) & MIPS16OP_MASK_IMM5;
853 info->insn_type = dis_dref;
858 immed = (l >> MIPS16OP_SH_IMM5) & MIPS16OP_MASK_IMM5;
863 immed = (l >> MIPS16OP_SH_IMM6) & MIPS16OP_MASK_IMM6;
867 immed = (l >> MIPS16OP_SH_IMM8) & MIPS16OP_MASK_IMM8;
872 immed = (l >> MIPS16OP_SH_IMM8) & MIPS16OP_MASK_IMM8;
873 /* FIXME: This might be lw, or it might be addiu to $sp or
874 $pc. We assume it's load. */
875 info->insn_type = dis_dref;
881 immed = (l >> MIPS16OP_SH_IMM8) & MIPS16OP_MASK_IMM8;
882 info->insn_type = dis_dref;
887 immed = (l >> MIPS16OP_SH_IMM8) & MIPS16OP_MASK_IMM8;
892 immed = (l >> MIPS16OP_SH_IMM8) & MIPS16OP_MASK_IMM8;
898 immed = (l >> MIPS16OP_SH_IMM8) & MIPS16OP_MASK_IMM8;
903 immed = (l >> MIPS16OP_SH_IMM8) & MIPS16OP_MASK_IMM8;
907 info->insn_type = dis_condbranch;
911 immed = (l >> MIPS16OP_SH_IMM11) & MIPS16OP_MASK_IMM11;
915 info->insn_type = dis_branch;
920 immed = (l >> MIPS16OP_SH_IMM8) & MIPS16OP_MASK_IMM8;
922 /* FIXME: This can be lw or la. We assume it is lw. */
923 info->insn_type = dis_dref;
929 immed = (l >> MIPS16OP_SH_IMM5) & MIPS16OP_MASK_IMM5;
931 info->insn_type = dis_dref;
937 immed = (l >> MIPS16OP_SH_IMM5) & MIPS16OP_MASK_IMM5;
946 if (signedp && immed >= (1 << (nbits - 1)))
949 if ((type == '<' || type == '>' || type == '[' || type == ']')
956 immed |= ((extend & 0x1f) << 11) | (extend & 0x7e0);
957 else if (extbits == 15)
958 immed |= ((extend & 0xf) << 11) | (extend & 0x7f0);
960 immed = ((extend >> 6) & 0x1f) | (extend & 0x20);
961 immed &= (1 << extbits) - 1;
962 if (! extu && immed >= (1 << (extbits - 1)))
963 immed -= 1 << extbits;
967 (*info->fprintf_func) (info->stream, "%d", immed);
976 baseaddr = memaddr + 2;
979 baseaddr = memaddr - 2;
987 /* If this instruction is in the delay slot of a jr
988 instruction, the base address is the address of the
989 jr instruction. If it is in the delay slot of jalr
990 instruction, the base address is the address of the
991 jalr instruction. This test is unreliable: we have
992 no way of knowing whether the previous word is
993 instruction or data. */
994 status = (*info->read_memory_func) (memaddr - 4, buffer, 2,
997 && (((info->endian == BFD_ENDIAN_BIG
998 ? bfd_getb16 (buffer)
999 : bfd_getl16 (buffer))
1000 & 0xf800) == 0x1800))
1001 baseaddr = memaddr - 4;
1004 status = (*info->read_memory_func) (memaddr - 2, buffer,
1007 && (((info->endian == BFD_ENDIAN_BIG
1008 ? bfd_getb16 (buffer)
1009 : bfd_getl16 (buffer))
1010 & 0xf81f) == 0xe800))
1011 baseaddr = memaddr - 2;
1014 val = (baseaddr & ~ ((1 << shift) - 1)) + immed;
1015 (*info->print_address_func) (val, info);
1024 l = ((l & 0x1f) << 23) | ((l & 0x3e0) << 13) | (extend << 2);
1025 (*info->print_address_func) ((memaddr & 0xf0000000) | l, info);
1026 info->insn_type = dis_jsr;
1027 info->target = (memaddr & 0xf0000000) | l;
1028 info->branch_delay_insns = 1;
1034 int need_comma, amask, smask;
1038 l = (l >> MIPS16OP_SH_IMM6) & MIPS16OP_MASK_IMM6;
1040 amask = (l >> 3) & 7;
1042 if (amask > 0 && amask < 5)
1044 (*info->fprintf_func) (info->stream, "$%s", reg_names[4]);
1046 (*info->fprintf_func) (info->stream, "-$%s",
1047 reg_names[amask + 3]);
1051 smask = (l >> 1) & 3;
1054 (*info->fprintf_func) (info->stream, "%s??",
1055 need_comma ? "," : "");
1060 (*info->fprintf_func) (info->stream, "%s$%s",
1061 need_comma ? "," : "",
1064 (*info->fprintf_func) (info->stream, "-$%s",
1065 reg_names[smask + 15]);
1071 (*info->fprintf_func) (info->stream, "%s$%s",
1072 need_comma ? "," : "",
1077 if (amask == 5 || amask == 6)
1079 (*info->fprintf_func) (info->stream, "%s$f0",
1080 need_comma ? "," : "");
1082 (*info->fprintf_func) (info->stream, "-$f1");