1 /* Print mips instructions for GDB, the GNU debugger, or for objdump.
2 Copyright 1989, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999,
3 2000, 2001, 2002, 2003, 2005, 2006, 2007, 2008, 2009
4 Free Software Foundation, Inc.
5 Contributed by Nobuyuki Hikichi(hikichi@sra.co.jp).
7 This file is part of the GNU opcodes library.
9 This library is free software; you can redistribute it and/or modify
10 it under the terms of the GNU General Public License as published by
11 the Free Software Foundation; either version 3, or (at your option)
14 It is distributed in the hope that it will be useful, but WITHOUT
15 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
16 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
17 License for more details.
19 You should have received a copy of the GNU General Public License
20 along with this program; if not, write to the Free Software
21 Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
22 MA 02110-1301, USA. */
26 #include "libiberty.h"
27 #include "opcode/mips.h"
30 /* FIXME: These are needed to figure out if the code is mips16 or
31 not. The low bit of the address is often a good indicator. No
32 symbol table is available when this code runs out in an embedded
33 system as when it is used for disassembler support in a monitor. */
35 #if !defined(EMBEDDED_ENV)
36 #define SYMTAB_AVAILABLE 1
41 /* Mips instructions are at maximum this many bytes long. */
45 /* FIXME: These should be shared with gdb somehow. */
47 struct mips_cp0sel_name
51 const char * const name;
54 /* The mips16 registers. */
55 static const unsigned int mips16_to_32_reg_map[] =
57 16, 17, 2, 3, 4, 5, 6, 7
60 #define mips16_reg_names(rn) mips_gpr_names[mips16_to_32_reg_map[rn]]
63 static const char * const mips_gpr_names_numeric[32] =
65 "$0", "$1", "$2", "$3", "$4", "$5", "$6", "$7",
66 "$8", "$9", "$10", "$11", "$12", "$13", "$14", "$15",
67 "$16", "$17", "$18", "$19", "$20", "$21", "$22", "$23",
68 "$24", "$25", "$26", "$27", "$28", "$29", "$30", "$31"
71 static const char * const mips_gpr_names_oldabi[32] =
73 "zero", "at", "v0", "v1", "a0", "a1", "a2", "a3",
74 "t0", "t1", "t2", "t3", "t4", "t5", "t6", "t7",
75 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7",
76 "t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra"
79 static const char * const mips_gpr_names_newabi[32] =
81 "zero", "at", "v0", "v1", "a0", "a1", "a2", "a3",
82 "a4", "a5", "a6", "a7", "t0", "t1", "t2", "t3",
83 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7",
84 "t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra"
87 static const char * const mips_fpr_names_numeric[32] =
89 "$f0", "$f1", "$f2", "$f3", "$f4", "$f5", "$f6", "$f7",
90 "$f8", "$f9", "$f10", "$f11", "$f12", "$f13", "$f14", "$f15",
91 "$f16", "$f17", "$f18", "$f19", "$f20", "$f21", "$f22", "$f23",
92 "$f24", "$f25", "$f26", "$f27", "$f28", "$f29", "$f30", "$f31"
95 static const char * const mips_fpr_names_32[32] =
97 "fv0", "fv0f", "fv1", "fv1f", "ft0", "ft0f", "ft1", "ft1f",
98 "ft2", "ft2f", "ft3", "ft3f", "fa0", "fa0f", "fa1", "fa1f",
99 "ft4", "ft4f", "ft5", "ft5f", "fs0", "fs0f", "fs1", "fs1f",
100 "fs2", "fs2f", "fs3", "fs3f", "fs4", "fs4f", "fs5", "fs5f"
103 static const char * const mips_fpr_names_n32[32] =
105 "fv0", "ft14", "fv1", "ft15", "ft0", "ft1", "ft2", "ft3",
106 "ft4", "ft5", "ft6", "ft7", "fa0", "fa1", "fa2", "fa3",
107 "fa4", "fa5", "fa6", "fa7", "fs0", "ft8", "fs1", "ft9",
108 "fs2", "ft10", "fs3", "ft11", "fs4", "ft12", "fs5", "ft13"
111 static const char * const mips_fpr_names_64[32] =
113 "fv0", "ft12", "fv1", "ft13", "ft0", "ft1", "ft2", "ft3",
114 "ft4", "ft5", "ft6", "ft7", "fa0", "fa1", "fa2", "fa3",
115 "fa4", "fa5", "fa6", "fa7", "ft8", "ft9", "ft10", "ft11",
116 "fs0", "fs1", "fs2", "fs3", "fs4", "fs5", "fs6", "fs7"
119 static const char * const mips_cp0_names_numeric[32] =
121 "$0", "$1", "$2", "$3", "$4", "$5", "$6", "$7",
122 "$8", "$9", "$10", "$11", "$12", "$13", "$14", "$15",
123 "$16", "$17", "$18", "$19", "$20", "$21", "$22", "$23",
124 "$24", "$25", "$26", "$27", "$28", "$29", "$30", "$31"
127 static const char * const mips_cp0_names_r3000[32] =
129 "c0_index", "c0_random", "c0_entrylo", "$3",
130 "c0_context", "$5", "$6", "$7",
131 "c0_badvaddr", "$9", "c0_entryhi", "$11",
132 "c0_sr", "c0_cause", "c0_epc", "c0_prid",
133 "$16", "$17", "$18", "$19",
134 "$20", "$21", "$22", "$23",
135 "$24", "$25", "$26", "$27",
136 "$28", "$29", "$30", "$31",
139 static const char * const mips_cp0_names_r4000[32] =
141 "c0_index", "c0_random", "c0_entrylo0", "c0_entrylo1",
142 "c0_context", "c0_pagemask", "c0_wired", "$7",
143 "c0_badvaddr", "c0_count", "c0_entryhi", "c0_compare",
144 "c0_sr", "c0_cause", "c0_epc", "c0_prid",
145 "c0_config", "c0_lladdr", "c0_watchlo", "c0_watchhi",
146 "c0_xcontext", "$21", "$22", "$23",
147 "$24", "$25", "c0_ecc", "c0_cacheerr",
148 "c0_taglo", "c0_taghi", "c0_errorepc", "$31",
151 static const char * const mips_cp0_names_mips3264[32] =
153 "c0_index", "c0_random", "c0_entrylo0", "c0_entrylo1",
154 "c0_context", "c0_pagemask", "c0_wired", "$7",
155 "c0_badvaddr", "c0_count", "c0_entryhi", "c0_compare",
156 "c0_status", "c0_cause", "c0_epc", "c0_prid",
157 "c0_config", "c0_lladdr", "c0_watchlo", "c0_watchhi",
158 "c0_xcontext", "$21", "$22", "c0_debug",
159 "c0_depc", "c0_perfcnt", "c0_errctl", "c0_cacheerr",
160 "c0_taglo", "c0_taghi", "c0_errorepc", "c0_desave",
163 static const struct mips_cp0sel_name mips_cp0sel_names_mips3264[] =
165 { 16, 1, "c0_config1" },
166 { 16, 2, "c0_config2" },
167 { 16, 3, "c0_config3" },
168 { 18, 1, "c0_watchlo,1" },
169 { 18, 2, "c0_watchlo,2" },
170 { 18, 3, "c0_watchlo,3" },
171 { 18, 4, "c0_watchlo,4" },
172 { 18, 5, "c0_watchlo,5" },
173 { 18, 6, "c0_watchlo,6" },
174 { 18, 7, "c0_watchlo,7" },
175 { 19, 1, "c0_watchhi,1" },
176 { 19, 2, "c0_watchhi,2" },
177 { 19, 3, "c0_watchhi,3" },
178 { 19, 4, "c0_watchhi,4" },
179 { 19, 5, "c0_watchhi,5" },
180 { 19, 6, "c0_watchhi,6" },
181 { 19, 7, "c0_watchhi,7" },
182 { 25, 1, "c0_perfcnt,1" },
183 { 25, 2, "c0_perfcnt,2" },
184 { 25, 3, "c0_perfcnt,3" },
185 { 25, 4, "c0_perfcnt,4" },
186 { 25, 5, "c0_perfcnt,5" },
187 { 25, 6, "c0_perfcnt,6" },
188 { 25, 7, "c0_perfcnt,7" },
189 { 27, 1, "c0_cacheerr,1" },
190 { 27, 2, "c0_cacheerr,2" },
191 { 27, 3, "c0_cacheerr,3" },
192 { 28, 1, "c0_datalo" },
193 { 29, 1, "c0_datahi" }
196 static const char * const mips_cp0_names_mips3264r2[32] =
198 "c0_index", "c0_random", "c0_entrylo0", "c0_entrylo1",
199 "c0_context", "c0_pagemask", "c0_wired", "c0_hwrena",
200 "c0_badvaddr", "c0_count", "c0_entryhi", "c0_compare",
201 "c0_status", "c0_cause", "c0_epc", "c0_prid",
202 "c0_config", "c0_lladdr", "c0_watchlo", "c0_watchhi",
203 "c0_xcontext", "$21", "$22", "c0_debug",
204 "c0_depc", "c0_perfcnt", "c0_errctl", "c0_cacheerr",
205 "c0_taglo", "c0_taghi", "c0_errorepc", "c0_desave",
208 static const struct mips_cp0sel_name mips_cp0sel_names_mips3264r2[] =
210 { 4, 1, "c0_contextconfig" },
211 { 0, 1, "c0_mvpcontrol" },
212 { 0, 2, "c0_mvpconf0" },
213 { 0, 3, "c0_mvpconf1" },
214 { 1, 1, "c0_vpecontrol" },
215 { 1, 2, "c0_vpeconf0" },
216 { 1, 3, "c0_vpeconf1" },
217 { 1, 4, "c0_yqmask" },
218 { 1, 5, "c0_vpeschedule" },
219 { 1, 6, "c0_vpeschefback" },
220 { 2, 1, "c0_tcstatus" },
221 { 2, 2, "c0_tcbind" },
222 { 2, 3, "c0_tcrestart" },
223 { 2, 4, "c0_tchalt" },
224 { 2, 5, "c0_tccontext" },
225 { 2, 6, "c0_tcschedule" },
226 { 2, 7, "c0_tcschefback" },
227 { 5, 1, "c0_pagegrain" },
228 { 6, 1, "c0_srsconf0" },
229 { 6, 2, "c0_srsconf1" },
230 { 6, 3, "c0_srsconf2" },
231 { 6, 4, "c0_srsconf3" },
232 { 6, 5, "c0_srsconf4" },
233 { 12, 1, "c0_intctl" },
234 { 12, 2, "c0_srsctl" },
235 { 12, 3, "c0_srsmap" },
236 { 15, 1, "c0_ebase" },
237 { 16, 1, "c0_config1" },
238 { 16, 2, "c0_config2" },
239 { 16, 3, "c0_config3" },
240 { 18, 1, "c0_watchlo,1" },
241 { 18, 2, "c0_watchlo,2" },
242 { 18, 3, "c0_watchlo,3" },
243 { 18, 4, "c0_watchlo,4" },
244 { 18, 5, "c0_watchlo,5" },
245 { 18, 6, "c0_watchlo,6" },
246 { 18, 7, "c0_watchlo,7" },
247 { 19, 1, "c0_watchhi,1" },
248 { 19, 2, "c0_watchhi,2" },
249 { 19, 3, "c0_watchhi,3" },
250 { 19, 4, "c0_watchhi,4" },
251 { 19, 5, "c0_watchhi,5" },
252 { 19, 6, "c0_watchhi,6" },
253 { 19, 7, "c0_watchhi,7" },
254 { 23, 1, "c0_tracecontrol" },
255 { 23, 2, "c0_tracecontrol2" },
256 { 23, 3, "c0_usertracedata" },
257 { 23, 4, "c0_tracebpc" },
258 { 25, 1, "c0_perfcnt,1" },
259 { 25, 2, "c0_perfcnt,2" },
260 { 25, 3, "c0_perfcnt,3" },
261 { 25, 4, "c0_perfcnt,4" },
262 { 25, 5, "c0_perfcnt,5" },
263 { 25, 6, "c0_perfcnt,6" },
264 { 25, 7, "c0_perfcnt,7" },
265 { 27, 1, "c0_cacheerr,1" },
266 { 27, 2, "c0_cacheerr,2" },
267 { 27, 3, "c0_cacheerr,3" },
268 { 28, 1, "c0_datalo" },
269 { 28, 2, "c0_taglo1" },
270 { 28, 3, "c0_datalo1" },
271 { 28, 4, "c0_taglo2" },
272 { 28, 5, "c0_datalo2" },
273 { 28, 6, "c0_taglo3" },
274 { 28, 7, "c0_datalo3" },
275 { 29, 1, "c0_datahi" },
276 { 29, 2, "c0_taghi1" },
277 { 29, 3, "c0_datahi1" },
278 { 29, 4, "c0_taghi2" },
279 { 29, 5, "c0_datahi2" },
280 { 29, 6, "c0_taghi3" },
281 { 29, 7, "c0_datahi3" },
284 /* SB-1: MIPS64 (mips_cp0_names_mips3264) with minor mods. */
285 static const char * const mips_cp0_names_sb1[32] =
287 "c0_index", "c0_random", "c0_entrylo0", "c0_entrylo1",
288 "c0_context", "c0_pagemask", "c0_wired", "$7",
289 "c0_badvaddr", "c0_count", "c0_entryhi", "c0_compare",
290 "c0_status", "c0_cause", "c0_epc", "c0_prid",
291 "c0_config", "c0_lladdr", "c0_watchlo", "c0_watchhi",
292 "c0_xcontext", "$21", "$22", "c0_debug",
293 "c0_depc", "c0_perfcnt", "c0_errctl", "c0_cacheerr_i",
294 "c0_taglo_i", "c0_taghi_i", "c0_errorepc", "c0_desave",
297 static const struct mips_cp0sel_name mips_cp0sel_names_sb1[] =
299 { 16, 1, "c0_config1" },
300 { 18, 1, "c0_watchlo,1" },
301 { 19, 1, "c0_watchhi,1" },
302 { 22, 0, "c0_perftrace" },
303 { 23, 3, "c0_edebug" },
304 { 25, 1, "c0_perfcnt,1" },
305 { 25, 2, "c0_perfcnt,2" },
306 { 25, 3, "c0_perfcnt,3" },
307 { 25, 4, "c0_perfcnt,4" },
308 { 25, 5, "c0_perfcnt,5" },
309 { 25, 6, "c0_perfcnt,6" },
310 { 25, 7, "c0_perfcnt,7" },
311 { 26, 1, "c0_buserr_pa" },
312 { 27, 1, "c0_cacheerr_d" },
313 { 27, 3, "c0_cacheerr_d_pa" },
314 { 28, 1, "c0_datalo_i" },
315 { 28, 2, "c0_taglo_d" },
316 { 28, 3, "c0_datalo_d" },
317 { 29, 1, "c0_datahi_i" },
318 { 29, 2, "c0_taghi_d" },
319 { 29, 3, "c0_datahi_d" },
322 /* Xlr cop0 register names. */
323 static const char * const mips_cp0_names_xlr[32] = {
324 "c0_index", "c0_random", "c0_entrylo0", "c0_entrylo1",
325 "c0_context", "c0_pagemask", "c0_wired", "$7",
326 "c0_badvaddr", "c0_count", "c0_entryhi", "c0_compare",
327 "c0_status", "c0_cause", "c0_epc", "c0_prid",
328 "c0_config", "c0_lladdr", "c0_watchlo", "c0_watchhi",
329 "c0_xcontext", "$21", "$22", "c0_debug",
330 "c0_depc", "c0_perfcnt", "c0_errctl", "c0_cacheerr_i",
331 "c0_taglo_i", "c0_taghi_i", "c0_errorepc", "c0_desave",
334 /* XLR's CP0 Select Registers. */
336 static const struct mips_cp0sel_name mips_cp0sel_names_xlr[] = {
337 { 9, 6, "c0_extintreq" },
338 { 9, 7, "c0_extintmask" },
339 { 15, 1, "c0_ebase" },
340 { 16, 1, "c0_config1" },
341 { 16, 2, "c0_config2" },
342 { 16, 3, "c0_config3" },
343 { 16, 7, "c0_procid2" },
344 { 18, 1, "c0_watchlo,1" },
345 { 18, 2, "c0_watchlo,2" },
346 { 18, 3, "c0_watchlo,3" },
347 { 18, 4, "c0_watchlo,4" },
348 { 18, 5, "c0_watchlo,5" },
349 { 18, 6, "c0_watchlo,6" },
350 { 18, 7, "c0_watchlo,7" },
351 { 19, 1, "c0_watchhi,1" },
352 { 19, 2, "c0_watchhi,2" },
353 { 19, 3, "c0_watchhi,3" },
354 { 19, 4, "c0_watchhi,4" },
355 { 19, 5, "c0_watchhi,5" },
356 { 19, 6, "c0_watchhi,6" },
357 { 19, 7, "c0_watchhi,7" },
358 { 25, 1, "c0_perfcnt,1" },
359 { 25, 2, "c0_perfcnt,2" },
360 { 25, 3, "c0_perfcnt,3" },
361 { 25, 4, "c0_perfcnt,4" },
362 { 25, 5, "c0_perfcnt,5" },
363 { 25, 6, "c0_perfcnt,6" },
364 { 25, 7, "c0_perfcnt,7" },
365 { 27, 1, "c0_cacheerr,1" },
366 { 27, 2, "c0_cacheerr,2" },
367 { 27, 3, "c0_cacheerr,3" },
368 { 28, 1, "c0_datalo" },
369 { 29, 1, "c0_datahi" }
372 static const char * const mips_hwr_names_numeric[32] =
374 "$0", "$1", "$2", "$3", "$4", "$5", "$6", "$7",
375 "$8", "$9", "$10", "$11", "$12", "$13", "$14", "$15",
376 "$16", "$17", "$18", "$19", "$20", "$21", "$22", "$23",
377 "$24", "$25", "$26", "$27", "$28", "$29", "$30", "$31"
380 static const char * const mips_hwr_names_mips3264r2[32] =
382 "hwr_cpunum", "hwr_synci_step", "hwr_cc", "hwr_ccres",
383 "$4", "$5", "$6", "$7",
384 "$8", "$9", "$10", "$11", "$12", "$13", "$14", "$15",
385 "$16", "$17", "$18", "$19", "$20", "$21", "$22", "$23",
386 "$24", "$25", "$26", "$27", "$28", "$29", "$30", "$31"
389 struct mips_abi_choice
392 const char * const *gpr_names;
393 const char * const *fpr_names;
396 struct mips_abi_choice mips_abi_choices[] =
398 { "numeric", mips_gpr_names_numeric, mips_fpr_names_numeric },
399 { "32", mips_gpr_names_oldabi, mips_fpr_names_32 },
400 { "n32", mips_gpr_names_newabi, mips_fpr_names_n32 },
401 { "64", mips_gpr_names_newabi, mips_fpr_names_64 },
404 struct mips_arch_choice
408 unsigned long bfd_mach;
411 const char * const *cp0_names;
412 const struct mips_cp0sel_name *cp0sel_names;
413 unsigned int cp0sel_names_len;
414 const char * const *hwr_names;
417 const struct mips_arch_choice mips_arch_choices[] =
419 { "numeric", 0, 0, 0, 0,
420 mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
422 { "r3000", 1, bfd_mach_mips3000, CPU_R3000, ISA_MIPS1,
423 mips_cp0_names_r3000, NULL, 0, mips_hwr_names_numeric },
424 { "r3900", 1, bfd_mach_mips3900, CPU_R3900, ISA_MIPS1,
425 mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
426 { "r4000", 1, bfd_mach_mips4000, CPU_R4000, ISA_MIPS3,
427 mips_cp0_names_r4000, NULL, 0, mips_hwr_names_numeric },
428 { "r4010", 1, bfd_mach_mips4010, CPU_R4010, ISA_MIPS2,
429 mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
430 { "vr4100", 1, bfd_mach_mips4100, CPU_VR4100, ISA_MIPS3,
431 mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
432 { "vr4111", 1, bfd_mach_mips4111, CPU_R4111, ISA_MIPS3,
433 mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
434 { "vr4120", 1, bfd_mach_mips4120, CPU_VR4120, ISA_MIPS3,
435 mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
436 { "r4300", 1, bfd_mach_mips4300, CPU_R4300, ISA_MIPS3,
437 mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
438 { "r4400", 1, bfd_mach_mips4400, CPU_R4400, ISA_MIPS3,
439 mips_cp0_names_r4000, NULL, 0, mips_hwr_names_numeric },
440 { "r4600", 1, bfd_mach_mips4600, CPU_R4600, ISA_MIPS3,
441 mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
442 { "r4650", 1, bfd_mach_mips4650, CPU_R4650, ISA_MIPS3,
443 mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
444 { "r5000", 1, bfd_mach_mips5000, CPU_R5000, ISA_MIPS4,
445 mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
446 { "vr5400", 1, bfd_mach_mips5400, CPU_VR5400, ISA_MIPS4,
447 mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
448 { "vr5500", 1, bfd_mach_mips5500, CPU_VR5500, ISA_MIPS4,
449 mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
450 { "r6000", 1, bfd_mach_mips6000, CPU_R6000, ISA_MIPS2,
451 mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
452 { "rm7000", 1, bfd_mach_mips7000, CPU_RM7000, ISA_MIPS4,
453 mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
454 { "rm9000", 1, bfd_mach_mips7000, CPU_RM7000, ISA_MIPS4,
455 mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
456 { "r8000", 1, bfd_mach_mips8000, CPU_R8000, ISA_MIPS4,
457 mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
458 { "r10000", 1, bfd_mach_mips10000, CPU_R10000, ISA_MIPS4,
459 mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
460 { "r12000", 1, bfd_mach_mips12000, CPU_R12000, ISA_MIPS4,
461 mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
462 { "r14000", 1, bfd_mach_mips14000, CPU_R14000, ISA_MIPS4,
463 mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
464 { "r16000", 1, bfd_mach_mips16000, CPU_R16000, ISA_MIPS4,
465 mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
466 { "mips5", 1, bfd_mach_mips5, CPU_MIPS5, ISA_MIPS5,
467 mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
469 /* For stock MIPS32, disassemble all applicable MIPS-specified ASEs.
470 Note that MIPS-3D and MDMX are not applicable to MIPS32. (See
471 _MIPS32 Architecture For Programmers Volume I: Introduction to the
472 MIPS32 Architecture_ (MIPS Document Number MD00082, Revision 0.95),
474 { "mips32", 1, bfd_mach_mipsisa32, CPU_MIPS32,
475 ISA_MIPS32 | INSN_SMARTMIPS,
476 mips_cp0_names_mips3264,
477 mips_cp0sel_names_mips3264, ARRAY_SIZE (mips_cp0sel_names_mips3264),
478 mips_hwr_names_numeric },
480 { "mips32r2", 1, bfd_mach_mipsisa32r2, CPU_MIPS32R2,
481 (ISA_MIPS32R2 | INSN_SMARTMIPS | INSN_DSP | INSN_DSPR2
482 | INSN_MIPS3D | INSN_MT),
483 mips_cp0_names_mips3264r2,
484 mips_cp0sel_names_mips3264r2, ARRAY_SIZE (mips_cp0sel_names_mips3264r2),
485 mips_hwr_names_mips3264r2 },
487 /* For stock MIPS64, disassemble all applicable MIPS-specified ASEs. */
488 { "mips64", 1, bfd_mach_mipsisa64, CPU_MIPS64,
489 ISA_MIPS64 | INSN_MIPS3D | INSN_MDMX,
490 mips_cp0_names_mips3264,
491 mips_cp0sel_names_mips3264, ARRAY_SIZE (mips_cp0sel_names_mips3264),
492 mips_hwr_names_numeric },
494 { "mips64r2", 1, bfd_mach_mipsisa64r2, CPU_MIPS64R2,
495 (ISA_MIPS64R2 | INSN_MIPS3D | INSN_DSP | INSN_DSPR2
496 | INSN_DSP64 | INSN_MT | INSN_MDMX),
497 mips_cp0_names_mips3264r2,
498 mips_cp0sel_names_mips3264r2, ARRAY_SIZE (mips_cp0sel_names_mips3264r2),
499 mips_hwr_names_mips3264r2 },
501 { "sb1", 1, bfd_mach_mips_sb1, CPU_SB1,
502 ISA_MIPS64 | INSN_MIPS3D | INSN_SB1,
504 mips_cp0sel_names_sb1, ARRAY_SIZE (mips_cp0sel_names_sb1),
505 mips_hwr_names_numeric },
507 { "loongson2e", 1, bfd_mach_mips_loongson_2e, CPU_LOONGSON_2E,
508 ISA_MIPS3 | INSN_LOONGSON_2E, mips_cp0_names_numeric,
509 NULL, 0, mips_hwr_names_numeric },
511 { "loongson2f", 1, bfd_mach_mips_loongson_2f, CPU_LOONGSON_2F,
512 ISA_MIPS3 | INSN_LOONGSON_2F, mips_cp0_names_numeric,
513 NULL, 0, mips_hwr_names_numeric },
515 { "octeon", 1, bfd_mach_mips_octeon, CPU_OCTEON,
516 ISA_MIPS64R2 | INSN_OCTEON, mips_cp0_names_numeric, NULL, 0,
517 mips_hwr_names_numeric },
519 { "xlr", 1, bfd_mach_mips_xlr, CPU_XLR,
520 ISA_MIPS64 | INSN_XLR,
522 mips_cp0sel_names_xlr, ARRAY_SIZE (mips_cp0sel_names_xlr),
523 mips_hwr_names_numeric },
525 /* This entry, mips16, is here only for ISA/processor selection; do
526 not print its name. */
527 { "", 1, bfd_mach_mips16, CPU_MIPS16, ISA_MIPS3,
528 mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
531 /* ISA and processor type to disassemble for, and register names to use.
532 set_default_mips_dis_options and parse_mips_dis_options fill in these
534 static int mips_processor;
536 static const char * const *mips_gpr_names;
537 static const char * const *mips_fpr_names;
538 static const char * const *mips_cp0_names;
539 static const struct mips_cp0sel_name *mips_cp0sel_names;
540 static int mips_cp0sel_names_len;
541 static const char * const *mips_hwr_names;
544 static int no_aliases; /* If set disassemble as most general inst. */
546 static const struct mips_abi_choice *
547 choose_abi_by_name (const char *name, unsigned int namelen)
549 const struct mips_abi_choice *c;
552 for (i = 0, c = NULL; i < ARRAY_SIZE (mips_abi_choices) && c == NULL; i++)
553 if (strncmp (mips_abi_choices[i].name, name, namelen) == 0
554 && strlen (mips_abi_choices[i].name) == namelen)
555 c = &mips_abi_choices[i];
560 static const struct mips_arch_choice *
561 choose_arch_by_name (const char *name, unsigned int namelen)
563 const struct mips_arch_choice *c = NULL;
566 for (i = 0, c = NULL; i < ARRAY_SIZE (mips_arch_choices) && c == NULL; i++)
567 if (strncmp (mips_arch_choices[i].name, name, namelen) == 0
568 && strlen (mips_arch_choices[i].name) == namelen)
569 c = &mips_arch_choices[i];
574 static const struct mips_arch_choice *
575 choose_arch_by_number (unsigned long mach)
577 static unsigned long hint_bfd_mach;
578 static const struct mips_arch_choice *hint_arch_choice;
579 const struct mips_arch_choice *c;
582 /* We optimize this because even if the user specifies no
583 flags, this will be done for every instruction! */
584 if (hint_bfd_mach == mach
585 && hint_arch_choice != NULL
586 && hint_arch_choice->bfd_mach == hint_bfd_mach)
587 return hint_arch_choice;
589 for (i = 0, c = NULL; i < ARRAY_SIZE (mips_arch_choices) && c == NULL; i++)
591 if (mips_arch_choices[i].bfd_mach_valid
592 && mips_arch_choices[i].bfd_mach == mach)
594 c = &mips_arch_choices[i];
595 hint_bfd_mach = mach;
596 hint_arch_choice = c;
602 /* Check if the object uses NewABI conventions. */
605 is_newabi (Elf_Internal_Ehdr *header)
607 /* There are no old-style ABIs which use 64-bit ELF. */
608 if (header->e_ident[EI_CLASS] == ELFCLASS64)
611 /* If a 32-bit ELF file, n32 is a new-style ABI. */
612 if ((header->e_flags & EF_MIPS_ABI2) != 0)
619 set_default_mips_dis_options (struct disassemble_info *info)
621 const struct mips_arch_choice *chosen_arch;
623 /* Defaults: mipsIII/r3000 (?!), (o)32-style ("oldabi") GPR names,
624 and numeric FPR, CP0 register, and HWR names. */
625 mips_isa = ISA_MIPS3;
626 mips_processor = CPU_R3000;
627 mips_gpr_names = mips_gpr_names_oldabi;
628 mips_fpr_names = mips_fpr_names_numeric;
629 mips_cp0_names = mips_cp0_names_numeric;
630 mips_cp0sel_names = NULL;
631 mips_cp0sel_names_len = 0;
632 mips_hwr_names = mips_hwr_names_numeric;
635 /* If an ELF "newabi" binary, use the n32/(n)64 GPR names. */
636 if (info->flavour == bfd_target_elf_flavour && info->section != NULL)
638 Elf_Internal_Ehdr *header;
640 header = elf_elfheader (info->section->owner);
641 if (is_newabi (header))
642 mips_gpr_names = mips_gpr_names_newabi;
645 /* Set ISA, architecture, and cp0 register names as best we can. */
646 #if ! SYMTAB_AVAILABLE
647 /* This is running out on a target machine, not in a host tool.
648 FIXME: Where does mips_target_info come from? */
649 target_processor = mips_target_info.processor;
650 mips_isa = mips_target_info.isa;
652 chosen_arch = choose_arch_by_number (info->mach);
653 if (chosen_arch != NULL)
655 mips_processor = chosen_arch->processor;
656 mips_isa = chosen_arch->isa;
657 mips_cp0_names = chosen_arch->cp0_names;
658 mips_cp0sel_names = chosen_arch->cp0sel_names;
659 mips_cp0sel_names_len = chosen_arch->cp0sel_names_len;
660 mips_hwr_names = chosen_arch->hwr_names;
666 parse_mips_dis_option (const char *option, unsigned int len)
668 unsigned int i, optionlen, vallen;
670 const struct mips_abi_choice *chosen_abi;
671 const struct mips_arch_choice *chosen_arch;
673 /* Try to match options that are simple flags */
674 if (CONST_STRNEQ (option, "no-aliases"))
680 /* Look for the = that delimits the end of the option name. */
681 for (i = 0; i < len; i++)
682 if (option[i] == '=')
685 if (i == 0) /* Invalid option: no name before '='. */
687 if (i == len) /* Invalid option: no '='. */
689 if (i == (len - 1)) /* Invalid option: no value after '='. */
693 val = option + (optionlen + 1);
694 vallen = len - (optionlen + 1);
696 if (strncmp ("gpr-names", option, optionlen) == 0
697 && strlen ("gpr-names") == optionlen)
699 chosen_abi = choose_abi_by_name (val, vallen);
700 if (chosen_abi != NULL)
701 mips_gpr_names = chosen_abi->gpr_names;
705 if (strncmp ("fpr-names", option, optionlen) == 0
706 && strlen ("fpr-names") == optionlen)
708 chosen_abi = choose_abi_by_name (val, vallen);
709 if (chosen_abi != NULL)
710 mips_fpr_names = chosen_abi->fpr_names;
714 if (strncmp ("cp0-names", option, optionlen) == 0
715 && strlen ("cp0-names") == optionlen)
717 chosen_arch = choose_arch_by_name (val, vallen);
718 if (chosen_arch != NULL)
720 mips_cp0_names = chosen_arch->cp0_names;
721 mips_cp0sel_names = chosen_arch->cp0sel_names;
722 mips_cp0sel_names_len = chosen_arch->cp0sel_names_len;
727 if (strncmp ("hwr-names", option, optionlen) == 0
728 && strlen ("hwr-names") == optionlen)
730 chosen_arch = choose_arch_by_name (val, vallen);
731 if (chosen_arch != NULL)
732 mips_hwr_names = chosen_arch->hwr_names;
736 if (strncmp ("reg-names", option, optionlen) == 0
737 && strlen ("reg-names") == optionlen)
739 /* We check both ABI and ARCH here unconditionally, so
740 that "numeric" will do the desirable thing: select
741 numeric register names for all registers. Other than
742 that, a given name probably won't match both. */
743 chosen_abi = choose_abi_by_name (val, vallen);
744 if (chosen_abi != NULL)
746 mips_gpr_names = chosen_abi->gpr_names;
747 mips_fpr_names = chosen_abi->fpr_names;
749 chosen_arch = choose_arch_by_name (val, vallen);
750 if (chosen_arch != NULL)
752 mips_cp0_names = chosen_arch->cp0_names;
753 mips_cp0sel_names = chosen_arch->cp0sel_names;
754 mips_cp0sel_names_len = chosen_arch->cp0sel_names_len;
755 mips_hwr_names = chosen_arch->hwr_names;
760 /* Invalid option. */
764 parse_mips_dis_options (const char *options)
766 const char *option_end;
771 while (*options != '\0')
773 /* Skip empty options. */
780 /* We know that *options is neither NUL or a comma. */
781 option_end = options + 1;
782 while (*option_end != ',' && *option_end != '\0')
785 parse_mips_dis_option (options, option_end - options);
787 /* Go on to the next one. If option_end points to a comma, it
788 will be skipped above. */
789 options = option_end;
793 static const struct mips_cp0sel_name *
794 lookup_mips_cp0sel_name (const struct mips_cp0sel_name *names,
801 for (i = 0; i < len; i++)
802 if (names[i].cp0reg == cp0reg && names[i].sel == sel)
807 /* Print insn arguments for 32/64-bit code. */
810 print_insn_args (const char *d,
811 register unsigned long int l,
813 struct disassemble_info *info,
814 const struct mips_opcode *opp)
817 unsigned int lsb, msb, msbd;
821 for (; *d != '\0'; d++)
830 (*info->fprintf_func) (info->stream, "%c", *d);
834 /* Extension character; switch for second char. */
839 /* xgettext:c-format */
840 (*info->fprintf_func) (info->stream,
841 _("# internal error, incomplete extension sequence (+)"));
845 lsb = (l >> OP_SH_SHAMT) & OP_MASK_SHAMT;
846 (*info->fprintf_func) (info->stream, "0x%x", lsb);
850 msb = (l >> OP_SH_INSMSB) & OP_MASK_INSMSB;
851 (*info->fprintf_func) (info->stream, "0x%x", msb - lsb + 1);
855 (*info->fprintf_func) (info->stream, "0x%lx",
856 (l >> OP_SH_UDI1) & OP_MASK_UDI1);
860 (*info->fprintf_func) (info->stream, "0x%lx",
861 (l >> OP_SH_UDI2) & OP_MASK_UDI2);
865 (*info->fprintf_func) (info->stream, "0x%lx",
866 (l >> OP_SH_UDI3) & OP_MASK_UDI3);
870 (*info->fprintf_func) (info->stream, "0x%lx",
871 (l >> OP_SH_UDI4) & OP_MASK_UDI4);
876 msbd = (l >> OP_SH_EXTMSBD) & OP_MASK_EXTMSBD;
877 (*info->fprintf_func) (info->stream, "0x%x", msbd + 1);
882 const struct mips_cp0sel_name *n;
883 unsigned int cp0reg, sel;
885 cp0reg = (l >> OP_SH_RD) & OP_MASK_RD;
886 sel = (l >> OP_SH_SEL) & OP_MASK_SEL;
888 /* CP0 register including 'sel' code for mtcN (et al.), to be
889 printed textually if known. If not known, print both
890 CP0 register name and sel numerically since CP0 register
891 with sel 0 may have a name unrelated to register being
893 n = lookup_mips_cp0sel_name(mips_cp0sel_names,
894 mips_cp0sel_names_len, cp0reg, sel);
896 (*info->fprintf_func) (info->stream, "%s", n->name);
898 (*info->fprintf_func) (info->stream, "$%d,%d", cp0reg, sel);
903 lsb = ((l >> OP_SH_SHAMT) & OP_MASK_SHAMT) + 32;
904 (*info->fprintf_func) (info->stream, "0x%x", lsb);
908 msb = ((l >> OP_SH_INSMSB) & OP_MASK_INSMSB) + 32;
909 (*info->fprintf_func) (info->stream, "0x%x", msb - lsb + 1);
913 msbd = ((l >> OP_SH_EXTMSBD) & OP_MASK_EXTMSBD) + 32;
914 (*info->fprintf_func) (info->stream, "0x%x", msbd + 1);
917 case 't': /* Coprocessor 0 reg name */
918 (*info->fprintf_func) (info->stream, "%s",
919 mips_cp0_names[(l >> OP_SH_RT) &
923 case 'T': /* Coprocessor 0 reg name */
925 const struct mips_cp0sel_name *n;
926 unsigned int cp0reg, sel;
928 cp0reg = (l >> OP_SH_RT) & OP_MASK_RT;
929 sel = (l >> OP_SH_SEL) & OP_MASK_SEL;
931 /* CP0 register including 'sel' code for mftc0, to be
932 printed textually if known. If not known, print both
933 CP0 register name and sel numerically since CP0 register
934 with sel 0 may have a name unrelated to register being
936 n = lookup_mips_cp0sel_name(mips_cp0sel_names,
937 mips_cp0sel_names_len, cp0reg, sel);
939 (*info->fprintf_func) (info->stream, "%s", n->name);
941 (*info->fprintf_func) (info->stream, "$%d,%d", cp0reg, sel);
945 case 'x': /* bbit bit index */
946 (*info->fprintf_func) (info->stream, "0x%lx",
947 (l >> OP_SH_BBITIND) & OP_MASK_BBITIND);
950 case 'p': /* cins, cins32, exts and exts32 position */
951 (*info->fprintf_func) (info->stream, "0x%lx",
952 (l >> OP_SH_CINSPOS) & OP_MASK_CINSPOS);
955 case 's': /* cins and exts length-minus-one */
956 (*info->fprintf_func) (info->stream, "0x%lx",
957 (l >> OP_SH_CINSLM1) & OP_MASK_CINSLM1);
960 case 'S': /* cins32 and exts32 length-minus-one field */
961 (*info->fprintf_func) (info->stream, "0x%lx",
962 (l >> OP_SH_CINSLM1) & OP_MASK_CINSLM1);
965 case 'Q': /* seqi/snei immediate field */
966 op = (l >> OP_SH_SEQI) & OP_MASK_SEQI;
967 /* Sign-extend it. */
968 op = (op ^ 512) - 512;
969 (*info->fprintf_func) (info->stream, "%d", op);
973 /* xgettext:c-format */
974 (*info->fprintf_func) (info->stream,
975 _("# internal error, undefined extension sequence (+%c)"),
982 (*info->fprintf_func) (info->stream, "0x%lx",
983 (l >> OP_SH_BP) & OP_MASK_BP);
987 (*info->fprintf_func) (info->stream, "0x%lx",
988 (l >> OP_SH_SA3) & OP_MASK_SA3);
992 (*info->fprintf_func) (info->stream, "0x%lx",
993 (l >> OP_SH_SA4) & OP_MASK_SA4);
997 (*info->fprintf_func) (info->stream, "0x%lx",
998 (l >> OP_SH_IMM8) & OP_MASK_IMM8);
1002 (*info->fprintf_func) (info->stream, "0x%lx",
1003 (l >> OP_SH_RS) & OP_MASK_RS);
1007 (*info->fprintf_func) (info->stream, "$ac%ld",
1008 (l >> OP_SH_DSPACC) & OP_MASK_DSPACC);
1012 (*info->fprintf_func) (info->stream, "0x%lx",
1013 (l >> OP_SH_WRDSP) & OP_MASK_WRDSP);
1017 (*info->fprintf_func) (info->stream, "$ac%ld",
1018 (l >> OP_SH_DSPACC_S) & OP_MASK_DSPACC_S);
1021 case '0': /* dsp 6-bit signed immediate in bit 20 */
1022 delta = ((l >> OP_SH_DSPSFT) & OP_MASK_DSPSFT);
1023 if (delta & 0x20) /* test sign bit */
1024 delta |= ~OP_MASK_DSPSFT;
1025 (*info->fprintf_func) (info->stream, "%d", delta);
1028 case ':': /* dsp 7-bit signed immediate in bit 19 */
1029 delta = ((l >> OP_SH_DSPSFT_7) & OP_MASK_DSPSFT_7);
1030 if (delta & 0x40) /* test sign bit */
1031 delta |= ~OP_MASK_DSPSFT_7;
1032 (*info->fprintf_func) (info->stream, "%d", delta);
1036 (*info->fprintf_func) (info->stream, "0x%lx",
1037 (l >> OP_SH_RDDSP) & OP_MASK_RDDSP);
1040 case '@': /* dsp 10-bit signed immediate in bit 16 */
1041 delta = ((l >> OP_SH_IMM10) & OP_MASK_IMM10);
1042 if (delta & 0x200) /* test sign bit */
1043 delta |= ~OP_MASK_IMM10;
1044 (*info->fprintf_func) (info->stream, "%d", delta);
1048 (*info->fprintf_func) (info->stream, "%ld",
1049 (l >> OP_SH_MT_U) & OP_MASK_MT_U);
1053 (*info->fprintf_func) (info->stream, "%ld",
1054 (l >> OP_SH_MT_H) & OP_MASK_MT_H);
1058 (*info->fprintf_func) (info->stream, "$ac%ld",
1059 (l >> OP_SH_MTACC_T) & OP_MASK_MTACC_T);
1063 (*info->fprintf_func) (info->stream, "$ac%ld",
1064 (l >> OP_SH_MTACC_D) & OP_MASK_MTACC_D);
1068 /* Coprocessor register for CTTC1, MTTC2, MTHC2, CTTC2. */
1069 (*info->fprintf_func) (info->stream, "$%ld",
1070 (l >> OP_SH_RD) & OP_MASK_RD);
1077 (*info->fprintf_func) (info->stream, "%s",
1078 mips_gpr_names[(l >> OP_SH_RS) & OP_MASK_RS]);
1083 (*info->fprintf_func) (info->stream, "%s",
1084 mips_gpr_names[(l >> OP_SH_RT) & OP_MASK_RT]);
1089 (*info->fprintf_func) (info->stream, "0x%lx",
1090 (l >> OP_SH_IMMEDIATE) & OP_MASK_IMMEDIATE);
1093 case 'j': /* Same as i, but sign-extended. */
1095 delta = (l >> OP_SH_DELTA) & OP_MASK_DELTA;
1098 (*info->fprintf_func) (info->stream, "%d",
1103 (*info->fprintf_func) (info->stream, "0x%x",
1104 (unsigned int) ((l >> OP_SH_PREFX)
1109 (*info->fprintf_func) (info->stream, "0x%x",
1110 (unsigned int) ((l >> OP_SH_CACHE)
1115 info->target = (((pc + 4) & ~(bfd_vma) 0x0fffffff)
1116 | (((l >> OP_SH_TARGET) & OP_MASK_TARGET) << 2));
1117 /* For gdb disassembler, force odd address on jalx. */
1118 if (info->flavour == bfd_target_unknown_flavour
1119 && strcmp (opp->name, "jalx") == 0)
1121 (*info->print_address_func) (info->target, info);
1125 /* Sign extend the displacement. */
1126 delta = (l >> OP_SH_DELTA) & OP_MASK_DELTA;
1129 info->target = (delta << 2) + pc + INSNLEN;
1130 (*info->print_address_func) (info->target, info);
1134 (*info->fprintf_func) (info->stream, "%s",
1135 mips_gpr_names[(l >> OP_SH_RD) & OP_MASK_RD]);
1140 /* First check for both rd and rt being equal. */
1141 unsigned int reg = (l >> OP_SH_RD) & OP_MASK_RD;
1142 if (reg == ((l >> OP_SH_RT) & OP_MASK_RT))
1143 (*info->fprintf_func) (info->stream, "%s",
1144 mips_gpr_names[reg]);
1147 /* If one is zero use the other. */
1149 (*info->fprintf_func) (info->stream, "%s",
1150 mips_gpr_names[(l >> OP_SH_RT) & OP_MASK_RT]);
1151 else if (((l >> OP_SH_RT) & OP_MASK_RT) == 0)
1152 (*info->fprintf_func) (info->stream, "%s",
1153 mips_gpr_names[reg]);
1154 else /* Bogus, result depends on processor. */
1155 (*info->fprintf_func) (info->stream, "%s or %s",
1156 mips_gpr_names[reg],
1157 mips_gpr_names[(l >> OP_SH_RT) & OP_MASK_RT]);
1163 (*info->fprintf_func) (info->stream, "%s", mips_gpr_names[0]);
1168 (*info->fprintf_func) (info->stream, "0x%lx",
1169 (l >> OP_SH_SHAMT) & OP_MASK_SHAMT);
1173 (*info->fprintf_func) (info->stream, "0x%lx",
1174 (l >> OP_SH_CODE) & OP_MASK_CODE);
1178 (*info->fprintf_func) (info->stream, "0x%lx",
1179 (l >> OP_SH_CODE2) & OP_MASK_CODE2);
1183 (*info->fprintf_func) (info->stream, "0x%lx",
1184 (l >> OP_SH_COPZ) & OP_MASK_COPZ);
1188 (*info->fprintf_func) (info->stream, "0x%lx",
1190 (l >> OP_SH_CODE20) & OP_MASK_CODE20);
1194 (*info->fprintf_func) (info->stream, "0x%lx",
1195 (l >> OP_SH_CODE19) & OP_MASK_CODE19);
1200 (*info->fprintf_func) (info->stream, "%s",
1201 mips_fpr_names[(l >> OP_SH_FS) & OP_MASK_FS]);
1206 (*info->fprintf_func) (info->stream, "%s",
1207 mips_fpr_names[(l >> OP_SH_FT) & OP_MASK_FT]);
1211 (*info->fprintf_func) (info->stream, "%s",
1212 mips_fpr_names[(l >> OP_SH_FD) & OP_MASK_FD]);
1216 (*info->fprintf_func) (info->stream, "%s",
1217 mips_fpr_names[(l >> OP_SH_FR) & OP_MASK_FR]);
1221 /* Coprocessor register for lwcN instructions, et al.
1223 Note that there is no load/store cp0 instructions, and
1224 that FPU (cp1) instructions disassemble this field using
1225 'T' format. Therefore, until we gain understanding of
1226 cp2 register names, we can simply print the register
1228 (*info->fprintf_func) (info->stream, "$%ld",
1229 (l >> OP_SH_RT) & OP_MASK_RT);
1233 /* Coprocessor register for mtcN instructions, et al. Note
1234 that FPU (cp1) instructions disassemble this field using
1235 'S' format. Therefore, we only need to worry about cp0,
1237 op = (l >> OP_SH_OP) & OP_MASK_OP;
1238 if (op == OP_OP_COP0)
1239 (*info->fprintf_func) (info->stream, "%s",
1240 mips_cp0_names[(l >> OP_SH_RD) & OP_MASK_RD]);
1242 (*info->fprintf_func) (info->stream, "$%ld",
1243 (l >> OP_SH_RD) & OP_MASK_RD);
1247 (*info->fprintf_func) (info->stream, "%s",
1248 mips_hwr_names[(l >> OP_SH_RD) & OP_MASK_RD]);
1252 (*info->fprintf_func) (info->stream,
1253 ((opp->pinfo & (FP_D | FP_S)) != 0
1254 ? "$fcc%ld" : "$cc%ld"),
1255 (l >> OP_SH_BCC) & OP_MASK_BCC);
1259 (*info->fprintf_func) (info->stream, "$fcc%ld",
1260 (l >> OP_SH_CCC) & OP_MASK_CCC);
1264 (*info->fprintf_func) (info->stream, "%ld",
1265 (l >> OP_SH_PERFREG) & OP_MASK_PERFREG);
1269 (*info->fprintf_func) (info->stream, "%ld",
1270 (l >> OP_SH_VECBYTE) & OP_MASK_VECBYTE);
1274 (*info->fprintf_func) (info->stream, "%ld",
1275 (l >> OP_SH_VECALIGN) & OP_MASK_VECALIGN);
1279 (*info->fprintf_func) (info->stream, "%ld",
1280 (l >> OP_SH_SEL) & OP_MASK_SEL);
1284 (*info->fprintf_func) (info->stream, "%ld",
1285 (l >> OP_SH_ALN) & OP_MASK_ALN);
1290 unsigned int vsel = (l >> OP_SH_VSEL) & OP_MASK_VSEL;
1292 if ((vsel & 0x10) == 0)
1297 for (fmt = 0; fmt < 3; fmt++, vsel >>= 1)
1298 if ((vsel & 1) == 0)
1300 (*info->fprintf_func) (info->stream, "$v%ld[%d]",
1301 (l >> OP_SH_FT) & OP_MASK_FT,
1304 else if ((vsel & 0x08) == 0)
1306 (*info->fprintf_func) (info->stream, "$v%ld",
1307 (l >> OP_SH_FT) & OP_MASK_FT);
1311 (*info->fprintf_func) (info->stream, "0x%lx",
1312 (l >> OP_SH_FT) & OP_MASK_FT);
1318 (*info->fprintf_func) (info->stream, "$v%ld",
1319 (l >> OP_SH_FD) & OP_MASK_FD);
1323 (*info->fprintf_func) (info->stream, "$v%ld",
1324 (l >> OP_SH_FS) & OP_MASK_FS);
1328 (*info->fprintf_func) (info->stream, "$v%ld",
1329 (l >> OP_SH_FT) & OP_MASK_FT);
1333 /* xgettext:c-format */
1334 (*info->fprintf_func) (info->stream,
1335 _("# internal error, undefined modifier (%c)"),
1342 /* Print the mips instruction at address MEMADDR in debugged memory,
1343 on using INFO. Returns length of the instruction, in bytes, which is
1344 always INSNLEN. BIGENDIAN must be 1 if this is big-endian code, 0 if
1345 this is little-endian code. */
1348 print_insn_mips (bfd_vma memaddr,
1349 unsigned long int word,
1350 struct disassemble_info *info)
1352 const struct mips_opcode *op;
1353 static bfd_boolean init = 0;
1354 static const struct mips_opcode *mips_hash[OP_MASK_OP + 1];
1356 /* Build a hash table to shorten the search time. */
1361 for (i = 0; i <= OP_MASK_OP; i++)
1363 for (op = mips_opcodes; op < &mips_opcodes[NUMOPCODES]; op++)
1365 if (op->pinfo == INSN_MACRO
1366 || (no_aliases && (op->pinfo2 & INSN2_ALIAS)))
1368 if (i == ((op->match >> OP_SH_OP) & OP_MASK_OP))
1379 info->bytes_per_chunk = INSNLEN;
1380 info->display_endian = info->endian;
1381 info->insn_info_valid = 1;
1382 info->branch_delay_insns = 0;
1383 info->data_size = 0;
1384 info->insn_type = dis_nonbranch;
1388 op = mips_hash[(word >> OP_SH_OP) & OP_MASK_OP];
1391 for (; op < &mips_opcodes[NUMOPCODES]; op++)
1393 if (op->pinfo != INSN_MACRO
1394 && !(no_aliases && (op->pinfo2 & INSN2_ALIAS))
1395 && (word & op->mask) == op->match)
1399 /* We always allow to disassemble the jalx instruction. */
1400 if (! OPCODE_IS_MEMBER (op, mips_isa, mips_processor)
1401 && strcmp (op->name, "jalx"))
1404 /* Figure out instruction type and branch delay information. */
1405 if ((op->pinfo & INSN_UNCOND_BRANCH_DELAY) != 0)
1407 if ((info->insn_type & INSN_WRITE_GPR_31) != 0)
1408 info->insn_type = dis_jsr;
1410 info->insn_type = dis_branch;
1411 info->branch_delay_insns = 1;
1413 else if ((op->pinfo & (INSN_COND_BRANCH_DELAY
1414 | INSN_COND_BRANCH_LIKELY)) != 0)
1416 if ((info->insn_type & INSN_WRITE_GPR_31) != 0)
1417 info->insn_type = dis_condjsr;
1419 info->insn_type = dis_condbranch;
1420 info->branch_delay_insns = 1;
1422 else if ((op->pinfo & (INSN_STORE_MEMORY
1423 | INSN_LOAD_MEMORY_DELAY)) != 0)
1424 info->insn_type = dis_dref;
1426 (*info->fprintf_func) (info->stream, "%s", op->name);
1429 if (d != NULL && *d != '\0')
1431 (*info->fprintf_func) (info->stream, "\t");
1432 print_insn_args (d, word, memaddr, info, op);
1440 /* Handle undefined instructions. */
1441 info->insn_type = dis_noninsn;
1442 (*info->fprintf_func) (info->stream, "0x%lx", word);
1446 /* Disassemble an operand for a mips16 instruction. */
1449 print_mips16_insn_arg (char type,
1450 const struct mips_opcode *op,
1452 bfd_boolean use_extend,
1455 struct disassemble_info *info)
1462 (*info->fprintf_func) (info->stream, "%c", type);
1467 (*info->fprintf_func) (info->stream, "%s",
1468 mips16_reg_names(((l >> MIPS16OP_SH_RY)
1469 & MIPS16OP_MASK_RY)));
1474 (*info->fprintf_func) (info->stream, "%s",
1475 mips16_reg_names(((l >> MIPS16OP_SH_RX)
1476 & MIPS16OP_MASK_RX)));
1480 (*info->fprintf_func) (info->stream, "%s",
1481 mips16_reg_names(((l >> MIPS16OP_SH_RZ)
1482 & MIPS16OP_MASK_RZ)));
1486 (*info->fprintf_func) (info->stream, "%s",
1487 mips16_reg_names(((l >> MIPS16OP_SH_MOVE32Z)
1488 & MIPS16OP_MASK_MOVE32Z)));
1492 (*info->fprintf_func) (info->stream, "%s", mips_gpr_names[0]);
1496 (*info->fprintf_func) (info->stream, "%s", mips_gpr_names[29]);
1500 (*info->fprintf_func) (info->stream, "$pc");
1504 (*info->fprintf_func) (info->stream, "%s", mips_gpr_names[31]);
1508 (*info->fprintf_func) (info->stream, "%s",
1509 mips_gpr_names[((l >> MIPS16OP_SH_REGR32)
1510 & MIPS16OP_MASK_REGR32)]);
1514 (*info->fprintf_func) (info->stream, "%s",
1515 mips_gpr_names[MIPS16OP_EXTRACT_REG32R (l)]);
1541 int immed, nbits, shift, signedp, extbits, pcrel, extu, branch;
1553 immed = (l >> MIPS16OP_SH_RZ) & MIPS16OP_MASK_RZ;
1559 immed = (l >> MIPS16OP_SH_RX) & MIPS16OP_MASK_RX;
1565 immed = (l >> MIPS16OP_SH_RZ) & MIPS16OP_MASK_RZ;
1571 immed = (l >> MIPS16OP_SH_RX) & MIPS16OP_MASK_RX;
1577 immed = (l >> MIPS16OP_SH_IMM4) & MIPS16OP_MASK_IMM4;
1583 immed = (l >> MIPS16OP_SH_IMM5) & MIPS16OP_MASK_IMM5;
1584 info->insn_type = dis_dref;
1585 info->data_size = 1;
1590 immed = (l >> MIPS16OP_SH_IMM5) & MIPS16OP_MASK_IMM5;
1591 info->insn_type = dis_dref;
1592 info->data_size = 2;
1597 immed = (l >> MIPS16OP_SH_IMM5) & MIPS16OP_MASK_IMM5;
1598 if ((op->pinfo & MIPS16_INSN_READ_PC) == 0
1599 && (op->pinfo & MIPS16_INSN_READ_SP) == 0)
1601 info->insn_type = dis_dref;
1602 info->data_size = 4;
1608 immed = (l >> MIPS16OP_SH_IMM5) & MIPS16OP_MASK_IMM5;
1609 info->insn_type = dis_dref;
1610 info->data_size = 8;
1614 immed = (l >> MIPS16OP_SH_IMM5) & MIPS16OP_MASK_IMM5;
1619 immed = (l >> MIPS16OP_SH_IMM6) & MIPS16OP_MASK_IMM6;
1623 immed = (l >> MIPS16OP_SH_IMM8) & MIPS16OP_MASK_IMM8;
1628 immed = (l >> MIPS16OP_SH_IMM8) & MIPS16OP_MASK_IMM8;
1629 /* FIXME: This might be lw, or it might be addiu to $sp or
1630 $pc. We assume it's load. */
1631 info->insn_type = dis_dref;
1632 info->data_size = 4;
1637 immed = (l >> MIPS16OP_SH_IMM8) & MIPS16OP_MASK_IMM8;
1638 info->insn_type = dis_dref;
1639 info->data_size = 8;
1643 immed = (l >> MIPS16OP_SH_IMM8) & MIPS16OP_MASK_IMM8;
1648 immed = (l >> MIPS16OP_SH_IMM8) & MIPS16OP_MASK_IMM8;
1654 immed = (l >> MIPS16OP_SH_IMM8) & MIPS16OP_MASK_IMM8;
1659 immed = (l >> MIPS16OP_SH_IMM8) & MIPS16OP_MASK_IMM8;
1666 immed = (l >> MIPS16OP_SH_IMM11) & MIPS16OP_MASK_IMM11;
1674 immed = (l >> MIPS16OP_SH_IMM8) & MIPS16OP_MASK_IMM8;
1676 /* FIXME: This can be lw or la. We assume it is lw. */
1677 info->insn_type = dis_dref;
1678 info->data_size = 4;
1683 immed = (l >> MIPS16OP_SH_IMM5) & MIPS16OP_MASK_IMM5;
1685 info->insn_type = dis_dref;
1686 info->data_size = 8;
1691 immed = (l >> MIPS16OP_SH_IMM5) & MIPS16OP_MASK_IMM5;
1700 if (signedp && immed >= (1 << (nbits - 1)))
1701 immed -= 1 << nbits;
1703 if ((type == '<' || type == '>' || type == '[' || type == ']')
1710 immed |= ((extend & 0x1f) << 11) | (extend & 0x7e0);
1711 else if (extbits == 15)
1712 immed |= ((extend & 0xf) << 11) | (extend & 0x7f0);
1714 immed = ((extend >> 6) & 0x1f) | (extend & 0x20);
1715 immed &= (1 << extbits) - 1;
1716 if (! extu && immed >= (1 << (extbits - 1)))
1717 immed -= 1 << extbits;
1721 (*info->fprintf_func) (info->stream, "%d", immed);
1729 baseaddr = memaddr + 2;
1731 else if (use_extend)
1732 baseaddr = memaddr - 2;
1740 /* If this instruction is in the delay slot of a jr
1741 instruction, the base address is the address of the
1742 jr instruction. If it is in the delay slot of jalr
1743 instruction, the base address is the address of the
1744 jalr instruction. This test is unreliable: we have
1745 no way of knowing whether the previous word is
1746 instruction or data. */
1747 status = (*info->read_memory_func) (memaddr - 4, buffer, 2,
1750 && (((info->endian == BFD_ENDIAN_BIG
1751 ? bfd_getb16 (buffer)
1752 : bfd_getl16 (buffer))
1753 & 0xf800) == 0x1800))
1754 baseaddr = memaddr - 4;
1757 status = (*info->read_memory_func) (memaddr - 2, buffer,
1760 && (((info->endian == BFD_ENDIAN_BIG
1761 ? bfd_getb16 (buffer)
1762 : bfd_getl16 (buffer))
1763 & 0xf81f) == 0xe800))
1764 baseaddr = memaddr - 2;
1767 info->target = (baseaddr & ~((1 << shift) - 1)) + immed;
1769 && info->flavour == bfd_target_unknown_flavour)
1770 /* For gdb disassembler, maintain odd address. */
1772 (*info->print_address_func) (info->target, info);
1779 int jalx = l & 0x400;
1783 l = ((l & 0x1f) << 23) | ((l & 0x3e0) << 13) | (extend << 2);
1784 if (!jalx && info->flavour == bfd_target_unknown_flavour)
1785 /* For gdb disassembler, maintain odd address. */
1788 info->target = ((memaddr + 4) & ~(bfd_vma) 0x0fffffff) | l;
1789 (*info->print_address_func) (info->target, info);
1795 int need_comma, amask, smask;
1799 l = (l >> MIPS16OP_SH_IMM6) & MIPS16OP_MASK_IMM6;
1801 amask = (l >> 3) & 7;
1803 if (amask > 0 && amask < 5)
1805 (*info->fprintf_func) (info->stream, "%s", mips_gpr_names[4]);
1807 (*info->fprintf_func) (info->stream, "-%s",
1808 mips_gpr_names[amask + 3]);
1812 smask = (l >> 1) & 3;
1815 (*info->fprintf_func) (info->stream, "%s??",
1816 need_comma ? "," : "");
1821 (*info->fprintf_func) (info->stream, "%s%s",
1822 need_comma ? "," : "",
1823 mips_gpr_names[16]);
1825 (*info->fprintf_func) (info->stream, "-%s",
1826 mips_gpr_names[smask + 15]);
1832 (*info->fprintf_func) (info->stream, "%s%s",
1833 need_comma ? "," : "",
1834 mips_gpr_names[31]);
1838 if (amask == 5 || amask == 6)
1840 (*info->fprintf_func) (info->stream, "%s$f0",
1841 need_comma ? "," : "");
1843 (*info->fprintf_func) (info->stream, "-$f1");
1850 /* MIPS16e save/restore. */
1853 int amask, args, statics;
1862 amask = (l >> 16) & 0xf;
1863 if (amask == MIPS16_ALL_ARGS)
1868 else if (amask == MIPS16_ALL_STATICS)
1876 statics = amask & 3;
1880 (*info->fprintf_func) (info->stream, "%s", mips_gpr_names[4]);
1882 (*info->fprintf_func) (info->stream, "-%s",
1883 mips_gpr_names[4 + args - 1]);
1887 framesz = (((l >> 16) & 0xf0) | (l & 0x0f)) * 8;
1888 if (framesz == 0 && !use_extend)
1891 (*info->fprintf_func) (info->stream, "%s%d",
1892 need_comma ? "," : "",
1895 if (l & 0x40) /* $ra */
1896 (*info->fprintf_func) (info->stream, ",%s", mips_gpr_names[31]);
1898 nsreg = (l >> 24) & 0x7;
1900 if (l & 0x20) /* $s0 */
1902 if (l & 0x10) /* $s1 */
1904 if (nsreg > 0) /* $s2-$s8 */
1905 smask |= ((1 << nsreg) - 1) << 2;
1907 /* Find first set static reg bit. */
1908 for (i = 0; i < 9; i++)
1910 if (smask & (1 << i))
1912 (*info->fprintf_func) (info->stream, ",%s",
1913 mips_gpr_names[i == 8 ? 30 : (16 + i)]);
1914 /* Skip over string of set bits. */
1915 for (j = i; smask & (2 << j); j++)
1918 (*info->fprintf_func) (info->stream, "-%s",
1919 mips_gpr_names[j == 8 ? 30 : (16 + j)]);
1924 /* Statics $ax - $a3. */
1926 (*info->fprintf_func) (info->stream, ",%s", mips_gpr_names[7]);
1927 else if (statics > 0)
1928 (*info->fprintf_func) (info->stream, ",%s-%s",
1929 mips_gpr_names[7 - statics + 1],
1935 /* xgettext:c-format */
1936 (*info->fprintf_func)
1938 _("# internal disassembler error, unrecognised modifier (%c)"),
1944 /* Disassemble mips16 instructions. */
1947 print_insn_mips16 (bfd_vma memaddr, struct disassemble_info *info)
1953 bfd_boolean use_extend;
1955 const struct mips_opcode *op, *opend;
1957 info->bytes_per_chunk = 2;
1958 info->display_endian = info->endian;
1959 info->insn_info_valid = 1;
1960 info->branch_delay_insns = 0;
1961 info->data_size = 0;
1962 info->insn_type = dis_nonbranch;
1966 status = (*info->read_memory_func) (memaddr, buffer, 2, info);
1969 (*info->memory_error_func) (status, memaddr, info);
1975 if (info->endian == BFD_ENDIAN_BIG)
1976 insn = bfd_getb16 (buffer);
1978 insn = bfd_getl16 (buffer);
1980 /* Handle the extend opcode specially. */
1982 if ((insn & 0xf800) == 0xf000)
1985 extend = insn & 0x7ff;
1989 status = (*info->read_memory_func) (memaddr, buffer, 2, info);
1992 (*info->fprintf_func) (info->stream, "extend 0x%x",
1993 (unsigned int) extend);
1994 (*info->memory_error_func) (status, memaddr, info);
1998 if (info->endian == BFD_ENDIAN_BIG)
1999 insn = bfd_getb16 (buffer);
2001 insn = bfd_getl16 (buffer);
2003 /* Check for an extend opcode followed by an extend opcode. */
2004 if ((insn & 0xf800) == 0xf000)
2006 (*info->fprintf_func) (info->stream, "extend 0x%x",
2007 (unsigned int) extend);
2008 info->insn_type = dis_noninsn;
2015 /* FIXME: Should probably use a hash table on the major opcode here. */
2017 opend = mips16_opcodes + bfd_mips16_num_opcodes;
2018 for (op = mips16_opcodes; op < opend; op++)
2020 if (op->pinfo != INSN_MACRO
2021 && !(no_aliases && (op->pinfo2 & INSN2_ALIAS))
2022 && (insn & op->mask) == op->match)
2026 if (strchr (op->args, 'a') != NULL)
2030 (*info->fprintf_func) (info->stream, "extend 0x%x",
2031 (unsigned int) extend);
2032 info->insn_type = dis_noninsn;
2040 status = (*info->read_memory_func) (memaddr, buffer, 2,
2045 if (info->endian == BFD_ENDIAN_BIG)
2046 extend = bfd_getb16 (buffer);
2048 extend = bfd_getl16 (buffer);
2053 (*info->fprintf_func) (info->stream, "%s", op->name);
2054 if (op->args[0] != '\0')
2055 (*info->fprintf_func) (info->stream, "\t");
2057 for (s = op->args; *s != '\0'; s++)
2061 && (((insn >> MIPS16OP_SH_RX) & MIPS16OP_MASK_RX)
2062 == ((insn >> MIPS16OP_SH_RY) & MIPS16OP_MASK_RY)))
2064 /* Skip the register and the comma. */
2070 && (((insn >> MIPS16OP_SH_RZ) & MIPS16OP_MASK_RZ)
2071 == ((insn >> MIPS16OP_SH_RX) & MIPS16OP_MASK_RX)))
2073 /* Skip the register and the comma. */
2077 print_mips16_insn_arg (*s, op, insn, use_extend, extend, memaddr,
2081 /* Figure out branch instruction type and delay slot information. */
2082 if ((op->pinfo & INSN_UNCOND_BRANCH_DELAY) != 0)
2083 info->branch_delay_insns = 1;
2084 if ((op->pinfo & (INSN_UNCOND_BRANCH_DELAY
2085 | MIPS16_INSN_UNCOND_BRANCH)) != 0)
2087 if ((op->pinfo & INSN_WRITE_GPR_31) != 0)
2088 info->insn_type = dis_jsr;
2090 info->insn_type = dis_branch;
2092 else if ((op->pinfo & MIPS16_INSN_COND_BRANCH) != 0)
2093 info->insn_type = dis_condbranch;
2100 (*info->fprintf_func) (info->stream, "0x%x", extend | 0xf000);
2101 (*info->fprintf_func) (info->stream, "0x%x", insn);
2102 info->insn_type = dis_noninsn;
2107 /* In an environment where we do not know the symbol type of the
2108 instruction we are forced to assume that the low order bit of the
2109 instructions' address may mark it as a mips16 instruction. If we
2110 are single stepping, or the pc is within the disassembled function,
2111 this works. Otherwise, we need a clue. Sometimes. */
2114 _print_insn_mips (bfd_vma memaddr,
2115 struct disassemble_info *info,
2116 enum bfd_endian endianness)
2118 bfd_byte buffer[INSNLEN];
2121 set_default_mips_dis_options (info);
2122 parse_mips_dis_options (info->disassembler_options);
2125 /* FIXME: If odd address, this is CLEARLY a mips 16 instruction. */
2126 /* Only a few tools will work this way. */
2128 return print_insn_mips16 (memaddr, info);
2131 #if SYMTAB_AVAILABLE
2132 if (info->mach == bfd_mach_mips16
2133 || (info->symbols != NULL
2134 && bfd_asymbol_flavour (*info->symbols) == bfd_target_elf_flavour
2135 && ELF_ST_IS_MIPS16 ((*(elf_symbol_type **) info->symbols)
2136 ->internal_elf_sym.st_other)))
2137 return print_insn_mips16 (memaddr, info);
2140 status = (*info->read_memory_func) (memaddr, buffer, INSNLEN, info);
2145 if (endianness == BFD_ENDIAN_BIG)
2146 insn = (unsigned long) bfd_getb32 (buffer);
2148 insn = (unsigned long) bfd_getl32 (buffer);
2150 return print_insn_mips (memaddr, insn, info);
2154 (*info->memory_error_func) (status, memaddr, info);
2160 print_insn_big_mips (bfd_vma memaddr, struct disassemble_info *info)
2162 return _print_insn_mips (memaddr, info, BFD_ENDIAN_BIG);
2166 print_insn_little_mips (bfd_vma memaddr, struct disassemble_info *info)
2168 return _print_insn_mips (memaddr, info, BFD_ENDIAN_LITTLE);
2172 print_mips_disassembler_options (FILE *stream)
2176 fprintf (stream, _("\n\
2177 The following MIPS specific disassembler options are supported for use\n\
2178 with the -M switch (multiple options should be separated by commas):\n"));
2180 fprintf (stream, _("\n\
2181 gpr-names=ABI Print GPR names according to specified ABI.\n\
2182 Default: based on binary being disassembled.\n"));
2184 fprintf (stream, _("\n\
2185 fpr-names=ABI Print FPR names according to specified ABI.\n\
2186 Default: numeric.\n"));
2188 fprintf (stream, _("\n\
2189 cp0-names=ARCH Print CP0 register names according to\n\
2190 specified architecture.\n\
2191 Default: based on binary being disassembled.\n"));
2193 fprintf (stream, _("\n\
2194 hwr-names=ARCH Print HWR names according to specified \n\
2196 Default: based on binary being disassembled.\n"));
2198 fprintf (stream, _("\n\
2199 reg-names=ABI Print GPR and FPR names according to\n\
2200 specified ABI.\n"));
2202 fprintf (stream, _("\n\
2203 reg-names=ARCH Print CP0 register and HWR names according to\n\
2204 specified architecture.\n"));
2206 fprintf (stream, _("\n\
2207 For the options above, the following values are supported for \"ABI\":\n\
2209 for (i = 0; i < ARRAY_SIZE (mips_abi_choices); i++)
2210 fprintf (stream, " %s", mips_abi_choices[i].name);
2211 fprintf (stream, _("\n"));
2213 fprintf (stream, _("\n\
2214 For the options above, The following values are supported for \"ARCH\":\n\
2216 for (i = 0; i < ARRAY_SIZE (mips_arch_choices); i++)
2217 if (*mips_arch_choices[i].name != '\0')
2218 fprintf (stream, " %s", mips_arch_choices[i].name);
2219 fprintf (stream, _("\n"));
2221 fprintf (stream, _("\n"));