1 /* Disassembler interface for targets using CGEN. -*- C -*-
2 CGEN: Cpu tools GENerator
4 THIS FILE IS MACHINE GENERATED WITH CGEN.
5 - the resultant file is machine generated, cgen-dis.in isn't
7 Copyright (C) 1996-2017 Free Software Foundation, Inc.
9 This file is part of libopcodes.
11 This library is free software; you can redistribute it and/or modify
12 it under the terms of the GNU General Public License as published by
13 the Free Software Foundation; either version 3, or (at your option)
16 It is distributed in the hope that it will be useful, but WITHOUT
17 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
18 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
19 License for more details.
21 You should have received a copy of the GNU General Public License
22 along with this program; if not, write to the Free Software Foundation, Inc.,
23 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */
25 /* ??? Eventually more and more of this stuff can go to cpu-independent files.
34 #include "libiberty.h"
39 /* Default text to print if an instruction isn't recognized. */
40 #define UNKNOWN_INSN_MSG _("*unknown*")
42 static void print_normal
43 (CGEN_CPU_DESC, void *, long, unsigned int, bfd_vma, int);
44 static void print_address
45 (CGEN_CPU_DESC, void *, bfd_vma, unsigned int, bfd_vma, int) ATTRIBUTE_UNUSED;
46 static void print_keyword
47 (CGEN_CPU_DESC, void *, CGEN_KEYWORD *, long, unsigned int) ATTRIBUTE_UNUSED;
48 static void print_insn_normal
49 (CGEN_CPU_DESC, void *, const CGEN_INSN *, CGEN_FIELDS *, bfd_vma, int);
51 (CGEN_CPU_DESC, bfd_vma, disassemble_info *, bfd_byte *, unsigned);
52 static int default_print_insn
53 (CGEN_CPU_DESC, bfd_vma, disassemble_info *) ATTRIBUTE_UNUSED;
55 (CGEN_CPU_DESC, bfd_vma, disassemble_info *, bfd_byte *, int, CGEN_EXTRACT_INFO *,
58 /* -- disassembler routines inserted here. */
65 #define CGEN_VALIDATE_INSN_SUPPORTED
67 static void print_tpreg (CGEN_CPU_DESC, PTR, CGEN_KEYWORD *, long, unsigned int);
68 static void print_spreg (CGEN_CPU_DESC, PTR, CGEN_KEYWORD *, long, unsigned int);
71 print_tpreg (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED, PTR dis_info,
72 CGEN_KEYWORD *table ATTRIBUTE_UNUSED, long val ATTRIBUTE_UNUSED,
73 unsigned int flags ATTRIBUTE_UNUSED)
75 disassemble_info *info = (disassemble_info *) dis_info;
77 (*info->fprintf_func) (info->stream, "$tp");
81 print_spreg (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED, PTR dis_info,
82 CGEN_KEYWORD *table ATTRIBUTE_UNUSED, long val ATTRIBUTE_UNUSED,
83 unsigned int flags ATTRIBUTE_UNUSED)
85 disassemble_info *info = (disassemble_info *) dis_info;
87 (*info->fprintf_func) (info->stream, "$sp");
90 /* begin-cop-ip-print-handlers */
92 print_ivc2_cr (CGEN_CPU_DESC,
96 unsigned int) ATTRIBUTE_UNUSED;
98 print_ivc2_cr (CGEN_CPU_DESC cd,
100 CGEN_KEYWORD *keyword_table ATTRIBUTE_UNUSED,
104 print_keyword (cd, dis_info, & mep_cgen_opval_h_cr_ivc2, value, attrs);
107 print_ivc2_ccr (CGEN_CPU_DESC,
111 unsigned int) ATTRIBUTE_UNUSED;
113 print_ivc2_ccr (CGEN_CPU_DESC cd,
115 CGEN_KEYWORD *keyword_table ATTRIBUTE_UNUSED,
119 print_keyword (cd, dis_info, & mep_cgen_opval_h_ccr_ivc2, value, attrs);
121 /* end-cop-ip-print-handlers */
123 /************************************************************\
124 *********************** Experimental *************************
125 \************************************************************/
127 #undef CGEN_PRINT_INSN
128 #define CGEN_PRINT_INSN mep_print_insn
131 mep_print_vliw_insns (CGEN_CPU_DESC cd, bfd_vma pc, disassemble_info *info,
132 bfd_byte *buf, int corelength, int copro1length,
133 int copro2length ATTRIBUTE_UNUSED)
137 /* char insnbuf[CGEN_MAX_INSN_SIZE]; */
138 bfd_byte insnbuf[64];
140 /* If corelength > 0 then there is a core insn present. It
141 will be at the beginning of the buffer. After printing
142 the core insn, we need to print the + on the next line. */
147 for (i = 0; i < corelength; i++ )
149 cd->isas = & MEP_CORE_ISA;
151 my_status = print_insn (cd, pc, info, insnbuf, corelength);
152 if (my_status != corelength)
154 (*info->fprintf_func) (info->stream, UNKNOWN_INSN_MSG);
155 my_status = corelength;
159 /* Print the + to indicate that the following copro insn is */
160 /* part of a vliw group. */
161 if (copro1length > 0)
162 (*info->fprintf_func) (info->stream, " + ");
165 /* Now all that is left to be processed is the coprocessor insns
166 In vliw mode, there will always be one. Its positioning will
167 be from byte corelength to byte corelength+copro1length -1.
168 No need to check for existence. Also, the first vliw insn,
169 will, as spec'd, always be at least as long as the core insn
170 so we don't need to flush the buffer. */
171 if (copro1length > 0)
175 for (i = corelength; i < corelength + copro1length; i++ )
176 insnbuf[i - corelength] = buf[i];
178 switch (copro1length)
183 cd->isas = & MEP_COP16_ISA;
186 cd->isas = & MEP_COP32_ISA;
189 cd->isas = & MEP_COP48_ISA;
192 cd->isas = & MEP_COP64_ISA;
195 /* Shouldn't be anything but 16,32,48,64. */
199 my_status = print_insn (cd, pc, info, insnbuf, copro1length);
201 if (my_status != copro1length)
203 (*info->fprintf_func) (info->stream, UNKNOWN_INSN_MSG);
204 my_status = copro1length;
210 /* Now we need to process the second copro insn if it exists. We
211 have no guarantee that the second copro insn will be longer
212 than the first, so we have to flush the buffer if we are have
213 a second copro insn to process. If present, this insn will
214 be in the position from byte corelength+copro1length to byte
215 corelength+copro1length+copro2length-1 (which better equal 8
216 or else we're in big trouble. */
217 if (copro2length > 0)
221 for (i = 0; i < 64 ; i++)
224 for (i = corelength + copro1length; i < 64; i++)
225 insnbuf[i - (corelength + copro1length)] = buf[i];
227 switch (copro2length)
230 cd->isas = 1 << ISA_EXT_COP1_16;
233 cd->isas = 1 << ISA_EXT_COP1_32;
236 cd->isas = 1 << ISA_EXT_COP1_48;
239 cd->isas = 1 << ISA_EXT_COP1_64;
242 /* Shouldn't be anything but 16,32,48,64. */
246 my_status = print_insn (cd, pc, info, insnbuf, copro2length);
248 if (my_status != copro2length)
250 (*info->fprintf_func) (info->stream, UNKNOWN_INSN_MSG);
251 my_status = copro2length;
258 /* Status should now be the number of bytes that were printed
259 which should be 4 for VLIW32 mode and 64 for VLIW64 mode. */
261 if ((!MEP_VLIW64 && (status != 4)) || (MEP_VLIW64 && (status != 8)))
267 /* The two functions mep_examine_vliw[32,64]_insns are used find out
268 which vliw combinaion (16 bit core with 48 bit copro, 32 bit core
269 with 32 bit copro, etc.) is present. Later on, when internally
270 parallel coprocessors are handled, only these functions should
273 At this time only the following combinations are supported:
276 16 bit core insn (core) and 16 bit coprocessor insn (cop1)
277 32 bit core insn (core)
278 32 bit coprocessor insn (cop1)
279 Note: As of this time, I do not believe we have enough information
280 to distinguish a 32 bit core insn from a 32 bit cop insn. Also,
281 no 16 bit coprocessor insns have been specified.
284 16 bit core insn (core) and 48 bit coprocessor insn (cop1)
285 32 bit core insn (core) and 32 bit coprocessor insn (cop1)
286 64 bit coprocessor insn (cop1)
288 The framework for an internally parallel coprocessor is also
289 present (2nd coprocessor insn is cop2), but at this time it
290 is not used. This only appears to be valid in VLIW64 mode. */
293 mep_examine_vliw32_insns (CGEN_CPU_DESC cd, bfd_vma pc, disassemble_info *info)
300 bfd_byte buf[CGEN_MAX_INSN_SIZE];
302 char indicatorcop32[2];
304 /* At this time we're not supporting internally parallel coprocessors,
305 so cop2buflength will always be 0. */
308 /* Read in 32 bits. */
309 buflength = 4; /* VLIW insn spans 4 bytes. */
310 status = (*info->read_memory_func) (pc, buf, buflength, info);
314 (*info->memory_error_func) (status, pc, info);
318 /* Put the big endian representation of the bytes to be examined
319 in the temporary buffers for examination. */
321 if (info->endian == BFD_ENDIAN_BIG)
323 indicator16[0] = buf[0];
324 indicatorcop32[0] = buf[0];
325 indicatorcop32[1] = buf[1];
329 indicator16[0] = buf[1];
330 indicatorcop32[0] = buf[1];
331 indicatorcop32[1] = buf[0];
334 /* If the two high order bits are 00, 01 or 10, we have a 16 bit
335 core insn and a 48 bit copro insn. */
337 if ((indicator16[0] & 0x80) && (indicator16[0] & 0x40))
339 if ((indicatorcop32[0] & 0xf0) == 0xf0 && (indicatorcop32[1] & 0x07) == 0x07)
341 /* We have a 32 bit copro insn. */
343 /* All 4 4ytes are one copro insn. */
348 /* We have a 32 bit core. */
355 /* We have a 16 bit core insn and a 16 bit copro insn. */
360 /* Now we have the distrubution set. Print them out. */
361 status = mep_print_vliw_insns (cd, pc, info, buf, corebuflength,
362 cop1buflength, cop2buflength);
368 mep_examine_vliw64_insns (CGEN_CPU_DESC cd, bfd_vma pc, disassemble_info *info)
375 bfd_byte buf[CGEN_MAX_INSN_SIZE];
379 /* At this time we're not supporting internally parallel
380 coprocessors, so cop2buflength will always be 0. */
383 /* Read in 64 bits. */
384 buflength = 8; /* VLIW insn spans 8 bytes. */
385 status = (*info->read_memory_func) (pc, buf, buflength, info);
389 (*info->memory_error_func) (status, pc, info);
393 /* We have all 64 bits in the buffer now. We have to figure out
394 what combination of instruction sizes are present. The two
395 high order bits will indicate whether or not we have a 16 bit
396 core insn or not. If not, then we have to look at the 7,8th
397 bytes to tell whether we have 64 bit copro insn or a 32 bit
398 core insn with a 32 bit copro insn. Endianness will make a
401 /* Put the big endian representation of the bytes to be examined
402 in the temporary buffers for examination. */
404 /* indicator16[0] = buf[0]; */
405 if (info->endian == BFD_ENDIAN_BIG)
407 indicator16[0] = buf[0];
408 indicator64[0] = buf[0];
409 indicator64[1] = buf[1];
410 indicator64[2] = buf[2];
411 indicator64[3] = buf[3];
415 indicator16[0] = buf[1];
416 indicator64[0] = buf[1];
417 indicator64[1] = buf[0];
418 indicator64[2] = buf[3];
419 indicator64[3] = buf[2];
422 /* If the two high order bits are 00, 01 or 10, we have a 16 bit
423 core insn and a 48 bit copro insn. */
425 if ((indicator16[0] & 0x80) && (indicator16[0] & 0x40))
427 if ((indicator64[0] & 0xf0) == 0xf0 && (indicator64[1] & 0x07) == 0x07
428 && ((indicator64[2] & 0xfe) != 0xf0 || (indicator64[3] & 0xf4) != 0))
430 /* We have a 64 bit copro insn. */
432 /* All 8 bytes are one copro insn. */
437 /* We have a 32 bit core insn and a 32 bit copro insn. */
444 /* We have a 16 bit core insn and a 48 bit copro insn. */
449 /* Now we have the distrubution set. Print them out. */
450 status = mep_print_vliw_insns (cd, pc, info, buf, corebuflength,
451 cop1buflength, cop2buflength);
456 #ifdef MEP_IVC2_SUPPORTED
459 print_slot_insn (CGEN_CPU_DESC cd,
461 disassemble_info *info,
465 const CGEN_INSN_LIST *insn_list;
466 CGEN_INSN_INT insn_value;
467 CGEN_EXTRACT_INFO ex_info;
469 insn_value = cgen_get_insn_value (cd, buf, 32);
471 /* Fill in ex_info fields like read_insn would. Don't actually call
472 read_insn, since the incoming buffer is already read (and possibly
473 modified a la m32r). */
474 ex_info.valid = (1 << 8) - 1;
475 ex_info.dis_info = info;
476 ex_info.insn_bytes = buf;
478 /* The instructions are stored in hash lists.
479 Pick the first one and keep trying until we find the right one. */
481 insn_list = CGEN_DIS_LOOKUP_INSN (cd, (char *) buf, insn_value);
482 while (insn_list != NULL)
484 const CGEN_INSN *insn = insn_list->insn;
488 if ((CGEN_INSN_ATTR_VALUE (insn, CGEN_INSN_CONFIG)
489 && CGEN_INSN_ATTR_VALUE (insn, CGEN_INSN_CONFIG) != MEP_CONFIG)
490 || ! (CGEN_ATTR_CGEN_INSN_SLOTS_VALUE (CGEN_INSN_ATTRS (insn)) & (1 << slot)))
492 insn_list = CGEN_DIS_NEXT_INSN (insn_list);
496 if ((insn_value & CGEN_INSN_BASE_MASK (insn))
497 == CGEN_INSN_BASE_VALUE (insn))
499 /* Printing is handled in two passes. The first pass parses the
500 machine insn and extracts the fields. The second pass prints
503 length = CGEN_EXTRACT_FN (cd, insn)
504 (cd, insn, &ex_info, insn_value, &fields, pc);
506 /* Length < 0 -> error. */
511 CGEN_PRINT_FN (cd, insn) (cd, info, insn, &fields, pc, length);
512 /* Length is in bits, result is in bytes. */
517 insn_list = CGEN_DIS_NEXT_INSN (insn_list);
520 if (slot == SLOTS_P0S)
521 (*info->fprintf_func) (info->stream, "*unknown-p0s*");
522 else if (slot == SLOTS_P0)
523 (*info->fprintf_func) (info->stream, "*unknown-p0*");
524 else if (slot == SLOTS_P1)
525 (*info->fprintf_func) (info->stream, "*unknown-p1*");
526 else if (slot == SLOTS_C3)
527 (*info->fprintf_func) (info->stream, "*unknown-c3*");
532 mep_examine_ivc2_insns (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED, bfd_vma pc ATTRIBUTE_UNUSED, disassemble_info *info ATTRIBUTE_UNUSED)
540 /* Read in 64 bits. */
541 buflength = 8; /* VLIW insn spans 8 bytes. */
542 status = (*info->read_memory_func) (pc, buf, buflength, info);
546 (*info->memory_error_func) (status, pc, info);
550 if (info->endian == BFD_ENDIAN_LITTLE)
555 if (((unsigned char)buf[0^e] & 0xf0) < 0xc0)
557 /* <--00--><--11--><--22--><--33--><--44--><--55--><--66--><--77--> */
558 /* V1 [-----core-----][--------p0s-------][------------p1------------] */
560 print_insn (cd, pc, info, buf, 2);
563 insn[1^e] = buf[2^e];
564 insn[2^e] = buf[3^e];
565 insn[3^e] = buf[4^e] & 0xf0;
566 (*info->fprintf_func) (info->stream, " + ");
567 print_slot_insn (cd, pc, info, SLOTS_P0S, insn);
569 insn[0^e] = buf[4^e] << 4 | buf[5^e] >> 4;
570 insn[1^e] = buf[5^e] << 4 | buf[6^e] >> 4;
571 insn[2^e] = buf[6^e] << 4 | buf[7^e] >> 4;
572 insn[3^e] = buf[7^e] << 4;
573 (*info->fprintf_func) (info->stream, " + ");
574 print_slot_insn (cd, pc, info, SLOTS_P1, insn);
576 else if ((buf[0^e] & 0xf0) == 0xf0 && (buf[1^e] & 0x0f) == 0x07)
578 /* <--00--><--11--><--22--><--33--><--44--><--55--><--66--><--77--> */
579 /* V3 1111[--p0--]0111[--------p0--------][------------p1------------] */
580 /* 00000000111111112222222233333333 */
582 insn[0^e] = buf[0^e] << 4 | buf[1^e] >> 4;
583 insn[1^e] = buf[2^e];
584 insn[2^e] = buf[3^e];
585 insn[3^e] = buf[4^e] & 0xf0;
586 print_slot_insn (cd, pc, info, SLOTS_P0, insn);
588 insn[0^e] = buf[4^e] << 4 | buf[5^e] >> 4;
589 insn[1^e] = buf[5^e] << 4 | buf[6^e] >> 4;
590 insn[2^e] = buf[6^e] << 4 | buf[7^e] >> 4;
591 insn[3^e] = buf[7^e] << 4;
592 (*info->fprintf_func) (info->stream, " + ");
593 print_slot_insn (cd, pc, info, SLOTS_P1, insn);
597 /* <--00--><--11--><--22--><--33--><--44--><--55--><--66--><--77--> */
598 /* V2 [-------------core-------------]xxxx[------------p1------------] */
599 print_insn (cd, pc, info, buf, 4);
601 insn[0^e] = buf[4^e] << 4 | buf[5^e] >> 4;
602 insn[1^e] = buf[5^e] << 4 | buf[6^e] >> 4;
603 insn[2^e] = buf[6^e] << 4 | buf[7^e] >> 4;
604 insn[3^e] = buf[7^e] << 4;
605 (*info->fprintf_func) (info->stream, " + ");
606 print_slot_insn (cd, pc, info, SLOTS_P1, insn);
612 #endif /* MEP_IVC2_SUPPORTED */
614 /* This is a hack. SID calls this to update the disassembler as the
615 CPU changes modes. */
616 static int mep_ivc2_disassemble_p = 0;
617 static int mep_ivc2_vliw_disassemble_p = 0;
620 mep_print_insn_set_ivc2_mode (int ivc2_p, int vliw_p, int cfg_idx);
622 mep_print_insn_set_ivc2_mode (int ivc2_p, int vliw_p, int cfg_idx)
624 mep_ivc2_disassemble_p = ivc2_p;
625 mep_ivc2_vliw_disassemble_p = vliw_p;
626 mep_config_index = cfg_idx;
630 mep_print_insn (CGEN_CPU_DESC cd, bfd_vma pc, disassemble_info *info)
635 static CGEN_ATTR_VALUE_BITSET_TYPE *ivc2_core_isa = NULL;
637 if (ivc2_core_isa == NULL)
639 /* IVC2 has some core-only coprocessor instructions. We
640 use COP32 to flag those, and COP64 for the VLIW ones,
641 since they have the same names. */
642 ivc2_core_isa = cgen_bitset_create (MAX_ISAS);
645 /* Extract and adapt to configuration number, if available. */
646 if (info->section && info->section->owner)
648 bfd *abfd = info->section->owner;
649 mep_config_index = abfd->tdata.elf_obj_data->elf_header->e_flags & EF_MEP_INDEX_MASK;
650 /* This instantly redefines MEP_CONFIG, MEP_OMASK, .... MEP_VLIW64 */
652 cop_type = abfd->tdata.elf_obj_data->elf_header->e_flags & EF_MEP_COP_MASK;
653 if (cop_type == EF_MEP_COP_IVC2)
657 /* Picking the right ISA bitmask for the current context is tricky. */
660 if (info->section->flags & SEC_MEP_VLIW)
662 #ifdef MEP_IVC2_SUPPORTED
665 /* ivc2 has its own way of selecting its functions. */
666 cd->isas = & MEP_CORE_ISA;
667 status = mep_examine_ivc2_insns (cd, pc, info);
671 /* Are we in 32 or 64 bit vliw mode? */
673 status = mep_examine_vliw64_insns (cd, pc, info);
675 status = mep_examine_vliw32_insns (cd, pc, info);
676 /* Both the above branches set their own isa bitmasks. */
682 cgen_bitset_clear (ivc2_core_isa);
683 cgen_bitset_union (ivc2_core_isa, &MEP_CORE_ISA, ivc2_core_isa);
684 cgen_bitset_union (ivc2_core_isa, &MEP_COP32_ISA, ivc2_core_isa);
685 cd->isas = ivc2_core_isa;
688 cd->isas = & MEP_CORE_ISA;
689 status = default_print_insn (cd, pc, info);
692 else /* sid or gdb */
694 #ifdef MEP_IVC2_SUPPORTED
695 if (mep_ivc2_disassemble_p)
697 if (mep_ivc2_vliw_disassemble_p)
699 cd->isas = & MEP_CORE_ISA;
700 status = mep_examine_ivc2_insns (cd, pc, info);
706 cd->isas = ivc2_core_isa;
711 status = default_print_insn (cd, pc, info);
720 void mep_cgen_print_operand
721 (CGEN_CPU_DESC, int, PTR, CGEN_FIELDS *, void const *, bfd_vma, int);
723 /* Main entry point for printing operands.
724 XINFO is a `void *' and not a `disassemble_info *' to not put a requirement
725 of dis-asm.h on cgen.h.
727 This function is basically just a big switch statement. Earlier versions
728 used tables to look up the function to use, but
729 - if the table contains both assembler and disassembler functions then
730 the disassembler contains much of the assembler and vice-versa,
731 - there's a lot of inlining possibilities as things grow,
732 - using a switch statement avoids the function call overhead.
734 This function could be moved into `print_insn_normal', but keeping it
735 separate makes clear the interface between `print_insn_normal' and each of
739 mep_cgen_print_operand (CGEN_CPU_DESC cd,
743 void const *attrs ATTRIBUTE_UNUSED,
747 disassemble_info *info = (disassemble_info *) xinfo;
751 case MEP_OPERAND_ADDR24A4 :
752 print_normal (cd, info, fields->f_24u8a4n, 0|(1<<CGEN_OPERAND_VIRTUAL), pc, length);
754 case MEP_OPERAND_C5RMUIMM20 :
755 print_normal (cd, info, fields->f_c5_rmuimm20, 0|(1<<CGEN_OPERAND_VIRTUAL), pc, length);
757 case MEP_OPERAND_C5RNMUIMM24 :
758 print_normal (cd, info, fields->f_c5_rnmuimm24, 0|(1<<CGEN_OPERAND_VIRTUAL), pc, length);
760 case MEP_OPERAND_CALLNUM :
761 print_normal (cd, info, fields->f_callnum, 0|(1<<CGEN_OPERAND_VIRTUAL), pc, length);
763 case MEP_OPERAND_CCCC :
764 print_normal (cd, info, fields->f_rm, 0, pc, length);
766 case MEP_OPERAND_CCRN :
767 print_keyword (cd, info, & mep_cgen_opval_h_ccr, fields->f_ccrn, 0|(1<<CGEN_OPERAND_VIRTUAL));
769 case MEP_OPERAND_CDISP10 :
770 print_normal (cd, info, fields->f_cdisp10, 0|(1<<CGEN_OPERAND_SIGNED), pc, length);
772 case MEP_OPERAND_CDISP10A2 :
773 print_normal (cd, info, fields->f_cdisp10, 0|(1<<CGEN_OPERAND_SIGNED), pc, length);
775 case MEP_OPERAND_CDISP10A4 :
776 print_normal (cd, info, fields->f_cdisp10, 0|(1<<CGEN_OPERAND_SIGNED), pc, length);
778 case MEP_OPERAND_CDISP10A8 :
779 print_normal (cd, info, fields->f_cdisp10, 0|(1<<CGEN_OPERAND_SIGNED), pc, length);
781 case MEP_OPERAND_CDISP12 :
782 print_normal (cd, info, fields->f_12s20, 0|(1<<CGEN_OPERAND_SIGNED), pc, length);
784 case MEP_OPERAND_CIMM4 :
785 print_normal (cd, info, fields->f_rn, 0, pc, length);
787 case MEP_OPERAND_CIMM5 :
788 print_normal (cd, info, fields->f_5u24, 0, pc, length);
790 case MEP_OPERAND_CODE16 :
791 print_normal (cd, info, fields->f_16u16, 0, pc, length);
793 case MEP_OPERAND_CODE24 :
794 print_normal (cd, info, fields->f_24u4n, 0|(1<<CGEN_OPERAND_VIRTUAL), pc, length);
796 case MEP_OPERAND_CP_FLAG :
797 print_keyword (cd, info, & mep_cgen_opval_h_ccr, 0, 0);
799 case MEP_OPERAND_CRN :
800 print_keyword (cd, info, & mep_cgen_opval_h_cr, fields->f_crn, 0);
802 case MEP_OPERAND_CRN64 :
803 print_keyword (cd, info, & mep_cgen_opval_h_cr64, fields->f_crn, 0);
805 case MEP_OPERAND_CRNX :
806 print_keyword (cd, info, & mep_cgen_opval_h_cr, fields->f_crnx, 0|(1<<CGEN_OPERAND_VIRTUAL));
808 case MEP_OPERAND_CRNX64 :
809 print_keyword (cd, info, & mep_cgen_opval_h_cr64, fields->f_crnx, 0|(1<<CGEN_OPERAND_VIRTUAL));
811 case MEP_OPERAND_CROC :
812 print_keyword (cd, info, & mep_cgen_opval_h_cr64, fields->f_ivc2_5u7, 0);
814 case MEP_OPERAND_CROP :
815 print_keyword (cd, info, & mep_cgen_opval_h_cr64, fields->f_ivc2_5u23, 0);
817 case MEP_OPERAND_CRPC :
818 print_keyword (cd, info, & mep_cgen_opval_h_cr64, fields->f_ivc2_5u26, 0);
820 case MEP_OPERAND_CRPP :
821 print_keyword (cd, info, & mep_cgen_opval_h_cr64, fields->f_ivc2_5u18, 0);
823 case MEP_OPERAND_CRQC :
824 print_keyword (cd, info, & mep_cgen_opval_h_cr64, fields->f_ivc2_5u21, 0);
826 case MEP_OPERAND_CRQP :
827 print_keyword (cd, info, & mep_cgen_opval_h_cr64, fields->f_ivc2_5u13, 0);
829 case MEP_OPERAND_CSRN :
830 print_keyword (cd, info, & mep_cgen_opval_h_csr, fields->f_csrn, 0|(1<<CGEN_OPERAND_VIRTUAL));
832 case MEP_OPERAND_CSRN_IDX :
833 print_normal (cd, info, fields->f_csrn, 0|(1<<CGEN_OPERAND_VIRTUAL), pc, length);
835 case MEP_OPERAND_DBG :
836 print_keyword (cd, info, & mep_cgen_opval_h_csr, 0, 0);
838 case MEP_OPERAND_DEPC :
839 print_keyword (cd, info, & mep_cgen_opval_h_csr, 0, 0);
841 case MEP_OPERAND_EPC :
842 print_keyword (cd, info, & mep_cgen_opval_h_csr, 0, 0);
844 case MEP_OPERAND_EXC :
845 print_keyword (cd, info, & mep_cgen_opval_h_csr, 0, 0);
847 case MEP_OPERAND_HI :
848 print_keyword (cd, info, & mep_cgen_opval_h_csr, 0, 0);
850 case MEP_OPERAND_IMM16P0 :
851 print_normal (cd, info, fields->f_ivc2_imm16p0, 0|(1<<CGEN_OPERAND_VIRTUAL), pc, length);
853 case MEP_OPERAND_IMM3P12 :
854 print_normal (cd, info, fields->f_ivc2_3u12, 0, pc, length);
856 case MEP_OPERAND_IMM3P25 :
857 print_normal (cd, info, fields->f_ivc2_3u25, 0, pc, length);
859 case MEP_OPERAND_IMM3P4 :
860 print_normal (cd, info, fields->f_ivc2_3u4, 0, pc, length);
862 case MEP_OPERAND_IMM3P5 :
863 print_normal (cd, info, fields->f_ivc2_3u5, 0, pc, length);
865 case MEP_OPERAND_IMM3P9 :
866 print_normal (cd, info, fields->f_ivc2_3u9, 0, pc, length);
868 case MEP_OPERAND_IMM4P10 :
869 print_normal (cd, info, fields->f_ivc2_4u10, 0, pc, length);
871 case MEP_OPERAND_IMM4P4 :
872 print_normal (cd, info, fields->f_ivc2_4u4, 0, pc, length);
874 case MEP_OPERAND_IMM4P8 :
875 print_normal (cd, info, fields->f_ivc2_4u8, 0, pc, length);
877 case MEP_OPERAND_IMM5P23 :
878 print_normal (cd, info, fields->f_ivc2_5u23, 0, pc, length);
880 case MEP_OPERAND_IMM5P3 :
881 print_normal (cd, info, fields->f_ivc2_5u3, 0, pc, length);
883 case MEP_OPERAND_IMM5P7 :
884 print_normal (cd, info, fields->f_ivc2_5u7, 0, pc, length);
886 case MEP_OPERAND_IMM5P8 :
887 print_normal (cd, info, fields->f_ivc2_5u8, 0, pc, length);
889 case MEP_OPERAND_IMM6P2 :
890 print_normal (cd, info, fields->f_ivc2_6u2, 0, pc, length);
892 case MEP_OPERAND_IMM6P6 :
893 print_normal (cd, info, fields->f_ivc2_6u6, 0, pc, length);
895 case MEP_OPERAND_IMM8P0 :
896 print_normal (cd, info, fields->f_ivc2_8u0, 0, pc, length);
898 case MEP_OPERAND_IMM8P20 :
899 print_normal (cd, info, fields->f_ivc2_8u20, 0, pc, length);
901 case MEP_OPERAND_IMM8P4 :
902 print_normal (cd, info, fields->f_ivc2_8u4, 0, pc, length);
904 case MEP_OPERAND_IVC_X_0_2 :
905 print_normal (cd, info, fields->f_ivc2_2u0, 0, pc, length);
907 case MEP_OPERAND_IVC_X_0_3 :
908 print_normal (cd, info, fields->f_ivc2_3u0, 0, pc, length);
910 case MEP_OPERAND_IVC_X_0_4 :
911 print_normal (cd, info, fields->f_ivc2_4u0, 0, pc, length);
913 case MEP_OPERAND_IVC_X_0_5 :
914 print_normal (cd, info, fields->f_ivc2_5u0, 0, pc, length);
916 case MEP_OPERAND_IVC_X_6_1 :
917 print_normal (cd, info, fields->f_ivc2_1u6, 0, pc, length);
919 case MEP_OPERAND_IVC_X_6_2 :
920 print_normal (cd, info, fields->f_ivc2_2u6, 0, pc, length);
922 case MEP_OPERAND_IVC_X_6_3 :
923 print_normal (cd, info, fields->f_ivc2_3u6, 0, pc, length);
925 case MEP_OPERAND_IVC2_ACC0_0 :
926 print_keyword (cd, info, & mep_cgen_opval_h_ccr_ivc2, 0, 0);
928 case MEP_OPERAND_IVC2_ACC0_1 :
929 print_keyword (cd, info, & mep_cgen_opval_h_ccr_ivc2, 0, 0);
931 case MEP_OPERAND_IVC2_ACC0_2 :
932 print_keyword (cd, info, & mep_cgen_opval_h_ccr_ivc2, 0, 0);
934 case MEP_OPERAND_IVC2_ACC0_3 :
935 print_keyword (cd, info, & mep_cgen_opval_h_ccr_ivc2, 0, 0);
937 case MEP_OPERAND_IVC2_ACC0_4 :
938 print_keyword (cd, info, & mep_cgen_opval_h_ccr_ivc2, 0, 0);
940 case MEP_OPERAND_IVC2_ACC0_5 :
941 print_keyword (cd, info, & mep_cgen_opval_h_ccr_ivc2, 0, 0);
943 case MEP_OPERAND_IVC2_ACC0_6 :
944 print_keyword (cd, info, & mep_cgen_opval_h_ccr_ivc2, 0, 0);
946 case MEP_OPERAND_IVC2_ACC0_7 :
947 print_keyword (cd, info, & mep_cgen_opval_h_ccr_ivc2, 0, 0);
949 case MEP_OPERAND_IVC2_ACC1_0 :
950 print_keyword (cd, info, & mep_cgen_opval_h_ccr_ivc2, 0, 0);
952 case MEP_OPERAND_IVC2_ACC1_1 :
953 print_keyword (cd, info, & mep_cgen_opval_h_ccr_ivc2, 0, 0);
955 case MEP_OPERAND_IVC2_ACC1_2 :
956 print_keyword (cd, info, & mep_cgen_opval_h_ccr_ivc2, 0, 0);
958 case MEP_OPERAND_IVC2_ACC1_3 :
959 print_keyword (cd, info, & mep_cgen_opval_h_ccr_ivc2, 0, 0);
961 case MEP_OPERAND_IVC2_ACC1_4 :
962 print_keyword (cd, info, & mep_cgen_opval_h_ccr_ivc2, 0, 0);
964 case MEP_OPERAND_IVC2_ACC1_5 :
965 print_keyword (cd, info, & mep_cgen_opval_h_ccr_ivc2, 0, 0);
967 case MEP_OPERAND_IVC2_ACC1_6 :
968 print_keyword (cd, info, & mep_cgen_opval_h_ccr_ivc2, 0, 0);
970 case MEP_OPERAND_IVC2_ACC1_7 :
971 print_keyword (cd, info, & mep_cgen_opval_h_ccr_ivc2, 0, 0);
973 case MEP_OPERAND_IVC2_CC :
974 print_keyword (cd, info, & mep_cgen_opval_h_ccr_ivc2, 0, 0);
976 case MEP_OPERAND_IVC2_COFA0 :
977 print_keyword (cd, info, & mep_cgen_opval_h_ccr_ivc2, 0, 0);
979 case MEP_OPERAND_IVC2_COFA1 :
980 print_keyword (cd, info, & mep_cgen_opval_h_ccr_ivc2, 0, 0);
982 case MEP_OPERAND_IVC2_COFR0 :
983 print_keyword (cd, info, & mep_cgen_opval_h_ccr_ivc2, 0, 0);
985 case MEP_OPERAND_IVC2_COFR1 :
986 print_keyword (cd, info, & mep_cgen_opval_h_ccr_ivc2, 0, 0);
988 case MEP_OPERAND_IVC2_CSAR0 :
989 print_keyword (cd, info, & mep_cgen_opval_h_ccr_ivc2, 0, 0);
991 case MEP_OPERAND_IVC2_CSAR1 :
992 print_keyword (cd, info, & mep_cgen_opval_h_ccr_ivc2, 0, 0);
994 case MEP_OPERAND_IVC2C3CCRN :
995 print_keyword (cd, info, & mep_cgen_opval_h_ccr_ivc2, fields->f_ivc2_ccrn_c3, 0|(1<<CGEN_OPERAND_VIRTUAL));
997 case MEP_OPERAND_IVC2CCRN :
998 print_keyword (cd, info, & mep_cgen_opval_h_ccr_ivc2, fields->f_ivc2_ccrn, 0|(1<<CGEN_OPERAND_VIRTUAL));
1000 case MEP_OPERAND_IVC2CRN :
1001 print_keyword (cd, info, & mep_cgen_opval_h_cr64, fields->f_ivc2_crnx, 0|(1<<CGEN_OPERAND_VIRTUAL));
1003 case MEP_OPERAND_IVC2RM :
1004 print_keyword (cd, info, & mep_cgen_opval_h_gpr, fields->f_ivc2_crm, 0);
1006 case MEP_OPERAND_LO :
1007 print_keyword (cd, info, & mep_cgen_opval_h_csr, 0, 0);
1009 case MEP_OPERAND_LP :
1010 print_keyword (cd, info, & mep_cgen_opval_h_csr, 0, 0);
1012 case MEP_OPERAND_MB0 :
1013 print_keyword (cd, info, & mep_cgen_opval_h_csr, 0, 0);
1015 case MEP_OPERAND_MB1 :
1016 print_keyword (cd, info, & mep_cgen_opval_h_csr, 0, 0);
1018 case MEP_OPERAND_ME0 :
1019 print_keyword (cd, info, & mep_cgen_opval_h_csr, 0, 0);
1021 case MEP_OPERAND_ME1 :
1022 print_keyword (cd, info, & mep_cgen_opval_h_csr, 0, 0);
1024 case MEP_OPERAND_NPC :
1025 print_keyword (cd, info, & mep_cgen_opval_h_csr, 0, 0);
1027 case MEP_OPERAND_OPT :
1028 print_keyword (cd, info, & mep_cgen_opval_h_csr, 0, 0);
1030 case MEP_OPERAND_PCABS24A2 :
1031 print_address (cd, info, fields->f_24u5a2n, 0|(1<<CGEN_OPERAND_ABS_ADDR)|(1<<CGEN_OPERAND_VIRTUAL), pc, length);
1033 case MEP_OPERAND_PCREL12A2 :
1034 print_address (cd, info, fields->f_12s4a2, 0|(1<<CGEN_OPERAND_SIGNED)|(1<<CGEN_OPERAND_RELAX)|(1<<CGEN_OPERAND_PCREL_ADDR), pc, length);
1036 case MEP_OPERAND_PCREL17A2 :
1037 print_address (cd, info, fields->f_17s16a2, 0|(1<<CGEN_OPERAND_SIGNED)|(1<<CGEN_OPERAND_RELAX)|(1<<CGEN_OPERAND_PCREL_ADDR), pc, length);
1039 case MEP_OPERAND_PCREL24A2 :
1040 print_address (cd, info, fields->f_24s5a2n, 0|(1<<CGEN_OPERAND_SIGNED)|(1<<CGEN_OPERAND_PCREL_ADDR)|(1<<CGEN_OPERAND_VIRTUAL), pc, length);
1042 case MEP_OPERAND_PCREL8A2 :
1043 print_address (cd, info, fields->f_8s8a2, 0|(1<<CGEN_OPERAND_SIGNED)|(1<<CGEN_OPERAND_RELAX)|(1<<CGEN_OPERAND_PCREL_ADDR), pc, length);
1045 case MEP_OPERAND_PSW :
1046 print_keyword (cd, info, & mep_cgen_opval_h_csr, 0, 0);
1048 case MEP_OPERAND_R0 :
1049 print_keyword (cd, info, & mep_cgen_opval_h_gpr, 0, 0);
1051 case MEP_OPERAND_R1 :
1052 print_keyword (cd, info, & mep_cgen_opval_h_gpr, 0, 0);
1054 case MEP_OPERAND_RL :
1055 print_keyword (cd, info, & mep_cgen_opval_h_gpr, fields->f_rl, 0);
1057 case MEP_OPERAND_RL5 :
1058 print_keyword (cd, info, & mep_cgen_opval_h_gpr, fields->f_rl5, 0);
1060 case MEP_OPERAND_RM :
1061 print_keyword (cd, info, & mep_cgen_opval_h_gpr, fields->f_rm, 0);
1063 case MEP_OPERAND_RMA :
1064 print_keyword (cd, info, & mep_cgen_opval_h_gpr, fields->f_rm, 0);
1066 case MEP_OPERAND_RN :
1067 print_keyword (cd, info, & mep_cgen_opval_h_gpr, fields->f_rn, 0);
1069 case MEP_OPERAND_RN3 :
1070 print_keyword (cd, info, & mep_cgen_opval_h_gpr, fields->f_rn3, 0);
1072 case MEP_OPERAND_RN3C :
1073 print_keyword (cd, info, & mep_cgen_opval_h_gpr, fields->f_rn3, 0);
1075 case MEP_OPERAND_RN3L :
1076 print_keyword (cd, info, & mep_cgen_opval_h_gpr, fields->f_rn3, 0);
1078 case MEP_OPERAND_RN3S :
1079 print_keyword (cd, info, & mep_cgen_opval_h_gpr, fields->f_rn3, 0);
1081 case MEP_OPERAND_RN3UC :
1082 print_keyword (cd, info, & mep_cgen_opval_h_gpr, fields->f_rn3, 0);
1084 case MEP_OPERAND_RN3UL :
1085 print_keyword (cd, info, & mep_cgen_opval_h_gpr, fields->f_rn3, 0);
1087 case MEP_OPERAND_RN3US :
1088 print_keyword (cd, info, & mep_cgen_opval_h_gpr, fields->f_rn3, 0);
1090 case MEP_OPERAND_RNC :
1091 print_keyword (cd, info, & mep_cgen_opval_h_gpr, fields->f_rn, 0);
1093 case MEP_OPERAND_RNL :
1094 print_keyword (cd, info, & mep_cgen_opval_h_gpr, fields->f_rn, 0);
1096 case MEP_OPERAND_RNS :
1097 print_keyword (cd, info, & mep_cgen_opval_h_gpr, fields->f_rn, 0);
1099 case MEP_OPERAND_RNUC :
1100 print_keyword (cd, info, & mep_cgen_opval_h_gpr, fields->f_rn, 0);
1102 case MEP_OPERAND_RNUL :
1103 print_keyword (cd, info, & mep_cgen_opval_h_gpr, fields->f_rn, 0);
1105 case MEP_OPERAND_RNUS :
1106 print_keyword (cd, info, & mep_cgen_opval_h_gpr, fields->f_rn, 0);
1108 case MEP_OPERAND_SAR :
1109 print_keyword (cd, info, & mep_cgen_opval_h_csr, 0, 0);
1111 case MEP_OPERAND_SDISP16 :
1112 print_normal (cd, info, fields->f_16s16, 0|(1<<CGEN_OPERAND_SIGNED), pc, length);
1114 case MEP_OPERAND_SIMM16 :
1115 print_normal (cd, info, fields->f_16s16, 0|(1<<CGEN_OPERAND_SIGNED), pc, length);
1117 case MEP_OPERAND_SIMM16P0 :
1118 print_normal (cd, info, fields->f_ivc2_simm16p0, 0|(1<<CGEN_OPERAND_SIGNED)|(1<<CGEN_OPERAND_VIRTUAL), pc, length);
1120 case MEP_OPERAND_SIMM6 :
1121 print_normal (cd, info, fields->f_6s8, 0|(1<<CGEN_OPERAND_SIGNED), pc, length);
1123 case MEP_OPERAND_SIMM8 :
1124 print_normal (cd, info, fields->f_8s8, 0|(1<<CGEN_OPERAND_SIGNED)|(1<<CGEN_OPERAND_RELOC_IMPLIES_OVERFLOW), pc, length);
1126 case MEP_OPERAND_SIMM8P0 :
1127 print_normal (cd, info, fields->f_ivc2_8s0, 0|(1<<CGEN_OPERAND_SIGNED), pc, length);
1129 case MEP_OPERAND_SIMM8P20 :
1130 print_normal (cd, info, fields->f_ivc2_8s20, 0|(1<<CGEN_OPERAND_SIGNED), pc, length);
1132 case MEP_OPERAND_SIMM8P4 :
1133 print_normal (cd, info, fields->f_ivc2_8s4, 0|(1<<CGEN_OPERAND_SIGNED), pc, length);
1135 case MEP_OPERAND_SP :
1136 print_keyword (cd, info, & mep_cgen_opval_h_gpr, 0, 0);
1138 case MEP_OPERAND_SPR :
1139 print_spreg (cd, info, & mep_cgen_opval_h_gpr, 0, 0);
1141 case MEP_OPERAND_TP :
1142 print_keyword (cd, info, & mep_cgen_opval_h_gpr, 0, 0);
1144 case MEP_OPERAND_TPR :
1145 print_tpreg (cd, info, & mep_cgen_opval_h_gpr, 0, 0);
1147 case MEP_OPERAND_UDISP2 :
1148 print_normal (cd, info, fields->f_2u6, 0|(1<<CGEN_OPERAND_SIGNED), pc, length);
1150 case MEP_OPERAND_UDISP7 :
1151 print_normal (cd, info, fields->f_7u9, 0, pc, length);
1153 case MEP_OPERAND_UDISP7A2 :
1154 print_normal (cd, info, fields->f_7u9a2, 0, pc, length);
1156 case MEP_OPERAND_UDISP7A4 :
1157 print_normal (cd, info, fields->f_7u9a4, 0, pc, length);
1159 case MEP_OPERAND_UIMM16 :
1160 print_normal (cd, info, fields->f_16u16, 0, pc, length);
1162 case MEP_OPERAND_UIMM2 :
1163 print_normal (cd, info, fields->f_2u10, 0, pc, length);
1165 case MEP_OPERAND_UIMM24 :
1166 print_normal (cd, info, fields->f_24u8n, 0|(1<<CGEN_OPERAND_VIRTUAL), pc, length);
1168 case MEP_OPERAND_UIMM3 :
1169 print_normal (cd, info, fields->f_3u5, 0, pc, length);
1171 case MEP_OPERAND_UIMM4 :
1172 print_normal (cd, info, fields->f_4u8, 0, pc, length);
1174 case MEP_OPERAND_UIMM5 :
1175 print_normal (cd, info, fields->f_5u8, 0, pc, length);
1177 case MEP_OPERAND_UIMM7A4 :
1178 print_normal (cd, info, fields->f_7u9a4, 0, pc, length);
1180 case MEP_OPERAND_ZERO :
1181 print_normal (cd, info, 0, 0|(1<<CGEN_OPERAND_SIGNED), pc, length);
1185 /* xgettext:c-format */
1186 fprintf (stderr, _("Unrecognized field %d while printing insn.\n"),
1192 cgen_print_fn * const mep_cgen_print_handlers[] =
1199 mep_cgen_init_dis (CGEN_CPU_DESC cd)
1201 mep_cgen_init_opcode_table (cd);
1202 mep_cgen_init_ibld_table (cd);
1203 cd->print_handlers = & mep_cgen_print_handlers[0];
1204 cd->print_operand = mep_cgen_print_operand;
1208 /* Default print handler. */
1211 print_normal (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
1215 bfd_vma pc ATTRIBUTE_UNUSED,
1216 int length ATTRIBUTE_UNUSED)
1218 disassemble_info *info = (disassemble_info *) dis_info;
1220 /* Print the operand as directed by the attributes. */
1221 if (CGEN_BOOL_ATTR (attrs, CGEN_OPERAND_SEM_ONLY))
1222 ; /* nothing to do */
1223 else if (CGEN_BOOL_ATTR (attrs, CGEN_OPERAND_SIGNED))
1224 (*info->fprintf_func) (info->stream, "%ld", value);
1226 (*info->fprintf_func) (info->stream, "0x%lx", value);
1229 /* Default address handler. */
1232 print_address (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
1236 bfd_vma pc ATTRIBUTE_UNUSED,
1237 int length ATTRIBUTE_UNUSED)
1239 disassemble_info *info = (disassemble_info *) dis_info;
1241 /* Print the operand as directed by the attributes. */
1242 if (CGEN_BOOL_ATTR (attrs, CGEN_OPERAND_SEM_ONLY))
1243 ; /* Nothing to do. */
1244 else if (CGEN_BOOL_ATTR (attrs, CGEN_OPERAND_PCREL_ADDR))
1245 (*info->print_address_func) (value, info);
1246 else if (CGEN_BOOL_ATTR (attrs, CGEN_OPERAND_ABS_ADDR))
1247 (*info->print_address_func) (value, info);
1248 else if (CGEN_BOOL_ATTR (attrs, CGEN_OPERAND_SIGNED))
1249 (*info->fprintf_func) (info->stream, "%ld", (long) value);
1251 (*info->fprintf_func) (info->stream, "0x%lx", (long) value);
1254 /* Keyword print handler. */
1257 print_keyword (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
1259 CGEN_KEYWORD *keyword_table,
1261 unsigned int attrs ATTRIBUTE_UNUSED)
1263 disassemble_info *info = (disassemble_info *) dis_info;
1264 const CGEN_KEYWORD_ENTRY *ke;
1266 ke = cgen_keyword_lookup_value (keyword_table, value);
1268 (*info->fprintf_func) (info->stream, "%s", ke->name);
1270 (*info->fprintf_func) (info->stream, "???");
1273 /* Default insn printer.
1275 DIS_INFO is defined as `void *' so the disassembler needn't know anything
1276 about disassemble_info. */
1279 print_insn_normal (CGEN_CPU_DESC cd,
1281 const CGEN_INSN *insn,
1282 CGEN_FIELDS *fields,
1286 const CGEN_SYNTAX *syntax = CGEN_INSN_SYNTAX (insn);
1287 disassemble_info *info = (disassemble_info *) dis_info;
1288 const CGEN_SYNTAX_CHAR_TYPE *syn;
1290 CGEN_INIT_PRINT (cd);
1292 for (syn = CGEN_SYNTAX_STRING (syntax); *syn; ++syn)
1294 if (CGEN_SYNTAX_MNEMONIC_P (*syn))
1296 (*info->fprintf_func) (info->stream, "%s", CGEN_INSN_MNEMONIC (insn));
1299 if (CGEN_SYNTAX_CHAR_P (*syn))
1301 (*info->fprintf_func) (info->stream, "%c", CGEN_SYNTAX_CHAR (*syn));
1305 /* We have an operand. */
1306 mep_cgen_print_operand (cd, CGEN_SYNTAX_FIELD (*syn), info,
1307 fields, CGEN_INSN_ATTRS (insn), pc, length);
1311 /* Subroutine of print_insn. Reads an insn into the given buffers and updates
1313 Returns 0 if all is well, non-zero otherwise. */
1316 read_insn (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
1318 disassemble_info *info,
1321 CGEN_EXTRACT_INFO *ex_info,
1322 unsigned long *insn_value)
1324 int status = (*info->read_memory_func) (pc, buf, buflen, info);
1328 (*info->memory_error_func) (status, pc, info);
1332 ex_info->dis_info = info;
1333 ex_info->valid = (1 << buflen) - 1;
1334 ex_info->insn_bytes = buf;
1336 *insn_value = bfd_get_bits (buf, buflen * 8, info->endian == BFD_ENDIAN_BIG);
1340 /* Utility to print an insn.
1341 BUF is the base part of the insn, target byte order, BUFLEN bytes long.
1342 The result is the size of the insn in bytes or zero for an unknown insn
1343 or -1 if an error occurs fetching data (memory_error_func will have
1347 print_insn (CGEN_CPU_DESC cd,
1349 disassemble_info *info,
1351 unsigned int buflen)
1353 CGEN_INSN_INT insn_value;
1354 const CGEN_INSN_LIST *insn_list;
1355 CGEN_EXTRACT_INFO ex_info;
1358 /* Extract base part of instruction, just in case CGEN_DIS_* uses it. */
1359 basesize = cd->base_insn_bitsize < buflen * 8 ?
1360 cd->base_insn_bitsize : buflen * 8;
1361 insn_value = cgen_get_insn_value (cd, buf, basesize);
1364 /* Fill in ex_info fields like read_insn would. Don't actually call
1365 read_insn, since the incoming buffer is already read (and possibly
1366 modified a la m32r). */
1367 ex_info.valid = (1 << buflen) - 1;
1368 ex_info.dis_info = info;
1369 ex_info.insn_bytes = buf;
1371 /* The instructions are stored in hash lists.
1372 Pick the first one and keep trying until we find the right one. */
1374 insn_list = CGEN_DIS_LOOKUP_INSN (cd, (char *) buf, insn_value);
1375 while (insn_list != NULL)
1377 const CGEN_INSN *insn = insn_list->insn;
1380 unsigned long insn_value_cropped;
1382 #ifdef CGEN_VALIDATE_INSN_SUPPORTED
1383 /* Not needed as insn shouldn't be in hash lists if not supported. */
1384 /* Supported by this cpu? */
1385 if (! mep_cgen_insn_supported (cd, insn))
1387 insn_list = CGEN_DIS_NEXT_INSN (insn_list);
1392 /* Basic bit mask must be correct. */
1393 /* ??? May wish to allow target to defer this check until the extract
1396 /* Base size may exceed this instruction's size. Extract the
1397 relevant part from the buffer. */
1398 if ((unsigned) (CGEN_INSN_BITSIZE (insn) / 8) < buflen &&
1399 (unsigned) (CGEN_INSN_BITSIZE (insn) / 8) <= sizeof (unsigned long))
1400 insn_value_cropped = bfd_get_bits (buf, CGEN_INSN_BITSIZE (insn),
1401 info->endian == BFD_ENDIAN_BIG);
1403 insn_value_cropped = insn_value;
1405 if ((insn_value_cropped & CGEN_INSN_BASE_MASK (insn))
1406 == CGEN_INSN_BASE_VALUE (insn))
1408 /* Printing is handled in two passes. The first pass parses the
1409 machine insn and extracts the fields. The second pass prints
1412 /* Make sure the entire insn is loaded into insn_value, if it
1414 if (((unsigned) CGEN_INSN_BITSIZE (insn) > cd->base_insn_bitsize) &&
1415 (unsigned) (CGEN_INSN_BITSIZE (insn) / 8) <= sizeof (unsigned long))
1417 unsigned long full_insn_value;
1418 int rc = read_insn (cd, pc, info, buf,
1419 CGEN_INSN_BITSIZE (insn) / 8,
1420 & ex_info, & full_insn_value);
1423 length = CGEN_EXTRACT_FN (cd, insn)
1424 (cd, insn, &ex_info, full_insn_value, &fields, pc);
1427 length = CGEN_EXTRACT_FN (cd, insn)
1428 (cd, insn, &ex_info, insn_value_cropped, &fields, pc);
1430 /* Length < 0 -> error. */
1435 CGEN_PRINT_FN (cd, insn) (cd, info, insn, &fields, pc, length);
1436 /* Length is in bits, result is in bytes. */
1441 insn_list = CGEN_DIS_NEXT_INSN (insn_list);
1447 /* Default value for CGEN_PRINT_INSN.
1448 The result is the size of the insn in bytes or zero for an unknown insn
1449 or -1 if an error occured fetching bytes. */
1451 #ifndef CGEN_PRINT_INSN
1452 #define CGEN_PRINT_INSN default_print_insn
1456 default_print_insn (CGEN_CPU_DESC cd, bfd_vma pc, disassemble_info *info)
1458 bfd_byte buf[CGEN_MAX_INSN_SIZE];
1462 /* Attempt to read the base part of the insn. */
1463 buflen = cd->base_insn_bitsize / 8;
1464 status = (*info->read_memory_func) (pc, buf, buflen, info);
1466 /* Try again with the minimum part, if min < base. */
1467 if (status != 0 && (cd->min_insn_bitsize < cd->base_insn_bitsize))
1469 buflen = cd->min_insn_bitsize / 8;
1470 status = (*info->read_memory_func) (pc, buf, buflen, info);
1475 (*info->memory_error_func) (status, pc, info);
1479 return print_insn (cd, pc, info, buf, buflen);
1482 /* Main entry point.
1483 Print one instruction from PC on INFO->STREAM.
1484 Return the size of the instruction (in bytes). */
1486 typedef struct cpu_desc_list
1488 struct cpu_desc_list *next;
1496 print_insn_mep (bfd_vma pc, disassemble_info *info)
1498 static cpu_desc_list *cd_list = 0;
1499 cpu_desc_list *cl = 0;
1500 static CGEN_CPU_DESC cd = 0;
1501 static CGEN_BITSET *prev_isa;
1502 static int prev_mach;
1503 static int prev_endian;
1507 int endian = (info->endian == BFD_ENDIAN_BIG
1509 : CGEN_ENDIAN_LITTLE);
1510 enum bfd_architecture arch;
1512 /* ??? gdb will set mach but leave the architecture as "unknown" */
1513 #ifndef CGEN_BFD_ARCH
1514 #define CGEN_BFD_ARCH bfd_arch_mep
1517 if (arch == bfd_arch_unknown)
1518 arch = CGEN_BFD_ARCH;
1520 /* There's no standard way to compute the machine or isa number
1521 so we leave it to the target. */
1522 #ifdef CGEN_COMPUTE_MACH
1523 mach = CGEN_COMPUTE_MACH (info);
1528 #ifdef CGEN_COMPUTE_ISA
1530 static CGEN_BITSET *permanent_isa;
1533 permanent_isa = cgen_bitset_create (MAX_ISAS);
1534 isa = permanent_isa;
1535 cgen_bitset_clear (isa);
1536 cgen_bitset_add (isa, CGEN_COMPUTE_ISA (info));
1539 isa = info->insn_sets;
1542 /* If we've switched cpu's, try to find a handle we've used before */
1544 && (cgen_bitset_compare (isa, prev_isa) != 0
1545 || mach != prev_mach
1546 || endian != prev_endian))
1549 for (cl = cd_list; cl; cl = cl->next)
1551 if (cgen_bitset_compare (cl->isa, isa) == 0 &&
1553 cl->endian == endian)
1556 prev_isa = cd->isas;
1562 /* If we haven't initialized yet, initialize the opcode table. */
1565 const bfd_arch_info_type *arch_type = bfd_lookup_arch (arch, mach);
1566 const char *mach_name;
1570 mach_name = arch_type->printable_name;
1572 prev_isa = cgen_bitset_copy (isa);
1574 prev_endian = endian;
1575 cd = mep_cgen_cpu_open (CGEN_CPU_OPEN_ISAS, prev_isa,
1576 CGEN_CPU_OPEN_BFDMACH, mach_name,
1577 CGEN_CPU_OPEN_ENDIAN, prev_endian,
1582 /* Save this away for future reference. */
1583 cl = xmalloc (sizeof (struct cpu_desc_list));
1587 cl->endian = endian;
1591 mep_cgen_init_dis (cd);
1594 /* We try to have as much common code as possible.
1595 But at this point some targets need to take over. */
1596 /* ??? Some targets may need a hook elsewhere. Try to avoid this,
1597 but if not possible try to move this hook elsewhere rather than
1599 length = CGEN_PRINT_INSN (cd, pc, info);
1605 (*info->fprintf_func) (info->stream, UNKNOWN_INSN_MSG);
1606 return cd->default_insn_bitsize / 8;