1 /* Instruction printing code for the MAXQ
3 Copyright 2004, 2005 Free Software Foundation, Inc.
5 Written by Vineet Sharma(vineets@noida.hcltech.com) Inderpreet
6 S.(inderpreetb@noida.hcltech.com)
8 This file is part of GDB.
10 This program is free software; you can redistribute it and/or modify it
11 under the terms of the GNU General Public License as published by the Free
12 Software Foundation; either version 2 of the License, or (at your option)
15 This program is distributed in the hope that it will be useful, but
16 WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
17 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
20 You should have received a copy of the GNU General Public License along
21 with this program; if not, write to the Free Software Foundation, Inc.,
22 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */
26 #include "opcode/maxq.h"
30 unsigned char group_no;
31 unsigned char sub_opcode;
40 typedef struct _group_info group_info;
48 #define MASK_LOW_BYTE 0x0f
49 #define MASK_HIGH_BYTE 0xf0
51 /* Flags for retrieving the bits from the op-code. */
52 #define _DECODE_LOWNIB_LOWBYTE 0x000f
53 #define _DECODE_HIGHNIB_LOWBYTE 0x00f0
54 #define _DECODE_LOWNIB_HIGHBYTE 0x0f00
55 #define _DECODE_HIGHNIB_HIGHBYTE 0xf000
56 #define _DECODE_HIGHBYTE 0xff00
57 #define _DECODE_LOWBYTE 0x00ff
58 #define _DECODE_4TO6_HIGHBYTE 0x7000
59 #define _DECODE_4TO6_LOWBYTE 0x0070
60 #define _DECODE_0TO6_HIGHBYTE 0x7f00
61 #define _DECODE_0TO2_HIGHBYTE 0x0700
62 #define _DECODE_GET_F_HIGHBYTE 0x8000
63 #define _DECODE_BIT7_HIGHBYTE 0x8000
64 #define _DECODE_BIT7_LOWBYTE 0x0080
65 #define _DECODE_GET_CARRY 0x10000
66 #define _DECODE_BIT0_LOWBYTE 0x1
67 #define _DECODE_BIT6AND7_HIGHBYTE 0xc000
69 /* Module and Register Indexed of System Registers. */
70 #define _CURR_ACC_MODINDEX 0xa
71 #define _CURR_ACC_REGINDEX 0x0
72 #define _PSF_REG_MODINDEX 0x8
73 #define _PSF_REG_REGINDEX 0x4
74 #define _PFX_REG_MODINDEX 0xb
75 #define _PFX0_REG_REGINDEX 0x0
76 #define _PFX2_REG_REGINDEX 0x2
77 #define _DP_REG_MODINDEX 0xf
78 #define _DP0_REG_REGINDEX 0x3
79 #define _DP1_REG_REGINDEX 0x7
80 #define _IP_REG_MODINDEX 0xc
81 #define _IP_REG_REGINDEX 0x0
82 #define _IIR_REG_MODINDEX 0x8
83 #define _IIR_REG_REGINDEX 0xb
84 #define _SP_REG_MODINDEX 0xd
85 #define _SP_REG_REGINDEX 0x1
86 #define _IC_REG_MODINDEX 0x8
87 #define _IC_REG_REGINDEX 0x5
88 #define _LC_REG_MODINDEX 0xe
89 #define _LC0_REG_REGINDEX 0x0
90 #define _LC1_REG_REGINDEX 0x1
91 #define _LC2_REG_REGINDEX 0x2
92 #define _LC3_REG_REGINDEX 0x3
94 /* Flags for finding the bits in PSF Register. */
95 #define SIM_ALU_DECODE_CARRY_BIT_POS 0x2
96 #define SIM_ALU_DECODE_SIGN_BIT_POS 0x40
97 #define SIM_ALU_DECODE_ZERO_BIT_POS 0x80
98 #define SIM_ALU_DECODE_EQUAL_BIT_POS 0x1
99 #define SIM_ALU_DECODE_IGE_BIT_POS 0x1
101 /* Number Of Op-code Groups. */
102 unsigned char const SIM_ALU_DECODE_OPCODE_GROUPS = 11;
104 /* Op-code Groups. */
105 unsigned char const SIM_ALU_DECODE_LOGICAL_XCHG_OP_GROUP = 1;
107 /* Group1: AND/OR/XOR/ADD/SUB Operations: fxxx 1010 ssss ssss. */
108 unsigned char const SIM_ALU_DECODE_AND_OR_ADD_SUB_OP_GROUP = 2;
110 /* Group2: Logical Operations: 1000 1010 xxxx 1010. */
111 unsigned char const SIM_ALU_DECODE_BIT_OP_GROUP = 3;
113 /* XCHG/Bit Operations: 1xxx 1010 xxxx 1010. */
114 unsigned char const SIM_ALU_DECODE_SET_DEST_BIT_GROUP = 4;
116 /* Move value in bit of destination register: 1ddd dddd xbbb 0111. */
117 unsigned char const SIM_ALU_DECODE_JUMP_OP_GROUP = 5;
119 #define JUMP_CHECK(insn) \
120 ( ((insn & _DECODE_4TO6_HIGHBYTE) == 0x0000) \
121 || ((insn & _DECODE_4TO6_HIGHBYTE) == 0x2000) \
122 || ((insn & _DECODE_4TO6_HIGHBYTE) == 0x6000) \
123 || ((insn & _DECODE_4TO6_HIGHBYTE) == 0x1000) \
124 || ((insn & _DECODE_4TO6_HIGHBYTE) == 0x5000) \
125 || ((insn & _DECODE_4TO6_HIGHBYTE) == 0x3000) \
126 || ((insn & _DECODE_4TO6_HIGHBYTE) == 0x7000) \
127 || ((insn & _DECODE_4TO6_HIGHBYTE) == 0x4000) )
129 /* JUMP operations: fxxx 1100 ssss ssss */
130 unsigned char const SIM_ALU_DECODE_RET_OP_GROUP = 6;
132 /* RET Operations: 1xxx 1100 0000 1101 */
133 unsigned char const SIM_ALU_DECODE_MOVE_SRC_DST_GROUP = 7;
135 /* Move src into dest register: fddd dddd ssss ssss */
136 unsigned char const SIM_ALU_DECODE_SET_SRC_BIT_GROUP = 8;
138 /* Move value in bit of source register: fbbb 0111 ssss ssss */
139 unsigned char const SIM_ALU_DECODE_DJNZ_CALL_PUSH_OP_GROUP = 9;
141 /* PUSH, DJNZ and CALL operations: fxxx 1101 ssss ssss */
142 unsigned char const SIM_ALU_DECODE_POP_OP_GROUP = 10;
144 /* POP operation: 1ddd dddd 0000 1101 */
145 unsigned char const SIM_ALU_DECODE_CMP_SRC_OP_GROUP = 11;
148 char unres_reg_name[20];
151 get_reg_name (unsigned char reg_code, type1 arg_pos)
153 unsigned char module;
156 reg_entry const *reg_x;
157 mem_access_syntax const *syntax;
162 module = (reg_code & MASK_LOW_BYTE);
163 index = (reg_code & MASK_HIGH_BYTE);
166 /* Search the system register table. */
167 for (reg_x = &system_reg_table[0]; reg_x->reg_name != NULL; ++reg_x)
168 if ((reg_x->Mod_name == module) && (reg_x->Mod_index == index))
169 return reg_x->reg_name;
171 /* Serch pheripheral table. */
172 for (ix = 0; ix < num_of_reg; ix++)
174 reg_x = &new_reg_table[ix];
176 if ((reg_x->Mod_name == module) && (reg_x->Mod_index == index))
177 return reg_x->reg_name;
180 for (mem_acc = &mem_table[0]; mem_acc->name != NULL || !mem_acc; ++mem_acc)
182 if (reg_code == mem_acc->opcode)
184 for (syntax = mem_access_syntax_table;
185 mem_access_syntax_table != NULL || mem_access_syntax_table->name;
187 if (!strcmp (mem_acc->name, syntax->name))
189 if ((arg_pos == syntax->type) || (syntax->type == BOTH))
190 return mem_acc->name;
197 memset (unres_reg_name, 0, 20);
198 sprintf (unres_reg_name, "%01x%01xh", index, module);
200 return unres_reg_name;
204 check_move (unsigned char insn0, unsigned char insn8)
206 bfd_boolean first = FALSE;
207 bfd_boolean second = FALSE;
210 reg_entry const *reg_x;
211 const unsigned char module1 = insn0 & MASK_LOW_BYTE;
212 const unsigned char index1 = ((insn0 & 0x70) >> 4);
213 const unsigned char module2 = insn8 & MASK_LOW_BYTE;
214 const unsigned char index2 = ((insn8 & MASK_HIGH_BYTE) >> 4);
217 if (((insn0 & MASK_LOW_BYTE) == MASK_LOW_BYTE)
218 && ((index1 == 0) || (index1 == 1) || (index1 == 2) || (index1 == 5)
219 || (index1 == 4) || (index1 == 6)))
222 else if (((insn0 & MASK_LOW_BYTE) == 0x0D) && (index1 == 0))
225 else if ((module1 == 0x0E)
226 && ((index1 == 0) || (index1 == 1) || (index1 == 2)))
231 for (reg_x = &system_reg_table[0]; reg_x->reg_name != NULL && reg_x;
234 if ((reg_x->Mod_name == module1) && (reg_x->Mod_index == index1)
235 && ((reg_x->rtype == Reg_16W) || (reg_x->rtype == Reg_8W)))
237 /* IP not allowed. */
238 if ((reg_x->Mod_name == 0x0C) && (reg_x->Mod_index == 0x00))
241 /* A[AP] not allowed. */
242 if ((reg_x->Mod_name == 0x0A) && (reg_x->Mod_index == 0x01))
244 first_reg = reg_x->reg_name;
252 /* No need to check further. */
258 if (((insn8 & MASK_LOW_BYTE) == MASK_LOW_BYTE)
259 && ((index2 == 0) || (index2 == 1) || (index2 == 2) || (index2 == 4)
260 || (index2 == 5) || (index2 == 6)))
263 else if (((insn8 & MASK_LOW_BYTE) == 0x0D) && (index2 == 0))
266 else if ((module2 == 0x0E)
267 && ((index2 == 0) || (index2 == 1) || (index2 == 2)))
272 for (reg_x = &system_reg_table[0];
273 reg_x->reg_name != NULL && reg_x;
276 if ((reg_x->Mod_name == (insn8 & MASK_LOW_BYTE))
277 && (reg_x->Mod_index == (((insn8 & 0xf0) >> 4))))
280 second_reg = reg_x->reg_name;
288 if ((module1 == 0x0A && index1 == 0x0)
289 && (module2 == 0x0A && index2 == 0x01))
302 maxq_print_arg (MAX_ARG_TYPE arg,
303 struct disassemble_info * info,
309 info->fprintf_func (info->stream, "C");
312 info->fprintf_func (info->stream, "NC");
316 info->fprintf_func (info->stream, "Z");
320 info->fprintf_func (info->stream, "NZ");
324 info->fprintf_func (info->stream, "S");
328 info->fprintf_func (info->stream, "E");
332 info->fprintf_func (info->stream, "NE");
336 info->fprintf_func (info->stream, "Acc");
337 if ((grp.flag & BIT_NO) == BIT_NO)
338 info->fprintf_func (info->stream, ".%d", grp.bit_no);
342 info->fprintf_func (info->stream, "#0");
345 info->fprintf_func (info->stream, "#1");
354 get_group (const unsigned int insn)
356 if (check_move ((insn >> 8), (insn & _DECODE_LOWBYTE)))
359 if ((insn & _DECODE_LOWNIB_HIGHBYTE) == 0x0A00)
361 /* && condition with sec part added on 26 May for resolving 2 & 3 grp
363 if (((insn & _DECODE_LOWNIB_LOWBYTE) == 0x000A)
364 && ((insn & _DECODE_GET_F_HIGHBYTE) == 0x8000))
366 if ((insn & _DECODE_HIGHNIB_HIGHBYTE) == 0x8000)
374 else if ((insn & _DECODE_LOWNIB_HIGHBYTE) == 0x0C00)
376 if (((insn & _DECODE_LOWBYTE) == 0x000D) && JUMP_CHECK (insn)
377 && ((insn & _DECODE_GET_F_HIGHBYTE) == 0x8000))
379 else if ((insn & _DECODE_LOWBYTE) == 0x008D)
384 else if (((insn & _DECODE_LOWNIB_HIGHBYTE) == 0x0D00)
385 && (((insn & _DECODE_4TO6_HIGHBYTE) == 0x3000)
386 || ((insn & _DECODE_4TO6_HIGHBYTE) == 0x4000)
387 || ((insn & _DECODE_4TO6_HIGHBYTE) == 0x5000)
388 || ((insn & _DECODE_4TO6_HIGHBYTE) == 0x0000)))
391 else if ((insn & _DECODE_LOWBYTE) == 0x000D)
394 else if ((insn & _DECODE_LOWBYTE) == 0x008D)
397 else if ((insn & _DECODE_0TO6_HIGHBYTE) == 0x7800)
400 else if ((insn & _DECODE_LOWNIB_HIGHBYTE) == 0x0700)
403 else if (((insn & _DECODE_LOWNIB_LOWBYTE) == 0x0007)
404 && ((insn & _DECODE_GET_F_HIGHBYTE) == 0x8000))
411 get_insn_opcode (const unsigned int insn, group_info *i)
413 static unsigned char pfx_flag = 0;
414 static unsigned char count_for_pfx = 0;
417 i->bit_no ^= i->bit_no;
420 i->group_no ^= i->group_no;
422 i->sub_opcode ^= i->sub_opcode;
424 if (count_for_pfx > 0)
427 if (((insn >> 8) == 0x0b) || ((insn >> 8) == 0x2b))
433 i->group_no = get_group (insn);
435 if (pfx_flag && (i->group_no == 0x0D) && (count_for_pfx == 2)
436 && ((insn & _DECODE_0TO6_HIGHBYTE) == 0x7800))
440 pfx_flag ^= pfx_flag;
446 i->sub_opcode = ((insn & _DECODE_4TO6_HIGHBYTE) >> 12);
448 i->src = ((insn & _DECODE_LOWBYTE));
450 i->fbit = ((insn & _DECODE_GET_F_HIGHBYTE) >> 15);
455 i->sub_opcode = ((insn & _DECODE_HIGHNIB_LOWBYTE) >> 4);
460 i->sub_opcode = ((insn & _DECODE_HIGHNIB_HIGHBYTE) >> 12);
462 i->bit_no = ((insn & _DECODE_HIGHNIB_LOWBYTE) >> 4);
467 i->sub_opcode = ((insn & _DECODE_BIT7_LOWBYTE) >> 7);
469 i->dst = ((insn & _DECODE_0TO6_HIGHBYTE) >> 8);
471 i->bit_no = ((insn & _DECODE_4TO6_LOWBYTE) >> 4);
476 i->sub_opcode = ((insn & _DECODE_4TO6_HIGHBYTE) >> 12);
478 i->src = ((insn & _DECODE_LOWBYTE));
480 i->fbit = ((insn & _DECODE_GET_F_HIGHBYTE) >> 15);
485 i->sub_opcode = ((insn & _DECODE_HIGHNIB_HIGHBYTE) >> 12);
490 i->sub_opcode = ((insn & _DECODE_HIGHNIB_HIGHBYTE) >> 12);
495 i->dst = ((insn & _DECODE_0TO6_HIGHBYTE) >> 8);
497 i->src = ((insn & _DECODE_LOWBYTE));
499 i->fbit = ((insn & _DECODE_GET_F_HIGHBYTE) >> 15);
504 i->sub_opcode = ((insn & _DECODE_0TO2_HIGHBYTE) >> 8);
506 i->bit_no = ((insn & _DECODE_4TO6_HIGHBYTE) >> 12);
508 i->fbit = ((insn & _DECODE_GET_F_HIGHBYTE) >> 15);
510 i->src = ((insn & _DECODE_LOWBYTE));
515 i->sub_opcode = ((insn & _DECODE_4TO6_HIGHBYTE) >> 12);
517 i->src = ((insn & _DECODE_LOWBYTE));
519 i->fbit = ((insn & _DECODE_GET_F_HIGHBYTE) >> 15);
524 i->dst = ((insn & _DECODE_0TO6_HIGHBYTE) >> 8);
529 i->dst = ((insn & _DECODE_0TO6_HIGHBYTE) >> 8);
534 i->sub_opcode = ((insn & _DECODE_4TO6_HIGHBYTE) >> 12);
536 i->src = ((insn & _DECODE_LOWBYTE));
538 i->fbit = ((insn & _DECODE_GET_F_HIGHBYTE) >> 15);
547 /* Print one instruction from MEMADDR on INFO->STREAM. Return the size of the
548 instruction (always 2 on MAXQ20). */
551 print_insn (bfd_vma memaddr, struct disassemble_info *info,
552 enum bfd_endian endianess)
554 /* The raw instruction. */
555 unsigned char insn[2], insn0, insn8, derived_code;
557 unsigned int actual_operands;
559 /* The group_info collected/decoded. */
561 MAXQ20_OPCODE_INFO const *opcode;
566 status = info->read_memory_func (memaddr, (bfd_byte *) & insn[0], 2, info);
570 info->memory_error_func (status, memaddr, info);
577 /* FIXME: Endianness always little. */
578 if (endianess == BFD_ENDIAN_BIG)
579 get_insn_opcode (((insn[0] << 8) | (insn[1])), &grp);
581 get_insn_opcode (((insn[1] << 8) | (insn[0])), &grp);
583 derived_code = ((grp.group_no << 4) | grp.sub_opcode);
585 if (insn[0] == 0 && insn[1] == 0)
587 info->fprintf_func (info->stream, "00 00");
591 /* The opcode is always in insn0. */
592 for (opcode = &op_table[0]; opcode->name != NULL; ++opcode)
594 if (opcode->instr_id == derived_code)
596 if (opcode->instr_id == 0x3D)
598 if ((grp.bit_no == 0) && (opcode->arg[1] != A_BIT_0))
600 if ((grp.bit_no == 1) && (opcode->arg[1] != A_BIT_1))
602 if ((grp.bit_no == 3) && (opcode->arg[0] != 0))
606 info->fprintf_func (info->stream, "%s ", opcode->name);
610 if ((grp.flag & SRC) == SRC)
613 if ((grp.flag & DST) == DST)
616 /* If Implict FLAG in the Instruction. */
617 if ((opcode->op_number > actual_operands)
618 && !((grp.flag & SRC) == SRC) && !((grp.flag & DST) == DST))
620 for (i = 0; i < opcode->op_number; i++)
622 if (i == 1 && (opcode->arg[1] != NO_ARG))
623 info->fprintf_func (info->stream, ",");
624 maxq_print_arg (opcode->arg[i], info, grp);
628 /* DST is ABSENT in the grp. */
629 if ((opcode->op_number > actual_operands)
630 && ((grp.flag & SRC) == SRC))
632 maxq_print_arg (opcode->arg[0], info, grp);
633 info->fprintf_func (info->stream, " ");
635 if (opcode->instr_id == 0xA4)
636 info->fprintf_func (info->stream, "LC[0]");
638 if (opcode->instr_id == 0xA5)
639 info->fprintf_func (info->stream, "LC[1]");
641 if ((grp.flag & SRC) == SRC)
642 info->fprintf_func (info->stream, ",");
645 if ((grp.flag & DST) == DST)
647 if ((grp.flag & BIT_NO) == BIT_NO)
649 info->fprintf_func (info->stream, " %s.%d",
650 get_reg_name (grp.dst,
655 info->fprintf_func (info->stream, " %s",
656 get_reg_name (grp.dst, (type1) 0));
659 /* SRC is ABSENT in the grp. */
660 if ((opcode->op_number > actual_operands)
661 && ((grp.flag & DST) == DST))
663 info->fprintf_func (info->stream, ",");
664 maxq_print_arg (opcode->arg[1], info, grp);
665 info->fprintf_func (info->stream, " ");
668 if ((grp.flag & SRC) == SRC)
670 if ((grp.flag & DST) == DST)
671 info->fprintf_func (info->stream, ",");
673 if ((grp.flag & BIT_NO) == BIT_NO)
675 format = opcode->format;
677 if ((grp.flag & FORMAT) == FORMAT)
680 info->fprintf_func (info->stream, " %s.%d",
681 get_reg_name (grp.src,
685 info->fprintf_func (info->stream, " #%02xh.%d",
686 grp.src, grp.bit_no);
690 format = opcode->format;
692 if ((grp.flag & FORMAT) == FORMAT)
695 info->fprintf_func (info->stream, " %s",
696 get_reg_name (grp.src,
699 info->fprintf_func (info->stream, " #%02xh",
708 info->fprintf_func (info->stream, "Unable to Decode : %02x %02x",
714 print_insn_maxq_little (bfd_vma memaddr, struct disassemble_info *info)
716 return print_insn (memaddr, info, BFD_ENDIAN_LITTLE);