1 /* Print Motorola 68k instructions.
2 Copyright 1986, 1987, 1989, 1991, 1992, 1993, 1994, 1995, 1996, 1997,
3 1998, 1999, 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009
4 Free Software Foundation, Inc.
6 This file is part of the GNU opcodes library.
8 This library is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 3, or (at your option)
13 It is distributed in the hope that it will be useful, but WITHOUT
14 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
15 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
16 License for more details.
18 You should have received a copy of the GNU General Public License
19 along with this program; if not, write to the Free Software
20 Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
21 MA 02110-1301, USA. */
25 #include "floatformat.h"
26 #include "libiberty.h"
29 #include "opcode/m68k.h"
31 /* Local function prototypes. */
33 const char * const fpcr_names[] =
35 "", "%fpiar", "%fpsr", "%fpiar/%fpsr", "%fpcr",
36 "%fpiar/%fpcr", "%fpsr/%fpcr", "%fpiar/%fpsr/%fpcr"
39 static char *const reg_names[] =
41 "%d0", "%d1", "%d2", "%d3", "%d4", "%d5", "%d6", "%d7",
42 "%a0", "%a1", "%a2", "%a3", "%a4", "%a5", "%fp", "%sp",
46 /* Name of register halves for MAC/EMAC.
47 Seperate from reg_names since 'spu', 'fpl' look weird. */
48 static char *const reg_half_names[] =
50 "%d0", "%d1", "%d2", "%d3", "%d4", "%d5", "%d6", "%d7",
51 "%a0", "%a1", "%a2", "%a3", "%a4", "%a5", "%a6", "%a7",
55 /* Sign-extend an (unsigned char). */
57 #define COERCE_SIGNED_CHAR(ch) ((signed char) (ch))
59 #define COERCE_SIGNED_CHAR(ch) ((int) (((ch) ^ 0x80) & 0xFF) - 128)
62 /* Get a 1 byte signed integer. */
63 #define NEXTBYTE(p, val) \
67 if (!FETCH_DATA (info, p)) \
69 val = COERCE_SIGNED_CHAR (p[-1]); \
73 /* Get a 2 byte signed integer. */
74 #define COERCE16(x) ((int) (((x) ^ 0x8000) - 0x8000))
76 #define NEXTWORD(p, val, ret_val) \
80 if (!FETCH_DATA (info, p)) \
82 val = COERCE16 ((p[-2] << 8) + p[-1]); \
86 /* Get a 4 byte signed integer. */
87 #define COERCE32(x) ((bfd_signed_vma) ((x) ^ 0x80000000) - 0x80000000)
89 #define NEXTLONG(p, val, ret_val) \
93 if (!FETCH_DATA (info, p)) \
95 val = COERCE32 ((((((p[-4] << 8) + p[-3]) << 8) + p[-2]) << 8) + p[-1]); \
99 /* Get a 4 byte unsigned integer. */
100 #define NEXTULONG(p, val) \
104 if (!FETCH_DATA (info, p)) \
106 val = (unsigned int) ((((((p[-4] << 8) + p[-3]) << 8) + p[-2]) << 8) + p[-1]); \
110 /* Get a single precision float. */
111 #define NEXTSINGLE(val, p) \
115 if (!FETCH_DATA (info, p)) \
117 floatformat_to_double (& floatformat_ieee_single_big, \
118 (char *) p - 4, & val); \
122 /* Get a double precision float. */
123 #define NEXTDOUBLE(val, p) \
127 if (!FETCH_DATA (info, p)) \
129 floatformat_to_double (& floatformat_ieee_double_big, \
130 (char *) p - 8, & val); \
134 /* Get an extended precision float. */
135 #define NEXTEXTEND(val, p) \
139 if (!FETCH_DATA (info, p)) \
141 floatformat_to_double (& floatformat_m68881_ext, \
142 (char *) p - 12, & val); \
146 /* Need a function to convert from packed to double
147 precision. Actually, it's easier to print a
148 packed number than a double anyway, so maybe
149 there should be a special case to handle this... */
150 #define NEXTPACKED(p, val) \
154 if (!FETCH_DATA (info, p)) \
161 /* Maximum length of an instruction. */
168 /* Points to first byte not fetched. */
169 bfd_byte *max_fetched;
170 bfd_byte the_buffer[MAXLEN];
174 /* Make sure that bytes from INFO->PRIVATE_DATA->BUFFER (inclusive)
175 to ADDR (exclusive) are valid. Returns 1 for success, 0 on error. */
176 #define FETCH_DATA(info, addr) \
177 ((addr) <= ((struct private *) (info->private_data))->max_fetched \
178 ? 1 : fetch_data ((info), (addr)))
181 fetch_data (struct disassemble_info *info, bfd_byte *addr)
184 struct private *priv = (struct private *)info->private_data;
185 bfd_vma start = priv->insn_start + (priv->max_fetched - priv->the_buffer);
187 status = (*info->read_memory_func) (start,
189 addr - priv->max_fetched,
193 (*info->memory_error_func) (status, start, info);
197 priv->max_fetched = addr;
201 /* This function is used to print to the bit-bucket. */
203 dummy_printer (FILE *file ATTRIBUTE_UNUSED,
204 const char *format ATTRIBUTE_UNUSED,
211 dummy_print_address (bfd_vma vma ATTRIBUTE_UNUSED,
212 struct disassemble_info *info ATTRIBUTE_UNUSED)
216 /* Fetch BITS bits from a position in the instruction specified by CODE.
217 CODE is a "place to put an argument", or 'x' for a destination
218 that is a general address (mode and register).
219 BUFFER contains the instruction.
220 Returns -1 on failure. */
223 fetch_arg (unsigned char *buffer,
226 disassemble_info *info)
232 case '/': /* MAC/EMAC mask bit. */
233 val = buffer[3] >> 5;
236 case 'G': /* EMAC ACC load. */
237 val = ((buffer[3] >> 3) & 0x2) | ((~buffer[1] >> 7) & 0x1);
240 case 'H': /* EMAC ACC !load. */
241 val = ((buffer[3] >> 3) & 0x2) | ((buffer[1] >> 7) & 0x1);
244 case ']': /* EMAC ACCEXT bit. */
245 val = buffer[0] >> 2;
248 case 'I': /* MAC/EMAC scale factor. */
249 val = buffer[2] >> 1;
252 case 'F': /* EMAC ACCx. */
253 val = buffer[0] >> 1;
264 case 'd': /* Destination, for register or quick. */
265 val = (buffer[0] << 8) + buffer[1];
269 case 'x': /* Destination, for general arg. */
270 val = (buffer[0] << 8) + buffer[1];
275 if (! FETCH_DATA (info, buffer + 3))
277 val = (buffer[3] >> 4);
281 if (! FETCH_DATA (info, buffer + 3))
287 if (! FETCH_DATA (info, buffer + 3))
289 val = (buffer[2] << 8) + buffer[3];
294 if (! FETCH_DATA (info, buffer + 3))
296 val = (buffer[2] << 8) + buffer[3];
302 if (! FETCH_DATA (info, buffer + 3))
304 val = (buffer[2] << 8) + buffer[3];
308 if (! FETCH_DATA (info, buffer + 5))
310 val = (buffer[4] << 8) + buffer[5];
315 if (! FETCH_DATA (info, buffer + 5))
317 val = (buffer[4] << 8) + buffer[5];
322 if (! FETCH_DATA (info, buffer + 5))
324 val = (buffer[4] << 8) + buffer[5];
328 if (! FETCH_DATA (info, buffer + 3))
330 val = (buffer[2] << 8) + buffer[3];
335 if (! FETCH_DATA (info, buffer + 3))
337 val = (buffer[2] << 8) + buffer[3];
342 if (! FETCH_DATA (info, buffer + 3))
344 val = (buffer[2] << 8) + buffer[3];
349 val = (buffer[1] >> 6);
353 if (! FETCH_DATA (info, buffer + 3))
355 val = (buffer[2] >> 1);
359 val = (buffer[1] & 0x40 ? 0x8 : 0)
360 | ((buffer[0] >> 1) & 0x7)
361 | (buffer[3] & 0x80 ? 0x10 : 0);
365 val = (buffer[1] & 0x40 ? 0x8 : 0) | ((buffer[0] >> 1) & 0x7);
369 val = (buffer[2] >> 4) | (buffer[3] & 0x80 ? 0x10 : 0);
373 val = (buffer[1] & 0xf) | (buffer[3] & 0x40 ? 0x10 : 0);
377 val = (buffer[3] & 0xf) | (buffer[3] & 0x40 ? 0x10 : 0);
381 val = buffer[2] >> 2;
388 /* bits is never too big. */
389 return val & ((1 << bits) - 1);
392 /* Check if an EA is valid for a particular code. This is required
393 for the EMAC instructions since the type of source address determines
394 if it is a EMAC-load instruciton if the EA is mode 2-5, otherwise it
395 is a non-load EMAC instruction and the bits mean register Ry.
396 A similar case exists for the movem instructions where the register
397 mask is interpreted differently for different EAs. */
400 m68k_valid_ea (char code, int val)
403 #define M(n0,n1,n2,n3,n4,n5,n6,n70,n71,n72,n73,n74) \
404 (n0 | n1 << 1 | n2 << 2 | n3 << 3 | n4 << 4 | n5 << 5 | n6 << 6 \
405 | n70 << 7 | n71 << 8 | n72 << 9 | n73 << 10 | n74 << 11)
410 mask = M (1,1,1,1,1,1,1,1,1,1,1,1);
413 mask = M (0,0,1,1,1,1,1,1,1,0,0,0);
416 mask = M (1,1,1,1,1,1,1,1,1,0,0,0);
419 mask = M (1,0,1,1,1,1,1,1,1,1,1,1);
422 mask = M (1,0,1,1,1,1,1,1,1,1,1,0);
425 mask = M (0,0,1,0,0,1,1,1,1,1,1,0);
428 mask = M (0,0,1,0,0,1,1,1,1,0,0,0);
431 mask = M (1,0,1,1,1,1,1,1,1,0,0,0);
434 mask = M (1,0,1,0,0,1,1,1,1,0,0,0);
437 mask = M (1,0,1,0,0,1,1,1,1,1,1,0);
440 mask = M (0,0,1,0,0,1,1,1,1,1,1,0);
443 mask = M (0,0,1,0,1,1,1,1,1,0,0,0);
446 mask = M (0,0,1,1,0,1,1,1,1,1,1,0);
449 mask = M (1,1,1,1,1,0,0,0,0,0,0,0);
452 mask = M (0,0,0,0,0,1,0,0,0,1,0,0);
455 mask = M (0,0,0,0,0,0,1,1,1,0,1,1);
458 mask = M (1,1,1,1,1,1,0,0,0,0,0,0);
461 mask = M (1,0,1,1,1,1,0,0,0,0,0,0);
464 mask = M (1,0,1,1,1,1,0,1,1,0,0,0);
467 mask = M (1,0,1,1,1,1,0,0,0,1,0,0);
470 mask = M (0,0,1,1,1,1,0,0,0,1,0,0);
473 mask = M (0,0,1,0,0,1,0,0,0,0,0,0);
476 mask = M (0,0,1,0,0,1,0,0,0,1,0,0);
479 mask = M (0,0,1,1,1,1,0,0,0,0,0,0);
486 mode = (val >> 3) & 7;
489 return (mask & (1 << mode)) != 0;
492 /* Print a base register REGNO and displacement DISP, on INFO->STREAM.
493 REGNO = -1 for pc, -2 for none (suppressed). */
496 print_base (int regno, bfd_vma disp, disassemble_info *info)
500 (*info->fprintf_func) (info->stream, "%%pc@(");
501 (*info->print_address_func) (disp, info);
508 (*info->fprintf_func) (info->stream, "@(");
509 else if (regno == -3)
510 (*info->fprintf_func) (info->stream, "%%zpc@(");
512 (*info->fprintf_func) (info->stream, "%s@(", reg_names[regno]);
514 sprintf_vma (buf, disp);
515 (*info->fprintf_func) (info->stream, "%s", buf);
519 /* Print an indexed argument. The base register is BASEREG (-1 for pc).
520 P points to extension word, in buffer.
521 ADDR is the nominal core address of that extension word.
522 Returns NULL upon error. */
524 static unsigned char *
525 print_indexed (int basereg,
528 disassemble_info *info)
531 static char *const scales[] = { "", ":2", ":4", ":8" };
537 NEXTWORD (p, word, NULL);
539 /* Generate the text for the index register.
540 Where this will be output is not yet determined. */
541 sprintf (buf, "%s:%c%s",
542 reg_names[(word >> 12) & 0xf],
543 (word & 0x800) ? 'l' : 'w',
544 scales[(word >> 9) & 3]);
546 /* Handle the 68000 style of indexing. */
548 if ((word & 0x100) == 0)
550 base_disp = word & 0xff;
551 if ((base_disp & 0x80) != 0)
555 print_base (basereg, base_disp, info);
556 (*info->fprintf_func) (info->stream, ",%s)", buf);
560 /* Handle the generalized kind. */
561 /* First, compute the displacement to add to the base register. */
572 switch ((word >> 4) & 3)
575 NEXTWORD (p, base_disp, NULL);
578 NEXTLONG (p, base_disp, NULL);
583 /* Handle single-level case (not indirect). */
586 print_base (basereg, base_disp, info);
588 (*info->fprintf_func) (info->stream, ",%s", buf);
589 (*info->fprintf_func) (info->stream, ")");
593 /* Two level. Compute displacement to add after indirection. */
598 NEXTWORD (p, outer_disp, NULL);
601 NEXTLONG (p, outer_disp, NULL);
604 print_base (basereg, base_disp, info);
605 if ((word & 4) == 0 && buf[0] != '\0')
607 (*info->fprintf_func) (info->stream, ",%s", buf);
610 sprintf_vma (vmabuf, outer_disp);
611 (*info->fprintf_func) (info->stream, ")@(%s", vmabuf);
613 (*info->fprintf_func) (info->stream, ",%s", buf);
614 (*info->fprintf_func) (info->stream, ")");
619 #define FETCH_ARG(size, val) \
622 val = fetch_arg (buffer, place, size, info); \
628 /* Returns number of bytes "eaten" by the operand, or
629 return -1 if an invalid operand was found, or -2 if
630 an opcode tabe error was found or -3 to simply abort.
631 ADDR is the pc for this arg to be relative to. */
634 print_insn_arg (const char *d,
635 unsigned char *buffer,
638 disassemble_info *info)
642 unsigned char *p = p0;
653 case 'c': /* Cache identifier. */
655 static char *const cacheFieldName[] = { "nc", "dc", "ic", "bc" };
657 (*info->fprintf_func) (info->stream, cacheFieldName[val]);
661 case 'a': /* Address register indirect only. Cf. case '+'. */
664 (*info->fprintf_func) (info->stream, "%s@", reg_names[val + 8]);
668 case '_': /* 32-bit absolute address for move16. */
671 (*info->print_address_func) (uval, info);
676 (*info->fprintf_func) (info->stream, "%%ccr");
680 (*info->fprintf_func) (info->stream, "%%sr");
684 (*info->fprintf_func) (info->stream, "%%usp");
688 (*info->fprintf_func) (info->stream, "%%acc");
692 (*info->fprintf_func) (info->stream, "%%macsr");
696 (*info->fprintf_func) (info->stream, "%%mask");
701 /* FIXME: There's a problem here, different m68k processors call the
702 same address different names. The tables below try to get it right
703 using info->mach, but only for v4e. */
704 struct regname { char * name; int value; };
705 static const struct regname names[] =
707 {"%sfc", 0x000}, {"%dfc", 0x001}, {"%cacr", 0x002},
708 {"%tc", 0x003}, {"%itt0",0x004}, {"%itt1", 0x005},
709 {"%dtt0",0x006}, {"%dtt1",0x007}, {"%buscr",0x008},
710 {"%rgpiobar", 0x009}, {"%acr4",0x00c},
711 {"%acr5",0x00d}, {"%acr6",0x00e}, {"%acr7", 0x00f},
712 {"%usp", 0x800}, {"%vbr", 0x801}, {"%caar", 0x802},
713 {"%msp", 0x803}, {"%isp", 0x804},
715 /* Reg c04 is sometimes called flashbar or rambar.
716 Reg c05 is also sometimes called rambar. */
717 {"%rambar0", 0xc04}, {"%rambar1", 0xc05},
719 /* reg c0e is sometimes called mbar2 or secmbar.
720 reg c0f is sometimes called mbar. */
721 {"%mbar0", 0xc0e}, {"%mbar1", 0xc0f},
723 /* Should we be calling this psr like we do in case 'Y'? */
726 {"%urp", 0x806}, {"%srp", 0x807}, {"%pcr", 0x808},
728 /* Fido added these. */
729 {"%cac", 0xffe}, {"%mbo", 0xfff}
731 /* Alternate names for v4e (MCF5407/5445x/MCF547x/MCF548x), at least. */
732 static const struct regname names_v4e[] =
734 {"%asid",0x003}, {"%acr0",0x004}, {"%acr1",0x005},
735 {"%acr2",0x006}, {"%acr3",0x007}, {"%mmubar",0x008},
737 unsigned int arch_mask;
739 arch_mask = bfd_m68k_mach_to_features (info->mach);
741 if (arch_mask & (mcfisa_b | mcfisa_c))
743 for (regno = ARRAY_SIZE (names_v4e); --regno >= 0;)
744 if (names_v4e[regno].value == val)
746 (*info->fprintf_func) (info->stream, "%s", names_v4e[regno].name);
752 for (regno = ARRAY_SIZE (names) - 1; regno >= 0; regno--)
753 if (names[regno].value == val)
755 (*info->fprintf_func) (info->stream, "%s", names[regno].name);
759 (*info->fprintf_func) (info->stream, "0x%x", val);
765 /* 0 means 8, except for the bkpt instruction... */
766 if (val == 0 && d[1] != 's')
768 (*info->fprintf_func) (info->stream, "#%d", val);
776 (*info->fprintf_func) (info->stream, "#%d", val);
781 (*info->fprintf_func) (info->stream, "#%d", val+1);
786 (*info->fprintf_func) (info->stream, "#%d", val);
792 static char *const scalefactor_name[] = { "<<", ">>" };
795 (*info->fprintf_func) (info->stream, scalefactor_name[val]);
802 (*info->fprintf_func) (info->stream, "#%d", val);
808 (*info->fprintf_func) (info->stream, "#%d", val);
813 (*info->fprintf_func) (info->stream, "%s", reg_names[val]);
818 (*info->fprintf_func) (info->stream, "%s", reg_names[val + 010]);
823 (*info->fprintf_func) (info->stream, "%s", reg_names[val]);
827 FETCH_ARG (4, regno);
829 (*info->fprintf_func) (info->stream, "%s@", reg_names[regno]);
831 (*info->fprintf_func) (info->stream, "@(%s)", reg_names[regno]);
836 (*info->fprintf_func) (info->stream, "%%fp%d", val);
842 (*info->fprintf_func) (info->stream, "%s", reg_names[val & 7]);
844 (*info->fprintf_func) (info->stream, "%d", val);
849 (*info->fprintf_func) (info->stream, "%s@+", reg_names[val + 8]);
854 (*info->fprintf_func) (info->stream, "%s@-", reg_names[val + 8]);
861 (*info->fprintf_func) (info->stream, "{%s}", reg_names[val]);
863 else if (place == 'C')
866 if (val > 63) /* This is a signed constant. */
868 (*info->fprintf_func) (info->stream, "{#%d}", val);
876 p1 = buffer + (*d == '#' ? 2 : 4);
879 else if (place == 'C')
881 else if (place == '8')
883 else if (place == '3')
885 else if (place == 'b')
887 else if (place == 'w' || place == 'W')
888 NEXTWORD (p1, val, -3);
889 else if (place == 'l')
890 NEXTLONG (p1, val, -3);
894 (*info->fprintf_func) (info->stream, "#%d", val);
900 else if (place == 'B')
901 disp = COERCE_SIGNED_CHAR (buffer[1]);
902 else if (place == 'w' || place == 'W')
903 NEXTWORD (p, disp, -3);
904 else if (place == 'l' || place == 'L' || place == 'C')
905 NEXTLONG (p, disp, -3);
906 else if (place == 'g')
908 NEXTBYTE (buffer, disp);
910 NEXTWORD (p, disp, -3);
912 NEXTLONG (p, disp, -3);
914 else if (place == 'c')
916 if (buffer[1] & 0x40) /* If bit six is one, long offset. */
917 NEXTLONG (p, disp, -3);
919 NEXTWORD (p, disp, -3);
924 (*info->print_address_func) (addr + disp, info);
931 NEXTWORD (p, val, -3);
933 (*info->fprintf_func) (info->stream, "%s@(%d)", reg_names[val1 + 8], val);
939 (*info->fprintf_func) (info->stream, "%s", fpcr_names[val]);
944 (*info->fprintf_func) (info->stream, "%%acc%d", val);
949 (*info->fprintf_func) (info->stream, "%%accext%s", val == 0 ? "01" : "23");
955 (*info->fprintf_func) (info->stream, "<<");
957 (*info->fprintf_func) (info->stream, ">>");
963 /* Get coprocessor ID... */
964 val = fetch_arg (buffer, 'd', 3, info);
967 if (val != 1) /* Unusual coprocessor ID? */
968 (*info->fprintf_func) (info->stream, "(cpid=%d) ", val);
997 val = fetch_arg (buffer, 'x', 6, info);
1000 val = ((val & 7) << 3) + ((val >> 3) & 7);
1004 val = fetch_arg (buffer, 's', 6, info);
1009 /* If the <ea> is invalid for *d, then reject this match. */
1010 if (!m68k_valid_ea (*d, val))
1013 /* Get register number assuming address register. */
1014 regno = (val & 7) + 8;
1015 regname = reg_names[regno];
1019 (*info->fprintf_func) (info->stream, "%s", reg_names[val]);
1023 (*info->fprintf_func) (info->stream, "%s", regname);
1027 (*info->fprintf_func) (info->stream, "%s@", regname);
1031 (*info->fprintf_func) (info->stream, "%s@+", regname);
1035 (*info->fprintf_func) (info->stream, "%s@-", regname);
1039 NEXTWORD (p, val, -3);
1040 (*info->fprintf_func) (info->stream, "%s@(%d)", regname, val);
1044 p = print_indexed (regno, p, addr, info);
1053 NEXTWORD (p, val, -3);
1054 (*info->print_address_func) (val, info);
1058 NEXTULONG (p, uval);
1059 (*info->print_address_func) (uval, info);
1063 NEXTWORD (p, val, -3);
1064 (*info->fprintf_func) (info->stream, "%%pc@(");
1065 (*info->print_address_func) (addr + val, info);
1066 (*info->fprintf_func) (info->stream, ")");
1070 p = print_indexed (-1, p, addr, info);
1076 flt_p = 1; /* Assume it's a float... */
1085 NEXTWORD (p, val, -3);
1090 NEXTLONG (p, val, -3);
1095 NEXTSINGLE (flval, p);
1099 NEXTDOUBLE (flval, p);
1103 NEXTEXTEND (flval, p);
1107 NEXTPACKED (p, flval);
1113 if (flt_p) /* Print a float? */
1114 (*info->fprintf_func) (info->stream, "#0e%g", flval);
1116 (*info->fprintf_func) (info->stream, "#%d", val);
1124 /* If place is '/', then this is the case of the mask bit for
1125 mac/emac loads. Now that the arg has been printed, grab the
1126 mask bit and if set, add a '&' to the arg. */
1131 info->fprintf_func (info->stream, "&");
1141 NEXTWORD (p1, val, -3);
1142 /* Move the pointer ahead if this point is farther ahead
1144 p = p1 > p ? p1 : p;
1147 (*info->fprintf_func) (info->stream, "#0");
1154 for (regno = 0; regno < 16; ++regno)
1155 if (val & (0x8000 >> regno))
1156 newval |= 1 << regno;
1161 for (regno = 0; regno < 16; ++regno)
1162 if (val & (1 << regno))
1167 (*info->fprintf_func) (info->stream, "/");
1169 (*info->fprintf_func) (info->stream, "%s", reg_names[regno]);
1170 first_regno = regno;
1171 while (val & (1 << (regno + 1)))
1173 if (regno > first_regno)
1174 (*info->fprintf_func) (info->stream, "-%s",
1178 else if (place == '3')
1180 /* `fmovem' insn. */
1186 (*info->fprintf_func) (info->stream, "#0");
1193 for (regno = 0; regno < 8; ++regno)
1194 if (val & (0x80 >> regno))
1195 newval |= 1 << regno;
1200 for (regno = 0; regno < 8; ++regno)
1201 if (val & (1 << regno))
1205 (*info->fprintf_func) (info->stream, "/");
1207 (*info->fprintf_func) (info->stream, "%%fp%d", regno);
1208 first_regno = regno;
1209 while (val & (1 << (regno + 1)))
1211 if (regno > first_regno)
1212 (*info->fprintf_func) (info->stream, "-%%fp%d", regno);
1215 else if (place == '8')
1218 /* fmoveml for FP status registers. */
1219 (*info->fprintf_func) (info->stream, "%s", fpcr_names[val]);
1240 case 2: name = "%tt0"; break;
1241 case 3: name = "%tt1"; break;
1242 case 0x10: name = "%tc"; break;
1243 case 0x11: name = "%drp"; break;
1244 case 0x12: name = "%srp"; break;
1245 case 0x13: name = "%crp"; break;
1246 case 0x14: name = "%cal"; break;
1247 case 0x15: name = "%val"; break;
1248 case 0x16: name = "%scc"; break;
1249 case 0x17: name = "%ac"; break;
1250 case 0x18: name = "%psr"; break;
1251 case 0x19: name = "%pcsr"; break;
1255 int break_reg = ((buffer[3] >> 2) & 7);
1257 (*info->fprintf_func)
1258 (info->stream, val == 0x1c ? "%%bad%d" : "%%bac%d",
1263 (*info->fprintf_func) (info->stream, "<mmu register %d>", val);
1266 (*info->fprintf_func) (info->stream, "%s", name);
1276 (*info->fprintf_func) (info->stream, "%%dfc");
1278 (*info->fprintf_func) (info->stream, "%%sfc");
1280 /* xgettext:c-format */
1281 (*info->fprintf_func) (info->stream, _("<function code %d>"), fc);
1286 (*info->fprintf_func) (info->stream, "%%val");
1293 FETCH_ARG (3, level);
1294 (*info->fprintf_func) (info->stream, "%d", level);
1309 (*info->fprintf_func) (info->stream, "%s%s",
1310 reg_half_names[reg],
1311 is_upper ? "u" : "l");
1322 /* Try to match the current instruction to best and if so, return the
1323 number of bytes consumed from the instruction stream, else zero. */
1326 match_insn_m68k (bfd_vma memaddr,
1327 disassemble_info * info,
1328 const struct m68k_opcode * best)
1330 unsigned char *save_p;
1333 const char *args = best->args;
1335 struct private *priv = (struct private *) info->private_data;
1336 bfd_byte *buffer = priv->the_buffer;
1337 fprintf_ftype save_printer = info->fprintf_func;
1338 void (* save_print_address) (bfd_vma, struct disassemble_info *)
1339 = info->print_address_func;
1344 /* Point at first word of argument data,
1345 and at descriptor for first argument. */
1348 /* Figure out how long the fixed-size portion of the instruction is.
1349 The only place this is stored in the opcode table is
1350 in the arguments--look for arguments which specify fields in the 2nd
1351 or 3rd words of the instruction. */
1352 for (d = args; *d; d += 2)
1354 /* I don't think it is necessary to be checking d[0] here;
1355 I suspect all this could be moved to the case statement below. */
1358 if (d[1] == 'l' && p - buffer < 6)
1360 else if (p - buffer < 4 && d[1] != 'C' && d[1] != '8')
1364 if ((d[0] == 'L' || d[0] == 'l') && d[1] == 'w' && p - buffer < 4)
1390 /* pflusha is an exceptions. It takes no arguments but is two words
1391 long. Recognize it by looking at the lower 16 bits of the mask. */
1392 if (p - buffer < 4 && (best->match & 0xFFFF) != 0)
1395 /* lpstop is another exception. It takes a one word argument but is
1396 three words long. */
1398 && (best->match & 0xffff) == 0xffff
1402 /* Copy the one word argument into the usual location for a one
1403 word argument, to simplify printing it. We can get away with
1404 this because we know exactly what the second word is, and we
1405 aren't going to print anything based on it. */
1407 FETCH_DATA (info, p);
1408 buffer[2] = buffer[4];
1409 buffer[3] = buffer[5];
1412 FETCH_DATA (info, p);
1415 info->print_address_func = dummy_print_address;
1416 info->fprintf_func = (fprintf_ftype) dummy_printer;
1418 /* We scan the operands twice. The first time we don't print anything,
1419 but look for errors. */
1420 for (d = args; *d; d += 2)
1422 int eaten = print_insn_arg (d, buffer, p, memaddr + (p - buffer), info);
1426 else if (eaten == -1 || eaten == -3)
1428 info->fprintf_func = save_printer;
1429 info->print_address_func = save_print_address;
1434 /* We must restore the print functions before trying to print the
1436 info->fprintf_func = save_printer;
1437 info->print_address_func = save_print_address;
1438 info->fprintf_func (info->stream,
1439 /* xgettext:c-format */
1440 _("<internal error in opcode table: %s %s>\n"),
1441 best->name, best->args);
1447 info->fprintf_func = save_printer;
1448 info->print_address_func = save_print_address;
1452 info->fprintf_func (info->stream, "%s", best->name);
1455 info->fprintf_func (info->stream, " ");
1459 p += print_insn_arg (d, buffer, p, memaddr + (p - buffer), info);
1462 if (*d && *(d - 2) != 'I' && *d != 'k')
1463 info->fprintf_func (info->stream, ",");
1469 /* Try to interpret the instruction at address MEMADDR as one that
1470 can execute on a processor with the features given by ARCH_MASK.
1471 If successful, print the instruction to INFO->STREAM and return
1472 its length in bytes. Return 0 otherwise. */
1475 m68k_scan_mask (bfd_vma memaddr, disassemble_info *info,
1476 unsigned int arch_mask)
1480 static const struct m68k_opcode **opcodes[16];
1481 static int numopcodes[16];
1485 struct private *priv = (struct private *) info->private_data;
1486 bfd_byte *buffer = priv->the_buffer;
1490 /* Speed up the matching by sorting the opcode
1491 table on the upper four bits of the opcode. */
1492 const struct m68k_opcode **opc_pointer[16];
1494 /* First count how many opcodes are in each of the sixteen buckets. */
1495 for (i = 0; i < m68k_numopcodes; i++)
1496 numopcodes[(m68k_opcodes[i].opcode >> 28) & 15]++;
1498 /* Then create a sorted table of pointers
1499 that point into the unsorted table. */
1500 opc_pointer[0] = xmalloc (sizeof (struct m68k_opcode *)
1502 opcodes[0] = opc_pointer[0];
1504 for (i = 1; i < 16; i++)
1506 opc_pointer[i] = opc_pointer[i - 1] + numopcodes[i - 1];
1507 opcodes[i] = opc_pointer[i];
1510 for (i = 0; i < m68k_numopcodes; i++)
1511 *opc_pointer[(m68k_opcodes[i].opcode >> 28) & 15]++ = &m68k_opcodes[i];
1514 FETCH_DATA (info, buffer + 2);
1515 major_opcode = (buffer[0] >> 4) & 15;
1517 for (i = 0; i < numopcodes[major_opcode]; i++)
1519 const struct m68k_opcode *opc = opcodes[major_opcode][i];
1520 unsigned long opcode = opc->opcode;
1521 unsigned long match = opc->match;
1522 const char *args = opc->args;
1527 if (((0xff & buffer[0] & (match >> 24)) == (0xff & (opcode >> 24)))
1528 && ((0xff & buffer[1] & (match >> 16)) == (0xff & (opcode >> 16)))
1529 /* Only fetch the next two bytes if we need to. */
1530 && (((0xffff & match) == 0)
1532 (FETCH_DATA (info, buffer + 4)
1533 && ((0xff & buffer[2] & (match >> 8)) == (0xff & (opcode >> 8)))
1534 && ((0xff & buffer[3] & match) == (0xff & opcode)))
1536 && (opc->arch & arch_mask) != 0)
1538 /* Don't use for printout the variants of divul and divsl
1539 that have the same register number in two places.
1540 The more general variants will match instead. */
1541 for (d = args; *d; d += 2)
1545 /* Don't use for printout the variants of most floating
1546 point coprocessor instructions which use the same
1547 register number in two places, as above. */
1549 for (d = args; *d; d += 2)
1553 /* Don't match fmovel with more than one register;
1554 wait for fmoveml. */
1557 for (d = args; *d; d += 2)
1559 if (d[0] == 's' && d[1] == '8')
1561 val = fetch_arg (buffer, d[1], 3, info);
1564 if ((val & (val - 1)) != 0)
1570 /* Don't match FPU insns with non-default coprocessor ID. */
1573 for (d = args; *d; d += 2)
1577 val = fetch_arg (buffer, 'd', 3, info);
1585 if ((val = match_insn_m68k (memaddr, info, opc)))
1592 /* Print the m68k instruction at address MEMADDR in debugged memory,
1593 on INFO->STREAM. Returns length of the instruction, in bytes. */
1596 print_insn_m68k (bfd_vma memaddr, disassemble_info *info)
1598 unsigned int arch_mask;
1599 struct private priv;
1602 bfd_byte *buffer = priv.the_buffer;
1604 info->private_data = & priv;
1605 /* Tell objdump to use two bytes per chunk
1606 and six bytes per line for displaying raw data. */
1607 info->bytes_per_chunk = 2;
1608 info->bytes_per_line = 6;
1609 info->display_endian = BFD_ENDIAN_BIG;
1610 priv.max_fetched = priv.the_buffer;
1611 priv.insn_start = memaddr;
1613 arch_mask = bfd_m68k_mach_to_features (info->mach);
1616 /* First try printing an m680x0 instruction. Try printing a Coldfire
1617 one if that fails. */
1618 val = m68k_scan_mask (memaddr, info, m68k_mask);
1620 val = m68k_scan_mask (memaddr, info, mcf_mask);
1624 val = m68k_scan_mask (memaddr, info, arch_mask);
1628 /* Handle undefined instructions. */
1629 info->fprintf_func (info->stream, ".short 0x%04x", (buffer[0] << 8) + buffer[1]);
1631 return val ? val : 2;