1 /* Print Motorola 68k instructions.
2 Copyright 1986, 1987, 1989, 1991, 1992, 1993, 1994, 1995, 1996, 1997,
3 1998, 1999, 2000, 2001, 2002, 2003, 2004
4 Free Software Foundation, Inc.
6 This file is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 2 of the License, or
9 (at your option) any later version.
11 This program is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
16 You should have received a copy of the GNU General Public License
17 along with this program; if not, write to the Free Software
18 Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */
22 #include "floatformat.h"
23 #include "libiberty.h"
26 #include "opcode/m68k.h"
28 /* Local function prototypes */
31 fetch_data PARAMS ((struct disassemble_info *, bfd_byte *));
34 dummy_print_address PARAMS ((bfd_vma, struct disassemble_info *));
37 fetch_arg PARAMS ((unsigned char *, int, int, disassemble_info *));
40 print_base PARAMS ((int, bfd_vma, disassemble_info *));
42 static unsigned char *
43 print_indexed PARAMS ((int, unsigned char *, bfd_vma, disassemble_info *));
46 print_insn_arg PARAMS ((const char *, unsigned char *, unsigned char *,
47 bfd_vma, disassemble_info *));
49 static bfd_boolean m68k_valid_ea (char code, int val);
51 const char * const fpcr_names[] =
53 "", "%fpiar", "%fpsr", "%fpiar/%fpsr", "%fpcr",
54 "%fpiar/%fpcr", "%fpsr/%fpcr", "%fpiar/%fpsr/%fpcr"
57 static char *const reg_names[] =
59 "%d0", "%d1", "%d2", "%d3", "%d4", "%d5", "%d6", "%d7",
60 "%a0", "%a1", "%a2", "%a3", "%a4", "%a5", "%fp", "%sp",
64 /* Name of register halves for MAC/EMAC.
65 Seperate from reg_names since 'spu', 'fpl' look weird. */
66 static char *const reg_half_names[] =
68 "%d0", "%d1", "%d2", "%d3", "%d4", "%d5", "%d6", "%d7",
69 "%a0", "%a1", "%a2", "%a3", "%a4", "%a5", "%a6", "%a7",
73 /* Sign-extend an (unsigned char). */
75 #define COERCE_SIGNED_CHAR(ch) ((signed char) (ch))
77 #define COERCE_SIGNED_CHAR(ch) ((int) (((ch) ^ 0x80) & 0xFF) - 128)
80 /* Get a 1 byte signed integer. */
81 #define NEXTBYTE(p) (p += 2, FETCH_DATA (info, p), COERCE_SIGNED_CHAR(p[-1]))
83 /* Get a 2 byte signed integer. */
84 #define COERCE16(x) ((int) (((x) ^ 0x8000) - 0x8000))
86 (p += 2, FETCH_DATA (info, p), \
87 COERCE16 ((p[-2] << 8) + p[-1]))
89 /* Get a 4 byte signed integer. */
90 #define COERCE32(x) ((bfd_signed_vma) ((x) ^ 0x80000000) - 0x80000000)
92 (p += 4, FETCH_DATA (info, p), \
93 (COERCE32 ((((((p[-4] << 8) + p[-3]) << 8) + p[-2]) << 8) + p[-1])))
95 /* Get a 4 byte unsigned integer. */
96 #define NEXTULONG(p) \
97 (p += 4, FETCH_DATA (info, p), \
98 (unsigned int) ((((((p[-4] << 8) + p[-3]) << 8) + p[-2]) << 8) + p[-1]))
100 /* Get a single precision float. */
101 #define NEXTSINGLE(val, p) \
102 (p += 4, FETCH_DATA (info, p), \
103 floatformat_to_double (&floatformat_ieee_single_big, (char *) p - 4, &val))
105 /* Get a double precision float. */
106 #define NEXTDOUBLE(val, p) \
107 (p += 8, FETCH_DATA (info, p), \
108 floatformat_to_double (&floatformat_ieee_double_big, (char *) p - 8, &val))
110 /* Get an extended precision float. */
111 #define NEXTEXTEND(val, p) \
112 (p += 12, FETCH_DATA (info, p), \
113 floatformat_to_double (&floatformat_m68881_ext, (char *) p - 12, &val))
115 /* Need a function to convert from packed to double
116 precision. Actually, it's easier to print a
117 packed number than a double anyway, so maybe
118 there should be a special case to handle this... */
119 #define NEXTPACKED(p) \
120 (p += 12, FETCH_DATA (info, p), 0.0)
122 /* Maximum length of an instruction. */
128 /* Points to first byte not fetched. */
129 bfd_byte *max_fetched;
130 bfd_byte the_buffer[MAXLEN];
135 /* Make sure that bytes from INFO->PRIVATE_DATA->BUFFER (inclusive)
136 to ADDR (exclusive) are valid. Returns 1 for success, longjmps
138 #define FETCH_DATA(info, addr) \
139 ((addr) <= ((struct private *) (info->private_data))->max_fetched \
140 ? 1 : fetch_data ((info), (addr)))
143 fetch_data (info, addr)
144 struct disassemble_info *info;
148 struct private *priv = (struct private *)info->private_data;
149 bfd_vma start = priv->insn_start + (priv->max_fetched - priv->the_buffer);
151 status = (*info->read_memory_func) (start,
153 addr - priv->max_fetched,
157 (*info->memory_error_func) (status, start, info);
158 longjmp (priv->bailout, 1);
161 priv->max_fetched = addr;
165 /* This function is used to print to the bit-bucket. */
168 dummy_printer (FILE *file ATTRIBUTE_UNUSED,
169 const char *format ATTRIBUTE_UNUSED, ...)
172 FILE *file ATTRIBUTE_UNUSED;
179 dummy_print_address (vma, info)
180 bfd_vma vma ATTRIBUTE_UNUSED;
181 struct disassemble_info *info ATTRIBUTE_UNUSED;
185 /* Try to match the current instruction to best and if so, return the
186 number of bytes consumed from the instruction stream, else zero. */
189 match_insn_m68k (bfd_vma memaddr, disassemble_info * info,
190 const struct m68k_opcode * best, struct private * priv)
192 unsigned char *save_p;
196 bfd_byte *buffer = priv->the_buffer;
197 fprintf_ftype save_printer = info->fprintf_func;
198 void (* save_print_address) (bfd_vma, struct disassemble_info *)
199 = info->print_address_func;
201 /* Point at first word of argument data,
202 and at descriptor for first argument. */
205 /* Figure out how long the fixed-size portion of the instruction is.
206 The only place this is stored in the opcode table is
207 in the arguments--look for arguments which specify fields in the 2nd
208 or 3rd words of the instruction. */
209 for (d = best->args; *d; d += 2)
211 /* I don't think it is necessary to be checking d[0] here;
212 I suspect all this could be moved to the case statement below. */
215 if (d[1] == 'l' && p - buffer < 6)
217 else if (p - buffer < 4 && d[1] != 'C' && d[1] != '8')
221 if ((d[0] == 'L' || d[0] == 'l') && d[1] == 'w' && p - buffer < 4)
247 /* pflusha is an exceptions. It takes no arguments but is two words
248 long. Recognize it by looking at the lower 16 bits of the mask. */
249 if (p - buffer < 4 && (best->match & 0xFFFF) != 0)
252 /* lpstop is another exception. It takes a one word argument but is
255 && (best->match & 0xffff) == 0xffff
256 && best->args[0] == '#'
257 && best->args[1] == 'w')
259 /* Copy the one word argument into the usual location for a one
260 word argument, to simplify printing it. We can get away with
261 this because we know exactly what the second word is, and we
262 aren't going to print anything based on it. */
264 FETCH_DATA (info, p);
265 buffer[2] = buffer[4];
266 buffer[3] = buffer[5];
269 FETCH_DATA (info, p);
274 info->print_address_func = dummy_print_address;
275 info->fprintf_func = (fprintf_ftype) dummy_printer;
277 /* We scan the operands twice. The first time we don't print anything,
278 but look for errors. */
281 int eaten = print_insn_arg (d, buffer, p, memaddr + (p - buffer), info);
285 else if (eaten == -1)
287 info->fprintf_func = save_printer;
288 info->print_address_func = save_print_address;
293 info->fprintf_func (info->stream,
294 /* xgettext:c-format */
295 _("<internal error in opcode table: %s %s>\n"),
296 best->name, best->args);
297 info->fprintf_func = save_printer;
298 info->print_address_func = save_print_address;
304 info->fprintf_func = save_printer;
305 info->print_address_func = save_print_address;
309 info->fprintf_func (info->stream, "%s", best->name);
312 info->fprintf_func (info->stream, " ");
316 p += print_insn_arg (d, buffer, p, memaddr + (p - buffer), info);
319 if (*d && *(d - 2) != 'I' && *d != 'k')
320 info->fprintf_func (info->stream, ",");
326 /* Print the m68k instruction at address MEMADDR in debugged memory,
327 on INFO->STREAM. Returns length of the instruction, in bytes. */
330 print_insn_m68k (memaddr, info)
332 disassemble_info *info;
336 unsigned int arch_mask;
338 bfd_byte *buffer = priv.the_buffer;
340 static int numopcodes[16];
341 static const struct m68k_opcode **opcodes[16];
346 /* Speed up the matching by sorting the opcode
347 table on the upper four bits of the opcode. */
348 const struct m68k_opcode **opc_pointer[16];
350 /* First count how many opcodes are in each of the sixteen buckets. */
351 for (i = 0; i < m68k_numopcodes; i++)
352 numopcodes[(m68k_opcodes[i].opcode >> 28) & 15]++;
354 /* Then create a sorted table of pointers
355 that point into the unsorted table. */
356 opc_pointer[0] = xmalloc (sizeof (struct m68k_opcode *)
358 opcodes[0] = opc_pointer[0];
360 for (i = 1; i < 16; i++)
362 opc_pointer[i] = opc_pointer[i - 1] + numopcodes[i - 1];
363 opcodes[i] = opc_pointer[i];
366 for (i = 0; i < m68k_numopcodes; i++)
367 *opc_pointer[(m68k_opcodes[i].opcode >> 28) & 15]++ = &m68k_opcodes[i];
370 info->private_data = (PTR) &priv;
371 /* Tell objdump to use two bytes per chunk
372 and six bytes per line for displaying raw data. */
373 info->bytes_per_chunk = 2;
374 info->bytes_per_line = 6;
375 info->display_endian = BFD_ENDIAN_BIG;
376 priv.max_fetched = priv.the_buffer;
377 priv.insn_start = memaddr;
379 if (setjmp (priv.bailout) != 0)
387 arch_mask = (unsigned int) -1;
389 case bfd_mach_m68000:
390 arch_mask = m68000|m68881|m68851;
392 case bfd_mach_m68008:
393 arch_mask = m68008|m68881|m68851;
395 case bfd_mach_m68010:
396 arch_mask = m68010|m68881|m68851;
398 case bfd_mach_m68020:
399 arch_mask = m68020|m68881|m68851;
401 case bfd_mach_m68030:
402 arch_mask = m68030|m68881|m68851;
404 case bfd_mach_m68040:
405 arch_mask = m68040|m68881|m68851;
407 case bfd_mach_m68060:
408 arch_mask = m68060|m68881|m68851;
410 case bfd_mach_mcf5200:
411 arch_mask = mcfisa_a;
413 case bfd_mach_mcf521x:
414 case bfd_mach_mcf528x:
415 arch_mask = mcfisa_a|mcfhwdiv|mcfisa_aa|mcfusp|mcfemac;
417 case bfd_mach_mcf5206e:
418 arch_mask = mcfisa_a|mcfhwdiv|mcfmac;
420 case bfd_mach_mcf5249:
421 arch_mask = mcfisa_a|mcfhwdiv|mcfemac;
423 case bfd_mach_mcf5307:
424 arch_mask = mcfisa_a|mcfhwdiv|mcfmac;
426 case bfd_mach_mcf5407:
427 arch_mask = mcfisa_a|mcfhwdiv|mcfisa_b|mcfmac;
429 case bfd_mach_mcf547x:
430 case bfd_mach_mcf548x:
431 case bfd_mach_mcfv4e:
432 arch_mask = mcfisa_a|mcfhwdiv|mcfisa_b|mcfusp|cfloat|mcfemac;
436 FETCH_DATA (info, buffer + 2);
437 major_opcode = (buffer[0] >> 4) & 15;
439 for (i = 0; i < numopcodes[major_opcode]; i++)
441 const struct m68k_opcode *opc = opcodes[major_opcode][i];
442 unsigned long opcode = opc->opcode;
443 unsigned long match = opc->match;
445 if (((0xff & buffer[0] & (match >> 24)) == (0xff & (opcode >> 24)))
446 && ((0xff & buffer[1] & (match >> 16)) == (0xff & (opcode >> 16)))
447 /* Only fetch the next two bytes if we need to. */
448 && (((0xffff & match) == 0)
450 (FETCH_DATA (info, buffer + 4)
451 && ((0xff & buffer[2] & (match >> 8)) == (0xff & (opcode >> 8)))
452 && ((0xff & buffer[3] & match) == (0xff & opcode)))
454 && (opc->arch & arch_mask) != 0)
456 /* Don't use for printout the variants of divul and divsl
457 that have the same register number in two places.
458 The more general variants will match instead. */
459 for (d = opc->args; *d; d += 2)
463 /* Don't use for printout the variants of most floating
464 point coprocessor instructions which use the same
465 register number in two places, as above. */
467 for (d = opc->args; *d; d += 2)
471 /* Don't match fmovel with more than one register;
475 for (d = opc->args; *d; d += 2)
477 if (d[0] == 's' && d[1] == '8')
479 val = fetch_arg (buffer, d[1], 3, info);
480 if ((val & (val - 1)) != 0)
487 if ((val = match_insn_m68k (memaddr, info, opc, & priv)))
492 /* Handle undefined instructions. */
493 info->fprintf_func (info->stream, "0%o", (buffer[0] << 8) + buffer[1]);
497 /* Returns number of bytes "eaten" by the operand, or
498 return -1 if an invalid operand was found, or -2 if
499 an opcode tabe error was found. */
502 print_insn_arg (d, buffer, p0, addr, info)
504 unsigned char *buffer;
506 bfd_vma addr; /* PC for this arg to be relative to. */
507 disassemble_info *info;
511 unsigned char *p = p0;
522 case 'c': /* Cache identifier. */
524 static char *const cacheFieldName[] = { "nc", "dc", "ic", "bc" };
525 val = fetch_arg (buffer, place, 2, info);
526 (*info->fprintf_func) (info->stream, cacheFieldName[val]);
530 case 'a': /* Address register indirect only. Cf. case '+'. */
532 (*info->fprintf_func)
535 reg_names[fetch_arg (buffer, place, 3, info) + 8]);
539 case '_': /* 32-bit absolute address for move16. */
541 uval = NEXTULONG (p);
542 (*info->print_address_func) (uval, info);
547 (*info->fprintf_func) (info->stream, "%%ccr");
551 (*info->fprintf_func) (info->stream, "%%sr");
555 (*info->fprintf_func) (info->stream, "%%usp");
559 (*info->fprintf_func) (info->stream, "%%acc");
563 (*info->fprintf_func) (info->stream, "%%macsr");
567 (*info->fprintf_func) (info->stream, "%%mask");
572 /* FIXME: There's a problem here, different m68k processors call the
573 same address different names. This table can't get it right
574 because it doesn't know which processor it's disassembling for. */
575 static const struct { char *name; int value; } names[]
576 = {{"%sfc", 0x000}, {"%dfc", 0x001}, {"%cacr", 0x002},
577 {"%tc", 0x003}, {"%itt0",0x004}, {"%itt1", 0x005},
578 {"%dtt0",0x006}, {"%dtt1",0x007}, {"%buscr",0x008},
579 {"%usp", 0x800}, {"%vbr", 0x801}, {"%caar", 0x802},
580 {"%msp", 0x803}, {"%isp", 0x804},
581 {"%flashbar", 0xc04}, {"%rambar", 0xc05}, /* mcf528x added these. */
583 /* Should we be calling this psr like we do in case 'Y'? */
586 {"%urp", 0x806}, {"%srp", 0x807}, {"%pcr", 0x808}};
588 val = fetch_arg (buffer, place, 12, info);
589 for (regno = sizeof names / sizeof names[0] - 1; regno >= 0; regno--)
590 if (names[regno].value == val)
592 (*info->fprintf_func) (info->stream, "%s", names[regno].name);
596 (*info->fprintf_func) (info->stream, "%d", val);
601 val = fetch_arg (buffer, place, 3, info);
602 /* 0 means 8, except for the bkpt instruction... */
603 if (val == 0 && d[1] != 's')
605 (*info->fprintf_func) (info->stream, "#%d", val);
609 val = fetch_arg (buffer, place, 3, info);
613 (*info->fprintf_func) (info->stream, "#%d", val);
619 static char *const scalefactor_name[] = { "<<", ">>" };
620 val = fetch_arg (buffer, place, 1, info);
621 (*info->fprintf_func) (info->stream, scalefactor_name[val]);
625 val = fetch_arg (buffer, place, 8, info);
628 (*info->fprintf_func) (info->stream, "#%d", val);
633 val = fetch_arg (buffer, place, 4, info);
634 (*info->fprintf_func) (info->stream, "#%d", val);
638 (*info->fprintf_func) (info->stream, "%s",
639 reg_names[fetch_arg (buffer, place, 3, info)]);
643 (*info->fprintf_func)
645 reg_names[fetch_arg (buffer, place, 3, info) + 010]);
649 (*info->fprintf_func)
651 reg_names[fetch_arg (buffer, place, 4, info)]);
655 regno = fetch_arg (buffer, place, 4, info);
657 (*info->fprintf_func) (info->stream, "%s@", reg_names[regno]);
659 (*info->fprintf_func) (info->stream, "@(%s)", reg_names[regno]);
663 (*info->fprintf_func)
664 (info->stream, "%%fp%d",
665 fetch_arg (buffer, place, 3, info));
669 val = fetch_arg (buffer, place, 6, info);
671 (*info->fprintf_func) (info->stream, "%s", reg_names[val & 7]);
673 (*info->fprintf_func) (info->stream, "%d", val);
677 (*info->fprintf_func)
678 (info->stream, "%s@+",
679 reg_names[fetch_arg (buffer, place, 3, info) + 8]);
683 (*info->fprintf_func)
684 (info->stream, "%s@-",
685 reg_names[fetch_arg (buffer, place, 3, info) + 8]);
690 (*info->fprintf_func)
691 (info->stream, "{%s}",
692 reg_names[fetch_arg (buffer, place, 3, info)]);
693 else if (place == 'C')
695 val = fetch_arg (buffer, place, 7, info);
696 if (val > 63) /* This is a signed constant. */
698 (*info->fprintf_func) (info->stream, "{#%d}", val);
706 p1 = buffer + (*d == '#' ? 2 : 4);
708 val = fetch_arg (buffer, place, 4, info);
709 else if (place == 'C')
710 val = fetch_arg (buffer, place, 7, info);
711 else if (place == '8')
712 val = fetch_arg (buffer, place, 3, info);
713 else if (place == '3')
714 val = fetch_arg (buffer, place, 8, info);
715 else if (place == 'b')
717 else if (place == 'w' || place == 'W')
719 else if (place == 'l')
723 (*info->fprintf_func) (info->stream, "#%d", val);
729 else if (place == 'B')
730 disp = COERCE_SIGNED_CHAR (buffer[1]);
731 else if (place == 'w' || place == 'W')
733 else if (place == 'l' || place == 'L' || place == 'C')
735 else if (place == 'g')
737 disp = NEXTBYTE (buffer);
743 else if (place == 'c')
745 if (buffer[1] & 0x40) /* If bit six is one, long offset */
753 (*info->print_address_func) (addr + disp, info);
758 (*info->fprintf_func)
759 (info->stream, "%s@(%d)",
760 reg_names[fetch_arg (buffer, place, 3, info) + 8], val);
764 (*info->fprintf_func) (info->stream, "%s",
765 fpcr_names[fetch_arg (buffer, place, 3, info)]);
769 val = fetch_arg(buffer, place, 2, info);
770 (*info->fprintf_func) (info->stream, "%%acc%d", val);
774 val = fetch_arg(buffer, place, 1, info);
775 (*info->fprintf_func) (info->stream, "%%accext%s", val==0 ? "01" : "23");
779 val = fetch_arg(buffer, place, 2, info);
781 (*info->fprintf_func) (info->stream, "<<");
783 (*info->fprintf_func) (info->stream, ">>");
789 /* Get coprocessor ID... */
790 val = fetch_arg (buffer, 'd', 3, info);
792 if (val != 1) /* Unusual coprocessor ID? */
793 (*info->fprintf_func) (info->stream, "(cpid=%d) ", val);
822 val = fetch_arg (buffer, 'x', 6, info);
823 val = ((val & 7) << 3) + ((val >> 3) & 7);
826 val = fetch_arg (buffer, 's', 6, info);
828 /* If the <ea> is invalid for *d, then reject this match. */
829 if (!m68k_valid_ea (*d, val))
832 /* Get register number assuming address register. */
833 regno = (val & 7) + 8;
834 regname = reg_names[regno];
838 (*info->fprintf_func) (info->stream, "%s", reg_names[val]);
842 (*info->fprintf_func) (info->stream, "%s", regname);
846 (*info->fprintf_func) (info->stream, "%s@", regname);
850 (*info->fprintf_func) (info->stream, "%s@+", regname);
854 (*info->fprintf_func) (info->stream, "%s@-", regname);
859 (*info->fprintf_func) (info->stream, "%s@(%d)", regname, val);
863 p = print_indexed (regno, p, addr, info);
871 (*info->print_address_func) (val, info);
875 uval = NEXTULONG (p);
876 (*info->print_address_func) (uval, info);
881 (*info->fprintf_func) (info->stream, "%%pc@(");
882 (*info->print_address_func) (addr + val, info);
883 (*info->fprintf_func) (info->stream, ")");
887 p = print_indexed (-1, p, addr, info);
891 flt_p = 1; /* Assume it's a float... */
910 NEXTSINGLE (flval, p);
914 NEXTDOUBLE (flval, p);
918 NEXTEXTEND (flval, p);
922 flval = NEXTPACKED (p);
928 if (flt_p) /* Print a float? */
929 (*info->fprintf_func) (info->stream, "#%g", flval);
931 (*info->fprintf_func) (info->stream, "#%d", val);
939 /* If place is '/', then this is the case of the mask bit for
940 mac/emac loads. Now that the arg has been printed, grab the
941 mask bit and if set, add a '&' to the arg. */
944 val = fetch_arg (buffer, place, 1, info);
946 info->fprintf_func (info->stream, "&");
957 /* Move the pointer ahead if this point is farther ahead
962 (*info->fprintf_func) (info->stream, "#0");
967 register int newval = 0;
968 for (regno = 0; regno < 16; ++regno)
969 if (val & (0x8000 >> regno))
970 newval |= 1 << regno;
975 for (regno = 0; regno < 16; ++regno)
976 if (val & (1 << regno))
980 (*info->fprintf_func) (info->stream, "/");
982 (*info->fprintf_func) (info->stream, "%s", reg_names[regno]);
984 while (val & (1 << (regno + 1)))
986 if (regno > first_regno)
987 (*info->fprintf_func) (info->stream, "-%s",
991 else if (place == '3')
995 val = fetch_arg (buffer, place, 8, info);
998 (*info->fprintf_func) (info->stream, "#0");
1003 register int newval = 0;
1004 for (regno = 0; regno < 8; ++regno)
1005 if (val & (0x80 >> regno))
1006 newval |= 1 << regno;
1011 for (regno = 0; regno < 8; ++regno)
1012 if (val & (1 << regno))
1016 (*info->fprintf_func) (info->stream, "/");
1018 (*info->fprintf_func) (info->stream, "%%fp%d", regno);
1019 first_regno = regno;
1020 while (val & (1 << (regno + 1)))
1022 if (regno > first_regno)
1023 (*info->fprintf_func) (info->stream, "-%%fp%d", regno);
1026 else if (place == '8')
1028 /* fmoveml for FP status registers */
1029 (*info->fprintf_func) (info->stream, "%s",
1030 fpcr_names[fetch_arg (buffer, place, 3,
1047 int val = fetch_arg (buffer, place, 5, info);
1051 case 2: name = "%tt0"; break;
1052 case 3: name = "%tt1"; break;
1053 case 0x10: name = "%tc"; break;
1054 case 0x11: name = "%drp"; break;
1055 case 0x12: name = "%srp"; break;
1056 case 0x13: name = "%crp"; break;
1057 case 0x14: name = "%cal"; break;
1058 case 0x15: name = "%val"; break;
1059 case 0x16: name = "%scc"; break;
1060 case 0x17: name = "%ac"; break;
1061 case 0x18: name = "%psr"; break;
1062 case 0x19: name = "%pcsr"; break;
1066 int break_reg = ((buffer[3] >> 2) & 7);
1067 (*info->fprintf_func)
1068 (info->stream, val == 0x1c ? "%%bad%d" : "%%bac%d",
1073 (*info->fprintf_func) (info->stream, "<mmu register %d>", val);
1076 (*info->fprintf_func) (info->stream, "%s", name);
1082 int fc = fetch_arg (buffer, place, 5, info);
1084 (*info->fprintf_func) (info->stream, "%%dfc");
1086 (*info->fprintf_func) (info->stream, "%%sfc");
1088 /* xgettext:c-format */
1089 (*info->fprintf_func) (info->stream, _("<function code %d>"), fc);
1094 (*info->fprintf_func) (info->stream, "%%val");
1099 int level = fetch_arg (buffer, place, 3, info);
1100 (*info->fprintf_func) (info->stream, "%d", level);
1107 int reg = fetch_arg (buffer, place, 5, info);
1114 (*info->fprintf_func) (info->stream, "%s%s",
1115 reg_half_names[reg],
1116 is_upper ? "u" : "l");
1127 /* Check if an EA is valid for a particular code. This is required
1128 for the EMAC instructions since the type of source address determines
1129 if it is a EMAC-load instruciton if the EA is mode 2-5, otherwise it
1130 is a non-load EMAC instruction and the bits mean register Ry.
1131 A similar case exists for the movem instructions where the register
1132 mask is interpreted differently for different EAs. */
1135 m68k_valid_ea (char code, int val)
1138 #define M(n0,n1,n2,n3,n4,n5,n6,n70,n71,n72,n73,n74) \
1139 (n0 | n1 << 1 | n2 << 2 | n3 << 3 | n4 << 4 | n5 << 5 | n6 << 6 \
1140 | n70 << 7 | n71 << 8 | n72 << 9 | n73 << 10 | n74 << 11)
1145 mask = M (1,1,1,1,1,1,1,1,1,1,1,1);
1148 mask = M (0,0,1,1,1,1,1,1,1,0,0,0);
1151 mask = M (1,1,1,1,1,1,1,1,1,0,0,0);
1154 mask = M (1,0,1,1,1,1,1,1,1,1,1,1);
1157 mask = M (1,0,1,1,1,1,1,1,1,1,1,0);
1160 mask = M (0,0,1,0,0,1,1,1,1,1,1,0);
1163 mask = M (0,0,1,0,0,1,1,1,1,0,0,0);
1166 mask = M (1,0,1,1,1,1,1,1,1,0,0,0);
1169 mask = M (0,1,0,0,1,1,1,1,1,0,0,0);
1172 mask = M (1,0,1,0,0,1,1,1,1,1,1,0);
1175 mask = M (0,0,1,0,0,1,1,1,1,1,1,0);
1178 mask = M (0,0,1,0,1,1,1,1,1,1,1,0);
1181 mask = M (0,0,1,1,0,1,1,1,1,0,0,0);
1184 mask = M (1,1,1,1,1,0,0,0,0,0,0,0);
1187 mask = M (0,0,0,0,0,1,0,0,0,1,0,0);
1190 mask = M (0,0,0,0,0,0,1,1,1,0,1,1);
1193 mask = M (1,1,1,1,1,1,0,0,0,0,0,0);
1196 mask = M (1,0,1,1,1,1,0,0,0,0,0,0);
1199 mask = M (1,0,1,1,1,1,0,1,1,0,0,0);
1202 mask = M (1,0,1,1,1,1,0,0,0,1,0,0);
1205 mask = M (0,0,1,1,1,1,0,0,0,1,0,0);
1208 mask = M (0,0,1,0,0,1,0,0,0,0,0,0);
1211 mask = M (0,0,1,0,0,1,0,0,0,1,0,0);
1214 mask = M (0,0,1,1,1,1,0,0,0,0,0,0);
1221 mode = (val >> 3) & 7;
1224 return (mask & (1 << mode)) != 0;
1227 /* Fetch BITS bits from a position in the instruction specified by CODE.
1228 CODE is a "place to put an argument", or 'x' for a destination
1229 that is a general address (mode and register).
1230 BUFFER contains the instruction. */
1233 fetch_arg (buffer, code, bits, info)
1234 unsigned char *buffer;
1237 disassemble_info *info;
1243 case '/': /* MAC/EMAC mask bit. */
1244 val = buffer[3] >> 5;
1247 case 'G': /* EMAC ACC load. */
1248 val = ((buffer[3] >> 3) & 0x2) | ((~buffer[1] >> 7) & 0x1);
1251 case 'H': /* EMAC ACC !load. */
1252 val = ((buffer[3] >> 3) & 0x2) | ((buffer[1] >> 7) & 0x1);
1255 case ']': /* EMAC ACCEXT bit. */
1256 val = buffer[0] >> 2;
1259 case 'I': /* MAC/EMAC scale factor. */
1260 val = buffer[2] >> 1;
1263 case 'F': /* EMAC ACCx. */
1264 val = buffer[0] >> 1;
1275 case 'd': /* Destination, for register or quick. */
1276 val = (buffer[0] << 8) + buffer[1];
1280 case 'x': /* Destination, for general arg */
1281 val = (buffer[0] << 8) + buffer[1];
1286 FETCH_DATA (info, buffer + 3);
1287 val = (buffer[3] >> 4);
1291 FETCH_DATA (info, buffer + 3);
1296 FETCH_DATA (info, buffer + 3);
1297 val = (buffer[2] << 8) + buffer[3];
1302 FETCH_DATA (info, buffer + 3);
1303 val = (buffer[2] << 8) + buffer[3];
1309 FETCH_DATA (info, buffer + 3);
1310 val = (buffer[2] << 8) + buffer[3];
1314 FETCH_DATA (info, buffer + 5);
1315 val = (buffer[4] << 8) + buffer[5];
1320 FETCH_DATA (info, buffer + 5);
1321 val = (buffer[4] << 8) + buffer[5];
1326 FETCH_DATA (info, buffer + 5);
1327 val = (buffer[4] << 8) + buffer[5];
1331 FETCH_DATA (info, buffer + 3);
1332 val = (buffer[2] << 8) + buffer[3];
1337 FETCH_DATA (info, buffer + 3);
1338 val = (buffer[2] << 8) + buffer[3];
1343 FETCH_DATA (info, buffer + 3);
1344 val = (buffer[2] << 8) + buffer[3];
1349 val = (buffer[1] >> 6);
1353 val = (buffer[1] & 0x40 ? 0x8 : 0)
1354 | ((buffer[0] >> 1) & 0x7)
1355 | (buffer[3] & 0x80 ? 0x10 : 0);
1359 val = (buffer[1] & 0x40 ? 0x8 : 0) | ((buffer[0] >> 1) & 0x7);
1363 val = (buffer[2] >> 4) | (buffer[3] & 0x80 ? 0x10 : 0);
1367 val = (buffer[1] & 0xf) | (buffer[3] & 0x40 ? 0x10 : 0);
1371 val = (buffer[3] & 0xf) | (buffer[3] & 0x40 ? 0x10 : 0);
1375 val = buffer[2] >> 2;
1407 /* Print an indexed argument. The base register is BASEREG (-1 for pc).
1408 P points to extension word, in buffer.
1409 ADDR is the nominal core address of that extension word. */
1411 static unsigned char *
1412 print_indexed (basereg, p, addr, info)
1416 disassemble_info *info;
1419 static char *const scales[] = { "", ":2", ":4", ":8" };
1425 word = NEXTWORD (p);
1427 /* Generate the text for the index register.
1428 Where this will be output is not yet determined. */
1429 sprintf (buf, "%s:%c%s",
1430 reg_names[(word >> 12) & 0xf],
1431 (word & 0x800) ? 'l' : 'w',
1432 scales[(word >> 9) & 3]);
1434 /* Handle the 68000 style of indexing. */
1436 if ((word & 0x100) == 0)
1438 base_disp = word & 0xff;
1439 if ((base_disp & 0x80) != 0)
1443 print_base (basereg, base_disp, info);
1444 (*info->fprintf_func) (info->stream, ",%s)", buf);
1448 /* Handle the generalized kind. */
1449 /* First, compute the displacement to add to the base register. */
1461 switch ((word >> 4) & 3)
1464 base_disp = NEXTWORD (p);
1467 base_disp = NEXTLONG (p);
1472 /* Handle single-level case (not indirect) */
1474 if ((word & 7) == 0)
1476 print_base (basereg, base_disp, info);
1478 (*info->fprintf_func) (info->stream, ",%s", buf);
1479 (*info->fprintf_func) (info->stream, ")");
1483 /* Two level. Compute displacement to add after indirection. */
1489 outer_disp = NEXTWORD (p);
1492 outer_disp = NEXTLONG (p);
1495 print_base (basereg, base_disp, info);
1496 if ((word & 4) == 0 && buf[0] != '\0')
1498 (*info->fprintf_func) (info->stream, ",%s", buf);
1501 sprintf_vma (vmabuf, outer_disp);
1502 (*info->fprintf_func) (info->stream, ")@(%s", vmabuf);
1504 (*info->fprintf_func) (info->stream, ",%s", buf);
1505 (*info->fprintf_func) (info->stream, ")");
1510 /* Print a base register REGNO and displacement DISP, on INFO->STREAM.
1511 REGNO = -1 for pc, -2 for none (suppressed). */
1514 print_base (regno, disp, info)
1517 disassemble_info *info;
1521 (*info->fprintf_func) (info->stream, "%%pc@(");
1522 (*info->print_address_func) (disp, info);
1529 (*info->fprintf_func) (info->stream, "@(");
1530 else if (regno == -3)
1531 (*info->fprintf_func) (info->stream, "%%zpc@(");
1533 (*info->fprintf_func) (info->stream, "%s@(", reg_names[regno]);
1535 sprintf_vma (buf, disp);
1536 (*info->fprintf_func) (info->stream, "%s", buf);