1 /* Print Motorola 68k instructions.
2 Copyright (C) 1986-2016 Free Software Foundation, Inc.
4 This file is part of the GNU opcodes library.
6 This library is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 3, or (at your option)
11 It is distributed in the hope that it will be useful, but WITHOUT
12 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
13 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
14 License for more details.
16 You should have received a copy of the GNU General Public License
17 along with this program; if not, write to the Free Software
18 Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
19 MA 02110-1301, USA. */
23 #include "floatformat.h"
24 #include "libiberty.h"
27 #include "opcode/m68k.h"
29 /* Local function prototypes. */
31 const char * const fpcr_names[] =
33 "", "%fpiar", "%fpsr", "%fpiar/%fpsr", "%fpcr",
34 "%fpiar/%fpcr", "%fpsr/%fpcr", "%fpiar/%fpsr/%fpcr"
37 static char *const reg_names[] =
39 "%d0", "%d1", "%d2", "%d3", "%d4", "%d5", "%d6", "%d7",
40 "%a0", "%a1", "%a2", "%a3", "%a4", "%a5", "%fp", "%sp",
44 /* Name of register halves for MAC/EMAC.
45 Seperate from reg_names since 'spu', 'fpl' look weird. */
46 static char *const reg_half_names[] =
48 "%d0", "%d1", "%d2", "%d3", "%d4", "%d5", "%d6", "%d7",
49 "%a0", "%a1", "%a2", "%a3", "%a4", "%a5", "%a6", "%a7",
53 /* Sign-extend an (unsigned char). */
55 #define COERCE_SIGNED_CHAR(ch) ((signed char) (ch))
57 #define COERCE_SIGNED_CHAR(ch) ((int) (((ch) ^ 0x80) & 0xFF) - 128)
60 /* Get a 1 byte signed integer. */
61 #define NEXTBYTE(p, val) \
65 if (!FETCH_DATA (info, p)) \
67 val = COERCE_SIGNED_CHAR (p[-1]); \
71 /* Get a 2 byte signed integer. */
72 #define COERCE16(x) ((int) (((x) ^ 0x8000) - 0x8000))
74 #define NEXTWORD(p, val, ret_val) \
78 if (!FETCH_DATA (info, p)) \
80 val = COERCE16 ((p[-2] << 8) + p[-1]); \
84 /* Get a 4 byte signed integer. */
85 #define COERCE32(x) ((bfd_signed_vma) ((x) ^ 0x80000000) - 0x80000000)
87 #define NEXTLONG(p, val, ret_val) \
91 if (!FETCH_DATA (info, p)) \
93 val = COERCE32 ((((((p[-4] << 8) + p[-3]) << 8) + p[-2]) << 8) + p[-1]); \
97 /* Get a 4 byte unsigned integer. */
98 #define NEXTULONG(p, val) \
102 if (!FETCH_DATA (info, p)) \
104 val = (unsigned int) ((((((p[-4] << 8) + p[-3]) << 8) + p[-2]) << 8) + p[-1]); \
108 /* Get a single precision float. */
109 #define NEXTSINGLE(val, p) \
113 if (!FETCH_DATA (info, p)) \
115 floatformat_to_double (& floatformat_ieee_single_big, \
116 (char *) p - 4, & val); \
120 /* Get a double precision float. */
121 #define NEXTDOUBLE(val, p) \
125 if (!FETCH_DATA (info, p)) \
127 floatformat_to_double (& floatformat_ieee_double_big, \
128 (char *) p - 8, & val); \
132 /* Get an extended precision float. */
133 #define NEXTEXTEND(val, p) \
137 if (!FETCH_DATA (info, p)) \
139 floatformat_to_double (& floatformat_m68881_ext, \
140 (char *) p - 12, & val); \
144 /* Need a function to convert from packed to double
145 precision. Actually, it's easier to print a
146 packed number than a double anyway, so maybe
147 there should be a special case to handle this... */
148 #define NEXTPACKED(p, val) \
152 if (!FETCH_DATA (info, p)) \
159 /* Maximum length of an instruction. */
164 /* Points to first byte not fetched. */
165 bfd_byte *max_fetched;
166 bfd_byte the_buffer[MAXLEN];
170 /* Make sure that bytes from INFO->PRIVATE_DATA->BUFFER (inclusive)
171 to ADDR (exclusive) are valid. Returns 1 for success, 0 on error. */
172 #define FETCH_DATA(info, addr) \
173 ((addr) <= ((struct private *) (info->private_data))->max_fetched \
174 ? 1 : fetch_data ((info), (addr)))
177 fetch_data (struct disassemble_info *info, bfd_byte *addr)
180 struct private *priv = (struct private *)info->private_data;
181 bfd_vma start = priv->insn_start + (priv->max_fetched - priv->the_buffer);
183 status = (*info->read_memory_func) (start,
185 addr - priv->max_fetched,
189 (*info->memory_error_func) (status, start, info);
193 priv->max_fetched = addr;
197 /* This function is used to print to the bit-bucket. */
199 dummy_printer (FILE *file ATTRIBUTE_UNUSED,
200 const char *format ATTRIBUTE_UNUSED,
207 dummy_print_address (bfd_vma vma ATTRIBUTE_UNUSED,
208 struct disassemble_info *info ATTRIBUTE_UNUSED)
212 /* Fetch BITS bits from a position in the instruction specified by CODE.
213 CODE is a "place to put an argument", or 'x' for a destination
214 that is a general address (mode and register).
215 BUFFER contains the instruction.
216 Returns -1 on failure. */
219 fetch_arg (unsigned char *buffer,
222 disassemble_info *info)
228 case '/': /* MAC/EMAC mask bit. */
229 val = buffer[3] >> 5;
232 case 'G': /* EMAC ACC load. */
233 val = ((buffer[3] >> 3) & 0x2) | ((~buffer[1] >> 7) & 0x1);
236 case 'H': /* EMAC ACC !load. */
237 val = ((buffer[3] >> 3) & 0x2) | ((buffer[1] >> 7) & 0x1);
240 case ']': /* EMAC ACCEXT bit. */
241 val = buffer[0] >> 2;
244 case 'I': /* MAC/EMAC scale factor. */
245 val = buffer[2] >> 1;
248 case 'F': /* EMAC ACCx. */
249 val = buffer[0] >> 1;
260 case 'd': /* Destination, for register or quick. */
261 val = (buffer[0] << 8) + buffer[1];
265 case 'x': /* Destination, for general arg. */
266 val = (buffer[0] << 8) + buffer[1];
271 if (! FETCH_DATA (info, buffer + 3))
273 val = (buffer[3] >> 4);
277 if (! FETCH_DATA (info, buffer + 3))
283 if (! FETCH_DATA (info, buffer + 3))
285 val = (buffer[2] << 8) + buffer[3];
290 if (! FETCH_DATA (info, buffer + 3))
292 val = (buffer[2] << 8) + buffer[3];
298 if (! FETCH_DATA (info, buffer + 3))
300 val = (buffer[2] << 8) + buffer[3];
304 if (! FETCH_DATA (info, buffer + 5))
306 val = (buffer[4] << 8) + buffer[5];
311 if (! FETCH_DATA (info, buffer + 5))
313 val = (buffer[4] << 8) + buffer[5];
318 if (! FETCH_DATA (info, buffer + 5))
320 val = (buffer[4] << 8) + buffer[5];
324 if (! FETCH_DATA (info, buffer + 3))
326 val = (buffer[2] << 8) + buffer[3];
331 if (! FETCH_DATA (info, buffer + 3))
333 val = (buffer[2] << 8) + buffer[3];
338 if (! FETCH_DATA (info, buffer + 3))
340 val = (buffer[2] << 8) + buffer[3];
345 val = (buffer[1] >> 6);
349 if (! FETCH_DATA (info, buffer + 3))
351 val = (buffer[2] >> 1);
355 val = (buffer[1] & 0x40 ? 0x8 : 0)
356 | ((buffer[0] >> 1) & 0x7)
357 | (buffer[3] & 0x80 ? 0x10 : 0);
361 val = (buffer[1] & 0x40 ? 0x8 : 0) | ((buffer[0] >> 1) & 0x7);
365 val = (buffer[2] >> 4) | (buffer[3] & 0x80 ? 0x10 : 0);
369 val = (buffer[1] & 0xf) | (buffer[3] & 0x40 ? 0x10 : 0);
373 val = (buffer[3] & 0xf) | (buffer[3] & 0x40 ? 0x10 : 0);
377 val = buffer[2] >> 2;
384 /* bits is never too big. */
385 return val & ((1 << bits) - 1);
388 /* Check if an EA is valid for a particular code. This is required
389 for the EMAC instructions since the type of source address determines
390 if it is a EMAC-load instruciton if the EA is mode 2-5, otherwise it
391 is a non-load EMAC instruction and the bits mean register Ry.
392 A similar case exists for the movem instructions where the register
393 mask is interpreted differently for different EAs. */
396 m68k_valid_ea (char code, int val)
399 #define M(n0,n1,n2,n3,n4,n5,n6,n70,n71,n72,n73,n74) \
400 (n0 | n1 << 1 | n2 << 2 | n3 << 3 | n4 << 4 | n5 << 5 | n6 << 6 \
401 | n70 << 7 | n71 << 8 | n72 << 9 | n73 << 10 | n74 << 11)
406 mask = M (1,1,1,1,1,1,1,1,1,1,1,1);
409 mask = M (0,0,1,1,1,1,1,1,1,0,0,0);
412 mask = M (1,1,1,1,1,1,1,1,1,0,0,0);
415 mask = M (1,0,1,1,1,1,1,1,1,1,1,1);
418 mask = M (1,0,1,1,1,1,1,1,1,1,1,0);
421 mask = M (0,0,1,0,0,1,1,1,1,1,1,0);
424 mask = M (0,0,1,0,0,1,1,1,1,0,0,0);
427 mask = M (1,0,1,1,1,1,1,1,1,0,0,0);
430 mask = M (1,0,1,0,0,1,1,1,1,0,0,0);
433 mask = M (1,0,1,0,0,1,1,1,1,1,1,0);
436 mask = M (0,0,1,0,0,1,1,1,1,1,1,0);
439 mask = M (0,0,1,0,1,1,1,1,1,0,0,0);
442 mask = M (0,0,1,1,0,1,1,1,1,1,1,0);
445 mask = M (1,1,1,1,1,0,0,0,0,0,0,0);
448 mask = M (0,0,0,0,0,1,0,0,0,1,0,0);
451 mask = M (0,0,0,0,0,0,1,1,1,0,1,1);
454 mask = M (1,1,1,1,1,1,0,0,0,0,0,0);
457 mask = M (1,0,1,1,1,1,0,0,0,0,0,0);
460 mask = M (1,0,1,1,1,1,0,1,1,0,0,0);
463 mask = M (1,0,1,1,1,1,0,0,0,1,0,0);
466 mask = M (0,0,1,1,1,1,0,0,0,1,0,0);
469 mask = M (0,0,1,0,0,1,0,0,0,0,0,0);
472 mask = M (0,0,1,0,0,1,0,0,0,1,0,0);
475 mask = M (0,0,1,1,1,1,0,0,0,0,0,0);
482 mode = (val >> 3) & 7;
485 return (mask & (1 << mode)) != 0;
488 /* Print a base register REGNO and displacement DISP, on INFO->STREAM.
489 REGNO = -1 for pc, -2 for none (suppressed). */
492 print_base (int regno, bfd_vma disp, disassemble_info *info)
496 (*info->fprintf_func) (info->stream, "%%pc@(");
497 (*info->print_address_func) (disp, info);
504 (*info->fprintf_func) (info->stream, "@(");
505 else if (regno == -3)
506 (*info->fprintf_func) (info->stream, "%%zpc@(");
508 (*info->fprintf_func) (info->stream, "%s@(", reg_names[regno]);
510 sprintf_vma (buf, disp);
511 (*info->fprintf_func) (info->stream, "%s", buf);
515 /* Print an indexed argument. The base register is BASEREG (-1 for pc).
516 P points to extension word, in buffer.
517 ADDR is the nominal core address of that extension word.
518 Returns NULL upon error. */
520 static unsigned char *
521 print_indexed (int basereg,
524 disassemble_info *info)
527 static char *const scales[] = { "", ":2", ":4", ":8" };
533 NEXTWORD (p, word, NULL);
535 /* Generate the text for the index register.
536 Where this will be output is not yet determined. */
537 sprintf (buf, "%s:%c%s",
538 reg_names[(word >> 12) & 0xf],
539 (word & 0x800) ? 'l' : 'w',
540 scales[(word >> 9) & 3]);
542 /* Handle the 68000 style of indexing. */
544 if ((word & 0x100) == 0)
546 base_disp = word & 0xff;
547 if ((base_disp & 0x80) != 0)
551 print_base (basereg, base_disp, info);
552 (*info->fprintf_func) (info->stream, ",%s)", buf);
556 /* Handle the generalized kind. */
557 /* First, compute the displacement to add to the base register. */
568 switch ((word >> 4) & 3)
571 NEXTWORD (p, base_disp, NULL);
574 NEXTLONG (p, base_disp, NULL);
579 /* Handle single-level case (not indirect). */
582 print_base (basereg, base_disp, info);
584 (*info->fprintf_func) (info->stream, ",%s", buf);
585 (*info->fprintf_func) (info->stream, ")");
589 /* Two level. Compute displacement to add after indirection. */
594 NEXTWORD (p, outer_disp, NULL);
597 NEXTLONG (p, outer_disp, NULL);
600 print_base (basereg, base_disp, info);
601 if ((word & 4) == 0 && buf[0] != '\0')
603 (*info->fprintf_func) (info->stream, ",%s", buf);
606 sprintf_vma (vmabuf, outer_disp);
607 (*info->fprintf_func) (info->stream, ")@(%s", vmabuf);
609 (*info->fprintf_func) (info->stream, ",%s", buf);
610 (*info->fprintf_func) (info->stream, ")");
615 #define FETCH_ARG(size, val) \
618 val = fetch_arg (buffer, place, size, info); \
624 /* Returns number of bytes "eaten" by the operand, or
625 return -1 if an invalid operand was found, or -2 if
626 an opcode tabe error was found or -3 to simply abort.
627 ADDR is the pc for this arg to be relative to. */
630 print_insn_arg (const char *d,
631 unsigned char *buffer,
634 disassemble_info *info)
638 unsigned char *p = p0;
649 case 'c': /* Cache identifier. */
651 static char *const cacheFieldName[] = { "nc", "dc", "ic", "bc" };
653 (*info->fprintf_func) (info->stream, "%s", cacheFieldName[val]);
657 case 'a': /* Address register indirect only. Cf. case '+'. */
660 (*info->fprintf_func) (info->stream, "%s@", reg_names[val + 8]);
664 case '_': /* 32-bit absolute address for move16. */
667 (*info->print_address_func) (uval, info);
672 (*info->fprintf_func) (info->stream, "%%ccr");
676 (*info->fprintf_func) (info->stream, "%%sr");
680 (*info->fprintf_func) (info->stream, "%%usp");
684 (*info->fprintf_func) (info->stream, "%%acc");
688 (*info->fprintf_func) (info->stream, "%%macsr");
692 (*info->fprintf_func) (info->stream, "%%mask");
697 /* FIXME: There's a problem here, different m68k processors call the
698 same address different names. The tables below try to get it right
699 using info->mach, but only for v4e. */
700 struct regname { char * name; int value; };
701 static const struct regname names[] =
703 {"%sfc", 0x000}, {"%dfc", 0x001}, {"%cacr", 0x002},
704 {"%tc", 0x003}, {"%itt0",0x004}, {"%itt1", 0x005},
705 {"%dtt0",0x006}, {"%dtt1",0x007}, {"%buscr",0x008},
706 {"%rgpiobar", 0x009}, {"%acr4",0x00c},
707 {"%acr5",0x00d}, {"%acr6",0x00e}, {"%acr7", 0x00f},
708 {"%usp", 0x800}, {"%vbr", 0x801}, {"%caar", 0x802},
709 {"%msp", 0x803}, {"%isp", 0x804},
711 /* Reg c04 is sometimes called flashbar or rambar.
712 Reg c05 is also sometimes called rambar. */
713 {"%rambar0", 0xc04}, {"%rambar1", 0xc05},
715 /* reg c0e is sometimes called mbar2 or secmbar.
716 reg c0f is sometimes called mbar. */
717 {"%mbar0", 0xc0e}, {"%mbar1", 0xc0f},
719 /* Should we be calling this psr like we do in case 'Y'? */
722 {"%urp", 0x806}, {"%srp", 0x807}, {"%pcr", 0x808},
724 /* Fido added these. */
725 {"%cac", 0xffe}, {"%mbo", 0xfff}
727 /* Alternate names for v4e (MCF5407/5445x/MCF547x/MCF548x), at least. */
728 static const struct regname names_v4e[] =
730 {"%asid",0x003}, {"%acr0",0x004}, {"%acr1",0x005},
731 {"%acr2",0x006}, {"%acr3",0x007}, {"%mmubar",0x008},
733 unsigned int arch_mask;
735 arch_mask = bfd_m68k_mach_to_features (info->mach);
737 if (arch_mask & (mcfisa_b | mcfisa_c))
739 for (regno = ARRAY_SIZE (names_v4e); --regno >= 0;)
740 if (names_v4e[regno].value == val)
742 (*info->fprintf_func) (info->stream, "%s", names_v4e[regno].name);
748 for (regno = ARRAY_SIZE (names) - 1; regno >= 0; regno--)
749 if (names[regno].value == val)
751 (*info->fprintf_func) (info->stream, "%s", names[regno].name);
755 (*info->fprintf_func) (info->stream, "0x%x", val);
761 /* 0 means 8, except for the bkpt instruction... */
762 if (val == 0 && d[1] != 's')
764 (*info->fprintf_func) (info->stream, "#%d", val);
772 (*info->fprintf_func) (info->stream, "#%d", val);
777 (*info->fprintf_func) (info->stream, "#%d", val+1);
782 (*info->fprintf_func) (info->stream, "#%d", val);
788 static char *const scalefactor_name[] = { "<<", ">>" };
791 (*info->fprintf_func) (info->stream, "%s", scalefactor_name[val]);
798 (*info->fprintf_func) (info->stream, "#%d", val);
804 (*info->fprintf_func) (info->stream, "#%d", val);
809 (*info->fprintf_func) (info->stream, "%s", reg_names[val]);
814 (*info->fprintf_func) (info->stream, "%s", reg_names[val + 010]);
819 (*info->fprintf_func) (info->stream, "%s", reg_names[val]);
823 FETCH_ARG (4, regno);
825 (*info->fprintf_func) (info->stream, "%s@", reg_names[regno]);
827 (*info->fprintf_func) (info->stream, "@(%s)", reg_names[regno]);
832 (*info->fprintf_func) (info->stream, "%%fp%d", val);
838 (*info->fprintf_func) (info->stream, "%s", reg_names[val & 7]);
840 (*info->fprintf_func) (info->stream, "%d", val);
845 (*info->fprintf_func) (info->stream, "%s@+", reg_names[val + 8]);
850 (*info->fprintf_func) (info->stream, "%s@-", reg_names[val + 8]);
857 (*info->fprintf_func) (info->stream, "{%s}", reg_names[val]);
859 else if (place == 'C')
862 if (val > 63) /* This is a signed constant. */
864 (*info->fprintf_func) (info->stream, "{#%d}", val);
872 p1 = buffer + (*d == '#' ? 2 : 4);
875 else if (place == 'C')
877 else if (place == '8')
879 else if (place == '3')
881 else if (place == 'b')
883 else if (place == 'w' || place == 'W')
884 NEXTWORD (p1, val, -3);
885 else if (place == 'l')
886 NEXTLONG (p1, val, -3);
890 (*info->fprintf_func) (info->stream, "#%d", val);
896 else if (place == 'B')
897 disp = COERCE_SIGNED_CHAR (buffer[1]);
898 else if (place == 'w' || place == 'W')
899 NEXTWORD (p, disp, -3);
900 else if (place == 'l' || place == 'L' || place == 'C')
901 NEXTLONG (p, disp, -3);
902 else if (place == 'g')
904 NEXTBYTE (buffer, disp);
906 NEXTWORD (p, disp, -3);
908 NEXTLONG (p, disp, -3);
910 else if (place == 'c')
912 if (buffer[1] & 0x40) /* If bit six is one, long offset. */
913 NEXTLONG (p, disp, -3);
915 NEXTWORD (p, disp, -3);
920 (*info->print_address_func) (addr + disp, info);
927 NEXTWORD (p, val, -3);
929 (*info->fprintf_func) (info->stream, "%s@(%d)", reg_names[val1 + 8], val);
935 (*info->fprintf_func) (info->stream, "%s", fpcr_names[val]);
940 (*info->fprintf_func) (info->stream, "%%acc%d", val);
945 (*info->fprintf_func) (info->stream, "%%accext%s", val == 0 ? "01" : "23");
951 (*info->fprintf_func) (info->stream, "<<");
953 (*info->fprintf_func) (info->stream, ">>");
959 /* Get coprocessor ID... */
960 val = fetch_arg (buffer, 'd', 3, info);
963 if (val != 1) /* Unusual coprocessor ID? */
964 (*info->fprintf_func) (info->stream, "(cpid=%d) ", val);
993 val = fetch_arg (buffer, 'x', 6, info);
996 val = ((val & 7) << 3) + ((val >> 3) & 7);
1000 val = fetch_arg (buffer, 's', 6, info);
1005 /* If the <ea> is invalid for *d, then reject this match. */
1006 if (!m68k_valid_ea (*d, val))
1009 /* Get register number assuming address register. */
1010 regno = (val & 7) + 8;
1011 regname = reg_names[regno];
1015 (*info->fprintf_func) (info->stream, "%s", reg_names[val]);
1019 (*info->fprintf_func) (info->stream, "%s", regname);
1023 (*info->fprintf_func) (info->stream, "%s@", regname);
1027 (*info->fprintf_func) (info->stream, "%s@+", regname);
1031 (*info->fprintf_func) (info->stream, "%s@-", regname);
1035 NEXTWORD (p, val, -3);
1036 (*info->fprintf_func) (info->stream, "%s@(%d)", regname, val);
1040 p = print_indexed (regno, p, addr, info);
1049 NEXTWORD (p, val, -3);
1050 (*info->print_address_func) (val, info);
1054 NEXTULONG (p, uval);
1055 (*info->print_address_func) (uval, info);
1059 NEXTWORD (p, val, -3);
1060 (*info->fprintf_func) (info->stream, "%%pc@(");
1061 (*info->print_address_func) (addr + val, info);
1062 (*info->fprintf_func) (info->stream, ")");
1066 p = print_indexed (-1, p, addr, info);
1072 flt_p = 1; /* Assume it's a float... */
1081 NEXTWORD (p, val, -3);
1086 NEXTLONG (p, val, -3);
1091 NEXTSINGLE (flval, p);
1095 NEXTDOUBLE (flval, p);
1099 NEXTEXTEND (flval, p);
1103 NEXTPACKED (p, flval);
1109 if (flt_p) /* Print a float? */
1110 (*info->fprintf_func) (info->stream, "#0e%g", flval);
1112 (*info->fprintf_func) (info->stream, "#%d", val);
1120 /* If place is '/', then this is the case of the mask bit for
1121 mac/emac loads. Now that the arg has been printed, grab the
1122 mask bit and if set, add a '&' to the arg. */
1127 info->fprintf_func (info->stream, "&");
1137 NEXTWORD (p1, val, -3);
1138 /* Move the pointer ahead if this point is farther ahead
1140 p = p1 > p ? p1 : p;
1143 (*info->fprintf_func) (info->stream, "#0");
1150 for (regno = 0; regno < 16; ++regno)
1151 if (val & (0x8000 >> regno))
1152 newval |= 1 << regno;
1157 for (regno = 0; regno < 16; ++regno)
1158 if (val & (1 << regno))
1163 (*info->fprintf_func) (info->stream, "/");
1165 (*info->fprintf_func) (info->stream, "%s", reg_names[regno]);
1166 first_regno = regno;
1167 while (val & (1 << (regno + 1)))
1169 if (regno > first_regno)
1170 (*info->fprintf_func) (info->stream, "-%s",
1174 else if (place == '3')
1176 /* `fmovem' insn. */
1182 (*info->fprintf_func) (info->stream, "#0");
1189 for (regno = 0; regno < 8; ++regno)
1190 if (val & (0x80 >> regno))
1191 newval |= 1 << regno;
1196 for (regno = 0; regno < 8; ++regno)
1197 if (val & (1 << regno))
1201 (*info->fprintf_func) (info->stream, "/");
1203 (*info->fprintf_func) (info->stream, "%%fp%d", regno);
1204 first_regno = regno;
1205 while (val & (1 << (regno + 1)))
1207 if (regno > first_regno)
1208 (*info->fprintf_func) (info->stream, "-%%fp%d", regno);
1211 else if (place == '8')
1214 /* fmoveml for FP status registers. */
1215 (*info->fprintf_func) (info->stream, "%s", fpcr_names[val]);
1236 case 2: name = "%tt0"; break;
1237 case 3: name = "%tt1"; break;
1238 case 0x10: name = "%tc"; break;
1239 case 0x11: name = "%drp"; break;
1240 case 0x12: name = "%srp"; break;
1241 case 0x13: name = "%crp"; break;
1242 case 0x14: name = "%cal"; break;
1243 case 0x15: name = "%val"; break;
1244 case 0x16: name = "%scc"; break;
1245 case 0x17: name = "%ac"; break;
1246 case 0x18: name = "%psr"; break;
1247 case 0x19: name = "%pcsr"; break;
1251 int break_reg = ((buffer[3] >> 2) & 7);
1253 (*info->fprintf_func)
1254 (info->stream, val == 0x1c ? "%%bad%d" : "%%bac%d",
1259 (*info->fprintf_func) (info->stream, "<mmu register %d>", val);
1262 (*info->fprintf_func) (info->stream, "%s", name);
1272 (*info->fprintf_func) (info->stream, "%%dfc");
1274 (*info->fprintf_func) (info->stream, "%%sfc");
1276 /* xgettext:c-format */
1277 (*info->fprintf_func) (info->stream, _("<function code %d>"), fc);
1282 (*info->fprintf_func) (info->stream, "%%val");
1289 FETCH_ARG (3, level);
1290 (*info->fprintf_func) (info->stream, "%d", level);
1305 (*info->fprintf_func) (info->stream, "%s%s",
1306 reg_half_names[reg],
1307 is_upper ? "u" : "l");
1318 /* Try to match the current instruction to best and if so, return the
1319 number of bytes consumed from the instruction stream, else zero. */
1322 match_insn_m68k (bfd_vma memaddr,
1323 disassemble_info * info,
1324 const struct m68k_opcode * best)
1326 unsigned char *save_p;
1329 const char *args = best->args;
1331 struct private *priv = (struct private *) info->private_data;
1332 bfd_byte *buffer = priv->the_buffer;
1333 fprintf_ftype save_printer = info->fprintf_func;
1334 void (* save_print_address) (bfd_vma, struct disassemble_info *)
1335 = info->print_address_func;
1340 /* Point at first word of argument data,
1341 and at descriptor for first argument. */
1344 /* Figure out how long the fixed-size portion of the instruction is.
1345 The only place this is stored in the opcode table is
1346 in the arguments--look for arguments which specify fields in the 2nd
1347 or 3rd words of the instruction. */
1348 for (d = args; *d; d += 2)
1350 /* I don't think it is necessary to be checking d[0] here;
1351 I suspect all this could be moved to the case statement below. */
1354 if (d[1] == 'l' && p - buffer < 6)
1356 else if (p - buffer < 4 && d[1] != 'C' && d[1] != '8')
1360 if ((d[0] == 'L' || d[0] == 'l') && d[1] == 'w' && p - buffer < 4)
1386 /* pflusha is an exceptions. It takes no arguments but is two words
1387 long. Recognize it by looking at the lower 16 bits of the mask. */
1388 if (p - buffer < 4 && (best->match & 0xFFFF) != 0)
1391 /* lpstop is another exception. It takes a one word argument but is
1392 three words long. */
1394 && (best->match & 0xffff) == 0xffff
1398 /* Copy the one word argument into the usual location for a one
1399 word argument, to simplify printing it. We can get away with
1400 this because we know exactly what the second word is, and we
1401 aren't going to print anything based on it. */
1403 FETCH_DATA (info, p);
1404 buffer[2] = buffer[4];
1405 buffer[3] = buffer[5];
1408 FETCH_DATA (info, p);
1411 info->print_address_func = dummy_print_address;
1412 info->fprintf_func = (fprintf_ftype) dummy_printer;
1414 /* We scan the operands twice. The first time we don't print anything,
1415 but look for errors. */
1416 for (d = args; *d; d += 2)
1418 int eaten = print_insn_arg (d, buffer, p, memaddr + (p - buffer), info);
1422 else if (eaten == -1 || eaten == -3)
1424 info->fprintf_func = save_printer;
1425 info->print_address_func = save_print_address;
1430 /* We must restore the print functions before trying to print the
1432 info->fprintf_func = save_printer;
1433 info->print_address_func = save_print_address;
1434 info->fprintf_func (info->stream,
1435 /* xgettext:c-format */
1436 _("<internal error in opcode table: %s %s>\n"),
1437 best->name, best->args);
1443 info->fprintf_func = save_printer;
1444 info->print_address_func = save_print_address;
1448 info->fprintf_func (info->stream, "%s", best->name);
1451 info->fprintf_func (info->stream, " ");
1455 p += print_insn_arg (d, buffer, p, memaddr + (p - buffer), info);
1458 if (*d && *(d - 2) != 'I' && *d != 'k')
1459 info->fprintf_func (info->stream, ",");
1465 /* Try to interpret the instruction at address MEMADDR as one that
1466 can execute on a processor with the features given by ARCH_MASK.
1467 If successful, print the instruction to INFO->STREAM and return
1468 its length in bytes. Return 0 otherwise. */
1471 m68k_scan_mask (bfd_vma memaddr, disassemble_info *info,
1472 unsigned int arch_mask)
1476 static const struct m68k_opcode **opcodes[16];
1477 static int numopcodes[16];
1481 struct private *priv = (struct private *) info->private_data;
1482 bfd_byte *buffer = priv->the_buffer;
1486 /* Speed up the matching by sorting the opcode
1487 table on the upper four bits of the opcode. */
1488 const struct m68k_opcode **opc_pointer[16];
1490 /* First count how many opcodes are in each of the sixteen buckets. */
1491 for (i = 0; i < m68k_numopcodes; i++)
1492 numopcodes[(m68k_opcodes[i].opcode >> 28) & 15]++;
1494 /* Then create a sorted table of pointers
1495 that point into the unsorted table. */
1496 opc_pointer[0] = xmalloc (sizeof (struct m68k_opcode *)
1498 opcodes[0] = opc_pointer[0];
1500 for (i = 1; i < 16; i++)
1502 opc_pointer[i] = opc_pointer[i - 1] + numopcodes[i - 1];
1503 opcodes[i] = opc_pointer[i];
1506 for (i = 0; i < m68k_numopcodes; i++)
1507 *opc_pointer[(m68k_opcodes[i].opcode >> 28) & 15]++ = &m68k_opcodes[i];
1510 FETCH_DATA (info, buffer + 2);
1511 major_opcode = (buffer[0] >> 4) & 15;
1513 for (i = 0; i < numopcodes[major_opcode]; i++)
1515 const struct m68k_opcode *opc = opcodes[major_opcode][i];
1516 unsigned long opcode = opc->opcode;
1517 unsigned long match = opc->match;
1518 const char *args = opc->args;
1523 if (((0xff & buffer[0] & (match >> 24)) == (0xff & (opcode >> 24)))
1524 && ((0xff & buffer[1] & (match >> 16)) == (0xff & (opcode >> 16)))
1525 /* Only fetch the next two bytes if we need to. */
1526 && (((0xffff & match) == 0)
1528 (FETCH_DATA (info, buffer + 4)
1529 && ((0xff & buffer[2] & (match >> 8)) == (0xff & (opcode >> 8)))
1530 && ((0xff & buffer[3] & match) == (0xff & opcode)))
1532 && (opc->arch & arch_mask) != 0)
1534 /* Don't use for printout the variants of divul and divsl
1535 that have the same register number in two places.
1536 The more general variants will match instead. */
1537 for (d = args; *d; d += 2)
1541 /* Don't use for printout the variants of most floating
1542 point coprocessor instructions which use the same
1543 register number in two places, as above. */
1545 for (d = args; *d; d += 2)
1549 /* Don't match fmovel with more than one register;
1550 wait for fmoveml. */
1553 for (d = args; *d; d += 2)
1555 if (d[0] == 's' && d[1] == '8')
1557 val = fetch_arg (buffer, d[1], 3, info);
1560 if ((val & (val - 1)) != 0)
1566 /* Don't match FPU insns with non-default coprocessor ID. */
1569 for (d = args; *d; d += 2)
1573 val = fetch_arg (buffer, 'd', 3, info);
1581 if ((val = match_insn_m68k (memaddr, info, opc)))
1588 /* Print the m68k instruction at address MEMADDR in debugged memory,
1589 on INFO->STREAM. Returns length of the instruction, in bytes. */
1592 print_insn_m68k (bfd_vma memaddr, disassemble_info *info)
1594 unsigned int arch_mask;
1595 struct private priv;
1598 bfd_byte *buffer = priv.the_buffer;
1600 info->private_data = & priv;
1601 /* Tell objdump to use two bytes per chunk
1602 and six bytes per line for displaying raw data. */
1603 info->bytes_per_chunk = 2;
1604 info->bytes_per_line = 6;
1605 info->display_endian = BFD_ENDIAN_BIG;
1606 priv.max_fetched = priv.the_buffer;
1607 priv.insn_start = memaddr;
1609 arch_mask = bfd_m68k_mach_to_features (info->mach);
1612 /* First try printing an m680x0 instruction. Try printing a Coldfire
1613 one if that fails. */
1614 val = m68k_scan_mask (memaddr, info, m68k_mask);
1616 val = m68k_scan_mask (memaddr, info, mcf_mask);
1620 val = m68k_scan_mask (memaddr, info, arch_mask);
1624 /* Handle undefined instructions. */
1625 info->fprintf_func (info->stream, ".short 0x%04x", (buffer[0] << 8) + buffer[1]);
1627 return val ? val : 2;