1 /* Instruction description for m32r.
3 This file is machine generated.
5 Copyright (C) 1996, 1997 Free Software Foundation, Inc.
7 This file is part of the GNU Binutils and/or GDB, the GNU debugger.
9 This program is free software; you can redistribute it and/or modify
10 it under the terms of the GNU General Public License as published by
11 the Free Software Foundation; either version 2, or (at your option)
14 This program is distributed in the hope that it will be useful,
15 but WITHOUT ANY WARRANTY; without even the implied warranty of
16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 GNU General Public License for more details.
19 You should have received a copy of the GNU General Public License along
20 with this program; if not, write to the Free Software Foundation, Inc.,
21 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
28 #define CGEN_ARCH m32r
29 /* Given symbol S, return m32r_cgen_<s>. */
30 #define CGEN_SYM(s) CGEN_CAT3 (m32r,_cgen_,s)
32 #define CGEN_WORD_BITSIZE 32
33 #define CGEN_DEFAULT_INSN_BITSIZE 32
34 #define CGEN_BASE_INSN_BITSIZE 32
35 #define CGEN_MAX_INSN_BITSIZE 32
36 #define CGEN_DEFAULT_INSN_SIZE (CGEN_DEFAULT_INSN_BITSIZE / 8)
37 #define CGEN_BASE_INSN_SIZE (CGEN_BASE_INSN_BITSIZE / 8)
38 #define CGEN_MAX_INSN_SIZE (CGEN_MAX_INSN_BITSIZE / 8)
41 /* +1 because the first entry is reserved (null) */
42 #define CGEN_NUM_INSNS (165 + 1)
43 #define CGEN_NUM_OPERANDS (24)
45 /* Number of non-boolean attributes. */
46 #define CGEN_MAX_INSN_ATTRS 2
47 #define CGEN_MAX_OPERAND_ATTRS 0
49 /* FIXME: Need to compute CGEN_MAX_SYNTAX_BYTES. */
51 /* CGEN_MNEMONIC_OPERANDS is defined if mnemonics have operands.
52 e.g. In "b,a foo" the ",a" is an operand. If mnemonics have operands
53 we can't hash on everything up to the space. */
54 #define CGEN_MNEMONIC_OPERANDS
56 /* Number of architecture variants. */
61 /* Enum declaration for insn format enums. */
62 typedef enum insn_op1 {
63 OP1_0 = 0, OP1_1 = 1, OP1_2 = 2, OP1_3 = 3,
64 OP1_4 = 4, OP1_5 = 5, OP1_6 = 6, OP1_7 = 7,
65 OP1_8 = 8, OP1_9 = 9, OP1_10 = 10, OP1_11 = 11,
66 OP1_12 = 12, OP1_13 = 13, OP1_14 = 14, OP1_15 = 15
69 /* Enum declaration for op2 enums. */
70 typedef enum insn_op2 {
71 OP2_0 = 0, OP2_1 = 1, OP2_2 = 2, OP2_3 = 3,
72 OP2_4 = 4, OP2_5 = 5, OP2_6 = 6, OP2_7 = 7,
73 OP2_8 = 8, OP2_9 = 9, OP2_10 = 10, OP2_11 = 11,
74 OP2_12 = 12, OP2_13 = 13, OP2_14 = 14, OP2_15 = 15
77 /* Enum declaration for m32r operand types. */
78 typedef enum cgen_operand_type {
79 M32R_OPERAND_PC = 0, M32R_OPERAND_SR = 1, M32R_OPERAND_DR = 2, M32R_OPERAND_SRC1 = 3,
80 M32R_OPERAND_SRC2 = 4, M32R_OPERAND_SCR = 5, M32R_OPERAND_DCR = 6, M32R_OPERAND_SIMM8 = 7,
81 M32R_OPERAND_SIMM16 = 8, M32R_OPERAND_UIMM4 = 9, M32R_OPERAND_UIMM5 = 10, M32R_OPERAND_UIMM16 = 11,
82 M32R_OPERAND_ACC_S = 12, M32R_OPERAND_ACC = 13, M32R_OPERAND_HI16 = 14, M32R_OPERAND_SLO16 = 15,
83 M32R_OPERAND_ULO16 = 16, M32R_OPERAND_UIMM24 = 17, M32R_OPERAND_DISP8 = 18, M32R_OPERAND_DISP16 = 19,
84 M32R_OPERAND_DISP24 = 20, M32R_OPERAND_CONDBIT = 21, M32R_OPERAND_ACCUM = 22, M32R_OPERAND_ABORT_PARALLEL_EXECUTION = 23
87 /* Non-boolean attributes. */
89 /* Enum declaration for machine type selection. */
90 typedef enum mach_attr {
91 MACH_M32R = 0, MACH_M32RX = 1
94 /* Enum declaration for parallel execution pipeline selection. */
95 typedef enum pipe_attr {
96 PIPE_NONE = 0, PIPE_O = 1, PIPE_S = 2, PIPE_OS = 3
99 /* Operand and instruction attribute indices. */
101 /* Enum declaration for cgen_operand attrs. */
102 typedef enum cgen_operand_attr {
103 CGEN_OPERAND_ABS_ADDR, CGEN_OPERAND_FAKE, CGEN_OPERAND_NEGATIVE, CGEN_OPERAND_PC,
104 CGEN_OPERAND_PCREL_ADDR, CGEN_OPERAND_RELAX, CGEN_OPERAND_RELOC, CGEN_OPERAND_SIGN_OPT,
105 CGEN_OPERAND_UNSIGNED
108 /* Enum declaration for cgen_insn attrs. */
109 typedef enum cgen_insn_attr {
110 CGEN_INSN_MACH, CGEN_INSN_PIPE, CGEN_INSN_ALIAS, CGEN_INSN_COND_CTI,
111 CGEN_INSN_FILL_SLOT, CGEN_INSN_PARALLEL, CGEN_INSN_RELAX, CGEN_INSN_RELAX_BC,
112 CGEN_INSN_RELAX_BCL, CGEN_INSN_RELAX_BL, CGEN_INSN_RELAX_BNC, CGEN_INSN_RELAX_BNCL,
113 CGEN_INSN_RELAX_BRA, CGEN_INSN_RELAXABLE, CGEN_INSN_UNCOND_CTI
116 /* Insn types are used by the simulator. */
117 /* Enum declaration for m32r instruction types. */
118 typedef enum cgen_insn_type {
119 M32R_INSN_ILLEGAL, M32R_INSN_ADD, M32R_INSN_ADD3, M32R_INSN_AND,
120 M32R_INSN_AND3, M32R_INSN_OR, M32R_INSN_OR3, M32R_INSN_XOR,
121 M32R_INSN_XOR3, M32R_INSN_ADDI, M32R_INSN_ADDV, M32R_INSN_ADDV3,
122 M32R_INSN_ADDX, M32R_INSN_BC8, M32R_INSN_BC8_S, M32R_INSN_BC24,
123 M32R_INSN_BC24_L, M32R_INSN_BEQ, M32R_INSN_BEQZ, M32R_INSN_BGEZ,
124 M32R_INSN_BGTZ, M32R_INSN_BLEZ, M32R_INSN_BLTZ, M32R_INSN_BNEZ,
125 M32R_INSN_BL8, M32R_INSN_BL8_S, M32R_INSN_BL24, M32R_INSN_BL24_L,
126 M32R_INSN_BCL8, M32R_INSN_BCL8_S, M32R_INSN_BCL24, M32R_INSN_BCL24_L,
127 M32R_INSN_BNC8, M32R_INSN_BNC8_S, M32R_INSN_BNC24, M32R_INSN_BNC24_L,
128 M32R_INSN_BNE, M32R_INSN_BRA8, M32R_INSN_BRA8_S, M32R_INSN_BRA24,
129 M32R_INSN_BRA24_L, M32R_INSN_BNCL8, M32R_INSN_BNCL8_S, M32R_INSN_BNCL24,
130 M32R_INSN_BNCL24_L, M32R_INSN_CMP, M32R_INSN_CMPI, M32R_INSN_CMPU,
131 M32R_INSN_CMPUI, M32R_INSN_CMPEQ, M32R_INSN_CMPZ, M32R_INSN_DIV,
132 M32R_INSN_DIVU, M32R_INSN_REM, M32R_INSN_REMU, M32R_INSN_JC,
133 M32R_INSN_JNC, M32R_INSN_JL, M32R_INSN_JMP, M32R_INSN_LD,
134 M32R_INSN_LD_2, M32R_INSN_LD_D, M32R_INSN_LD_D2, M32R_INSN_LDB,
135 M32R_INSN_LDB_2, M32R_INSN_LDB_D, M32R_INSN_LDB_D2, M32R_INSN_LDH,
136 M32R_INSN_LDH_2, M32R_INSN_LDH_D, M32R_INSN_LDH_D2, M32R_INSN_LDUB,
137 M32R_INSN_LDUB_2, M32R_INSN_LDUB_D, M32R_INSN_LDUB_D2, M32R_INSN_LDUH,
138 M32R_INSN_LDUH_2, M32R_INSN_LDUH_D, M32R_INSN_LDUH_D2, M32R_INSN_LD_PLUS,
139 M32R_INSN_LD24, M32R_INSN_LDI8, M32R_INSN_LDI8A, M32R_INSN_LDI16,
140 M32R_INSN_LDI16A, M32R_INSN_LOCK, M32R_INSN_MACHI, M32R_INSN_MACHI_A,
141 M32R_INSN_MACLO, M32R_INSN_MACLO_A, M32R_INSN_MACWHI, M32R_INSN_MACWHI_A,
142 M32R_INSN_MACWLO, M32R_INSN_MACWLO_A, M32R_INSN_MUL, M32R_INSN_MULHI,
143 M32R_INSN_MULHI_A, M32R_INSN_MULLO, M32R_INSN_MULLO_A, M32R_INSN_MULWHI,
144 M32R_INSN_MULWHI_A, M32R_INSN_MULWLO, M32R_INSN_MULWLO_A, M32R_INSN_MV,
145 M32R_INSN_MVFACHI, M32R_INSN_MVFACHI_A, M32R_INSN_MVFACLO, M32R_INSN_MVFACLO_A,
146 M32R_INSN_MVFACMI, M32R_INSN_MVFACMI_A, M32R_INSN_MVFC, M32R_INSN_MVTACHI,
147 M32R_INSN_MVTACHI_A, M32R_INSN_MVTACLO, M32R_INSN_MVTACLO_A, M32R_INSN_MVTC,
148 M32R_INSN_NEG, M32R_INSN_NOP, M32R_INSN_NOT, M32R_INSN_RAC,
149 M32R_INSN_RAC_A, M32R_INSN_RACH, M32R_INSN_RACH_A, M32R_INSN_RTE,
150 M32R_INSN_SETH, M32R_INSN_SLL, M32R_INSN_SLL3, M32R_INSN_SLLI,
151 M32R_INSN_SRA, M32R_INSN_SRA3, M32R_INSN_SRAI, M32R_INSN_SRL,
152 M32R_INSN_SRL3, M32R_INSN_SRLI, M32R_INSN_ST, M32R_INSN_ST_2,
153 M32R_INSN_ST_D, M32R_INSN_ST_D2, M32R_INSN_STB, M32R_INSN_STB_2,
154 M32R_INSN_STB_D, M32R_INSN_STB_D2, M32R_INSN_STH, M32R_INSN_STH_2,
155 M32R_INSN_STH_D, M32R_INSN_STH_D2, M32R_INSN_ST_PLUS, M32R_INSN_ST_MINUS,
156 M32R_INSN_SUB, M32R_INSN_SUBV, M32R_INSN_SUBX, M32R_INSN_TRAP,
157 M32R_INSN_UNLOCK, M32R_INSN_PUSH, M32R_INSN_POP, M32R_INSN_SATB,
158 M32R_INSN_SATH, M32R_INSN_SAT, M32R_INSN_PCMPBZ, M32R_INSN_SADD,
159 M32R_INSN_MACWU1, M32R_INSN_MSBLO, M32R_INSN_MULWU1, M32R_INSN_MACHL1,
160 M32R_INSN_SC, M32R_INSN_SNC, M32R_INSN_MAX
163 /* Index of `illegal' insn place holder. */
164 #define CGEN_INSN_ILLEGAL M32R_INSN_ILLEGAL
165 /* Total number of insns in table. */
166 #define CGEN_MAX_INSNS ((int) M32R_INSN_MAX)
168 /* cgen.h uses things we just defined. */
169 #include "opcode/cgen.h"
171 /* This struct records data prior to insertion or after extraction. */
172 typedef struct cgen_fields {
198 extern const CGEN_ATTR_TABLE m32r_cgen_operand_attr_table[];
199 extern const CGEN_ATTR_TABLE m32r_cgen_insn_attr_table[];
201 extern CGEN_KEYWORD m32r_cgen_opval_mach;
202 extern CGEN_KEYWORD m32r_cgen_opval_h_gr;
203 extern CGEN_KEYWORD m32r_cgen_opval_h_cr;
204 extern CGEN_KEYWORD m32r_cgen_opval_h_accums;
206 #define CGEN_INIT_PARSE() \
209 #define CGEN_INIT_INSERT() \
212 #define CGEN_INIT_EXTRACT() \
215 #define CGEN_INIT_PRINT() \
221 #undef CGEN_DIS_HASH_SIZE
222 #define CGEN_DIS_HASH_SIZE 256
224 #define X(b) (((unsigned char *) (b))[0] & 0xf0)
225 #define CGEN_DIS_HASH(buffer, insn) \
227 (X (buffer) == 0x40 || X (buffer) == 0xe0 || X (buffer) == 0x60 || X (buffer) == 0x50 ? 0 \
228 : X (buffer) == 0x70 || X (buffer) == 0xf0 ? (((unsigned char *) (buffer))[0] & 0xf) \
229 : ((((unsigned char *) (buffer))[1] & 0xf0) >> 4)))
234 #endif /* m32r_OPC_H */