1 /* Generic opcode table support for targets using CGEN. -*- C -*-
2 CGEN: Cpu tools GENerator
4 THIS FILE IS USED TO GENERATE m32r-opc.c.
6 Copyright (C) 1998 Free Software Foundation, Inc.
8 This file is part of the GNU Binutils and GDB, the GNU debugger.
10 This program is free software; you can redistribute it and/or modify
11 it under the terms of the GNU General Public License as published by
12 the Free Software Foundation; either version 2, or (at your option)
15 This program is distributed in the hope that it will be useful,
16 but WITHOUT ANY WARRANTY; without even the implied warranty of
17 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 GNU General Public License for more details.
20 You should have received a copy of the GNU General Public License
21 along with this program; if not, write to the Free Software Foundation, Inc.,
22 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */
27 #include "libiberty.h"
33 /* Look up instruction INSN_VALUE and extract its fields.
34 INSN, if non-null, is the insn table entry.
35 Otherwise INSN_VALUE is examined to compute it.
36 LENGTH is the bit length of INSN_VALUE if known, otherwise 0.
37 0 is only valid if `insn == NULL && ! defined (CGEN_INT_INSN)'.
38 If INSN != NULL, LENGTH must be valid.
39 ALIAS_P is non-zero if alias insns are to be included in the search.
41 The result a pointer to the insn table entry, or NULL if the instruction
45 m32r_cgen_lookup_insn (insn, insn_value, length, fields, alias_p)
46 const CGEN_INSN *insn;
47 cgen_insn_t insn_value;
56 const CGEN_INSN_LIST *insn_list;
65 if (cgen_current_endian == CGEN_ENDIAN_BIG)
66 bfd_putb16 (insn_value, buf);
68 bfd_putl16 (insn_value, buf);
71 if (cgen_current_endian == CGEN_ENDIAN_BIG)
72 bfd_putb32 (insn_value, buf);
74 bfd_putl32 (insn_value, buf);
80 abort (); /* FIXME: unfinished */
83 /* The instructions are stored in hash lists.
84 Pick the first one and keep trying until we find the right one. */
86 insn_list = CGEN_DIS_LOOKUP_INSN (buf, insn_value);
87 while (insn_list != NULL)
89 insn = insn_list->insn;
92 || ! CGEN_INSN_ATTR (insn, CGEN_INSN_ALIAS))
94 /* Basic bit mask must be correct. */
95 /* ??? May wish to allow target to defer this check until the
97 if ((insn_value & CGEN_INSN_MASK (insn)) == CGEN_INSN_VALUE (insn))
99 /* ??? 0 is passed for `pc' */
100 int elength = (*CGEN_EXTRACT_FN (insn)) (insn, NULL,
106 if (length != 0 && length != elength)
113 insn_list = CGEN_DIS_NEXT_INSN (insn_list);
118 /* Sanity check: can't pass an alias insn if ! alias_p. */
120 && CGEN_INSN_ATTR (insn, CGEN_INSN_ALIAS))
122 /* Sanity check: length must be correct. */
123 if (length != CGEN_INSN_BITSIZE (insn))
126 /* ??? 0 is passed for `pc' */
127 length = (*CGEN_EXTRACT_FN (insn)) (insn, NULL, insn_value, fields,
129 /* Sanity check: must succeed.
130 Could relax this later if it ever proves useful. */
139 /* Fill in the operand instances used by INSN whose operands are FIELDS.
140 INDICES is a pointer to a buffer of MAX_OPERAND_INSTANCES ints to be filled
144 m32r_cgen_get_insn_operands (insn, fields, indices)
145 const CGEN_INSN * insn;
146 const CGEN_FIELDS * fields;
149 const CGEN_OPERAND_INSTANCE *opinst;
152 for (i = 0, opinst = CGEN_INSN_OPERANDS (insn);
154 && CGEN_OPERAND_INSTANCE_TYPE (opinst) != CGEN_OPERAND_INSTANCE_END;
157 const CGEN_OPERAND *op = CGEN_OPERAND_INSTANCE_OPERAND (opinst);
159 indices[i] = CGEN_OPERAND_INSTANCE_INDEX (opinst);
161 indices[i] = m32r_cgen_get_int_operand (CGEN_OPERAND_INDEX (op), fields);
165 /* Cover function to m32r_cgen_get_insn_operands when either INSN or FIELDS
167 The INSN, INSN_VALUE, and LENGTH arguments are passed to
168 m32r_cgen_lookup_insn unchanged.
170 The result is the insn table entry or NULL if the instruction wasn't
174 m32r_cgen_lookup_get_insn_operands (insn, insn_value, length, indices)
175 const CGEN_INSN *insn;
176 cgen_insn_t insn_value;
182 /* Pass non-zero for ALIAS_P only if INSN != NULL.
183 If INSN == NULL, we want a real insn. */
184 insn = m32r_cgen_lookup_insn (insn, insn_value, length, &fields,
189 m32r_cgen_get_insn_operands (insn, &fields, indices);
194 static const CGEN_ATTR_ENTRY MACH_attr[] =
196 { "m32r", MACH_M32R },
197 /* start-sanitize-m32rx */
198 { "m32rx", MACH_M32RX },
199 /* end-sanitize-m32rx */
204 /* start-sanitize-m32rx */
205 static const CGEN_ATTR_ENTRY PIPE_attr[] =
207 { "NONE", PIPE_NONE },
214 /* end-sanitize-m32rx */
215 const CGEN_ATTR_TABLE m32r_cgen_operand_attr_table[] =
217 { "ABS-ADDR", NULL },
219 { "HASH-PREFIX", NULL },
220 { "NEGATIVE", NULL },
221 { "PCREL-ADDR", NULL },
224 { "SIGN-OPT", NULL },
225 { "UNSIGNED", NULL },
229 const CGEN_ATTR_TABLE m32r_cgen_insn_attr_table[] =
231 { "MACH", & MACH_attr[0] },
232 /* start-sanitize-m32rx */
233 { "PIPE", & PIPE_attr[0] },
234 /* end-sanitize-m32rx */
236 { "COND-CTI", NULL },
237 { "FILL-SLOT", NULL },
239 { "PARALLEL", NULL },
241 { "RELAXABLE", NULL },
243 { "UNCOND-CTI", NULL },
247 CGEN_KEYWORD_ENTRY m32r_cgen_opval_h_gr_entries[] =
270 CGEN_KEYWORD m32r_cgen_opval_h_gr =
272 & m32r_cgen_opval_h_gr_entries[0],
276 CGEN_KEYWORD_ENTRY m32r_cgen_opval_h_cr_entries[] =
301 CGEN_KEYWORD m32r_cgen_opval_h_cr =
303 & m32r_cgen_opval_h_cr_entries[0],
307 /* start-sanitize-m32rx */
308 CGEN_KEYWORD_ENTRY m32r_cgen_opval_h_accums_entries[] =
314 CGEN_KEYWORD m32r_cgen_opval_h_accums =
316 & m32r_cgen_opval_h_accums_entries[0],
320 /* end-sanitize-m32rx */
322 /* The hardware table. */
324 #define HW_ENT(n) m32r_cgen_hw_entries[n]
325 static const CGEN_HW_ENTRY m32r_cgen_hw_entries[] =
327 { HW_H_PC, & HW_ENT (HW_H_PC + 1), "h-pc", CGEN_ASM_KEYWORD, (PTR) 0 },
328 { HW_H_MEMORY, & HW_ENT (HW_H_MEMORY + 1), "h-memory", CGEN_ASM_KEYWORD, (PTR) 0 },
329 { HW_H_SINT, & HW_ENT (HW_H_SINT + 1), "h-sint", CGEN_ASM_KEYWORD, (PTR) 0 },
330 { HW_H_UINT, & HW_ENT (HW_H_UINT + 1), "h-uint", CGEN_ASM_KEYWORD, (PTR) 0 },
331 { HW_H_ADDR, & HW_ENT (HW_H_ADDR + 1), "h-addr", CGEN_ASM_KEYWORD, (PTR) 0 },
332 { HW_H_IADDR, & HW_ENT (HW_H_IADDR + 1), "h-iaddr", CGEN_ASM_KEYWORD, (PTR) 0 },
333 { HW_H_HI16, & HW_ENT (HW_H_HI16 + 1), "h-hi16", CGEN_ASM_KEYWORD, (PTR) 0 },
334 { HW_H_SLO16, & HW_ENT (HW_H_SLO16 + 1), "h-slo16", CGEN_ASM_KEYWORD, (PTR) 0 },
335 { HW_H_ULO16, & HW_ENT (HW_H_ULO16 + 1), "h-ulo16", CGEN_ASM_KEYWORD, (PTR) 0 },
336 { HW_H_GR, & HW_ENT (HW_H_GR + 1), "h-gr", CGEN_ASM_KEYWORD, (PTR) & m32r_cgen_opval_h_gr },
337 { HW_H_CR, & HW_ENT (HW_H_CR + 1), "h-cr", CGEN_ASM_KEYWORD, (PTR) & m32r_cgen_opval_h_cr },
338 { HW_H_ACCUM, & HW_ENT (HW_H_ACCUM + 1), "h-accum", CGEN_ASM_KEYWORD, (PTR) 0 },
339 /* start-sanitize-m32rx */
340 { HW_H_ACCUMS, & HW_ENT (HW_H_ACCUMS + 1), "h-accums", CGEN_ASM_KEYWORD, (PTR) & m32r_cgen_opval_h_accums },
341 /* end-sanitize-m32rx */
342 { HW_H_COND, & HW_ENT (HW_H_COND + 1), "h-cond", CGEN_ASM_KEYWORD, (PTR) 0 },
343 { HW_H_SM, & HW_ENT (HW_H_SM + 1), "h-sm", CGEN_ASM_KEYWORD, (PTR) 0 },
344 { HW_H_BSM, & HW_ENT (HW_H_BSM + 1), "h-bsm", CGEN_ASM_KEYWORD, (PTR) 0 },
345 { HW_H_IE, & HW_ENT (HW_H_IE + 1), "h-ie", CGEN_ASM_KEYWORD, (PTR) 0 },
346 { HW_H_BIE, & HW_ENT (HW_H_BIE + 1), "h-bie", CGEN_ASM_KEYWORD, (PTR) 0 },
347 { HW_H_BCOND, & HW_ENT (HW_H_BCOND + 1), "h-bcond", CGEN_ASM_KEYWORD, (PTR) 0 },
348 { HW_H_BPC, & HW_ENT (HW_H_BPC + 1), "h-bpc", CGEN_ASM_KEYWORD, (PTR) 0 },
349 { HW_H_LOCK, & HW_ENT (HW_H_LOCK + 1), "h-lock", CGEN_ASM_KEYWORD, (PTR) 0 },
353 /* The operand table. */
355 #define OPERAND(op) CONCAT2 (M32R_OPERAND_,op)
356 #define OP_ENT(op) m32r_cgen_operand_table[OPERAND (op)]
358 const CGEN_OPERAND m32r_cgen_operand_table[MAX_OPERANDS] =
360 /* pc: program counter */
361 { "pc", & HW_ENT (HW_H_PC), 0, 0,
362 { 0, 0|(1<<CGEN_OPERAND_FAKE), { 0 } } },
363 /* sr: source register */
364 { "sr", & HW_ENT (HW_H_GR), 12, 4,
365 { 0, 0|(1<<CGEN_OPERAND_UNSIGNED), { 0 } } },
366 /* dr: destination register */
367 { "dr", & HW_ENT (HW_H_GR), 4, 4,
368 { 0, 0|(1<<CGEN_OPERAND_UNSIGNED), { 0 } } },
369 /* src1: source register 1 */
370 { "src1", & HW_ENT (HW_H_GR), 4, 4,
371 { 0, 0|(1<<CGEN_OPERAND_UNSIGNED), { 0 } } },
372 /* src2: source register 2 */
373 { "src2", & HW_ENT (HW_H_GR), 12, 4,
374 { 0, 0|(1<<CGEN_OPERAND_UNSIGNED), { 0 } } },
375 /* scr: source control register */
376 { "scr", & HW_ENT (HW_H_CR), 12, 4,
377 { 0, 0|(1<<CGEN_OPERAND_UNSIGNED), { 0 } } },
378 /* dcr: destination control register */
379 { "dcr", & HW_ENT (HW_H_CR), 4, 4,
380 { 0, 0|(1<<CGEN_OPERAND_UNSIGNED), { 0 } } },
381 /* simm8: 8 bit signed immediate */
382 { "simm8", & HW_ENT (HW_H_SINT), 8, 8,
383 { 0, 0|(1<<CGEN_OPERAND_HASH_PREFIX), { 0 } } },
384 /* simm16: 16 bit signed immediate */
385 { "simm16", & HW_ENT (HW_H_SINT), 16, 16,
386 { 0, 0|(1<<CGEN_OPERAND_HASH_PREFIX), { 0 } } },
387 /* uimm4: 4 bit trap number */
388 { "uimm4", & HW_ENT (HW_H_UINT), 12, 4,
389 { 0, 0|(1<<CGEN_OPERAND_HASH_PREFIX)|(1<<CGEN_OPERAND_UNSIGNED), { 0 } } },
390 /* uimm5: 5 bit shift count */
391 { "uimm5", & HW_ENT (HW_H_UINT), 11, 5,
392 { 0, 0|(1<<CGEN_OPERAND_HASH_PREFIX)|(1<<CGEN_OPERAND_UNSIGNED), { 0 } } },
393 /* uimm16: 16 bit unsigned immediate */
394 { "uimm16", & HW_ENT (HW_H_UINT), 16, 16,
395 { 0, 0|(1<<CGEN_OPERAND_HASH_PREFIX)|(1<<CGEN_OPERAND_UNSIGNED), { 0 } } },
396 /* start-sanitize-m32rx */
397 /* imm1: 1 bit immediate */
398 { "imm1", & HW_ENT (HW_H_UINT), 15, 1,
399 { 0, 0|(1<<CGEN_OPERAND_HASH_PREFIX)|(1<<CGEN_OPERAND_UNSIGNED), { 0 } } },
400 /* end-sanitize-m32rx */
401 /* start-sanitize-m32rx */
402 /* accd: accumulator destination register */
403 { "accd", & HW_ENT (HW_H_ACCUMS), 4, 2,
404 { 0, 0|(1<<CGEN_OPERAND_UNSIGNED), { 0 } } },
405 /* end-sanitize-m32rx */
406 /* start-sanitize-m32rx */
407 /* accs: accumulator source register */
408 { "accs", & HW_ENT (HW_H_ACCUMS), 12, 2,
409 { 0, 0|(1<<CGEN_OPERAND_UNSIGNED), { 0 } } },
410 /* end-sanitize-m32rx */
411 /* start-sanitize-m32rx */
412 /* acc: accumulator reg (d) */
413 { "acc", & HW_ENT (HW_H_ACCUMS), 8, 1,
414 { 0, 0|(1<<CGEN_OPERAND_UNSIGNED), { 0 } } },
415 /* end-sanitize-m32rx */
417 { "hash", & HW_ENT (HW_H_SINT), 0, 0,
419 /* hi16: high 16 bit immediate, sign optional */
420 { "hi16", & HW_ENT (HW_H_HI16), 16, 16,
421 { 0, 0|(1<<CGEN_OPERAND_SIGN_OPT)|(1<<CGEN_OPERAND_UNSIGNED), { 0 } } },
422 /* slo16: 16 bit signed immediate, for low() */
423 { "slo16", & HW_ENT (HW_H_SLO16), 16, 16,
425 /* ulo16: 16 bit unsigned immediate, for low() */
426 { "ulo16", & HW_ENT (HW_H_ULO16), 16, 16,
427 { 0, 0|(1<<CGEN_OPERAND_UNSIGNED), { 0 } } },
428 /* uimm24: 24 bit address */
429 { "uimm24", & HW_ENT (HW_H_ADDR), 8, 24,
430 { 0, 0|(1<<CGEN_OPERAND_HASH_PREFIX)|(1<<CGEN_OPERAND_RELOC)|(1<<CGEN_OPERAND_ABS_ADDR)|(1<<CGEN_OPERAND_UNSIGNED), { 0 } } },
431 /* disp8: 8 bit displacement */
432 { "disp8", & HW_ENT (HW_H_IADDR), 8, 8,
433 { 0, 0|(1<<CGEN_OPERAND_RELAX)|(1<<CGEN_OPERAND_RELOC)|(1<<CGEN_OPERAND_PCREL_ADDR), { 0 } } },
434 /* disp16: 16 bit displacement */
435 { "disp16", & HW_ENT (HW_H_IADDR), 16, 16,
436 { 0, 0|(1<<CGEN_OPERAND_RELOC)|(1<<CGEN_OPERAND_PCREL_ADDR), { 0 } } },
437 /* disp24: 24 bit displacement */
438 { "disp24", & HW_ENT (HW_H_IADDR), 8, 24,
439 { 0, 0|(1<<CGEN_OPERAND_RELAX)|(1<<CGEN_OPERAND_RELOC)|(1<<CGEN_OPERAND_PCREL_ADDR), { 0 } } },
440 /* condbit: condition bit */
441 { "condbit", & HW_ENT (HW_H_COND), 0, 0,
442 { 0, 0|(1<<CGEN_OPERAND_FAKE), { 0 } } },
443 /* accum: accumulator */
444 { "accum", & HW_ENT (HW_H_ACCUM), 0, 0,
445 { 0, 0|(1<<CGEN_OPERAND_FAKE), { 0 } } },
448 /* Operand references. */
450 #define INPUT CGEN_OPERAND_INSTANCE_INPUT
451 #define OUTPUT CGEN_OPERAND_INSTANCE_OUTPUT
453 static const CGEN_OPERAND_INSTANCE fmt_add_ops[] = {
454 { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0 },
455 { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SR), 0 },
456 { OUTPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0 },
460 static const CGEN_OPERAND_INSTANCE fmt_add3_ops[] = {
461 { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SR), 0 },
462 { INPUT, & HW_ENT (HW_H_SLO16), CGEN_MODE_HI, & OP_ENT (SLO16), 0 },
463 { OUTPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0 },
467 static const CGEN_OPERAND_INSTANCE fmt_and3_ops[] = {
468 { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SR), 0 },
469 { INPUT, & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (UIMM16), 0 },
470 { OUTPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0 },
474 static const CGEN_OPERAND_INSTANCE fmt_or3_ops[] = {
475 { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SR), 0 },
476 { INPUT, & HW_ENT (HW_H_ULO16), CGEN_MODE_UHI, & OP_ENT (ULO16), 0 },
477 { OUTPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0 },
481 static const CGEN_OPERAND_INSTANCE fmt_addi_ops[] = {
482 { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0 },
483 { INPUT, & HW_ENT (HW_H_SINT), CGEN_MODE_SI, & OP_ENT (SIMM8), 0 },
484 { OUTPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0 },
488 static const CGEN_OPERAND_INSTANCE fmt_addv_ops[] = {
489 { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0 },
490 { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SR), 0 },
491 { OUTPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0 },
492 { OUTPUT, & HW_ENT (HW_H_COND), CGEN_MODE_UBI, 0, 0 },
496 static const CGEN_OPERAND_INSTANCE fmt_addv3_ops[] = {
497 { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SR), 0 },
498 { INPUT, & HW_ENT (HW_H_SINT), CGEN_MODE_SI, & OP_ENT (SIMM16), 0 },
499 { OUTPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0 },
500 { OUTPUT, & HW_ENT (HW_H_COND), CGEN_MODE_UBI, 0, 0 },
504 static const CGEN_OPERAND_INSTANCE fmt_addx_ops[] = {
505 { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0 },
506 { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SR), 0 },
507 { INPUT, & HW_ENT (HW_H_COND), CGEN_MODE_UBI, 0, 0 },
508 { OUTPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0 },
509 { OUTPUT, & HW_ENT (HW_H_COND), CGEN_MODE_UBI, 0, 0 },
513 static const CGEN_OPERAND_INSTANCE fmt_bc8_ops[] = {
514 { INPUT, & HW_ENT (HW_H_COND), CGEN_MODE_UBI, 0, 0 },
515 { INPUT, & HW_ENT (HW_H_IADDR), CGEN_MODE_USI, & OP_ENT (DISP8), 0 },
516 { OUTPUT, & HW_ENT (HW_H_PC), CGEN_MODE_USI, 0, 0 },
520 static const CGEN_OPERAND_INSTANCE fmt_bc24_ops[] = {
521 { INPUT, & HW_ENT (HW_H_COND), CGEN_MODE_UBI, 0, 0 },
522 { INPUT, & HW_ENT (HW_H_IADDR), CGEN_MODE_USI, & OP_ENT (DISP24), 0 },
523 { OUTPUT, & HW_ENT (HW_H_PC), CGEN_MODE_USI, 0, 0 },
527 static const CGEN_OPERAND_INSTANCE fmt_beq_ops[] = {
528 { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC1), 0 },
529 { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC2), 0 },
530 { INPUT, & HW_ENT (HW_H_IADDR), CGEN_MODE_USI, & OP_ENT (DISP16), 0 },
531 { OUTPUT, & HW_ENT (HW_H_PC), CGEN_MODE_USI, 0, 0 },
535 static const CGEN_OPERAND_INSTANCE fmt_beqz_ops[] = {
536 { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC2), 0 },
537 { INPUT, & HW_ENT (HW_H_IADDR), CGEN_MODE_USI, & OP_ENT (DISP16), 0 },
538 { OUTPUT, & HW_ENT (HW_H_PC), CGEN_MODE_USI, 0, 0 },
542 static const CGEN_OPERAND_INSTANCE fmt_bl8_ops[] = {
543 { INPUT, & HW_ENT (HW_H_PC), CGEN_MODE_USI, 0, 0 },
544 { INPUT, & HW_ENT (HW_H_IADDR), CGEN_MODE_USI, & OP_ENT (DISP8), 0 },
545 { OUTPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 14 },
546 { OUTPUT, & HW_ENT (HW_H_PC), CGEN_MODE_USI, 0, 0 },
550 static const CGEN_OPERAND_INSTANCE fmt_bl24_ops[] = {
551 { INPUT, & HW_ENT (HW_H_PC), CGEN_MODE_USI, 0, 0 },
552 { INPUT, & HW_ENT (HW_H_IADDR), CGEN_MODE_USI, & OP_ENT (DISP24), 0 },
553 { OUTPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 14 },
554 { OUTPUT, & HW_ENT (HW_H_PC), CGEN_MODE_USI, 0, 0 },
558 /* start-sanitize-m32rx */
559 static const CGEN_OPERAND_INSTANCE fmt_bcl8_ops[] = {
560 { INPUT, & HW_ENT (HW_H_COND), CGEN_MODE_UBI, 0, 0 },
561 { INPUT, & HW_ENT (HW_H_PC), CGEN_MODE_USI, 0, 0 },
562 { INPUT, & HW_ENT (HW_H_IADDR), CGEN_MODE_USI, & OP_ENT (DISP8), 0 },
563 { OUTPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 14 },
564 { OUTPUT, & HW_ENT (HW_H_PC), CGEN_MODE_USI, 0, 0 },
568 /* end-sanitize-m32rx */
569 /* start-sanitize-m32rx */
570 static const CGEN_OPERAND_INSTANCE fmt_bcl24_ops[] = {
571 { INPUT, & HW_ENT (HW_H_COND), CGEN_MODE_UBI, 0, 0 },
572 { INPUT, & HW_ENT (HW_H_PC), CGEN_MODE_USI, 0, 0 },
573 { INPUT, & HW_ENT (HW_H_IADDR), CGEN_MODE_USI, & OP_ENT (DISP24), 0 },
574 { OUTPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 14 },
575 { OUTPUT, & HW_ENT (HW_H_PC), CGEN_MODE_USI, 0, 0 },
579 /* end-sanitize-m32rx */
580 static const CGEN_OPERAND_INSTANCE fmt_bra8_ops[] = {
581 { INPUT, & HW_ENT (HW_H_IADDR), CGEN_MODE_USI, & OP_ENT (DISP8), 0 },
582 { OUTPUT, & HW_ENT (HW_H_PC), CGEN_MODE_USI, 0, 0 },
586 static const CGEN_OPERAND_INSTANCE fmt_bra24_ops[] = {
587 { INPUT, & HW_ENT (HW_H_IADDR), CGEN_MODE_USI, & OP_ENT (DISP24), 0 },
588 { OUTPUT, & HW_ENT (HW_H_PC), CGEN_MODE_USI, 0, 0 },
592 static const CGEN_OPERAND_INSTANCE fmt_cmp_ops[] = {
593 { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC1), 0 },
594 { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC2), 0 },
595 { OUTPUT, & HW_ENT (HW_H_COND), CGEN_MODE_UBI, 0, 0 },
599 static const CGEN_OPERAND_INSTANCE fmt_cmpi_ops[] = {
600 { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC2), 0 },
601 { INPUT, & HW_ENT (HW_H_SINT), CGEN_MODE_SI, & OP_ENT (SIMM16), 0 },
602 { OUTPUT, & HW_ENT (HW_H_COND), CGEN_MODE_UBI, 0, 0 },
606 /* start-sanitize-m32rx */
607 static const CGEN_OPERAND_INSTANCE fmt_cmpz_ops[] = {
608 { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC2), 0 },
609 { OUTPUT, & HW_ENT (HW_H_COND), CGEN_MODE_UBI, 0, 0 },
613 /* end-sanitize-m32rx */
614 static const CGEN_OPERAND_INSTANCE fmt_div_ops[] = {
615 { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0 },
616 { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SR), 0 },
617 { OUTPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0 },
621 /* start-sanitize-m32rx */
622 static const CGEN_OPERAND_INSTANCE fmt_jc_ops[] = {
623 { INPUT, & HW_ENT (HW_H_COND), CGEN_MODE_UBI, 0, 0 },
624 { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SR), 0 },
625 { OUTPUT, & HW_ENT (HW_H_PC), CGEN_MODE_USI, 0, 0 },
629 /* end-sanitize-m32rx */
630 static const CGEN_OPERAND_INSTANCE fmt_jl_ops[] = {
631 { INPUT, & HW_ENT (HW_H_PC), CGEN_MODE_USI, 0, 0 },
632 { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SR), 0 },
633 { OUTPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 14 },
634 { OUTPUT, & HW_ENT (HW_H_PC), CGEN_MODE_USI, 0, 0 },
638 static const CGEN_OPERAND_INSTANCE fmt_jmp_ops[] = {
639 { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SR), 0 },
640 { OUTPUT, & HW_ENT (HW_H_PC), CGEN_MODE_USI, 0, 0 },
644 static const CGEN_OPERAND_INSTANCE fmt_ld_ops[] = {
645 { INPUT, & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0 },
646 { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_USI, & OP_ENT (SR), 0 },
647 { OUTPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0 },
651 static const CGEN_OPERAND_INSTANCE fmt_ld_d_ops[] = {
652 { INPUT, & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0 },
653 { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SR), 0 },
654 { INPUT, & HW_ENT (HW_H_SLO16), CGEN_MODE_HI, & OP_ENT (SLO16), 0 },
655 { OUTPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0 },
659 static const CGEN_OPERAND_INSTANCE fmt_ldb_ops[] = {
660 { INPUT, & HW_ENT (HW_H_MEMORY), CGEN_MODE_QI, 0, 0 },
661 { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_USI, & OP_ENT (SR), 0 },
662 { OUTPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0 },
666 static const CGEN_OPERAND_INSTANCE fmt_ldb_d_ops[] = {
667 { INPUT, & HW_ENT (HW_H_MEMORY), CGEN_MODE_QI, 0, 0 },
668 { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SR), 0 },
669 { INPUT, & HW_ENT (HW_H_SLO16), CGEN_MODE_HI, & OP_ENT (SLO16), 0 },
670 { OUTPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0 },
674 static const CGEN_OPERAND_INSTANCE fmt_ldh_ops[] = {
675 { INPUT, & HW_ENT (HW_H_MEMORY), CGEN_MODE_HI, 0, 0 },
676 { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_USI, & OP_ENT (SR), 0 },
677 { OUTPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0 },
681 static const CGEN_OPERAND_INSTANCE fmt_ldh_d_ops[] = {
682 { INPUT, & HW_ENT (HW_H_MEMORY), CGEN_MODE_HI, 0, 0 },
683 { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SR), 0 },
684 { INPUT, & HW_ENT (HW_H_SLO16), CGEN_MODE_HI, & OP_ENT (SLO16), 0 },
685 { OUTPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0 },
689 static const CGEN_OPERAND_INSTANCE fmt_ld_plus_ops[] = {
690 { INPUT, & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0 },
691 { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SR), 0 },
692 { OUTPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0 },
693 { OUTPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SR), 0 },
697 static const CGEN_OPERAND_INSTANCE fmt_ld24_ops[] = {
698 { INPUT, & HW_ENT (HW_H_ADDR), CGEN_MODE_USI, & OP_ENT (UIMM24), 0 },
699 { OUTPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0 },
703 static const CGEN_OPERAND_INSTANCE fmt_ldi8_ops[] = {
704 { INPUT, & HW_ENT (HW_H_SINT), CGEN_MODE_SI, & OP_ENT (SIMM8), 0 },
705 { OUTPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0 },
709 static const CGEN_OPERAND_INSTANCE fmt_ldi16_ops[] = {
710 { INPUT, & HW_ENT (HW_H_SLO16), CGEN_MODE_HI, & OP_ENT (SLO16), 0 },
711 { OUTPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0 },
715 static const CGEN_OPERAND_INSTANCE fmt_lock_ops[] = {
716 { INPUT, & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0 },
717 { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_USI, & OP_ENT (SR), 0 },
718 { OUTPUT, & HW_ENT (HW_H_LOCK), CGEN_MODE_UBI, 0, 0 },
719 { OUTPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0 },
723 static const CGEN_OPERAND_INSTANCE fmt_machi_ops[] = {
724 { INPUT, & HW_ENT (HW_H_ACCUM), CGEN_MODE_DI, 0, 0 },
725 { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC1), 0 },
726 { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC2), 0 },
727 { OUTPUT, & HW_ENT (HW_H_ACCUM), CGEN_MODE_DI, 0, 0 },
731 /* start-sanitize-m32rx */
732 static const CGEN_OPERAND_INSTANCE fmt_machi_a_ops[] = {
733 { INPUT, & HW_ENT (HW_H_ACCUMS), CGEN_MODE_DI, & OP_ENT (ACC), 0 },
734 { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC1), 0 },
735 { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC2), 0 },
736 { OUTPUT, & HW_ENT (HW_H_ACCUMS), CGEN_MODE_DI, & OP_ENT (ACC), 0 },
740 /* end-sanitize-m32rx */
741 static const CGEN_OPERAND_INSTANCE fmt_mulhi_ops[] = {
742 { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC1), 0 },
743 { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC2), 0 },
744 { OUTPUT, & HW_ENT (HW_H_ACCUM), CGEN_MODE_DI, 0, 0 },
748 /* start-sanitize-m32rx */
749 static const CGEN_OPERAND_INSTANCE fmt_mulhi_a_ops[] = {
750 { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC1), 0 },
751 { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC2), 0 },
752 { OUTPUT, & HW_ENT (HW_H_ACCUMS), CGEN_MODE_DI, & OP_ENT (ACC), 0 },
756 /* end-sanitize-m32rx */
757 static const CGEN_OPERAND_INSTANCE fmt_mv_ops[] = {
758 { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SR), 0 },
759 { OUTPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0 },
763 static const CGEN_OPERAND_INSTANCE fmt_mvfachi_ops[] = {
764 { INPUT, & HW_ENT (HW_H_ACCUM), CGEN_MODE_DI, 0, 0 },
765 { OUTPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0 },
769 /* start-sanitize-m32rx */
770 static const CGEN_OPERAND_INSTANCE fmt_mvfachi_a_ops[] = {
771 { INPUT, & HW_ENT (HW_H_ACCUMS), CGEN_MODE_DI, & OP_ENT (ACCS), 0 },
772 { OUTPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0 },
776 /* end-sanitize-m32rx */
777 static const CGEN_OPERAND_INSTANCE fmt_mvfc_ops[] = {
778 { INPUT, & HW_ENT (HW_H_CR), CGEN_MODE_USI, & OP_ENT (SCR), 0 },
779 { OUTPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0 },
783 static const CGEN_OPERAND_INSTANCE fmt_mvtachi_ops[] = {
784 { INPUT, & HW_ENT (HW_H_ACCUM), CGEN_MODE_DI, 0, 0 },
785 { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC1), 0 },
786 { OUTPUT, & HW_ENT (HW_H_ACCUM), CGEN_MODE_DI, 0, 0 },
790 /* start-sanitize-m32rx */
791 static const CGEN_OPERAND_INSTANCE fmt_mvtachi_a_ops[] = {
792 { INPUT, & HW_ENT (HW_H_ACCUMS), CGEN_MODE_DI, & OP_ENT (ACCS), 0 },
793 { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC1), 0 },
794 { OUTPUT, & HW_ENT (HW_H_ACCUMS), CGEN_MODE_DI, & OP_ENT (ACCS), 0 },
798 /* end-sanitize-m32rx */
799 static const CGEN_OPERAND_INSTANCE fmt_mvtc_ops[] = {
800 { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SR), 0 },
801 { OUTPUT, & HW_ENT (HW_H_CR), CGEN_MODE_USI, & OP_ENT (DCR), 0 },
805 static const CGEN_OPERAND_INSTANCE fmt_rac_ops[] = {
806 { INPUT, & HW_ENT (HW_H_ACCUM), CGEN_MODE_DI, 0, 0 },
807 { OUTPUT, & HW_ENT (HW_H_ACCUM), CGEN_MODE_DI, 0, 0 },
811 /* start-sanitize-m32rx */
812 static const CGEN_OPERAND_INSTANCE fmt_rac_dsi_ops[] = {
813 { INPUT, & HW_ENT (HW_H_ACCUMS), CGEN_MODE_DI, & OP_ENT (ACCS), 0 },
814 { INPUT, & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (IMM1), 0 },
815 { OUTPUT, & HW_ENT (HW_H_ACCUMS), CGEN_MODE_DI, & OP_ENT (ACCD), 0 },
819 /* end-sanitize-m32rx */
820 static const CGEN_OPERAND_INSTANCE fmt_rte_ops[] = {
821 { INPUT, & HW_ENT (HW_H_BSM), CGEN_MODE_UBI, 0, 0 },
822 { INPUT, & HW_ENT (HW_H_BIE), CGEN_MODE_UBI, 0, 0 },
823 { INPUT, & HW_ENT (HW_H_BCOND), CGEN_MODE_UBI, 0, 0 },
824 { INPUT, & HW_ENT (HW_H_BPC), CGEN_MODE_SI, 0, 0 },
825 { OUTPUT, & HW_ENT (HW_H_SM), CGEN_MODE_UBI, 0, 0 },
826 { OUTPUT, & HW_ENT (HW_H_IE), CGEN_MODE_UBI, 0, 0 },
827 { OUTPUT, & HW_ENT (HW_H_COND), CGEN_MODE_UBI, 0, 0 },
828 { OUTPUT, & HW_ENT (HW_H_PC), CGEN_MODE_USI, 0, 0 },
832 static const CGEN_OPERAND_INSTANCE fmt_seth_ops[] = {
833 { INPUT, & HW_ENT (HW_H_HI16), CGEN_MODE_SI, & OP_ENT (HI16), 0 },
834 { OUTPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0 },
838 static const CGEN_OPERAND_INSTANCE fmt_sll3_ops[] = {
839 { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SR), 0 },
840 { INPUT, & HW_ENT (HW_H_SINT), CGEN_MODE_SI, & OP_ENT (SIMM16), 0 },
841 { OUTPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0 },
845 static const CGEN_OPERAND_INSTANCE fmt_slli_ops[] = {
846 { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0 },
847 { INPUT, & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (UIMM5), 0 },
848 { OUTPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0 },
852 static const CGEN_OPERAND_INSTANCE fmt_st_ops[] = {
853 { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_USI, & OP_ENT (SRC2), 0 },
854 { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC1), 0 },
855 { OUTPUT, & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0 },
859 static const CGEN_OPERAND_INSTANCE fmt_st_d_ops[] = {
860 { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC2), 0 },
861 { INPUT, & HW_ENT (HW_H_SLO16), CGEN_MODE_HI, & OP_ENT (SLO16), 0 },
862 { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC1), 0 },
863 { OUTPUT, & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0 },
867 static const CGEN_OPERAND_INSTANCE fmt_stb_ops[] = {
868 { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_USI, & OP_ENT (SRC2), 0 },
869 { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_QI, & OP_ENT (SRC1), 0 },
870 { OUTPUT, & HW_ENT (HW_H_MEMORY), CGEN_MODE_QI, 0, 0 },
874 static const CGEN_OPERAND_INSTANCE fmt_stb_d_ops[] = {
875 { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC2), 0 },
876 { INPUT, & HW_ENT (HW_H_SLO16), CGEN_MODE_HI, & OP_ENT (SLO16), 0 },
877 { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_QI, & OP_ENT (SRC1), 0 },
878 { OUTPUT, & HW_ENT (HW_H_MEMORY), CGEN_MODE_QI, 0, 0 },
882 static const CGEN_OPERAND_INSTANCE fmt_sth_ops[] = {
883 { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_USI, & OP_ENT (SRC2), 0 },
884 { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_HI, & OP_ENT (SRC1), 0 },
885 { OUTPUT, & HW_ENT (HW_H_MEMORY), CGEN_MODE_HI, 0, 0 },
889 static const CGEN_OPERAND_INSTANCE fmt_sth_d_ops[] = {
890 { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC2), 0 },
891 { INPUT, & HW_ENT (HW_H_SLO16), CGEN_MODE_HI, & OP_ENT (SLO16), 0 },
892 { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_HI, & OP_ENT (SRC1), 0 },
893 { OUTPUT, & HW_ENT (HW_H_MEMORY), CGEN_MODE_HI, 0, 0 },
897 static const CGEN_OPERAND_INSTANCE fmt_st_plus_ops[] = {
898 { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC2), 0 },
899 { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC1), 0 },
900 { OUTPUT, & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0 },
901 { OUTPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC2), 0 },
905 static const CGEN_OPERAND_INSTANCE fmt_trap_ops[] = {
906 { INPUT, & HW_ENT (HW_H_PC), CGEN_MODE_USI, 0, 0 },
907 { INPUT, & HW_ENT (HW_H_CR), CGEN_MODE_USI, 0, 0 },
908 { INPUT, & HW_ENT (HW_H_UINT), CGEN_MODE_SI, & OP_ENT (UIMM4), 0 },
909 { OUTPUT, & HW_ENT (HW_H_CR), CGEN_MODE_USI, 0, 6 },
910 { OUTPUT, & HW_ENT (HW_H_CR), CGEN_MODE_USI, 0, 0 },
911 { OUTPUT, & HW_ENT (HW_H_PC), CGEN_MODE_SI, 0, 0 },
915 static const CGEN_OPERAND_INSTANCE fmt_unlock_ops[] = {
916 { INPUT, & HW_ENT (HW_H_LOCK), CGEN_MODE_UBI, 0, 0 },
917 { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_USI, & OP_ENT (SRC2), 0 },
918 { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC1), 0 },
919 { OUTPUT, & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0 },
920 { OUTPUT, & HW_ENT (HW_H_LOCK), CGEN_MODE_UBI, 0, 0 },
924 /* start-sanitize-m32rx */
925 static const CGEN_OPERAND_INSTANCE fmt_satb_ops[] = {
926 { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SR), 0 },
927 { OUTPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0 },
931 /* end-sanitize-m32rx */
932 /* start-sanitize-m32rx */
933 static const CGEN_OPERAND_INSTANCE fmt_sat_ops[] = {
934 { INPUT, & HW_ENT (HW_H_COND), CGEN_MODE_UBI, 0, 0 },
935 { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SR), 0 },
936 { OUTPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0 },
940 /* end-sanitize-m32rx */
941 /* start-sanitize-m32rx */
942 static const CGEN_OPERAND_INSTANCE fmt_sadd_ops[] = {
943 { INPUT, & HW_ENT (HW_H_ACCUMS), CGEN_MODE_DI, 0, 1 },
944 { INPUT, & HW_ENT (HW_H_ACCUMS), CGEN_MODE_DI, 0, 0 },
945 { OUTPUT, & HW_ENT (HW_H_ACCUMS), CGEN_MODE_DI, 0, 0 },
949 /* end-sanitize-m32rx */
950 /* start-sanitize-m32rx */
951 static const CGEN_OPERAND_INSTANCE fmt_macwu1_ops[] = {
952 { INPUT, & HW_ENT (HW_H_ACCUMS), CGEN_MODE_DI, 0, 1 },
953 { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC1), 0 },
954 { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC2), 0 },
955 { OUTPUT, & HW_ENT (HW_H_ACCUMS), CGEN_MODE_DI, 0, 1 },
959 /* end-sanitize-m32rx */
960 /* start-sanitize-m32rx */
961 static const CGEN_OPERAND_INSTANCE fmt_mulwu1_ops[] = {
962 { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC1), 0 },
963 { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC2), 0 },
964 { OUTPUT, & HW_ENT (HW_H_ACCUMS), CGEN_MODE_DI, 0, 1 },
968 /* end-sanitize-m32rx */
969 /* start-sanitize-m32rx */
970 static const CGEN_OPERAND_INSTANCE fmt_sc_ops[] = {
971 { INPUT, & HW_ENT (HW_H_COND), CGEN_MODE_UBI, 0, 0 },
975 /* end-sanitize-m32rx */
979 #define A(a) (1 << CONCAT2 (CGEN_INSN_,a))
980 #define MNEM CGEN_SYNTAX_MNEMONIC /* syntax value for mnemonic */
981 #define OP(field) CGEN_SYNTAX_MAKE_FIELD (OPERAND (field))
983 /* The instruction table.
984 This is currently non-static because the simulator accesses it
987 const CGEN_INSN m32r_cgen_insn_table_entries[MAX_INSNS] =
989 /* Special null first entry.
990 A `num' value of zero is thus illegal.
991 Also, the special `illegal' insn resides here. */
996 M32R_INSN_ADD, "add", "add",
997 { MNEM, ' ', OP (DR), ',', OP (SR), 0 },
998 { 16, 16, 0xf0f0 }, 0xa0,
999 (PTR) & fmt_add_ops[0],
1000 { CGEN_INSN_NBOOL_ATTRS, 0|A(PARALLEL), { (1<<MACH_M32R), PIPE_OS } }
1002 /* add3 $dr,$sr,$hash$slo16 */
1005 M32R_INSN_ADD3, "add3", "add3",
1006 { MNEM, ' ', OP (DR), ',', OP (SR), ',', OP (HASH), OP (SLO16), 0 },
1007 { 32, 32, 0xf0f00000 }, 0x80a00000,
1008 (PTR) & fmt_add3_ops[0],
1009 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_NONE } }
1014 M32R_INSN_AND, "and", "and",
1015 { MNEM, ' ', OP (DR), ',', OP (SR), 0 },
1016 { 16, 16, 0xf0f0 }, 0xc0,
1017 (PTR) & fmt_add_ops[0],
1018 { CGEN_INSN_NBOOL_ATTRS, 0|A(PARALLEL), { (1<<MACH_M32R), PIPE_OS } }
1020 /* and3 $dr,$sr,$uimm16 */
1023 M32R_INSN_AND3, "and3", "and3",
1024 { MNEM, ' ', OP (DR), ',', OP (SR), ',', OP (UIMM16), 0 },
1025 { 32, 32, 0xf0f00000 }, 0x80c00000,
1026 (PTR) & fmt_and3_ops[0],
1027 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_NONE } }
1032 M32R_INSN_OR, "or", "or",
1033 { MNEM, ' ', OP (DR), ',', OP (SR), 0 },
1034 { 16, 16, 0xf0f0 }, 0xe0,
1035 (PTR) & fmt_add_ops[0],
1036 { CGEN_INSN_NBOOL_ATTRS, 0|A(PARALLEL), { (1<<MACH_M32R), PIPE_OS } }
1038 /* or3 $dr,$sr,$hash$ulo16 */
1041 M32R_INSN_OR3, "or3", "or3",
1042 { MNEM, ' ', OP (DR), ',', OP (SR), ',', OP (HASH), OP (ULO16), 0 },
1043 { 32, 32, 0xf0f00000 }, 0x80e00000,
1044 (PTR) & fmt_or3_ops[0],
1045 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_NONE } }
1050 M32R_INSN_XOR, "xor", "xor",
1051 { MNEM, ' ', OP (DR), ',', OP (SR), 0 },
1052 { 16, 16, 0xf0f0 }, 0xd0,
1053 (PTR) & fmt_add_ops[0],
1054 { CGEN_INSN_NBOOL_ATTRS, 0|A(PARALLEL), { (1<<MACH_M32R), PIPE_OS } }
1056 /* xor3 $dr,$sr,$uimm16 */
1059 M32R_INSN_XOR3, "xor3", "xor3",
1060 { MNEM, ' ', OP (DR), ',', OP (SR), ',', OP (UIMM16), 0 },
1061 { 32, 32, 0xf0f00000 }, 0x80d00000,
1062 (PTR) & fmt_and3_ops[0],
1063 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_NONE } }
1065 /* addi $dr,$simm8 */
1068 M32R_INSN_ADDI, "addi", "addi",
1069 { MNEM, ' ', OP (DR), ',', OP (SIMM8), 0 },
1070 { 16, 16, 0xf000 }, 0x4000,
1071 (PTR) & fmt_addi_ops[0],
1072 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_OS } }
1077 M32R_INSN_ADDV, "addv", "addv",
1078 { MNEM, ' ', OP (DR), ',', OP (SR), 0 },
1079 { 16, 16, 0xf0f0 }, 0x80,
1080 (PTR) & fmt_addv_ops[0],
1081 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_OS } }
1083 /* addv3 $dr,$sr,$simm16 */
1086 M32R_INSN_ADDV3, "addv3", "addv3",
1087 { MNEM, ' ', OP (DR), ',', OP (SR), ',', OP (SIMM16), 0 },
1088 { 32, 32, 0xf0f00000 }, 0x80800000,
1089 (PTR) & fmt_addv3_ops[0],
1090 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_NONE } }
1095 M32R_INSN_ADDX, "addx", "addx",
1096 { MNEM, ' ', OP (DR), ',', OP (SR), 0 },
1097 { 16, 16, 0xf0f0 }, 0x90,
1098 (PTR) & fmt_addx_ops[0],
1099 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_OS } }
1104 M32R_INSN_BC8, "bc8", "bc.s",
1105 { MNEM, ' ', OP (DISP8), 0 },
1106 { 16, 16, 0xff00 }, 0x7c00,
1107 (PTR) & fmt_bc8_ops[0],
1108 { CGEN_INSN_NBOOL_ATTRS, 0|A(COND_CTI), { (1<<MACH_M32R), PIPE_O } }
1113 M32R_INSN_BC24, "bc24", "bc.l",
1114 { MNEM, ' ', OP (DISP24), 0 },
1115 { 32, 32, 0xff000000 }, 0xfc000000,
1116 (PTR) & fmt_bc24_ops[0],
1117 { CGEN_INSN_NBOOL_ATTRS, 0|A(COND_CTI), { (1<<MACH_M32R), PIPE_NONE } }
1119 /* beq $src1,$src2,$disp16 */
1122 M32R_INSN_BEQ, "beq", "beq",
1123 { MNEM, ' ', OP (SRC1), ',', OP (SRC2), ',', OP (DISP16), 0 },
1124 { 32, 32, 0xf0f00000 }, 0xb0000000,
1125 (PTR) & fmt_beq_ops[0],
1126 { CGEN_INSN_NBOOL_ATTRS, 0|A(COND_CTI), { (1<<MACH_M32R), PIPE_NONE } }
1128 /* beqz $src2,$disp16 */
1131 M32R_INSN_BEQZ, "beqz", "beqz",
1132 { MNEM, ' ', OP (SRC2), ',', OP (DISP16), 0 },
1133 { 32, 32, 0xfff00000 }, 0xb0800000,
1134 (PTR) & fmt_beqz_ops[0],
1135 { CGEN_INSN_NBOOL_ATTRS, 0|A(COND_CTI), { (1<<MACH_M32R), PIPE_NONE } }
1137 /* bgez $src2,$disp16 */
1140 M32R_INSN_BGEZ, "bgez", "bgez",
1141 { MNEM, ' ', OP (SRC2), ',', OP (DISP16), 0 },
1142 { 32, 32, 0xfff00000 }, 0xb0b00000,
1143 (PTR) & fmt_beqz_ops[0],
1144 { CGEN_INSN_NBOOL_ATTRS, 0|A(COND_CTI), { (1<<MACH_M32R), PIPE_NONE } }
1146 /* bgtz $src2,$disp16 */
1149 M32R_INSN_BGTZ, "bgtz", "bgtz",
1150 { MNEM, ' ', OP (SRC2), ',', OP (DISP16), 0 },
1151 { 32, 32, 0xfff00000 }, 0xb0d00000,
1152 (PTR) & fmt_beqz_ops[0],
1153 { CGEN_INSN_NBOOL_ATTRS, 0|A(COND_CTI), { (1<<MACH_M32R), PIPE_NONE } }
1155 /* blez $src2,$disp16 */
1158 M32R_INSN_BLEZ, "blez", "blez",
1159 { MNEM, ' ', OP (SRC2), ',', OP (DISP16), 0 },
1160 { 32, 32, 0xfff00000 }, 0xb0c00000,
1161 (PTR) & fmt_beqz_ops[0],
1162 { CGEN_INSN_NBOOL_ATTRS, 0|A(COND_CTI), { (1<<MACH_M32R), PIPE_NONE } }
1164 /* bltz $src2,$disp16 */
1167 M32R_INSN_BLTZ, "bltz", "bltz",
1168 { MNEM, ' ', OP (SRC2), ',', OP (DISP16), 0 },
1169 { 32, 32, 0xfff00000 }, 0xb0a00000,
1170 (PTR) & fmt_beqz_ops[0],
1171 { CGEN_INSN_NBOOL_ATTRS, 0|A(COND_CTI), { (1<<MACH_M32R), PIPE_NONE } }
1173 /* bnez $src2,$disp16 */
1176 M32R_INSN_BNEZ, "bnez", "bnez",
1177 { MNEM, ' ', OP (SRC2), ',', OP (DISP16), 0 },
1178 { 32, 32, 0xfff00000 }, 0xb0900000,
1179 (PTR) & fmt_beqz_ops[0],
1180 { CGEN_INSN_NBOOL_ATTRS, 0|A(COND_CTI), { (1<<MACH_M32R), PIPE_NONE } }
1185 M32R_INSN_BL8, "bl8", "bl.s",
1186 { MNEM, ' ', OP (DISP8), 0 },
1187 { 16, 16, 0xff00 }, 0x7e00,
1188 (PTR) & fmt_bl8_ops[0],
1189 { CGEN_INSN_NBOOL_ATTRS, 0|A(FILL_SLOT)|A(UNCOND_CTI), { (1<<MACH_M32R), PIPE_O } }
1194 M32R_INSN_BL24, "bl24", "bl.l",
1195 { MNEM, ' ', OP (DISP24), 0 },
1196 { 32, 32, 0xff000000 }, 0xfe000000,
1197 (PTR) & fmt_bl24_ops[0],
1198 { CGEN_INSN_NBOOL_ATTRS, 0|A(UNCOND_CTI), { (1<<MACH_M32R), PIPE_NONE } }
1200 /* start-sanitize-m32rx */
1204 M32R_INSN_BCL8, "bcl8", "bcl.s",
1205 { MNEM, ' ', OP (DISP8), 0 },
1206 { 16, 16, 0xff00 }, 0x7800,
1207 (PTR) & fmt_bcl8_ops[0],
1208 { CGEN_INSN_NBOOL_ATTRS, 0|A(COND_CTI), { (1<<MACH_M32RX), PIPE_O } }
1210 /* end-sanitize-m32rx */
1211 /* start-sanitize-m32rx */
1215 M32R_INSN_BCL24, "bcl24", "bcl.l",
1216 { MNEM, ' ', OP (DISP24), 0 },
1217 { 32, 32, 0xff000000 }, 0xf8000000,
1218 (PTR) & fmt_bcl24_ops[0],
1219 { CGEN_INSN_NBOOL_ATTRS, 0|A(COND_CTI), { (1<<MACH_M32RX), PIPE_NONE } }
1221 /* end-sanitize-m32rx */
1225 M32R_INSN_BNC8, "bnc8", "bnc.s",
1226 { MNEM, ' ', OP (DISP8), 0 },
1227 { 16, 16, 0xff00 }, 0x7d00,
1228 (PTR) & fmt_bc8_ops[0],
1229 { CGEN_INSN_NBOOL_ATTRS, 0|A(COND_CTI), { (1<<MACH_M32R), PIPE_O } }
1234 M32R_INSN_BNC24, "bnc24", "bnc.l",
1235 { MNEM, ' ', OP (DISP24), 0 },
1236 { 32, 32, 0xff000000 }, 0xfd000000,
1237 (PTR) & fmt_bc24_ops[0],
1238 { CGEN_INSN_NBOOL_ATTRS, 0|A(COND_CTI), { (1<<MACH_M32R), PIPE_NONE } }
1240 /* bne $src1,$src2,$disp16 */
1243 M32R_INSN_BNE, "bne", "bne",
1244 { MNEM, ' ', OP (SRC1), ',', OP (SRC2), ',', OP (DISP16), 0 },
1245 { 32, 32, 0xf0f00000 }, 0xb0100000,
1246 (PTR) & fmt_beq_ops[0],
1247 { CGEN_INSN_NBOOL_ATTRS, 0|A(COND_CTI), { (1<<MACH_M32R), PIPE_NONE } }
1252 M32R_INSN_BRA8, "bra8", "bra.s",
1253 { MNEM, ' ', OP (DISP8), 0 },
1254 { 16, 16, 0xff00 }, 0x7f00,
1255 (PTR) & fmt_bra8_ops[0],
1256 { CGEN_INSN_NBOOL_ATTRS, 0|A(FILL_SLOT)|A(UNCOND_CTI), { (1<<MACH_M32R), PIPE_O } }
1261 M32R_INSN_BRA24, "bra24", "bra.l",
1262 { MNEM, ' ', OP (DISP24), 0 },
1263 { 32, 32, 0xff000000 }, 0xff000000,
1264 (PTR) & fmt_bra24_ops[0],
1265 { CGEN_INSN_NBOOL_ATTRS, 0|A(UNCOND_CTI), { (1<<MACH_M32R), PIPE_NONE } }
1267 /* start-sanitize-m32rx */
1271 M32R_INSN_BNCL8, "bncl8", "bncl.s",
1272 { MNEM, ' ', OP (DISP8), 0 },
1273 { 16, 16, 0xff00 }, 0x7900,
1274 (PTR) & fmt_bcl8_ops[0],
1275 { CGEN_INSN_NBOOL_ATTRS, 0|A(COND_CTI), { (1<<MACH_M32RX), PIPE_O } }
1277 /* end-sanitize-m32rx */
1278 /* start-sanitize-m32rx */
1279 /* bncl.l $disp24 */
1282 M32R_INSN_BNCL24, "bncl24", "bncl.l",
1283 { MNEM, ' ', OP (DISP24), 0 },
1284 { 32, 32, 0xff000000 }, 0xf9000000,
1285 (PTR) & fmt_bcl24_ops[0],
1286 { CGEN_INSN_NBOOL_ATTRS, 0|A(COND_CTI), { (1<<MACH_M32RX), PIPE_NONE } }
1288 /* end-sanitize-m32rx */
1289 /* cmp $src1,$src2 */
1292 M32R_INSN_CMP, "cmp", "cmp",
1293 { MNEM, ' ', OP (SRC1), ',', OP (SRC2), 0 },
1294 { 16, 16, 0xf0f0 }, 0x40,
1295 (PTR) & fmt_cmp_ops[0],
1296 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_OS } }
1298 /* cmpi $src2,$simm16 */
1301 M32R_INSN_CMPI, "cmpi", "cmpi",
1302 { MNEM, ' ', OP (SRC2), ',', OP (SIMM16), 0 },
1303 { 32, 32, 0xfff00000 }, 0x80400000,
1304 (PTR) & fmt_cmpi_ops[0],
1305 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_NONE } }
1307 /* cmpu $src1,$src2 */
1310 M32R_INSN_CMPU, "cmpu", "cmpu",
1311 { MNEM, ' ', OP (SRC1), ',', OP (SRC2), 0 },
1312 { 16, 16, 0xf0f0 }, 0x50,
1313 (PTR) & fmt_cmp_ops[0],
1314 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_OS } }
1316 /* cmpui $src2,$simm16 */
1319 M32R_INSN_CMPUI, "cmpui", "cmpui",
1320 { MNEM, ' ', OP (SRC2), ',', OP (SIMM16), 0 },
1321 { 32, 32, 0xfff00000 }, 0x80500000,
1322 (PTR) & fmt_cmpi_ops[0],
1323 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_NONE } }
1325 /* start-sanitize-m32rx */
1326 /* cmpeq $src1,$src2 */
1329 M32R_INSN_CMPEQ, "cmpeq", "cmpeq",
1330 { MNEM, ' ', OP (SRC1), ',', OP (SRC2), 0 },
1331 { 16, 16, 0xf0f0 }, 0x60,
1332 (PTR) & fmt_cmp_ops[0],
1333 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32RX), PIPE_OS } }
1335 /* end-sanitize-m32rx */
1336 /* start-sanitize-m32rx */
1340 M32R_INSN_CMPZ, "cmpz", "cmpz",
1341 { MNEM, ' ', OP (SRC2), 0 },
1342 { 16, 16, 0xfff0 }, 0x70,
1343 (PTR) & fmt_cmpz_ops[0],
1344 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32RX), PIPE_OS } }
1346 /* end-sanitize-m32rx */
1350 M32R_INSN_DIV, "div", "div",
1351 { MNEM, ' ', OP (DR), ',', OP (SR), 0 },
1352 { 32, 32, 0xf0f0ffff }, 0x90000000,
1353 (PTR) & fmt_div_ops[0],
1354 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_NONE } }
1359 M32R_INSN_DIVU, "divu", "divu",
1360 { MNEM, ' ', OP (DR), ',', OP (SR), 0 },
1361 { 32, 32, 0xf0f0ffff }, 0x90100000,
1362 (PTR) & fmt_div_ops[0],
1363 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_NONE } }
1368 M32R_INSN_REM, "rem", "rem",
1369 { MNEM, ' ', OP (DR), ',', OP (SR), 0 },
1370 { 32, 32, 0xf0f0ffff }, 0x90200000,
1371 (PTR) & fmt_div_ops[0],
1372 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_NONE } }
1377 M32R_INSN_REMU, "remu", "remu",
1378 { MNEM, ' ', OP (DR), ',', OP (SR), 0 },
1379 { 32, 32, 0xf0f0ffff }, 0x90300000,
1380 (PTR) & fmt_div_ops[0],
1381 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_NONE } }
1383 /* start-sanitize-m32rx */
1387 M32R_INSN_DIVH, "divh", "divh",
1388 { MNEM, ' ', OP (DR), ',', OP (SR), 0 },
1389 { 32, 32, 0xf0f0ffff }, 0x90000010,
1390 (PTR) & fmt_div_ops[0],
1391 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32RX), PIPE_NONE } }
1393 /* end-sanitize-m32rx */
1394 /* start-sanitize-m32rx */
1398 M32R_INSN_JC, "jc", "jc",
1399 { MNEM, ' ', OP (SR), 0 },
1400 { 16, 16, 0xfff0 }, 0x1cc0,
1401 (PTR) & fmt_jc_ops[0],
1402 { CGEN_INSN_NBOOL_ATTRS, 0|A(SPECIAL)|A(COND_CTI), { (1<<MACH_M32RX), PIPE_O } }
1404 /* end-sanitize-m32rx */
1405 /* start-sanitize-m32rx */
1409 M32R_INSN_JNC, "jnc", "jnc",
1410 { MNEM, ' ', OP (SR), 0 },
1411 { 16, 16, 0xfff0 }, 0x1dc0,
1412 (PTR) & fmt_jc_ops[0],
1413 { CGEN_INSN_NBOOL_ATTRS, 0|A(SPECIAL)|A(COND_CTI), { (1<<MACH_M32RX), PIPE_O } }
1415 /* end-sanitize-m32rx */
1419 M32R_INSN_JL, "jl", "jl",
1420 { MNEM, ' ', OP (SR), 0 },
1421 { 16, 16, 0xfff0 }, 0x1ec0,
1422 (PTR) & fmt_jl_ops[0],
1423 { CGEN_INSN_NBOOL_ATTRS, 0|A(FILL_SLOT)|A(UNCOND_CTI), { (1<<MACH_M32R), PIPE_O } }
1428 M32R_INSN_JMP, "jmp", "jmp",
1429 { MNEM, ' ', OP (SR), 0 },
1430 { 16, 16, 0xfff0 }, 0x1fc0,
1431 (PTR) & fmt_jmp_ops[0],
1432 { CGEN_INSN_NBOOL_ATTRS, 0|A(UNCOND_CTI), { (1<<MACH_M32R), PIPE_O } }
1437 M32R_INSN_LD, "ld", "ld",
1438 { MNEM, ' ', OP (DR), ',', '@', OP (SR), 0 },
1439 { 16, 16, 0xf0f0 }, 0x20c0,
1440 (PTR) & fmt_ld_ops[0],
1441 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_O } }
1443 /* ld $dr,@($slo16,$sr) */
1446 M32R_INSN_LD_D, "ld-d", "ld",
1447 { MNEM, ' ', OP (DR), ',', '@', '(', OP (SLO16), ',', OP (SR), ')', 0 },
1448 { 32, 32, 0xf0f00000 }, 0xa0c00000,
1449 (PTR) & fmt_ld_d_ops[0],
1450 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_NONE } }
1455 M32R_INSN_LDB, "ldb", "ldb",
1456 { MNEM, ' ', OP (DR), ',', '@', OP (SR), 0 },
1457 { 16, 16, 0xf0f0 }, 0x2080,
1458 (PTR) & fmt_ldb_ops[0],
1459 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_O } }
1461 /* ldb $dr,@($slo16,$sr) */
1464 M32R_INSN_LDB_D, "ldb-d", "ldb",
1465 { MNEM, ' ', OP (DR), ',', '@', '(', OP (SLO16), ',', OP (SR), ')', 0 },
1466 { 32, 32, 0xf0f00000 }, 0xa0800000,
1467 (PTR) & fmt_ldb_d_ops[0],
1468 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_NONE } }
1473 M32R_INSN_LDH, "ldh", "ldh",
1474 { MNEM, ' ', OP (DR), ',', '@', OP (SR), 0 },
1475 { 16, 16, 0xf0f0 }, 0x20a0,
1476 (PTR) & fmt_ldh_ops[0],
1477 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_O } }
1479 /* ldh $dr,@($slo16,$sr) */
1482 M32R_INSN_LDH_D, "ldh-d", "ldh",
1483 { MNEM, ' ', OP (DR), ',', '@', '(', OP (SLO16), ',', OP (SR), ')', 0 },
1484 { 32, 32, 0xf0f00000 }, 0xa0a00000,
1485 (PTR) & fmt_ldh_d_ops[0],
1486 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_NONE } }
1491 M32R_INSN_LDUB, "ldub", "ldub",
1492 { MNEM, ' ', OP (DR), ',', '@', OP (SR), 0 },
1493 { 16, 16, 0xf0f0 }, 0x2090,
1494 (PTR) & fmt_ldb_ops[0],
1495 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_O } }
1497 /* ldub $dr,@($slo16,$sr) */
1500 M32R_INSN_LDUB_D, "ldub-d", "ldub",
1501 { MNEM, ' ', OP (DR), ',', '@', '(', OP (SLO16), ',', OP (SR), ')', 0 },
1502 { 32, 32, 0xf0f00000 }, 0xa0900000,
1503 (PTR) & fmt_ldb_d_ops[0],
1504 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_NONE } }
1509 M32R_INSN_LDUH, "lduh", "lduh",
1510 { MNEM, ' ', OP (DR), ',', '@', OP (SR), 0 },
1511 { 16, 16, 0xf0f0 }, 0x20b0,
1512 (PTR) & fmt_ldh_ops[0],
1513 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_O } }
1515 /* lduh $dr,@($slo16,$sr) */
1518 M32R_INSN_LDUH_D, "lduh-d", "lduh",
1519 { MNEM, ' ', OP (DR), ',', '@', '(', OP (SLO16), ',', OP (SR), ')', 0 },
1520 { 32, 32, 0xf0f00000 }, 0xa0b00000,
1521 (PTR) & fmt_ldh_d_ops[0],
1522 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_NONE } }
1527 M32R_INSN_LD_PLUS, "ld-plus", "ld",
1528 { MNEM, ' ', OP (DR), ',', '@', OP (SR), '+', 0 },
1529 { 16, 16, 0xf0f0 }, 0x20e0,
1530 (PTR) & fmt_ld_plus_ops[0],
1531 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_O } }
1533 /* ld24 $dr,$uimm24 */
1536 M32R_INSN_LD24, "ld24", "ld24",
1537 { MNEM, ' ', OP (DR), ',', OP (UIMM24), 0 },
1538 { 32, 32, 0xf0000000 }, 0xe0000000,
1539 (PTR) & fmt_ld24_ops[0],
1540 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_NONE } }
1542 /* ldi8 $dr,$simm8 */
1545 M32R_INSN_LDI8, "ldi8", "ldi8",
1546 { MNEM, ' ', OP (DR), ',', OP (SIMM8), 0 },
1547 { 16, 16, 0xf000 }, 0x6000,
1548 (PTR) & fmt_ldi8_ops[0],
1549 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_OS } }
1551 /* ldi16 $dr,$hash$slo16 */
1554 M32R_INSN_LDI16, "ldi16", "ldi16",
1555 { MNEM, ' ', OP (DR), ',', OP (HASH), OP (SLO16), 0 },
1556 { 32, 32, 0xf0ff0000 }, 0x90f00000,
1557 (PTR) & fmt_ldi16_ops[0],
1558 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_NONE } }
1563 M32R_INSN_LOCK, "lock", "lock",
1564 { MNEM, ' ', OP (DR), ',', '@', OP (SR), 0 },
1565 { 16, 16, 0xf0f0 }, 0x20d0,
1566 (PTR) & fmt_lock_ops[0],
1567 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_O } }
1569 /* machi $src1,$src2 */
1572 M32R_INSN_MACHI, "machi", "machi",
1573 { MNEM, ' ', OP (SRC1), ',', OP (SRC2), 0 },
1574 { 16, 16, 0xf0f0 }, 0x3040,
1575 (PTR) & fmt_machi_ops[0],
1576 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_S } }
1578 /* start-sanitize-m32rx */
1579 /* machi $src1,$src2,$acc */
1582 M32R_INSN_MACHI_A, "machi-a", "machi",
1583 { MNEM, ' ', OP (SRC1), ',', OP (SRC2), ',', OP (ACC), 0 },
1584 { 16, 16, 0xf070 }, 0x3040,
1585 (PTR) & fmt_machi_a_ops[0],
1586 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32RX), PIPE_S } }
1588 /* end-sanitize-m32rx */
1589 /* maclo $src1,$src2 */
1592 M32R_INSN_MACLO, "maclo", "maclo",
1593 { MNEM, ' ', OP (SRC1), ',', OP (SRC2), 0 },
1594 { 16, 16, 0xf0f0 }, 0x3050,
1595 (PTR) & fmt_machi_ops[0],
1596 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_S } }
1598 /* start-sanitize-m32rx */
1599 /* maclo $src1,$src2,$acc */
1602 M32R_INSN_MACLO_A, "maclo-a", "maclo",
1603 { MNEM, ' ', OP (SRC1), ',', OP (SRC2), ',', OP (ACC), 0 },
1604 { 16, 16, 0xf070 }, 0x3050,
1605 (PTR) & fmt_machi_a_ops[0],
1606 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32RX), PIPE_S } }
1608 /* end-sanitize-m32rx */
1609 /* macwhi $src1,$src2 */
1612 M32R_INSN_MACWHI, "macwhi", "macwhi",
1613 { MNEM, ' ', OP (SRC1), ',', OP (SRC2), 0 },
1614 { 16, 16, 0xf0f0 }, 0x3060,
1615 (PTR) & fmt_machi_ops[0],
1616 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_S } }
1618 /* macwlo $src1,$src2 */
1621 M32R_INSN_MACWLO, "macwlo", "macwlo",
1622 { MNEM, ' ', OP (SRC1), ',', OP (SRC2), 0 },
1623 { 16, 16, 0xf0f0 }, 0x3070,
1624 (PTR) & fmt_machi_ops[0],
1625 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_S } }
1630 M32R_INSN_MUL, "mul", "mul",
1631 { MNEM, ' ', OP (DR), ',', OP (SR), 0 },
1632 { 16, 16, 0xf0f0 }, 0x1060,
1633 (PTR) & fmt_add_ops[0],
1634 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_S } }
1636 /* mulhi $src1,$src2 */
1639 M32R_INSN_MULHI, "mulhi", "mulhi",
1640 { MNEM, ' ', OP (SRC1), ',', OP (SRC2), 0 },
1641 { 16, 16, 0xf0f0 }, 0x3000,
1642 (PTR) & fmt_mulhi_ops[0],
1643 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_S } }
1645 /* start-sanitize-m32rx */
1646 /* mulhi $src1,$src2,$acc */
1649 M32R_INSN_MULHI_A, "mulhi-a", "mulhi",
1650 { MNEM, ' ', OP (SRC1), ',', OP (SRC2), ',', OP (ACC), 0 },
1651 { 16, 16, 0xf070 }, 0x3000,
1652 (PTR) & fmt_mulhi_a_ops[0],
1653 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32RX), PIPE_S } }
1655 /* end-sanitize-m32rx */
1656 /* mullo $src1,$src2 */
1659 M32R_INSN_MULLO, "mullo", "mullo",
1660 { MNEM, ' ', OP (SRC1), ',', OP (SRC2), 0 },
1661 { 16, 16, 0xf0f0 }, 0x3010,
1662 (PTR) & fmt_mulhi_ops[0],
1663 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_S } }
1665 /* start-sanitize-m32rx */
1666 /* mullo $src1,$src2,$acc */
1669 M32R_INSN_MULLO_A, "mullo-a", "mullo",
1670 { MNEM, ' ', OP (SRC1), ',', OP (SRC2), ',', OP (ACC), 0 },
1671 { 16, 16, 0xf070 }, 0x3010,
1672 (PTR) & fmt_mulhi_a_ops[0],
1673 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32RX), PIPE_S } }
1675 /* end-sanitize-m32rx */
1676 /* mulwhi $src1,$src2 */
1679 M32R_INSN_MULWHI, "mulwhi", "mulwhi",
1680 { MNEM, ' ', OP (SRC1), ',', OP (SRC2), 0 },
1681 { 16, 16, 0xf0f0 }, 0x3020,
1682 (PTR) & fmt_mulhi_ops[0],
1683 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_S } }
1685 /* mulwlo $src1,$src2 */
1688 M32R_INSN_MULWLO, "mulwlo", "mulwlo",
1689 { MNEM, ' ', OP (SRC1), ',', OP (SRC2), 0 },
1690 { 16, 16, 0xf0f0 }, 0x3030,
1691 (PTR) & fmt_mulhi_ops[0],
1692 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_S } }
1697 M32R_INSN_MV, "mv", "mv",
1698 { MNEM, ' ', OP (DR), ',', OP (SR), 0 },
1699 { 16, 16, 0xf0f0 }, 0x1080,
1700 (PTR) & fmt_mv_ops[0],
1701 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_OS } }
1706 M32R_INSN_MVFACHI, "mvfachi", "mvfachi",
1707 { MNEM, ' ', OP (DR), 0 },
1708 { 16, 16, 0xf0ff }, 0x50f0,
1709 (PTR) & fmt_mvfachi_ops[0],
1710 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_S } }
1712 /* start-sanitize-m32rx */
1713 /* mvfachi $dr,$accs */
1716 M32R_INSN_MVFACHI_A, "mvfachi-a", "mvfachi",
1717 { MNEM, ' ', OP (DR), ',', OP (ACCS), 0 },
1718 { 16, 16, 0xf0f3 }, 0x50f0,
1719 (PTR) & fmt_mvfachi_a_ops[0],
1720 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32RX), PIPE_S } }
1722 /* end-sanitize-m32rx */
1726 M32R_INSN_MVFACLO, "mvfaclo", "mvfaclo",
1727 { MNEM, ' ', OP (DR), 0 },
1728 { 16, 16, 0xf0ff }, 0x50f1,
1729 (PTR) & fmt_mvfachi_ops[0],
1730 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_S } }
1732 /* start-sanitize-m32rx */
1733 /* mvfaclo $dr,$accs */
1736 M32R_INSN_MVFACLO_A, "mvfaclo-a", "mvfaclo",
1737 { MNEM, ' ', OP (DR), ',', OP (ACCS), 0 },
1738 { 16, 16, 0xf0f3 }, 0x50f1,
1739 (PTR) & fmt_mvfachi_a_ops[0],
1740 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32RX), PIPE_S } }
1742 /* end-sanitize-m32rx */
1746 M32R_INSN_MVFACMI, "mvfacmi", "mvfacmi",
1747 { MNEM, ' ', OP (DR), 0 },
1748 { 16, 16, 0xf0ff }, 0x50f2,
1749 (PTR) & fmt_mvfachi_ops[0],
1750 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_S } }
1752 /* start-sanitize-m32rx */
1753 /* mvfacmi $dr,$accs */
1756 M32R_INSN_MVFACMI_A, "mvfacmi-a", "mvfacmi",
1757 { MNEM, ' ', OP (DR), ',', OP (ACCS), 0 },
1758 { 16, 16, 0xf0f3 }, 0x50f2,
1759 (PTR) & fmt_mvfachi_a_ops[0],
1760 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32RX), PIPE_S } }
1762 /* end-sanitize-m32rx */
1766 M32R_INSN_MVFC, "mvfc", "mvfc",
1767 { MNEM, ' ', OP (DR), ',', OP (SCR), 0 },
1768 { 16, 16, 0xf0f0 }, 0x1090,
1769 (PTR) & fmt_mvfc_ops[0],
1770 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_O } }
1775 M32R_INSN_MVTACHI, "mvtachi", "mvtachi",
1776 { MNEM, ' ', OP (SRC1), 0 },
1777 { 16, 16, 0xf0ff }, 0x5070,
1778 (PTR) & fmt_mvtachi_ops[0],
1779 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_S } }
1781 /* start-sanitize-m32rx */
1782 /* mvtachi $src1,$accs */
1785 M32R_INSN_MVTACHI_A, "mvtachi-a", "mvtachi",
1786 { MNEM, ' ', OP (SRC1), ',', OP (ACCS), 0 },
1787 { 16, 16, 0xf0f3 }, 0x5070,
1788 (PTR) & fmt_mvtachi_a_ops[0],
1789 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32RX), PIPE_S } }
1791 /* end-sanitize-m32rx */
1795 M32R_INSN_MVTACLO, "mvtaclo", "mvtaclo",
1796 { MNEM, ' ', OP (SRC1), 0 },
1797 { 16, 16, 0xf0ff }, 0x5071,
1798 (PTR) & fmt_mvtachi_ops[0],
1799 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_S } }
1801 /* start-sanitize-m32rx */
1802 /* mvtaclo $src1,$accs */
1805 M32R_INSN_MVTACLO_A, "mvtaclo-a", "mvtaclo",
1806 { MNEM, ' ', OP (SRC1), ',', OP (ACCS), 0 },
1807 { 16, 16, 0xf0f3 }, 0x5071,
1808 (PTR) & fmt_mvtachi_a_ops[0],
1809 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32RX), PIPE_S } }
1811 /* end-sanitize-m32rx */
1815 M32R_INSN_MVTC, "mvtc", "mvtc",
1816 { MNEM, ' ', OP (SR), ',', OP (DCR), 0 },
1817 { 16, 16, 0xf0f0 }, 0x10a0,
1818 (PTR) & fmt_mvtc_ops[0],
1819 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_O } }
1824 M32R_INSN_NEG, "neg", "neg",
1825 { MNEM, ' ', OP (DR), ',', OP (SR), 0 },
1826 { 16, 16, 0xf0f0 }, 0x30,
1827 (PTR) & fmt_mv_ops[0],
1828 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_OS } }
1833 M32R_INSN_NOP, "nop", "nop",
1835 { 16, 16, 0xffff }, 0x7000,
1837 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_OS } }
1842 M32R_INSN_NOT, "not", "not",
1843 { MNEM, ' ', OP (DR), ',', OP (SR), 0 },
1844 { 16, 16, 0xf0f0 }, 0xb0,
1845 (PTR) & fmt_mv_ops[0],
1846 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_OS } }
1851 M32R_INSN_RAC, "rac", "rac",
1853 { 16, 16, 0xffff }, 0x5090,
1854 (PTR) & fmt_rac_ops[0],
1855 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_S } }
1857 /* start-sanitize-m32rx */
1858 /* rac $accd,$accs,$imm1 */
1861 M32R_INSN_RAC_DSI, "rac-dsi", "rac",
1862 { MNEM, ' ', OP (ACCD), ',', OP (ACCS), ',', OP (IMM1), 0 },
1863 { 16, 16, 0xf3f2 }, 0x5090,
1864 (PTR) & fmt_rac_dsi_ops[0],
1865 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32RX), PIPE_S } }
1867 /* end-sanitize-m32rx */
1871 M32R_INSN_RACH, "rach", "rach",
1873 { 16, 16, 0xffff }, 0x5080,
1874 (PTR) & fmt_rac_ops[0],
1875 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_S } }
1877 /* start-sanitize-m32rx */
1878 /* rach $accd,$accs,$imm1 */
1881 M32R_INSN_RACH_DSI, "rach-dsi", "rach",
1882 { MNEM, ' ', OP (ACCD), ',', OP (ACCS), ',', OP (IMM1), 0 },
1883 { 16, 16, 0xf3f2 }, 0x5080,
1884 (PTR) & fmt_rac_dsi_ops[0],
1885 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32RX), PIPE_S } }
1887 /* end-sanitize-m32rx */
1891 M32R_INSN_RTE, "rte", "rte",
1893 { 16, 16, 0xffff }, 0x10d6,
1894 (PTR) & fmt_rte_ops[0],
1895 { CGEN_INSN_NBOOL_ATTRS, 0|A(UNCOND_CTI), { (1<<MACH_M32R), PIPE_O } }
1897 /* seth $dr,$hash$hi16 */
1900 M32R_INSN_SETH, "seth", "seth",
1901 { MNEM, ' ', OP (DR), ',', OP (HASH), OP (HI16), 0 },
1902 { 32, 32, 0xf0ff0000 }, 0xd0c00000,
1903 (PTR) & fmt_seth_ops[0],
1904 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_NONE } }
1909 M32R_INSN_SLL, "sll", "sll",
1910 { MNEM, ' ', OP (DR), ',', OP (SR), 0 },
1911 { 16, 16, 0xf0f0 }, 0x1040,
1912 (PTR) & fmt_add_ops[0],
1913 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_O } }
1915 /* sll3 $dr,$sr,$simm16 */
1918 M32R_INSN_SLL3, "sll3", "sll3",
1919 { MNEM, ' ', OP (DR), ',', OP (SR), ',', OP (SIMM16), 0 },
1920 { 32, 32, 0xf0f00000 }, 0x90c00000,
1921 (PTR) & fmt_sll3_ops[0],
1922 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_NONE } }
1924 /* slli $dr,$uimm5 */
1927 M32R_INSN_SLLI, "slli", "slli",
1928 { MNEM, ' ', OP (DR), ',', OP (UIMM5), 0 },
1929 { 16, 16, 0xf0e0 }, 0x5040,
1930 (PTR) & fmt_slli_ops[0],
1931 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_O } }
1936 M32R_INSN_SRA, "sra", "sra",
1937 { MNEM, ' ', OP (DR), ',', OP (SR), 0 },
1938 { 16, 16, 0xf0f0 }, 0x1020,
1939 (PTR) & fmt_add_ops[0],
1940 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_O } }
1942 /* sra3 $dr,$sr,$simm16 */
1945 M32R_INSN_SRA3, "sra3", "sra3",
1946 { MNEM, ' ', OP (DR), ',', OP (SR), ',', OP (SIMM16), 0 },
1947 { 32, 32, 0xf0f00000 }, 0x90a00000,
1948 (PTR) & fmt_sll3_ops[0],
1949 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_NONE } }
1951 /* srai $dr,$uimm5 */
1954 M32R_INSN_SRAI, "srai", "srai",
1955 { MNEM, ' ', OP (DR), ',', OP (UIMM5), 0 },
1956 { 16, 16, 0xf0e0 }, 0x5020,
1957 (PTR) & fmt_slli_ops[0],
1958 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_O } }
1963 M32R_INSN_SRL, "srl", "srl",
1964 { MNEM, ' ', OP (DR), ',', OP (SR), 0 },
1965 { 16, 16, 0xf0f0 }, 0x1000,
1966 (PTR) & fmt_add_ops[0],
1967 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_O } }
1969 /* srl3 $dr,$sr,$simm16 */
1972 M32R_INSN_SRL3, "srl3", "srl3",
1973 { MNEM, ' ', OP (DR), ',', OP (SR), ',', OP (SIMM16), 0 },
1974 { 32, 32, 0xf0f00000 }, 0x90800000,
1975 (PTR) & fmt_sll3_ops[0],
1976 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_NONE } }
1978 /* srli $dr,$uimm5 */
1981 M32R_INSN_SRLI, "srli", "srli",
1982 { MNEM, ' ', OP (DR), ',', OP (UIMM5), 0 },
1983 { 16, 16, 0xf0e0 }, 0x5000,
1984 (PTR) & fmt_slli_ops[0],
1985 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_O } }
1987 /* st $src1,@$src2 */
1990 M32R_INSN_ST, "st", "st",
1991 { MNEM, ' ', OP (SRC1), ',', '@', OP (SRC2), 0 },
1992 { 16, 16, 0xf0f0 }, 0x2040,
1993 (PTR) & fmt_st_ops[0],
1994 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_O } }
1996 /* st $src1,@($slo16,$src2) */
1999 M32R_INSN_ST_D, "st-d", "st",
2000 { MNEM, ' ', OP (SRC1), ',', '@', '(', OP (SLO16), ',', OP (SRC2), ')', 0 },
2001 { 32, 32, 0xf0f00000 }, 0xa0400000,
2002 (PTR) & fmt_st_d_ops[0],
2003 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_NONE } }
2005 /* stb $src1,@$src2 */
2008 M32R_INSN_STB, "stb", "stb",
2009 { MNEM, ' ', OP (SRC1), ',', '@', OP (SRC2), 0 },
2010 { 16, 16, 0xf0f0 }, 0x2000,
2011 (PTR) & fmt_stb_ops[0],
2012 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_O } }
2014 /* stb $src1,@($slo16,$src2) */
2017 M32R_INSN_STB_D, "stb-d", "stb",
2018 { MNEM, ' ', OP (SRC1), ',', '@', '(', OP (SLO16), ',', OP (SRC2), ')', 0 },
2019 { 32, 32, 0xf0f00000 }, 0xa0000000,
2020 (PTR) & fmt_stb_d_ops[0],
2021 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_NONE } }
2023 /* sth $src1,@$src2 */
2026 M32R_INSN_STH, "sth", "sth",
2027 { MNEM, ' ', OP (SRC1), ',', '@', OP (SRC2), 0 },
2028 { 16, 16, 0xf0f0 }, 0x2020,
2029 (PTR) & fmt_sth_ops[0],
2030 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_O } }
2032 /* sth $src1,@($slo16,$src2) */
2035 M32R_INSN_STH_D, "sth-d", "sth",
2036 { MNEM, ' ', OP (SRC1), ',', '@', '(', OP (SLO16), ',', OP (SRC2), ')', 0 },
2037 { 32, 32, 0xf0f00000 }, 0xa0200000,
2038 (PTR) & fmt_sth_d_ops[0],
2039 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_NONE } }
2041 /* st $src1,@+$src2 */
2044 M32R_INSN_ST_PLUS, "st-plus", "st",
2045 { MNEM, ' ', OP (SRC1), ',', '@', '+', OP (SRC2), 0 },
2046 { 16, 16, 0xf0f0 }, 0x2060,
2047 (PTR) & fmt_st_plus_ops[0],
2048 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_O } }
2050 /* st $src1,@-$src2 */
2053 M32R_INSN_ST_MINUS, "st-minus", "st",
2054 { MNEM, ' ', OP (SRC1), ',', '@', '-', OP (SRC2), 0 },
2055 { 16, 16, 0xf0f0 }, 0x2070,
2056 (PTR) & fmt_st_plus_ops[0],
2057 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_O } }
2062 M32R_INSN_SUB, "sub", "sub",
2063 { MNEM, ' ', OP (DR), ',', OP (SR), 0 },
2064 { 16, 16, 0xf0f0 }, 0x20,
2065 (PTR) & fmt_add_ops[0],
2066 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_OS } }
2071 M32R_INSN_SUBV, "subv", "subv",
2072 { MNEM, ' ', OP (DR), ',', OP (SR), 0 },
2073 { 16, 16, 0xf0f0 }, 0x0,
2074 (PTR) & fmt_addv_ops[0],
2075 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_OS } }
2080 M32R_INSN_SUBX, "subx", "subx",
2081 { MNEM, ' ', OP (DR), ',', OP (SR), 0 },
2082 { 16, 16, 0xf0f0 }, 0x10,
2083 (PTR) & fmt_addx_ops[0],
2084 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_OS } }
2089 M32R_INSN_TRAP, "trap", "trap",
2090 { MNEM, ' ', OP (UIMM4), 0 },
2091 { 16, 16, 0xfff0 }, 0x10f0,
2092 (PTR) & fmt_trap_ops[0],
2093 { CGEN_INSN_NBOOL_ATTRS, 0|A(FILL_SLOT)|A(UNCOND_CTI), { (1<<MACH_M32R), PIPE_O } }
2095 /* unlock $src1,@$src2 */
2098 M32R_INSN_UNLOCK, "unlock", "unlock",
2099 { MNEM, ' ', OP (SRC1), ',', '@', OP (SRC2), 0 },
2100 { 16, 16, 0xf0f0 }, 0x2050,
2101 (PTR) & fmt_unlock_ops[0],
2102 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_O } }
2104 /* start-sanitize-m32rx */
2108 M32R_INSN_SATB, "satb", "satb",
2109 { MNEM, ' ', OP (DR), ',', OP (SR), 0 },
2110 { 32, 32, 0xf0f0ffff }, 0x80600300,
2111 (PTR) & fmt_satb_ops[0],
2112 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32RX), PIPE_NONE } }
2114 /* end-sanitize-m32rx */
2115 /* start-sanitize-m32rx */
2119 M32R_INSN_SATH, "sath", "sath",
2120 { MNEM, ' ', OP (DR), ',', OP (SR), 0 },
2121 { 32, 32, 0xf0f0ffff }, 0x80600200,
2122 (PTR) & fmt_satb_ops[0],
2123 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32RX), PIPE_NONE } }
2125 /* end-sanitize-m32rx */
2126 /* start-sanitize-m32rx */
2130 M32R_INSN_SAT, "sat", "sat",
2131 { MNEM, ' ', OP (DR), ',', OP (SR), 0 },
2132 { 32, 32, 0xf0f0ffff }, 0x80600000,
2133 (PTR) & fmt_sat_ops[0],
2134 { CGEN_INSN_NBOOL_ATTRS, 0|A(SPECIAL), { (1<<MACH_M32RX), PIPE_NONE } }
2136 /* end-sanitize-m32rx */
2137 /* start-sanitize-m32rx */
2141 M32R_INSN_PCMPBZ, "pcmpbz", "pcmpbz",
2142 { MNEM, ' ', OP (SRC2), 0 },
2143 { 16, 16, 0xfff0 }, 0x370,
2144 (PTR) & fmt_cmpz_ops[0],
2145 { CGEN_INSN_NBOOL_ATTRS, 0|A(SPECIAL), { (1<<MACH_M32RX), PIPE_OS } }
2147 /* end-sanitize-m32rx */
2148 /* start-sanitize-m32rx */
2152 M32R_INSN_SADD, "sadd", "sadd",
2154 { 16, 16, 0xffff }, 0x50e4,
2155 (PTR) & fmt_sadd_ops[0],
2156 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32RX), PIPE_S } }
2158 /* end-sanitize-m32rx */
2159 /* start-sanitize-m32rx */
2160 /* macwu1 $src1,$src2 */
2163 M32R_INSN_MACWU1, "macwu1", "macwu1",
2164 { MNEM, ' ', OP (SRC1), ',', OP (SRC2), 0 },
2165 { 16, 16, 0xf0f0 }, 0x50b0,
2166 (PTR) & fmt_macwu1_ops[0],
2167 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32RX), PIPE_S } }
2169 /* end-sanitize-m32rx */
2170 /* start-sanitize-m32rx */
2171 /* msblo $src1,$src2 */
2174 M32R_INSN_MSBLO, "msblo", "msblo",
2175 { MNEM, ' ', OP (SRC1), ',', OP (SRC2), 0 },
2176 { 16, 16, 0xf0f0 }, 0x50d0,
2177 (PTR) & fmt_machi_ops[0],
2178 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32RX), PIPE_S } }
2180 /* end-sanitize-m32rx */
2181 /* start-sanitize-m32rx */
2182 /* mulwu1 $src1,$src2 */
2185 M32R_INSN_MULWU1, "mulwu1", "mulwu1",
2186 { MNEM, ' ', OP (SRC1), ',', OP (SRC2), 0 },
2187 { 16, 16, 0xf0f0 }, 0x50a0,
2188 (PTR) & fmt_mulwu1_ops[0],
2189 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32RX), PIPE_S } }
2191 /* end-sanitize-m32rx */
2192 /* start-sanitize-m32rx */
2193 /* maclh1 $src1,$src2 */
2196 M32R_INSN_MACLH1, "maclh1", "maclh1",
2197 { MNEM, ' ', OP (SRC1), ',', OP (SRC2), 0 },
2198 { 16, 16, 0xf0f0 }, 0x50c0,
2199 (PTR) & fmt_macwu1_ops[0],
2200 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32RX), PIPE_S } }
2202 /* end-sanitize-m32rx */
2203 /* start-sanitize-m32rx */
2207 M32R_INSN_SC, "sc", "sc",
2209 { 16, 16, 0xffff }, 0x7401,
2210 (PTR) & fmt_sc_ops[0],
2211 { CGEN_INSN_NBOOL_ATTRS, 0|A(SPECIAL), { (1<<MACH_M32RX), PIPE_O } }
2213 /* end-sanitize-m32rx */
2214 /* start-sanitize-m32rx */
2218 M32R_INSN_SNC, "snc", "snc",
2220 { 16, 16, 0xffff }, 0x7501,
2221 (PTR) & fmt_sc_ops[0],
2222 { CGEN_INSN_NBOOL_ATTRS, 0|A(SPECIAL), { (1<<MACH_M32RX), PIPE_O } }
2224 /* end-sanitize-m32rx */
2231 static CGEN_INSN_TABLE insn_table =
2233 & m32r_cgen_insn_table_entries[0],
2239 /* Each non-simple macro entry points to an array of expansion possibilities. */
2241 #define A(a) (1 << CONCAT2 (CGEN_INSN_,a))
2242 #define MNEM CGEN_SYNTAX_MNEMONIC /* syntax value for mnemonic */
2243 #define OP(field) CGEN_SYNTAX_MAKE_FIELD (OPERAND (field))
2245 /* The macro instruction table. */
2247 static const CGEN_INSN macro_insn_table_entries[] =
2253 { MNEM, ' ', OP (DISP8), 0 },
2254 { 16, 16, 0xff00 }, 0x7c00,
2256 { CGEN_INSN_NBOOL_ATTRS, 0|A(RELAXABLE)|A(COND_CTI)|A(ALIAS), { (1<<MACH_M32R), PIPE_O } }
2262 { MNEM, ' ', OP (DISP24), 0 },
2263 { 32, 32, 0xff000000 }, 0xfc000000,
2265 { CGEN_INSN_NBOOL_ATTRS, 0|A(RELAX)|A(COND_CTI)|A(ALIAS), { (1<<MACH_M32R), PIPE_NONE } }
2271 { MNEM, ' ', OP (DISP8), 0 },
2272 { 16, 16, 0xff00 }, 0x7e00,
2274 { CGEN_INSN_NBOOL_ATTRS, 0|A(RELAXABLE)|A(FILL_SLOT)|A(UNCOND_CTI)|A(ALIAS), { (1<<MACH_M32R), PIPE_O } }
2280 { MNEM, ' ', OP (DISP24), 0 },
2281 { 32, 32, 0xff000000 }, 0xfe000000,
2283 { CGEN_INSN_NBOOL_ATTRS, 0|A(RELAX)|A(UNCOND_CTI)|A(ALIAS), { (1<<MACH_M32R), PIPE_NONE } }
2289 { MNEM, ' ', OP (DISP8), 0 },
2290 { 16, 16, 0xff00 }, 0x7800,
2292 { CGEN_INSN_NBOOL_ATTRS, 0|A(RELAXABLE)|A(COND_CTI)|A(ALIAS), { (1<<MACH_M32RX), PIPE_O } }
2297 -1, "bcl24r", "bcl",
2298 { MNEM, ' ', OP (DISP24), 0 },
2299 { 32, 32, 0xff000000 }, 0xf8000000,
2301 { CGEN_INSN_NBOOL_ATTRS, 0|A(RELAX)|A(COND_CTI)|A(ALIAS), { (1<<MACH_M32RX), PIPE_NONE } }
2307 { MNEM, ' ', OP (DISP8), 0 },
2308 { 16, 16, 0xff00 }, 0x7d00,
2310 { CGEN_INSN_NBOOL_ATTRS, 0|A(RELAXABLE)|A(COND_CTI)|A(ALIAS), { (1<<MACH_M32R), PIPE_O } }
2315 -1, "bnc24r", "bnc",
2316 { MNEM, ' ', OP (DISP24), 0 },
2317 { 32, 32, 0xff000000 }, 0xfd000000,
2319 { CGEN_INSN_NBOOL_ATTRS, 0|A(RELAX)|A(COND_CTI)|A(ALIAS), { (1<<MACH_M32R), PIPE_NONE } }
2325 { MNEM, ' ', OP (DISP8), 0 },
2326 { 16, 16, 0xff00 }, 0x7f00,
2328 { CGEN_INSN_NBOOL_ATTRS, 0|A(RELAXABLE)|A(FILL_SLOT)|A(UNCOND_CTI)|A(ALIAS), { (1<<MACH_M32R), PIPE_O } }
2333 -1, "bra24r", "bra",
2334 { MNEM, ' ', OP (DISP24), 0 },
2335 { 32, 32, 0xff000000 }, 0xff000000,
2337 { CGEN_INSN_NBOOL_ATTRS, 0|A(RELAX)|A(UNCOND_CTI)|A(ALIAS), { (1<<MACH_M32R), PIPE_NONE } }
2342 -1, "bncl8r", "bncl",
2343 { MNEM, ' ', OP (DISP8), 0 },
2344 { 16, 16, 0xff00 }, 0x7900,
2346 { CGEN_INSN_NBOOL_ATTRS, 0|A(RELAXABLE)|A(COND_CTI)|A(ALIAS), { (1<<MACH_M32RX), PIPE_O } }
2351 -1, "bncl24r", "bncl",
2352 { MNEM, ' ', OP (DISP24), 0 },
2353 { 32, 32, 0xff000000 }, 0xf9000000,
2355 { CGEN_INSN_NBOOL_ATTRS, 0|A(RELAX)|A(COND_CTI)|A(ALIAS), { (1<<MACH_M32RX), PIPE_NONE } }
2361 { MNEM, ' ', OP (DR), ',', '@', '(', OP (SR), ')', 0 },
2362 { 16, 16, 0xf0f0 }, 0x20c0,
2364 { CGEN_INSN_NBOOL_ATTRS, 0|A(NO_DIS)|A(ALIAS), { (1<<MACH_M32R), PIPE_O } }
2366 /* ld $dr,@($sr,$slo16) */
2370 { MNEM, ' ', OP (DR), ',', '@', '(', OP (SR), ',', OP (SLO16), ')', 0 },
2371 { 32, 32, 0xf0f00000 }, 0xa0c00000,
2373 { CGEN_INSN_NBOOL_ATTRS, 0|A(NO_DIS)|A(ALIAS), { (1<<MACH_M32R), PIPE_NONE } }
2375 /* ldb $dr,@($sr) */
2379 { MNEM, ' ', OP (DR), ',', '@', '(', OP (SR), ')', 0 },
2380 { 16, 16, 0xf0f0 }, 0x2080,
2382 { CGEN_INSN_NBOOL_ATTRS, 0|A(NO_DIS)|A(ALIAS), { (1<<MACH_M32R), PIPE_O } }
2384 /* ldb $dr,@($sr,$slo16) */
2387 -1, "ldb-d2", "ldb",
2388 { MNEM, ' ', OP (DR), ',', '@', '(', OP (SR), ',', OP (SLO16), ')', 0 },
2389 { 32, 32, 0xf0f00000 }, 0xa0800000,
2391 { CGEN_INSN_NBOOL_ATTRS, 0|A(NO_DIS)|A(ALIAS), { (1<<MACH_M32R), PIPE_NONE } }
2393 /* ldh $dr,@($sr) */
2397 { MNEM, ' ', OP (DR), ',', '@', '(', OP (SR), ')', 0 },
2398 { 16, 16, 0xf0f0 }, 0x20a0,
2400 { CGEN_INSN_NBOOL_ATTRS, 0|A(NO_DIS)|A(ALIAS), { (1<<MACH_M32R), PIPE_O } }
2402 /* ldh $dr,@($sr,$slo16) */
2405 -1, "ldh-d2", "ldh",
2406 { MNEM, ' ', OP (DR), ',', '@', '(', OP (SR), ',', OP (SLO16), ')', 0 },
2407 { 32, 32, 0xf0f00000 }, 0xa0a00000,
2409 { CGEN_INSN_NBOOL_ATTRS, 0|A(NO_DIS)|A(ALIAS), { (1<<MACH_M32R), PIPE_NONE } }
2411 /* ldub $dr,@($sr) */
2414 -1, "ldub-2", "ldub",
2415 { MNEM, ' ', OP (DR), ',', '@', '(', OP (SR), ')', 0 },
2416 { 16, 16, 0xf0f0 }, 0x2090,
2418 { CGEN_INSN_NBOOL_ATTRS, 0|A(NO_DIS)|A(ALIAS), { (1<<MACH_M32R), PIPE_O } }
2420 /* ldub $dr,@($sr,$slo16) */
2423 -1, "ldub-d2", "ldub",
2424 { MNEM, ' ', OP (DR), ',', '@', '(', OP (SR), ',', OP (SLO16), ')', 0 },
2425 { 32, 32, 0xf0f00000 }, 0xa0900000,
2427 { CGEN_INSN_NBOOL_ATTRS, 0|A(NO_DIS)|A(ALIAS), { (1<<MACH_M32R), PIPE_NONE } }
2429 /* lduh $dr,@($sr) */
2432 -1, "lduh-2", "lduh",
2433 { MNEM, ' ', OP (DR), ',', '@', '(', OP (SR), ')', 0 },
2434 { 16, 16, 0xf0f0 }, 0x20b0,
2436 { CGEN_INSN_NBOOL_ATTRS, 0|A(NO_DIS)|A(ALIAS), { (1<<MACH_M32R), PIPE_O } }
2438 /* lduh $dr,@($sr,$slo16) */
2441 -1, "lduh-d2", "lduh",
2442 { MNEM, ' ', OP (DR), ',', '@', '(', OP (SR), ',', OP (SLO16), ')', 0 },
2443 { 32, 32, 0xf0f00000 }, 0xa0b00000,
2445 { CGEN_INSN_NBOOL_ATTRS, 0|A(NO_DIS)|A(ALIAS), { (1<<MACH_M32R), PIPE_NONE } }
2451 { MNEM, ' ', OP (DR), 0 },
2452 { 16, 16, 0xf0ff }, 0x20ef,
2454 { CGEN_INSN_NBOOL_ATTRS, 0|A(ALIAS), { (1<<MACH_M32R), PIPE_NONE } }
2456 /* ldi $dr,$simm8 */
2460 { MNEM, ' ', OP (DR), ',', OP (SIMM8), 0 },
2461 { 16, 16, 0xf000 }, 0x6000,
2463 { CGEN_INSN_NBOOL_ATTRS, 0|A(ALIAS), { (1<<MACH_M32R), PIPE_OS } }
2465 /* ldi $dr,$hash$slo16 */
2468 -1, "ldi16a", "ldi",
2469 { MNEM, ' ', OP (DR), ',', OP (HASH), OP (SLO16), 0 },
2470 { 32, 32, 0xf0ff0000 }, 0x90f00000,
2472 { CGEN_INSN_NBOOL_ATTRS, 0|A(ALIAS), { (1<<MACH_M32R), PIPE_NONE } }
2478 { MNEM, ' ', OP (ACCD), 0 },
2479 { 16, 16, 0xf3ff }, 0x5090,
2481 { CGEN_INSN_NBOOL_ATTRS, 0|A(ALIAS), { (1<<MACH_M32RX), PIPE_S } }
2483 /* rac $accd,$accs */
2486 -1, "rac-ds", "rac",
2487 { MNEM, ' ', OP (ACCD), ',', OP (ACCS), 0 },
2488 { 16, 16, 0xf3f3 }, 0x5090,
2490 { CGEN_INSN_NBOOL_ATTRS, 0|A(ALIAS), { (1<<MACH_M32RX), PIPE_S } }
2495 -1, "rach-d", "rach",
2496 { MNEM, ' ', OP (ACCD), 0 },
2497 { 16, 16, 0xf3ff }, 0x5080,
2499 { CGEN_INSN_NBOOL_ATTRS, 0|A(ALIAS), { (1<<MACH_M32RX), PIPE_S } }
2501 /* rach $accd,$accs */
2504 -1, "rach-ds", "rach",
2505 { MNEM, ' ', OP (ACCD), ',', OP (ACCS), 0 },
2506 { 16, 16, 0xf3f3 }, 0x5080,
2508 { CGEN_INSN_NBOOL_ATTRS, 0|A(ALIAS), { (1<<MACH_M32RX), PIPE_S } }
2510 /* st $src1,@($src2) */
2514 { MNEM, ' ', OP (SRC1), ',', '@', '(', OP (SRC2), ')', 0 },
2515 { 16, 16, 0xf0f0 }, 0x2040,
2517 { CGEN_INSN_NBOOL_ATTRS, 0|A(NO_DIS)|A(ALIAS), { (1<<MACH_M32R), PIPE_O } }
2519 /* st $src1,@($src2,$slo16) */
2523 { MNEM, ' ', OP (SRC1), ',', '@', '(', OP (SRC2), ',', OP (SLO16), ')', 0 },
2524 { 32, 32, 0xf0f00000 }, 0xa0400000,
2526 { CGEN_INSN_NBOOL_ATTRS, 0|A(NO_DIS)|A(ALIAS), { (1<<MACH_M32R), PIPE_NONE } }
2528 /* stb $src1,@($src2) */
2532 { MNEM, ' ', OP (SRC1), ',', '@', '(', OP (SRC2), ')', 0 },
2533 { 16, 16, 0xf0f0 }, 0x2000,
2535 { CGEN_INSN_NBOOL_ATTRS, 0|A(NO_DIS)|A(ALIAS), { (1<<MACH_M32R), PIPE_O } }
2537 /* stb $src1,@($src2,$slo16) */
2540 -1, "stb-d2", "stb",
2541 { MNEM, ' ', OP (SRC1), ',', '@', '(', OP (SRC2), ',', OP (SLO16), ')', 0 },
2542 { 32, 32, 0xf0f00000 }, 0xa0000000,
2544 { CGEN_INSN_NBOOL_ATTRS, 0|A(NO_DIS)|A(ALIAS), { (1<<MACH_M32R), PIPE_NONE } }
2546 /* sth $src1,@($src2) */
2550 { MNEM, ' ', OP (SRC1), ',', '@', '(', OP (SRC2), ')', 0 },
2551 { 16, 16, 0xf0f0 }, 0x2020,
2553 { CGEN_INSN_NBOOL_ATTRS, 0|A(NO_DIS)|A(ALIAS), { (1<<MACH_M32R), PIPE_O } }
2555 /* sth $src1,@($src2,$slo16) */
2558 -1, "sth-d2", "sth",
2559 { MNEM, ' ', OP (SRC1), ',', '@', '(', OP (SRC2), ',', OP (SLO16), ')', 0 },
2560 { 32, 32, 0xf0f00000 }, 0xa0200000,
2562 { CGEN_INSN_NBOOL_ATTRS, 0|A(NO_DIS)|A(ALIAS), { (1<<MACH_M32R), PIPE_NONE } }
2568 { MNEM, ' ', OP (SRC1), 0 },
2569 { 16, 16, 0xf0ff }, 0x207f,
2571 { CGEN_INSN_NBOOL_ATTRS, 0|A(ALIAS), { (1<<MACH_M32R), PIPE_NONE } }
2579 static CGEN_INSN_TABLE macro_insn_table =
2581 & macro_insn_table_entries[0],
2583 (sizeof (macro_insn_table_entries) /
2584 sizeof (macro_insn_table_entries[0])),
2588 /* The hash functions are recorded here to help keep assembler code out of
2589 the disassembler and vice versa.
2591 static int asm_hash_insn_p PARAMS ((const CGEN_INSN *));
2592 static unsigned int asm_hash_insn PARAMS ((const char *));
2593 static int dis_hash_insn_p PARAMS ((const CGEN_INSN *));
2594 static unsigned int dis_hash_insn PARAMS ((const char *, unsigned long));
2596 /* Return non-zero if INSN is to be added to the hash table.
2597 Targets are free to override CGEN_{ASM,DIS}_HASH_P in the .opc file. */
2600 asm_hash_insn_p (insn)
2601 const CGEN_INSN * insn;
2603 return CGEN_ASM_HASH_P (insn);
2607 dis_hash_insn_p (insn)
2608 const CGEN_INSN * insn;
2610 /* If building the hash table and the NO-DIS attribute is present,
2612 if (CGEN_INSN_ATTR (insn, CGEN_INSN_NO_DIS))
2614 return CGEN_DIS_HASH_P (insn);
2617 /* The result is the hash value of the insn.
2618 Targets are free to override CGEN_{ASM,DIS}_HASH in the .opc file. */
2621 asm_hash_insn (mnem)
2624 return CGEN_ASM_HASH (mnem);
2628 dis_hash_insn (buf, value)
2630 unsigned long value;
2632 return CGEN_DIS_HASH (buf, value);
2635 const CGEN_OPCODE_TABLE m32r_cgen_opcode_table =
2637 & m32r_cgen_hw_entries[0],
2638 /*& m32r_cgen_operand_table[0], - FIXME:wip */
2641 asm_hash_insn_p, asm_hash_insn, CGEN_ASM_HASH_SIZE,
2642 dis_hash_insn_p, dis_hash_insn, CGEN_DIS_HASH_SIZE
2646 m32r_cgen_init_tables (mach)
2651 /* Getting values from cgen_fields is handled by a collection of functions.
2652 They are distinguished by the type of the VALUE argument they return.
2653 TODO: floating point, inlining support, remove cases where result type
2657 m32r_cgen_get_int_operand (opindex, fields)
2659 const CGEN_FIELDS * fields;
2665 case M32R_OPERAND_SR :
2666 value = fields->f_r2;
2668 case M32R_OPERAND_DR :
2669 value = fields->f_r1;
2671 case M32R_OPERAND_SRC1 :
2672 value = fields->f_r1;
2674 case M32R_OPERAND_SRC2 :
2675 value = fields->f_r2;
2677 case M32R_OPERAND_SCR :
2678 value = fields->f_r2;
2680 case M32R_OPERAND_DCR :
2681 value = fields->f_r1;
2683 case M32R_OPERAND_SIMM8 :
2684 value = fields->f_simm8;
2686 case M32R_OPERAND_SIMM16 :
2687 value = fields->f_simm16;
2689 case M32R_OPERAND_UIMM4 :
2690 value = fields->f_uimm4;
2692 case M32R_OPERAND_UIMM5 :
2693 value = fields->f_uimm5;
2695 case M32R_OPERAND_UIMM16 :
2696 value = fields->f_uimm16;
2698 /* start-sanitize-m32rx */
2699 case M32R_OPERAND_IMM1 :
2700 value = fields->f_imm1;
2702 /* end-sanitize-m32rx */
2703 /* start-sanitize-m32rx */
2704 case M32R_OPERAND_ACCD :
2705 value = fields->f_accd;
2707 /* end-sanitize-m32rx */
2708 /* start-sanitize-m32rx */
2709 case M32R_OPERAND_ACCS :
2710 value = fields->f_accs;
2712 /* end-sanitize-m32rx */
2713 /* start-sanitize-m32rx */
2714 case M32R_OPERAND_ACC :
2715 value = fields->f_acc;
2717 /* end-sanitize-m32rx */
2718 case M32R_OPERAND_HASH :
2719 value = fields->f_nil;
2721 case M32R_OPERAND_HI16 :
2722 value = fields->f_hi16;
2724 case M32R_OPERAND_SLO16 :
2725 value = fields->f_simm16;
2727 case M32R_OPERAND_ULO16 :
2728 value = fields->f_uimm16;
2730 case M32R_OPERAND_UIMM24 :
2731 value = fields->f_uimm24;
2733 case M32R_OPERAND_DISP8 :
2734 value = fields->f_disp8;
2736 case M32R_OPERAND_DISP16 :
2737 value = fields->f_disp16;
2739 case M32R_OPERAND_DISP24 :
2740 value = fields->f_disp24;
2744 /* xgettext:c-format */
2745 fprintf (stderr, _("Unrecognized field %d while getting int operand.\n"),
2754 m32r_cgen_get_vma_operand (opindex, fields)
2756 const CGEN_FIELDS * fields;
2762 case M32R_OPERAND_SR :
2763 value = fields->f_r2;
2765 case M32R_OPERAND_DR :
2766 value = fields->f_r1;
2768 case M32R_OPERAND_SRC1 :
2769 value = fields->f_r1;
2771 case M32R_OPERAND_SRC2 :
2772 value = fields->f_r2;
2774 case M32R_OPERAND_SCR :
2775 value = fields->f_r2;
2777 case M32R_OPERAND_DCR :
2778 value = fields->f_r1;
2780 case M32R_OPERAND_SIMM8 :
2781 value = fields->f_simm8;
2783 case M32R_OPERAND_SIMM16 :
2784 value = fields->f_simm16;
2786 case M32R_OPERAND_UIMM4 :
2787 value = fields->f_uimm4;
2789 case M32R_OPERAND_UIMM5 :
2790 value = fields->f_uimm5;
2792 case M32R_OPERAND_UIMM16 :
2793 value = fields->f_uimm16;
2795 /* start-sanitize-m32rx */
2796 case M32R_OPERAND_IMM1 :
2797 value = fields->f_imm1;
2799 /* end-sanitize-m32rx */
2800 /* start-sanitize-m32rx */
2801 case M32R_OPERAND_ACCD :
2802 value = fields->f_accd;
2804 /* end-sanitize-m32rx */
2805 /* start-sanitize-m32rx */
2806 case M32R_OPERAND_ACCS :
2807 value = fields->f_accs;
2809 /* end-sanitize-m32rx */
2810 /* start-sanitize-m32rx */
2811 case M32R_OPERAND_ACC :
2812 value = fields->f_acc;
2814 /* end-sanitize-m32rx */
2815 case M32R_OPERAND_HASH :
2816 value = fields->f_nil;
2818 case M32R_OPERAND_HI16 :
2819 value = fields->f_hi16;
2821 case M32R_OPERAND_SLO16 :
2822 value = fields->f_simm16;
2824 case M32R_OPERAND_ULO16 :
2825 value = fields->f_uimm16;
2827 case M32R_OPERAND_UIMM24 :
2828 value = fields->f_uimm24;
2830 case M32R_OPERAND_DISP8 :
2831 value = fields->f_disp8;
2833 case M32R_OPERAND_DISP16 :
2834 value = fields->f_disp16;
2836 case M32R_OPERAND_DISP24 :
2837 value = fields->f_disp24;
2841 /* xgettext:c-format */
2842 fprintf (stderr, _("Unrecognized field %d while getting vma operand.\n"),
2850 /* Stuffing values in cgen_fields is handled by a collection of functions.
2851 They are distinguished by the type of the VALUE argument they accept.
2852 TODO: floating point, inlining support, remove cases where argument type
2856 m32r_cgen_set_int_operand (opindex, fields, value)
2858 CGEN_FIELDS * fields;
2863 case M32R_OPERAND_SR :
2864 fields->f_r2 = value;
2866 case M32R_OPERAND_DR :
2867 fields->f_r1 = value;
2869 case M32R_OPERAND_SRC1 :
2870 fields->f_r1 = value;
2872 case M32R_OPERAND_SRC2 :
2873 fields->f_r2 = value;
2875 case M32R_OPERAND_SCR :
2876 fields->f_r2 = value;
2878 case M32R_OPERAND_DCR :
2879 fields->f_r1 = value;
2881 case M32R_OPERAND_SIMM8 :
2882 fields->f_simm8 = value;
2884 case M32R_OPERAND_SIMM16 :
2885 fields->f_simm16 = value;
2887 case M32R_OPERAND_UIMM4 :
2888 fields->f_uimm4 = value;
2890 case M32R_OPERAND_UIMM5 :
2891 fields->f_uimm5 = value;
2893 case M32R_OPERAND_UIMM16 :
2894 fields->f_uimm16 = value;
2896 /* start-sanitize-m32rx */
2897 case M32R_OPERAND_IMM1 :
2898 fields->f_imm1 = value;
2900 /* end-sanitize-m32rx */
2901 /* start-sanitize-m32rx */
2902 case M32R_OPERAND_ACCD :
2903 fields->f_accd = value;
2905 /* end-sanitize-m32rx */
2906 /* start-sanitize-m32rx */
2907 case M32R_OPERAND_ACCS :
2908 fields->f_accs = value;
2910 /* end-sanitize-m32rx */
2911 /* start-sanitize-m32rx */
2912 case M32R_OPERAND_ACC :
2913 fields->f_acc = value;
2915 /* end-sanitize-m32rx */
2916 case M32R_OPERAND_HASH :
2917 fields->f_nil = value;
2919 case M32R_OPERAND_HI16 :
2920 fields->f_hi16 = value;
2922 case M32R_OPERAND_SLO16 :
2923 fields->f_simm16 = value;
2925 case M32R_OPERAND_ULO16 :
2926 fields->f_uimm16 = value;
2928 case M32R_OPERAND_UIMM24 :
2929 fields->f_uimm24 = value;
2931 case M32R_OPERAND_DISP8 :
2932 fields->f_disp8 = value;
2934 case M32R_OPERAND_DISP16 :
2935 fields->f_disp16 = value;
2937 case M32R_OPERAND_DISP24 :
2938 fields->f_disp24 = value;
2942 /* xgettext:c-format */
2943 fprintf (stderr, _("Unrecognized field %d while setting int operand.\n"),
2950 m32r_cgen_set_vma_operand (opindex, fields, value)
2952 CGEN_FIELDS * fields;
2957 case M32R_OPERAND_SR :
2958 fields->f_r2 = value;
2960 case M32R_OPERAND_DR :
2961 fields->f_r1 = value;
2963 case M32R_OPERAND_SRC1 :
2964 fields->f_r1 = value;
2966 case M32R_OPERAND_SRC2 :
2967 fields->f_r2 = value;
2969 case M32R_OPERAND_SCR :
2970 fields->f_r2 = value;
2972 case M32R_OPERAND_DCR :
2973 fields->f_r1 = value;
2975 case M32R_OPERAND_SIMM8 :
2976 fields->f_simm8 = value;
2978 case M32R_OPERAND_SIMM16 :
2979 fields->f_simm16 = value;
2981 case M32R_OPERAND_UIMM4 :
2982 fields->f_uimm4 = value;
2984 case M32R_OPERAND_UIMM5 :
2985 fields->f_uimm5 = value;
2987 case M32R_OPERAND_UIMM16 :
2988 fields->f_uimm16 = value;
2990 /* start-sanitize-m32rx */
2991 case M32R_OPERAND_IMM1 :
2992 fields->f_imm1 = value;
2994 /* end-sanitize-m32rx */
2995 /* start-sanitize-m32rx */
2996 case M32R_OPERAND_ACCD :
2997 fields->f_accd = value;
2999 /* end-sanitize-m32rx */
3000 /* start-sanitize-m32rx */
3001 case M32R_OPERAND_ACCS :
3002 fields->f_accs = value;
3004 /* end-sanitize-m32rx */
3005 /* start-sanitize-m32rx */
3006 case M32R_OPERAND_ACC :
3007 fields->f_acc = value;
3009 /* end-sanitize-m32rx */
3010 case M32R_OPERAND_HASH :
3011 fields->f_nil = value;
3013 case M32R_OPERAND_HI16 :
3014 fields->f_hi16 = value;
3016 case M32R_OPERAND_SLO16 :
3017 fields->f_simm16 = value;
3019 case M32R_OPERAND_ULO16 :
3020 fields->f_uimm16 = value;
3022 case M32R_OPERAND_UIMM24 :
3023 fields->f_uimm24 = value;
3025 case M32R_OPERAND_DISP8 :
3026 fields->f_disp8 = value;
3028 case M32R_OPERAND_DISP16 :
3029 fields->f_disp16 = value;
3031 case M32R_OPERAND_DISP24 :
3032 fields->f_disp24 = value;
3036 /* xgettext:c-format */
3037 fprintf (stderr, _("Unrecognized field %d while setting vma operand.\n"),