1 /* Generic opcode table support for targets using CGEN. -*- C -*-
2 CGEN: Cpu tools GENerator
4 This file is used to generate m32r-opc.c.
6 Copyright (C) 1998 Free Software Foundation, Inc.
8 This file is part of the GNU Binutils and GDB, the GNU debugger.
10 This program is free software; you can redistribute it and/or modify
11 it under the terms of the GNU General Public License as published by
12 the Free Software Foundation; either version 2, or (at your option)
15 This program is distributed in the hope that it will be useful,
16 but WITHOUT ANY WARRANTY; without even the implied warranty of
17 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 GNU General Public License for more details.
20 You should have received a copy of the GNU General Public License
21 along with this program; if not, write to the Free Software
22 Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */
27 #include "libiberty.h"
32 /* Look up instruction INSN_VALUE and extract its fields.
33 If non-null INSN is the insn table entry.
34 Otherwise INSN_VALUE is examined to compute it.
35 LENGTH is the bit length of INSN_VALUE if known, otherwise 0.
36 ALIAS_P is non-zero if alias insns are to be included in the search.
37 The result a pointer to the insn table entry, or NULL if the instruction
41 m32r_cgen_lookup_insn (insn, insn_value, length, fields, alias_p)
42 const CGEN_INSN *insn;
43 cgen_insn_t insn_value;
51 const CGEN_INSN_LIST *insn_list;
60 if (cgen_current_endian == CGEN_ENDIAN_BIG)
61 bfd_putb16 (insn_value, buf);
63 bfd_putl16 (insn_value, buf);
66 if (cgen_current_endian == CGEN_ENDIAN_BIG)
67 bfd_putb32 (insn_value, buf);
69 bfd_putl32 (insn_value, buf);
75 abort (); /* FIXME: unfinished */
78 /* The instructions are stored in hash lists.
79 Pick the first one and keep trying until we find the right one. */
81 insn_list = CGEN_DIS_LOOKUP_INSN (buf, insn_value);
82 while (insn_list != NULL)
84 insn = insn_list->insn;
87 || ! CGEN_INSN_ATTR (insn, CGEN_INSN_ALIAS))
89 /* Basic bit mask must be correct. */
90 /* ??? May wish to allow target to defer this check until the
92 if ((insn_value & CGEN_INSN_MASK (insn)) == CGEN_INSN_VALUE (insn))
94 length = (*CGEN_EXTRACT_FN (insn)) (insn, NULL, insn_value, fields);
100 insn_list = CGEN_DIS_NEXT_INSN (insn_list);
105 /* Sanity check: can't pass an alias insn if ! alias_p. */
107 && CGEN_INSN_ATTR (insn, CGEN_INSN_ALIAS))
110 length = (*CGEN_EXTRACT_FN (insn)) (insn, NULL, insn_value, fields);
118 /* Fill in the operand instances used by insn INSN_VALUE.
119 If non-null INS is the insn table entry.
120 Otherwise INSN_VALUE is examined to compute it.
121 LENGTH is the number of bits in INSN_VALUE if known, otherwise 0.
122 INDICES is a pointer to a buffer of MAX_OPERAND_INSTANCES ints to be filled
124 The result a pointer to the insn table entry, or NULL if the instruction
125 wasn't recognized. */
128 m32r_cgen_get_insn_operands (insn, insn_value, length, indices)
129 const CGEN_INSN *insn;
130 cgen_insn_t insn_value;
135 const CGEN_OPERAND_INSTANCE *opinst;
138 /* FIXME: ALIAS insns are in transition from being record in the insn table
139 to being recorded separately as macros. They don't have semantic code
140 so they can't be used here. Thus we currently always ignore the INSN
142 insn = m32r_cgen_lookup_insn (NULL, insn_value, length, &fields, 0);
146 for (i = 0, opinst = CGEN_INSN_OPERANDS (insn);
148 && CGEN_OPERAND_INSTANCE_TYPE (opinst) != CGEN_OPERAND_INSTANCE_END;
151 const CGEN_OPERAND *op = CGEN_OPERAND_INSTANCE_OPERAND (opinst);
153 indices[i] = CGEN_OPERAND_INSTANCE_INDEX (opinst);
155 indices[i] = m32r_cgen_get_operand (CGEN_OPERAND_INDEX (op), &fields);
162 static const CGEN_ATTR_ENTRY MACH_attr[] =
164 { "m32r", MACH_M32R },
165 /* start-sanitize-m32rx */
166 { "m32rx", MACH_M32RX },
167 /* end-sanitize-m32rx */
172 /* start-sanitize-m32rx */
173 static const CGEN_ATTR_ENTRY PIPE_attr[] =
175 { "NONE", PIPE_NONE },
182 /* end-sanitize-m32rx */
183 const CGEN_ATTR_TABLE m32r_cgen_operand_attr_table[] =
185 { "ABS-ADDR", NULL },
187 { "HASH-PREFIX", NULL },
188 { "NEGATIVE", NULL },
190 { "PCREL-ADDR", NULL },
193 { "SIGN-OPT", NULL },
194 { "UNSIGNED", NULL },
198 const CGEN_ATTR_TABLE m32r_cgen_insn_attr_table[] =
200 { "MACH", & MACH_attr[0] },
201 /* start-sanitize-m32rx */
202 { "PIPE", & PIPE_attr[0] },
203 /* end-sanitize-m32rx */
205 { "COND-CTI", NULL },
206 { "FILL-SLOT", NULL },
207 { "PARALLEL", NULL },
209 { "RELAXABLE", NULL },
210 { "UNCOND-CTI", NULL },
214 CGEN_KEYWORD_ENTRY m32r_cgen_opval_h_gr_entries[] =
237 CGEN_KEYWORD m32r_cgen_opval_h_gr =
239 & m32r_cgen_opval_h_gr_entries[0],
243 CGEN_KEYWORD_ENTRY m32r_cgen_opval_h_cr_entries[] =
259 CGEN_KEYWORD m32r_cgen_opval_h_cr =
261 & m32r_cgen_opval_h_cr_entries[0],
265 /* start-sanitize-m32rx */
266 CGEN_KEYWORD_ENTRY m32r_cgen_opval_h_accums_entries[] =
272 CGEN_KEYWORD m32r_cgen_opval_h_accums =
274 & m32r_cgen_opval_h_accums_entries[0],
278 /* end-sanitize-m32rx */
280 /* The hardware table. */
282 #define HW_ENT(n) m32r_cgen_hw_entries[n]
283 static const CGEN_HW_ENTRY m32r_cgen_hw_entries[] =
285 { HW_H_PC, & HW_ENT (HW_H_PC + 1), "h-pc", CGEN_ASM_KEYWORD, (PTR) 0 },
286 { HW_H_MEMORY, & HW_ENT (HW_H_MEMORY + 1), "h-memory", CGEN_ASM_KEYWORD, (PTR) 0 },
287 { HW_H_SINT, & HW_ENT (HW_H_SINT + 1), "h-sint", CGEN_ASM_KEYWORD, (PTR) 0 },
288 { HW_H_UINT, & HW_ENT (HW_H_UINT + 1), "h-uint", CGEN_ASM_KEYWORD, (PTR) 0 },
289 { HW_H_ADDR, & HW_ENT (HW_H_ADDR + 1), "h-addr", CGEN_ASM_KEYWORD, (PTR) 0 },
290 { HW_H_IADDR, & HW_ENT (HW_H_IADDR + 1), "h-iaddr", CGEN_ASM_KEYWORD, (PTR) 0 },
291 { HW_H_HI16, & HW_ENT (HW_H_HI16 + 1), "h-hi16", CGEN_ASM_KEYWORD, (PTR) 0 },
292 { HW_H_SLO16, & HW_ENT (HW_H_SLO16 + 1), "h-slo16", CGEN_ASM_KEYWORD, (PTR) 0 },
293 { HW_H_ULO16, & HW_ENT (HW_H_ULO16 + 1), "h-ulo16", CGEN_ASM_KEYWORD, (PTR) 0 },
294 { HW_H_GR, & HW_ENT (HW_H_GR + 1), "h-gr", CGEN_ASM_KEYWORD, (PTR) & m32r_cgen_opval_h_gr },
295 { HW_H_CR, & HW_ENT (HW_H_CR + 1), "h-cr", CGEN_ASM_KEYWORD, (PTR) & m32r_cgen_opval_h_cr },
296 { HW_H_ACCUM, & HW_ENT (HW_H_ACCUM + 1), "h-accum", CGEN_ASM_KEYWORD, (PTR) 0 },
297 /* start-sanitize-m32rx */
298 { HW_H_ACCUMS, & HW_ENT (HW_H_ACCUMS + 1), "h-accums", CGEN_ASM_KEYWORD, (PTR) & m32r_cgen_opval_h_accums },
299 /* end-sanitize-m32rx */
300 /* start-sanitize-m32rx */
301 { HW_H_ABORT, & HW_ENT (HW_H_ABORT + 1), "h-abort", CGEN_ASM_KEYWORD, (PTR) 0 },
302 /* end-sanitize-m32rx */
303 { HW_H_COND, & HW_ENT (HW_H_COND + 1), "h-cond", CGEN_ASM_KEYWORD, (PTR) 0 },
304 { HW_H_SM, & HW_ENT (HW_H_SM + 1), "h-sm", CGEN_ASM_KEYWORD, (PTR) 0 },
305 { HW_H_BSM, & HW_ENT (HW_H_BSM + 1), "h-bsm", CGEN_ASM_KEYWORD, (PTR) 0 },
306 { HW_H_IE, & HW_ENT (HW_H_IE + 1), "h-ie", CGEN_ASM_KEYWORD, (PTR) 0 },
307 { HW_H_BIE, & HW_ENT (HW_H_BIE + 1), "h-bie", CGEN_ASM_KEYWORD, (PTR) 0 },
308 { HW_H_BCOND, & HW_ENT (HW_H_BCOND + 1), "h-bcond", CGEN_ASM_KEYWORD, (PTR) 0 },
309 { HW_H_BPC, & HW_ENT (HW_H_BPC + 1), "h-bpc", CGEN_ASM_KEYWORD, (PTR) 0 },
310 { HW_H_LOCK, & HW_ENT (HW_H_LOCK + 1), "h-lock", CGEN_ASM_KEYWORD, (PTR) 0 },
314 /* The operand table. */
316 #define OPERAND(op) CONCAT2 (M32R_OPERAND_,op)
317 #define OP_ENT(op) m32r_cgen_operand_table[OPERAND (op)]
319 const CGEN_OPERAND m32r_cgen_operand_table[MAX_OPERANDS] =
321 /* pc: program counter */
322 { "pc", & HW_ENT (HW_H_PC), 0, 0,
323 { 0, 0|(1<<CGEN_OPERAND_FAKE)|(1<<CGEN_OPERAND_PC), { 0 } } },
324 /* sr: source register */
325 { "sr", & HW_ENT (HW_H_GR), 12, 4,
326 { 0, 0|(1<<CGEN_OPERAND_UNSIGNED), { 0 } } },
327 /* dr: destination register */
328 { "dr", & HW_ENT (HW_H_GR), 4, 4,
329 { 0, 0|(1<<CGEN_OPERAND_UNSIGNED), { 0 } } },
330 /* src1: source register 1 */
331 { "src1", & HW_ENT (HW_H_GR), 4, 4,
332 { 0, 0|(1<<CGEN_OPERAND_UNSIGNED), { 0 } } },
333 /* src2: source register 2 */
334 { "src2", & HW_ENT (HW_H_GR), 12, 4,
335 { 0, 0|(1<<CGEN_OPERAND_UNSIGNED), { 0 } } },
336 /* scr: source control register */
337 { "scr", & HW_ENT (HW_H_CR), 12, 4,
338 { 0, 0|(1<<CGEN_OPERAND_UNSIGNED), { 0 } } },
339 /* dcr: destination control register */
340 { "dcr", & HW_ENT (HW_H_CR), 4, 4,
341 { 0, 0|(1<<CGEN_OPERAND_UNSIGNED), { 0 } } },
342 /* simm8: 8 bit signed immediate */
343 { "simm8", & HW_ENT (HW_H_SINT), 8, 8,
344 { 0, 0|(1<<CGEN_OPERAND_HASH_PREFIX), { 0 } } },
345 /* simm16: 16 bit signed immediate */
346 { "simm16", & HW_ENT (HW_H_SINT), 16, 16,
347 { 0, 0|(1<<CGEN_OPERAND_HASH_PREFIX), { 0 } } },
348 /* uimm4: 4 bit trap number */
349 { "uimm4", & HW_ENT (HW_H_UINT), 12, 4,
350 { 0, 0|(1<<CGEN_OPERAND_HASH_PREFIX)|(1<<CGEN_OPERAND_UNSIGNED), { 0 } } },
351 /* uimm5: 5 bit shift count */
352 { "uimm5", & HW_ENT (HW_H_UINT), 11, 5,
353 { 0, 0|(1<<CGEN_OPERAND_HASH_PREFIX)|(1<<CGEN_OPERAND_UNSIGNED), { 0 } } },
354 /* uimm16: 16 bit unsigned immediate */
355 { "uimm16", & HW_ENT (HW_H_UINT), 16, 16,
356 { 0, 0|(1<<CGEN_OPERAND_HASH_PREFIX)|(1<<CGEN_OPERAND_UNSIGNED), { 0 } } },
357 /* start-sanitize-m32rx */
358 /* imm1: 1 bit immediate */
359 { "imm1", & HW_ENT (HW_H_UINT), 15, 1,
360 { 0, 0|(1<<CGEN_OPERAND_HASH_PREFIX)|(1<<CGEN_OPERAND_UNSIGNED), { 0 } } },
361 /* end-sanitize-m32rx */
362 /* start-sanitize-m32rx */
363 /* accd: accumulator destination register */
364 { "accd", & HW_ENT (HW_H_ACCUMS), 4, 2,
365 { 0, 0|(1<<CGEN_OPERAND_UNSIGNED), { 0 } } },
366 /* end-sanitize-m32rx */
367 /* start-sanitize-m32rx */
368 /* accs: accumulator source register */
369 { "accs", & HW_ENT (HW_H_ACCUMS), 12, 2,
370 { 0, 0|(1<<CGEN_OPERAND_UNSIGNED), { 0 } } },
371 /* end-sanitize-m32rx */
372 /* start-sanitize-m32rx */
373 /* acc: accumulator reg (d) */
374 { "acc", & HW_ENT (HW_H_ACCUMS), 8, 1,
375 { 0, 0|(1<<CGEN_OPERAND_UNSIGNED), { 0 } } },
376 /* end-sanitize-m32rx */
378 { "hash", & HW_ENT (HW_H_SINT), 0, 0,
380 /* hi16: high 16 bit immediate, sign optional */
381 { "hi16", & HW_ENT (HW_H_HI16), 16, 16,
382 { 0, 0|(1<<CGEN_OPERAND_SIGN_OPT)|(1<<CGEN_OPERAND_UNSIGNED), { 0 } } },
383 /* slo16: 16 bit signed immediate, for low() */
384 { "slo16", & HW_ENT (HW_H_SLO16), 16, 16,
386 /* ulo16: 16 bit unsigned immediate, for low() */
387 { "ulo16", & HW_ENT (HW_H_ULO16), 16, 16,
388 { 0, 0|(1<<CGEN_OPERAND_UNSIGNED), { 0 } } },
389 /* uimm24: 24 bit address */
390 { "uimm24", & HW_ENT (HW_H_ADDR), 8, 24,
391 { 0, 0|(1<<CGEN_OPERAND_HASH_PREFIX)|(1<<CGEN_OPERAND_RELOC)|(1<<CGEN_OPERAND_ABS_ADDR)|(1<<CGEN_OPERAND_UNSIGNED), { 0 } } },
392 /* disp8: 8 bit displacement */
393 { "disp8", & HW_ENT (HW_H_IADDR), 8, 8,
394 { 0, 0|(1<<CGEN_OPERAND_RELAX)|(1<<CGEN_OPERAND_RELOC)|(1<<CGEN_OPERAND_PCREL_ADDR), { 0 } } },
395 /* disp16: 16 bit displacement */
396 { "disp16", & HW_ENT (HW_H_IADDR), 16, 16,
397 { 0, 0|(1<<CGEN_OPERAND_RELOC)|(1<<CGEN_OPERAND_PCREL_ADDR), { 0 } } },
398 /* disp24: 24 bit displacement */
399 { "disp24", & HW_ENT (HW_H_IADDR), 8, 24,
400 { 0, 0|(1<<CGEN_OPERAND_RELAX)|(1<<CGEN_OPERAND_RELOC)|(1<<CGEN_OPERAND_PCREL_ADDR), { 0 } } },
401 /* condbit: condition bit */
402 { "condbit", & HW_ENT (HW_H_COND), 0, 0,
403 { 0, 0|(1<<CGEN_OPERAND_FAKE), { 0 } } },
404 /* accum: accumulator */
405 { "accum", & HW_ENT (HW_H_ACCUM), 0, 0,
406 { 0, 0|(1<<CGEN_OPERAND_FAKE), { 0 } } },
409 /* Operand references. */
411 #define INPUT CGEN_OPERAND_INSTANCE_INPUT
412 #define OUTPUT CGEN_OPERAND_INSTANCE_OUTPUT
414 static const CGEN_OPERAND_INSTANCE fmt_0_add_ops[] = {
415 { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0 },
416 { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SR), 0 },
417 { OUTPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0 },
421 static const CGEN_OPERAND_INSTANCE fmt_1_add3_ops[] = {
422 { INPUT, & HW_ENT (HW_H_SLO16), CGEN_MODE_HI, & OP_ENT (SLO16), 0 },
423 { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SR), 0 },
424 { OUTPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0 },
428 static const CGEN_OPERAND_INSTANCE fmt_2_and3_ops[] = {
429 { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SR), 0 },
430 { INPUT, & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (UIMM16), 0 },
431 { OUTPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0 },
435 static const CGEN_OPERAND_INSTANCE fmt_3_or3_ops[] = {
436 { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SR), 0 },
437 { INPUT, & HW_ENT (HW_H_ULO16), CGEN_MODE_UHI, & OP_ENT (ULO16), 0 },
438 { OUTPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0 },
442 static const CGEN_OPERAND_INSTANCE fmt_4_addi_ops[] = {
443 { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0 },
444 { INPUT, & HW_ENT (HW_H_SINT), CGEN_MODE_SI, & OP_ENT (SIMM8), 0 },
445 { OUTPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0 },
449 static const CGEN_OPERAND_INSTANCE fmt_5_addv_ops[] = {
450 { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0 },
451 { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SR), 0 },
452 { OUTPUT, & HW_ENT (HW_H_COND), CGEN_MODE_UBI, 0, 0 },
453 { OUTPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0 },
457 static const CGEN_OPERAND_INSTANCE fmt_6_addv3_ops[] = {
458 { INPUT, & HW_ENT (HW_H_SINT), CGEN_MODE_SI, & OP_ENT (SIMM16), 0 },
459 { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SR), 0 },
460 { OUTPUT, & HW_ENT (HW_H_COND), CGEN_MODE_UBI, 0, 0 },
461 { OUTPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0 },
465 static const CGEN_OPERAND_INSTANCE fmt_7_addx_ops[] = {
466 { INPUT, & HW_ENT (HW_H_COND), CGEN_MODE_UBI, 0, 0 },
467 { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0 },
468 { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SR), 0 },
469 { OUTPUT, & HW_ENT (HW_H_COND), CGEN_MODE_UBI, 0, 0 },
470 { OUTPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0 },
474 static const CGEN_OPERAND_INSTANCE fmt_8_bc8_ops[] = {
475 { INPUT, & HW_ENT (HW_H_COND), CGEN_MODE_UBI, 0, 0 },
476 { INPUT, & HW_ENT (HW_H_IADDR), CGEN_MODE_VM, & OP_ENT (DISP8), 0 },
477 { OUTPUT, & HW_ENT (HW_H_PC), CGEN_MODE_USI, 0, 0 },
481 static const CGEN_OPERAND_INSTANCE fmt_10_bc24_ops[] = {
482 { INPUT, & HW_ENT (HW_H_COND), CGEN_MODE_UBI, 0, 0 },
483 { INPUT, & HW_ENT (HW_H_IADDR), CGEN_MODE_VM, & OP_ENT (DISP24), 0 },
484 { OUTPUT, & HW_ENT (HW_H_PC), CGEN_MODE_USI, 0, 0 },
488 static const CGEN_OPERAND_INSTANCE fmt_12_beq_ops[] = {
489 { INPUT, & HW_ENT (HW_H_IADDR), CGEN_MODE_VM, & OP_ENT (DISP16), 0 },
490 { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC1), 0 },
491 { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC2), 0 },
492 { OUTPUT, & HW_ENT (HW_H_PC), CGEN_MODE_USI, 0, 0 },
496 static const CGEN_OPERAND_INSTANCE fmt_13_beqz_ops[] = {
497 { INPUT, & HW_ENT (HW_H_IADDR), CGEN_MODE_VM, & OP_ENT (DISP16), 0 },
498 { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC2), 0 },
499 { OUTPUT, & HW_ENT (HW_H_PC), CGEN_MODE_USI, 0, 0 },
503 static const CGEN_OPERAND_INSTANCE fmt_14_bl8_ops[] = {
504 { INPUT, & HW_ENT (HW_H_IADDR), CGEN_MODE_VM, & OP_ENT (DISP8), 0 },
505 { INPUT, & HW_ENT (HW_H_PC), CGEN_MODE_USI, 0, 0 },
506 { OUTPUT, & HW_ENT (HW_H_PC), CGEN_MODE_USI, 0, 0 },
507 { OUTPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 14 },
511 static const CGEN_OPERAND_INSTANCE fmt_15_bl24_ops[] = {
512 { INPUT, & HW_ENT (HW_H_IADDR), CGEN_MODE_VM, & OP_ENT (DISP24), 0 },
513 { INPUT, & HW_ENT (HW_H_PC), CGEN_MODE_USI, 0, 0 },
514 { OUTPUT, & HW_ENT (HW_H_PC), CGEN_MODE_USI, 0, 0 },
515 { OUTPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 14 },
519 static const CGEN_OPERAND_INSTANCE fmt_16_bcl8_ops[] = {
520 { INPUT, & HW_ENT (HW_H_COND), CGEN_MODE_UBI, 0, 0 },
521 { INPUT, & HW_ENT (HW_H_IADDR), CGEN_MODE_VM, & OP_ENT (DISP8), 0 },
522 { INPUT, & HW_ENT (HW_H_PC), CGEN_MODE_USI, 0, 0 },
523 { OUTPUT, & HW_ENT (HW_H_PC), CGEN_MODE_USI, 0, 0 },
524 { OUTPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 14 },
528 static const CGEN_OPERAND_INSTANCE fmt_17_bcl24_ops[] = {
529 { INPUT, & HW_ENT (HW_H_COND), CGEN_MODE_UBI, 0, 0 },
530 { INPUT, & HW_ENT (HW_H_IADDR), CGEN_MODE_VM, & OP_ENT (DISP24), 0 },
531 { INPUT, & HW_ENT (HW_H_PC), CGEN_MODE_USI, 0, 0 },
532 { OUTPUT, & HW_ENT (HW_H_PC), CGEN_MODE_USI, 0, 0 },
533 { OUTPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 14 },
537 static const CGEN_OPERAND_INSTANCE fmt_18_bra8_ops[] = {
538 { INPUT, & HW_ENT (HW_H_IADDR), CGEN_MODE_VM, & OP_ENT (DISP8), 0 },
539 { OUTPUT, & HW_ENT (HW_H_PC), CGEN_MODE_USI, 0, 0 },
543 static const CGEN_OPERAND_INSTANCE fmt_19_bra24_ops[] = {
544 { INPUT, & HW_ENT (HW_H_IADDR), CGEN_MODE_VM, & OP_ENT (DISP24), 0 },
545 { OUTPUT, & HW_ENT (HW_H_PC), CGEN_MODE_USI, 0, 0 },
549 static const CGEN_OPERAND_INSTANCE fmt_20_cmp_ops[] = {
550 { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC1), 0 },
551 { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC2), 0 },
552 { OUTPUT, & HW_ENT (HW_H_COND), CGEN_MODE_UBI, 0, 0 },
556 static const CGEN_OPERAND_INSTANCE fmt_21_cmpi_ops[] = {
557 { INPUT, & HW_ENT (HW_H_SINT), CGEN_MODE_SI, & OP_ENT (SIMM16), 0 },
558 { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC2), 0 },
559 { OUTPUT, & HW_ENT (HW_H_COND), CGEN_MODE_UBI, 0, 0 },
563 static const CGEN_OPERAND_INSTANCE fmt_22_cmpui_ops[] = {
564 { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC2), 0 },
565 { INPUT, & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (UIMM16), 0 },
566 { OUTPUT, & HW_ENT (HW_H_COND), CGEN_MODE_UBI, 0, 0 },
570 static const CGEN_OPERAND_INSTANCE fmt_23_cmpz_ops[] = {
571 { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC2), 0 },
572 { OUTPUT, & HW_ENT (HW_H_COND), CGEN_MODE_UBI, 0, 0 },
576 static const CGEN_OPERAND_INSTANCE fmt_24_div_ops[] = {
577 { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0 },
578 { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SR), 0 },
579 { OUTPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0 },
583 static const CGEN_OPERAND_INSTANCE fmt_25_jc_ops[] = {
584 { INPUT, & HW_ENT (HW_H_COND), CGEN_MODE_UBI, 0, 0 },
585 { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SR), 0 },
586 { OUTPUT, & HW_ENT (HW_H_PC), CGEN_MODE_USI, 0, 0 },
590 static const CGEN_OPERAND_INSTANCE fmt_26_jl_ops[] = {
591 { INPUT, & HW_ENT (HW_H_PC), CGEN_MODE_USI, 0, 0 },
592 { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SR), 0 },
593 { OUTPUT, & HW_ENT (HW_H_PC), CGEN_MODE_USI, 0, 0 },
594 { OUTPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 14 },
598 static const CGEN_OPERAND_INSTANCE fmt_27_jmp_ops[] = {
599 { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SR), 0 },
600 { OUTPUT, & HW_ENT (HW_H_PC), CGEN_MODE_USI, 0, 0 },
604 static const CGEN_OPERAND_INSTANCE fmt_28_ld_ops[] = {
605 { INPUT, & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0 },
606 { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SR), 0 },
607 { OUTPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0 },
611 static const CGEN_OPERAND_INSTANCE fmt_30_ld_d_ops[] = {
612 { INPUT, & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0 },
613 { INPUT, & HW_ENT (HW_H_SLO16), CGEN_MODE_HI, & OP_ENT (SLO16), 0 },
614 { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SR), 0 },
615 { OUTPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0 },
619 static const CGEN_OPERAND_INSTANCE fmt_32_ldb_ops[] = {
620 { INPUT, & HW_ENT (HW_H_MEMORY), CGEN_MODE_QI, 0, 0 },
621 { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SR), 0 },
622 { OUTPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0 },
626 static const CGEN_OPERAND_INSTANCE fmt_33_ldb_d_ops[] = {
627 { INPUT, & HW_ENT (HW_H_MEMORY), CGEN_MODE_QI, 0, 0 },
628 { INPUT, & HW_ENT (HW_H_SLO16), CGEN_MODE_HI, & OP_ENT (SLO16), 0 },
629 { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SR), 0 },
630 { OUTPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0 },
634 static const CGEN_OPERAND_INSTANCE fmt_34_ldh_ops[] = {
635 { INPUT, & HW_ENT (HW_H_MEMORY), CGEN_MODE_HI, 0, 0 },
636 { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SR), 0 },
637 { OUTPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0 },
641 static const CGEN_OPERAND_INSTANCE fmt_35_ldh_d_ops[] = {
642 { INPUT, & HW_ENT (HW_H_MEMORY), CGEN_MODE_HI, 0, 0 },
643 { INPUT, & HW_ENT (HW_H_SLO16), CGEN_MODE_HI, & OP_ENT (SLO16), 0 },
644 { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SR), 0 },
645 { OUTPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0 },
649 static const CGEN_OPERAND_INSTANCE fmt_36_ld_plus_ops[] = {
650 { INPUT, & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0 },
651 { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SR), 0 },
652 { OUTPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0 },
653 { OUTPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SR), 0 },
657 static const CGEN_OPERAND_INSTANCE fmt_37_ld24_ops[] = {
658 { INPUT, & HW_ENT (HW_H_ADDR), CGEN_MODE_VM, & OP_ENT (UIMM24), 0 },
659 { OUTPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0 },
663 static const CGEN_OPERAND_INSTANCE fmt_38_ldi8_ops[] = {
664 { INPUT, & HW_ENT (HW_H_SINT), CGEN_MODE_SI, & OP_ENT (SIMM8), 0 },
665 { OUTPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0 },
669 static const CGEN_OPERAND_INSTANCE fmt_39_ldi16_ops[] = {
670 { INPUT, & HW_ENT (HW_H_SLO16), CGEN_MODE_HI, & OP_ENT (SLO16), 0 },
671 { OUTPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0 },
675 static const CGEN_OPERAND_INSTANCE fmt_40_lock_ops[] = {
676 { INPUT, & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0 },
677 { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SR), 0 },
678 { OUTPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0 },
679 { OUTPUT, & HW_ENT (HW_H_LOCK), CGEN_MODE_UBI, 0, 0 },
683 static const CGEN_OPERAND_INSTANCE fmt_41_machi_ops[] = {
684 { INPUT, & HW_ENT (HW_H_ACCUM), CGEN_MODE_DI, 0, 0 },
685 { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC1), 0 },
686 { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC2), 0 },
687 { OUTPUT, & HW_ENT (HW_H_ACCUM), CGEN_MODE_DI, 0, 0 },
691 static const CGEN_OPERAND_INSTANCE fmt_42_machi_a_ops[] = {
692 { INPUT, & HW_ENT (HW_H_ACCUMS), CGEN_MODE_DI, & OP_ENT (ACC), 0 },
693 { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC1), 0 },
694 { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC2), 0 },
695 { OUTPUT, & HW_ENT (HW_H_ACCUMS), CGEN_MODE_DI, & OP_ENT (ACC), 0 },
699 static const CGEN_OPERAND_INSTANCE fmt_43_mulhi_ops[] = {
700 { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC1), 0 },
701 { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC2), 0 },
702 { OUTPUT, & HW_ENT (HW_H_ACCUM), CGEN_MODE_DI, 0, 0 },
706 static const CGEN_OPERAND_INSTANCE fmt_44_mulhi_a_ops[] = {
707 { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC1), 0 },
708 { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC2), 0 },
709 { OUTPUT, & HW_ENT (HW_H_ACCUMS), CGEN_MODE_DI, & OP_ENT (ACC), 0 },
713 static const CGEN_OPERAND_INSTANCE fmt_45_mv_ops[] = {
714 { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SR), 0 },
715 { OUTPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0 },
719 static const CGEN_OPERAND_INSTANCE fmt_46_mvfachi_ops[] = {
720 { INPUT, & HW_ENT (HW_H_ACCUM), CGEN_MODE_DI, 0, 0 },
721 { OUTPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0 },
725 static const CGEN_OPERAND_INSTANCE fmt_47_mvfachi_a_ops[] = {
726 { INPUT, & HW_ENT (HW_H_ACCUMS), CGEN_MODE_DI, & OP_ENT (ACCS), 0 },
727 { OUTPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0 },
731 static const CGEN_OPERAND_INSTANCE fmt_48_mvfc_ops[] = {
732 { INPUT, & HW_ENT (HW_H_CR), CGEN_MODE_USI, & OP_ENT (SCR), 0 },
733 { OUTPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0 },
737 static const CGEN_OPERAND_INSTANCE fmt_49_mvtachi_ops[] = {
738 { INPUT, & HW_ENT (HW_H_ACCUM), CGEN_MODE_DI, 0, 0 },
739 { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC1), 0 },
740 { OUTPUT, & HW_ENT (HW_H_ACCUM), CGEN_MODE_DI, 0, 0 },
744 static const CGEN_OPERAND_INSTANCE fmt_50_mvtachi_a_ops[] = {
745 { INPUT, & HW_ENT (HW_H_ACCUMS), CGEN_MODE_DI, & OP_ENT (ACCS), 0 },
746 { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC1), 0 },
747 { OUTPUT, & HW_ENT (HW_H_ACCUMS), CGEN_MODE_DI, & OP_ENT (ACCS), 0 },
751 static const CGEN_OPERAND_INSTANCE fmt_51_mvtc_ops[] = {
752 { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SR), 0 },
753 { OUTPUT, & HW_ENT (HW_H_CR), CGEN_MODE_USI, & OP_ENT (DCR), 0 },
757 static const CGEN_OPERAND_INSTANCE fmt_53_rac_ops[] = {
758 { INPUT, & HW_ENT (HW_H_ACCUM), CGEN_MODE_DI, 0, 0 },
759 { OUTPUT, & HW_ENT (HW_H_ACCUM), CGEN_MODE_DI, 0, 0 },
763 static const CGEN_OPERAND_INSTANCE fmt_56_rac_dsi_ops[] = {
764 { INPUT, & HW_ENT (HW_H_ACCUMS), CGEN_MODE_DI, & OP_ENT (ACCS), 0 },
765 { INPUT, & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (IMM1), 0 },
766 { OUTPUT, & HW_ENT (HW_H_ACCUMS), CGEN_MODE_DI, & OP_ENT (ACCD), 0 },
770 static const CGEN_OPERAND_INSTANCE fmt_57_rte_ops[] = {
771 { INPUT, & HW_ENT (HW_H_BCOND), CGEN_MODE_VM, 0, 0 },
772 { INPUT, & HW_ENT (HW_H_BIE), CGEN_MODE_VM, 0, 0 },
773 { INPUT, & HW_ENT (HW_H_BPC), CGEN_MODE_VM, 0, 0 },
774 { INPUT, & HW_ENT (HW_H_BSM), CGEN_MODE_VM, 0, 0 },
775 { OUTPUT, & HW_ENT (HW_H_COND), CGEN_MODE_UBI, 0, 0 },
776 { OUTPUT, & HW_ENT (HW_H_PC), CGEN_MODE_USI, 0, 0 },
777 { OUTPUT, & HW_ENT (HW_H_IE), CGEN_MODE_VM, 0, 0 },
778 { OUTPUT, & HW_ENT (HW_H_SM), CGEN_MODE_VM, 0, 0 },
782 static const CGEN_OPERAND_INSTANCE fmt_58_seth_ops[] = {
783 { INPUT, & HW_ENT (HW_H_HI16), CGEN_MODE_UHI, & OP_ENT (HI16), 0 },
784 { OUTPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0 },
788 static const CGEN_OPERAND_INSTANCE fmt_59_sll3_ops[] = {
789 { INPUT, & HW_ENT (HW_H_SINT), CGEN_MODE_SI, & OP_ENT (SIMM16), 0 },
790 { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SR), 0 },
791 { OUTPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0 },
795 static const CGEN_OPERAND_INSTANCE fmt_60_slli_ops[] = {
796 { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0 },
797 { INPUT, & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (UIMM5), 0 },
798 { OUTPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0 },
802 static const CGEN_OPERAND_INSTANCE fmt_61_st_ops[] = {
803 { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC1), 0 },
804 { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC2), 0 },
805 { OUTPUT, & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0 },
809 static const CGEN_OPERAND_INSTANCE fmt_63_st_d_ops[] = {
810 { INPUT, & HW_ENT (HW_H_SLO16), CGEN_MODE_HI, & OP_ENT (SLO16), 0 },
811 { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC1), 0 },
812 { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC2), 0 },
813 { OUTPUT, & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0 },
817 static const CGEN_OPERAND_INSTANCE fmt_65_stb_ops[] = {
818 { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC1), 0 },
819 { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC2), 0 },
820 { OUTPUT, & HW_ENT (HW_H_MEMORY), CGEN_MODE_QI, 0, 0 },
824 static const CGEN_OPERAND_INSTANCE fmt_66_stb_d_ops[] = {
825 { INPUT, & HW_ENT (HW_H_SLO16), CGEN_MODE_HI, & OP_ENT (SLO16), 0 },
826 { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC1), 0 },
827 { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC2), 0 },
828 { OUTPUT, & HW_ENT (HW_H_MEMORY), CGEN_MODE_QI, 0, 0 },
832 static const CGEN_OPERAND_INSTANCE fmt_67_sth_ops[] = {
833 { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC1), 0 },
834 { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC2), 0 },
835 { OUTPUT, & HW_ENT (HW_H_MEMORY), CGEN_MODE_HI, 0, 0 },
839 static const CGEN_OPERAND_INSTANCE fmt_68_sth_d_ops[] = {
840 { INPUT, & HW_ENT (HW_H_SLO16), CGEN_MODE_HI, & OP_ENT (SLO16), 0 },
841 { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC1), 0 },
842 { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC2), 0 },
843 { OUTPUT, & HW_ENT (HW_H_MEMORY), CGEN_MODE_HI, 0, 0 },
847 static const CGEN_OPERAND_INSTANCE fmt_69_st_plus_ops[] = {
848 { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC1), 0 },
849 { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC2), 0 },
850 { OUTPUT, & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0 },
851 { OUTPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC2), 0 },
855 static const CGEN_OPERAND_INSTANCE fmt_70_trap_ops[] = {
856 { INPUT, & HW_ENT (HW_H_PC), CGEN_MODE_USI, 0, 0 },
857 { INPUT, & HW_ENT (HW_H_CR), CGEN_MODE_SI, 0, 0 },
858 { INPUT, & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (UIMM4), 0 },
859 { OUTPUT, & HW_ENT (HW_H_PC), CGEN_MODE_USI, 0, 0 },
860 { OUTPUT, & HW_ENT (HW_H_CR), CGEN_MODE_SI, 0, 0 },
861 { OUTPUT, & HW_ENT (HW_H_CR), CGEN_MODE_SI, 0, 6 },
865 static const CGEN_OPERAND_INSTANCE fmt_71_unlock_ops[] = {
866 { INPUT, & HW_ENT (HW_H_LOCK), CGEN_MODE_UBI, 0, 0 },
867 { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC1), 0 },
868 { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC2), 0 },
869 { OUTPUT, & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0 },
870 { OUTPUT, & HW_ENT (HW_H_LOCK), CGEN_MODE_UBI, 0, 0 },
874 static const CGEN_OPERAND_INSTANCE fmt_74_satb_ops[] = {
875 { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SR), 0 },
876 { OUTPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0 },
880 static const CGEN_OPERAND_INSTANCE fmt_75_sat_ops[] = {
881 { INPUT, & HW_ENT (HW_H_COND), CGEN_MODE_UBI, 0, 0 },
882 { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SR), 0 },
883 { OUTPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0 },
887 static const CGEN_OPERAND_INSTANCE fmt_76_sadd_ops[] = {
888 { INPUT, & HW_ENT (HW_H_ACCUMS), CGEN_MODE_DI, 0, 0 },
889 { INPUT, & HW_ENT (HW_H_ACCUMS), CGEN_MODE_DI, 0, 1 },
890 { OUTPUT, & HW_ENT (HW_H_ACCUMS), CGEN_MODE_DI, 0, 0 },
894 static const CGEN_OPERAND_INSTANCE fmt_77_macwu1_ops[] = {
895 { INPUT, & HW_ENT (HW_H_ACCUMS), CGEN_MODE_DI, 0, 1 },
896 { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC1), 0 },
897 { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC2), 0 },
898 { OUTPUT, & HW_ENT (HW_H_ACCUMS), CGEN_MODE_DI, 0, 1 },
902 static const CGEN_OPERAND_INSTANCE fmt_78_mulwu1_ops[] = {
903 { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC1), 0 },
904 { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC2), 0 },
905 { OUTPUT, & HW_ENT (HW_H_ACCUMS), CGEN_MODE_DI, 0, 1 },
909 static const CGEN_OPERAND_INSTANCE fmt_79_sc_ops[] = {
910 { INPUT, & HW_ENT (HW_H_COND), CGEN_MODE_UBI, 0, 0 },
917 #define A(a) (1 << CONCAT2 (CGEN_INSN_,a))
918 #define MNEM CGEN_SYNTAX_MNEMONIC /* syntax value for mnemonic */
919 #define OP(field) CGEN_SYNTAX_MAKE_FIELD (OPERAND (field))
921 /* The instruction table. */
923 const CGEN_INSN m32r_cgen_insn_table_entries[MAX_INSNS] =
925 /* null first entry, end of all hash chains */
931 { MNEM, ' ', OP (DR), ',', OP (SR), 0 },
932 { 16, 16, 0xf0f0 }, 0xa0,
934 { CGEN_INSN_NBOOL_ATTRS, 0|A(PARALLEL), { (1<<MACH_M32R), PIPE_OS } }
936 /* add3 $dr,$sr,$hash$slo16 */
940 { MNEM, ' ', OP (DR), ',', OP (SR), ',', OP (HASH), OP (SLO16), 0 },
941 { 32, 32, 0xf0f00000 }, 0x80a00000,
943 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_NONE } }
949 { MNEM, ' ', OP (DR), ',', OP (SR), 0 },
950 { 16, 16, 0xf0f0 }, 0xc0,
952 { CGEN_INSN_NBOOL_ATTRS, 0|A(PARALLEL), { (1<<MACH_M32R), PIPE_OS } }
954 /* and3 $dr,$sr,$uimm16 */
958 { MNEM, ' ', OP (DR), ',', OP (SR), ',', OP (UIMM16), 0 },
959 { 32, 32, 0xf0f00000 }, 0x80c00000,
961 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_NONE } }
967 { MNEM, ' ', OP (DR), ',', OP (SR), 0 },
968 { 16, 16, 0xf0f0 }, 0xe0,
970 { CGEN_INSN_NBOOL_ATTRS, 0|A(PARALLEL), { (1<<MACH_M32R), PIPE_OS } }
972 /* or3 $dr,$sr,$hash$ulo16 */
976 { MNEM, ' ', OP (DR), ',', OP (SR), ',', OP (HASH), OP (ULO16), 0 },
977 { 32, 32, 0xf0f00000 }, 0x80e00000,
979 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_NONE } }
985 { MNEM, ' ', OP (DR), ',', OP (SR), 0 },
986 { 16, 16, 0xf0f0 }, 0xd0,
988 { CGEN_INSN_NBOOL_ATTRS, 0|A(PARALLEL), { (1<<MACH_M32R), PIPE_OS } }
990 /* xor3 $dr,$sr,$uimm16 */
994 { MNEM, ' ', OP (DR), ',', OP (SR), ',', OP (UIMM16), 0 },
995 { 32, 32, 0xf0f00000 }, 0x80d00000,
997 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_NONE } }
999 /* addi $dr,$simm8 */
1003 { MNEM, ' ', OP (DR), ',', OP (SIMM8), 0 },
1004 { 16, 16, 0xf000 }, 0x4000,
1005 & fmt_4_addi_ops[0],
1006 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_OS } }
1012 { MNEM, ' ', OP (DR), ',', OP (SR), 0 },
1013 { 16, 16, 0xf0f0 }, 0x80,
1014 & fmt_5_addv_ops[0],
1015 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_OS } }
1017 /* addv3 $dr,$sr,$simm16 */
1021 { MNEM, ' ', OP (DR), ',', OP (SR), ',', OP (SIMM16), 0 },
1022 { 32, 32, 0xf0f00000 }, 0x80800000,
1023 & fmt_6_addv3_ops[0],
1024 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_NONE } }
1030 { MNEM, ' ', OP (DR), ',', OP (SR), 0 },
1031 { 16, 16, 0xf0f0 }, 0x90,
1032 & fmt_7_addx_ops[0],
1033 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_OS } }
1039 { MNEM, ' ', OP (DISP8), 0 },
1040 { 16, 16, 0xff00 }, 0x7c00,
1042 { CGEN_INSN_NBOOL_ATTRS, 0|A(RELAXABLE)|A(COND_CTI), { (1<<MACH_M32R), PIPE_O } }
1048 { MNEM, ' ', OP (DISP8), 0 },
1049 { 16, 16, 0xff00 }, 0x7c00,
1051 { CGEN_INSN_NBOOL_ATTRS, 0|A(ALIAS)|A(COND_CTI), { (1<<MACH_M32R), PIPE_O } }
1057 { MNEM, ' ', OP (DISP24), 0 },
1058 { 32, 32, 0xff000000 }, 0xfc000000,
1059 & fmt_10_bc24_ops[0],
1060 { CGEN_INSN_NBOOL_ATTRS, 0|A(RELAX)|A(COND_CTI), { (1<<MACH_M32R), PIPE_NONE } }
1066 { MNEM, ' ', OP (DISP24), 0 },
1067 { 32, 32, 0xff000000 }, 0xfc000000,
1069 { CGEN_INSN_NBOOL_ATTRS, 0|A(ALIAS)|A(COND_CTI), { (1<<MACH_M32R), PIPE_NONE } }
1071 /* beq $src1,$src2,$disp16 */
1075 { MNEM, ' ', OP (SRC1), ',', OP (SRC2), ',', OP (DISP16), 0 },
1076 { 32, 32, 0xf0f00000 }, 0xb0000000,
1077 & fmt_12_beq_ops[0],
1078 { CGEN_INSN_NBOOL_ATTRS, 0|A(COND_CTI), { (1<<MACH_M32R), PIPE_NONE } }
1080 /* beqz $src2,$disp16 */
1084 { MNEM, ' ', OP (SRC2), ',', OP (DISP16), 0 },
1085 { 32, 32, 0xfff00000 }, 0xb0800000,
1086 & fmt_13_beqz_ops[0],
1087 { CGEN_INSN_NBOOL_ATTRS, 0|A(COND_CTI), { (1<<MACH_M32R), PIPE_NONE } }
1089 /* bgez $src2,$disp16 */
1093 { MNEM, ' ', OP (SRC2), ',', OP (DISP16), 0 },
1094 { 32, 32, 0xfff00000 }, 0xb0b00000,
1095 & fmt_13_beqz_ops[0],
1096 { CGEN_INSN_NBOOL_ATTRS, 0|A(COND_CTI), { (1<<MACH_M32R), PIPE_NONE } }
1098 /* bgtz $src2,$disp16 */
1102 { MNEM, ' ', OP (SRC2), ',', OP (DISP16), 0 },
1103 { 32, 32, 0xfff00000 }, 0xb0d00000,
1104 & fmt_13_beqz_ops[0],
1105 { CGEN_INSN_NBOOL_ATTRS, 0|A(COND_CTI), { (1<<MACH_M32R), PIPE_NONE } }
1107 /* blez $src2,$disp16 */
1111 { MNEM, ' ', OP (SRC2), ',', OP (DISP16), 0 },
1112 { 32, 32, 0xfff00000 }, 0xb0c00000,
1113 & fmt_13_beqz_ops[0],
1114 { CGEN_INSN_NBOOL_ATTRS, 0|A(COND_CTI), { (1<<MACH_M32R), PIPE_NONE } }
1116 /* bltz $src2,$disp16 */
1120 { MNEM, ' ', OP (SRC2), ',', OP (DISP16), 0 },
1121 { 32, 32, 0xfff00000 }, 0xb0a00000,
1122 & fmt_13_beqz_ops[0],
1123 { CGEN_INSN_NBOOL_ATTRS, 0|A(COND_CTI), { (1<<MACH_M32R), PIPE_NONE } }
1125 /* bnez $src2,$disp16 */
1129 { MNEM, ' ', OP (SRC2), ',', OP (DISP16), 0 },
1130 { 32, 32, 0xfff00000 }, 0xb0900000,
1131 & fmt_13_beqz_ops[0],
1132 { CGEN_INSN_NBOOL_ATTRS, 0|A(COND_CTI), { (1<<MACH_M32R), PIPE_NONE } }
1138 { MNEM, ' ', OP (DISP8), 0 },
1139 { 16, 16, 0xff00 }, 0x7e00,
1140 & fmt_14_bl8_ops[0],
1141 { CGEN_INSN_NBOOL_ATTRS, 0|A(FILL_SLOT)|A(RELAXABLE)|A(UNCOND_CTI), { (1<<MACH_M32R), PIPE_O } }
1147 { MNEM, ' ', OP (DISP8), 0 },
1148 { 16, 16, 0xff00 }, 0x7e00,
1150 { CGEN_INSN_NBOOL_ATTRS, 0|A(FILL_SLOT)|A(ALIAS)|A(UNCOND_CTI), { (1<<MACH_M32R), PIPE_O } }
1156 { MNEM, ' ', OP (DISP24), 0 },
1157 { 32, 32, 0xff000000 }, 0xfe000000,
1158 & fmt_15_bl24_ops[0],
1159 { CGEN_INSN_NBOOL_ATTRS, 0|A(RELAX)|A(UNCOND_CTI), { (1<<MACH_M32R), PIPE_NONE } }
1165 { MNEM, ' ', OP (DISP24), 0 },
1166 { 32, 32, 0xff000000 }, 0xfe000000,
1168 { CGEN_INSN_NBOOL_ATTRS, 0|A(ALIAS)|A(UNCOND_CTI), { (1<<MACH_M32R), PIPE_NONE } }
1170 /* start-sanitize-m32rx */
1175 { MNEM, ' ', OP (DISP8), 0 },
1176 { 16, 16, 0xff00 }, 0x7800,
1177 & fmt_16_bcl8_ops[0],
1178 { CGEN_INSN_NBOOL_ATTRS, 0|A(RELAXABLE)|A(COND_CTI), { (1<<MACH_M32RX), PIPE_O } }
1180 /* end-sanitize-m32rx */
1181 /* start-sanitize-m32rx */
1186 { MNEM, ' ', OP (DISP8), 0 },
1187 { 16, 16, 0xff00 }, 0x7800,
1189 { CGEN_INSN_NBOOL_ATTRS, 0|A(ALIAS)|A(COND_CTI), { (1<<MACH_M32RX), PIPE_O } }
1191 /* end-sanitize-m32rx */
1192 /* start-sanitize-m32rx */
1197 { MNEM, ' ', OP (DISP24), 0 },
1198 { 32, 32, 0xff000000 }, 0xf8000000,
1199 & fmt_17_bcl24_ops[0],
1200 { CGEN_INSN_NBOOL_ATTRS, 0|A(RELAX)|A(COND_CTI), { (1<<MACH_M32RX), PIPE_NONE } }
1202 /* end-sanitize-m32rx */
1203 /* start-sanitize-m32rx */
1208 { MNEM, ' ', OP (DISP24), 0 },
1209 { 32, 32, 0xff000000 }, 0xf8000000,
1211 { CGEN_INSN_NBOOL_ATTRS, 0|A(ALIAS)|A(COND_CTI), { (1<<MACH_M32RX), PIPE_NONE } }
1213 /* end-sanitize-m32rx */
1218 { MNEM, ' ', OP (DISP8), 0 },
1219 { 16, 16, 0xff00 }, 0x7d00,
1221 { CGEN_INSN_NBOOL_ATTRS, 0|A(RELAXABLE)|A(COND_CTI), { (1<<MACH_M32R), PIPE_O } }
1227 { MNEM, ' ', OP (DISP8), 0 },
1228 { 16, 16, 0xff00 }, 0x7d00,
1230 { CGEN_INSN_NBOOL_ATTRS, 0|A(ALIAS)|A(COND_CTI), { (1<<MACH_M32R), PIPE_O } }
1236 { MNEM, ' ', OP (DISP24), 0 },
1237 { 32, 32, 0xff000000 }, 0xfd000000,
1238 & fmt_10_bc24_ops[0],
1239 { CGEN_INSN_NBOOL_ATTRS, 0|A(RELAX)|A(COND_CTI), { (1<<MACH_M32R), PIPE_NONE } }
1245 { MNEM, ' ', OP (DISP24), 0 },
1246 { 32, 32, 0xff000000 }, 0xfd000000,
1248 { CGEN_INSN_NBOOL_ATTRS, 0|A(ALIAS)|A(COND_CTI), { (1<<MACH_M32R), PIPE_NONE } }
1250 /* bne $src1,$src2,$disp16 */
1254 { MNEM, ' ', OP (SRC1), ',', OP (SRC2), ',', OP (DISP16), 0 },
1255 { 32, 32, 0xf0f00000 }, 0xb0100000,
1256 & fmt_12_beq_ops[0],
1257 { CGEN_INSN_NBOOL_ATTRS, 0|A(COND_CTI), { (1<<MACH_M32R), PIPE_NONE } }
1263 { MNEM, ' ', OP (DISP8), 0 },
1264 { 16, 16, 0xff00 }, 0x7f00,
1265 & fmt_18_bra8_ops[0],
1266 { CGEN_INSN_NBOOL_ATTRS, 0|A(FILL_SLOT)|A(RELAXABLE)|A(UNCOND_CTI), { (1<<MACH_M32R), PIPE_O } }
1272 { MNEM, ' ', OP (DISP8), 0 },
1273 { 16, 16, 0xff00 }, 0x7f00,
1275 { CGEN_INSN_NBOOL_ATTRS, 0|A(ALIAS)|A(UNCOND_CTI), { (1<<MACH_M32R), PIPE_O } }
1281 { MNEM, ' ', OP (DISP24), 0 },
1282 { 32, 32, 0xff000000 }, 0xff000000,
1283 & fmt_19_bra24_ops[0],
1284 { CGEN_INSN_NBOOL_ATTRS, 0|A(RELAX)|A(UNCOND_CTI), { (1<<MACH_M32R), PIPE_NONE } }
1290 { MNEM, ' ', OP (DISP24), 0 },
1291 { 32, 32, 0xff000000 }, 0xff000000,
1293 { CGEN_INSN_NBOOL_ATTRS, 0|A(ALIAS)|A(UNCOND_CTI), { (1<<MACH_M32R), PIPE_NONE } }
1295 /* start-sanitize-m32rx */
1300 { MNEM, ' ', OP (DISP8), 0 },
1301 { 16, 16, 0xff00 }, 0x7900,
1302 & fmt_16_bcl8_ops[0],
1303 { CGEN_INSN_NBOOL_ATTRS, 0|A(RELAXABLE)|A(COND_CTI), { (1<<MACH_M32RX), PIPE_O } }
1305 /* end-sanitize-m32rx */
1306 /* start-sanitize-m32rx */
1310 "bncl8.s", "bncl.s",
1311 { MNEM, ' ', OP (DISP8), 0 },
1312 { 16, 16, 0xff00 }, 0x7900,
1314 { CGEN_INSN_NBOOL_ATTRS, 0|A(ALIAS)|A(COND_CTI), { (1<<MACH_M32RX), PIPE_O } }
1316 /* end-sanitize-m32rx */
1317 /* start-sanitize-m32rx */
1322 { MNEM, ' ', OP (DISP24), 0 },
1323 { 32, 32, 0xff000000 }, 0xf9000000,
1324 & fmt_17_bcl24_ops[0],
1325 { CGEN_INSN_NBOOL_ATTRS, 0|A(RELAX)|A(COND_CTI), { (1<<MACH_M32RX), PIPE_NONE } }
1327 /* end-sanitize-m32rx */
1328 /* start-sanitize-m32rx */
1329 /* bncl.l $disp24 */
1332 "bncl24.l", "bncl.l",
1333 { MNEM, ' ', OP (DISP24), 0 },
1334 { 32, 32, 0xff000000 }, 0xf9000000,
1336 { CGEN_INSN_NBOOL_ATTRS, 0|A(ALIAS)|A(COND_CTI), { (1<<MACH_M32RX), PIPE_NONE } }
1338 /* end-sanitize-m32rx */
1339 /* cmp $src1,$src2 */
1343 { MNEM, ' ', OP (SRC1), ',', OP (SRC2), 0 },
1344 { 16, 16, 0xf0f0 }, 0x40,
1345 & fmt_20_cmp_ops[0],
1346 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_OS } }
1348 /* cmpi $src2,$simm16 */
1352 { MNEM, ' ', OP (SRC2), ',', OP (SIMM16), 0 },
1353 { 32, 32, 0xfff00000 }, 0x80400000,
1354 & fmt_21_cmpi_ops[0],
1355 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_NONE } }
1357 /* cmpu $src1,$src2 */
1361 { MNEM, ' ', OP (SRC1), ',', OP (SRC2), 0 },
1362 { 16, 16, 0xf0f0 }, 0x50,
1363 & fmt_20_cmp_ops[0],
1364 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_OS } }
1366 /* cmpui $src2,$uimm16 */
1370 { MNEM, ' ', OP (SRC2), ',', OP (UIMM16), 0 },
1371 { 32, 32, 0xfff00000 }, 0x80500000,
1372 & fmt_22_cmpui_ops[0],
1373 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_NONE } }
1375 /* start-sanitize-m32rx */
1376 /* cmpeq $src1,$src2 */
1380 { MNEM, ' ', OP (SRC1), ',', OP (SRC2), 0 },
1381 { 16, 16, 0xf0f0 }, 0x60,
1382 & fmt_20_cmp_ops[0],
1383 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32RX), PIPE_OS } }
1385 /* end-sanitize-m32rx */
1386 /* start-sanitize-m32rx */
1391 { MNEM, ' ', OP (SRC2), 0 },
1392 { 16, 16, 0xfff0 }, 0x70,
1393 & fmt_23_cmpz_ops[0],
1394 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32RX), PIPE_OS } }
1396 /* end-sanitize-m32rx */
1401 { MNEM, ' ', OP (DR), ',', OP (SR), 0 },
1402 { 32, 32, 0xf0f0ffff }, 0x90000000,
1403 & fmt_24_div_ops[0],
1404 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_NONE } }
1410 { MNEM, ' ', OP (DR), ',', OP (SR), 0 },
1411 { 32, 32, 0xf0f0ffff }, 0x90100000,
1412 & fmt_24_div_ops[0],
1413 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_NONE } }
1419 { MNEM, ' ', OP (DR), ',', OP (SR), 0 },
1420 { 32, 32, 0xf0f0ffff }, 0x90200000,
1421 & fmt_24_div_ops[0],
1422 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_NONE } }
1428 { MNEM, ' ', OP (DR), ',', OP (SR), 0 },
1429 { 32, 32, 0xf0f0ffff }, 0x90300000,
1430 & fmt_24_div_ops[0],
1431 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_NONE } }
1433 /* start-sanitize-m32rx */
1438 { MNEM, ' ', OP (DR), ',', OP (SR), 0 },
1439 { 32, 32, 0xf0f0ffff }, 0x90000010,
1440 & fmt_24_div_ops[0],
1441 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32RX), PIPE_NONE } }
1443 /* end-sanitize-m32rx */
1444 /* start-sanitize-m32rx */
1449 { MNEM, ' ', OP (SR), 0 },
1450 { 16, 16, 0xfff0 }, 0x1cc0,
1452 { CGEN_INSN_NBOOL_ATTRS, 0|A(COND_CTI), { (1<<MACH_M32RX), PIPE_O } }
1454 /* end-sanitize-m32rx */
1455 /* start-sanitize-m32rx */
1460 { MNEM, ' ', OP (SR), 0 },
1461 { 16, 16, 0xfff0 }, 0x1dc0,
1463 { CGEN_INSN_NBOOL_ATTRS, 0|A(COND_CTI), { (1<<MACH_M32RX), PIPE_O } }
1465 /* end-sanitize-m32rx */
1470 { MNEM, ' ', OP (SR), 0 },
1471 { 16, 16, 0xfff0 }, 0x1ec0,
1473 { CGEN_INSN_NBOOL_ATTRS, 0|A(FILL_SLOT)|A(UNCOND_CTI), { (1<<MACH_M32R), PIPE_O } }
1479 { MNEM, ' ', OP (SR), 0 },
1480 { 16, 16, 0xfff0 }, 0x1fc0,
1481 & fmt_27_jmp_ops[0],
1482 { CGEN_INSN_NBOOL_ATTRS, 0|A(UNCOND_CTI), { (1<<MACH_M32R), PIPE_O } }
1488 { MNEM, ' ', OP (DR), ',', '@', OP (SR), 0 },
1489 { 16, 16, 0xf0f0 }, 0x20c0,
1491 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_O } }
1497 { MNEM, ' ', OP (DR), ',', '@', '(', OP (SR), ')', 0 },
1498 { 16, 16, 0xf0f0 }, 0x20c0,
1500 { CGEN_INSN_NBOOL_ATTRS, 0|A(ALIAS), { (1<<MACH_M32R), PIPE_O } }
1502 /* ld $dr,@($slo16,$sr) */
1506 { MNEM, ' ', OP (DR), ',', '@', '(', OP (SLO16), ',', OP (SR), ')', 0 },
1507 { 32, 32, 0xf0f00000 }, 0xa0c00000,
1508 & fmt_30_ld_d_ops[0],
1509 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_NONE } }
1511 /* ld $dr,@($sr,$slo16) */
1515 { MNEM, ' ', OP (DR), ',', '@', '(', OP (SR), ',', OP (SLO16), ')', 0 },
1516 { 32, 32, 0xf0f00000 }, 0xa0c00000,
1518 { CGEN_INSN_NBOOL_ATTRS, 0|A(ALIAS), { (1<<MACH_M32R), PIPE_NONE } }
1524 { MNEM, ' ', OP (DR), ',', '@', OP (SR), 0 },
1525 { 16, 16, 0xf0f0 }, 0x2080,
1526 & fmt_32_ldb_ops[0],
1527 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_O } }
1529 /* ldb $dr,@($sr) */
1533 { MNEM, ' ', OP (DR), ',', '@', '(', OP (SR), ')', 0 },
1534 { 16, 16, 0xf0f0 }, 0x2080,
1536 { CGEN_INSN_NBOOL_ATTRS, 0|A(ALIAS), { (1<<MACH_M32R), PIPE_O } }
1538 /* ldb $dr,@($slo16,$sr) */
1542 { MNEM, ' ', OP (DR), ',', '@', '(', OP (SLO16), ',', OP (SR), ')', 0 },
1543 { 32, 32, 0xf0f00000 }, 0xa0800000,
1544 & fmt_33_ldb_d_ops[0],
1545 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_NONE } }
1547 /* ldb $dr,@($sr,$slo16) */
1551 { MNEM, ' ', OP (DR), ',', '@', '(', OP (SR), ',', OP (SLO16), ')', 0 },
1552 { 32, 32, 0xf0f00000 }, 0xa0800000,
1554 { CGEN_INSN_NBOOL_ATTRS, 0|A(ALIAS), { (1<<MACH_M32R), PIPE_NONE } }
1560 { MNEM, ' ', OP (DR), ',', '@', OP (SR), 0 },
1561 { 16, 16, 0xf0f0 }, 0x20a0,
1562 & fmt_34_ldh_ops[0],
1563 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_O } }
1565 /* ldh $dr,@($sr) */
1569 { MNEM, ' ', OP (DR), ',', '@', '(', OP (SR), ')', 0 },
1570 { 16, 16, 0xf0f0 }, 0x20a0,
1572 { CGEN_INSN_NBOOL_ATTRS, 0|A(ALIAS), { (1<<MACH_M32R), PIPE_O } }
1574 /* ldh $dr,@($slo16,$sr) */
1578 { MNEM, ' ', OP (DR), ',', '@', '(', OP (SLO16), ',', OP (SR), ')', 0 },
1579 { 32, 32, 0xf0f00000 }, 0xa0a00000,
1580 & fmt_35_ldh_d_ops[0],
1581 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_NONE } }
1583 /* ldh $dr,@($sr,$slo16) */
1587 { MNEM, ' ', OP (DR), ',', '@', '(', OP (SR), ',', OP (SLO16), ')', 0 },
1588 { 32, 32, 0xf0f00000 }, 0xa0a00000,
1590 { CGEN_INSN_NBOOL_ATTRS, 0|A(ALIAS), { (1<<MACH_M32R), PIPE_NONE } }
1596 { MNEM, ' ', OP (DR), ',', '@', OP (SR), 0 },
1597 { 16, 16, 0xf0f0 }, 0x2090,
1598 & fmt_32_ldb_ops[0],
1599 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_O } }
1601 /* ldub $dr,@($sr) */
1605 { MNEM, ' ', OP (DR), ',', '@', '(', OP (SR), ')', 0 },
1606 { 16, 16, 0xf0f0 }, 0x2090,
1608 { CGEN_INSN_NBOOL_ATTRS, 0|A(ALIAS), { (1<<MACH_M32R), PIPE_O } }
1610 /* ldub $dr,@($slo16,$sr) */
1614 { MNEM, ' ', OP (DR), ',', '@', '(', OP (SLO16), ',', OP (SR), ')', 0 },
1615 { 32, 32, 0xf0f00000 }, 0xa0900000,
1616 & fmt_33_ldb_d_ops[0],
1617 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_NONE } }
1619 /* ldub $dr,@($sr,$slo16) */
1623 { MNEM, ' ', OP (DR), ',', '@', '(', OP (SR), ',', OP (SLO16), ')', 0 },
1624 { 32, 32, 0xf0f00000 }, 0xa0900000,
1626 { CGEN_INSN_NBOOL_ATTRS, 0|A(ALIAS), { (1<<MACH_M32R), PIPE_NONE } }
1632 { MNEM, ' ', OP (DR), ',', '@', OP (SR), 0 },
1633 { 16, 16, 0xf0f0 }, 0x20b0,
1634 & fmt_34_ldh_ops[0],
1635 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_O } }
1637 /* lduh $dr,@($sr) */
1641 { MNEM, ' ', OP (DR), ',', '@', '(', OP (SR), ')', 0 },
1642 { 16, 16, 0xf0f0 }, 0x20b0,
1644 { CGEN_INSN_NBOOL_ATTRS, 0|A(ALIAS), { (1<<MACH_M32R), PIPE_O } }
1646 /* lduh $dr,@($slo16,$sr) */
1650 { MNEM, ' ', OP (DR), ',', '@', '(', OP (SLO16), ',', OP (SR), ')', 0 },
1651 { 32, 32, 0xf0f00000 }, 0xa0b00000,
1652 & fmt_35_ldh_d_ops[0],
1653 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_NONE } }
1655 /* lduh $dr,@($sr,$slo16) */
1659 { MNEM, ' ', OP (DR), ',', '@', '(', OP (SR), ',', OP (SLO16), ')', 0 },
1660 { 32, 32, 0xf0f00000 }, 0xa0b00000,
1662 { CGEN_INSN_NBOOL_ATTRS, 0|A(ALIAS), { (1<<MACH_M32R), PIPE_NONE } }
1668 { MNEM, ' ', OP (DR), ',', '@', OP (SR), '+', 0 },
1669 { 16, 16, 0xf0f0 }, 0x20e0,
1670 & fmt_36_ld_plus_ops[0],
1671 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_O } }
1673 /* ld24 $dr,$uimm24 */
1677 { MNEM, ' ', OP (DR), ',', OP (UIMM24), 0 },
1678 { 32, 32, 0xf0000000 }, 0xe0000000,
1679 & fmt_37_ld24_ops[0],
1680 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_NONE } }
1682 /* ldi $dr,$simm8 */
1686 { MNEM, ' ', OP (DR), ',', OP (SIMM8), 0 },
1687 { 16, 16, 0xf000 }, 0x6000,
1688 & fmt_38_ldi8_ops[0],
1689 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_OS } }
1691 /* ldi8 $dr,$simm8 */
1695 { MNEM, ' ', OP (DR), ',', OP (SIMM8), 0 },
1696 { 16, 16, 0xf000 }, 0x6000,
1697 & fmt_38_ldi8_ops[0],
1698 { CGEN_INSN_NBOOL_ATTRS, 0|A(ALIAS), { (1<<MACH_M32R), PIPE_OS } }
1700 /* ldi $dr,$hash$slo16 */
1704 { MNEM, ' ', OP (DR), ',', OP (HASH), OP (SLO16), 0 },
1705 { 32, 32, 0xf0ff0000 }, 0x90f00000,
1706 & fmt_39_ldi16_ops[0],
1707 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_NONE } }
1709 /* ldi16 $dr,$hash$slo16 */
1713 { MNEM, ' ', OP (DR), ',', OP (HASH), OP (SLO16), 0 },
1714 { 32, 32, 0xf0ff0000 }, 0x90f00000,
1715 & fmt_39_ldi16_ops[0],
1716 { CGEN_INSN_NBOOL_ATTRS, 0|A(ALIAS), { (1<<MACH_M32R), PIPE_NONE } }
1722 { MNEM, ' ', OP (DR), ',', '@', OP (SR), 0 },
1723 { 16, 16, 0xf0f0 }, 0x20d0,
1724 & fmt_40_lock_ops[0],
1725 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_O } }
1727 /* machi $src1,$src2 */
1731 { MNEM, ' ', OP (SRC1), ',', OP (SRC2), 0 },
1732 { 16, 16, 0xf0f0 }, 0x3040,
1733 & fmt_41_machi_ops[0],
1734 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_S } }
1736 /* start-sanitize-m32rx */
1737 /* machi $src1,$src2,$acc */
1741 { MNEM, ' ', OP (SRC1), ',', OP (SRC2), ',', OP (ACC), 0 },
1742 { 16, 16, 0xf070 }, 0x3040,
1743 & fmt_42_machi_a_ops[0],
1744 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32RX), PIPE_S } }
1746 /* end-sanitize-m32rx */
1747 /* maclo $src1,$src2 */
1751 { MNEM, ' ', OP (SRC1), ',', OP (SRC2), 0 },
1752 { 16, 16, 0xf0f0 }, 0x3050,
1753 & fmt_41_machi_ops[0],
1754 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_S } }
1756 /* start-sanitize-m32rx */
1757 /* maclo $src1,$src2,$acc */
1761 { MNEM, ' ', OP (SRC1), ',', OP (SRC2), ',', OP (ACC), 0 },
1762 { 16, 16, 0xf070 }, 0x3050,
1763 & fmt_42_machi_a_ops[0],
1764 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32RX), PIPE_S } }
1766 /* end-sanitize-m32rx */
1767 /* macwhi $src1,$src2 */
1771 { MNEM, ' ', OP (SRC1), ',', OP (SRC2), 0 },
1772 { 16, 16, 0xf0f0 }, 0x3060,
1773 & fmt_41_machi_ops[0],
1774 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_S } }
1776 /* macwlo $src1,$src2 */
1780 { MNEM, ' ', OP (SRC1), ',', OP (SRC2), 0 },
1781 { 16, 16, 0xf0f0 }, 0x3070,
1782 & fmt_41_machi_ops[0],
1783 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_S } }
1789 { MNEM, ' ', OP (DR), ',', OP (SR), 0 },
1790 { 16, 16, 0xf0f0 }, 0x1060,
1792 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_S } }
1794 /* mulhi $src1,$src2 */
1798 { MNEM, ' ', OP (SRC1), ',', OP (SRC2), 0 },
1799 { 16, 16, 0xf0f0 }, 0x3000,
1800 & fmt_43_mulhi_ops[0],
1801 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_S } }
1803 /* start-sanitize-m32rx */
1804 /* mulhi $src1,$src2,$acc */
1808 { MNEM, ' ', OP (SRC1), ',', OP (SRC2), ',', OP (ACC), 0 },
1809 { 16, 16, 0xf070 }, 0x3000,
1810 & fmt_44_mulhi_a_ops[0],
1811 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32RX), PIPE_S } }
1813 /* end-sanitize-m32rx */
1814 /* mullo $src1,$src2 */
1818 { MNEM, ' ', OP (SRC1), ',', OP (SRC2), 0 },
1819 { 16, 16, 0xf0f0 }, 0x3010,
1820 & fmt_43_mulhi_ops[0],
1821 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_S } }
1823 /* start-sanitize-m32rx */
1824 /* mullo $src1,$src2,$acc */
1828 { MNEM, ' ', OP (SRC1), ',', OP (SRC2), ',', OP (ACC), 0 },
1829 { 16, 16, 0xf070 }, 0x3010,
1830 & fmt_44_mulhi_a_ops[0],
1831 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32RX), PIPE_S } }
1833 /* end-sanitize-m32rx */
1834 /* mulwhi $src1,$src2 */
1838 { MNEM, ' ', OP (SRC1), ',', OP (SRC2), 0 },
1839 { 16, 16, 0xf0f0 }, 0x3020,
1840 & fmt_43_mulhi_ops[0],
1841 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_S } }
1843 /* mulwlo $src1,$src2 */
1847 { MNEM, ' ', OP (SRC1), ',', OP (SRC2), 0 },
1848 { 16, 16, 0xf0f0 }, 0x3030,
1849 & fmt_43_mulhi_ops[0],
1850 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_S } }
1856 { MNEM, ' ', OP (DR), ',', OP (SR), 0 },
1857 { 16, 16, 0xf0f0 }, 0x1080,
1859 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_OS } }
1864 "mvfachi", "mvfachi",
1865 { MNEM, ' ', OP (DR), 0 },
1866 { 16, 16, 0xf0ff }, 0x50f0,
1867 & fmt_46_mvfachi_ops[0],
1868 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_S } }
1870 /* start-sanitize-m32rx */
1871 /* mvfachi $dr,$accs */
1874 "mvfachi-a", "mvfachi",
1875 { MNEM, ' ', OP (DR), ',', OP (ACCS), 0 },
1876 { 16, 16, 0xf0f3 }, 0x50f0,
1877 & fmt_47_mvfachi_a_ops[0],
1878 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32RX), PIPE_S } }
1880 /* end-sanitize-m32rx */
1884 "mvfaclo", "mvfaclo",
1885 { MNEM, ' ', OP (DR), 0 },
1886 { 16, 16, 0xf0ff }, 0x50f1,
1887 & fmt_46_mvfachi_ops[0],
1888 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_S } }
1890 /* start-sanitize-m32rx */
1891 /* mvfaclo $dr,$accs */
1894 "mvfaclo-a", "mvfaclo",
1895 { MNEM, ' ', OP (DR), ',', OP (ACCS), 0 },
1896 { 16, 16, 0xf0f3 }, 0x50f1,
1897 & fmt_47_mvfachi_a_ops[0],
1898 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32RX), PIPE_S } }
1900 /* end-sanitize-m32rx */
1904 "mvfacmi", "mvfacmi",
1905 { MNEM, ' ', OP (DR), 0 },
1906 { 16, 16, 0xf0ff }, 0x50f2,
1907 & fmt_46_mvfachi_ops[0],
1908 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_S } }
1910 /* start-sanitize-m32rx */
1911 /* mvfacmi $dr,$accs */
1914 "mvfacmi-a", "mvfacmi",
1915 { MNEM, ' ', OP (DR), ',', OP (ACCS), 0 },
1916 { 16, 16, 0xf0f3 }, 0x50f2,
1917 & fmt_47_mvfachi_a_ops[0],
1918 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32RX), PIPE_S } }
1920 /* end-sanitize-m32rx */
1925 { MNEM, ' ', OP (DR), ',', OP (SCR), 0 },
1926 { 16, 16, 0xf0f0 }, 0x1090,
1927 & fmt_48_mvfc_ops[0],
1928 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_O } }
1933 "mvtachi", "mvtachi",
1934 { MNEM, ' ', OP (SRC1), 0 },
1935 { 16, 16, 0xf0ff }, 0x5070,
1936 & fmt_49_mvtachi_ops[0],
1937 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_S } }
1939 /* start-sanitize-m32rx */
1940 /* mvtachi $src1,$accs */
1943 "mvtachi-a", "mvtachi",
1944 { MNEM, ' ', OP (SRC1), ',', OP (ACCS), 0 },
1945 { 16, 16, 0xf0f3 }, 0x5070,
1946 & fmt_50_mvtachi_a_ops[0],
1947 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32RX), PIPE_S } }
1949 /* end-sanitize-m32rx */
1953 "mvtaclo", "mvtaclo",
1954 { MNEM, ' ', OP (SRC1), 0 },
1955 { 16, 16, 0xf0ff }, 0x5071,
1956 & fmt_49_mvtachi_ops[0],
1957 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_S } }
1959 /* start-sanitize-m32rx */
1960 /* mvtaclo $src1,$accs */
1963 "mvtaclo-a", "mvtaclo",
1964 { MNEM, ' ', OP (SRC1), ',', OP (ACCS), 0 },
1965 { 16, 16, 0xf0f3 }, 0x5071,
1966 & fmt_50_mvtachi_a_ops[0],
1967 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32RX), PIPE_S } }
1969 /* end-sanitize-m32rx */
1974 { MNEM, ' ', OP (SR), ',', OP (DCR), 0 },
1975 { 16, 16, 0xf0f0 }, 0x10a0,
1976 & fmt_51_mvtc_ops[0],
1977 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_O } }
1983 { MNEM, ' ', OP (DR), ',', OP (SR), 0 },
1984 { 16, 16, 0xf0f0 }, 0x30,
1986 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_OS } }
1993 { 16, 16, 0xffff }, 0x7000,
1995 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_OS } }
2001 { MNEM, ' ', OP (DR), ',', OP (SR), 0 },
2002 { 16, 16, 0xf0f0 }, 0xb0,
2004 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_OS } }
2011 { 16, 16, 0xffff }, 0x5090,
2012 & fmt_53_rac_ops[0],
2013 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_S } }
2015 /* start-sanitize-m32rx */
2020 { MNEM, ' ', OP (ACCD), 0 },
2021 { 16, 16, 0xf3ff }, 0x5090,
2023 { CGEN_INSN_NBOOL_ATTRS, 0|A(ALIAS), { (1<<MACH_M32R), PIPE_NONE } }
2025 /* end-sanitize-m32rx */
2026 /* start-sanitize-m32rx */
2027 /* rac $accd,$accs */
2031 { MNEM, ' ', OP (ACCD), ',', OP (ACCS), 0 },
2032 { 16, 16, 0xf3f3 }, 0x5090,
2034 { CGEN_INSN_NBOOL_ATTRS, 0|A(ALIAS), { (1<<MACH_M32R), PIPE_NONE } }
2036 /* end-sanitize-m32rx */
2037 /* start-sanitize-m32rx */
2038 /* rac $accd,$accs,$imm1 */
2042 { MNEM, ' ', OP (ACCD), ',', OP (ACCS), ',', OP (IMM1), 0 },
2043 { 16, 16, 0xf3f2 }, 0x5090,
2044 & fmt_56_rac_dsi_ops[0],
2045 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32RX), PIPE_S } }
2047 /* end-sanitize-m32rx */
2053 { 16, 16, 0xffff }, 0x5080,
2054 & fmt_53_rac_ops[0],
2055 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_S } }
2057 /* start-sanitize-m32rx */
2062 { MNEM, ' ', OP (ACCD), 0 },
2063 { 16, 16, 0xf3ff }, 0x5080,
2065 { CGEN_INSN_NBOOL_ATTRS, 0|A(ALIAS), { (1<<MACH_M32R), PIPE_NONE } }
2067 /* end-sanitize-m32rx */
2068 /* start-sanitize-m32rx */
2069 /* rach $accd,$accs */
2073 { MNEM, ' ', OP (ACCD), ',', OP (ACCS), 0 },
2074 { 16, 16, 0xf3f3 }, 0x5080,
2076 { CGEN_INSN_NBOOL_ATTRS, 0|A(ALIAS), { (1<<MACH_M32R), PIPE_NONE } }
2078 /* end-sanitize-m32rx */
2079 /* start-sanitize-m32rx */
2080 /* rach $accd,$accs,$imm1 */
2084 { MNEM, ' ', OP (ACCD), ',', OP (ACCS), ',', OP (IMM1), 0 },
2085 { 16, 16, 0xf3f2 }, 0x5080,
2086 & fmt_56_rac_dsi_ops[0],
2087 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32RX), PIPE_S } }
2089 /* end-sanitize-m32rx */
2095 { 16, 16, 0xffff }, 0x10d6,
2096 & fmt_57_rte_ops[0],
2097 { CGEN_INSN_NBOOL_ATTRS, 0|A(UNCOND_CTI), { (1<<MACH_M32R), PIPE_O } }
2099 /* seth $dr,$hash$hi16 */
2103 { MNEM, ' ', OP (DR), ',', OP (HASH), OP (HI16), 0 },
2104 { 32, 32, 0xf0ff0000 }, 0xd0c00000,
2105 & fmt_58_seth_ops[0],
2106 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_NONE } }
2112 { MNEM, ' ', OP (DR), ',', OP (SR), 0 },
2113 { 16, 16, 0xf0f0 }, 0x1040,
2115 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_O } }
2117 /* sll3 $dr,$sr,$simm16 */
2121 { MNEM, ' ', OP (DR), ',', OP (SR), ',', OP (SIMM16), 0 },
2122 { 32, 32, 0xf0f00000 }, 0x90c00000,
2123 & fmt_59_sll3_ops[0],
2124 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_NONE } }
2126 /* slli $dr,$uimm5 */
2130 { MNEM, ' ', OP (DR), ',', OP (UIMM5), 0 },
2131 { 16, 16, 0xf0e0 }, 0x5040,
2132 & fmt_60_slli_ops[0],
2133 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_O } }
2139 { MNEM, ' ', OP (DR), ',', OP (SR), 0 },
2140 { 16, 16, 0xf0f0 }, 0x1020,
2142 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_O } }
2144 /* sra3 $dr,$sr,$simm16 */
2148 { MNEM, ' ', OP (DR), ',', OP (SR), ',', OP (SIMM16), 0 },
2149 { 32, 32, 0xf0f00000 }, 0x90a00000,
2150 & fmt_59_sll3_ops[0],
2151 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_NONE } }
2153 /* srai $dr,$uimm5 */
2157 { MNEM, ' ', OP (DR), ',', OP (UIMM5), 0 },
2158 { 16, 16, 0xf0e0 }, 0x5020,
2159 & fmt_60_slli_ops[0],
2160 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_O } }
2166 { MNEM, ' ', OP (DR), ',', OP (SR), 0 },
2167 { 16, 16, 0xf0f0 }, 0x1000,
2169 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_O } }
2171 /* srl3 $dr,$sr,$simm16 */
2175 { MNEM, ' ', OP (DR), ',', OP (SR), ',', OP (SIMM16), 0 },
2176 { 32, 32, 0xf0f00000 }, 0x90800000,
2177 & fmt_59_sll3_ops[0],
2178 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_NONE } }
2180 /* srli $dr,$uimm5 */
2184 { MNEM, ' ', OP (DR), ',', OP (UIMM5), 0 },
2185 { 16, 16, 0xf0e0 }, 0x5000,
2186 & fmt_60_slli_ops[0],
2187 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_O } }
2189 /* st $src1,@$src2 */
2193 { MNEM, ' ', OP (SRC1), ',', '@', OP (SRC2), 0 },
2194 { 16, 16, 0xf0f0 }, 0x2040,
2196 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_O } }
2198 /* st $src1,@($src2) */
2202 { MNEM, ' ', OP (SRC1), ',', '@', '(', OP (SRC2), ')', 0 },
2203 { 16, 16, 0xf0f0 }, 0x2040,
2205 { CGEN_INSN_NBOOL_ATTRS, 0|A(ALIAS), { (1<<MACH_M32R), PIPE_O } }
2207 /* st $src1,@($slo16,$src2) */
2211 { MNEM, ' ', OP (SRC1), ',', '@', '(', OP (SLO16), ',', OP (SRC2), ')', 0 },
2212 { 32, 32, 0xf0f00000 }, 0xa0400000,
2213 & fmt_63_st_d_ops[0],
2214 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_NONE } }
2216 /* st $src1,@($src2,$slo16) */
2220 { MNEM, ' ', OP (SRC1), ',', '@', '(', OP (SRC2), ',', OP (SLO16), ')', 0 },
2221 { 32, 32, 0xf0f00000 }, 0xa0400000,
2223 { CGEN_INSN_NBOOL_ATTRS, 0|A(ALIAS), { (1<<MACH_M32R), PIPE_NONE } }
2225 /* stb $src1,@$src2 */
2229 { MNEM, ' ', OP (SRC1), ',', '@', OP (SRC2), 0 },
2230 { 16, 16, 0xf0f0 }, 0x2000,
2231 & fmt_65_stb_ops[0],
2232 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_O } }
2234 /* stb $src1,@($src2) */
2238 { MNEM, ' ', OP (SRC1), ',', '@', '(', OP (SRC2), ')', 0 },
2239 { 16, 16, 0xf0f0 }, 0x2000,
2241 { CGEN_INSN_NBOOL_ATTRS, 0|A(ALIAS), { (1<<MACH_M32R), PIPE_O } }
2243 /* stb $src1,@($slo16,$src2) */
2247 { MNEM, ' ', OP (SRC1), ',', '@', '(', OP (SLO16), ',', OP (SRC2), ')', 0 },
2248 { 32, 32, 0xf0f00000 }, 0xa0000000,
2249 & fmt_66_stb_d_ops[0],
2250 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_NONE } }
2252 /* stb $src1,@($src2,$slo16) */
2256 { MNEM, ' ', OP (SRC1), ',', '@', '(', OP (SRC2), ',', OP (SLO16), ')', 0 },
2257 { 32, 32, 0xf0f00000 }, 0xa0000000,
2259 { CGEN_INSN_NBOOL_ATTRS, 0|A(ALIAS), { (1<<MACH_M32R), PIPE_NONE } }
2261 /* sth $src1,@$src2 */
2265 { MNEM, ' ', OP (SRC1), ',', '@', OP (SRC2), 0 },
2266 { 16, 16, 0xf0f0 }, 0x2020,
2267 & fmt_67_sth_ops[0],
2268 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_O } }
2270 /* sth $src1,@($src2) */
2274 { MNEM, ' ', OP (SRC1), ',', '@', '(', OP (SRC2), ')', 0 },
2275 { 16, 16, 0xf0f0 }, 0x2020,
2277 { CGEN_INSN_NBOOL_ATTRS, 0|A(ALIAS), { (1<<MACH_M32R), PIPE_O } }
2279 /* sth $src1,@($slo16,$src2) */
2283 { MNEM, ' ', OP (SRC1), ',', '@', '(', OP (SLO16), ',', OP (SRC2), ')', 0 },
2284 { 32, 32, 0xf0f00000 }, 0xa0200000,
2285 & fmt_68_sth_d_ops[0],
2286 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_NONE } }
2288 /* sth $src1,@($src2,$slo16) */
2292 { MNEM, ' ', OP (SRC1), ',', '@', '(', OP (SRC2), ',', OP (SLO16), ')', 0 },
2293 { 32, 32, 0xf0f00000 }, 0xa0200000,
2295 { CGEN_INSN_NBOOL_ATTRS, 0|A(ALIAS), { (1<<MACH_M32R), PIPE_NONE } }
2297 /* st $src1,@+$src2 */
2301 { MNEM, ' ', OP (SRC1), ',', '@', '+', OP (SRC2), 0 },
2302 { 16, 16, 0xf0f0 }, 0x2060,
2303 & fmt_69_st_plus_ops[0],
2304 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_O } }
2306 /* st $src1,@-$src2 */
2310 { MNEM, ' ', OP (SRC1), ',', '@', '-', OP (SRC2), 0 },
2311 { 16, 16, 0xf0f0 }, 0x2070,
2312 & fmt_69_st_plus_ops[0],
2313 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_O } }
2319 { MNEM, ' ', OP (DR), ',', OP (SR), 0 },
2320 { 16, 16, 0xf0f0 }, 0x20,
2322 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_OS } }
2328 { MNEM, ' ', OP (DR), ',', OP (SR), 0 },
2329 { 16, 16, 0xf0f0 }, 0x0,
2330 & fmt_5_addv_ops[0],
2331 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_OS } }
2337 { MNEM, ' ', OP (DR), ',', OP (SR), 0 },
2338 { 16, 16, 0xf0f0 }, 0x10,
2339 & fmt_7_addx_ops[0],
2340 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_OS } }
2346 { MNEM, ' ', OP (UIMM4), 0 },
2347 { 16, 16, 0xfff0 }, 0x10f0,
2348 & fmt_70_trap_ops[0],
2349 { CGEN_INSN_NBOOL_ATTRS, 0|A(FILL_SLOT)|A(UNCOND_CTI), { (1<<MACH_M32R), PIPE_O } }
2351 /* unlock $src1,@$src2 */
2355 { MNEM, ' ', OP (SRC1), ',', '@', OP (SRC2), 0 },
2356 { 16, 16, 0xf0f0 }, 0x2050,
2357 & fmt_71_unlock_ops[0],
2358 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_O } }
2364 { MNEM, ' ', OP (SRC1), 0 },
2365 { 16, 16, 0xf0ff }, 0x207f,
2367 { CGEN_INSN_NBOOL_ATTRS, 0|A(ALIAS), { (1<<MACH_M32R), PIPE_NONE } }
2373 { MNEM, ' ', OP (DR), 0 },
2374 { 16, 16, 0xf0ff }, 0x20ef,
2376 { CGEN_INSN_NBOOL_ATTRS, 0|A(ALIAS), { (1<<MACH_M32R), PIPE_NONE } }
2378 /* start-sanitize-m32rx */
2383 { MNEM, ' ', OP (DR), ',', OP (SR), 0 },
2384 { 32, 32, 0xf0f0ffff }, 0x80000100,
2385 & fmt_74_satb_ops[0],
2386 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32RX), PIPE_NONE } }
2388 /* end-sanitize-m32rx */
2389 /* start-sanitize-m32rx */
2394 { MNEM, ' ', OP (DR), ',', OP (SR), 0 },
2395 { 32, 32, 0xf0f0ffff }, 0x80000200,
2396 & fmt_74_satb_ops[0],
2397 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32RX), PIPE_NONE } }
2399 /* end-sanitize-m32rx */
2400 /* start-sanitize-m32rx */
2405 { MNEM, ' ', OP (DR), ',', OP (SR), 0 },
2406 { 32, 32, 0xf0f0ffff }, 0x80000000,
2407 & fmt_75_sat_ops[0],
2408 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32RX), PIPE_NONE } }
2410 /* end-sanitize-m32rx */
2411 /* start-sanitize-m32rx */
2416 { MNEM, ' ', OP (SRC2), 0 },
2417 { 16, 16, 0xfff0 }, 0x370,
2418 & fmt_23_cmpz_ops[0],
2419 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32RX), PIPE_OS } }
2421 /* end-sanitize-m32rx */
2422 /* start-sanitize-m32rx */
2428 { 16, 16, 0xffff }, 0x50e4,
2429 & fmt_76_sadd_ops[0],
2430 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32RX), PIPE_S } }
2432 /* end-sanitize-m32rx */
2433 /* start-sanitize-m32rx */
2434 /* macwu1 $src1,$src2 */
2438 { MNEM, ' ', OP (SRC1), ',', OP (SRC2), 0 },
2439 { 16, 16, 0xf0f0 }, 0x50b0,
2440 & fmt_77_macwu1_ops[0],
2441 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32RX), PIPE_S } }
2443 /* end-sanitize-m32rx */
2444 /* start-sanitize-m32rx */
2445 /* msblo $src1,$src2 */
2449 { MNEM, ' ', OP (SRC1), ',', OP (SRC2), 0 },
2450 { 16, 16, 0xf0f0 }, 0x50d0,
2451 & fmt_41_machi_ops[0],
2452 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32RX), PIPE_S } }
2454 /* end-sanitize-m32rx */
2455 /* start-sanitize-m32rx */
2456 /* mulwu1 $src1,$src2 */
2460 { MNEM, ' ', OP (SRC1), ',', OP (SRC2), 0 },
2461 { 16, 16, 0xf0f0 }, 0x50a0,
2462 & fmt_78_mulwu1_ops[0],
2463 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32RX), PIPE_S } }
2465 /* end-sanitize-m32rx */
2466 /* start-sanitize-m32rx */
2467 /* maclh1 $src1,$src2 */
2471 { MNEM, ' ', OP (SRC1), ',', OP (SRC2), 0 },
2472 { 16, 16, 0xf0f0 }, 0x50c0,
2473 & fmt_77_macwu1_ops[0],
2474 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32RX), PIPE_S } }
2476 /* end-sanitize-m32rx */
2477 /* start-sanitize-m32rx */
2483 { 16, 16, 0xffff }, 0x7401,
2485 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32RX), PIPE_O } }
2487 /* end-sanitize-m32rx */
2488 /* start-sanitize-m32rx */
2494 { 16, 16, 0xffff }, 0x7501,
2496 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32RX), PIPE_O } }
2498 /* end-sanitize-m32rx */
2505 CGEN_INSN_TABLE m32r_cgen_insn_table =
2507 & m32r_cgen_insn_table_entries[0],
2511 m32r_cgen_asm_hash_insn, CGEN_ASM_HASH_SIZE,
2512 m32r_cgen_dis_hash_insn, CGEN_DIS_HASH_SIZE
2515 /* The hash functions are recorded here to help keep assembler code out of
2516 the disassembler and vice versa. */
2519 m32r_cgen_asm_hash_insn (insn)
2522 return CGEN_ASM_HASH (insn);
2526 m32r_cgen_dis_hash_insn (buf, value)
2528 unsigned long value;
2530 return CGEN_DIS_HASH (buf, value);
2533 CGEN_OPCODE_DATA m32r_cgen_opcode_data =
2535 & m32r_cgen_hw_entries[0],
2536 & m32r_cgen_insn_table,
2540 m32r_cgen_init_tables (mach)
2545 /* Main entry point for stuffing values in cgen_fields. */
2548 m32r_cgen_set_operand (opindex, valuep, fields)
2550 const long * valuep;
2551 CGEN_FIELDS * fields;
2555 case M32R_OPERAND_SR :
2556 fields->f_r2 = * valuep;
2558 case M32R_OPERAND_DR :
2559 fields->f_r1 = * valuep;
2561 case M32R_OPERAND_SRC1 :
2562 fields->f_r1 = * valuep;
2564 case M32R_OPERAND_SRC2 :
2565 fields->f_r2 = * valuep;
2567 case M32R_OPERAND_SCR :
2568 fields->f_r2 = * valuep;
2570 case M32R_OPERAND_DCR :
2571 fields->f_r1 = * valuep;
2573 case M32R_OPERAND_SIMM8 :
2574 fields->f_simm8 = * valuep;
2576 case M32R_OPERAND_SIMM16 :
2577 fields->f_simm16 = * valuep;
2579 case M32R_OPERAND_UIMM4 :
2580 fields->f_uimm4 = * valuep;
2582 case M32R_OPERAND_UIMM5 :
2583 fields->f_uimm5 = * valuep;
2585 case M32R_OPERAND_UIMM16 :
2586 fields->f_uimm16 = * valuep;
2588 /* start-sanitize-m32rx */
2589 case M32R_OPERAND_IMM1 :
2590 fields->f_imm1 = * valuep;
2592 /* end-sanitize-m32rx */
2593 /* start-sanitize-m32rx */
2594 case M32R_OPERAND_ACCD :
2595 fields->f_accd = * valuep;
2597 /* end-sanitize-m32rx */
2598 /* start-sanitize-m32rx */
2599 case M32R_OPERAND_ACCS :
2600 fields->f_accs = * valuep;
2602 /* end-sanitize-m32rx */
2603 /* start-sanitize-m32rx */
2604 case M32R_OPERAND_ACC :
2605 fields->f_acc = * valuep;
2607 /* end-sanitize-m32rx */
2608 case M32R_OPERAND_HASH :
2609 fields->f_nil = * valuep;
2611 case M32R_OPERAND_HI16 :
2612 fields->f_hi16 = * valuep;
2614 case M32R_OPERAND_SLO16 :
2615 fields->f_simm16 = * valuep;
2617 case M32R_OPERAND_ULO16 :
2618 fields->f_uimm16 = * valuep;
2620 case M32R_OPERAND_UIMM24 :
2621 fields->f_uimm24 = * valuep;
2623 case M32R_OPERAND_DISP8 :
2624 fields->f_disp8 = * valuep;
2626 case M32R_OPERAND_DISP16 :
2627 fields->f_disp16 = * valuep;
2629 case M32R_OPERAND_DISP24 :
2630 fields->f_disp24 = * valuep;
2634 fprintf (stderr, "Unrecognized field %d while setting operand.\n",
2640 /* Main entry point for getting values from cgen_fields. */
2643 m32r_cgen_get_operand (opindex, fields)
2645 const CGEN_FIELDS * fields;
2651 case M32R_OPERAND_SR :
2652 value = fields->f_r2;
2654 case M32R_OPERAND_DR :
2655 value = fields->f_r1;
2657 case M32R_OPERAND_SRC1 :
2658 value = fields->f_r1;
2660 case M32R_OPERAND_SRC2 :
2661 value = fields->f_r2;
2663 case M32R_OPERAND_SCR :
2664 value = fields->f_r2;
2666 case M32R_OPERAND_DCR :
2667 value = fields->f_r1;
2669 case M32R_OPERAND_SIMM8 :
2670 value = fields->f_simm8;
2672 case M32R_OPERAND_SIMM16 :
2673 value = fields->f_simm16;
2675 case M32R_OPERAND_UIMM4 :
2676 value = fields->f_uimm4;
2678 case M32R_OPERAND_UIMM5 :
2679 value = fields->f_uimm5;
2681 case M32R_OPERAND_UIMM16 :
2682 value = fields->f_uimm16;
2684 /* start-sanitize-m32rx */
2685 case M32R_OPERAND_IMM1 :
2686 value = fields->f_imm1;
2688 /* end-sanitize-m32rx */
2689 /* start-sanitize-m32rx */
2690 case M32R_OPERAND_ACCD :
2691 value = fields->f_accd;
2693 /* end-sanitize-m32rx */
2694 /* start-sanitize-m32rx */
2695 case M32R_OPERAND_ACCS :
2696 value = fields->f_accs;
2698 /* end-sanitize-m32rx */
2699 /* start-sanitize-m32rx */
2700 case M32R_OPERAND_ACC :
2701 value = fields->f_acc;
2703 /* end-sanitize-m32rx */
2704 case M32R_OPERAND_HASH :
2705 value = fields->f_nil;
2707 case M32R_OPERAND_HI16 :
2708 value = fields->f_hi16;
2710 case M32R_OPERAND_SLO16 :
2711 value = fields->f_simm16;
2713 case M32R_OPERAND_ULO16 :
2714 value = fields->f_uimm16;
2716 case M32R_OPERAND_UIMM24 :
2717 value = fields->f_uimm24;
2719 case M32R_OPERAND_DISP8 :
2720 value = fields->f_disp8;
2722 case M32R_OPERAND_DISP16 :
2723 value = fields->f_disp16;
2725 case M32R_OPERAND_DISP24 :
2726 value = fields->f_disp24;
2730 fprintf (stderr, "Unrecognized field %d while getting operand.\n",