1 /* CGEN opcode support for m32r.
3 This file is machine generated with CGEN.
5 Copyright (C) 1996, 1997, 1998 Free Software Foundation, Inc.
7 This file is part of the GNU Binutils and/or GDB, the GNU debugger.
9 This program is free software; you can redistribute it and/or modify
10 it under the terms of the GNU General Public License as published by
11 the Free Software Foundation; either version 2, or (at your option)
14 This program is distributed in the hope that it will be useful,
15 but WITHOUT ANY WARRANTY; without even the implied warranty of
16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 GNU General Public License for more details.
19 You should have received a copy of the GNU General Public License along
20 with this program; if not, write to the Free Software Foundation, Inc.,
21 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
29 #include "libiberty.h"
35 static const CGEN_ATTR_ENTRY MACH_attr[] =
37 { "m32r", MACH_M32R },
38 /* start-sanitize-m32rx */
39 { "m32rx", MACH_M32RX },
40 /* end-sanitize-m32rx */
45 /* start-sanitize-m32rx */
46 static const CGEN_ATTR_ENTRY PIPE_attr[] =
48 { "NONE", PIPE_NONE },
55 /* end-sanitize-m32rx */
56 const CGEN_ATTR_TABLE m32r_cgen_operand_attr_table[] =
62 { "PCREL-ADDR", NULL },
70 const CGEN_ATTR_TABLE m32r_cgen_insn_attr_table[] =
72 { "MACH", & MACH_attr[0] },
73 /* start-sanitize-m32rx */
74 { "PIPE", & PIPE_attr[0] },
75 /* end-sanitize-m32rx */
78 { "FILL-SLOT", NULL },
81 { "RELAXABLE", NULL },
82 { "UNCOND-CTI", NULL },
86 CGEN_KEYWORD_ENTRY m32r_cgen_opval_h_gr_entries[] =
109 CGEN_KEYWORD m32r_cgen_opval_h_gr =
111 & m32r_cgen_opval_h_gr_entries[0],
115 CGEN_KEYWORD_ENTRY m32r_cgen_opval_h_cr_entries[] =
131 CGEN_KEYWORD m32r_cgen_opval_h_cr =
133 & m32r_cgen_opval_h_cr_entries[0],
137 /* start-sanitize-m32rx */
138 CGEN_KEYWORD_ENTRY m32r_cgen_opval_h_accums_entries[] =
144 CGEN_KEYWORD m32r_cgen_opval_h_accums =
146 & m32r_cgen_opval_h_accums_entries[0],
150 /* end-sanitize-m32rx */
152 static CGEN_HW_ENTRY m32r_cgen_hw_entries[] =
154 { "h-pc", CGEN_ASM_KEYWORD, (PTR) 0 },
155 { "h-memory", CGEN_ASM_KEYWORD, (PTR) 0 },
156 { "h-sint", CGEN_ASM_KEYWORD, (PTR) 0 },
157 { "h-uint", CGEN_ASM_KEYWORD, (PTR) 0 },
158 { "h-addr", CGEN_ASM_KEYWORD, (PTR) 0 },
159 { "h-iaddr", CGEN_ASM_KEYWORD, (PTR) 0 },
160 { "h-hi16", CGEN_ASM_KEYWORD, (PTR) 0 },
161 { "h-slo16", CGEN_ASM_KEYWORD, (PTR) 0 },
162 { "h-ulo16", CGEN_ASM_KEYWORD, (PTR) 0 },
163 { "h-gr", CGEN_ASM_KEYWORD, (PTR) & m32r_cgen_opval_h_gr },
164 { "h-cr", CGEN_ASM_KEYWORD, (PTR) & m32r_cgen_opval_h_cr },
165 { "h-accum", CGEN_ASM_KEYWORD, (PTR) 0 },
166 /* start-sanitize-m32rx */
167 { "h-accums", CGEN_ASM_KEYWORD, (PTR) & m32r_cgen_opval_h_accums },
168 /* end-sanitize-m32rx */
169 /* start-sanitize-m32rx */
170 { "h-abort", CGEN_ASM_KEYWORD, (PTR) 0 },
171 /* end-sanitize-m32rx */
172 { "h-cond", CGEN_ASM_KEYWORD, (PTR) 0 },
173 { "h-sm", CGEN_ASM_KEYWORD, (PTR) 0 },
174 { "h-bsm", CGEN_ASM_KEYWORD, (PTR) 0 },
175 { "h-ie", CGEN_ASM_KEYWORD, (PTR) 0 },
176 { "h-bie", CGEN_ASM_KEYWORD, (PTR) 0 },
177 { "h-bcond", CGEN_ASM_KEYWORD, (PTR) 0 },
178 { "h-bpc", CGEN_ASM_KEYWORD, (PTR) 0 },
182 const CGEN_OPERAND m32r_cgen_operand_table[MAX_OPERANDS] =
184 /* pc: program counter */
185 { "pc", 0, 0, { 0, 0|(1<<CGEN_OPERAND_FAKE)|(1<<CGEN_OPERAND_PC), { 0 } } },
186 /* sr: source register */
187 { "sr", 12, 4, { 0, 0|(1<<CGEN_OPERAND_UNSIGNED), { 0 } } },
188 /* dr: destination register */
189 { "dr", 4, 4, { 0, 0|(1<<CGEN_OPERAND_UNSIGNED), { 0 } } },
190 /* src1: source register 1 */
191 { "src1", 4, 4, { 0, 0|(1<<CGEN_OPERAND_UNSIGNED), { 0 } } },
192 /* src2: source register 2 */
193 { "src2", 12, 4, { 0, 0|(1<<CGEN_OPERAND_UNSIGNED), { 0 } } },
194 /* scr: source control register */
195 { "scr", 12, 4, { 0, 0|(1<<CGEN_OPERAND_UNSIGNED), { 0 } } },
196 /* dcr: destination control register */
197 { "dcr", 4, 4, { 0, 0|(1<<CGEN_OPERAND_UNSIGNED), { 0 } } },
198 /* simm8: 8 bit signed immediate */
199 { "simm8", 8, 8, { 0, 0, { 0 } } },
200 /* simm16: 16 bit signed immediate */
201 { "simm16", 16, 16, { 0, 0, { 0 } } },
202 /* uimm4: 4 bit trap number */
203 { "uimm4", 12, 4, { 0, 0|(1<<CGEN_OPERAND_UNSIGNED), { 0 } } },
204 /* uimm5: 5 bit shift count */
205 { "uimm5", 11, 5, { 0, 0|(1<<CGEN_OPERAND_UNSIGNED), { 0 } } },
206 /* uimm16: 16 bit unsigned immediate */
207 { "uimm16", 16, 16, { 0, 0|(1<<CGEN_OPERAND_UNSIGNED), { 0 } } },
208 /* start-sanitize-m32rx */
209 /* accs: accumulator register */
210 { "accs", 12, 2, { 0, 0|(1<<CGEN_OPERAND_UNSIGNED), { 0 } } },
211 /* end-sanitize-m32rx */
212 /* start-sanitize-m32rx */
213 /* acc: accumulator reg (d) */
214 { "acc", 8, 1, { 0, 0|(1<<CGEN_OPERAND_UNSIGNED), { 0 } } },
215 /* end-sanitize-m32rx */
216 /* hi16: high 16 bit immediate, sign optional */
217 { "hi16", 16, 16, { 0, 0|(1<<CGEN_OPERAND_SIGN_OPT)|(1<<CGEN_OPERAND_UNSIGNED), { 0 } } },
218 /* slo16: 16 bit signed immediate, for low() */
219 { "slo16", 16, 16, { 0, 0, { 0 } } },
220 /* ulo16: 16 bit unsigned immediate, for low() */
221 { "ulo16", 16, 16, { 0, 0|(1<<CGEN_OPERAND_UNSIGNED), { 0 } } },
222 /* uimm24: 24 bit address */
223 { "uimm24", 8, 24, { 0, 0|(1<<CGEN_OPERAND_RELOC)|(1<<CGEN_OPERAND_ABS_ADDR)|(1<<CGEN_OPERAND_UNSIGNED), { 0 } } },
224 /* disp8: 8 bit displacement */
225 { "disp8", 8, 8, { 0, 0|(1<<CGEN_OPERAND_RELAX)|(1<<CGEN_OPERAND_RELOC)|(1<<CGEN_OPERAND_PCREL_ADDR), { 0 } } },
226 /* disp16: 16 bit displacement */
227 { "disp16", 16, 16, { 0, 0|(1<<CGEN_OPERAND_RELOC)|(1<<CGEN_OPERAND_PCREL_ADDR), { 0 } } },
228 /* disp24: 24 bit displacement */
229 { "disp24", 8, 24, { 0, 0|(1<<CGEN_OPERAND_RELAX)|(1<<CGEN_OPERAND_RELOC)|(1<<CGEN_OPERAND_PCREL_ADDR), { 0 } } },
230 /* condbit: condition bit */
231 { "condbit", 0, 0, { 0, 0|(1<<CGEN_OPERAND_FAKE), { 0 } } },
232 /* accum: accumulator */
233 { "accum", 0, 0, { 0, 0|(1<<CGEN_OPERAND_FAKE), { 0 } } },
234 /* start-sanitize-m32rx */
235 /* abort-parallel-execution: abort parallel execution */
236 { "abort-parallel-execution", 0, 0, { 0, 0|(1<<CGEN_OPERAND_FAKE), { 0 } } },
237 /* end-sanitize-m32rx */
240 #define OP 1 /* syntax value for mnemonic */
242 static const CGEN_SYNTAX syntax_table[] =
245 /* 0 */ { OP, ' ', 130, ',', 129, 0 },
246 /* <op> $dr,$sr,#$slo16 */
247 /* 1 */ { OP, ' ', 130, ',', 129, ',', '#', 143, 0 },
248 /* <op> $dr,$sr,$slo16 */
249 /* 2 */ { OP, ' ', 130, ',', 129, ',', 143, 0 },
250 /* <op> $dr,$sr,#$uimm16 */
251 /* 3 */ { OP, ' ', 130, ',', 129, ',', '#', 139, 0 },
252 /* <op> $dr,$sr,$uimm16 */
253 /* 4 */ { OP, ' ', 130, ',', 129, ',', 139, 0 },
254 /* <op> $dr,$sr,#$ulo16 */
255 /* 5 */ { OP, ' ', 130, ',', 129, ',', '#', 144, 0 },
256 /* <op> $dr,$sr,$ulo16 */
257 /* 6 */ { OP, ' ', 130, ',', 129, ',', 144, 0 },
258 /* <op> $dr,#$simm8 */
259 /* 7 */ { OP, ' ', 130, ',', '#', 135, 0 },
260 /* <op> $dr,$simm8 */
261 /* 8 */ { OP, ' ', 130, ',', 135, 0 },
262 /* <op> $dr,$sr,#$simm16 */
263 /* 9 */ { OP, ' ', 130, ',', 129, ',', '#', 136, 0 },
264 /* <op> $dr,$sr,$simm16 */
265 /* 10 */ { OP, ' ', 130, ',', 129, ',', 136, 0 },
267 /* 11 */ { OP, ' ', 146, 0 },
269 /* 12 */ { OP, ' ', 148, 0 },
270 /* <op> $src1,$src2,$disp16 */
271 /* 13 */ { OP, ' ', 131, ',', 132, ',', 147, 0 },
272 /* <op> $src2,$disp16 */
273 /* 14 */ { OP, ' ', 132, ',', 147, 0 },
274 /* <op> $src1,$src2 */
275 /* 15 */ { OP, ' ', 131, ',', 132, 0 },
276 /* <op> $src2,#$simm16 */
277 /* 16 */ { OP, ' ', 132, ',', '#', 136, 0 },
278 /* <op> $src2,$simm16 */
279 /* 17 */ { OP, ' ', 132, ',', 136, 0 },
280 /* <op> $src2,#$uimm16 */
281 /* 18 */ { OP, ' ', 132, ',', '#', 139, 0 },
282 /* <op> $src2,$uimm16 */
283 /* 19 */ { OP, ' ', 132, ',', 139, 0 },
285 /* 20 */ { OP, ' ', 132, 0 },
287 /* 21 */ { OP, ' ', 129, 0 },
289 /* 22 */ { OP, ' ', 130, ',', '@', 129, 0 },
290 /* <op> $dr,@($sr) */
291 /* 23 */ { OP, ' ', 130, ',', '@', '(', 129, ')', 0 },
292 /* <op> $dr,@($slo16,$sr) */
293 /* 24 */ { OP, ' ', 130, ',', '@', '(', 143, ',', 129, ')', 0 },
294 /* <op> $dr,@($sr,$slo16) */
295 /* 25 */ { OP, ' ', 130, ',', '@', '(', 129, ',', 143, ')', 0 },
297 /* 26 */ { OP, ' ', 130, ',', '@', 129, '+', 0 },
298 /* <op> $dr,#$uimm24 */
299 /* 27 */ { OP, ' ', 130, ',', '#', 145, 0 },
300 /* <op> $dr,$uimm24 */
301 /* 28 */ { OP, ' ', 130, ',', 145, 0 },
302 /* <op> $dr,$slo16 */
303 /* 29 */ { OP, ' ', 130, ',', 143, 0 },
304 /* <op> $src1,$src2,$acc */
305 /* 30 */ { OP, ' ', 131, ',', 132, ',', 141, 0 },
307 /* 31 */ { OP, ' ', 130, 0 },
309 /* 32 */ { OP, ' ', 130, ',', 140, 0 },
311 /* 33 */ { OP, ' ', 130, ',', 133, 0 },
313 /* 34 */ { OP, ' ', 131, 0 },
314 /* <op> $src1,$accs */
315 /* 35 */ { OP, ' ', 131, ',', 140, 0 },
317 /* 36 */ { OP, ' ', 129, ',', 134, 0 },
321 /* 38 */ { OP, ' ', 140, 0 },
322 /* <op> $dr,#$hi16 */
323 /* 39 */ { OP, ' ', 130, ',', '#', 142, 0 },
325 /* 40 */ { OP, ' ', 130, ',', 142, 0 },
326 /* <op> $dr,#$uimm5 */
327 /* 41 */ { OP, ' ', 130, ',', '#', 138, 0 },
328 /* <op> $dr,$uimm5 */
329 /* 42 */ { OP, ' ', 130, ',', 138, 0 },
330 /* <op> $src1,@$src2 */
331 /* 43 */ { OP, ' ', 131, ',', '@', 132, 0 },
332 /* <op> $src1,@($src2) */
333 /* 44 */ { OP, ' ', 131, ',', '@', '(', 132, ')', 0 },
334 /* <op> $src1,@($slo16,$src2) */
335 /* 45 */ { OP, ' ', 131, ',', '@', '(', 143, ',', 132, ')', 0 },
336 /* <op> $src1,@($src2,$slo16) */
337 /* 46 */ { OP, ' ', 131, ',', '@', '(', 132, ',', 143, ')', 0 },
338 /* <op> $src1,@+$src2 */
339 /* 47 */ { OP, ' ', 131, ',', '@', '+', 132, 0 },
340 /* <op> $src1,@-$src2 */
341 /* 48 */ { OP, ' ', 131, ',', '@', '-', 132, 0 },
343 /* 49 */ { OP, ' ', '#', 137, 0 },
345 /* 50 */ { OP, ' ', 137, 0 },
347 /* 51 */ { OP, ' ', 130, ',', 132, 0 },
352 static const CGEN_FORMAT format_table[] =
354 /* f-op1.number.f-r1.dr.f-op2.number.f-r2.sr. */
355 /* 0 */ { 16, 16, 0xf0f0 },
356 /* f-op1.number.f-r1.dr.f-op2.number.f-r2.sr.f-simm16.slo16. */
357 /* 1 */ { 32, 32, 0xf0f00000 },
358 /* f-op1.number.f-r1.dr.f-op2.number.f-r2.sr.f-uimm16.uimm16. */
359 /* 2 */ { 32, 32, 0xf0f00000 },
360 /* f-op1.number.f-r1.dr.f-op2.number.f-r2.sr.f-uimm16.ulo16. */
361 /* 3 */ { 32, 32, 0xf0f00000 },
362 /* f-op1.number.f-r1.dr.f-simm8.simm8. */
363 /* 4 */ { 16, 16, 0xf000 },
364 /* f-op1.number.f-r1.dr.f-op2.number.f-r2.sr.f-simm16.simm16. */
365 /* 5 */ { 32, 32, 0xf0f00000 },
366 /* f-op1.number.f-r1.number.f-disp8.disp8. */
367 /* 6 */ { 16, 16, 0xff00 },
368 /* f-op1.number.f-r1.number.f-disp24.disp24. */
369 /* 7 */ { 32, 32, 0xff000000 },
370 /* f-op1.number.f-r1.src1.f-op2.number.f-r2.src2.f-disp16.disp16. */
371 /* 8 */ { 32, 32, 0xf0f00000 },
372 /* f-op1.number.f-r1.number.f-op2.number.f-r2.src2.f-disp16.disp16. */
373 /* 9 */ { 32, 32, 0xfff00000 },
374 /* f-op1.number.f-r1.src1.f-op2.number.f-r2.src2. */
375 /* 10 */ { 16, 16, 0xf0f0 },
376 /* f-op1.number.f-r1.number.f-op2.number.f-r2.src2.f-simm16.simm16. */
377 /* 11 */ { 32, 32, 0xfff00000 },
378 /* f-op1.number.f-r1.number.f-op2.number.f-r2.src2.f-uimm16.uimm16. */
379 /* 12 */ { 32, 32, 0xfff00000 },
380 /* f-op1.number.f-r1.number.f-op2.number.f-r2.src2. */
381 /* 13 */ { 16, 16, 0xfff0 },
382 /* f-op1.number.f-r1.dr.f-op2.number.f-r2.sr.f-simm16.number. */
383 /* 14 */ { 32, 32, 0xf0f0ffff },
384 /* f-op1.number.f-r1.number.f-op2.number.f-r2.sr. */
385 /* 15 */ { 16, 16, 0xfff0 },
386 /* f-op1.number.f-r1.dr.f-uimm24.uimm24. */
387 /* 16 */ { 32, 32, 0xf0000000 },
388 /* f-op1.number.f-r1.dr.f-op2.number.f-r2.number.f-simm16.slo16. */
389 /* 17 */ { 32, 32, 0xf0ff0000 },
390 /* f-op1.number.f-r1.src1.f-acc.acc.f-op23.number.f-r2.src2. */
391 /* 18 */ { 16, 16, 0xf070 },
392 /* f-op1.number.f-r1.dr.f-op2.number.f-r2.number. */
393 /* 19 */ { 16, 16, 0xf0ff },
394 /* f-op1.number.f-r1.dr.f-op2.number.f-accs.accs.f-op3.number. */
395 /* 20 */ { 16, 16, 0xf0f3 },
396 /* f-op1.number.f-r1.dr.f-op2.number.f-r2.scr. */
397 /* 21 */ { 16, 16, 0xf0f0 },
398 /* f-op1.number.f-r1.src1.f-op2.number.f-r2.number. */
399 /* 22 */ { 16, 16, 0xf0ff },
400 /* f-op1.number.f-r1.src1.f-op2.number.f-accs.accs.f-op3.number. */
401 /* 23 */ { 16, 16, 0xf0f3 },
402 /* f-op1.number.f-r1.dcr.f-op2.number.f-r2.sr. */
403 /* 24 */ { 16, 16, 0xf0f0 },
404 /* f-op1.number.f-r1.number.f-op2.number.f-r2.number. */
405 /* 25 */ { 16, 16, 0xffff },
406 /* f-op1.number.f-r1.number.f-op2.number.f-accs.accs.f-op3.number. */
407 /* 26 */ { 16, 16, 0xfff3 },
408 /* f-op1.number.f-r1.dr.f-op2.number.f-r2.number.f-hi16.hi16. */
409 /* 27 */ { 32, 32, 0xf0ff0000 },
410 /* f-op1.number.f-r1.dr.f-shift-op2.number.f-uimm5.uimm5. */
411 /* 28 */ { 16, 16, 0xf0e0 },
412 /* f-op1.number.f-r1.src1.f-op2.number.f-r2.src2.f-simm16.slo16. */
413 /* 29 */ { 32, 32, 0xf0f00000 },
414 /* f-op1.number.f-r1.number.f-op2.number.f-uimm4.uimm4. */
415 /* 30 */ { 16, 16, 0xfff0 },
416 /* f-op1.number.f-r1.dr.f-op2.number.f-r2.src2.f-uimm16.number. */
417 /* 31 */ { 32, 32, 0xf0f0ffff },
420 #define A(a) (1 << CGEN_CAT3 (CGEN_INSN,_,a))
421 #define SYN(n) (& syntax_table[n])
422 #define FMT(n) (& format_table[n])
424 const CGEN_INSN m32r_cgen_insn_table_entries[MAX_INSNS] =
426 /* null first entry, end of all hash chains */
431 "add", "add", SYN (0), FMT (0), 0xa0,
432 { 2, 0|A(PARALLEL), { (1<<MACH_M32R), PIPE_OS } }
434 /* add3 $dr,$sr,#$slo16 */
437 "add3", "add3", SYN (1), FMT (1), 0x80a00000,
438 { 2, 0, { (1<<MACH_M32R), PIPE_NONE } }
440 /* add3 $dr,$sr,$slo16 */
443 "add3.a", "add3", SYN (2), FMT (1), 0x80a00000,
444 { 2, 0|A(ALIAS), { (1<<MACH_M32R), PIPE_NONE } }
449 "and", "and", SYN (0), FMT (0), 0xc0,
450 { 2, 0|A(PARALLEL), { (1<<MACH_M32R), PIPE_OS } }
452 /* and3 $dr,$sr,#$uimm16 */
455 "and3", "and3", SYN (3), FMT (2), 0x80c00000,
456 { 2, 0, { (1<<MACH_M32R), PIPE_NONE } }
458 /* and3 $dr,$sr,$uimm16 */
461 "and3.a", "and3", SYN (4), FMT (2), 0x80c00000,
462 { 2, 0|A(ALIAS), { (1<<MACH_M32R), PIPE_NONE } }
467 "or", "or", SYN (0), FMT (0), 0xe0,
468 { 2, 0|A(PARALLEL), { (1<<MACH_M32R), PIPE_OS } }
470 /* or3 $dr,$sr,#$ulo16 */
473 "or3", "or3", SYN (5), FMT (3), 0x80e00000,
474 { 2, 0, { (1<<MACH_M32R), PIPE_NONE } }
476 /* or3 $dr,$sr,$ulo16 */
479 "or3.a", "or3", SYN (6), FMT (3), 0x80e00000,
480 { 2, 0|A(ALIAS), { (1<<MACH_M32R), PIPE_NONE } }
485 "xor", "xor", SYN (0), FMT (0), 0xd0,
486 { 2, 0|A(PARALLEL), { (1<<MACH_M32R), PIPE_OS } }
488 /* xor3 $dr,$sr,#$uimm16 */
491 "xor3", "xor3", SYN (3), FMT (2), 0x80d00000,
492 { 2, 0, { (1<<MACH_M32R), PIPE_NONE } }
494 /* xor3 $dr,$sr,$uimm16 */
497 "xor3.a", "xor3", SYN (4), FMT (2), 0x80d00000,
498 { 2, 0|A(ALIAS), { (1<<MACH_M32R), PIPE_NONE } }
500 /* addi $dr,#$simm8 */
503 "addi", "addi", SYN (7), FMT (4), 0x4000,
504 { 2, 0, { (1<<MACH_M32R), PIPE_OS } }
506 /* addi $dr,$simm8 */
509 "addi.a", "addi", SYN (8), FMT (4), 0x4000,
510 { 2, 0|A(ALIAS), { (1<<MACH_M32R), PIPE_OS } }
515 "addv", "addv", SYN (0), FMT (0), 0x80,
516 { 2, 0, { (1<<MACH_M32R), PIPE_OS } }
518 /* addv3 $dr,$sr,#$simm16 */
521 "addv3", "addv3", SYN (9), FMT (5), 0x80800000,
522 { 2, 0, { (1<<MACH_M32R), PIPE_NONE } }
524 /* addv3 $dr,$sr,$simm16 */
527 "addv3.a", "addv3", SYN (10), FMT (5), 0x80800000,
528 { 2, 0|A(ALIAS), { (1<<MACH_M32R), PIPE_NONE } }
533 "addx", "addx", SYN (0), FMT (0), 0x90,
534 { 2, 0, { (1<<MACH_M32R), PIPE_OS } }
539 "bc8", "bc", SYN (11), FMT (6), 0x7c00,
540 { 2, 0|A(RELAXABLE)|A(COND_CTI), { (1<<MACH_M32R), PIPE_O } }
545 "bc8.s", "bc.s", SYN (11), FMT (6), 0x7c00,
546 { 2, 0|A(ALIAS)|A(COND_CTI), { (1<<MACH_M32R), PIPE_O } }
551 "bc24", "bc", SYN (12), FMT (7), 0xfc000000,
552 { 2, 0|A(RELAX)|A(COND_CTI), { (1<<MACH_M32R), PIPE_NONE } }
557 "bc24.l", "bc.l", SYN (12), FMT (7), 0xfc000000,
558 { 2, 0|A(ALIAS)|A(COND_CTI), { (1<<MACH_M32R), PIPE_NONE } }
560 /* beq $src1,$src2,$disp16 */
563 "beq", "beq", SYN (13), FMT (8), 0xb0000000,
564 { 2, 0|A(COND_CTI), { (1<<MACH_M32R), PIPE_NONE } }
566 /* beqz $src2,$disp16 */
569 "beqz", "beqz", SYN (14), FMT (9), 0xb0800000,
570 { 2, 0|A(COND_CTI), { (1<<MACH_M32R), PIPE_NONE } }
572 /* bgez $src2,$disp16 */
575 "bgez", "bgez", SYN (14), FMT (9), 0xb0b00000,
576 { 2, 0|A(COND_CTI), { (1<<MACH_M32R), PIPE_NONE } }
578 /* bgtz $src2,$disp16 */
581 "bgtz", "bgtz", SYN (14), FMT (9), 0xb0d00000,
582 { 2, 0|A(COND_CTI), { (1<<MACH_M32R), PIPE_NONE } }
584 /* blez $src2,$disp16 */
587 "blez", "blez", SYN (14), FMT (9), 0xb0c00000,
588 { 2, 0|A(COND_CTI), { (1<<MACH_M32R), PIPE_NONE } }
590 /* bltz $src2,$disp16 */
593 "bltz", "bltz", SYN (14), FMT (9), 0xb0a00000,
594 { 2, 0|A(COND_CTI), { (1<<MACH_M32R), PIPE_NONE } }
596 /* bnez $src2,$disp16 */
599 "bnez", "bnez", SYN (14), FMT (9), 0xb0900000,
600 { 2, 0|A(COND_CTI), { (1<<MACH_M32R), PIPE_NONE } }
605 "bl8", "bl", SYN (11), FMT (6), 0x7e00,
606 { 2, 0|A(FILL_SLOT)|A(RELAXABLE)|A(UNCOND_CTI), { (1<<MACH_M32R), PIPE_O } }
611 "bl8.s", "bl.s", SYN (11), FMT (6), 0x7e00,
612 { 2, 0|A(FILL_SLOT)|A(ALIAS)|A(UNCOND_CTI), { (1<<MACH_M32R), PIPE_O } }
617 "bl24", "bl", SYN (12), FMT (7), 0xfe000000,
618 { 2, 0|A(RELAX)|A(UNCOND_CTI), { (1<<MACH_M32R), PIPE_NONE } }
623 "bl24.l", "bl.l", SYN (12), FMT (7), 0xfe000000,
624 { 2, 0|A(ALIAS)|A(UNCOND_CTI), { (1<<MACH_M32R), PIPE_NONE } }
626 /* start-sanitize-m32rx */
630 "bcl8", "bcl", SYN (11), FMT (6), 0x7800,
631 { 2, 0|A(RELAXABLE)|A(COND_CTI), { (1<<MACH_M32RX), PIPE_O } }
633 /* end-sanitize-m32rx */
634 /* start-sanitize-m32rx */
638 "bcl8.s", "bcl.s", SYN (11), FMT (6), 0x7800,
639 { 2, 0|A(ALIAS)|A(COND_CTI), { (1<<MACH_M32RX), PIPE_O } }
641 /* end-sanitize-m32rx */
642 /* start-sanitize-m32rx */
646 "bcl24", "bcl", SYN (12), FMT (7), 0xf8000000,
647 { 2, 0|A(RELAX)|A(COND_CTI), { (1<<MACH_M32RX), PIPE_NONE } }
649 /* end-sanitize-m32rx */
650 /* start-sanitize-m32rx */
654 "bcl24.l", "bcl.l", SYN (12), FMT (7), 0xf8000000,
655 { 2, 0|A(ALIAS)|A(COND_CTI), { (1<<MACH_M32RX), PIPE_NONE } }
657 /* end-sanitize-m32rx */
661 "bnc8", "bnc", SYN (11), FMT (6), 0x7d00,
662 { 2, 0|A(RELAXABLE)|A(COND_CTI), { (1<<MACH_M32R), PIPE_O } }
667 "bnc8.s", "bnc.s", SYN (11), FMT (6), 0x7d00,
668 { 2, 0|A(ALIAS)|A(COND_CTI), { (1<<MACH_M32R), PIPE_O } }
673 "bnc24", "bnc", SYN (12), FMT (7), 0xfd000000,
674 { 2, 0|A(RELAX)|A(COND_CTI), { (1<<MACH_M32R), PIPE_NONE } }
679 "bnc24.l", "bnc.l", SYN (12), FMT (7), 0xfd000000,
680 { 2, 0|A(ALIAS)|A(COND_CTI), { (1<<MACH_M32R), PIPE_NONE } }
682 /* bne $src1,$src2,$disp16 */
685 "bne", "bne", SYN (13), FMT (8), 0xb0100000,
686 { 2, 0|A(COND_CTI), { (1<<MACH_M32R), PIPE_NONE } }
691 "bra8", "bra", SYN (11), FMT (6), 0x7f00,
692 { 2, 0|A(FILL_SLOT)|A(RELAXABLE)|A(UNCOND_CTI), { (1<<MACH_M32R), PIPE_O } }
697 "bra8.s", "bra.s", SYN (11), FMT (6), 0x7f00,
698 { 2, 0|A(ALIAS)|A(UNCOND_CTI), { (1<<MACH_M32R), PIPE_O } }
703 "bra24", "bra", SYN (12), FMT (7), 0xff000000,
704 { 2, 0|A(RELAX)|A(UNCOND_CTI), { (1<<MACH_M32R), PIPE_NONE } }
709 "bra24.l", "bra.l", SYN (12), FMT (7), 0xff000000,
710 { 2, 0|A(ALIAS)|A(UNCOND_CTI), { (1<<MACH_M32R), PIPE_NONE } }
712 /* start-sanitize-m32rx */
716 "bncl8", "bncl", SYN (11), FMT (6), 0x7900,
717 { 2, 0|A(RELAXABLE)|A(COND_CTI), { (1<<MACH_M32RX), PIPE_O } }
719 /* end-sanitize-m32rx */
720 /* start-sanitize-m32rx */
724 "bncl8.s", "bncl.s", SYN (11), FMT (6), 0x7900,
725 { 2, 0|A(ALIAS)|A(COND_CTI), { (1<<MACH_M32RX), PIPE_NONE } }
727 /* end-sanitize-m32rx */
728 /* start-sanitize-m32rx */
732 "bncl24", "bncl", SYN (12), FMT (7), 0xf9000000,
733 { 2, 0|A(RELAX)|A(COND_CTI), { (1<<MACH_M32RX), PIPE_NONE } }
735 /* end-sanitize-m32rx */
736 /* start-sanitize-m32rx */
740 "bncl24.l", "bncl.l", SYN (12), FMT (7), 0xf9000000,
741 { 2, 0|A(ALIAS)|A(COND_CTI), { (1<<MACH_M32RX), PIPE_NONE } }
743 /* end-sanitize-m32rx */
744 /* cmp $src1,$src2 */
747 "cmp", "cmp", SYN (15), FMT (10), 0x40,
748 { 2, 0, { (1<<MACH_M32R), PIPE_OS } }
750 /* cmpi $src2,#$simm16 */
753 "cmpi", "cmpi", SYN (16), FMT (11), 0x80400000,
754 { 2, 0, { (1<<MACH_M32R), PIPE_NONE } }
756 /* cmpi $src2,$simm16 */
759 "cmpi.a", "cmpi", SYN (17), FMT (11), 0x80400000,
760 { 2, 0|A(ALIAS), { (1<<MACH_M32R), PIPE_NONE } }
762 /* cmpu $src1,$src2 */
765 "cmpu", "cmpu", SYN (15), FMT (10), 0x50,
766 { 2, 0, { (1<<MACH_M32R), PIPE_OS } }
768 /* cmpui $src2,#$uimm16 */
771 "cmpui", "cmpui", SYN (18), FMT (12), 0x80500000,
772 { 2, 0, { (1<<MACH_M32R), PIPE_NONE } }
774 /* cmpui $src2,$uimm16 */
777 "cmpui.a", "cmpui", SYN (19), FMT (12), 0x80500000,
778 { 2, 0|A(ALIAS), { (1<<MACH_M32R), PIPE_NONE } }
780 /* start-sanitize-m32rx */
781 /* cmpeq $src1,$src2 */
784 "cmpeq", "cmpeq", SYN (15), FMT (10), 0x60,
785 { 2, 0, { (1<<MACH_M32RX), PIPE_OS } }
787 /* end-sanitize-m32rx */
788 /* start-sanitize-m32rx */
792 "cmpz", "cmpz", SYN (20), FMT (13), 0x70,
793 { 2, 0, { (1<<MACH_M32RX), PIPE_OS } }
795 /* end-sanitize-m32rx */
799 "div", "div", SYN (0), FMT (14), 0x90000000,
800 { 2, 0, { (1<<MACH_M32R), PIPE_NONE } }
805 "divu", "divu", SYN (0), FMT (14), 0x90100000,
806 { 2, 0, { (1<<MACH_M32R), PIPE_NONE } }
811 "rem", "rem", SYN (0), FMT (14), 0x90200000,
812 { 2, 0, { (1<<MACH_M32R), PIPE_NONE } }
817 "remu", "remu", SYN (0), FMT (14), 0x90300000,
818 { 2, 0, { (1<<MACH_M32R), PIPE_NONE } }
820 /* start-sanitize-m32rx */
824 "jc", "jc", SYN (21), FMT (15), 0x1cc0,
825 { 2, 0|A(COND_CTI), { (1<<MACH_M32RX), PIPE_O } }
827 /* end-sanitize-m32rx */
828 /* start-sanitize-m32rx */
832 "jnc", "jnc", SYN (21), FMT (15), 0x1dc0,
833 { 2, 0|A(COND_CTI), { (1<<MACH_M32RX), PIPE_O } }
835 /* end-sanitize-m32rx */
839 "jl", "jl", SYN (21), FMT (15), 0x1ec0,
840 { 2, 0|A(FILL_SLOT)|A(UNCOND_CTI), { (1<<MACH_M32R), PIPE_O } }
845 "jmp", "jmp", SYN (21), FMT (15), 0x1fc0,
846 { 2, 0|A(UNCOND_CTI), { (1<<MACH_M32R), PIPE_O } }
851 "ld", "ld", SYN (22), FMT (0), 0x20c0,
852 { 2, 0, { (1<<MACH_M32R), PIPE_O } }
857 "ld-2", "ld", SYN (23), FMT (0), 0x20c0,
858 { 2, 0|A(ALIAS), { (1<<MACH_M32R), PIPE_O } }
860 /* ld $dr,@($slo16,$sr) */
863 "ld-d", "ld", SYN (24), FMT (1), 0xa0c00000,
864 { 2, 0, { (1<<MACH_M32R), PIPE_NONE } }
866 /* ld $dr,@($sr,$slo16) */
869 "ld-d2", "ld", SYN (25), FMT (1), 0xa0c00000,
870 { 2, 0|A(ALIAS), { (1<<MACH_M32R), PIPE_NONE } }
875 "ldb", "ldb", SYN (22), FMT (0), 0x2080,
876 { 2, 0, { (1<<MACH_M32R), PIPE_O } }
881 "ldb-2", "ldb", SYN (23), FMT (0), 0x2080,
882 { 2, 0|A(ALIAS), { (1<<MACH_M32R), PIPE_O } }
884 /* ldb $dr,@($slo16,$sr) */
887 "ldb-d", "ldb", SYN (24), FMT (1), 0xa0800000,
888 { 2, 0, { (1<<MACH_M32R), PIPE_NONE } }
890 /* ldb $dr,@($sr,$slo16) */
893 "ldb-d2", "ldb", SYN (25), FMT (1), 0xa0800000,
894 { 2, 0|A(ALIAS), { (1<<MACH_M32R), PIPE_NONE } }
899 "ldh", "ldh", SYN (22), FMT (0), 0x20a0,
900 { 2, 0, { (1<<MACH_M32R), PIPE_O } }
905 "ldh-2", "ldh", SYN (23), FMT (0), 0x20a0,
906 { 2, 0|A(ALIAS), { (1<<MACH_M32R), PIPE_O } }
908 /* ldh $dr,@($slo16,$sr) */
911 "ldh-d", "ldh", SYN (24), FMT (1), 0xa0a00000,
912 { 2, 0, { (1<<MACH_M32R), PIPE_NONE } }
914 /* ldh $dr,@($sr,$slo16) */
917 "ldh-d2", "ldh", SYN (25), FMT (1), 0xa0a00000,
918 { 2, 0|A(ALIAS), { (1<<MACH_M32R), PIPE_NONE } }
923 "ldub", "ldub", SYN (22), FMT (0), 0x2090,
924 { 2, 0, { (1<<MACH_M32R), PIPE_O } }
926 /* ldub $dr,@($sr) */
929 "ldub-2", "ldub", SYN (23), FMT (0), 0x2090,
930 { 2, 0|A(ALIAS), { (1<<MACH_M32R), PIPE_O } }
932 /* ldub $dr,@($slo16,$sr) */
935 "ldub-d", "ldub", SYN (24), FMT (1), 0xa0900000,
936 { 2, 0, { (1<<MACH_M32R), PIPE_NONE } }
938 /* ldub $dr,@($sr,$slo16) */
941 "ldub-d2", "ldub", SYN (25), FMT (1), 0xa0900000,
942 { 2, 0|A(ALIAS), { (1<<MACH_M32R), PIPE_NONE } }
947 "lduh", "lduh", SYN (22), FMT (0), 0x20b0,
948 { 2, 0, { (1<<MACH_M32R), PIPE_O } }
950 /* lduh $dr,@($sr) */
953 "lduh-2", "lduh", SYN (23), FMT (0), 0x20b0,
954 { 2, 0|A(ALIAS), { (1<<MACH_M32R), PIPE_O } }
956 /* lduh $dr,@($slo16,$sr) */
959 "lduh-d", "lduh", SYN (24), FMT (1), 0xa0b00000,
960 { 2, 0, { (1<<MACH_M32R), PIPE_NONE } }
962 /* lduh $dr,@($sr,$slo16) */
965 "lduh-d2", "lduh", SYN (25), FMT (1), 0xa0b00000,
966 { 2, 0|A(ALIAS), { (1<<MACH_M32R), PIPE_NONE } }
971 "ld-plus", "ld", SYN (26), FMT (0), 0x20e0,
972 { 2, 0, { (1<<MACH_M32R), PIPE_O } }
974 /* ld24 $dr,#$uimm24 */
977 "ld24", "ld24", SYN (27), FMT (16), 0xe0000000,
978 { 2, 0, { (1<<MACH_M32R), PIPE_NONE } }
980 /* ld24 $dr,$uimm24 */
983 "ld24.a", "ld24", SYN (28), FMT (16), 0xe0000000,
984 { 2, 0|A(ALIAS), { (1<<MACH_M32R), PIPE_NONE } }
986 /* ldi $dr,#$simm8 */
989 "ldi8", "ldi", SYN (7), FMT (4), 0x6000,
990 { 2, 0, { (1<<MACH_M32R), PIPE_OS } }
995 "ldi8.a", "ldi", SYN (8), FMT (4), 0x6000,
996 { 2, 0|A(ALIAS), { (1<<MACH_M32R), PIPE_OS } }
998 /* ldi8 $dr,#$simm8 */
1001 "ldi8a", "ldi8", SYN (7), FMT (4), 0x6000,
1002 { 2, 0|A(ALIAS), { (1<<MACH_M32R), PIPE_OS } }
1004 /* ldi8 $dr,$simm8 */
1007 "ldi8a.a", "ldi8", SYN (8), FMT (4), 0x6000,
1008 { 2, 0|A(ALIAS), { (1<<MACH_M32R), PIPE_OS } }
1010 /* ldi $dr,$slo16 */
1013 "ldi16", "ldi", SYN (29), FMT (17), 0x90f00000,
1014 { 2, 0, { (1<<MACH_M32R), PIPE_NONE } }
1016 /* ldi16 $dr,$slo16 */
1019 "ldi16a", "ldi16", SYN (29), FMT (17), 0x90f00000,
1020 { 2, 0|A(ALIAS), { (1<<MACH_M32R), PIPE_NONE } }
1025 "lock", "lock", SYN (22), FMT (0), 0x20d0,
1026 { 2, 0, { (1<<MACH_M32R), PIPE_O } }
1028 /* machi $src1,$src2 */
1031 "machi", "machi", SYN (15), FMT (10), 0x3040,
1032 { 2, 0, { (1<<MACH_M32R), PIPE_S } }
1034 /* start-sanitize-m32rx */
1035 /* machi $src1,$src2,$acc */
1038 "machi-a", "machi", SYN (30), FMT (18), 0x3040,
1039 { 2, 0, { (1<<MACH_M32RX), PIPE_S } }
1041 /* end-sanitize-m32rx */
1042 /* maclo $src1,$src2 */
1045 "maclo", "maclo", SYN (15), FMT (10), 0x3050,
1046 { 2, 0, { (1<<MACH_M32R), PIPE_S } }
1048 /* start-sanitize-m32rx */
1049 /* maclo $src1,$src2,$acc */
1052 "maclo-a", "maclo", SYN (30), FMT (18), 0x3050,
1053 { 2, 0, { (1<<MACH_M32RX), PIPE_S } }
1055 /* end-sanitize-m32rx */
1056 /* macwhi $src1,$src2 */
1059 "macwhi", "macwhi", SYN (15), FMT (10), 0x3060,
1060 { 2, 0, { (1<<MACH_M32R), PIPE_S } }
1062 /* macwlo $src1,$src2 */
1065 "macwlo", "macwlo", SYN (15), FMT (10), 0x3070,
1066 { 2, 0, { (1<<MACH_M32R), PIPE_S } }
1071 "mul", "mul", SYN (0), FMT (0), 0x1060,
1072 { 2, 0, { (1<<MACH_M32R), PIPE_S } }
1074 /* mulhi $src1,$src2 */
1077 "mulhi", "mulhi", SYN (15), FMT (10), 0x3000,
1078 { 2, 0, { (1<<MACH_M32R), PIPE_S } }
1080 /* start-sanitize-m32rx */
1081 /* mulhi $src1,$src2,$acc */
1084 "mulhi-a", "mulhi", SYN (30), FMT (18), 0x3000,
1085 { 2, 0, { (1<<MACH_M32RX), PIPE_S } }
1087 /* end-sanitize-m32rx */
1088 /* mullo $src1,$src2 */
1091 "mullo", "mullo", SYN (15), FMT (10), 0x3010,
1092 { 2, 0, { (1<<MACH_M32R), PIPE_S } }
1094 /* start-sanitize-m32rx */
1095 /* mullo $src1,$src2,$acc */
1098 "mullo-a", "mullo", SYN (30), FMT (18), 0x3010,
1099 { 2, 0, { (1<<MACH_M32RX), PIPE_S } }
1101 /* end-sanitize-m32rx */
1102 /* mulwhi $src1,$src2 */
1105 "mulwhi", "mulwhi", SYN (15), FMT (10), 0x3020,
1106 { 2, 0, { (1<<MACH_M32R), PIPE_S } }
1108 /* mulwlo $src1,$src2 */
1111 "mulwlo", "mulwlo", SYN (15), FMT (10), 0x3030,
1112 { 2, 0, { (1<<MACH_M32R), PIPE_S } }
1117 "mv", "mv", SYN (0), FMT (0), 0x1080,
1118 { 2, 0, { (1<<MACH_M32R), PIPE_OS } }
1123 "mvfachi", "mvfachi", SYN (31), FMT (19), 0x50f0,
1124 { 2, 0, { (1<<MACH_M32R), PIPE_S } }
1126 /* start-sanitize-m32rx */
1127 /* mvfachi $dr,$accs */
1130 "mvfachi-a", "mvfachi", SYN (32), FMT (20), 0x50f0,
1131 { 2, 0, { (1<<MACH_M32RX), PIPE_S } }
1133 /* end-sanitize-m32rx */
1137 "mvfaclo", "mvfaclo", SYN (31), FMT (19), 0x50f1,
1138 { 2, 0, { (1<<MACH_M32R), PIPE_S } }
1140 /* start-sanitize-m32rx */
1141 /* mvfaclo $dr,$accs */
1144 "mvfaclo-a", "mvfaclo", SYN (32), FMT (20), 0x50f1,
1145 { 2, 0, { (1<<MACH_M32RX), PIPE_S } }
1147 /* end-sanitize-m32rx */
1151 "mvfacmi", "mvfacmi", SYN (31), FMT (19), 0x50f2,
1152 { 2, 0, { (1<<MACH_M32R), PIPE_S } }
1154 /* start-sanitize-m32rx */
1155 /* mvfacmi $dr,$accs */
1158 "mvfacmi-a", "mvfacmi", SYN (32), FMT (20), 0x50f2,
1159 { 2, 0, { (1<<MACH_M32RX), PIPE_S } }
1161 /* end-sanitize-m32rx */
1165 "mvfc", "mvfc", SYN (33), FMT (21), 0x1090,
1166 { 2, 0, { (1<<MACH_M32R), PIPE_O } }
1171 "mvtachi", "mvtachi", SYN (34), FMT (22), 0x5070,
1172 { 2, 0, { (1<<MACH_M32R), PIPE_S } }
1174 /* start-sanitize-m32rx */
1175 /* mvtachi $src1,$accs */
1178 "mvtachi-a", "mvtachi", SYN (35), FMT (23), 0x5070,
1179 { 2, 0, { (1<<MACH_M32RX), PIPE_S } }
1181 /* end-sanitize-m32rx */
1185 "mvtaclo", "mvtaclo", SYN (34), FMT (22), 0x5071,
1186 { 2, 0, { (1<<MACH_M32R), PIPE_S } }
1188 /* start-sanitize-m32rx */
1189 /* mvtaclo $src1,$accs */
1192 "mvtaclo-a", "mvtaclo", SYN (35), FMT (23), 0x5071,
1193 { 2, 0, { (1<<MACH_M32RX), PIPE_S } }
1195 /* end-sanitize-m32rx */
1199 "mvtc", "mvtc", SYN (36), FMT (24), 0x10a0,
1200 { 2, 0, { (1<<MACH_M32R), PIPE_O } }
1205 "neg", "neg", SYN (0), FMT (0), 0x30,
1206 { 2, 0, { (1<<MACH_M32R), PIPE_OS } }
1211 "nop", "nop", SYN (37), FMT (25), 0x7000,
1212 { 2, 0, { (1<<MACH_M32R), PIPE_OS } }
1217 "not", "not", SYN (0), FMT (0), 0xb0,
1218 { 2, 0, { (1<<MACH_M32R), PIPE_OS } }
1223 "rac", "rac", SYN (37), FMT (25), 0x5090,
1224 { 2, 0, { (1<<MACH_M32R), PIPE_S } }
1226 /* start-sanitize-m32rx */
1230 "rac-a", "rac", SYN (38), FMT (26), 0x5090,
1231 { 2, 0, { (1<<MACH_M32RX), PIPE_S } }
1233 /* end-sanitize-m32rx */
1237 "rach", "rach", SYN (37), FMT (25), 0x5080,
1238 { 2, 0, { (1<<MACH_M32R), PIPE_S } }
1240 /* start-sanitize-m32rx */
1244 "rach-a", "rach", SYN (38), FMT (26), 0x5080,
1245 { 2, 0, { (1<<MACH_M32RX), PIPE_S } }
1247 /* end-sanitize-m32rx */
1251 "rte", "rte", SYN (37), FMT (25), 0x10d6,
1252 { 2, 0|A(UNCOND_CTI), { (1<<MACH_M32R), PIPE_O } }
1254 /* seth $dr,#$hi16 */
1257 "seth", "seth", SYN (39), FMT (27), 0xd0c00000,
1258 { 2, 0, { (1<<MACH_M32R), PIPE_NONE } }
1260 /* seth $dr,$hi16 */
1263 "seth.a", "seth", SYN (40), FMT (27), 0xd0c00000,
1264 { 2, 0|A(ALIAS), { (1<<MACH_M32R), PIPE_NONE } }
1269 "sll", "sll", SYN (0), FMT (0), 0x1040,
1270 { 2, 0, { (1<<MACH_M32R), PIPE_O } }
1272 /* sll3 $dr,$sr,#$simm16 */
1275 "sll3", "sll3", SYN (9), FMT (5), 0x90c00000,
1276 { 2, 0, { (1<<MACH_M32R), PIPE_NONE } }
1278 /* sll3 $dr,$sr,$simm16 */
1281 "sll3.a", "sll3", SYN (10), FMT (5), 0x90c00000,
1282 { 2, 0|A(ALIAS), { (1<<MACH_M32R), PIPE_NONE } }
1284 /* slli $dr,#$uimm5 */
1287 "slli", "slli", SYN (41), FMT (28), 0x5040,
1288 { 2, 0, { (1<<MACH_M32R), PIPE_O } }
1290 /* slli $dr,$uimm5 */
1293 "slli.a", "slli", SYN (42), FMT (28), 0x5040,
1294 { 2, 0|A(ALIAS), { (1<<MACH_M32R), PIPE_O } }
1299 "sra", "sra", SYN (0), FMT (0), 0x1020,
1300 { 2, 0, { (1<<MACH_M32R), PIPE_O } }
1302 /* sra3 $dr,$sr,#$simm16 */
1305 "sra3", "sra3", SYN (9), FMT (5), 0x90a00000,
1306 { 2, 0, { (1<<MACH_M32R), PIPE_NONE } }
1308 /* sra3 $dr,$sr,$simm16 */
1311 "sra3.a", "sra3", SYN (10), FMT (5), 0x90a00000,
1312 { 2, 0|A(ALIAS), { (1<<MACH_M32R), PIPE_NONE } }
1314 /* srai $dr,#$uimm5 */
1317 "srai", "srai", SYN (41), FMT (28), 0x5020,
1318 { 2, 0, { (1<<MACH_M32R), PIPE_O } }
1320 /* srai $dr,$uimm5 */
1323 "srai.a", "srai", SYN (42), FMT (28), 0x5020,
1324 { 2, 0|A(ALIAS), { (1<<MACH_M32R), PIPE_O } }
1329 "srl", "srl", SYN (0), FMT (0), 0x1000,
1330 { 2, 0, { (1<<MACH_M32R), PIPE_O } }
1332 /* srl3 $dr,$sr,#$simm16 */
1335 "srl3", "srl3", SYN (9), FMT (5), 0x90800000,
1336 { 2, 0, { (1<<MACH_M32R), PIPE_NONE } }
1338 /* srl3 $dr,$sr,$simm16 */
1341 "srl3.a", "srl3", SYN (10), FMT (5), 0x90800000,
1342 { 2, 0|A(ALIAS), { (1<<MACH_M32R), PIPE_NONE } }
1344 /* srli $dr,#$uimm5 */
1347 "srli", "srli", SYN (41), FMT (28), 0x5000,
1348 { 2, 0, { (1<<MACH_M32R), PIPE_O } }
1350 /* srli $dr,$uimm5 */
1353 "srli.a", "srli", SYN (42), FMT (28), 0x5000,
1354 { 2, 0|A(ALIAS), { (1<<MACH_M32R), PIPE_O } }
1356 /* st $src1,@$src2 */
1359 "st", "st", SYN (43), FMT (10), 0x2040,
1360 { 2, 0, { (1<<MACH_M32R), PIPE_O } }
1362 /* st $src1,@($src2) */
1365 "st-2", "st", SYN (44), FMT (10), 0x2040,
1366 { 2, 0|A(ALIAS), { (1<<MACH_M32R), PIPE_O } }
1368 /* st $src1,@($slo16,$src2) */
1371 "st-d", "st", SYN (45), FMT (29), 0xa0400000,
1372 { 2, 0, { (1<<MACH_M32R), PIPE_NONE } }
1374 /* st $src1,@($src2,$slo16) */
1377 "st-d2", "st", SYN (46), FMT (29), 0xa0400000,
1378 { 2, 0|A(ALIAS), { (1<<MACH_M32R), PIPE_NONE } }
1380 /* stb $src1,@$src2 */
1383 "stb", "stb", SYN (43), FMT (10), 0x2000,
1384 { 2, 0, { (1<<MACH_M32R), PIPE_O } }
1386 /* stb $src1,@($src2) */
1389 "stb-2", "stb", SYN (44), FMT (10), 0x2000,
1390 { 2, 0|A(ALIAS), { (1<<MACH_M32R), PIPE_O } }
1392 /* stb $src1,@($slo16,$src2) */
1395 "stb-d", "stb", SYN (45), FMT (29), 0xa0000000,
1396 { 2, 0, { (1<<MACH_M32R), PIPE_NONE } }
1398 /* stb $src1,@($src2,$slo16) */
1401 "stb-d2", "stb", SYN (46), FMT (29), 0xa0000000,
1402 { 2, 0|A(ALIAS), { (1<<MACH_M32R), PIPE_NONE } }
1404 /* sth $src1,@$src2 */
1407 "sth", "sth", SYN (43), FMT (10), 0x2020,
1408 { 2, 0, { (1<<MACH_M32R), PIPE_O } }
1410 /* sth $src1,@($src2) */
1413 "sth-2", "sth", SYN (44), FMT (10), 0x2020,
1414 { 2, 0|A(ALIAS), { (1<<MACH_M32R), PIPE_O } }
1416 /* sth $src1,@($slo16,$src2) */
1419 "sth-d", "sth", SYN (45), FMT (29), 0xa0200000,
1420 { 2, 0, { (1<<MACH_M32R), PIPE_NONE } }
1422 /* sth $src1,@($src2,$slo16) */
1425 "sth-d2", "sth", SYN (46), FMT (29), 0xa0200000,
1426 { 2, 0|A(ALIAS), { (1<<MACH_M32R), PIPE_NONE } }
1428 /* st $src1,@+$src2 */
1431 "st-plus", "st", SYN (47), FMT (10), 0x2060,
1432 { 2, 0, { (1<<MACH_M32R), PIPE_O } }
1434 /* st $src1,@-$src2 */
1437 "st-minus", "st", SYN (48), FMT (10), 0x2070,
1438 { 2, 0, { (1<<MACH_M32R), PIPE_O } }
1443 "sub", "sub", SYN (0), FMT (0), 0x20,
1444 { 2, 0, { (1<<MACH_M32R), PIPE_OS } }
1449 "subv", "subv", SYN (0), FMT (0), 0x0,
1450 { 2, 0, { (1<<MACH_M32R), PIPE_OS } }
1455 "subx", "subx", SYN (0), FMT (0), 0x10,
1456 { 2, 0, { (1<<MACH_M32R), PIPE_OS } }
1461 "trap", "trap", SYN (49), FMT (30), 0x10f0,
1462 { 2, 0|A(FILL_SLOT)|A(UNCOND_CTI), { (1<<MACH_M32R), PIPE_O } }
1467 "trap.a", "trap", SYN (50), FMT (30), 0x10f0,
1468 { 2, 0|A(ALIAS)|A(FILL_SLOT)|A(UNCOND_CTI), { (1<<MACH_M32R), PIPE_O } }
1470 /* unlock $src1,@$src2 */
1473 "unlock", "unlock", SYN (43), FMT (10), 0x2050,
1474 { 2, 0, { (1<<MACH_M32R), PIPE_O } }
1479 "push", "push", SYN (34), FMT (22), 0x207f,
1480 { 2, 0|A(ALIAS), { (1<<MACH_M32R), PIPE_NONE } }
1485 "pop", "pop", SYN (31), FMT (19), 0x20ef,
1486 { 2, 0|A(ALIAS), { (1<<MACH_M32R), PIPE_NONE } }
1488 /* start-sanitize-m32rx */
1489 /* satb $dr,$src2 */
1492 "satb", "satb", SYN (51), FMT (31), 0x80000100,
1493 { 2, 0, { (1<<MACH_M32RX), PIPE_NONE } }
1495 /* end-sanitize-m32rx */
1496 /* start-sanitize-m32rx */
1497 /* sath $dr,$src2 */
1500 "sath", "sath", SYN (51), FMT (31), 0x80000200,
1501 { 2, 0, { (1<<MACH_M32RX), PIPE_NONE } }
1503 /* end-sanitize-m32rx */
1504 /* start-sanitize-m32rx */
1508 "sat", "sat", SYN (51), FMT (31), 0x80000000,
1509 { 2, 0, { (1<<MACH_M32RX), PIPE_NONE } }
1511 /* end-sanitize-m32rx */
1512 /* start-sanitize-m32rx */
1516 "pcmpbz", "pcmpbz", SYN (20), FMT (13), 0x370,
1517 { 2, 0, { (1<<MACH_M32RX), PIPE_OS } }
1519 /* end-sanitize-m32rx */
1520 /* start-sanitize-m32rx */
1524 "sadd", "sadd", SYN (37), FMT (25), 0x50e4,
1525 { 2, 0, { (1<<MACH_M32RX), PIPE_S } }
1527 /* end-sanitize-m32rx */
1528 /* start-sanitize-m32rx */
1529 /* macwu1 $src1,$src2 */
1532 "macwu1", "macwu1", SYN (15), FMT (10), 0x50b0,
1533 { 2, 0, { (1<<MACH_M32RX), PIPE_S } }
1535 /* end-sanitize-m32rx */
1536 /* start-sanitize-m32rx */
1537 /* msblo $src1,$src2 */
1540 "msblo", "msblo", SYN (15), FMT (10), 0x50d0,
1541 { 2, 0, { (1<<MACH_M32RX), PIPE_S } }
1543 /* end-sanitize-m32rx */
1544 /* start-sanitize-m32rx */
1545 /* mulwu1 $src1,$src2 */
1548 "mulwu1", "mulwu1", SYN (15), FMT (10), 0x50a0,
1549 { 2, 0, { (1<<MACH_M32RX), PIPE_S } }
1551 /* end-sanitize-m32rx */
1552 /* start-sanitize-m32rx */
1553 /* machl1 $src1,$src2 */
1556 "machl1", "machl1", SYN (15), FMT (10), 0x50c0,
1557 { 2, 0, { (1<<MACH_M32RX), PIPE_S } }
1559 /* end-sanitize-m32rx */
1560 /* start-sanitize-m32rx */
1564 "sc", "sc", SYN (37), FMT (25), 0x7401,
1565 { 2, 0, { (1<<MACH_M32RX), PIPE_O } }
1567 /* end-sanitize-m32rx */
1568 /* start-sanitize-m32rx */
1572 "snc", "snc", SYN (37), FMT (25), 0x7501,
1573 { 2, 0, { (1<<MACH_M32RX), PIPE_O } }
1575 /* end-sanitize-m32rx */
1582 CGEN_INSN_TABLE m32r_cgen_insn_table =
1584 & m32r_cgen_insn_table_entries[0],
1588 m32r_cgen_asm_hash_insn, CGEN_ASM_HASH_SIZE,
1589 m32r_cgen_dis_hash_insn, CGEN_DIS_HASH_SIZE
1592 /* The hash functions are recorded here to help keep assembler code out of
1593 the disassembler and vice versa. */
1596 m32r_cgen_asm_hash_insn (insn)
1599 return CGEN_ASM_HASH (insn);
1603 m32r_cgen_dis_hash_insn (buf, value)
1605 unsigned long value;
1607 return CGEN_DIS_HASH (buf, value);
1610 CGEN_OPCODE_DATA m32r_cgen_opcode_data =
1612 & m32r_cgen_hw_entries[0],
1613 & m32r_cgen_insn_table,
1617 m32r_cgen_init_tables (mach)
1622 /* Main entry point for stuffing values in cgen_fields. */
1625 m32r_cgen_set_operand (opindex, valuep, fields)
1627 const long * valuep;
1628 CGEN_FIELDS * fields;
1632 case M32R_OPERAND_SR :
1633 fields->f_r2 = * valuep;
1635 case M32R_OPERAND_DR :
1636 fields->f_r1 = * valuep;
1638 case M32R_OPERAND_SRC1 :
1639 fields->f_r1 = * valuep;
1641 case M32R_OPERAND_SRC2 :
1642 fields->f_r2 = * valuep;
1644 case M32R_OPERAND_SCR :
1645 fields->f_r2 = * valuep;
1647 case M32R_OPERAND_DCR :
1648 fields->f_r1 = * valuep;
1650 case M32R_OPERAND_SIMM8 :
1651 fields->f_simm8 = * valuep;
1653 case M32R_OPERAND_SIMM16 :
1654 fields->f_simm16 = * valuep;
1656 case M32R_OPERAND_UIMM4 :
1657 fields->f_uimm4 = * valuep;
1659 case M32R_OPERAND_UIMM5 :
1660 fields->f_uimm5 = * valuep;
1662 case M32R_OPERAND_UIMM16 :
1663 fields->f_uimm16 = * valuep;
1665 /* start-sanitize-m32rx */
1666 case M32R_OPERAND_ACCS :
1667 fields->f_accs = * valuep;
1669 /* end-sanitize-m32rx */
1670 /* start-sanitize-m32rx */
1671 case M32R_OPERAND_ACC :
1672 fields->f_acc = * valuep;
1674 /* end-sanitize-m32rx */
1675 case M32R_OPERAND_HI16 :
1676 fields->f_hi16 = * valuep;
1678 case M32R_OPERAND_SLO16 :
1679 fields->f_simm16 = * valuep;
1681 case M32R_OPERAND_ULO16 :
1682 fields->f_uimm16 = * valuep;
1684 case M32R_OPERAND_UIMM24 :
1685 fields->f_uimm24 = * valuep;
1687 case M32R_OPERAND_DISP8 :
1688 fields->f_disp8 = * valuep;
1690 case M32R_OPERAND_DISP16 :
1691 fields->f_disp16 = * valuep;
1693 case M32R_OPERAND_DISP24 :
1694 fields->f_disp24 = * valuep;
1698 fprintf (stderr, "Unrecognized field %d while setting operand.\n",
1704 /* Main entry point for getting values from cgen_fields. */
1707 m32r_cgen_get_operand (opindex, fields)
1709 const CGEN_FIELDS * fields;
1715 case M32R_OPERAND_SR :
1716 value = fields->f_r2;
1718 case M32R_OPERAND_DR :
1719 value = fields->f_r1;
1721 case M32R_OPERAND_SRC1 :
1722 value = fields->f_r1;
1724 case M32R_OPERAND_SRC2 :
1725 value = fields->f_r2;
1727 case M32R_OPERAND_SCR :
1728 value = fields->f_r2;
1730 case M32R_OPERAND_DCR :
1731 value = fields->f_r1;
1733 case M32R_OPERAND_SIMM8 :
1734 value = fields->f_simm8;
1736 case M32R_OPERAND_SIMM16 :
1737 value = fields->f_simm16;
1739 case M32R_OPERAND_UIMM4 :
1740 value = fields->f_uimm4;
1742 case M32R_OPERAND_UIMM5 :
1743 value = fields->f_uimm5;
1745 case M32R_OPERAND_UIMM16 :
1746 value = fields->f_uimm16;
1748 /* start-sanitize-m32rx */
1749 case M32R_OPERAND_ACCS :
1750 value = fields->f_accs;
1752 /* end-sanitize-m32rx */
1753 /* start-sanitize-m32rx */
1754 case M32R_OPERAND_ACC :
1755 value = fields->f_acc;
1757 /* end-sanitize-m32rx */
1758 case M32R_OPERAND_HI16 :
1759 value = fields->f_hi16;
1761 case M32R_OPERAND_SLO16 :
1762 value = fields->f_simm16;
1764 case M32R_OPERAND_ULO16 :
1765 value = fields->f_uimm16;
1767 case M32R_OPERAND_UIMM24 :
1768 value = fields->f_uimm24;
1770 case M32R_OPERAND_DISP8 :
1771 value = fields->f_disp8;
1773 case M32R_OPERAND_DISP16 :
1774 value = fields->f_disp16;
1776 case M32R_OPERAND_DISP24 :
1777 value = fields->f_disp24;
1781 fprintf (stderr, "Unrecognized field %d while getting operand.\n",