1 /* CGEN opcode support for m32r.
3 Copyright (C) 1996, 1997, 1998 Free Software Foundation, Inc.
5 This file is part of the GNU Binutils and/or GDB, the GNU debugger.
7 This program is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 2, or (at your option)
12 This program is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
17 You should have received a copy of the GNU General Public License along
18 with this program; if not, write to the Free Software Foundation, Inc.,
19 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
27 #include "libiberty.h"
33 static const CGEN_ATTR_ENTRY MACH_attr[] =
35 { "m32r", MACH_M32R },
39 const CGEN_ATTR_TABLE m32r_cgen_operand_attr_table[] =
45 { "PCREL-ADDR", NULL },
53 const CGEN_ATTR_TABLE m32r_cgen_insn_attr_table[] =
57 { "FILL-SLOT", NULL },
61 { "RELAX-BNC", NULL },
62 { "RELAX-BRA", NULL },
63 { "RELAXABLE", NULL },
64 { "UNCOND-CTI", NULL },
68 CGEN_KEYWORD_ENTRY m32r_cgen_opval_mach_entries[] =
73 CGEN_KEYWORD m32r_cgen_opval_mach =
75 & m32r_cgen_opval_mach_entries[0],
79 CGEN_KEYWORD_ENTRY m32r_cgen_opval_h_gr_entries[] =
102 CGEN_KEYWORD m32r_cgen_opval_h_gr =
104 & m32r_cgen_opval_h_gr_entries[0],
108 CGEN_KEYWORD_ENTRY m32r_cgen_opval_h_cr_entries[] =
124 CGEN_KEYWORD m32r_cgen_opval_h_cr =
126 & m32r_cgen_opval_h_cr_entries[0],
131 static CGEN_HW_ENTRY m32r_cgen_hw_entries[] =
133 { & m32r_cgen_hw_entries[1], "h-pc", CGEN_ASM_KEYWORD /*FIXME*/, 0 },
134 { & m32r_cgen_hw_entries[2], "h-memory", CGEN_ASM_KEYWORD /*FIXME*/, 0 },
135 { & m32r_cgen_hw_entries[3], "h-sint", CGEN_ASM_KEYWORD /*FIXME*/, 0 },
136 { & m32r_cgen_hw_entries[4], "h-uint", CGEN_ASM_KEYWORD /*FIXME*/, 0 },
137 { & m32r_cgen_hw_entries[5], "h-addr", CGEN_ASM_KEYWORD /*FIXME*/, 0 },
138 { & m32r_cgen_hw_entries[6], "h-iaddr", CGEN_ASM_KEYWORD /*FIXME*/, 0 },
139 { & m32r_cgen_hw_entries[7], "h-hi16", CGEN_ASM_KEYWORD /*FIXME*/, 0 },
140 { & m32r_cgen_hw_entries[8], "h-slo16", CGEN_ASM_KEYWORD /*FIXME*/, 0 },
141 { & m32r_cgen_hw_entries[9], "h-ulo16", CGEN_ASM_KEYWORD /*FIXME*/, 0 },
142 { & m32r_cgen_hw_entries[10], "h-gr", CGEN_ASM_KEYWORD /*FIXME*/, & m32r_cgen_opval_h_gr },
143 { & m32r_cgen_hw_entries[11], "h-cr", CGEN_ASM_KEYWORD /*FIXME*/, & m32r_cgen_opval_h_cr },
144 { & m32r_cgen_hw_entries[12], "h-accum", CGEN_ASM_KEYWORD /*FIXME*/, 0 },
145 { & m32r_cgen_hw_entries[13], "h-cond", CGEN_ASM_KEYWORD /*FIXME*/, 0 },
146 { & m32r_cgen_hw_entries[14], "h-sm", CGEN_ASM_KEYWORD /*FIXME*/, 0 },
147 { & m32r_cgen_hw_entries[15], "h-bsm", CGEN_ASM_KEYWORD /*FIXME*/, 0 },
148 { & m32r_cgen_hw_entries[16], "h-ie", CGEN_ASM_KEYWORD /*FIXME*/, 0 },
149 { & m32r_cgen_hw_entries[17], "h-bie", CGEN_ASM_KEYWORD /*FIXME*/, 0 },
150 { & m32r_cgen_hw_entries[18], "h-bcond", CGEN_ASM_KEYWORD /*FIXME*/, 0 },
151 { NULL, "h-bpc", CGEN_ASM_KEYWORD /*FIXME*/, 0 }
155 const CGEN_OPERAND m32r_cgen_operand_table[CGEN_NUM_OPERANDS] =
157 /* pc: program counter */
158 { "pc", 0, 0, { 0, 0|(1<<CGEN_OPERAND_FAKE)|(1<<CGEN_OPERAND_PC), { 0 } } },
159 /* sr: source register */
160 { "sr", 12, 4, { 0, 0|(1<<CGEN_OPERAND_UNSIGNED), { 0 } } },
161 /* dr: destination register */
162 { "dr", 4, 4, { 0, 0|(1<<CGEN_OPERAND_UNSIGNED), { 0 } } },
163 /* src1: source register 1 */
164 { "src1", 4, 4, { 0, 0|(1<<CGEN_OPERAND_UNSIGNED), { 0 } } },
165 /* src2: source register 2 */
166 { "src2", 12, 4, { 0, 0|(1<<CGEN_OPERAND_UNSIGNED), { 0 } } },
167 /* scr: source control register */
168 { "scr", 12, 4, { 0, 0|(1<<CGEN_OPERAND_UNSIGNED), { 0 } } },
169 /* dcr: destination control register */
170 { "dcr", 4, 4, { 0, 0|(1<<CGEN_OPERAND_UNSIGNED), { 0 } } },
171 /* simm8: 8 bit signed immediate */
172 { "simm8", 8, 8, { 0, 0, { 0 } } },
173 /* simm16: 16 bit signed immediate */
174 { "simm16", 16, 16, { 0, 0, { 0 } } },
175 /* uimm4: 4 bit trap number */
176 { "uimm4", 12, 4, { 0, 0|(1<<CGEN_OPERAND_UNSIGNED), { 0 } } },
177 /* uimm5: 5 bit shift count */
178 { "uimm5", 11, 5, { 0, 0|(1<<CGEN_OPERAND_UNSIGNED), { 0 } } },
179 /* uimm16: 16 bit unsigned immediate */
180 { "uimm16", 16, 16, { 0, 0|(1<<CGEN_OPERAND_UNSIGNED), { 0 } } },
181 /* hi16: high 16 bit immediate, sign optional */
182 { "hi16", 16, 16, { 0, 0|(1<<CGEN_OPERAND_SIGN_OPT)|(1<<CGEN_OPERAND_UNSIGNED), { 0 } } },
183 /* slo16: 16 bit signed immediate, for low() */
184 { "slo16", 16, 16, { 0, 0, { 0 } } },
185 /* ulo16: 16 bit unsigned immediate, for low() */
186 { "ulo16", 16, 16, { 0, 0|(1<<CGEN_OPERAND_UNSIGNED), { 0 } } },
187 /* uimm24: 24 bit address */
188 { "uimm24", 8, 24, { 0, 0|(1<<CGEN_OPERAND_RELOC)|(1<<CGEN_OPERAND_ABS_ADDR)|(1<<CGEN_OPERAND_UNSIGNED), { 0 } } },
189 /* disp8: 8 bit displacement */
190 { "disp8", 8, 8, { 0, 0|(1<<CGEN_OPERAND_RELAX)|(1<<CGEN_OPERAND_RELOC)|(1<<CGEN_OPERAND_PCREL_ADDR), { 0 } } },
191 /* disp16: 16 bit displacement */
192 { "disp16", 16, 16, { 0, 0|(1<<CGEN_OPERAND_RELOC)|(1<<CGEN_OPERAND_PCREL_ADDR), { 0 } } },
193 /* disp24: 24 bit displacement */
194 { "disp24", 8, 24, { 0, 0|(1<<CGEN_OPERAND_RELAX)|(1<<CGEN_OPERAND_RELOC)|(1<<CGEN_OPERAND_PCREL_ADDR), { 0 } } },
195 /* condbit: condition bit */
196 { "condbit", 0, 0, { 0, 0|(1<<CGEN_OPERAND_FAKE), { 0 } } },
197 /* accum: accumulator */
198 { "accum", 0, 0, { 0, 0|(1<<CGEN_OPERAND_FAKE), { 0 } } },
201 #define OP 1 /* syntax value for mnemonic */
203 static const CGEN_SYNTAX syntax_table[] =
206 /* 0 */ { OP, ' ', 130, ',', 129, 0 },
207 /* <op> $dr,$sr,$slo16 */
208 /* 1 */ { OP, ' ', 130, ',', 129, ',', 141, 0 },
209 /* <op> $dr,$sr,$uimm16 */
210 /* 2 */ { OP, ' ', 130, ',', 129, ',', 139, 0 },
211 /* <op> $dr,$sr,$ulo16 */
212 /* 3 */ { OP, ' ', 130, ',', 129, ',', 142, 0 },
213 /* <op> $dr,$simm8 */
214 /* 4 */ { OP, ' ', 130, ',', 135, 0 },
215 /* <op> $dr,$sr,$simm16 */
216 /* 5 */ { OP, ' ', 130, ',', 129, ',', 136, 0 },
218 /* 6 */ { OP, ' ', 144, 0 },
220 /* 7 */ { OP, ' ', 146, 0 },
221 /* <op> $src1,$src2,$disp16 */
222 /* 8 */ { OP, ' ', 131, ',', 132, ',', 145, 0 },
223 /* <op> $src2,$disp16 */
224 /* 9 */ { OP, ' ', 132, ',', 145, 0 },
225 /* <op> $src1,$src2 */
226 /* 10 */ { OP, ' ', 131, ',', 132, 0 },
227 /* <op> $src2,$simm16 */
228 /* 11 */ { OP, ' ', 132, ',', 136, 0 },
229 /* <op> $src2,$uimm16 */
230 /* 12 */ { OP, ' ', 132, ',', 139, 0 },
232 /* 13 */ { OP, ' ', 129, 0 },
234 /* 14 */ { OP, ' ', 130, ',', '@', 129, 0 },
235 /* <op> $dr,@($sr) */
236 /* 15 */ { OP, ' ', 130, ',', '@', '(', 129, ')', 0 },
237 /* <op> $dr,@($slo16,$sr) */
238 /* 16 */ { OP, ' ', 130, ',', '@', '(', 141, ',', 129, ')', 0 },
239 /* <op> $dr,@($sr,$slo16) */
240 /* 17 */ { OP, ' ', 130, ',', '@', '(', 129, ',', 141, ')', 0 },
242 /* 18 */ { OP, ' ', 130, ',', '@', 129, '+', 0 },
243 /* <op> $dr,$uimm24 */
244 /* 19 */ { OP, ' ', 130, ',', 143, 0 },
245 /* <op> $dr,$slo16 */
246 /* 20 */ { OP, ' ', 130, ',', 141, 0 },
248 /* 21 */ { OP, ' ', 130, 0 },
250 /* 22 */ { OP, ' ', 130, ',', 133, 0 },
252 /* 23 */ { OP, ' ', 131, 0 },
254 /* 24 */ { OP, ' ', 129, ',', 134, 0 },
258 /* 26 */ { OP, ' ', 130, ',', 140, 0 },
259 /* <op> $dr,$uimm5 */
260 /* 27 */ { OP, ' ', 130, ',', 138, 0 },
261 /* <op> $src1,@$src2 */
262 /* 28 */ { OP, ' ', 131, ',', '@', 132, 0 },
263 /* <op> $src1,@($src2) */
264 /* 29 */ { OP, ' ', 131, ',', '@', '(', 132, ')', 0 },
265 /* <op> $src1,@($slo16,$src2) */
266 /* 30 */ { OP, ' ', 131, ',', '@', '(', 141, ',', 132, ')', 0 },
267 /* <op> $src1,@($src2,$slo16) */
268 /* 31 */ { OP, ' ', 131, ',', '@', '(', 132, ',', 141, ')', 0 },
269 /* <op> $src1,@+$src2 */
270 /* 32 */ { OP, ' ', 131, ',', '@', '+', 132, 0 },
271 /* <op> $src1,@-$src2 */
272 /* 33 */ { OP, ' ', 131, ',', '@', '-', 132, 0 },
274 /* 34 */ { OP, ' ', 137, 0 },
279 static const CGEN_FORMAT format_table[] =
281 /* f-op1.number.f-r1.dr.f-op2.number.f-r2.sr. */
282 /* 0 */ { 16, 16, 0xf0f0 },
283 /* f-op1.number.f-r1.dr.f-op2.number.f-r2.sr.f-simm16.slo16. */
284 /* 1 */ { 32, 32, 0xf0f00000 },
285 /* f-op1.number.f-r1.dr.f-op2.number.f-r2.sr.f-uimm16.uimm16. */
286 /* 2 */ { 32, 32, 0xf0f00000 },
287 /* f-op1.number.f-r1.dr.f-op2.number.f-r2.sr.f-uimm16.ulo16. */
288 /* 3 */ { 32, 32, 0xf0f00000 },
289 /* f-op1.number.f-r1.dr.f-simm8.simm8. */
290 /* 4 */ { 16, 16, 0xf000 },
291 /* f-op1.number.f-r1.dr.f-op2.number.f-r2.sr.f-simm16.simm16. */
292 /* 5 */ { 32, 32, 0xf0f00000 },
293 /* f-op1.number.f-r1.number.f-disp8.disp8. */
294 /* 6 */ { 16, 16, 0xff00 },
295 /* f-op1.number.f-r1.number.f-disp24.disp24. */
296 /* 7 */ { 32, 32, 0xff000000 },
297 /* f-op1.number.f-r1.src1.f-op2.number.f-r2.src2.f-disp16.disp16. */
298 /* 8 */ { 32, 32, 0xf0f00000 },
299 /* f-op1.number.f-r1.number.f-op2.number.f-r2.src2.f-disp16.disp16. */
300 /* 9 */ { 32, 32, 0xfff00000 },
301 /* f-op1.number.f-r1.src1.f-op2.number.f-r2.src2. */
302 /* 10 */ { 16, 16, 0xf0f0 },
303 /* f-op1.number.f-r1.number.f-op2.number.f-r2.src2.f-simm16.simm16. */
304 /* 11 */ { 32, 32, 0xfff00000 },
305 /* f-op1.number.f-r1.number.f-op2.number.f-r2.src2.f-uimm16.uimm16. */
306 /* 12 */ { 32, 32, 0xfff00000 },
307 /* f-op1.number.f-r1.dr.f-op2.number.f-r2.sr.f-simm16.number. */
308 /* 13 */ { 32, 32, 0xf0f0ffff },
309 /* f-op1.number.f-r1.number.f-op2.number.f-r2.sr. */
310 /* 14 */ { 16, 16, 0xfff0 },
311 /* f-op1.number.f-r1.dr.f-uimm24.uimm24. */
312 /* 15 */ { 32, 32, 0xf0000000 },
313 /* f-op1.number.f-r1.dr.f-op2.number.f-r2.number.f-simm16.slo16. */
314 /* 16 */ { 32, 32, 0xf0ff0000 },
315 /* f-op1.number.f-r1.dr.f-op2.number.f-r2.number. */
316 /* 17 */ { 16, 16, 0xf0ff },
317 /* f-op1.number.f-r1.dr.f-op2.number.f-r2.scr. */
318 /* 18 */ { 16, 16, 0xf0f0 },
319 /* f-op1.number.f-r1.src1.f-op2.number.f-r2.number. */
320 /* 19 */ { 16, 16, 0xf0ff },
321 /* f-op1.number.f-r1.dcr.f-op2.number.f-r2.sr. */
322 /* 20 */ { 16, 16, 0xf0f0 },
323 /* f-op1.number.f-r1.number.f-op2.number.f-r2.number. */
324 /* 21 */ { 16, 16, 0xffff },
325 /* f-op1.number.f-r1.dr.f-op2.number.f-r2.number.f-hi16.hi16. */
326 /* 22 */ { 32, 32, 0xf0ff0000 },
327 /* f-op1.number.f-r1.dr.f-shift-op2.number.f-uimm5.uimm5. */
328 /* 23 */ { 16, 16, 0xf0e0 },
329 /* f-op1.number.f-r1.src1.f-op2.number.f-r2.src2.f-simm16.slo16. */
330 /* 24 */ { 32, 32, 0xf0f00000 },
331 /* f-op1.number.f-r1.number.f-op2.number.f-uimm4.uimm4. */
332 /* 25 */ { 16, 16, 0xfff0 },
335 #define A(a) (1 << CGEN_CAT3 (CGEN_INSN,_,a))
336 #define SYN(n) (& syntax_table[n])
337 #define FMT(n) (& format_table[n])
339 const CGEN_INSN m32r_cgen_insn_table_entries[CGEN_NUM_INSNS] =
341 /* null first entry, end of all hash chains */
346 "add", "add", SYN (0), FMT (0), 0xa0,
349 /* add3 $dr,$sr,$slo16 */
352 "add3", "add3", SYN (1), FMT (1), 0x80a00000,
358 "and", "and", SYN (0), FMT (0), 0xc0,
361 /* and3 $dr,$sr,$uimm16 */
364 "and3", "and3", SYN (2), FMT (2), 0x80c00000,
370 "or", "or", SYN (0), FMT (0), 0xe0,
373 /* or3 $dr,$sr,$ulo16 */
376 "or3", "or3", SYN (3), FMT (3), 0x80e00000,
382 "xor", "xor", SYN (0), FMT (0), 0xd0,
385 /* xor3 $dr,$sr,$uimm16 */
388 "xor3", "xor3", SYN (2), FMT (2), 0x80d00000,
391 /* addi $dr,$simm8 */
394 "addi", "addi", SYN (4), FMT (4), 0x4000,
400 "addv", "addv", SYN (0), FMT (0), 0x80,
403 /* addv3 $dr,$sr,$simm16 */
406 "addv3", "addv3", SYN (5), FMT (5), 0x80800000,
412 "addx", "addx", SYN (0), FMT (0), 0x90,
418 "bc8", "bc", SYN (6), FMT (6), 0x7c00,
419 { 0, 0|A(RELAX_BC)|A(RELAXABLE)|A(COND_CTI), { 0 } }
424 "bc8.s", "bc.s", SYN (6), FMT (6), 0x7c00,
425 { 0, 0|A(ALIAS)|A(COND_CTI), { 0 } }
430 "bc24", "bc", SYN (7), FMT (7), 0xfc000000,
431 { 0, 0|A(RELAX_BC)|A(RELAX)|A(COND_CTI), { 0 } }
436 "bc24.l", "bc.l", SYN (7), FMT (7), 0xfc000000,
437 { 0, 0|A(ALIAS)|A(COND_CTI), { 0 } }
439 /* beq $src1,$src2,$disp16 */
442 "beq", "beq", SYN (8), FMT (8), 0xb0000000,
443 { 0, 0|A(COND_CTI), { 0 } }
445 /* beqz $src2,$disp16 */
448 "beqz", "beqz", SYN (9), FMT (9), 0xb0800000,
449 { 0, 0|A(COND_CTI), { 0 } }
451 /* bgez $src2,$disp16 */
454 "bgez", "bgez", SYN (9), FMT (9), 0xb0b00000,
455 { 0, 0|A(COND_CTI), { 0 } }
457 /* bgtz $src2,$disp16 */
460 "bgtz", "bgtz", SYN (9), FMT (9), 0xb0d00000,
461 { 0, 0|A(COND_CTI), { 0 } }
463 /* blez $src2,$disp16 */
466 "blez", "blez", SYN (9), FMT (9), 0xb0c00000,
467 { 0, 0|A(COND_CTI), { 0 } }
469 /* bltz $src2,$disp16 */
472 "bltz", "bltz", SYN (9), FMT (9), 0xb0a00000,
473 { 0, 0|A(COND_CTI), { 0 } }
475 /* bnez $src2,$disp16 */
478 "bnez", "bnez", SYN (9), FMT (9), 0xb0900000,
479 { 0, 0|A(COND_CTI), { 0 } }
484 "bl8", "bl", SYN (6), FMT (6), 0x7e00,
485 { 0, 0|A(FILL_SLOT)|A(RELAX_BL)|A(RELAXABLE)|A(UNCOND_CTI), { 0 } }
490 "bl8.s", "bl.s", SYN (6), FMT (6), 0x7e00,
491 { 0, 0|A(FILL_SLOT)|A(ALIAS)|A(UNCOND_CTI), { 0 } }
496 "bl24", "bl", SYN (7), FMT (7), 0xfe000000,
497 { 0, 0|A(RELAX_BL)|A(RELAX)|A(UNCOND_CTI), { 0 } }
502 "bl24.l", "bl.l", SYN (7), FMT (7), 0xfe000000,
503 { 0, 0|A(ALIAS)|A(UNCOND_CTI), { 0 } }
508 "bnc8", "bnc", SYN (6), FMT (6), 0x7d00,
509 { 0, 0|A(RELAX_BNC)|A(RELAXABLE)|A(COND_CTI), { 0 } }
514 "bnc8.s", "bnc.s", SYN (6), FMT (6), 0x7d00,
515 { 0, 0|A(ALIAS)|A(COND_CTI), { 0 } }
520 "bnc24", "bnc", SYN (7), FMT (7), 0xfd000000,
521 { 0, 0|A(RELAX_BNC)|A(RELAX)|A(COND_CTI), { 0 } }
526 "bnc24.l", "bnc.l", SYN (7), FMT (7), 0xfd000000,
527 { 0, 0|A(ALIAS)|A(COND_CTI), { 0 } }
529 /* bne $src1,$src2,$disp16 */
532 "bne", "bne", SYN (8), FMT (8), 0xb0100000,
533 { 0, 0|A(COND_CTI), { 0 } }
538 "bra8", "bra", SYN (6), FMT (6), 0x7f00,
539 { 0, 0|A(RELAX_BRA)|A(RELAXABLE)|A(UNCOND_CTI), { 0 } }
544 "bra8.s", "bra.s", SYN (6), FMT (6), 0x7f00,
545 { 0, 0|A(ALIAS)|A(UNCOND_CTI), { 0 } }
550 "bra24", "bra", SYN (7), FMT (7), 0xff000000,
551 { 0, 0|A(RELAX_BRA)|A(RELAX)|A(UNCOND_CTI), { 0 } }
556 "bra24.l", "bra.l", SYN (7), FMT (7), 0xff000000,
557 { 0, 0|A(ALIAS)|A(UNCOND_CTI), { 0 } }
559 /* cmp $src1,$src2 */
562 "cmp", "cmp", SYN (10), FMT (10), 0x40,
565 /* cmpi $src2,$simm16 */
568 "cmpi", "cmpi", SYN (11), FMT (11), 0x80400000,
571 /* cmpu $src1,$src2 */
574 "cmpu", "cmpu", SYN (10), FMT (10), 0x50,
577 /* cmpui $src2,$uimm16 */
580 "cmpui", "cmpui", SYN (12), FMT (12), 0x80500000,
586 "div", "div", SYN (0), FMT (13), 0x90000000,
592 "divu", "divu", SYN (0), FMT (13), 0x90100000,
598 "rem", "rem", SYN (0), FMT (13), 0x90200000,
604 "remu", "remu", SYN (0), FMT (13), 0x90300000,
610 "jl", "jl", SYN (13), FMT (14), 0x1ec0,
611 { 0, 0|A(FILL_SLOT)|A(UNCOND_CTI), { 0 } }
616 "jmp", "jmp", SYN (13), FMT (14), 0x1fc0,
617 { 0, 0|A(UNCOND_CTI), { 0 } }
622 "ld", "ld", SYN (14), FMT (0), 0x20c0,
628 "ld-2", "ld", SYN (15), FMT (0), 0x20c0,
629 { 0, 0|A(ALIAS), { 0 } }
631 /* ld $dr,@($slo16,$sr) */
634 "ld-d", "ld", SYN (16), FMT (1), 0xa0c00000,
637 /* ld $dr,@($sr,$slo16) */
640 "ld-d2", "ld", SYN (17), FMT (1), 0xa0c00000,
641 { 0, 0|A(ALIAS), { 0 } }
646 "ldb", "ldb", SYN (14), FMT (0), 0x2080,
652 "ldb-2", "ldb", SYN (15), FMT (0), 0x2080,
653 { 0, 0|A(ALIAS), { 0 } }
655 /* ldb $dr,@($slo16,$sr) */
658 "ldb-d", "ldb", SYN (16), FMT (1), 0xa0800000,
661 /* ldb $dr,@($sr,$slo16) */
664 "ldb-d2", "ldb", SYN (17), FMT (1), 0xa0800000,
665 { 0, 0|A(ALIAS), { 0 } }
670 "ldh", "ldh", SYN (14), FMT (0), 0x20a0,
676 "ldh-2", "ldh", SYN (15), FMT (0), 0x20a0,
677 { 0, 0|A(ALIAS), { 0 } }
679 /* ldh $dr,@($slo16,$sr) */
682 "ldh-d", "ldh", SYN (16), FMT (1), 0xa0a00000,
685 /* ldh $dr,@($sr,$slo16) */
688 "ldh-d2", "ldh", SYN (17), FMT (1), 0xa0a00000,
689 { 0, 0|A(ALIAS), { 0 } }
694 "ldub", "ldub", SYN (14), FMT (0), 0x2090,
697 /* ldub $dr,@($sr) */
700 "ldub-2", "ldub", SYN (15), FMT (0), 0x2090,
701 { 0, 0|A(ALIAS), { 0 } }
703 /* ldub $dr,@($slo16,$sr) */
706 "ldub-d", "ldub", SYN (16), FMT (1), 0xa0900000,
709 /* ldub $dr,@($sr,$slo16) */
712 "ldub-d2", "ldub", SYN (17), FMT (1), 0xa0900000,
713 { 0, 0|A(ALIAS), { 0 } }
718 "lduh", "lduh", SYN (14), FMT (0), 0x20b0,
721 /* lduh $dr,@($sr) */
724 "lduh-2", "lduh", SYN (15), FMT (0), 0x20b0,
725 { 0, 0|A(ALIAS), { 0 } }
727 /* lduh $dr,@($slo16,$sr) */
730 "lduh-d", "lduh", SYN (16), FMT (1), 0xa0b00000,
733 /* lduh $dr,@($sr,$slo16) */
736 "lduh-d2", "lduh", SYN (17), FMT (1), 0xa0b00000,
737 { 0, 0|A(ALIAS), { 0 } }
742 "ld-plus", "ld", SYN (18), FMT (0), 0x20e0,
745 /* ld24 $dr,$uimm24 */
748 "ld24", "ld24", SYN (19), FMT (15), 0xe0000000,
754 "ldi8", "ldi", SYN (4), FMT (4), 0x6000,
757 /* ldi8 $dr,$simm8 */
760 "ldi8a", "ldi8", SYN (4), FMT (4), 0x6000,
761 { 0, 0|A(ALIAS), { 0 } }
766 "ldi16", "ldi", SYN (20), FMT (16), 0x90f00000,
769 /* ldi16 $dr,$slo16 */
772 "ldi16a", "ldi16", SYN (20), FMT (16), 0x90f00000,
773 { 0, 0|A(ALIAS), { 0 } }
778 "lock", "lock", SYN (14), FMT (0), 0x20d0,
781 /* machi $src1,$src2 */
784 "machi", "machi", SYN (10), FMT (10), 0x3040,
787 /* maclo $src1,$src2 */
790 "maclo", "maclo", SYN (10), FMT (10), 0x3050,
793 /* macwhi $src1,$src2 */
796 "macwhi", "macwhi", SYN (10), FMT (10), 0x3060,
799 /* macwlo $src1,$src2 */
802 "macwlo", "macwlo", SYN (10), FMT (10), 0x3070,
808 "mul", "mul", SYN (0), FMT (0), 0x1060,
811 /* mulhi $src1,$src2 */
814 "mulhi", "mulhi", SYN (10), FMT (10), 0x3000,
817 /* mullo $src1,$src2 */
820 "mullo", "mullo", SYN (10), FMT (10), 0x3010,
823 /* mulwhi $src1,$src2 */
826 "mulwhi", "mulwhi", SYN (10), FMT (10), 0x3020,
829 /* mulwlo $src1,$src2 */
832 "mulwlo", "mulwlo", SYN (10), FMT (10), 0x3030,
838 "mv", "mv", SYN (0), FMT (0), 0x1080,
844 "mvfachi", "mvfachi", SYN (21), FMT (17), 0x50f0,
850 "mvfaclo", "mvfaclo", SYN (21), FMT (17), 0x50f1,
856 "mvfacmi", "mvfacmi", SYN (21), FMT (17), 0x50f2,
862 "mvfc", "mvfc", SYN (22), FMT (18), 0x1090,
868 "mvtachi", "mvtachi", SYN (23), FMT (19), 0x5070,
874 "mvtaclo", "mvtaclo", SYN (23), FMT (19), 0x5071,
880 "mvtc", "mvtc", SYN (24), FMT (20), 0x10a0,
886 "neg", "neg", SYN (0), FMT (0), 0x30,
892 "nop", "nop", SYN (25), FMT (21), 0x7000,
898 "not", "not", SYN (0), FMT (0), 0xb0,
904 "rac", "rac", SYN (25), FMT (21), 0x5090,
910 "rach", "rach", SYN (25), FMT (21), 0x5080,
916 "rte", "rte", SYN (25), FMT (21), 0x10d6,
917 { 0, 0|A(UNCOND_CTI), { 0 } }
922 "seth", "seth", SYN (26), FMT (22), 0xd0c00000,
928 "sll", "sll", SYN (0), FMT (0), 0x1040,
931 /* sll3 $dr,$sr,$simm16 */
934 "sll3", "sll3", SYN (5), FMT (5), 0x90c00000,
937 /* slli $dr,$uimm5 */
940 "slli", "slli", SYN (27), FMT (23), 0x5040,
946 "sra", "sra", SYN (0), FMT (0), 0x1020,
949 /* sra3 $dr,$sr,$simm16 */
952 "sra3", "sra3", SYN (5), FMT (5), 0x90a00000,
955 /* srai $dr,$uimm5 */
958 "srai", "srai", SYN (27), FMT (23), 0x5020,
964 "srl", "srl", SYN (0), FMT (0), 0x1000,
967 /* srl3 $dr,$sr,$simm16 */
970 "srl3", "srl3", SYN (5), FMT (5), 0x90800000,
973 /* srli $dr,$uimm5 */
976 "srli", "srli", SYN (27), FMT (23), 0x5000,
979 /* st $src1,@$src2 */
982 "st", "st", SYN (28), FMT (10), 0x2040,
985 /* st $src1,@($src2) */
988 "st-2", "st", SYN (29), FMT (10), 0x2040,
989 { 0, 0|A(ALIAS), { 0 } }
991 /* st $src1,@($slo16,$src2) */
994 "st-d", "st", SYN (30), FMT (24), 0xa0400000,
997 /* st $src1,@($src2,$slo16) */
1000 "st-d2", "st", SYN (31), FMT (24), 0xa0400000,
1001 { 0, 0|A(ALIAS), { 0 } }
1003 /* stb $src1,@$src2 */
1006 "stb", "stb", SYN (28), FMT (10), 0x2000,
1009 /* stb $src1,@($src2) */
1012 "stb-2", "stb", SYN (29), FMT (10), 0x2000,
1013 { 0, 0|A(ALIAS), { 0 } }
1015 /* stb $src1,@($slo16,$src2) */
1018 "stb-d", "stb", SYN (30), FMT (24), 0xa0000000,
1021 /* stb $src1,@($src2,$slo16) */
1024 "stb-d2", "stb", SYN (31), FMT (24), 0xa0000000,
1025 { 0, 0|A(ALIAS), { 0 } }
1027 /* sth $src1,@$src2 */
1030 "sth", "sth", SYN (28), FMT (10), 0x2020,
1033 /* sth $src1,@($src2) */
1036 "sth-2", "sth", SYN (29), FMT (10), 0x2020,
1037 { 0, 0|A(ALIAS), { 0 } }
1039 /* sth $src1,@($slo16,$src2) */
1042 "sth-d", "sth", SYN (30), FMT (24), 0xa0200000,
1045 /* sth $src1,@($src2,$slo16) */
1048 "sth-d2", "sth", SYN (31), FMT (24), 0xa0200000,
1049 { 0, 0|A(ALIAS), { 0 } }
1051 /* st $src1,@+$src2 */
1054 "st-plus", "st", SYN (32), FMT (10), 0x2060,
1057 /* st $src1,@-$src2 */
1060 "st-minus", "st", SYN (33), FMT (10), 0x2070,
1066 "sub", "sub", SYN (0), FMT (0), 0x20,
1072 "subv", "subv", SYN (0), FMT (0), 0x0,
1078 "subx", "subx", SYN (0), FMT (0), 0x10,
1084 "trap", "trap", SYN (34), FMT (25), 0x10f0,
1085 { 0, 0|A(FILL_SLOT)|A(UNCOND_CTI), { 0 } }
1087 /* unlock $src1,@$src2 */
1090 "unlock", "unlock", SYN (28), FMT (10), 0x2050,
1096 "push", "push", SYN (23), FMT (19), 0x207f,
1097 { 0, 0|A(ALIAS), { 0 } }
1102 "pop", "pop", SYN (21), FMT (17), 0x20ef,
1103 { 0, 0|A(ALIAS), { 0 } }
1111 CGEN_INSN_TABLE m32r_cgen_insn_table =
1113 & m32r_cgen_insn_table_entries[0],
1117 m32r_cgen_asm_hash_insn, CGEN_ASM_HASH_SIZE,
1118 m32r_cgen_dis_hash_insn, CGEN_DIS_HASH_SIZE
1121 /* The hash functions are recorded here to help keep assembler code out of
1122 the disassembler and vice versa. */
1125 m32r_cgen_asm_hash_insn (insn)
1128 return CGEN_ASM_HASH (insn);
1132 m32r_cgen_dis_hash_insn (buf, value)
1134 unsigned long value;
1136 return CGEN_DIS_HASH (buf, value);
1139 CGEN_OPCODE_DATA m32r_cgen_opcode_data =
1141 & m32r_cgen_hw_entries[0],
1142 & m32r_cgen_insn_table,
1146 m32r_cgen_init_tables (mach)
1151 /* Main entry point for stuffing values in cgen_fields. */
1154 m32r_cgen_set_operand (opindex, valuep, fields)
1156 const long * valuep;
1157 CGEN_FIELDS * fields;
1161 case M32R_OPERAND_SR :
1162 fields->f_r2 = * valuep;
1164 case M32R_OPERAND_DR :
1165 fields->f_r1 = * valuep;
1167 case M32R_OPERAND_SRC1 :
1168 fields->f_r1 = * valuep;
1170 case M32R_OPERAND_SRC2 :
1171 fields->f_r2 = * valuep;
1173 case M32R_OPERAND_SCR :
1174 fields->f_r2 = * valuep;
1176 case M32R_OPERAND_DCR :
1177 fields->f_r1 = * valuep;
1179 case M32R_OPERAND_SIMM8 :
1180 fields->f_simm8 = * valuep;
1182 case M32R_OPERAND_SIMM16 :
1183 fields->f_simm16 = * valuep;
1185 case M32R_OPERAND_UIMM4 :
1186 fields->f_uimm4 = * valuep;
1188 case M32R_OPERAND_UIMM5 :
1189 fields->f_uimm5 = * valuep;
1191 case M32R_OPERAND_UIMM16 :
1192 fields->f_uimm16 = * valuep;
1194 case M32R_OPERAND_HI16 :
1195 fields->f_hi16 = * valuep;
1197 case M32R_OPERAND_SLO16 :
1198 fields->f_simm16 = * valuep;
1200 case M32R_OPERAND_ULO16 :
1201 fields->f_uimm16 = * valuep;
1203 case M32R_OPERAND_UIMM24 :
1204 fields->f_uimm24 = * valuep;
1206 case M32R_OPERAND_DISP8 :
1207 fields->f_disp8 = * valuep;
1209 case M32R_OPERAND_DISP16 :
1210 fields->f_disp16 = * valuep;
1212 case M32R_OPERAND_DISP24 :
1213 fields->f_disp24 = * valuep;
1217 fprintf (stderr, "Unrecognized field %d while setting operand.\n",
1223 /* Main entry point for getting values from cgen_fields. */
1226 m32r_cgen_get_operand (opindex, fields)
1228 const CGEN_FIELDS * fields;
1234 case M32R_OPERAND_SR :
1235 value = fields->f_r2;
1237 case M32R_OPERAND_DR :
1238 value = fields->f_r1;
1240 case M32R_OPERAND_SRC1 :
1241 value = fields->f_r1;
1243 case M32R_OPERAND_SRC2 :
1244 value = fields->f_r2;
1246 case M32R_OPERAND_SCR :
1247 value = fields->f_r2;
1249 case M32R_OPERAND_DCR :
1250 value = fields->f_r1;
1252 case M32R_OPERAND_SIMM8 :
1253 value = fields->f_simm8;
1255 case M32R_OPERAND_SIMM16 :
1256 value = fields->f_simm16;
1258 case M32R_OPERAND_UIMM4 :
1259 value = fields->f_uimm4;
1261 case M32R_OPERAND_UIMM5 :
1262 value = fields->f_uimm5;
1264 case M32R_OPERAND_UIMM16 :
1265 value = fields->f_uimm16;
1267 case M32R_OPERAND_HI16 :
1268 value = fields->f_hi16;
1270 case M32R_OPERAND_SLO16 :
1271 value = fields->f_simm16;
1273 case M32R_OPERAND_ULO16 :
1274 value = fields->f_uimm16;
1276 case M32R_OPERAND_UIMM24 :
1277 value = fields->f_uimm24;
1279 case M32R_OPERAND_DISP8 :
1280 value = fields->f_disp8;
1282 case M32R_OPERAND_DISP16 :
1283 value = fields->f_disp16;
1285 case M32R_OPERAND_DISP24 :
1286 value = fields->f_disp24;
1290 fprintf (stderr, "Unrecognized field %d while getting operand.\n",