1 /* Generic opcode table support for targets using CGEN. -*- C -*-
2 CGEN: Cpu tools GENerator
4 This file is used to generate m32r-opc.c.
6 Copyright (C) 1998 Free Software Foundation, Inc.
8 This file is part of the GNU Binutils and GDB, the GNU debugger.
10 This program is free software; you can redistribute it and/or modify
11 it under the terms of the GNU General Public License as published by
12 the Free Software Foundation; either version 2, or (at your option)
15 This program is distributed in the hope that it will be useful,
16 but WITHOUT ANY WARRANTY; without even the implied warranty of
17 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 GNU General Public License for more details.
20 You should have received a copy of the GNU General Public License
21 along with this program; if not, write to the Free Software
22 Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */
27 #include "libiberty.h"
32 /* Look up instruction INSN_VALUE and extract its fields.
33 If non-null INSN is the insn table entry.
34 Otherwise INSN_VALUE is examined to compute it.
35 LENGTH is the bit length of INSN_VALUE if known, otherwise 0.
36 ALIAS_P is non-zero if alias insns are to be included in the search.
37 The result a pointer to the insn table entry, or NULL if the instruction
41 m32r_cgen_lookup_insn (insn, insn_value, length, fields, alias_p)
42 const CGEN_INSN *insn;
43 cgen_insn_t insn_value;
51 const CGEN_INSN_LIST *insn_list;
60 if (cgen_current_endian == CGEN_ENDIAN_BIG)
61 bfd_putb16 (insn_value, buf);
63 bfd_putl16 (insn_value, buf);
66 if (cgen_current_endian == CGEN_ENDIAN_BIG)
67 bfd_putb32 (insn_value, buf);
69 bfd_putl32 (insn_value, buf);
75 abort (); /* FIXME: unfinished */
78 /* The instructions are stored in hash lists.
79 Pick the first one and keep trying until we find the right one. */
81 insn_list = CGEN_DIS_LOOKUP_INSN (buf, insn_value);
82 while (insn_list != NULL)
84 insn = insn_list->insn;
87 || ! CGEN_INSN_ATTR (insn, CGEN_INSN_ALIAS))
89 /* Basic bit mask must be correct. */
90 /* ??? May wish to allow target to defer this check until the
92 if ((insn_value & CGEN_INSN_MASK (insn)) == CGEN_INSN_VALUE (insn))
94 length = (*CGEN_EXTRACT_FN (insn)) (insn, NULL, insn_value, fields);
100 insn_list = CGEN_DIS_NEXT_INSN (insn_list);
105 /* Sanity check: can't pass an alias insn if ! alias_p. */
107 && CGEN_INSN_ATTR (insn, CGEN_INSN_ALIAS))
110 length = (*CGEN_EXTRACT_FN (insn)) (insn, NULL, insn_value, fields);
118 /* Fill in the operand instances used by insn INSN_VALUE.
119 If non-null INS is the insn table entry.
120 Otherwise INSN_VALUE is examined to compute it.
121 LENGTH is the number of bits in INSN_VALUE if known, otherwise 0.
122 INDICES is a pointer to a buffer of MAX_OPERANDS ints to be filled in.
123 The result a pointer to the insn table entry, or NULL if the instruction
124 wasn't recognized. */
127 m32r_cgen_get_insn_operands (insn, insn_value, length, indices)
128 const CGEN_INSN *insn;
129 cgen_insn_t insn_value;
134 const CGEN_OPERAND_INSTANCE *opinst;
137 /* FIXME: ALIAS insns are in transition from being record in the insn table
138 to being recorded separately as macros. They don't have semantic code
139 so they can't be used here. Thus we currently always ignore the INSN
141 insn = m32r_cgen_lookup_insn (NULL, insn_value, length, &fields, 0);
145 for (i = 0, opinst = CGEN_INSN_OPERANDS (insn);
146 CGEN_OPERAND_INSTANCE_TYPE (opinst) != CGEN_OPERAND_INSTANCE_END;
149 const CGEN_OPERAND *op = CGEN_OPERAND_INSTANCE_OPERAND (opinst);
151 indices[i] = CGEN_OPERAND_INSTANCE_INDEX (opinst);
153 indices[i] = m32r_cgen_get_operand (CGEN_OPERAND_INDEX (op), &fields);
160 static const CGEN_ATTR_ENTRY MACH_attr[] =
162 { "m32r", MACH_M32R },
163 /* start-sanitize-m32rx */
164 { "m32rx", MACH_M32RX },
165 /* end-sanitize-m32rx */
170 static const CGEN_ATTR_ENTRY WRITE_LR_attr[] =
172 { "NO", WRITE_LR_NO },
173 { "YES", WRITE_LR_YES },
177 static const CGEN_ATTR_ENTRY WRITE_SRC_attr[] =
179 { "NO", WRITE_SRC_NO },
180 { "YES", WRITE_SRC_YES },
184 /* start-sanitize-m32rx */
185 static const CGEN_ATTR_ENTRY PIPE_attr[] =
187 { "NONE", PIPE_NONE },
194 /* end-sanitize-m32rx */
195 const CGEN_ATTR_TABLE m32r_cgen_operand_attr_table[] =
197 { "ABS-ADDR", NULL },
199 { "NEGATIVE", NULL },
201 { "PCREL-ADDR", NULL },
204 { "SIGN-OPT", NULL },
205 { "UNSIGNED", NULL },
209 const CGEN_ATTR_TABLE m32r_cgen_insn_attr_table[] =
211 { "MACH", & MACH_attr[0] },
212 /* start-sanitize-m32rx */
213 { "PIPE", & PIPE_attr[0] },
214 /* end-sanitize-m32rx */
215 { "WRITE_LR", & WRITE_LR_attr[0] },
216 { "WRITE_SRC", & WRITE_SRC_attr[0] },
218 { "COND-CTI", NULL },
219 { "FILL-SLOT", NULL },
220 { "PARALLEL", NULL },
222 { "RELAXABLE", NULL },
223 { "UNCOND-CTI", NULL },
227 CGEN_KEYWORD_ENTRY m32r_cgen_opval_h_gr_entries[] =
250 CGEN_KEYWORD m32r_cgen_opval_h_gr =
252 & m32r_cgen_opval_h_gr_entries[0],
256 CGEN_KEYWORD_ENTRY m32r_cgen_opval_h_cr_entries[] =
272 CGEN_KEYWORD m32r_cgen_opval_h_cr =
274 & m32r_cgen_opval_h_cr_entries[0],
278 /* start-sanitize-m32rx */
279 CGEN_KEYWORD_ENTRY m32r_cgen_opval_h_accums_entries[] =
285 CGEN_KEYWORD m32r_cgen_opval_h_accums =
287 & m32r_cgen_opval_h_accums_entries[0],
291 /* end-sanitize-m32rx */
293 /* The hardware table. */
295 #define HW_ENT(n) m32r_cgen_hw_entries[n]
296 static const CGEN_HW_ENTRY m32r_cgen_hw_entries[] =
298 { HW_H_PC, & HW_ENT (HW_H_PC + 1), "h-pc", CGEN_ASM_KEYWORD, (PTR) 0 },
299 { HW_H_MEMORY, & HW_ENT (HW_H_MEMORY + 1), "h-memory", CGEN_ASM_KEYWORD, (PTR) 0 },
300 { HW_H_SINT, & HW_ENT (HW_H_SINT + 1), "h-sint", CGEN_ASM_KEYWORD, (PTR) 0 },
301 { HW_H_UINT, & HW_ENT (HW_H_UINT + 1), "h-uint", CGEN_ASM_KEYWORD, (PTR) 0 },
302 { HW_H_ADDR, & HW_ENT (HW_H_ADDR + 1), "h-addr", CGEN_ASM_KEYWORD, (PTR) 0 },
303 { HW_H_IADDR, & HW_ENT (HW_H_IADDR + 1), "h-iaddr", CGEN_ASM_KEYWORD, (PTR) 0 },
304 { HW_H_HI16, & HW_ENT (HW_H_HI16 + 1), "h-hi16", CGEN_ASM_KEYWORD, (PTR) 0 },
305 { HW_H_SLO16, & HW_ENT (HW_H_SLO16 + 1), "h-slo16", CGEN_ASM_KEYWORD, (PTR) 0 },
306 { HW_H_ULO16, & HW_ENT (HW_H_ULO16 + 1), "h-ulo16", CGEN_ASM_KEYWORD, (PTR) 0 },
307 { HW_H_GR, & HW_ENT (HW_H_GR + 1), "h-gr", CGEN_ASM_KEYWORD, (PTR) & m32r_cgen_opval_h_gr },
308 { HW_H_CR, & HW_ENT (HW_H_CR + 1), "h-cr", CGEN_ASM_KEYWORD, (PTR) & m32r_cgen_opval_h_cr },
309 { HW_H_ACCUM, & HW_ENT (HW_H_ACCUM + 1), "h-accum", CGEN_ASM_KEYWORD, (PTR) 0 },
310 /* start-sanitize-m32rx */
311 { HW_H_ACCUMS, & HW_ENT (HW_H_ACCUMS + 1), "h-accums", CGEN_ASM_KEYWORD, (PTR) & m32r_cgen_opval_h_accums },
312 /* end-sanitize-m32rx */
313 /* start-sanitize-m32rx */
314 { HW_H_ABORT, & HW_ENT (HW_H_ABORT + 1), "h-abort", CGEN_ASM_KEYWORD, (PTR) 0 },
315 /* end-sanitize-m32rx */
316 { HW_H_COND, & HW_ENT (HW_H_COND + 1), "h-cond", CGEN_ASM_KEYWORD, (PTR) 0 },
317 { HW_H_SM, & HW_ENT (HW_H_SM + 1), "h-sm", CGEN_ASM_KEYWORD, (PTR) 0 },
318 { HW_H_BSM, & HW_ENT (HW_H_BSM + 1), "h-bsm", CGEN_ASM_KEYWORD, (PTR) 0 },
319 { HW_H_IE, & HW_ENT (HW_H_IE + 1), "h-ie", CGEN_ASM_KEYWORD, (PTR) 0 },
320 { HW_H_BIE, & HW_ENT (HW_H_BIE + 1), "h-bie", CGEN_ASM_KEYWORD, (PTR) 0 },
321 { HW_H_BCOND, & HW_ENT (HW_H_BCOND + 1), "h-bcond", CGEN_ASM_KEYWORD, (PTR) 0 },
322 { HW_H_BPC, & HW_ENT (HW_H_BPC + 1), "h-bpc", CGEN_ASM_KEYWORD, (PTR) 0 },
326 /* The operand table. */
328 #define OP_ENT(op) m32r_cgen_operand_table[CONCAT2 (M32R_OPERAND_,op)]
329 const CGEN_OPERAND m32r_cgen_operand_table[MAX_OPERANDS] =
331 /* pc: program counter */
332 { "pc", & HW_ENT (HW_H_PC), 0, 0,
333 { 0, 0|(1<<CGEN_OPERAND_FAKE)|(1<<CGEN_OPERAND_PC), { 0 } } },
334 /* sr: source register */
335 { "sr", & HW_ENT (HW_H_GR), 12, 4,
336 { 0, 0|(1<<CGEN_OPERAND_UNSIGNED), { 0 } } },
337 /* dr: destination register */
338 { "dr", & HW_ENT (HW_H_GR), 4, 4,
339 { 0, 0|(1<<CGEN_OPERAND_UNSIGNED), { 0 } } },
340 /* src1: source register 1 */
341 { "src1", & HW_ENT (HW_H_GR), 4, 4,
342 { 0, 0|(1<<CGEN_OPERAND_UNSIGNED), { 0 } } },
343 /* src2: source register 2 */
344 { "src2", & HW_ENT (HW_H_GR), 12, 4,
345 { 0, 0|(1<<CGEN_OPERAND_UNSIGNED), { 0 } } },
346 /* scr: source control register */
347 { "scr", & HW_ENT (HW_H_CR), 12, 4,
348 { 0, 0|(1<<CGEN_OPERAND_UNSIGNED), { 0 } } },
349 /* dcr: destination control register */
350 { "dcr", & HW_ENT (HW_H_CR), 4, 4,
351 { 0, 0|(1<<CGEN_OPERAND_UNSIGNED), { 0 } } },
352 /* simm8: 8 bit signed immediate */
353 { "simm8", & HW_ENT (HW_H_SINT), 8, 8,
355 /* simm16: 16 bit signed immediate */
356 { "simm16", & HW_ENT (HW_H_SINT), 16, 16,
358 /* uimm4: 4 bit trap number */
359 { "uimm4", & HW_ENT (HW_H_UINT), 12, 4,
360 { 0, 0|(1<<CGEN_OPERAND_UNSIGNED), { 0 } } },
361 /* uimm5: 5 bit shift count */
362 { "uimm5", & HW_ENT (HW_H_UINT), 11, 5,
363 { 0, 0|(1<<CGEN_OPERAND_UNSIGNED), { 0 } } },
364 /* uimm16: 16 bit unsigned immediate */
365 { "uimm16", & HW_ENT (HW_H_UINT), 16, 16,
366 { 0, 0|(1<<CGEN_OPERAND_UNSIGNED), { 0 } } },
367 /* start-sanitize-m32rx */
368 /* imm1: 1 bit immediate */
369 { "imm1", & HW_ENT (HW_H_UINT), 15, 1,
370 { 0, 0|(1<<CGEN_OPERAND_UNSIGNED), { 0 } } },
371 /* end-sanitize-m32rx */
372 /* start-sanitize-m32rx */
373 /* accd: accumulator destination register */
374 { "accd", & HW_ENT (HW_H_ACCUMS), 4, 2,
375 { 0, 0|(1<<CGEN_OPERAND_UNSIGNED), { 0 } } },
376 /* end-sanitize-m32rx */
377 /* start-sanitize-m32rx */
378 /* accs: accumulator source register */
379 { "accs", & HW_ENT (HW_H_ACCUMS), 12, 2,
380 { 0, 0|(1<<CGEN_OPERAND_UNSIGNED), { 0 } } },
381 /* end-sanitize-m32rx */
382 /* start-sanitize-m32rx */
383 /* acc: accumulator reg (d) */
384 { "acc", & HW_ENT (HW_H_ACCUMS), 8, 1,
385 { 0, 0|(1<<CGEN_OPERAND_UNSIGNED), { 0 } } },
386 /* end-sanitize-m32rx */
387 /* hi16: high 16 bit immediate, sign optional */
388 { "hi16", & HW_ENT (HW_H_HI16), 16, 16,
389 { 0, 0|(1<<CGEN_OPERAND_SIGN_OPT)|(1<<CGEN_OPERAND_UNSIGNED), { 0 } } },
390 /* slo16: 16 bit signed immediate, for low() */
391 { "slo16", & HW_ENT (HW_H_SLO16), 16, 16,
393 /* ulo16: 16 bit unsigned immediate, for low() */
394 { "ulo16", & HW_ENT (HW_H_ULO16), 16, 16,
395 { 0, 0|(1<<CGEN_OPERAND_UNSIGNED), { 0 } } },
396 /* uimm24: 24 bit address */
397 { "uimm24", & HW_ENT (HW_H_ADDR), 8, 24,
398 { 0, 0|(1<<CGEN_OPERAND_RELOC)|(1<<CGEN_OPERAND_ABS_ADDR)|(1<<CGEN_OPERAND_UNSIGNED), { 0 } } },
399 /* disp8: 8 bit displacement */
400 { "disp8", & HW_ENT (HW_H_IADDR), 8, 8,
401 { 0, 0|(1<<CGEN_OPERAND_RELAX)|(1<<CGEN_OPERAND_RELOC)|(1<<CGEN_OPERAND_PCREL_ADDR), { 0 } } },
402 /* disp16: 16 bit displacement */
403 { "disp16", & HW_ENT (HW_H_IADDR), 16, 16,
404 { 0, 0|(1<<CGEN_OPERAND_RELOC)|(1<<CGEN_OPERAND_PCREL_ADDR), { 0 } } },
405 /* disp24: 24 bit displacement */
406 { "disp24", & HW_ENT (HW_H_IADDR), 8, 24,
407 { 0, 0|(1<<CGEN_OPERAND_RELAX)|(1<<CGEN_OPERAND_RELOC)|(1<<CGEN_OPERAND_PCREL_ADDR), { 0 } } },
408 /* condbit: condition bit */
409 { "condbit", & HW_ENT (HW_H_COND), 0, 0,
410 { 0, 0|(1<<CGEN_OPERAND_FAKE), { 0 } } },
411 /* accum: accumulator */
412 { "accum", & HW_ENT (HW_H_ACCUM), 0, 0,
413 { 0, 0|(1<<CGEN_OPERAND_FAKE), { 0 } } },
414 /* start-sanitize-m32rx */
415 /* abort-parallel-execution: abort parallel execution */
416 { "abort-parallel-execution", & HW_ENT (HW_H_ABORT), 0, 0,
417 { 0, 0|(1<<CGEN_OPERAND_FAKE), { 0 } } },
418 /* end-sanitize-m32rx */
421 /* Operand references. */
423 #define INPUT CGEN_OPERAND_INSTANCE_INPUT
424 #define OUTPUT CGEN_OPERAND_INSTANCE_OUTPUT
426 static const CGEN_OPERAND_INSTANCE fmt_0_add_ops[] = {
427 { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0 },
428 { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SR), 0 },
429 { OUTPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0 },
433 static const CGEN_OPERAND_INSTANCE fmt_1_add3_ops[] = {
434 { INPUT, & HW_ENT (HW_H_SLO16), CGEN_MODE_HI, & OP_ENT (SLO16), 0 },
435 { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SR), 0 },
436 { OUTPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0 },
440 static const CGEN_OPERAND_INSTANCE fmt_2_and3_ops[] = {
441 { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SR), 0 },
442 { INPUT, & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (UIMM16), 0 },
443 { OUTPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0 },
447 static const CGEN_OPERAND_INSTANCE fmt_3_or3_ops[] = {
448 { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SR), 0 },
449 { INPUT, & HW_ENT (HW_H_ULO16), CGEN_MODE_UHI, & OP_ENT (ULO16), 0 },
450 { OUTPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0 },
454 static const CGEN_OPERAND_INSTANCE fmt_4_addi_ops[] = {
455 { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0 },
456 { INPUT, & HW_ENT (HW_H_SINT), CGEN_MODE_SI, & OP_ENT (SIMM8), 0 },
457 { OUTPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0 },
461 static const CGEN_OPERAND_INSTANCE fmt_5_addv_ops[] = {
462 { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0 },
463 { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SR), 0 },
464 { OUTPUT, & HW_ENT (HW_H_COND), CGEN_MODE_UBI, 0, 0 },
465 { OUTPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0 },
469 static const CGEN_OPERAND_INSTANCE fmt_6_addv3_ops[] = {
470 { INPUT, & HW_ENT (HW_H_SINT), CGEN_MODE_SI, & OP_ENT (SIMM16), 0 },
471 { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SR), 0 },
472 { OUTPUT, & HW_ENT (HW_H_COND), CGEN_MODE_UBI, 0, 0 },
473 { OUTPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0 },
477 static const CGEN_OPERAND_INSTANCE fmt_7_addx_ops[] = {
478 { INPUT, & HW_ENT (HW_H_COND), CGEN_MODE_UBI, 0, 0 },
479 { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0 },
480 { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SR), 0 },
481 { OUTPUT, & HW_ENT (HW_H_COND), CGEN_MODE_UBI, 0, 0 },
482 { OUTPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0 },
486 static const CGEN_OPERAND_INSTANCE fmt_8_bc8_ops[] = {
487 { INPUT, & HW_ENT (HW_H_COND), CGEN_MODE_UBI, 0, 0 },
488 { INPUT, & HW_ENT (HW_H_IADDR), CGEN_MODE_VM, & OP_ENT (DISP8), 0 },
492 static const CGEN_OPERAND_INSTANCE fmt_10_bc24_ops[] = {
493 { INPUT, & HW_ENT (HW_H_COND), CGEN_MODE_UBI, 0, 0 },
494 { INPUT, & HW_ENT (HW_H_IADDR), CGEN_MODE_VM, & OP_ENT (DISP24), 0 },
498 static const CGEN_OPERAND_INSTANCE fmt_12_beq_ops[] = {
499 { INPUT, & HW_ENT (HW_H_IADDR), CGEN_MODE_VM, & OP_ENT (DISP16), 0 },
500 { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC1), 0 },
501 { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC2), 0 },
505 static const CGEN_OPERAND_INSTANCE fmt_13_beqz_ops[] = {
506 { INPUT, & HW_ENT (HW_H_IADDR), CGEN_MODE_VM, & OP_ENT (DISP16), 0 },
507 { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC2), 0 },
511 static const CGEN_OPERAND_INSTANCE fmt_14_bl8_ops[] = {
512 { INPUT, & HW_ENT (HW_H_IADDR), CGEN_MODE_VM, & OP_ENT (DISP8), 0 },
513 { INPUT, & HW_ENT (HW_H_PC), CGEN_MODE_USI, 0, 0 },
514 { OUTPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 14 },
518 static const CGEN_OPERAND_INSTANCE fmt_15_bl24_ops[] = {
519 { INPUT, & HW_ENT (HW_H_IADDR), CGEN_MODE_VM, & OP_ENT (DISP24), 0 },
520 { INPUT, & HW_ENT (HW_H_PC), CGEN_MODE_USI, 0, 0 },
521 { OUTPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 14 },
525 static const CGEN_OPERAND_INSTANCE fmt_16_bcl8_ops[] = {
526 { INPUT, & HW_ENT (HW_H_COND), CGEN_MODE_UBI, 0, 0 },
527 { INPUT, & HW_ENT (HW_H_IADDR), CGEN_MODE_VM, & OP_ENT (DISP8), 0 },
528 { INPUT, & HW_ENT (HW_H_PC), CGEN_MODE_USI, 0, 0 },
529 { OUTPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 14 },
533 static const CGEN_OPERAND_INSTANCE fmt_17_bcl24_ops[] = {
534 { INPUT, & HW_ENT (HW_H_COND), CGEN_MODE_UBI, 0, 0 },
535 { INPUT, & HW_ENT (HW_H_IADDR), CGEN_MODE_VM, & OP_ENT (DISP24), 0 },
536 { INPUT, & HW_ENT (HW_H_PC), CGEN_MODE_USI, 0, 0 },
537 { OUTPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 14 },
541 static const CGEN_OPERAND_INSTANCE fmt_18_bra8_ops[] = {
542 { INPUT, & HW_ENT (HW_H_IADDR), CGEN_MODE_VM, & OP_ENT (DISP8), 0 },
546 static const CGEN_OPERAND_INSTANCE fmt_19_bra24_ops[] = {
547 { INPUT, & HW_ENT (HW_H_IADDR), CGEN_MODE_VM, & OP_ENT (DISP24), 0 },
551 static const CGEN_OPERAND_INSTANCE fmt_20_cmp_ops[] = {
552 { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC1), 0 },
553 { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC2), 0 },
554 { OUTPUT, & HW_ENT (HW_H_COND), CGEN_MODE_UBI, 0, 0 },
558 static const CGEN_OPERAND_INSTANCE fmt_21_cmpi_ops[] = {
559 { INPUT, & HW_ENT (HW_H_SINT), CGEN_MODE_SI, & OP_ENT (SIMM16), 0 },
560 { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC2), 0 },
561 { OUTPUT, & HW_ENT (HW_H_COND), CGEN_MODE_UBI, 0, 0 },
565 static const CGEN_OPERAND_INSTANCE fmt_22_cmpui_ops[] = {
566 { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC2), 0 },
567 { INPUT, & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (UIMM16), 0 },
568 { OUTPUT, & HW_ENT (HW_H_COND), CGEN_MODE_UBI, 0, 0 },
572 static const CGEN_OPERAND_INSTANCE fmt_23_cmpz_ops[] = {
573 { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC2), 0 },
574 { OUTPUT, & HW_ENT (HW_H_COND), CGEN_MODE_UBI, 0, 0 },
578 static const CGEN_OPERAND_INSTANCE fmt_24_div_ops[] = {
579 { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0 },
580 { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SR), 0 },
581 { OUTPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0 },
585 static const CGEN_OPERAND_INSTANCE fmt_25_jc_ops[] = {
586 { INPUT, & HW_ENT (HW_H_COND), CGEN_MODE_UBI, 0, 0 },
587 { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SR), 0 },
591 static const CGEN_OPERAND_INSTANCE fmt_26_jl_ops[] = {
592 { INPUT, & HW_ENT (HW_H_PC), CGEN_MODE_USI, 0, 0 },
593 { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SR), 0 },
594 { OUTPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 14 },
598 static const CGEN_OPERAND_INSTANCE fmt_27_jmp_ops[] = {
599 { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SR), 0 },
603 static const CGEN_OPERAND_INSTANCE fmt_28_ld_ops[] = {
604 { INPUT, & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0 },
605 { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SR), 0 },
606 { OUTPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0 },
610 static const CGEN_OPERAND_INSTANCE fmt_30_ld_d_ops[] = {
611 { INPUT, & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0 },
612 { INPUT, & HW_ENT (HW_H_SLO16), CGEN_MODE_HI, & OP_ENT (SLO16), 0 },
613 { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SR), 0 },
614 { OUTPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0 },
618 static const CGEN_OPERAND_INSTANCE fmt_32_ldb_ops[] = {
619 { INPUT, & HW_ENT (HW_H_MEMORY), CGEN_MODE_QI, 0, 0 },
620 { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SR), 0 },
621 { OUTPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0 },
625 static const CGEN_OPERAND_INSTANCE fmt_33_ldb_d_ops[] = {
626 { INPUT, & HW_ENT (HW_H_MEMORY), CGEN_MODE_QI, 0, 0 },
627 { INPUT, & HW_ENT (HW_H_SLO16), CGEN_MODE_HI, & OP_ENT (SLO16), 0 },
628 { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SR), 0 },
629 { OUTPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0 },
633 static const CGEN_OPERAND_INSTANCE fmt_34_ldh_ops[] = {
634 { INPUT, & HW_ENT (HW_H_MEMORY), CGEN_MODE_HI, 0, 0 },
635 { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SR), 0 },
636 { OUTPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0 },
640 static const CGEN_OPERAND_INSTANCE fmt_35_ldh_d_ops[] = {
641 { INPUT, & HW_ENT (HW_H_MEMORY), CGEN_MODE_HI, 0, 0 },
642 { INPUT, & HW_ENT (HW_H_SLO16), CGEN_MODE_HI, & OP_ENT (SLO16), 0 },
643 { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SR), 0 },
644 { OUTPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0 },
648 static const CGEN_OPERAND_INSTANCE fmt_36_ld_plus_ops[] = {
649 { INPUT, & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0 },
650 { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SR), 0 },
651 { OUTPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0 },
652 { OUTPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SR), 0 },
656 static const CGEN_OPERAND_INSTANCE fmt_37_ld24_ops[] = {
657 { INPUT, & HW_ENT (HW_H_ADDR), CGEN_MODE_VM, & OP_ENT (UIMM24), 0 },
658 { OUTPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0 },
662 static const CGEN_OPERAND_INSTANCE fmt_38_ldi8_ops[] = {
663 { INPUT, & HW_ENT (HW_H_SINT), CGEN_MODE_SI, & OP_ENT (SIMM8), 0 },
664 { OUTPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0 },
668 static const CGEN_OPERAND_INSTANCE fmt_39_ldi16_ops[] = {
669 { INPUT, & HW_ENT (HW_H_SLO16), CGEN_MODE_HI, & OP_ENT (SLO16), 0 },
670 { OUTPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0 },
674 static const CGEN_OPERAND_INSTANCE fmt_40_lock_ops[] = {
675 { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0 },
676 { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SR), 0 },
680 static const CGEN_OPERAND_INSTANCE fmt_41_machi_ops[] = {
681 { INPUT, & HW_ENT (HW_H_ACCUM), CGEN_MODE_DI, 0, 0 },
682 { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC1), 0 },
683 { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC2), 0 },
684 { OUTPUT, & HW_ENT (HW_H_ACCUM), CGEN_MODE_DI, 0, 0 },
688 static const CGEN_OPERAND_INSTANCE fmt_42_machi_a_ops[] = {
689 { INPUT, & HW_ENT (HW_H_ACCUMS), CGEN_MODE_DI, & OP_ENT (ACC), 0 },
690 { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC1), 0 },
691 { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC2), 0 },
692 { OUTPUT, & HW_ENT (HW_H_ACCUMS), CGEN_MODE_DI, & OP_ENT (ACC), 0 },
696 static const CGEN_OPERAND_INSTANCE fmt_43_mulhi_ops[] = {
697 { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC1), 0 },
698 { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC2), 0 },
699 { OUTPUT, & HW_ENT (HW_H_ACCUM), CGEN_MODE_DI, 0, 0 },
703 static const CGEN_OPERAND_INSTANCE fmt_44_mulhi_a_ops[] = {
704 { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC1), 0 },
705 { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC2), 0 },
706 { OUTPUT, & HW_ENT (HW_H_ACCUMS), CGEN_MODE_DI, & OP_ENT (ACC), 0 },
710 static const CGEN_OPERAND_INSTANCE fmt_45_mv_ops[] = {
711 { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SR), 0 },
712 { OUTPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0 },
716 static const CGEN_OPERAND_INSTANCE fmt_46_mvfachi_ops[] = {
717 { INPUT, & HW_ENT (HW_H_ACCUM), CGEN_MODE_DI, 0, 0 },
718 { OUTPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0 },
722 static const CGEN_OPERAND_INSTANCE fmt_47_mvfachi_a_ops[] = {
723 { INPUT, & HW_ENT (HW_H_ACCUMS), CGEN_MODE_DI, & OP_ENT (ACCS), 0 },
724 { OUTPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0 },
728 static const CGEN_OPERAND_INSTANCE fmt_48_mvfc_ops[] = {
729 { INPUT, & HW_ENT (HW_H_CR), CGEN_MODE_SI, & OP_ENT (SCR), 0 },
730 { OUTPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0 },
734 static const CGEN_OPERAND_INSTANCE fmt_49_mvtachi_ops[] = {
735 { INPUT, & HW_ENT (HW_H_ACCUM), CGEN_MODE_DI, 0, 0 },
736 { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC1), 0 },
737 { OUTPUT, & HW_ENT (HW_H_ACCUM), CGEN_MODE_DI, 0, 0 },
741 static const CGEN_OPERAND_INSTANCE fmt_50_mvtachi_a_ops[] = {
742 { INPUT, & HW_ENT (HW_H_ACCUMS), CGEN_MODE_DI, & OP_ENT (ACCS), 0 },
743 { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC1), 0 },
744 { OUTPUT, & HW_ENT (HW_H_ACCUMS), CGEN_MODE_DI, & OP_ENT (ACCS), 0 },
748 static const CGEN_OPERAND_INSTANCE fmt_51_mvtc_ops[] = {
749 { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SR), 0 },
750 { OUTPUT, & HW_ENT (HW_H_CR), CGEN_MODE_SI, & OP_ENT (DCR), 0 },
754 static const CGEN_OPERAND_INSTANCE fmt_53_rac_ops[] = {
755 { INPUT, & HW_ENT (HW_H_ACCUM), CGEN_MODE_DI, 0, 0 },
756 { OUTPUT, & HW_ENT (HW_H_ACCUM), CGEN_MODE_DI, 0, 0 },
760 static const CGEN_OPERAND_INSTANCE fmt_54_rac_d_ops[] = {
761 { INPUT, & HW_ENT (HW_H_ACCUM), CGEN_MODE_DI, 0, 0 },
762 { OUTPUT, & HW_ENT (HW_H_ACCUMS), CGEN_MODE_DI, & OP_ENT (ACCD), 0 },
766 static const CGEN_OPERAND_INSTANCE fmt_55_rac_ds_ops[] = {
767 { INPUT, & HW_ENT (HW_H_ACCUMS), CGEN_MODE_DI, & OP_ENT (ACCS), 0 },
768 { OUTPUT, & HW_ENT (HW_H_ACCUMS), CGEN_MODE_DI, & OP_ENT (ACCD), 0 },
772 static const CGEN_OPERAND_INSTANCE fmt_56_rac_dsi_ops[] = {
773 { INPUT, & HW_ENT (HW_H_ACCUMS), CGEN_MODE_DI, & OP_ENT (ACCS), 0 },
774 { INPUT, & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (IMM1), 0 },
775 { OUTPUT, & HW_ENT (HW_H_ACCUMS), CGEN_MODE_DI, & OP_ENT (ACCD), 0 },
779 static const CGEN_OPERAND_INSTANCE fmt_57_rte_ops[] = {
780 { INPUT, & HW_ENT (HW_H_BCOND), CGEN_MODE_VM, 0, 0 },
781 { INPUT, & HW_ENT (HW_H_BIE), CGEN_MODE_VM, 0, 0 },
782 { INPUT, & HW_ENT (HW_H_BPC), CGEN_MODE_VM, 0, 0 },
783 { INPUT, & HW_ENT (HW_H_BSM), CGEN_MODE_VM, 0, 0 },
784 { OUTPUT, & HW_ENT (HW_H_COND), CGEN_MODE_UBI, 0, 0 },
785 { OUTPUT, & HW_ENT (HW_H_PC), CGEN_MODE_USI, 0, 0 },
786 { OUTPUT, & HW_ENT (HW_H_IE), CGEN_MODE_VM, 0, 0 },
787 { OUTPUT, & HW_ENT (HW_H_SM), CGEN_MODE_VM, 0, 0 },
791 static const CGEN_OPERAND_INSTANCE fmt_58_seth_ops[] = {
792 { INPUT, & HW_ENT (HW_H_HI16), CGEN_MODE_UHI, & OP_ENT (HI16), 0 },
793 { OUTPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0 },
797 static const CGEN_OPERAND_INSTANCE fmt_59_sll3_ops[] = {
798 { INPUT, & HW_ENT (HW_H_SINT), CGEN_MODE_SI, & OP_ENT (SIMM16), 0 },
799 { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SR), 0 },
800 { OUTPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0 },
804 static const CGEN_OPERAND_INSTANCE fmt_60_slli_ops[] = {
805 { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0 },
806 { INPUT, & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (UIMM5), 0 },
807 { OUTPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0 },
811 static const CGEN_OPERAND_INSTANCE fmt_61_st_ops[] = {
812 { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC1), 0 },
813 { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC2), 0 },
814 { OUTPUT, & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0 },
818 static const CGEN_OPERAND_INSTANCE fmt_63_st_d_ops[] = {
819 { INPUT, & HW_ENT (HW_H_SLO16), CGEN_MODE_HI, & OP_ENT (SLO16), 0 },
820 { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC1), 0 },
821 { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC2), 0 },
822 { OUTPUT, & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0 },
826 static const CGEN_OPERAND_INSTANCE fmt_65_stb_ops[] = {
827 { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC1), 0 },
828 { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC2), 0 },
829 { OUTPUT, & HW_ENT (HW_H_MEMORY), CGEN_MODE_QI, 0, 0 },
833 static const CGEN_OPERAND_INSTANCE fmt_66_stb_d_ops[] = {
834 { INPUT, & HW_ENT (HW_H_SLO16), CGEN_MODE_HI, & OP_ENT (SLO16), 0 },
835 { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC1), 0 },
836 { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC2), 0 },
837 { OUTPUT, & HW_ENT (HW_H_MEMORY), CGEN_MODE_QI, 0, 0 },
841 static const CGEN_OPERAND_INSTANCE fmt_67_sth_ops[] = {
842 { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC1), 0 },
843 { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC2), 0 },
844 { OUTPUT, & HW_ENT (HW_H_MEMORY), CGEN_MODE_HI, 0, 0 },
848 static const CGEN_OPERAND_INSTANCE fmt_68_sth_d_ops[] = {
849 { INPUT, & HW_ENT (HW_H_SLO16), CGEN_MODE_HI, & OP_ENT (SLO16), 0 },
850 { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC1), 0 },
851 { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC2), 0 },
852 { OUTPUT, & HW_ENT (HW_H_MEMORY), CGEN_MODE_HI, 0, 0 },
856 static const CGEN_OPERAND_INSTANCE fmt_69_st_plus_ops[] = {
857 { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC1), 0 },
858 { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC2), 0 },
859 { OUTPUT, & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0 },
860 { OUTPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC2), 0 },
864 static const CGEN_OPERAND_INSTANCE fmt_70_trap_ops[] = {
865 { INPUT, & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (UIMM4), 0 },
869 static const CGEN_OPERAND_INSTANCE fmt_71_unlock_ops[] = {
870 { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC1), 0 },
871 { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC2), 0 },
875 static const CGEN_OPERAND_INSTANCE fmt_74_satb_ops[] = {
876 { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC2), 0 },
877 { OUTPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0 },
881 static const CGEN_OPERAND_INSTANCE fmt_75_sat_ops[] = {
882 { INPUT, & HW_ENT (HW_H_COND), CGEN_MODE_UBI, 0, 0 },
883 { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC2), 0 },
884 { OUTPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0 },
888 static const CGEN_OPERAND_INSTANCE fmt_76_sadd_ops[] = {
889 { INPUT, & HW_ENT (HW_H_ACCUMS), CGEN_MODE_DI, 0, 0 },
890 { INPUT, & HW_ENT (HW_H_ACCUMS), CGEN_MODE_DI, 0, 1 },
891 { OUTPUT, & HW_ENT (HW_H_ACCUMS), CGEN_MODE_DI, 0, 0 },
895 static const CGEN_OPERAND_INSTANCE fmt_77_macwu1_ops[] = {
896 { INPUT, & HW_ENT (HW_H_ACCUMS), CGEN_MODE_DI, 0, 1 },
897 { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC1), 0 },
898 { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC2), 0 },
899 { OUTPUT, & HW_ENT (HW_H_ACCUMS), CGEN_MODE_DI, 0, 1 },
903 static const CGEN_OPERAND_INSTANCE fmt_78_mulwu1_ops[] = {
904 { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC1), 0 },
905 { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC2), 0 },
906 { OUTPUT, & HW_ENT (HW_H_ACCUMS), CGEN_MODE_DI, 0, 1 },
910 static const CGEN_OPERAND_INSTANCE fmt_79_sc_ops[] = {
911 { INPUT, & HW_ENT (HW_H_COND), CGEN_MODE_UBI, 0, 0 },
912 { OUTPUT, & HW_ENT (HW_H_ABORT), CGEN_MODE_UBI, 0, 0 },
919 #define OP 1 /* syntax value for mnemonic */
921 static const CGEN_SYNTAX syntax_table[] =
924 /* 0 */ { OP, ' ', 130, ',', 129, 0 },
925 /* <op> $dr,$sr,#$slo16 */
926 /* 1 */ { OP, ' ', 130, ',', 129, ',', '#', 145, 0 },
927 /* <op> $dr,$sr,$slo16 */
928 /* 2 */ { OP, ' ', 130, ',', 129, ',', 145, 0 },
929 /* <op> $dr,$sr,#$uimm16 */
930 /* 3 */ { OP, ' ', 130, ',', 129, ',', '#', 139, 0 },
931 /* <op> $dr,$sr,$uimm16 */
932 /* 4 */ { OP, ' ', 130, ',', 129, ',', 139, 0 },
933 /* <op> $dr,$sr,#$ulo16 */
934 /* 5 */ { OP, ' ', 130, ',', 129, ',', '#', 146, 0 },
935 /* <op> $dr,$sr,$ulo16 */
936 /* 6 */ { OP, ' ', 130, ',', 129, ',', 146, 0 },
937 /* <op> $dr,#$simm8 */
938 /* 7 */ { OP, ' ', 130, ',', '#', 135, 0 },
939 /* <op> $dr,$simm8 */
940 /* 8 */ { OP, ' ', 130, ',', 135, 0 },
941 /* <op> $dr,$sr,#$simm16 */
942 /* 9 */ { OP, ' ', 130, ',', 129, ',', '#', 136, 0 },
943 /* <op> $dr,$sr,$simm16 */
944 /* 10 */ { OP, ' ', 130, ',', 129, ',', 136, 0 },
946 /* 11 */ { OP, ' ', 148, 0 },
948 /* 12 */ { OP, ' ', 150, 0 },
949 /* <op> $src1,$src2,$disp16 */
950 /* 13 */ { OP, ' ', 131, ',', 132, ',', 149, 0 },
951 /* <op> $src2,$disp16 */
952 /* 14 */ { OP, ' ', 132, ',', 149, 0 },
953 /* <op> $src1,$src2 */
954 /* 15 */ { OP, ' ', 131, ',', 132, 0 },
955 /* <op> $src2,#$simm16 */
956 /* 16 */ { OP, ' ', 132, ',', '#', 136, 0 },
957 /* <op> $src2,$simm16 */
958 /* 17 */ { OP, ' ', 132, ',', 136, 0 },
959 /* <op> $src2,#$uimm16 */
960 /* 18 */ { OP, ' ', 132, ',', '#', 139, 0 },
961 /* <op> $src2,$uimm16 */
962 /* 19 */ { OP, ' ', 132, ',', 139, 0 },
964 /* 20 */ { OP, ' ', 132, 0 },
966 /* 21 */ { OP, ' ', 129, 0 },
968 /* 22 */ { OP, ' ', 130, ',', '@', 129, 0 },
969 /* <op> $dr,@($sr) */
970 /* 23 */ { OP, ' ', 130, ',', '@', '(', 129, ')', 0 },
971 /* <op> $dr,@($slo16,$sr) */
972 /* 24 */ { OP, ' ', 130, ',', '@', '(', 145, ',', 129, ')', 0 },
973 /* <op> $dr,@($sr,$slo16) */
974 /* 25 */ { OP, ' ', 130, ',', '@', '(', 129, ',', 145, ')', 0 },
976 /* 26 */ { OP, ' ', 130, ',', '@', 129, '+', 0 },
977 /* <op> $dr,#$uimm24 */
978 /* 27 */ { OP, ' ', 130, ',', '#', 147, 0 },
979 /* <op> $dr,$uimm24 */
980 /* 28 */ { OP, ' ', 130, ',', 147, 0 },
981 /* <op> $dr,$slo16 */
982 /* 29 */ { OP, ' ', 130, ',', 145, 0 },
983 /* <op> $src1,$src2,$acc */
984 /* 30 */ { OP, ' ', 131, ',', 132, ',', 143, 0 },
986 /* 31 */ { OP, ' ', 130, 0 },
988 /* 32 */ { OP, ' ', 130, ',', 142, 0 },
990 /* 33 */ { OP, ' ', 130, ',', 133, 0 },
992 /* 34 */ { OP, ' ', 131, 0 },
993 /* <op> $src1,$accs */
994 /* 35 */ { OP, ' ', 131, ',', 142, 0 },
996 /* 36 */ { OP, ' ', 129, ',', 134, 0 },
1000 /* 38 */ { OP, ' ', 141, 0 },
1001 /* <op> $accd,$accs */
1002 /* 39 */ { OP, ' ', 141, ',', 142, 0 },
1003 /* <op> $accd,$accs,#$imm1 */
1004 /* 40 */ { OP, ' ', 141, ',', 142, ',', '#', 140, 0 },
1005 /* <op> $dr,#$hi16 */
1006 /* 41 */ { OP, ' ', 130, ',', '#', 144, 0 },
1007 /* <op> $dr,$hi16 */
1008 /* 42 */ { OP, ' ', 130, ',', 144, 0 },
1009 /* <op> $dr,#$uimm5 */
1010 /* 43 */ { OP, ' ', 130, ',', '#', 138, 0 },
1011 /* <op> $dr,$uimm5 */
1012 /* 44 */ { OP, ' ', 130, ',', 138, 0 },
1013 /* <op> $src1,@$src2 */
1014 /* 45 */ { OP, ' ', 131, ',', '@', 132, 0 },
1015 /* <op> $src1,@($src2) */
1016 /* 46 */ { OP, ' ', 131, ',', '@', '(', 132, ')', 0 },
1017 /* <op> $src1,@($slo16,$src2) */
1018 /* 47 */ { OP, ' ', 131, ',', '@', '(', 145, ',', 132, ')', 0 },
1019 /* <op> $src1,@($src2,$slo16) */
1020 /* 48 */ { OP, ' ', 131, ',', '@', '(', 132, ',', 145, ')', 0 },
1021 /* <op> $src1,@+$src2 */
1022 /* 49 */ { OP, ' ', 131, ',', '@', '+', 132, 0 },
1023 /* <op> $src1,@-$src2 */
1024 /* 50 */ { OP, ' ', 131, ',', '@', '-', 132, 0 },
1026 /* 51 */ { OP, ' ', '#', 137, 0 },
1028 /* 52 */ { OP, ' ', 137, 0 },
1029 /* <op> $dr,$src2 */
1030 /* 53 */ { OP, ' ', 130, ',', 132, 0 },
1035 static const CGEN_FORMAT format_table[] =
1037 /* (f-op1 #)(f-r1 dr)(f-op2 #)(f-r2 sr)(dr SI)(sr SI)(dr SI) */
1038 /* 0 */ { 16, 16, 0xf0f0 },
1039 /* (f-op1 #)(f-r1 dr)(f-op2 #)(f-r2 sr)(f-simm16 slo16)(slo16 HI)(sr SI)(dr SI) */
1040 /* 1 */ { 32, 32, 0xf0f00000 },
1041 /* (f-op1 #)(f-r1 dr)(f-op2 #)(f-r2 sr)(f-uimm16 uimm16)(sr SI)(uimm16 USI)(dr SI) */
1042 /* 2 */ { 32, 32, 0xf0f00000 },
1043 /* (f-op1 #)(f-r1 dr)(f-op2 #)(f-r2 sr)(f-uimm16 ulo16)(sr SI)(ulo16 UHI)(dr SI) */
1044 /* 3 */ { 32, 32, 0xf0f00000 },
1045 /* (f-op1 #)(f-r1 dr)(f-simm8 simm8)(dr SI)(simm8 SI)(dr SI) */
1046 /* 4 */ { 16, 16, 0xf000 },
1047 /* (f-op1 #)(f-r1 dr)(f-op2 #)(f-r2 sr)(dr SI)(sr SI)(condbit UBI)(dr SI) */
1048 /* 5 */ { 16, 16, 0xf0f0 },
1049 /* (f-op1 #)(f-r1 dr)(f-op2 #)(f-r2 sr)(f-simm16 simm16)(simm16 SI)(sr SI)(condbit UBI)(dr SI) */
1050 /* 6 */ { 32, 32, 0xf0f00000 },
1051 /* (f-op1 #)(f-r1 dr)(f-op2 #)(f-r2 sr)(condbit UBI)(dr SI)(sr SI)(condbit UBI)(dr SI) */
1052 /* 7 */ { 16, 16, 0xf0f0 },
1053 /* (f-op1 #)(f-r1 #)(f-disp8 disp8)(condbit UBI)(disp8 VM) */
1054 /* 8 */ { 16, 16, 0xff00 },
1055 /* (f-op1 #)(f-r1 #)(f-disp8 disp8) */
1056 /* 9 */ { 16, 16, 0xff00 },
1057 /* (f-op1 #)(f-r1 #)(f-disp24 disp24)(condbit UBI)(disp24 VM) */
1058 /* 10 */ { 32, 32, 0xff000000 },
1059 /* (f-op1 #)(f-r1 #)(f-disp24 disp24) */
1060 /* 11 */ { 32, 32, 0xff000000 },
1061 /* (f-op1 #)(f-r1 src1)(f-op2 #)(f-r2 src2)(f-disp16 disp16)(disp16 VM)(src1 SI)(src2 SI) */
1062 /* 12 */ { 32, 32, 0xf0f00000 },
1063 /* (f-op1 #)(f-r1 #)(f-op2 #)(f-r2 src2)(f-disp16 disp16)(disp16 VM)(src2 SI) */
1064 /* 13 */ { 32, 32, 0xfff00000 },
1065 /* (f-op1 #)(f-r1 #)(f-disp8 disp8)(disp8 VM)(pc USI)(h-gr-14 SI) */
1066 /* 14 */ { 16, 16, 0xff00 },
1067 /* (f-op1 #)(f-r1 #)(f-disp24 disp24)(disp24 VM)(pc USI)(h-gr-14 SI) */
1068 /* 15 */ { 32, 32, 0xff000000 },
1069 /* (f-op1 #)(f-r1 #)(f-disp8 disp8)(condbit UBI)(disp8 VM)(pc USI)(h-gr-14 SI) */
1070 /* 16 */ { 16, 16, 0xff00 },
1071 /* (f-op1 #)(f-r1 #)(f-disp24 disp24)(condbit UBI)(disp24 VM)(pc USI)(h-gr-14 SI) */
1072 /* 17 */ { 32, 32, 0xff000000 },
1073 /* (f-op1 #)(f-r1 #)(f-disp8 disp8)(disp8 VM) */
1074 /* 18 */ { 16, 16, 0xff00 },
1075 /* (f-op1 #)(f-r1 #)(f-disp24 disp24)(disp24 VM) */
1076 /* 19 */ { 32, 32, 0xff000000 },
1077 /* (f-op1 #)(f-r1 src1)(f-op2 #)(f-r2 src2)(src1 SI)(src2 SI)(condbit UBI) */
1078 /* 20 */ { 16, 16, 0xf0f0 },
1079 /* (f-op1 #)(f-r1 #)(f-op2 #)(f-r2 src2)(f-simm16 simm16)(simm16 SI)(src2 SI)(condbit UBI) */
1080 /* 21 */ { 32, 32, 0xfff00000 },
1081 /* (f-op1 #)(f-r1 #)(f-op2 #)(f-r2 src2)(f-uimm16 uimm16)(src2 SI)(uimm16 USI)(condbit UBI) */
1082 /* 22 */ { 32, 32, 0xfff00000 },
1083 /* (f-op1 #)(f-r1 #)(f-op2 #)(f-r2 src2)(src2 SI)(condbit UBI) */
1084 /* 23 */ { 16, 16, 0xfff0 },
1085 /* (f-op1 #)(f-r1 dr)(f-op2 #)(f-r2 sr)(f-simm16 #)(dr SI)(sr SI)(dr SI) */
1086 /* 24 */ { 32, 32, 0xf0f0ffff },
1087 /* (f-op1 #)(f-r1 #)(f-op2 #)(f-r2 sr)(condbit UBI)(sr SI) */
1088 /* 25 */ { 16, 16, 0xfff0 },
1089 /* (f-op1 #)(f-r1 #)(f-op2 #)(f-r2 sr)(pc USI)(sr SI)(h-gr-14 SI) */
1090 /* 26 */ { 16, 16, 0xfff0 },
1091 /* (f-op1 #)(f-r1 #)(f-op2 #)(f-r2 sr)(sr SI) */
1092 /* 27 */ { 16, 16, 0xfff0 },
1093 /* (f-op1 #)(f-r1 dr)(f-op2 #)(f-r2 sr)(h-memory-sr SI)(sr SI)(dr SI) */
1094 /* 28 */ { 16, 16, 0xf0f0 },
1095 /* (f-op1 #)(f-r1 dr)(f-op2 #)(f-r2 sr) */
1096 /* 29 */ { 16, 16, 0xf0f0 },
1097 /* (f-op1 #)(f-r1 dr)(f-op2 #)(f-r2 sr)(f-simm16 slo16)(h-memory-add-WI-sr-slo16 SI)(slo16 HI)(sr SI)(dr SI) */
1098 /* 30 */ { 32, 32, 0xf0f00000 },
1099 /* (f-op1 #)(f-r1 dr)(f-op2 #)(f-r2 sr)(f-simm16 slo16) */
1100 /* 31 */ { 32, 32, 0xf0f00000 },
1101 /* (f-op1 #)(f-r1 dr)(f-op2 #)(f-r2 sr)(h-memory-sr QI)(sr SI)(dr SI) */
1102 /* 32 */ { 16, 16, 0xf0f0 },
1103 /* (f-op1 #)(f-r1 dr)(f-op2 #)(f-r2 sr)(f-simm16 slo16)(h-memory-add-WI-sr-slo16 QI)(slo16 HI)(sr SI)(dr SI) */
1104 /* 33 */ { 32, 32, 0xf0f00000 },
1105 /* (f-op1 #)(f-r1 dr)(f-op2 #)(f-r2 sr)(h-memory-sr HI)(sr SI)(dr SI) */
1106 /* 34 */ { 16, 16, 0xf0f0 },
1107 /* (f-op1 #)(f-r1 dr)(f-op2 #)(f-r2 sr)(f-simm16 slo16)(h-memory-add-WI-sr-slo16 HI)(slo16 HI)(sr SI)(dr SI) */
1108 /* 35 */ { 32, 32, 0xf0f00000 },
1109 /* (f-op1 #)(f-r1 dr)(f-op2 #)(f-r2 sr)(h-memory-sr SI)(sr SI)(dr SI)(sr SI) */
1110 /* 36 */ { 16, 16, 0xf0f0 },
1111 /* (f-op1 #)(f-r1 dr)(f-uimm24 uimm24)(uimm24 VM)(dr SI) */
1112 /* 37 */ { 32, 32, 0xf0000000 },
1113 /* (f-op1 #)(f-r1 dr)(f-simm8 simm8)(simm8 SI)(dr SI) */
1114 /* 38 */ { 16, 16, 0xf000 },
1115 /* (f-op1 #)(f-r1 dr)(f-op2 #)(f-r2 #)(f-simm16 slo16)(slo16 HI)(dr SI) */
1116 /* 39 */ { 32, 32, 0xf0ff0000 },
1117 /* (f-op1 #)(f-r1 dr)(f-op2 #)(f-r2 sr)(dr SI)(sr SI) */
1118 /* 40 */ { 16, 16, 0xf0f0 },
1119 /* (f-op1 #)(f-r1 src1)(f-op2 #)(f-r2 src2)(accum DI)(src1 SI)(src2 SI)(accum DI) */
1120 /* 41 */ { 16, 16, 0xf0f0 },
1121 /* (f-op1 #)(f-r1 src1)(f-acc acc)(f-op23 #)(f-r2 src2)(acc DI)(src1 SI)(src2 SI)(acc DI) */
1122 /* 42 */ { 16, 16, 0xf070 },
1123 /* (f-op1 #)(f-r1 src1)(f-op2 #)(f-r2 src2)(src1 SI)(src2 SI)(accum DI) */
1124 /* 43 */ { 16, 16, 0xf0f0 },
1125 /* (f-op1 #)(f-r1 src1)(f-acc acc)(f-op23 #)(f-r2 src2)(src1 SI)(src2 SI)(acc DI) */
1126 /* 44 */ { 16, 16, 0xf070 },
1127 /* (f-op1 #)(f-r1 dr)(f-op2 #)(f-r2 sr)(sr SI)(dr SI) */
1128 /* 45 */ { 16, 16, 0xf0f0 },
1129 /* (f-op1 #)(f-r1 dr)(f-op2 #)(f-r2 #)(accum DI)(dr SI) */
1130 /* 46 */ { 16, 16, 0xf0ff },
1131 /* (f-op1 #)(f-r1 dr)(f-op2 #)(f-accs accs)(f-op3 #)(accs DI)(dr SI) */
1132 /* 47 */ { 16, 16, 0xf0f3 },
1133 /* (f-op1 #)(f-r1 dr)(f-op2 #)(f-r2 scr)(scr SI)(dr SI) */
1134 /* 48 */ { 16, 16, 0xf0f0 },
1135 /* (f-op1 #)(f-r1 src1)(f-op2 #)(f-r2 #)(accum DI)(src1 SI)(accum DI) */
1136 /* 49 */ { 16, 16, 0xf0ff },
1137 /* (f-op1 #)(f-r1 src1)(f-op2 #)(f-accs accs)(f-op3 #)(accs DI)(src1 SI)(accs DI) */
1138 /* 50 */ { 16, 16, 0xf0f3 },
1139 /* (f-op1 #)(f-r1 dcr)(f-op2 #)(f-r2 sr)(sr SI)(dcr SI) */
1140 /* 51 */ { 16, 16, 0xf0f0 },
1141 /* (f-op1 #)(f-r1 #)(f-op2 #)(f-r2 #) */
1142 /* 52 */ { 16, 16, 0xffff },
1143 /* (f-op1 #)(f-r1 #)(f-op2 #)(f-r2 #)(accum DI)(accum DI) */
1144 /* 53 */ { 16, 16, 0xffff },
1145 /* (f-op1 #)(f-accd accd)(f-bits67 #)(f-op2 #)(f-accs #)(f-bit14 #)(f-imm1 #)(accum DI)(accd DI) */
1146 /* 54 */ { 16, 16, 0xf3ff },
1147 /* (f-op1 #)(f-accd accd)(f-bits67 #)(f-op2 #)(f-accs accs)(f-bit14 #)(f-imm1 #)(accs DI)(accd DI) */
1148 /* 55 */ { 16, 16, 0xf3f3 },
1149 /* (f-op1 #)(f-accd accd)(f-bits67 #)(f-op2 #)(f-accs accs)(f-bit14 #)(f-imm1 imm1)(accs DI)(imm1 USI)(accd DI) */
1150 /* 56 */ { 16, 16, 0xf3f2 },
1151 /* (f-op1 #)(f-r1 #)(f-op2 #)(f-r2 #)(h-bcond-0 VM)(h-bie-0 VM)(h-bpc-0 VM)(h-bsm-0 VM)(condbit UBI)(pc USI)(h-ie-0 VM)(h-sm-0 VM) */
1152 /* 57 */ { 16, 16, 0xffff },
1153 /* (f-op1 #)(f-r1 dr)(f-op2 #)(f-r2 #)(f-hi16 hi16)(hi16 UHI)(dr SI) */
1154 /* 58 */ { 32, 32, 0xf0ff0000 },
1155 /* (f-op1 #)(f-r1 dr)(f-op2 #)(f-r2 sr)(f-simm16 simm16)(simm16 SI)(sr SI)(dr SI) */
1156 /* 59 */ { 32, 32, 0xf0f00000 },
1157 /* (f-op1 #)(f-r1 dr)(f-shift-op2 #)(f-uimm5 uimm5)(dr SI)(uimm5 USI)(dr SI) */
1158 /* 60 */ { 16, 16, 0xf0e0 },
1159 /* (f-op1 #)(f-r1 src1)(f-op2 #)(f-r2 src2)(src1 SI)(src2 SI)(h-memory-src2 SI) */
1160 /* 61 */ { 16, 16, 0xf0f0 },
1161 /* (f-op1 #)(f-r1 src1)(f-op2 #)(f-r2 src2) */
1162 /* 62 */ { 16, 16, 0xf0f0 },
1163 /* (f-op1 #)(f-r1 src1)(f-op2 #)(f-r2 src2)(f-simm16 slo16)(slo16 HI)(src1 SI)(src2 SI)(h-memory-add-WI-src2-slo16 SI) */
1164 /* 63 */ { 32, 32, 0xf0f00000 },
1165 /* (f-op1 #)(f-r1 src1)(f-op2 #)(f-r2 src2)(f-simm16 slo16) */
1166 /* 64 */ { 32, 32, 0xf0f00000 },
1167 /* (f-op1 #)(f-r1 src1)(f-op2 #)(f-r2 src2)(src1 SI)(src2 SI)(h-memory-src2 QI) */
1168 /* 65 */ { 16, 16, 0xf0f0 },
1169 /* (f-op1 #)(f-r1 src1)(f-op2 #)(f-r2 src2)(f-simm16 slo16)(slo16 HI)(src1 SI)(src2 SI)(h-memory-add-WI-src2-slo16 QI) */
1170 /* 66 */ { 32, 32, 0xf0f00000 },
1171 /* (f-op1 #)(f-r1 src1)(f-op2 #)(f-r2 src2)(src1 SI)(src2 SI)(h-memory-src2 HI) */
1172 /* 67 */ { 16, 16, 0xf0f0 },
1173 /* (f-op1 #)(f-r1 src1)(f-op2 #)(f-r2 src2)(f-simm16 slo16)(slo16 HI)(src1 SI)(src2 SI)(h-memory-add-WI-src2-slo16 HI) */
1174 /* 68 */ { 32, 32, 0xf0f00000 },
1175 /* (f-op1 #)(f-r1 src1)(f-op2 #)(f-r2 src2)(src1 SI)(src2 SI)(h-memory-src2 SI)(src2 SI) */
1176 /* 69 */ { 16, 16, 0xf0f0 },
1177 /* (f-op1 #)(f-r1 #)(f-op2 #)(f-uimm4 uimm4)(uimm4 USI) */
1178 /* 70 */ { 16, 16, 0xfff0 },
1179 /* (f-op1 #)(f-r1 src1)(f-op2 #)(f-r2 src2)(src1 SI)(src2 SI) */
1180 /* 71 */ { 16, 16, 0xf0f0 },
1181 /* (f-op1 #)(f-r1 src1)(f-op2 #)(f-r2 #) */
1182 /* 72 */ { 16, 16, 0xf0ff },
1183 /* (f-op1 #)(f-r1 dr)(f-op2 #)(f-r2 #) */
1184 /* 73 */ { 16, 16, 0xf0ff },
1185 /* (f-op1 #)(f-r1 dr)(f-op2 #)(f-r2 src2)(f-uimm16 #)(src2 SI)(dr SI) */
1186 /* 74 */ { 32, 32, 0xf0f0ffff },
1187 /* (f-op1 #)(f-r1 dr)(f-op2 #)(f-r2 src2)(f-uimm16 #)(condbit UBI)(src2 SI)(dr SI) */
1188 /* 75 */ { 32, 32, 0xf0f0ffff },
1189 /* (f-op1 #)(f-r1 #)(f-op2 #)(f-r2 #)(h-accums-0 DI)(h-accums-1 DI)(h-accums-0 DI) */
1190 /* 76 */ { 16, 16, 0xffff },
1191 /* (f-op1 #)(f-r1 src1)(f-op2 #)(f-r2 src2)(h-accums-1 DI)(src1 SI)(src2 SI)(h-accums-1 DI) */
1192 /* 77 */ { 16, 16, 0xf0f0 },
1193 /* (f-op1 #)(f-r1 src1)(f-op2 #)(f-r2 src2)(src1 SI)(src2 SI)(h-accums-1 DI) */
1194 /* 78 */ { 16, 16, 0xf0f0 },
1195 /* (f-op1 #)(f-r1 #)(f-op2 #)(f-r2 #)(condbit UBI)(abort-parallel-execution UBI) */
1196 /* 79 */ { 16, 16, 0xffff },
1199 #define A(a) (1 << CGEN_CAT3 (CGEN_INSN,_,a))
1200 #define SYN(n) (& syntax_table[n])
1201 #define FMT(n) (& format_table[n])
1203 /* The instruction table. */
1205 const CGEN_INSN m32r_cgen_insn_table_entries[MAX_INSNS] =
1207 /* null first entry, end of all hash chains */
1212 "add", "add", SYN (0), FMT (0), 0xa0,
1214 { 4, 0|A(PARALLEL), { (1<<MACH_M32R), PIPE_OS, WRITE_LR_NO, WRITE_SRC_NO } }
1216 /* add3 $dr,$sr,#$slo16 */
1219 "add3", "add3", SYN (1), FMT (1), 0x80a00000,
1220 & fmt_1_add3_ops[0],
1221 { 4, 0, { (1<<MACH_M32R), PIPE_NONE, WRITE_LR_NO, WRITE_SRC_NO } }
1223 /* add3 $dr,$sr,$slo16 */
1226 "add3.a", "add3", SYN (2), FMT (1), 0x80a00000,
1227 & fmt_1_add3_ops[0],
1228 { 4, 0|A(ALIAS), { (1<<MACH_M32R), PIPE_NONE, WRITE_LR_NO, WRITE_SRC_NO } }
1233 "and", "and", SYN (0), FMT (0), 0xc0,
1235 { 4, 0|A(PARALLEL), { (1<<MACH_M32R), PIPE_OS, WRITE_LR_NO, WRITE_SRC_NO } }
1237 /* and3 $dr,$sr,#$uimm16 */
1240 "and3", "and3", SYN (3), FMT (2), 0x80c00000,
1241 & fmt_2_and3_ops[0],
1242 { 4, 0, { (1<<MACH_M32R), PIPE_NONE, WRITE_LR_NO, WRITE_SRC_NO } }
1244 /* and3 $dr,$sr,$uimm16 */
1247 "and3.a", "and3", SYN (4), FMT (2), 0x80c00000,
1248 & fmt_2_and3_ops[0],
1249 { 4, 0|A(ALIAS), { (1<<MACH_M32R), PIPE_NONE, WRITE_LR_NO, WRITE_SRC_NO } }
1254 "or", "or", SYN (0), FMT (0), 0xe0,
1256 { 4, 0|A(PARALLEL), { (1<<MACH_M32R), PIPE_OS, WRITE_LR_NO, WRITE_SRC_NO } }
1258 /* or3 $dr,$sr,#$ulo16 */
1261 "or3", "or3", SYN (5), FMT (3), 0x80e00000,
1263 { 4, 0, { (1<<MACH_M32R), PIPE_NONE, WRITE_LR_NO, WRITE_SRC_NO } }
1265 /* or3 $dr,$sr,$ulo16 */
1268 "or3.a", "or3", SYN (6), FMT (3), 0x80e00000,
1270 { 4, 0|A(ALIAS), { (1<<MACH_M32R), PIPE_NONE, WRITE_LR_NO, WRITE_SRC_NO } }
1275 "xor", "xor", SYN (0), FMT (0), 0xd0,
1277 { 4, 0|A(PARALLEL), { (1<<MACH_M32R), PIPE_OS, WRITE_LR_NO, WRITE_SRC_NO } }
1279 /* xor3 $dr,$sr,#$uimm16 */
1282 "xor3", "xor3", SYN (3), FMT (2), 0x80d00000,
1283 & fmt_2_and3_ops[0],
1284 { 4, 0, { (1<<MACH_M32R), PIPE_NONE, WRITE_LR_NO, WRITE_SRC_NO } }
1286 /* xor3 $dr,$sr,$uimm16 */
1289 "xor3.a", "xor3", SYN (4), FMT (2), 0x80d00000,
1290 & fmt_2_and3_ops[0],
1291 { 4, 0|A(ALIAS), { (1<<MACH_M32R), PIPE_NONE, WRITE_LR_NO, WRITE_SRC_NO } }
1293 /* addi $dr,#$simm8 */
1296 "addi", "addi", SYN (7), FMT (4), 0x4000,
1297 & fmt_4_addi_ops[0],
1298 { 4, 0, { (1<<MACH_M32R), PIPE_OS, WRITE_LR_NO, WRITE_SRC_NO } }
1300 /* addi $dr,$simm8 */
1303 "addi.a", "addi", SYN (8), FMT (4), 0x4000,
1304 & fmt_4_addi_ops[0],
1305 { 4, 0|A(ALIAS), { (1<<MACH_M32R), PIPE_OS, WRITE_LR_NO, WRITE_SRC_NO } }
1310 "addv", "addv", SYN (0), FMT (5), 0x80,
1311 & fmt_5_addv_ops[0],
1312 { 4, 0, { (1<<MACH_M32R), PIPE_OS, WRITE_LR_NO, WRITE_SRC_NO } }
1314 /* addv3 $dr,$sr,#$simm16 */
1317 "addv3", "addv3", SYN (9), FMT (6), 0x80800000,
1318 & fmt_6_addv3_ops[0],
1319 { 4, 0, { (1<<MACH_M32R), PIPE_NONE, WRITE_LR_NO, WRITE_SRC_NO } }
1321 /* addv3 $dr,$sr,$simm16 */
1324 "addv3.a", "addv3", SYN (10), FMT (6), 0x80800000,
1325 & fmt_6_addv3_ops[0],
1326 { 4, 0|A(ALIAS), { (1<<MACH_M32R), PIPE_NONE, WRITE_LR_NO, WRITE_SRC_NO } }
1331 "addx", "addx", SYN (0), FMT (7), 0x90,
1332 & fmt_7_addx_ops[0],
1333 { 4, 0, { (1<<MACH_M32R), PIPE_OS, WRITE_LR_NO, WRITE_SRC_NO } }
1338 "bc8", "bc", SYN (11), FMT (8), 0x7c00,
1340 { 4, 0|A(RELAXABLE)|A(COND_CTI), { (1<<MACH_M32R), PIPE_O, WRITE_LR_NO, WRITE_SRC_NO } }
1345 "bc8.s", "bc.s", SYN (11), FMT (9), 0x7c00,
1347 { 4, 0|A(ALIAS)|A(COND_CTI), { (1<<MACH_M32R), PIPE_O, WRITE_LR_NO, WRITE_SRC_NO } }
1352 "bc24", "bc", SYN (12), FMT (10), 0xfc000000,
1353 & fmt_10_bc24_ops[0],
1354 { 4, 0|A(RELAX)|A(COND_CTI), { (1<<MACH_M32R), PIPE_NONE, WRITE_LR_NO, WRITE_SRC_NO } }
1359 "bc24.l", "bc.l", SYN (12), FMT (11), 0xfc000000,
1361 { 4, 0|A(ALIAS)|A(COND_CTI), { (1<<MACH_M32R), PIPE_NONE, WRITE_LR_NO, WRITE_SRC_NO } }
1363 /* beq $src1,$src2,$disp16 */
1366 "beq", "beq", SYN (13), FMT (12), 0xb0000000,
1367 & fmt_12_beq_ops[0],
1368 { 4, 0|A(COND_CTI), { (1<<MACH_M32R), PIPE_NONE, WRITE_LR_NO, WRITE_SRC_NO } }
1370 /* beqz $src2,$disp16 */
1373 "beqz", "beqz", SYN (14), FMT (13), 0xb0800000,
1374 & fmt_13_beqz_ops[0],
1375 { 4, 0|A(COND_CTI), { (1<<MACH_M32R), PIPE_NONE, WRITE_LR_NO, WRITE_SRC_NO } }
1377 /* bgez $src2,$disp16 */
1380 "bgez", "bgez", SYN (14), FMT (13), 0xb0b00000,
1381 & fmt_13_beqz_ops[0],
1382 { 4, 0|A(COND_CTI), { (1<<MACH_M32R), PIPE_NONE, WRITE_LR_NO, WRITE_SRC_NO } }
1384 /* bgtz $src2,$disp16 */
1387 "bgtz", "bgtz", SYN (14), FMT (13), 0xb0d00000,
1388 & fmt_13_beqz_ops[0],
1389 { 4, 0|A(COND_CTI), { (1<<MACH_M32R), PIPE_NONE, WRITE_LR_NO, WRITE_SRC_NO } }
1391 /* blez $src2,$disp16 */
1394 "blez", "blez", SYN (14), FMT (13), 0xb0c00000,
1395 & fmt_13_beqz_ops[0],
1396 { 4, 0|A(COND_CTI), { (1<<MACH_M32R), PIPE_NONE, WRITE_LR_NO, WRITE_SRC_NO } }
1398 /* bltz $src2,$disp16 */
1401 "bltz", "bltz", SYN (14), FMT (13), 0xb0a00000,
1402 & fmt_13_beqz_ops[0],
1403 { 4, 0|A(COND_CTI), { (1<<MACH_M32R), PIPE_NONE, WRITE_LR_NO, WRITE_SRC_NO } }
1405 /* bnez $src2,$disp16 */
1408 "bnez", "bnez", SYN (14), FMT (13), 0xb0900000,
1409 & fmt_13_beqz_ops[0],
1410 { 4, 0|A(COND_CTI), { (1<<MACH_M32R), PIPE_NONE, WRITE_LR_NO, WRITE_SRC_NO } }
1415 "bl8", "bl", SYN (11), FMT (14), 0x7e00,
1416 & fmt_14_bl8_ops[0],
1417 { 4, 0|A(FILL_SLOT)|A(RELAXABLE)|A(UNCOND_CTI), { (1<<MACH_M32R), PIPE_O, WRITE_LR_YES, WRITE_SRC_NO } }
1422 "bl8.s", "bl.s", SYN (11), FMT (9), 0x7e00,
1424 { 4, 0|A(FILL_SLOT)|A(ALIAS)|A(UNCOND_CTI), { (1<<MACH_M32R), PIPE_O, WRITE_LR_YES, WRITE_SRC_NO } }
1429 "bl24", "bl", SYN (12), FMT (15), 0xfe000000,
1430 & fmt_15_bl24_ops[0],
1431 { 4, 0|A(RELAX)|A(UNCOND_CTI), { (1<<MACH_M32R), PIPE_NONE, WRITE_LR_YES, WRITE_SRC_NO } }
1436 "bl24.l", "bl.l", SYN (12), FMT (11), 0xfe000000,
1438 { 4, 0|A(ALIAS)|A(UNCOND_CTI), { (1<<MACH_M32R), PIPE_NONE, WRITE_LR_YES, WRITE_SRC_NO } }
1440 /* start-sanitize-m32rx */
1444 "bcl8", "bcl", SYN (11), FMT (16), 0x7800,
1445 & fmt_16_bcl8_ops[0],
1446 { 4, 0|A(RELAXABLE)|A(COND_CTI), { (1<<MACH_M32RX), PIPE_O, WRITE_LR_YES, WRITE_SRC_NO } }
1448 /* end-sanitize-m32rx */
1449 /* start-sanitize-m32rx */
1453 "bcl8.s", "bcl.s", SYN (11), FMT (9), 0x7800,
1455 { 4, 0|A(ALIAS)|A(COND_CTI), { (1<<MACH_M32RX), PIPE_O, WRITE_LR_YES, WRITE_SRC_NO } }
1457 /* end-sanitize-m32rx */
1458 /* start-sanitize-m32rx */
1462 "bcl24", "bcl", SYN (12), FMT (17), 0xf8000000,
1463 & fmt_17_bcl24_ops[0],
1464 { 4, 0|A(RELAX)|A(COND_CTI), { (1<<MACH_M32RX), PIPE_NONE, WRITE_LR_YES, WRITE_SRC_NO } }
1466 /* end-sanitize-m32rx */
1467 /* start-sanitize-m32rx */
1471 "bcl24.l", "bcl.l", SYN (12), FMT (11), 0xf8000000,
1473 { 4, 0|A(ALIAS)|A(COND_CTI), { (1<<MACH_M32RX), PIPE_NONE, WRITE_LR_YES, WRITE_SRC_NO } }
1475 /* end-sanitize-m32rx */
1479 "bnc8", "bnc", SYN (11), FMT (8), 0x7d00,
1481 { 4, 0|A(RELAXABLE)|A(COND_CTI), { (1<<MACH_M32R), PIPE_O, WRITE_LR_NO, WRITE_SRC_NO } }
1486 "bnc8.s", "bnc.s", SYN (11), FMT (9), 0x7d00,
1488 { 4, 0|A(ALIAS)|A(COND_CTI), { (1<<MACH_M32R), PIPE_O, WRITE_LR_NO, WRITE_SRC_NO } }
1493 "bnc24", "bnc", SYN (12), FMT (10), 0xfd000000,
1494 & fmt_10_bc24_ops[0],
1495 { 4, 0|A(RELAX)|A(COND_CTI), { (1<<MACH_M32R), PIPE_NONE, WRITE_LR_NO, WRITE_SRC_NO } }
1500 "bnc24.l", "bnc.l", SYN (12), FMT (11), 0xfd000000,
1502 { 4, 0|A(ALIAS)|A(COND_CTI), { (1<<MACH_M32R), PIPE_NONE, WRITE_LR_NO, WRITE_SRC_NO } }
1504 /* bne $src1,$src2,$disp16 */
1507 "bne", "bne", SYN (13), FMT (12), 0xb0100000,
1508 & fmt_12_beq_ops[0],
1509 { 4, 0|A(COND_CTI), { (1<<MACH_M32R), PIPE_NONE, WRITE_LR_NO, WRITE_SRC_NO } }
1514 "bra8", "bra", SYN (11), FMT (18), 0x7f00,
1515 & fmt_18_bra8_ops[0],
1516 { 4, 0|A(FILL_SLOT)|A(RELAXABLE)|A(UNCOND_CTI), { (1<<MACH_M32R), PIPE_O, WRITE_LR_NO, WRITE_SRC_NO } }
1521 "bra8.s", "bra.s", SYN (11), FMT (9), 0x7f00,
1523 { 4, 0|A(ALIAS)|A(UNCOND_CTI), { (1<<MACH_M32R), PIPE_O, WRITE_LR_NO, WRITE_SRC_NO } }
1528 "bra24", "bra", SYN (12), FMT (19), 0xff000000,
1529 & fmt_19_bra24_ops[0],
1530 { 4, 0|A(RELAX)|A(UNCOND_CTI), { (1<<MACH_M32R), PIPE_NONE, WRITE_LR_NO, WRITE_SRC_NO } }
1535 "bra24.l", "bra.l", SYN (12), FMT (11), 0xff000000,
1537 { 4, 0|A(ALIAS)|A(UNCOND_CTI), { (1<<MACH_M32R), PIPE_NONE, WRITE_LR_NO, WRITE_SRC_NO } }
1539 /* start-sanitize-m32rx */
1543 "bncl8", "bncl", SYN (11), FMT (16), 0x7900,
1544 & fmt_16_bcl8_ops[0],
1545 { 4, 0|A(RELAXABLE)|A(COND_CTI), { (1<<MACH_M32RX), PIPE_O, WRITE_LR_YES, WRITE_SRC_NO } }
1547 /* end-sanitize-m32rx */
1548 /* start-sanitize-m32rx */
1552 "bncl8.s", "bncl.s", SYN (11), FMT (9), 0x7900,
1554 { 4, 0|A(ALIAS)|A(COND_CTI), { (1<<MACH_M32RX), PIPE_O, WRITE_LR_YES, WRITE_SRC_NO } }
1556 /* end-sanitize-m32rx */
1557 /* start-sanitize-m32rx */
1561 "bncl24", "bncl", SYN (12), FMT (17), 0xf9000000,
1562 & fmt_17_bcl24_ops[0],
1563 { 4, 0|A(RELAX)|A(COND_CTI), { (1<<MACH_M32RX), PIPE_NONE, WRITE_LR_YES, WRITE_SRC_NO } }
1565 /* end-sanitize-m32rx */
1566 /* start-sanitize-m32rx */
1567 /* bncl.l $disp24 */
1570 "bncl24.l", "bncl.l", SYN (12), FMT (11), 0xf9000000,
1572 { 4, 0|A(ALIAS)|A(COND_CTI), { (1<<MACH_M32RX), PIPE_NONE, WRITE_LR_YES, WRITE_SRC_NO } }
1574 /* end-sanitize-m32rx */
1575 /* cmp $src1,$src2 */
1578 "cmp", "cmp", SYN (15), FMT (20), 0x40,
1579 & fmt_20_cmp_ops[0],
1580 { 4, 0, { (1<<MACH_M32R), PIPE_OS, WRITE_LR_NO, WRITE_SRC_NO } }
1582 /* cmpi $src2,#$simm16 */
1585 "cmpi", "cmpi", SYN (16), FMT (21), 0x80400000,
1586 & fmt_21_cmpi_ops[0],
1587 { 4, 0, { (1<<MACH_M32R), PIPE_NONE, WRITE_LR_NO, WRITE_SRC_NO } }
1589 /* cmpi $src2,$simm16 */
1592 "cmpi.a", "cmpi", SYN (17), FMT (21), 0x80400000,
1593 & fmt_21_cmpi_ops[0],
1594 { 4, 0|A(ALIAS), { (1<<MACH_M32R), PIPE_NONE, WRITE_LR_NO, WRITE_SRC_NO } }
1596 /* cmpu $src1,$src2 */
1599 "cmpu", "cmpu", SYN (15), FMT (20), 0x50,
1600 & fmt_20_cmp_ops[0],
1601 { 4, 0, { (1<<MACH_M32R), PIPE_OS, WRITE_LR_NO, WRITE_SRC_NO } }
1603 /* cmpui $src2,#$uimm16 */
1606 "cmpui", "cmpui", SYN (18), FMT (22), 0x80500000,
1607 & fmt_22_cmpui_ops[0],
1608 { 4, 0, { (1<<MACH_M32R), PIPE_NONE, WRITE_LR_NO, WRITE_SRC_NO } }
1610 /* cmpui $src2,$uimm16 */
1613 "cmpui.a", "cmpui", SYN (19), FMT (22), 0x80500000,
1614 & fmt_22_cmpui_ops[0],
1615 { 4, 0|A(ALIAS), { (1<<MACH_M32R), PIPE_NONE, WRITE_LR_NO, WRITE_SRC_NO } }
1617 /* start-sanitize-m32rx */
1618 /* cmpeq $src1,$src2 */
1621 "cmpeq", "cmpeq", SYN (15), FMT (20), 0x60,
1622 & fmt_20_cmp_ops[0],
1623 { 4, 0, { (1<<MACH_M32RX), PIPE_OS, WRITE_LR_NO, WRITE_SRC_NO } }
1625 /* end-sanitize-m32rx */
1626 /* start-sanitize-m32rx */
1630 "cmpz", "cmpz", SYN (20), FMT (23), 0x70,
1631 & fmt_23_cmpz_ops[0],
1632 { 4, 0, { (1<<MACH_M32RX), PIPE_OS, WRITE_LR_NO, WRITE_SRC_NO } }
1634 /* end-sanitize-m32rx */
1638 "div", "div", SYN (0), FMT (24), 0x90000000,
1639 & fmt_24_div_ops[0],
1640 { 4, 0, { (1<<MACH_M32R), PIPE_NONE, WRITE_LR_NO, WRITE_SRC_NO } }
1645 "divu", "divu", SYN (0), FMT (24), 0x90100000,
1646 & fmt_24_div_ops[0],
1647 { 4, 0, { (1<<MACH_M32R), PIPE_NONE, WRITE_LR_NO, WRITE_SRC_NO } }
1652 "rem", "rem", SYN (0), FMT (24), 0x90200000,
1653 & fmt_24_div_ops[0],
1654 { 4, 0, { (1<<MACH_M32R), PIPE_NONE, WRITE_LR_NO, WRITE_SRC_NO } }
1659 "remu", "remu", SYN (0), FMT (24), 0x90300000,
1660 & fmt_24_div_ops[0],
1661 { 4, 0, { (1<<MACH_M32R), PIPE_NONE, WRITE_LR_NO, WRITE_SRC_NO } }
1663 /* start-sanitize-m32rx */
1667 "divh", "divh", SYN (0), FMT (24), 0x90000010,
1668 & fmt_24_div_ops[0],
1669 { 4, 0, { (1<<MACH_M32R), PIPE_NONE, WRITE_LR_NO, WRITE_SRC_NO } }
1671 /* end-sanitize-m32rx */
1672 /* start-sanitize-m32rx */
1676 "jc", "jc", SYN (21), FMT (25), 0x1cc0,
1678 { 4, 0|A(COND_CTI), { (1<<MACH_M32RX), PIPE_O, WRITE_LR_NO, WRITE_SRC_NO } }
1680 /* end-sanitize-m32rx */
1681 /* start-sanitize-m32rx */
1685 "jnc", "jnc", SYN (21), FMT (25), 0x1dc0,
1687 { 4, 0|A(COND_CTI), { (1<<MACH_M32RX), PIPE_O, WRITE_LR_NO, WRITE_SRC_NO } }
1689 /* end-sanitize-m32rx */
1693 "jl", "jl", SYN (21), FMT (26), 0x1ec0,
1695 { 4, 0|A(FILL_SLOT)|A(UNCOND_CTI), { (1<<MACH_M32R), PIPE_O, WRITE_LR_YES, WRITE_SRC_NO } }
1700 "jmp", "jmp", SYN (21), FMT (27), 0x1fc0,
1701 & fmt_27_jmp_ops[0],
1702 { 4, 0|A(UNCOND_CTI), { (1<<MACH_M32R), PIPE_O, WRITE_LR_NO, WRITE_SRC_NO } }
1707 "ld", "ld", SYN (22), FMT (28), 0x20c0,
1709 { 4, 0, { (1<<MACH_M32R), PIPE_O, WRITE_LR_NO, WRITE_SRC_NO } }
1714 "ld-2", "ld", SYN (23), FMT (29), 0x20c0,
1716 { 4, 0|A(ALIAS), { (1<<MACH_M32R), PIPE_O, WRITE_LR_NO, WRITE_SRC_NO } }
1718 /* ld $dr,@($slo16,$sr) */
1721 "ld-d", "ld", SYN (24), FMT (30), 0xa0c00000,
1722 & fmt_30_ld_d_ops[0],
1723 { 4, 0, { (1<<MACH_M32R), PIPE_NONE, WRITE_LR_NO, WRITE_SRC_NO } }
1725 /* ld $dr,@($sr,$slo16) */
1728 "ld-d2", "ld", SYN (25), FMT (31), 0xa0c00000,
1730 { 4, 0|A(ALIAS), { (1<<MACH_M32R), PIPE_NONE, WRITE_LR_NO, WRITE_SRC_NO } }
1735 "ldb", "ldb", SYN (22), FMT (32), 0x2080,
1736 & fmt_32_ldb_ops[0],
1737 { 4, 0, { (1<<MACH_M32R), PIPE_O, WRITE_LR_NO, WRITE_SRC_NO } }
1739 /* ldb $dr,@($sr) */
1742 "ldb-2", "ldb", SYN (23), FMT (29), 0x2080,
1744 { 4, 0|A(ALIAS), { (1<<MACH_M32R), PIPE_O, WRITE_LR_NO, WRITE_SRC_NO } }
1746 /* ldb $dr,@($slo16,$sr) */
1749 "ldb-d", "ldb", SYN (24), FMT (33), 0xa0800000,
1750 & fmt_33_ldb_d_ops[0],
1751 { 4, 0, { (1<<MACH_M32R), PIPE_NONE, WRITE_LR_NO, WRITE_SRC_NO } }
1753 /* ldb $dr,@($sr,$slo16) */
1756 "ldb-d2", "ldb", SYN (25), FMT (31), 0xa0800000,
1758 { 4, 0|A(ALIAS), { (1<<MACH_M32R), PIPE_NONE, WRITE_LR_NO, WRITE_SRC_NO } }
1763 "ldh", "ldh", SYN (22), FMT (34), 0x20a0,
1764 & fmt_34_ldh_ops[0],
1765 { 4, 0, { (1<<MACH_M32R), PIPE_O, WRITE_LR_NO, WRITE_SRC_NO } }
1767 /* ldh $dr,@($sr) */
1770 "ldh-2", "ldh", SYN (23), FMT (29), 0x20a0,
1772 { 4, 0|A(ALIAS), { (1<<MACH_M32R), PIPE_O, WRITE_LR_NO, WRITE_SRC_NO } }
1774 /* ldh $dr,@($slo16,$sr) */
1777 "ldh-d", "ldh", SYN (24), FMT (35), 0xa0a00000,
1778 & fmt_35_ldh_d_ops[0],
1779 { 4, 0, { (1<<MACH_M32R), PIPE_NONE, WRITE_LR_NO, WRITE_SRC_NO } }
1781 /* ldh $dr,@($sr,$slo16) */
1784 "ldh-d2", "ldh", SYN (25), FMT (31), 0xa0a00000,
1786 { 4, 0|A(ALIAS), { (1<<MACH_M32R), PIPE_NONE, WRITE_LR_NO, WRITE_SRC_NO } }
1791 "ldub", "ldub", SYN (22), FMT (32), 0x2090,
1792 & fmt_32_ldb_ops[0],
1793 { 4, 0, { (1<<MACH_M32R), PIPE_O, WRITE_LR_NO, WRITE_SRC_NO } }
1795 /* ldub $dr,@($sr) */
1798 "ldub-2", "ldub", SYN (23), FMT (29), 0x2090,
1800 { 4, 0|A(ALIAS), { (1<<MACH_M32R), PIPE_O, WRITE_LR_NO, WRITE_SRC_NO } }
1802 /* ldub $dr,@($slo16,$sr) */
1805 "ldub-d", "ldub", SYN (24), FMT (33), 0xa0900000,
1806 & fmt_33_ldb_d_ops[0],
1807 { 4, 0, { (1<<MACH_M32R), PIPE_NONE, WRITE_LR_NO, WRITE_SRC_NO } }
1809 /* ldub $dr,@($sr,$slo16) */
1812 "ldub-d2", "ldub", SYN (25), FMT (31), 0xa0900000,
1814 { 4, 0|A(ALIAS), { (1<<MACH_M32R), PIPE_NONE, WRITE_LR_NO, WRITE_SRC_NO } }
1819 "lduh", "lduh", SYN (22), FMT (34), 0x20b0,
1820 & fmt_34_ldh_ops[0],
1821 { 4, 0, { (1<<MACH_M32R), PIPE_O, WRITE_LR_NO, WRITE_SRC_NO } }
1823 /* lduh $dr,@($sr) */
1826 "lduh-2", "lduh", SYN (23), FMT (29), 0x20b0,
1828 { 4, 0|A(ALIAS), { (1<<MACH_M32R), PIPE_O, WRITE_LR_NO, WRITE_SRC_NO } }
1830 /* lduh $dr,@($slo16,$sr) */
1833 "lduh-d", "lduh", SYN (24), FMT (35), 0xa0b00000,
1834 & fmt_35_ldh_d_ops[0],
1835 { 4, 0, { (1<<MACH_M32R), PIPE_NONE, WRITE_LR_NO, WRITE_SRC_NO } }
1837 /* lduh $dr,@($sr,$slo16) */
1840 "lduh-d2", "lduh", SYN (25), FMT (31), 0xa0b00000,
1842 { 4, 0|A(ALIAS), { (1<<MACH_M32R), PIPE_NONE, WRITE_LR_NO, WRITE_SRC_NO } }
1847 "ld-plus", "ld", SYN (26), FMT (36), 0x20e0,
1848 & fmt_36_ld_plus_ops[0],
1849 { 4, 0, { (1<<MACH_M32R), PIPE_O, WRITE_LR_NO, WRITE_SRC_YES } }
1851 /* ld24 $dr,#$uimm24 */
1854 "ld24", "ld24", SYN (27), FMT (37), 0xe0000000,
1855 & fmt_37_ld24_ops[0],
1856 { 4, 0, { (1<<MACH_M32R), PIPE_NONE, WRITE_LR_NO, WRITE_SRC_NO } }
1858 /* ld24 $dr,$uimm24 */
1861 "ld24.a", "ld24", SYN (28), FMT (37), 0xe0000000,
1862 & fmt_37_ld24_ops[0],
1863 { 4, 0|A(ALIAS), { (1<<MACH_M32R), PIPE_NONE, WRITE_LR_NO, WRITE_SRC_NO } }
1865 /* ldi $dr,#$simm8 */
1868 "ldi8", "ldi", SYN (7), FMT (38), 0x6000,
1869 & fmt_38_ldi8_ops[0],
1870 { 4, 0, { (1<<MACH_M32R), PIPE_OS, WRITE_LR_NO, WRITE_SRC_NO } }
1872 /* ldi $dr,$simm8 */
1875 "ldi8.a", "ldi", SYN (8), FMT (38), 0x6000,
1876 & fmt_38_ldi8_ops[0],
1877 { 4, 0|A(ALIAS), { (1<<MACH_M32R), PIPE_OS, WRITE_LR_NO, WRITE_SRC_NO } }
1879 /* ldi8 $dr,#$simm8 */
1882 "ldi8a", "ldi8", SYN (7), FMT (38), 0x6000,
1883 & fmt_38_ldi8_ops[0],
1884 { 4, 0|A(ALIAS), { (1<<MACH_M32R), PIPE_OS, WRITE_LR_NO, WRITE_SRC_NO } }
1886 /* ldi8 $dr,$simm8 */
1889 "ldi8a.a", "ldi8", SYN (8), FMT (38), 0x6000,
1890 & fmt_38_ldi8_ops[0],
1891 { 4, 0|A(ALIAS), { (1<<MACH_M32R), PIPE_OS, WRITE_LR_NO, WRITE_SRC_NO } }
1893 /* ldi $dr,$slo16 */
1896 "ldi16", "ldi", SYN (29), FMT (39), 0x90f00000,
1897 & fmt_39_ldi16_ops[0],
1898 { 4, 0, { (1<<MACH_M32R), PIPE_NONE, WRITE_LR_NO, WRITE_SRC_NO } }
1900 /* ldi16 $dr,$slo16 */
1903 "ldi16a", "ldi16", SYN (29), FMT (39), 0x90f00000,
1904 & fmt_39_ldi16_ops[0],
1905 { 4, 0|A(ALIAS), { (1<<MACH_M32R), PIPE_NONE, WRITE_LR_NO, WRITE_SRC_NO } }
1910 "lock", "lock", SYN (22), FMT (40), 0x20d0,
1911 & fmt_40_lock_ops[0],
1912 { 4, 0, { (1<<MACH_M32R), PIPE_O, WRITE_LR_NO, WRITE_SRC_NO } }
1914 /* machi $src1,$src2 */
1917 "machi", "machi", SYN (15), FMT (41), 0x3040,
1918 & fmt_41_machi_ops[0],
1919 { 4, 0, { (1<<MACH_M32R), PIPE_S, WRITE_LR_NO, WRITE_SRC_NO } }
1921 /* start-sanitize-m32rx */
1922 /* machi $src1,$src2,$acc */
1925 "machi-a", "machi", SYN (30), FMT (42), 0x3040,
1926 & fmt_42_machi_a_ops[0],
1927 { 4, 0, { (1<<MACH_M32RX), PIPE_S, WRITE_LR_NO, WRITE_SRC_NO } }
1929 /* end-sanitize-m32rx */
1930 /* maclo $src1,$src2 */
1933 "maclo", "maclo", SYN (15), FMT (41), 0x3050,
1934 & fmt_41_machi_ops[0],
1935 { 4, 0, { (1<<MACH_M32R), PIPE_S, WRITE_LR_NO, WRITE_SRC_NO } }
1937 /* start-sanitize-m32rx */
1938 /* maclo $src1,$src2,$acc */
1941 "maclo-a", "maclo", SYN (30), FMT (42), 0x3050,
1942 & fmt_42_machi_a_ops[0],
1943 { 4, 0, { (1<<MACH_M32RX), PIPE_S, WRITE_LR_NO, WRITE_SRC_NO } }
1945 /* end-sanitize-m32rx */
1946 /* macwhi $src1,$src2 */
1949 "macwhi", "macwhi", SYN (15), FMT (41), 0x3060,
1950 & fmt_41_machi_ops[0],
1951 { 4, 0, { (1<<MACH_M32R), PIPE_S, WRITE_LR_NO, WRITE_SRC_NO } }
1953 /* macwlo $src1,$src2 */
1956 "macwlo", "macwlo", SYN (15), FMT (41), 0x3070,
1957 & fmt_41_machi_ops[0],
1958 { 4, 0, { (1<<MACH_M32R), PIPE_S, WRITE_LR_NO, WRITE_SRC_NO } }
1963 "mul", "mul", SYN (0), FMT (0), 0x1060,
1965 { 4, 0, { (1<<MACH_M32R), PIPE_S, WRITE_LR_NO, WRITE_SRC_NO } }
1967 /* mulhi $src1,$src2 */
1970 "mulhi", "mulhi", SYN (15), FMT (43), 0x3000,
1971 & fmt_43_mulhi_ops[0],
1972 { 4, 0, { (1<<MACH_M32R), PIPE_S, WRITE_LR_NO, WRITE_SRC_NO } }
1974 /* start-sanitize-m32rx */
1975 /* mulhi $src1,$src2,$acc */
1978 "mulhi-a", "mulhi", SYN (30), FMT (44), 0x3000,
1979 & fmt_44_mulhi_a_ops[0],
1980 { 4, 0, { (1<<MACH_M32RX), PIPE_S, WRITE_LR_NO, WRITE_SRC_NO } }
1982 /* end-sanitize-m32rx */
1983 /* mullo $src1,$src2 */
1986 "mullo", "mullo", SYN (15), FMT (43), 0x3010,
1987 & fmt_43_mulhi_ops[0],
1988 { 4, 0, { (1<<MACH_M32R), PIPE_S, WRITE_LR_NO, WRITE_SRC_NO } }
1990 /* start-sanitize-m32rx */
1991 /* mullo $src1,$src2,$acc */
1994 "mullo-a", "mullo", SYN (30), FMT (44), 0x3010,
1995 & fmt_44_mulhi_a_ops[0],
1996 { 4, 0, { (1<<MACH_M32RX), PIPE_S, WRITE_LR_NO, WRITE_SRC_NO } }
1998 /* end-sanitize-m32rx */
1999 /* mulwhi $src1,$src2 */
2002 "mulwhi", "mulwhi", SYN (15), FMT (43), 0x3020,
2003 & fmt_43_mulhi_ops[0],
2004 { 4, 0, { (1<<MACH_M32R), PIPE_S, WRITE_LR_NO, WRITE_SRC_NO } }
2006 /* mulwlo $src1,$src2 */
2009 "mulwlo", "mulwlo", SYN (15), FMT (43), 0x3030,
2010 & fmt_43_mulhi_ops[0],
2011 { 4, 0, { (1<<MACH_M32R), PIPE_S, WRITE_LR_NO, WRITE_SRC_NO } }
2016 "mv", "mv", SYN (0), FMT (45), 0x1080,
2018 { 4, 0, { (1<<MACH_M32R), PIPE_OS, WRITE_LR_NO, WRITE_SRC_NO } }
2023 "mvfachi", "mvfachi", SYN (31), FMT (46), 0x50f0,
2024 & fmt_46_mvfachi_ops[0],
2025 { 4, 0, { (1<<MACH_M32R), PIPE_S, WRITE_LR_NO, WRITE_SRC_NO } }
2027 /* start-sanitize-m32rx */
2028 /* mvfachi $dr,$accs */
2031 "mvfachi-a", "mvfachi", SYN (32), FMT (47), 0x50f0,
2032 & fmt_47_mvfachi_a_ops[0],
2033 { 4, 0, { (1<<MACH_M32RX), PIPE_S, WRITE_LR_NO, WRITE_SRC_NO } }
2035 /* end-sanitize-m32rx */
2039 "mvfaclo", "mvfaclo", SYN (31), FMT (46), 0x50f1,
2040 & fmt_46_mvfachi_ops[0],
2041 { 4, 0, { (1<<MACH_M32R), PIPE_S, WRITE_LR_NO, WRITE_SRC_NO } }
2043 /* start-sanitize-m32rx */
2044 /* mvfaclo $dr,$accs */
2047 "mvfaclo-a", "mvfaclo", SYN (32), FMT (47), 0x50f1,
2048 & fmt_47_mvfachi_a_ops[0],
2049 { 4, 0, { (1<<MACH_M32RX), PIPE_S, WRITE_LR_NO, WRITE_SRC_NO } }
2051 /* end-sanitize-m32rx */
2055 "mvfacmi", "mvfacmi", SYN (31), FMT (46), 0x50f2,
2056 & fmt_46_mvfachi_ops[0],
2057 { 4, 0, { (1<<MACH_M32R), PIPE_S, WRITE_LR_NO, WRITE_SRC_NO } }
2059 /* start-sanitize-m32rx */
2060 /* mvfacmi $dr,$accs */
2063 "mvfacmi-a", "mvfacmi", SYN (32), FMT (47), 0x50f2,
2064 & fmt_47_mvfachi_a_ops[0],
2065 { 4, 0, { (1<<MACH_M32RX), PIPE_S, WRITE_LR_NO, WRITE_SRC_NO } }
2067 /* end-sanitize-m32rx */
2071 "mvfc", "mvfc", SYN (33), FMT (48), 0x1090,
2072 & fmt_48_mvfc_ops[0],
2073 { 4, 0, { (1<<MACH_M32R), PIPE_O, WRITE_LR_NO, WRITE_SRC_NO } }
2078 "mvtachi", "mvtachi", SYN (34), FMT (49), 0x5070,
2079 & fmt_49_mvtachi_ops[0],
2080 { 4, 0, { (1<<MACH_M32R), PIPE_S, WRITE_LR_NO, WRITE_SRC_NO } }
2082 /* start-sanitize-m32rx */
2083 /* mvtachi $src1,$accs */
2086 "mvtachi-a", "mvtachi", SYN (35), FMT (50), 0x5070,
2087 & fmt_50_mvtachi_a_ops[0],
2088 { 4, 0, { (1<<MACH_M32RX), PIPE_S, WRITE_LR_NO, WRITE_SRC_NO } }
2090 /* end-sanitize-m32rx */
2094 "mvtaclo", "mvtaclo", SYN (34), FMT (49), 0x5071,
2095 & fmt_49_mvtachi_ops[0],
2096 { 4, 0, { (1<<MACH_M32R), PIPE_S, WRITE_LR_NO, WRITE_SRC_NO } }
2098 /* start-sanitize-m32rx */
2099 /* mvtaclo $src1,$accs */
2102 "mvtaclo-a", "mvtaclo", SYN (35), FMT (50), 0x5071,
2103 & fmt_50_mvtachi_a_ops[0],
2104 { 4, 0, { (1<<MACH_M32RX), PIPE_S, WRITE_LR_NO, WRITE_SRC_NO } }
2106 /* end-sanitize-m32rx */
2110 "mvtc", "mvtc", SYN (36), FMT (51), 0x10a0,
2111 & fmt_51_mvtc_ops[0],
2112 { 4, 0, { (1<<MACH_M32R), PIPE_O, WRITE_LR_NO, WRITE_SRC_NO } }
2117 "neg", "neg", SYN (0), FMT (45), 0x30,
2119 { 4, 0, { (1<<MACH_M32R), PIPE_OS, WRITE_LR_NO, WRITE_SRC_NO } }
2124 "nop", "nop", SYN (37), FMT (52), 0x7000,
2126 { 4, 0, { (1<<MACH_M32R), PIPE_OS, WRITE_LR_NO, WRITE_SRC_NO } }
2131 "not", "not", SYN (0), FMT (45), 0xb0,
2133 { 4, 0, { (1<<MACH_M32R), PIPE_OS, WRITE_LR_NO, WRITE_SRC_NO } }
2138 "rac", "rac", SYN (37), FMT (53), 0x5090,
2139 & fmt_53_rac_ops[0],
2140 { 4, 0, { (1<<MACH_M32R), PIPE_S, WRITE_LR_NO, WRITE_SRC_NO } }
2142 /* start-sanitize-m32rx */
2146 "rac-d", "rac", SYN (38), FMT (54), 0x5090,
2147 & fmt_54_rac_d_ops[0],
2148 { 4, 0, { (1<<MACH_M32RX), PIPE_S, WRITE_LR_NO, WRITE_SRC_NO } }
2150 /* end-sanitize-m32rx */
2151 /* start-sanitize-m32rx */
2152 /* rac $accd,$accs */
2155 "rac-ds", "rac", SYN (39), FMT (55), 0x5090,
2156 & fmt_55_rac_ds_ops[0],
2157 { 4, 0, { (1<<MACH_M32RX), PIPE_S, WRITE_LR_NO, WRITE_SRC_NO } }
2159 /* end-sanitize-m32rx */
2160 /* start-sanitize-m32rx */
2161 /* rac $accd,$accs,#$imm1 */
2164 "rac-dsi", "rac", SYN (40), FMT (56), 0x5090,
2165 & fmt_56_rac_dsi_ops[0],
2166 { 4, 0, { (1<<MACH_M32RX), PIPE_S, WRITE_LR_NO, WRITE_SRC_NO } }
2168 /* end-sanitize-m32rx */
2172 "rach", "rach", SYN (37), FMT (53), 0x5080,
2173 & fmt_53_rac_ops[0],
2174 { 4, 0, { (1<<MACH_M32R), PIPE_S, WRITE_LR_NO, WRITE_SRC_NO } }
2176 /* start-sanitize-m32rx */
2180 "rach-d", "rach", SYN (38), FMT (54), 0x5080,
2181 & fmt_54_rac_d_ops[0],
2182 { 4, 0, { (1<<MACH_M32RX), PIPE_S, WRITE_LR_NO, WRITE_SRC_NO } }
2184 /* end-sanitize-m32rx */
2185 /* start-sanitize-m32rx */
2186 /* rach $accd,$accs */
2189 "rach-ds", "rach", SYN (39), FMT (55), 0x5080,
2190 & fmt_55_rac_ds_ops[0],
2191 { 4, 0, { (1<<MACH_M32RX), PIPE_S, WRITE_LR_NO, WRITE_SRC_NO } }
2193 /* end-sanitize-m32rx */
2194 /* start-sanitize-m32rx */
2195 /* rach $accd,$accs,#$imm1 */
2198 "rach-dsi", "rach", SYN (40), FMT (56), 0x5080,
2199 & fmt_56_rac_dsi_ops[0],
2200 { 4, 0, { (1<<MACH_M32RX), PIPE_S, WRITE_LR_NO, WRITE_SRC_NO } }
2202 /* end-sanitize-m32rx */
2206 "rte", "rte", SYN (37), FMT (57), 0x10d6,
2207 & fmt_57_rte_ops[0],
2208 { 4, 0|A(UNCOND_CTI), { (1<<MACH_M32R), PIPE_O, WRITE_LR_NO, WRITE_SRC_NO } }
2210 /* seth $dr,#$hi16 */
2213 "seth", "seth", SYN (41), FMT (58), 0xd0c00000,
2214 & fmt_58_seth_ops[0],
2215 { 4, 0, { (1<<MACH_M32R), PIPE_NONE, WRITE_LR_NO, WRITE_SRC_NO } }
2217 /* seth $dr,$hi16 */
2220 "seth.a", "seth", SYN (42), FMT (58), 0xd0c00000,
2221 & fmt_58_seth_ops[0],
2222 { 4, 0|A(ALIAS), { (1<<MACH_M32R), PIPE_NONE, WRITE_LR_NO, WRITE_SRC_NO } }
2227 "sll", "sll", SYN (0), FMT (0), 0x1040,
2229 { 4, 0, { (1<<MACH_M32R), PIPE_O, WRITE_LR_NO, WRITE_SRC_NO } }
2231 /* sll3 $dr,$sr,#$simm16 */
2234 "sll3", "sll3", SYN (9), FMT (59), 0x90c00000,
2235 & fmt_59_sll3_ops[0],
2236 { 4, 0, { (1<<MACH_M32R), PIPE_NONE, WRITE_LR_NO, WRITE_SRC_NO } }
2238 /* sll3 $dr,$sr,$simm16 */
2241 "sll3.a", "sll3", SYN (10), FMT (59), 0x90c00000,
2242 & fmt_59_sll3_ops[0],
2243 { 4, 0|A(ALIAS), { (1<<MACH_M32R), PIPE_NONE, WRITE_LR_NO, WRITE_SRC_NO } }
2245 /* slli $dr,#$uimm5 */
2248 "slli", "slli", SYN (43), FMT (60), 0x5040,
2249 & fmt_60_slli_ops[0],
2250 { 4, 0, { (1<<MACH_M32R), PIPE_O, WRITE_LR_NO, WRITE_SRC_NO } }
2252 /* slli $dr,$uimm5 */
2255 "slli.a", "slli", SYN (44), FMT (60), 0x5040,
2256 & fmt_60_slli_ops[0],
2257 { 4, 0|A(ALIAS), { (1<<MACH_M32R), PIPE_O, WRITE_LR_NO, WRITE_SRC_NO } }
2262 "sra", "sra", SYN (0), FMT (0), 0x1020,
2264 { 4, 0, { (1<<MACH_M32R), PIPE_O, WRITE_LR_NO, WRITE_SRC_NO } }
2266 /* sra3 $dr,$sr,#$simm16 */
2269 "sra3", "sra3", SYN (9), FMT (59), 0x90a00000,
2270 & fmt_59_sll3_ops[0],
2271 { 4, 0, { (1<<MACH_M32R), PIPE_NONE, WRITE_LR_NO, WRITE_SRC_NO } }
2273 /* sra3 $dr,$sr,$simm16 */
2276 "sra3.a", "sra3", SYN (10), FMT (59), 0x90a00000,
2277 & fmt_59_sll3_ops[0],
2278 { 4, 0|A(ALIAS), { (1<<MACH_M32R), PIPE_NONE, WRITE_LR_NO, WRITE_SRC_NO } }
2280 /* srai $dr,#$uimm5 */
2283 "srai", "srai", SYN (43), FMT (60), 0x5020,
2284 & fmt_60_slli_ops[0],
2285 { 4, 0, { (1<<MACH_M32R), PIPE_O, WRITE_LR_NO, WRITE_SRC_NO } }
2287 /* srai $dr,$uimm5 */
2290 "srai.a", "srai", SYN (44), FMT (60), 0x5020,
2291 & fmt_60_slli_ops[0],
2292 { 4, 0|A(ALIAS), { (1<<MACH_M32R), PIPE_O, WRITE_LR_NO, WRITE_SRC_NO } }
2297 "srl", "srl", SYN (0), FMT (0), 0x1000,
2299 { 4, 0, { (1<<MACH_M32R), PIPE_O, WRITE_LR_NO, WRITE_SRC_NO } }
2301 /* srl3 $dr,$sr,#$simm16 */
2304 "srl3", "srl3", SYN (9), FMT (59), 0x90800000,
2305 & fmt_59_sll3_ops[0],
2306 { 4, 0, { (1<<MACH_M32R), PIPE_NONE, WRITE_LR_NO, WRITE_SRC_NO } }
2308 /* srl3 $dr,$sr,$simm16 */
2311 "srl3.a", "srl3", SYN (10), FMT (59), 0x90800000,
2312 & fmt_59_sll3_ops[0],
2313 { 4, 0|A(ALIAS), { (1<<MACH_M32R), PIPE_NONE, WRITE_LR_NO, WRITE_SRC_NO } }
2315 /* srli $dr,#$uimm5 */
2318 "srli", "srli", SYN (43), FMT (60), 0x5000,
2319 & fmt_60_slli_ops[0],
2320 { 4, 0, { (1<<MACH_M32R), PIPE_O, WRITE_LR_NO, WRITE_SRC_NO } }
2322 /* srli $dr,$uimm5 */
2325 "srli.a", "srli", SYN (44), FMT (60), 0x5000,
2326 & fmt_60_slli_ops[0],
2327 { 4, 0|A(ALIAS), { (1<<MACH_M32R), PIPE_O, WRITE_LR_NO, WRITE_SRC_NO } }
2329 /* st $src1,@$src2 */
2332 "st", "st", SYN (45), FMT (61), 0x2040,
2334 { 4, 0, { (1<<MACH_M32R), PIPE_O, WRITE_LR_NO, WRITE_SRC_NO } }
2336 /* st $src1,@($src2) */
2339 "st-2", "st", SYN (46), FMT (62), 0x2040,
2341 { 4, 0|A(ALIAS), { (1<<MACH_M32R), PIPE_O, WRITE_LR_NO, WRITE_SRC_NO } }
2343 /* st $src1,@($slo16,$src2) */
2346 "st-d", "st", SYN (47), FMT (63), 0xa0400000,
2347 & fmt_63_st_d_ops[0],
2348 { 4, 0, { (1<<MACH_M32R), PIPE_NONE, WRITE_LR_NO, WRITE_SRC_NO } }
2350 /* st $src1,@($src2,$slo16) */
2353 "st-d2", "st", SYN (48), FMT (64), 0xa0400000,
2355 { 4, 0|A(ALIAS), { (1<<MACH_M32R), PIPE_NONE, WRITE_LR_NO, WRITE_SRC_NO } }
2357 /* stb $src1,@$src2 */
2360 "stb", "stb", SYN (45), FMT (65), 0x2000,
2361 & fmt_65_stb_ops[0],
2362 { 4, 0, { (1<<MACH_M32R), PIPE_O, WRITE_LR_NO, WRITE_SRC_NO } }
2364 /* stb $src1,@($src2) */
2367 "stb-2", "stb", SYN (46), FMT (62), 0x2000,
2369 { 4, 0|A(ALIAS), { (1<<MACH_M32R), PIPE_O, WRITE_LR_NO, WRITE_SRC_NO } }
2371 /* stb $src1,@($slo16,$src2) */
2374 "stb-d", "stb", SYN (47), FMT (66), 0xa0000000,
2375 & fmt_66_stb_d_ops[0],
2376 { 4, 0, { (1<<MACH_M32R), PIPE_NONE, WRITE_LR_NO, WRITE_SRC_NO } }
2378 /* stb $src1,@($src2,$slo16) */
2381 "stb-d2", "stb", SYN (48), FMT (64), 0xa0000000,
2383 { 4, 0|A(ALIAS), { (1<<MACH_M32R), PIPE_NONE, WRITE_LR_NO, WRITE_SRC_NO } }
2385 /* sth $src1,@$src2 */
2388 "sth", "sth", SYN (45), FMT (67), 0x2020,
2389 & fmt_67_sth_ops[0],
2390 { 4, 0, { (1<<MACH_M32R), PIPE_O, WRITE_LR_NO, WRITE_SRC_NO } }
2392 /* sth $src1,@($src2) */
2395 "sth-2", "sth", SYN (46), FMT (62), 0x2020,
2397 { 4, 0|A(ALIAS), { (1<<MACH_M32R), PIPE_O, WRITE_LR_NO, WRITE_SRC_NO } }
2399 /* sth $src1,@($slo16,$src2) */
2402 "sth-d", "sth", SYN (47), FMT (68), 0xa0200000,
2403 & fmt_68_sth_d_ops[0],
2404 { 4, 0, { (1<<MACH_M32R), PIPE_NONE, WRITE_LR_NO, WRITE_SRC_NO } }
2406 /* sth $src1,@($src2,$slo16) */
2409 "sth-d2", "sth", SYN (48), FMT (64), 0xa0200000,
2411 { 4, 0|A(ALIAS), { (1<<MACH_M32R), PIPE_NONE, WRITE_LR_NO, WRITE_SRC_NO } }
2413 /* st $src1,@+$src2 */
2416 "st-plus", "st", SYN (49), FMT (69), 0x2060,
2417 & fmt_69_st_plus_ops[0],
2418 { 4, 0, { (1<<MACH_M32R), PIPE_O, WRITE_LR_NO, WRITE_SRC_YES } }
2420 /* st $src1,@-$src2 */
2423 "st-minus", "st", SYN (50), FMT (69), 0x2070,
2424 & fmt_69_st_plus_ops[0],
2425 { 4, 0, { (1<<MACH_M32R), PIPE_O, WRITE_LR_NO, WRITE_SRC_YES } }
2430 "sub", "sub", SYN (0), FMT (0), 0x20,
2432 { 4, 0, { (1<<MACH_M32R), PIPE_OS, WRITE_LR_NO, WRITE_SRC_NO } }
2437 "subv", "subv", SYN (0), FMT (5), 0x0,
2438 & fmt_5_addv_ops[0],
2439 { 4, 0, { (1<<MACH_M32R), PIPE_OS, WRITE_LR_NO, WRITE_SRC_NO } }
2444 "subx", "subx", SYN (0), FMT (7), 0x10,
2445 & fmt_7_addx_ops[0],
2446 { 4, 0, { (1<<MACH_M32R), PIPE_OS, WRITE_LR_NO, WRITE_SRC_NO } }
2451 "trap", "trap", SYN (51), FMT (70), 0x10f0,
2452 & fmt_70_trap_ops[0],
2453 { 4, 0|A(FILL_SLOT)|A(UNCOND_CTI), { (1<<MACH_M32R), PIPE_O, WRITE_LR_NO, WRITE_SRC_NO } }
2458 "trap.a", "trap", SYN (52), FMT (70), 0x10f0,
2459 & fmt_70_trap_ops[0],
2460 { 4, 0|A(ALIAS)|A(FILL_SLOT)|A(UNCOND_CTI), { (1<<MACH_M32R), PIPE_O, WRITE_LR_NO, WRITE_SRC_NO } }
2462 /* unlock $src1,@$src2 */
2465 "unlock", "unlock", SYN (45), FMT (71), 0x2050,
2466 & fmt_71_unlock_ops[0],
2467 { 4, 0, { (1<<MACH_M32R), PIPE_O, WRITE_LR_NO, WRITE_SRC_NO } }
2472 "push", "push", SYN (34), FMT (72), 0x207f,
2474 { 4, 0|A(ALIAS), { (1<<MACH_M32R), PIPE_NONE, WRITE_LR_NO, WRITE_SRC_NO } }
2479 "pop", "pop", SYN (31), FMT (73), 0x20ef,
2481 { 4, 0|A(ALIAS), { (1<<MACH_M32R), PIPE_NONE, WRITE_LR_NO, WRITE_SRC_NO } }
2483 /* start-sanitize-m32rx */
2484 /* satb $dr,$src2 */
2487 "satb", "satb", SYN (53), FMT (74), 0x80000100,
2488 & fmt_74_satb_ops[0],
2489 { 4, 0, { (1<<MACH_M32RX), PIPE_NONE, WRITE_LR_NO, WRITE_SRC_NO } }
2491 /* end-sanitize-m32rx */
2492 /* start-sanitize-m32rx */
2493 /* sath $dr,$src2 */
2496 "sath", "sath", SYN (53), FMT (74), 0x80000200,
2497 & fmt_74_satb_ops[0],
2498 { 4, 0, { (1<<MACH_M32RX), PIPE_NONE, WRITE_LR_NO, WRITE_SRC_NO } }
2500 /* end-sanitize-m32rx */
2501 /* start-sanitize-m32rx */
2505 "sat", "sat", SYN (53), FMT (75), 0x80000000,
2506 & fmt_75_sat_ops[0],
2507 { 4, 0, { (1<<MACH_M32RX), PIPE_NONE, WRITE_LR_NO, WRITE_SRC_NO } }
2509 /* end-sanitize-m32rx */
2510 /* start-sanitize-m32rx */
2514 "pcmpbz", "pcmpbz", SYN (20), FMT (23), 0x370,
2515 & fmt_23_cmpz_ops[0],
2516 { 4, 0, { (1<<MACH_M32RX), PIPE_OS, WRITE_LR_NO, WRITE_SRC_NO } }
2518 /* end-sanitize-m32rx */
2519 /* start-sanitize-m32rx */
2523 "sadd", "sadd", SYN (37), FMT (76), 0x50e4,
2524 & fmt_76_sadd_ops[0],
2525 { 4, 0, { (1<<MACH_M32RX), PIPE_S, WRITE_LR_NO, WRITE_SRC_NO } }
2527 /* end-sanitize-m32rx */
2528 /* start-sanitize-m32rx */
2529 /* macwu1 $src1,$src2 */
2532 "macwu1", "macwu1", SYN (15), FMT (77), 0x50b0,
2533 & fmt_77_macwu1_ops[0],
2534 { 4, 0, { (1<<MACH_M32RX), PIPE_S, WRITE_LR_NO, WRITE_SRC_NO } }
2536 /* end-sanitize-m32rx */
2537 /* start-sanitize-m32rx */
2538 /* msblo $src1,$src2 */
2541 "msblo", "msblo", SYN (15), FMT (41), 0x50d0,
2542 & fmt_41_machi_ops[0],
2543 { 4, 0, { (1<<MACH_M32RX), PIPE_S, WRITE_LR_NO, WRITE_SRC_NO } }
2545 /* end-sanitize-m32rx */
2546 /* start-sanitize-m32rx */
2547 /* mulwu1 $src1,$src2 */
2550 "mulwu1", "mulwu1", SYN (15), FMT (78), 0x50a0,
2551 & fmt_78_mulwu1_ops[0],
2552 { 4, 0, { (1<<MACH_M32RX), PIPE_S, WRITE_LR_NO, WRITE_SRC_NO } }
2554 /* end-sanitize-m32rx */
2555 /* start-sanitize-m32rx */
2556 /* maclh1 $src1,$src2 */
2559 "maclh1", "maclh1", SYN (15), FMT (77), 0x50c0,
2560 & fmt_77_macwu1_ops[0],
2561 { 4, 0, { (1<<MACH_M32RX), PIPE_S, WRITE_LR_NO, WRITE_SRC_NO } }
2563 /* end-sanitize-m32rx */
2564 /* start-sanitize-m32rx */
2568 "sc", "sc", SYN (37), FMT (79), 0x7401,
2570 { 4, 0, { (1<<MACH_M32RX), PIPE_O, WRITE_LR_NO, WRITE_SRC_NO } }
2572 /* end-sanitize-m32rx */
2573 /* start-sanitize-m32rx */
2577 "snc", "snc", SYN (37), FMT (79), 0x7501,
2579 { 4, 0, { (1<<MACH_M32RX), PIPE_O, WRITE_LR_NO, WRITE_SRC_NO } }
2581 /* end-sanitize-m32rx */
2588 CGEN_INSN_TABLE m32r_cgen_insn_table =
2590 & m32r_cgen_insn_table_entries[0],
2594 m32r_cgen_asm_hash_insn, CGEN_ASM_HASH_SIZE,
2595 m32r_cgen_dis_hash_insn, CGEN_DIS_HASH_SIZE
2598 /* The hash functions are recorded here to help keep assembler code out of
2599 the disassembler and vice versa. */
2602 m32r_cgen_asm_hash_insn (insn)
2605 return CGEN_ASM_HASH (insn);
2609 m32r_cgen_dis_hash_insn (buf, value)
2611 unsigned long value;
2613 return CGEN_DIS_HASH (buf, value);
2616 CGEN_OPCODE_DATA m32r_cgen_opcode_data =
2618 & m32r_cgen_hw_entries[0],
2619 & m32r_cgen_insn_table,
2623 m32r_cgen_init_tables (mach)
2628 /* Main entry point for stuffing values in cgen_fields. */
2631 m32r_cgen_set_operand (opindex, valuep, fields)
2633 const long * valuep;
2634 CGEN_FIELDS * fields;
2638 case M32R_OPERAND_SR :
2639 fields->f_r2 = * valuep;
2641 case M32R_OPERAND_DR :
2642 fields->f_r1 = * valuep;
2644 case M32R_OPERAND_SRC1 :
2645 fields->f_r1 = * valuep;
2647 case M32R_OPERAND_SRC2 :
2648 fields->f_r2 = * valuep;
2650 case M32R_OPERAND_SCR :
2651 fields->f_r2 = * valuep;
2653 case M32R_OPERAND_DCR :
2654 fields->f_r1 = * valuep;
2656 case M32R_OPERAND_SIMM8 :
2657 fields->f_simm8 = * valuep;
2659 case M32R_OPERAND_SIMM16 :
2660 fields->f_simm16 = * valuep;
2662 case M32R_OPERAND_UIMM4 :
2663 fields->f_uimm4 = * valuep;
2665 case M32R_OPERAND_UIMM5 :
2666 fields->f_uimm5 = * valuep;
2668 case M32R_OPERAND_UIMM16 :
2669 fields->f_uimm16 = * valuep;
2671 /* start-sanitize-m32rx */
2672 case M32R_OPERAND_IMM1 :
2673 fields->f_imm1 = * valuep;
2675 /* end-sanitize-m32rx */
2676 /* start-sanitize-m32rx */
2677 case M32R_OPERAND_ACCD :
2678 fields->f_accd = * valuep;
2680 /* end-sanitize-m32rx */
2681 /* start-sanitize-m32rx */
2682 case M32R_OPERAND_ACCS :
2683 fields->f_accs = * valuep;
2685 /* end-sanitize-m32rx */
2686 /* start-sanitize-m32rx */
2687 case M32R_OPERAND_ACC :
2688 fields->f_acc = * valuep;
2690 /* end-sanitize-m32rx */
2691 case M32R_OPERAND_HI16 :
2692 fields->f_hi16 = * valuep;
2694 case M32R_OPERAND_SLO16 :
2695 fields->f_simm16 = * valuep;
2697 case M32R_OPERAND_ULO16 :
2698 fields->f_uimm16 = * valuep;
2700 case M32R_OPERAND_UIMM24 :
2701 fields->f_uimm24 = * valuep;
2703 case M32R_OPERAND_DISP8 :
2704 fields->f_disp8 = * valuep;
2706 case M32R_OPERAND_DISP16 :
2707 fields->f_disp16 = * valuep;
2709 case M32R_OPERAND_DISP24 :
2710 fields->f_disp24 = * valuep;
2714 fprintf (stderr, "Unrecognized field %d while setting operand.\n",
2720 /* Main entry point for getting values from cgen_fields. */
2723 m32r_cgen_get_operand (opindex, fields)
2725 const CGEN_FIELDS * fields;
2731 case M32R_OPERAND_SR :
2732 value = fields->f_r2;
2734 case M32R_OPERAND_DR :
2735 value = fields->f_r1;
2737 case M32R_OPERAND_SRC1 :
2738 value = fields->f_r1;
2740 case M32R_OPERAND_SRC2 :
2741 value = fields->f_r2;
2743 case M32R_OPERAND_SCR :
2744 value = fields->f_r2;
2746 case M32R_OPERAND_DCR :
2747 value = fields->f_r1;
2749 case M32R_OPERAND_SIMM8 :
2750 value = fields->f_simm8;
2752 case M32R_OPERAND_SIMM16 :
2753 value = fields->f_simm16;
2755 case M32R_OPERAND_UIMM4 :
2756 value = fields->f_uimm4;
2758 case M32R_OPERAND_UIMM5 :
2759 value = fields->f_uimm5;
2761 case M32R_OPERAND_UIMM16 :
2762 value = fields->f_uimm16;
2764 /* start-sanitize-m32rx */
2765 case M32R_OPERAND_IMM1 :
2766 value = fields->f_imm1;
2768 /* end-sanitize-m32rx */
2769 /* start-sanitize-m32rx */
2770 case M32R_OPERAND_ACCD :
2771 value = fields->f_accd;
2773 /* end-sanitize-m32rx */
2774 /* start-sanitize-m32rx */
2775 case M32R_OPERAND_ACCS :
2776 value = fields->f_accs;
2778 /* end-sanitize-m32rx */
2779 /* start-sanitize-m32rx */
2780 case M32R_OPERAND_ACC :
2781 value = fields->f_acc;
2783 /* end-sanitize-m32rx */
2784 case M32R_OPERAND_HI16 :
2785 value = fields->f_hi16;
2787 case M32R_OPERAND_SLO16 :
2788 value = fields->f_simm16;
2790 case M32R_OPERAND_ULO16 :
2791 value = fields->f_uimm16;
2793 case M32R_OPERAND_UIMM24 :
2794 value = fields->f_uimm24;
2796 case M32R_OPERAND_DISP8 :
2797 value = fields->f_disp8;
2799 case M32R_OPERAND_DISP16 :
2800 value = fields->f_disp16;
2802 case M32R_OPERAND_DISP24 :
2803 value = fields->f_disp24;
2807 fprintf (stderr, "Unrecognized field %d while getting operand.\n",