1 /* Instruction building/extraction support for m32r. -*- C -*-
3 THIS FILE IS MACHINE GENERATED WITH CGEN: Cpu tools GENerator.
4 - the resultant file is machine generated, cgen-ibld.in isn't
6 Copyright 1996, 1997, 1998, 1999, 2000, 2001 Free Software Foundation, Inc.
8 This file is part of the GNU Binutils and GDB, the GNU debugger.
10 This program is free software; you can redistribute it and/or modify
11 it under the terms of the GNU General Public License as published by
12 the Free Software Foundation; either version 2, or (at your option)
15 This program is distributed in the hope that it will be useful,
16 but WITHOUT ANY WARRANTY; without even the implied warranty of
17 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 GNU General Public License for more details.
20 You should have received a copy of the GNU General Public License
21 along with this program; if not, write to the Free Software Foundation, Inc.,
22 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */
24 /* ??? Eventually more and more of this stuff can go to cpu-independent files.
33 #include "m32r-desc.h"
38 #define min(a,b) ((a) < (b) ? (a) : (b))
40 #define max(a,b) ((a) > (b) ? (a) : (b))
42 /* Used by the ifield rtx function. */
43 #define FLD(f) (fields->f)
45 static const char * insert_normal
46 PARAMS ((CGEN_CPU_DESC, long, unsigned int, unsigned int, unsigned int,
47 unsigned int, unsigned int, unsigned int, CGEN_INSN_BYTES_PTR));
48 static const char * insert_insn_normal
49 PARAMS ((CGEN_CPU_DESC, const CGEN_INSN *,
50 CGEN_FIELDS *, CGEN_INSN_BYTES_PTR, bfd_vma));
52 static int extract_normal
53 PARAMS ((CGEN_CPU_DESC, CGEN_EXTRACT_INFO *, CGEN_INSN_INT,
54 unsigned int, unsigned int, unsigned int, unsigned int,
55 unsigned int, unsigned int, bfd_vma, long *));
56 static int extract_insn_normal
57 PARAMS ((CGEN_CPU_DESC, const CGEN_INSN *, CGEN_EXTRACT_INFO *,
58 CGEN_INSN_INT, CGEN_FIELDS *, bfd_vma));
59 static void put_insn_int_value
60 PARAMS ((CGEN_CPU_DESC, CGEN_INSN_BYTES_PTR, int, int, CGEN_INSN_INT));
63 /* Operand insertion. */
67 /* Subroutine of insert_normal. */
69 static CGEN_INLINE void
70 insert_1 (cd, value, start, length, word_length, bufp)
73 int start,length,word_length;
78 int big_p = CGEN_CPU_INSN_ENDIAN (cd) == CGEN_ENDIAN_BIG;
80 x = bfd_get_bits (bufp, word_length, big_p);
82 /* Written this way to avoid undefined behaviour. */
83 mask = (((1L << (length - 1)) - 1) << 1) | 1;
85 shift = (start + 1) - length;
87 shift = (word_length - (start + length));
88 x = (x & ~(mask << shift)) | ((value & mask) << shift);
90 bfd_put_bits ((bfd_vma) x, bufp, word_length, big_p);
93 #endif /* ! CGEN_INT_INSN_P */
95 /* Default insertion routine.
97 ATTRS is a mask of the boolean attributes.
98 WORD_OFFSET is the offset in bits from the start of the insn of the value.
99 WORD_LENGTH is the length of the word in bits in which the value resides.
100 START is the starting bit number in the word, architecture origin.
101 LENGTH is the length of VALUE in bits.
102 TOTAL_LENGTH is the total length of the insn in bits.
104 The result is an error message or NULL if success. */
106 /* ??? This duplicates functionality with bfd's howto table and
107 bfd_install_relocation. */
108 /* ??? This doesn't handle bfd_vma's. Create another function when
112 insert_normal (cd, value, attrs, word_offset, start, length, word_length,
113 total_length, buffer)
117 unsigned int word_offset, start, length, word_length, total_length;
118 CGEN_INSN_BYTES_PTR buffer;
120 static char errbuf[100];
121 /* Written this way to avoid undefined behaviour. */
122 unsigned long mask = (((1L << (length - 1)) - 1) << 1) | 1;
124 /* If LENGTH is zero, this operand doesn't contribute to the value. */
134 if (word_length > 32)
137 /* For architectures with insns smaller than the base-insn-bitsize,
138 word_length may be too big. */
139 if (cd->min_insn_bitsize < cd->base_insn_bitsize)
142 && word_length > total_length)
143 word_length = total_length;
146 /* Ensure VALUE will fit. */
147 if (CGEN_BOOL_ATTR (attrs, CGEN_IFLD_SIGN_OPT))
149 long minval = - (1L << (length - 1));
150 unsigned long maxval = mask;
152 if ((value > 0 && (unsigned long) value > maxval)
155 /* xgettext:c-format */
157 _("operand out of range (%ld not between %ld and %lu)"),
158 value, minval, maxval);
162 else if (! CGEN_BOOL_ATTR (attrs, CGEN_IFLD_SIGNED))
164 unsigned long maxval = mask;
166 if ((unsigned long) value > maxval)
168 /* xgettext:c-format */
170 _("operand out of range (%lu not between 0 and %lu)"),
177 if (! cgen_signed_overflow_ok_p (cd))
179 long minval = - (1L << (length - 1));
180 long maxval = (1L << (length - 1)) - 1;
182 if (value < minval || value > maxval)
185 /* xgettext:c-format */
186 (errbuf, _("operand out of range (%ld not between %ld and %ld)"),
187 value, minval, maxval);
198 if (CGEN_INSN_LSB0_P)
199 shift = (word_offset + start + 1) - length;
201 shift = total_length - (word_offset + start + length);
202 *buffer = (*buffer & ~(mask << shift)) | ((value & mask) << shift);
205 #else /* ! CGEN_INT_INSN_P */
208 unsigned char *bufp = (unsigned char *) buffer + word_offset / 8;
210 insert_1 (cd, value, start, length, word_length, bufp);
213 #endif /* ! CGEN_INT_INSN_P */
218 /* Default insn builder (insert handler).
219 The instruction is recorded in CGEN_INT_INSN_P byte order (meaning
220 that if CGEN_INSN_BYTES_PTR is an int * and thus, the value is
221 recorded in host byte order, otherwise BUFFER is an array of bytes
222 and the value is recorded in target byte order).
223 The result is an error message or NULL if success. */
226 insert_insn_normal (cd, insn, fields, buffer, pc)
228 const CGEN_INSN * insn;
229 CGEN_FIELDS * fields;
230 CGEN_INSN_BYTES_PTR buffer;
233 const CGEN_SYNTAX *syntax = CGEN_INSN_SYNTAX (insn);
235 const CGEN_SYNTAX_CHAR_TYPE * syn;
237 CGEN_INIT_INSERT (cd);
238 value = CGEN_INSN_BASE_VALUE (insn);
240 /* If we're recording insns as numbers (rather than a string of bytes),
241 target byte order handling is deferred until later. */
245 put_insn_int_value (cd, buffer, cd->base_insn_bitsize,
246 CGEN_FIELDS_BITSIZE (fields), value);
250 cgen_put_insn_value (cd, buffer, min (cd->base_insn_bitsize,
251 CGEN_FIELDS_BITSIZE (fields)),
254 #endif /* ! CGEN_INT_INSN_P */
256 /* ??? It would be better to scan the format's fields.
257 Still need to be able to insert a value based on the operand though;
258 e.g. storing a branch displacement that got resolved later.
259 Needs more thought first. */
261 for (syn = CGEN_SYNTAX_STRING (syntax); * syn; ++ syn)
265 if (CGEN_SYNTAX_CHAR_P (* syn))
268 errmsg = (* cd->insert_operand) (cd, CGEN_SYNTAX_FIELD (*syn),
277 /* Cover function to store an insn value into an integral insn. Must go here
278 because it needs <prefix>-desc.h for CGEN_INT_INSN_P. */
281 put_insn_int_value (cd, buf, length, insn_length, value)
282 CGEN_CPU_DESC cd ATTRIBUTE_UNUSED;
283 CGEN_INSN_BYTES_PTR buf;
288 /* For architectures with insns smaller than the base-insn-bitsize,
289 length may be too big. */
290 if (length > insn_length)
294 int shift = insn_length - length;
295 /* Written this way to avoid undefined behaviour. */
296 CGEN_INSN_INT mask = (((1L << (length - 1)) - 1) << 1) | 1;
297 *buf = (*buf & ~(mask << shift)) | ((value & mask) << shift);
301 /* Operand extraction. */
303 #if ! CGEN_INT_INSN_P
305 /* Subroutine of extract_normal.
306 Ensure sufficient bytes are cached in EX_INFO.
307 OFFSET is the offset in bytes from the start of the insn of the value.
308 BYTES is the length of the needed value.
309 Returns 1 for success, 0 for failure. */
311 static CGEN_INLINE int
312 fill_cache (cd, ex_info, offset, bytes, pc)
314 CGEN_EXTRACT_INFO *ex_info;
318 /* It's doubtful that the middle part has already been fetched so
319 we don't optimize that case. kiss. */
321 disassemble_info *info = (disassemble_info *) ex_info->dis_info;
323 /* First do a quick check. */
324 mask = (1 << bytes) - 1;
325 if (((ex_info->valid >> offset) & mask) == mask)
328 /* Search for the first byte we need to read. */
329 for (mask = 1 << offset; bytes > 0; --bytes, ++offset, mask <<= 1)
330 if (! (mask & ex_info->valid))
338 status = (*info->read_memory_func)
339 (pc, ex_info->insn_bytes + offset, bytes, info);
343 (*info->memory_error_func) (status, pc, info);
347 ex_info->valid |= ((1 << bytes) - 1) << offset;
353 /* Subroutine of extract_normal. */
355 static CGEN_INLINE long
356 extract_1 (cd, ex_info, start, length, word_length, bufp, pc)
358 CGEN_EXTRACT_INFO *ex_info;
359 int start,length,word_length;
365 int big_p = CGEN_CPU_INSN_ENDIAN (cd) == CGEN_ENDIAN_BIG;
367 x = bfd_get_bits (bufp, word_length, big_p);
369 if (CGEN_INSN_LSB0_P)
370 shift = (start + 1) - length;
372 shift = (word_length - (start + length));
376 #endif /* ! CGEN_INT_INSN_P */
378 /* Default extraction routine.
380 INSN_VALUE is the first base_insn_bitsize bits of the insn in host order,
381 or sometimes less for cases like the m32r where the base insn size is 32
382 but some insns are 16 bits.
383 ATTRS is a mask of the boolean attributes. We only need `SIGNED',
384 but for generality we take a bitmask of all of them.
385 WORD_OFFSET is the offset in bits from the start of the insn of the value.
386 WORD_LENGTH is the length of the word in bits in which the value resides.
387 START is the starting bit number in the word, architecture origin.
388 LENGTH is the length of VALUE in bits.
389 TOTAL_LENGTH is the total length of the insn in bits.
391 Returns 1 for success, 0 for failure. */
393 /* ??? The return code isn't properly used. wip. */
395 /* ??? This doesn't handle bfd_vma's. Create another function when
399 extract_normal (cd, ex_info, insn_value, attrs, word_offset, start, length,
400 word_length, total_length, pc, valuep)
402 #if ! CGEN_INT_INSN_P
403 CGEN_EXTRACT_INFO *ex_info;
405 CGEN_EXTRACT_INFO *ex_info ATTRIBUTE_UNUSED;
407 CGEN_INSN_INT insn_value;
409 unsigned int word_offset, start, length, word_length, total_length;
410 #if ! CGEN_INT_INSN_P
413 bfd_vma pc ATTRIBUTE_UNUSED;
419 /* If LENGTH is zero, this operand doesn't contribute to the value
420 so give it a standard value of zero. */
433 if (word_length > 32)
436 /* For architectures with insns smaller than the insn-base-bitsize,
437 word_length may be too big. */
438 if (cd->min_insn_bitsize < cd->base_insn_bitsize)
441 && word_length > total_length)
442 word_length = total_length;
445 /* Does the value reside in INSN_VALUE, and at the right alignment? */
447 if (CGEN_INT_INSN_P || (word_offset == 0 && word_length == total_length))
449 if (CGEN_INSN_LSB0_P)
450 value = insn_value >> ((word_offset + start + 1) - length);
452 value = insn_value >> (total_length - ( word_offset + start + length));
455 #if ! CGEN_INT_INSN_P
459 unsigned char *bufp = ex_info->insn_bytes + word_offset / 8;
461 if (word_length > 32)
464 if (fill_cache (cd, ex_info, word_offset / 8, word_length / 8, pc) == 0)
467 value = extract_1 (cd, ex_info, start, length, word_length, bufp, pc);
470 #endif /* ! CGEN_INT_INSN_P */
472 /* Written this way to avoid undefined behaviour. */
473 mask = (((1L << (length - 1)) - 1) << 1) | 1;
477 if (CGEN_BOOL_ATTR (attrs, CGEN_IFLD_SIGNED)
478 && (value & (1L << (length - 1))))
486 /* Default insn extractor.
488 INSN_VALUE is the first base_insn_bitsize bits, translated to host order.
489 The extracted fields are stored in FIELDS.
490 EX_INFO is used to handle reading variable length insns.
491 Return the length of the insn in bits, or 0 if no match,
492 or -1 if an error occurs fetching data (memory_error_func will have
496 extract_insn_normal (cd, insn, ex_info, insn_value, fields, pc)
498 const CGEN_INSN *insn;
499 CGEN_EXTRACT_INFO *ex_info;
500 CGEN_INSN_INT insn_value;
504 const CGEN_SYNTAX *syntax = CGEN_INSN_SYNTAX (insn);
505 const CGEN_SYNTAX_CHAR_TYPE *syn;
507 CGEN_FIELDS_BITSIZE (fields) = CGEN_INSN_BITSIZE (insn);
509 CGEN_INIT_EXTRACT (cd);
511 for (syn = CGEN_SYNTAX_STRING (syntax); *syn; ++syn)
515 if (CGEN_SYNTAX_CHAR_P (*syn))
518 length = (* cd->extract_operand) (cd, CGEN_SYNTAX_FIELD (*syn),
519 ex_info, insn_value, fields, pc);
524 /* We recognized and successfully extracted this insn. */
525 return CGEN_INSN_BITSIZE (insn);
528 /* machine generated code added here */
530 /* Main entry point for operand insertion.
532 This function is basically just a big switch statement. Earlier versions
533 used tables to look up the function to use, but
534 - if the table contains both assembler and disassembler functions then
535 the disassembler contains much of the assembler and vice-versa,
536 - there's a lot of inlining possibilities as things grow,
537 - using a switch statement avoids the function call overhead.
539 This function could be moved into `parse_insn_normal', but keeping it
540 separate makes clear the interface between `parse_insn_normal' and each of
541 the handlers. It's also needed by GAS to insert operands that couldn't be
542 resolved during parsing.
546 m32r_cgen_insert_operand (cd, opindex, fields, buffer, pc)
549 CGEN_FIELDS * fields;
550 CGEN_INSN_BYTES_PTR buffer;
553 const char * errmsg = NULL;
554 unsigned int total_length = CGEN_FIELDS_BITSIZE (fields);
558 case M32R_OPERAND_ACC :
559 errmsg = insert_normal (cd, fields->f_acc, 0, 0, 8, 1, 32, total_length, buffer);
561 case M32R_OPERAND_ACCD :
562 errmsg = insert_normal (cd, fields->f_accd, 0, 0, 4, 2, 32, total_length, buffer);
564 case M32R_OPERAND_ACCS :
565 errmsg = insert_normal (cd, fields->f_accs, 0, 0, 12, 2, 32, total_length, buffer);
567 case M32R_OPERAND_DCR :
568 errmsg = insert_normal (cd, fields->f_r1, 0, 0, 4, 4, 32, total_length, buffer);
570 case M32R_OPERAND_DISP16 :
572 long value = fields->f_disp16;
573 value = ((int) (((value) - (pc))) >> (2));
574 errmsg = insert_normal (cd, value, 0|(1<<CGEN_IFLD_SIGNED)|(1<<CGEN_IFLD_RELOC)|(1<<CGEN_IFLD_PCREL_ADDR), 0, 16, 16, 32, total_length, buffer);
577 case M32R_OPERAND_DISP24 :
579 long value = fields->f_disp24;
580 value = ((int) (((value) - (pc))) >> (2));
581 errmsg = insert_normal (cd, value, 0|(1<<CGEN_IFLD_SIGNED)|(1<<CGEN_IFLD_RELOC)|(1<<CGEN_IFLD_PCREL_ADDR), 0, 8, 24, 32, total_length, buffer);
584 case M32R_OPERAND_DISP8 :
586 long value = fields->f_disp8;
587 value = ((int) (((value) - (((pc) & (-4))))) >> (2));
588 errmsg = insert_normal (cd, value, 0|(1<<CGEN_IFLD_SIGNED)|(1<<CGEN_IFLD_RELOC)|(1<<CGEN_IFLD_PCREL_ADDR), 0, 8, 8, 32, total_length, buffer);
591 case M32R_OPERAND_DR :
592 errmsg = insert_normal (cd, fields->f_r1, 0, 0, 4, 4, 32, total_length, buffer);
594 case M32R_OPERAND_HASH :
596 case M32R_OPERAND_HI16 :
597 errmsg = insert_normal (cd, fields->f_hi16, 0|(1<<CGEN_IFLD_SIGN_OPT), 0, 16, 16, 32, total_length, buffer);
599 case M32R_OPERAND_IMM1 :
601 long value = fields->f_imm1;
602 value = ((value) - (1));
603 errmsg = insert_normal (cd, value, 0, 0, 15, 1, 32, total_length, buffer);
606 case M32R_OPERAND_SCR :
607 errmsg = insert_normal (cd, fields->f_r2, 0, 0, 12, 4, 32, total_length, buffer);
609 case M32R_OPERAND_SIMM16 :
610 errmsg = insert_normal (cd, fields->f_simm16, 0|(1<<CGEN_IFLD_SIGNED), 0, 16, 16, 32, total_length, buffer);
612 case M32R_OPERAND_SIMM8 :
613 errmsg = insert_normal (cd, fields->f_simm8, 0|(1<<CGEN_IFLD_SIGNED), 0, 8, 8, 32, total_length, buffer);
615 case M32R_OPERAND_SLO16 :
616 errmsg = insert_normal (cd, fields->f_simm16, 0|(1<<CGEN_IFLD_SIGNED), 0, 16, 16, 32, total_length, buffer);
618 case M32R_OPERAND_SR :
619 errmsg = insert_normal (cd, fields->f_r2, 0, 0, 12, 4, 32, total_length, buffer);
621 case M32R_OPERAND_SRC1 :
622 errmsg = insert_normal (cd, fields->f_r1, 0, 0, 4, 4, 32, total_length, buffer);
624 case M32R_OPERAND_SRC2 :
625 errmsg = insert_normal (cd, fields->f_r2, 0, 0, 12, 4, 32, total_length, buffer);
627 case M32R_OPERAND_UIMM16 :
628 errmsg = insert_normal (cd, fields->f_uimm16, 0, 0, 16, 16, 32, total_length, buffer);
630 case M32R_OPERAND_UIMM24 :
631 errmsg = insert_normal (cd, fields->f_uimm24, 0|(1<<CGEN_IFLD_RELOC)|(1<<CGEN_IFLD_ABS_ADDR), 0, 8, 24, 32, total_length, buffer);
633 case M32R_OPERAND_UIMM4 :
634 errmsg = insert_normal (cd, fields->f_uimm4, 0, 0, 12, 4, 32, total_length, buffer);
636 case M32R_OPERAND_UIMM5 :
637 errmsg = insert_normal (cd, fields->f_uimm5, 0, 0, 11, 5, 32, total_length, buffer);
639 case M32R_OPERAND_ULO16 :
640 errmsg = insert_normal (cd, fields->f_uimm16, 0, 0, 16, 16, 32, total_length, buffer);
644 /* xgettext:c-format */
645 fprintf (stderr, _("Unrecognized field %d while building insn.\n"),
653 /* Main entry point for operand extraction.
654 The result is <= 0 for error, >0 for success.
655 ??? Actual values aren't well defined right now.
657 This function is basically just a big switch statement. Earlier versions
658 used tables to look up the function to use, but
659 - if the table contains both assembler and disassembler functions then
660 the disassembler contains much of the assembler and vice-versa,
661 - there's a lot of inlining possibilities as things grow,
662 - using a switch statement avoids the function call overhead.
664 This function could be moved into `print_insn_normal', but keeping it
665 separate makes clear the interface between `print_insn_normal' and each of
670 m32r_cgen_extract_operand (cd, opindex, ex_info, insn_value, fields, pc)
673 CGEN_EXTRACT_INFO *ex_info;
674 CGEN_INSN_INT insn_value;
675 CGEN_FIELDS * fields;
678 /* Assume success (for those operands that are nops). */
680 unsigned int total_length = CGEN_FIELDS_BITSIZE (fields);
684 case M32R_OPERAND_ACC :
685 length = extract_normal (cd, ex_info, insn_value, 0, 0, 8, 1, 32, total_length, pc, & fields->f_acc);
687 case M32R_OPERAND_ACCD :
688 length = extract_normal (cd, ex_info, insn_value, 0, 0, 4, 2, 32, total_length, pc, & fields->f_accd);
690 case M32R_OPERAND_ACCS :
691 length = extract_normal (cd, ex_info, insn_value, 0, 0, 12, 2, 32, total_length, pc, & fields->f_accs);
693 case M32R_OPERAND_DCR :
694 length = extract_normal (cd, ex_info, insn_value, 0, 0, 4, 4, 32, total_length, pc, & fields->f_r1);
696 case M32R_OPERAND_DISP16 :
699 length = extract_normal (cd, ex_info, insn_value, 0|(1<<CGEN_IFLD_SIGNED)|(1<<CGEN_IFLD_RELOC)|(1<<CGEN_IFLD_PCREL_ADDR), 0, 16, 16, 32, total_length, pc, & value);
700 value = ((((value) << (2))) + (pc));
701 fields->f_disp16 = value;
704 case M32R_OPERAND_DISP24 :
707 length = extract_normal (cd, ex_info, insn_value, 0|(1<<CGEN_IFLD_SIGNED)|(1<<CGEN_IFLD_RELOC)|(1<<CGEN_IFLD_PCREL_ADDR), 0, 8, 24, 32, total_length, pc, & value);
708 value = ((((value) << (2))) + (pc));
709 fields->f_disp24 = value;
712 case M32R_OPERAND_DISP8 :
715 length = extract_normal (cd, ex_info, insn_value, 0|(1<<CGEN_IFLD_SIGNED)|(1<<CGEN_IFLD_RELOC)|(1<<CGEN_IFLD_PCREL_ADDR), 0, 8, 8, 32, total_length, pc, & value);
716 value = ((((value) << (2))) + (((pc) & (-4))));
717 fields->f_disp8 = value;
720 case M32R_OPERAND_DR :
721 length = extract_normal (cd, ex_info, insn_value, 0, 0, 4, 4, 32, total_length, pc, & fields->f_r1);
723 case M32R_OPERAND_HASH :
725 case M32R_OPERAND_HI16 :
726 length = extract_normal (cd, ex_info, insn_value, 0|(1<<CGEN_IFLD_SIGN_OPT), 0, 16, 16, 32, total_length, pc, & fields->f_hi16);
728 case M32R_OPERAND_IMM1 :
731 length = extract_normal (cd, ex_info, insn_value, 0, 0, 15, 1, 32, total_length, pc, & value);
732 value = ((value) + (1));
733 fields->f_imm1 = value;
736 case M32R_OPERAND_SCR :
737 length = extract_normal (cd, ex_info, insn_value, 0, 0, 12, 4, 32, total_length, pc, & fields->f_r2);
739 case M32R_OPERAND_SIMM16 :
740 length = extract_normal (cd, ex_info, insn_value, 0|(1<<CGEN_IFLD_SIGNED), 0, 16, 16, 32, total_length, pc, & fields->f_simm16);
742 case M32R_OPERAND_SIMM8 :
743 length = extract_normal (cd, ex_info, insn_value, 0|(1<<CGEN_IFLD_SIGNED), 0, 8, 8, 32, total_length, pc, & fields->f_simm8);
745 case M32R_OPERAND_SLO16 :
746 length = extract_normal (cd, ex_info, insn_value, 0|(1<<CGEN_IFLD_SIGNED), 0, 16, 16, 32, total_length, pc, & fields->f_simm16);
748 case M32R_OPERAND_SR :
749 length = extract_normal (cd, ex_info, insn_value, 0, 0, 12, 4, 32, total_length, pc, & fields->f_r2);
751 case M32R_OPERAND_SRC1 :
752 length = extract_normal (cd, ex_info, insn_value, 0, 0, 4, 4, 32, total_length, pc, & fields->f_r1);
754 case M32R_OPERAND_SRC2 :
755 length = extract_normal (cd, ex_info, insn_value, 0, 0, 12, 4, 32, total_length, pc, & fields->f_r2);
757 case M32R_OPERAND_UIMM16 :
758 length = extract_normal (cd, ex_info, insn_value, 0, 0, 16, 16, 32, total_length, pc, & fields->f_uimm16);
760 case M32R_OPERAND_UIMM24 :
761 length = extract_normal (cd, ex_info, insn_value, 0|(1<<CGEN_IFLD_RELOC)|(1<<CGEN_IFLD_ABS_ADDR), 0, 8, 24, 32, total_length, pc, & fields->f_uimm24);
763 case M32R_OPERAND_UIMM4 :
764 length = extract_normal (cd, ex_info, insn_value, 0, 0, 12, 4, 32, total_length, pc, & fields->f_uimm4);
766 case M32R_OPERAND_UIMM5 :
767 length = extract_normal (cd, ex_info, insn_value, 0, 0, 11, 5, 32, total_length, pc, & fields->f_uimm5);
769 case M32R_OPERAND_ULO16 :
770 length = extract_normal (cd, ex_info, insn_value, 0, 0, 16, 16, 32, total_length, pc, & fields->f_uimm16);
774 /* xgettext:c-format */
775 fprintf (stderr, _("Unrecognized field %d while decoding insn.\n"),
783 cgen_insert_fn * const m32r_cgen_insert_handlers[] =
788 cgen_extract_fn * const m32r_cgen_extract_handlers[] =
793 /* Getting values from cgen_fields is handled by a collection of functions.
794 They are distinguished by the type of the VALUE argument they return.
795 TODO: floating point, inlining support, remove cases where result type
799 m32r_cgen_get_int_operand (cd, opindex, fields)
802 const CGEN_FIELDS * fields;
808 case M32R_OPERAND_ACC :
809 value = fields->f_acc;
811 case M32R_OPERAND_ACCD :
812 value = fields->f_accd;
814 case M32R_OPERAND_ACCS :
815 value = fields->f_accs;
817 case M32R_OPERAND_DCR :
818 value = fields->f_r1;
820 case M32R_OPERAND_DISP16 :
821 value = fields->f_disp16;
823 case M32R_OPERAND_DISP24 :
824 value = fields->f_disp24;
826 case M32R_OPERAND_DISP8 :
827 value = fields->f_disp8;
829 case M32R_OPERAND_DR :
830 value = fields->f_r1;
832 case M32R_OPERAND_HASH :
835 case M32R_OPERAND_HI16 :
836 value = fields->f_hi16;
838 case M32R_OPERAND_IMM1 :
839 value = fields->f_imm1;
841 case M32R_OPERAND_SCR :
842 value = fields->f_r2;
844 case M32R_OPERAND_SIMM16 :
845 value = fields->f_simm16;
847 case M32R_OPERAND_SIMM8 :
848 value = fields->f_simm8;
850 case M32R_OPERAND_SLO16 :
851 value = fields->f_simm16;
853 case M32R_OPERAND_SR :
854 value = fields->f_r2;
856 case M32R_OPERAND_SRC1 :
857 value = fields->f_r1;
859 case M32R_OPERAND_SRC2 :
860 value = fields->f_r2;
862 case M32R_OPERAND_UIMM16 :
863 value = fields->f_uimm16;
865 case M32R_OPERAND_UIMM24 :
866 value = fields->f_uimm24;
868 case M32R_OPERAND_UIMM4 :
869 value = fields->f_uimm4;
871 case M32R_OPERAND_UIMM5 :
872 value = fields->f_uimm5;
874 case M32R_OPERAND_ULO16 :
875 value = fields->f_uimm16;
879 /* xgettext:c-format */
880 fprintf (stderr, _("Unrecognized field %d while getting int operand.\n"),
889 m32r_cgen_get_vma_operand (cd, opindex, fields)
892 const CGEN_FIELDS * fields;
898 case M32R_OPERAND_ACC :
899 value = fields->f_acc;
901 case M32R_OPERAND_ACCD :
902 value = fields->f_accd;
904 case M32R_OPERAND_ACCS :
905 value = fields->f_accs;
907 case M32R_OPERAND_DCR :
908 value = fields->f_r1;
910 case M32R_OPERAND_DISP16 :
911 value = fields->f_disp16;
913 case M32R_OPERAND_DISP24 :
914 value = fields->f_disp24;
916 case M32R_OPERAND_DISP8 :
917 value = fields->f_disp8;
919 case M32R_OPERAND_DR :
920 value = fields->f_r1;
922 case M32R_OPERAND_HASH :
925 case M32R_OPERAND_HI16 :
926 value = fields->f_hi16;
928 case M32R_OPERAND_IMM1 :
929 value = fields->f_imm1;
931 case M32R_OPERAND_SCR :
932 value = fields->f_r2;
934 case M32R_OPERAND_SIMM16 :
935 value = fields->f_simm16;
937 case M32R_OPERAND_SIMM8 :
938 value = fields->f_simm8;
940 case M32R_OPERAND_SLO16 :
941 value = fields->f_simm16;
943 case M32R_OPERAND_SR :
944 value = fields->f_r2;
946 case M32R_OPERAND_SRC1 :
947 value = fields->f_r1;
949 case M32R_OPERAND_SRC2 :
950 value = fields->f_r2;
952 case M32R_OPERAND_UIMM16 :
953 value = fields->f_uimm16;
955 case M32R_OPERAND_UIMM24 :
956 value = fields->f_uimm24;
958 case M32R_OPERAND_UIMM4 :
959 value = fields->f_uimm4;
961 case M32R_OPERAND_UIMM5 :
962 value = fields->f_uimm5;
964 case M32R_OPERAND_ULO16 :
965 value = fields->f_uimm16;
969 /* xgettext:c-format */
970 fprintf (stderr, _("Unrecognized field %d while getting vma operand.\n"),
978 /* Stuffing values in cgen_fields is handled by a collection of functions.
979 They are distinguished by the type of the VALUE argument they accept.
980 TODO: floating point, inlining support, remove cases where argument type
984 m32r_cgen_set_int_operand (cd, opindex, fields, value)
987 CGEN_FIELDS * fields;
992 case M32R_OPERAND_ACC :
993 fields->f_acc = value;
995 case M32R_OPERAND_ACCD :
996 fields->f_accd = value;
998 case M32R_OPERAND_ACCS :
999 fields->f_accs = value;
1001 case M32R_OPERAND_DCR :
1002 fields->f_r1 = value;
1004 case M32R_OPERAND_DISP16 :
1005 fields->f_disp16 = value;
1007 case M32R_OPERAND_DISP24 :
1008 fields->f_disp24 = value;
1010 case M32R_OPERAND_DISP8 :
1011 fields->f_disp8 = value;
1013 case M32R_OPERAND_DR :
1014 fields->f_r1 = value;
1016 case M32R_OPERAND_HASH :
1018 case M32R_OPERAND_HI16 :
1019 fields->f_hi16 = value;
1021 case M32R_OPERAND_IMM1 :
1022 fields->f_imm1 = value;
1024 case M32R_OPERAND_SCR :
1025 fields->f_r2 = value;
1027 case M32R_OPERAND_SIMM16 :
1028 fields->f_simm16 = value;
1030 case M32R_OPERAND_SIMM8 :
1031 fields->f_simm8 = value;
1033 case M32R_OPERAND_SLO16 :
1034 fields->f_simm16 = value;
1036 case M32R_OPERAND_SR :
1037 fields->f_r2 = value;
1039 case M32R_OPERAND_SRC1 :
1040 fields->f_r1 = value;
1042 case M32R_OPERAND_SRC2 :
1043 fields->f_r2 = value;
1045 case M32R_OPERAND_UIMM16 :
1046 fields->f_uimm16 = value;
1048 case M32R_OPERAND_UIMM24 :
1049 fields->f_uimm24 = value;
1051 case M32R_OPERAND_UIMM4 :
1052 fields->f_uimm4 = value;
1054 case M32R_OPERAND_UIMM5 :
1055 fields->f_uimm5 = value;
1057 case M32R_OPERAND_ULO16 :
1058 fields->f_uimm16 = value;
1062 /* xgettext:c-format */
1063 fprintf (stderr, _("Unrecognized field %d while setting int operand.\n"),
1070 m32r_cgen_set_vma_operand (cd, opindex, fields, value)
1073 CGEN_FIELDS * fields;
1078 case M32R_OPERAND_ACC :
1079 fields->f_acc = value;
1081 case M32R_OPERAND_ACCD :
1082 fields->f_accd = value;
1084 case M32R_OPERAND_ACCS :
1085 fields->f_accs = value;
1087 case M32R_OPERAND_DCR :
1088 fields->f_r1 = value;
1090 case M32R_OPERAND_DISP16 :
1091 fields->f_disp16 = value;
1093 case M32R_OPERAND_DISP24 :
1094 fields->f_disp24 = value;
1096 case M32R_OPERAND_DISP8 :
1097 fields->f_disp8 = value;
1099 case M32R_OPERAND_DR :
1100 fields->f_r1 = value;
1102 case M32R_OPERAND_HASH :
1104 case M32R_OPERAND_HI16 :
1105 fields->f_hi16 = value;
1107 case M32R_OPERAND_IMM1 :
1108 fields->f_imm1 = value;
1110 case M32R_OPERAND_SCR :
1111 fields->f_r2 = value;
1113 case M32R_OPERAND_SIMM16 :
1114 fields->f_simm16 = value;
1116 case M32R_OPERAND_SIMM8 :
1117 fields->f_simm8 = value;
1119 case M32R_OPERAND_SLO16 :
1120 fields->f_simm16 = value;
1122 case M32R_OPERAND_SR :
1123 fields->f_r2 = value;
1125 case M32R_OPERAND_SRC1 :
1126 fields->f_r1 = value;
1128 case M32R_OPERAND_SRC2 :
1129 fields->f_r2 = value;
1131 case M32R_OPERAND_UIMM16 :
1132 fields->f_uimm16 = value;
1134 case M32R_OPERAND_UIMM24 :
1135 fields->f_uimm24 = value;
1137 case M32R_OPERAND_UIMM4 :
1138 fields->f_uimm4 = value;
1140 case M32R_OPERAND_UIMM5 :
1141 fields->f_uimm5 = value;
1143 case M32R_OPERAND_ULO16 :
1144 fields->f_uimm16 = value;
1148 /* xgettext:c-format */
1149 fprintf (stderr, _("Unrecognized field %d while setting vma operand.\n"),
1155 /* Function to call before using the instruction builder tables. */
1158 m32r_cgen_init_ibld_table (cd)
1161 cd->insert_handlers = & m32r_cgen_insert_handlers[0];
1162 cd->extract_handlers = & m32r_cgen_extract_handlers[0];
1164 cd->insert_operand = m32r_cgen_insert_operand;
1165 cd->extract_operand = m32r_cgen_extract_operand;
1167 cd->get_int_operand = m32r_cgen_get_int_operand;
1168 cd->set_int_operand = m32r_cgen_set_int_operand;
1169 cd->get_vma_operand = m32r_cgen_get_vma_operand;
1170 cd->set_vma_operand = m32r_cgen_set_vma_operand;